1 /* yellowfin.c: A Packet Engines G-NIC ethernet driver for linux. */
3 Written 1997-2001 by Donald Becker.
5 This software may be used and distributed according to the terms of
6 the GNU General Public License (GPL), incorporated herein by reference.
7 Drivers based on or derived from this code fall under the GPL and must
8 retain the authorship, copyright and license notice. This file is not
9 a complete program and may only be used when the entire operating
10 system is licensed under the GPL.
12 This driver is for the Packet Engines G-NIC PCI Gigabit Ethernet adapter.
13 It also supports the Symbios Logic version of the same chip core.
15 The author may be reached as becker@scyld.com, or C/O
16 Scyld Computing Corporation
17 410 Severn Ave., Suite 210
20 Support and updates available at
21 http://www.scyld.com/network/yellowfin.html
22 [link no longer provides useful info -jgarzik]
26 #define DRV_NAME "yellowfin"
27 #define DRV_VERSION "2.1"
28 #define DRV_RELDATE "Sep 11, 2006"
30 #define PFX DRV_NAME ": "
32 /* The user-configurable values.
33 These may be modified when a driver module is loaded.*/
35 static int debug = 1; /* 1 normal messages, 0 quiet .. 7 verbose. */
36 /* Maximum events (Rx packets, etc.) to handle at each interrupt. */
37 static int max_interrupt_work = 20;
39 #ifdef YF_PROTOTYPE /* Support for prototype hardware errata. */
40 /* System-wide count of bogus-rx frames. */
42 static int dma_ctrl = 0x004A0263; /* Constrained by errata */
43 static int fifo_cfg = 0x0020; /* Bypass external Tx FIFO. */
44 #elif defined(YF_NEW) /* A future perfect board :->. */
45 static int dma_ctrl = 0x00CAC277; /* Override when loading module! */
46 static int fifo_cfg = 0x0028;
48 static const int dma_ctrl = 0x004A0263; /* Constrained by errata */
49 static const int fifo_cfg = 0x0020; /* Bypass external Tx FIFO. */
52 /* Set the copy breakpoint for the copy-only-tiny-frames scheme.
53 Setting to > 1514 effectively disables this feature. */
54 static int rx_copybreak;
56 /* Used to pass the media type, etc.
57 No media types are currently defined. These exist for driver
60 #define MAX_UNITS 8 /* More are supported, limit only on options */
61 static int options[MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1};
62 static int full_duplex[MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1};
64 /* Do ugly workaround for GX server chipset errata. */
67 /* Operational parameters that are set at compile time. */
69 /* Keep the ring sizes a power of two for efficiency.
70 Making the Tx ring too long decreases the effectiveness of channel
71 bonding and packet priority.
72 There are no ill effects from too-large receive rings. */
73 #define TX_RING_SIZE 16
74 #define TX_QUEUE_SIZE 12 /* Must be > 4 && <= TX_RING_SIZE */
75 #define RX_RING_SIZE 64
76 #define STATUS_TOTAL_SIZE TX_RING_SIZE*sizeof(struct tx_status_words)
77 #define TX_TOTAL_SIZE 2*TX_RING_SIZE*sizeof(struct yellowfin_desc)
78 #define RX_TOTAL_SIZE RX_RING_SIZE*sizeof(struct yellowfin_desc)
80 /* Operational parameters that usually are not changed. */
81 /* Time in jiffies before concluding the transmitter is hung. */
82 #define TX_TIMEOUT (2*HZ)
83 #define PKT_BUF_SZ 1536 /* Size of each temporary Rx buffer.*/
85 #define yellowfin_debug debug
87 #include <linux/module.h>
88 #include <linux/kernel.h>
89 #include <linux/string.h>
90 #include <linux/timer.h>
91 #include <linux/errno.h>
92 #include <linux/ioport.h>
93 #include <linux/slab.h>
94 #include <linux/interrupt.h>
95 #include <linux/pci.h>
96 #include <linux/init.h>
97 #include <linux/mii.h>
98 #include <linux/netdevice.h>
99 #include <linux/etherdevice.h>
100 #include <linux/skbuff.h>
101 #include <linux/ethtool.h>
102 #include <linux/crc32.h>
103 #include <linux/bitops.h>
104 #include <asm/uaccess.h>
105 #include <asm/processor.h> /* Processor type for cache alignment. */
106 #include <asm/unaligned.h>
109 /* These identify the driver base version and may not be removed. */
110 static char version[] __devinitdata =
111 KERN_INFO DRV_NAME ".c:v1.05 1/09/2001 Written by Donald Becker <becker@scyld.com>\n"
112 KERN_INFO " (unofficial 2.4.x port, " DRV_VERSION ", " DRV_RELDATE ")\n";
114 MODULE_AUTHOR("Donald Becker <becker@scyld.com>");
115 MODULE_DESCRIPTION("Packet Engines Yellowfin G-NIC Gigabit Ethernet driver");
116 MODULE_LICENSE("GPL");
118 module_param(max_interrupt_work, int, 0);
119 module_param(mtu, int, 0);
120 module_param(debug, int, 0);
121 module_param(rx_copybreak, int, 0);
122 module_param_array(options, int, NULL, 0);
123 module_param_array(full_duplex, int, NULL, 0);
124 module_param(gx_fix, int, 0);
125 MODULE_PARM_DESC(max_interrupt_work, "G-NIC maximum events handled per interrupt");
126 MODULE_PARM_DESC(mtu, "G-NIC MTU (all boards)");
127 MODULE_PARM_DESC(debug, "G-NIC debug level (0-7)");
128 MODULE_PARM_DESC(rx_copybreak, "G-NIC copy breakpoint for copy-only-tiny-frames");
129 MODULE_PARM_DESC(options, "G-NIC: Bits 0-3: media type, bit 17: full duplex");
130 MODULE_PARM_DESC(full_duplex, "G-NIC full duplex setting(s) (1)");
131 MODULE_PARM_DESC(gx_fix, "G-NIC: enable GX server chipset bug workaround (0-1)");
136 I. Board Compatibility
138 This device driver is designed for the Packet Engines "Yellowfin" Gigabit
139 Ethernet adapter. The G-NIC 64-bit PCI card is supported, as well as the
140 Symbios 53C885E dual function chip.
142 II. Board-specific settings
144 PCI bus devices are configured by the system at boot time, so no jumpers
145 need to be set on the board. The system BIOS preferably should assign the
146 PCI INTA signal to an otherwise unused system IRQ line.
147 Note: Kernel versions earlier than 1.3.73 do not support shared PCI
150 III. Driver operation
154 The Yellowfin uses the Descriptor Based DMA Architecture specified by Apple.
155 This is a descriptor list scheme similar to that used by the EEPro100 and
156 Tulip. This driver uses two statically allocated fixed-size descriptor lists
157 formed into rings by a branch from the final descriptor to the beginning of
158 the list. The ring sizes are set at compile time by RX/TX_RING_SIZE.
160 The driver allocates full frame size skbuffs for the Rx ring buffers at
161 open() time and passes the skb->data field to the Yellowfin as receive data
162 buffers. When an incoming frame is less than RX_COPYBREAK bytes long,
163 a fresh skbuff is allocated and the frame is copied to the new skbuff.
164 When the incoming frame is larger, the skbuff is passed directly up the
165 protocol stack and replaced by a newly allocated skbuff.
167 The RX_COPYBREAK value is chosen to trade-off the memory wasted by
168 using a full-sized skbuff for small frames vs. the copying costs of larger
169 frames. For small frames the copying cost is negligible (esp. considering
170 that we are pre-loading the cache with immediately useful header
171 information). For large frames the copying cost is non-trivial, and the
172 larger copy might flush the cache of useful data.
174 IIIC. Synchronization
176 The driver runs as two independent, single-threaded flows of control. One
177 is the send-packet routine, which enforces single-threaded use by the
178 dev->tbusy flag. The other thread is the interrupt handler, which is single
179 threaded by the hardware and other software.
181 The send packet thread has partial control over the Tx ring and 'dev->tbusy'
182 flag. It sets the tbusy flag whenever it's queuing a Tx packet. If the next
183 queue slot is empty, it clears the tbusy flag when finished otherwise it sets
184 the 'yp->tx_full' flag.
186 The interrupt handler has exclusive control over the Rx ring and records stats
187 from the Tx ring. After reaping the stats, it marks the Tx queue entry as
188 empty by incrementing the dirty_tx mark. Iff the 'yp->tx_full' flag is set, it
189 clears both the tx_full and tbusy flags.
193 Thanks to Kim Stearns of Packet Engines for providing a pair of G-NIC boards.
194 Thanks to Bruce Faust of Digitalscape for providing both their SYM53C885 board
195 and an AlphaStation to verifty the Alpha port!
199 Yellowfin Engineering Design Specification, 4/23/97 Preliminary/Confidential
200 Symbios SYM53C885 PCI-SCSI/Fast Ethernet Multifunction Controller Preliminary
202 http://cesdis.gsfc.nasa.gov/linux/misc/NWay.html
203 http://cesdis.gsfc.nasa.gov/linux/misc/100mbps.html
207 See Packet Engines confidential appendix (prototype chips only).
212 enum capability_flags {
213 HasMII=1, FullTxStatus=2, IsGigabit=4, HasMulticastBug=8, FullRxStatus=16,
214 HasMACAddrBug=32, /* Only on early revs. */
215 DontUseEeprom=64, /* Don't read the MAC from the EEPROm. */
218 /* The PCI I/O space extent. */
220 YELLOWFIN_SIZE = 0x100,
226 int pci, pci_mask, subsystem, subsystem_mask;
227 int revision, revision_mask; /* Only 8 bits. */
229 int drv_flags; /* Driver use, intended as capability flags. */
232 static const struct pci_id_info pci_id_tbl[] = {
233 {"Yellowfin G-NIC Gigabit Ethernet", { 0x07021000, 0xffffffff},
234 FullTxStatus | IsGigabit | HasMulticastBug | HasMACAddrBug | DontUseEeprom},
235 {"Symbios SYM83C885", { 0x07011000, 0xffffffff},
236 HasMII | DontUseEeprom },
240 static const struct pci_device_id yellowfin_pci_tbl[] = {
241 { 0x1000, 0x0702, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
242 { 0x1000, 0x0701, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1 },
245 MODULE_DEVICE_TABLE (pci, yellowfin_pci_tbl);
248 /* Offsets to the Yellowfin registers. Various sizes and alignments. */
249 enum yellowfin_offsets {
250 TxCtrl=0x00, TxStatus=0x04, TxPtr=0x0C,
251 TxIntrSel=0x10, TxBranchSel=0x14, TxWaitSel=0x18,
252 RxCtrl=0x40, RxStatus=0x44, RxPtr=0x4C,
253 RxIntrSel=0x50, RxBranchSel=0x54, RxWaitSel=0x58,
254 EventStatus=0x80, IntrEnb=0x82, IntrClear=0x84, IntrStatus=0x86,
255 ChipRev=0x8C, DMACtrl=0x90, TxThreshold=0x94,
256 Cnfg=0xA0, FrameGap0=0xA2, FrameGap1=0xA4,
257 MII_Cmd=0xA6, MII_Addr=0xA8, MII_Wr_Data=0xAA, MII_Rd_Data=0xAC,
259 RxDepth=0xB8, FlowCtrl=0xBC,
260 AddrMode=0xD0, StnAddr=0xD2, HashTbl=0xD8, FIFOcfg=0xF8,
261 EEStatus=0xF0, EECtrl=0xF1, EEAddr=0xF2, EERead=0xF3, EEWrite=0xF4,
265 /* The Yellowfin Rx and Tx buffer descriptors.
266 Elements are written as 32 bit for endian portability. */
267 struct yellowfin_desc {
274 struct tx_status_words {
280 #else /* Little endian chips. */
285 #endif /* __BIG_ENDIAN */
288 /* Bits in yellowfin_desc.cmd */
290 CMD_TX_PKT=0x10000000, CMD_RX_BUF=0x20000000, CMD_TXSTATUS=0x30000000,
291 CMD_NOP=0x60000000, CMD_STOP=0x70000000,
292 BRANCH_ALWAYS=0x0C0000, INTR_ALWAYS=0x300000, WAIT_ALWAYS=0x030000,
293 BRANCH_IFTRUE=0x040000,
296 /* Bits in yellowfin_desc.status */
297 enum desc_status_bits { RX_EOP=0x0040, };
299 /* Bits in the interrupt status/mask registers. */
300 enum intr_status_bits {
301 IntrRxDone=0x01, IntrRxInvalid=0x02, IntrRxPCIFault=0x04,IntrRxPCIErr=0x08,
302 IntrTxDone=0x10, IntrTxInvalid=0x20, IntrTxPCIFault=0x40,IntrTxPCIErr=0x80,
303 IntrEarlyRx=0x100, IntrWakeup=0x200, };
305 #define PRIV_ALIGN 31 /* Required alignment mask */
307 struct yellowfin_private {
308 /* Descriptor rings first for alignment.
309 Tx requires a second descriptor for status. */
310 struct yellowfin_desc *rx_ring;
311 struct yellowfin_desc *tx_ring;
312 struct sk_buff* rx_skbuff[RX_RING_SIZE];
313 struct sk_buff* tx_skbuff[TX_RING_SIZE];
314 dma_addr_t rx_ring_dma;
315 dma_addr_t tx_ring_dma;
317 struct tx_status_words *tx_status;
318 dma_addr_t tx_status_dma;
320 struct timer_list timer; /* Media selection timer. */
321 /* Frequently used and paired value: keep adjacent for cache effect. */
322 int chip_id, drv_flags;
323 struct pci_dev *pci_dev;
324 unsigned int cur_rx, dirty_rx; /* Producer/consumer ring indices */
325 unsigned int rx_buf_sz; /* Based on MTU+slack. */
326 struct tx_status_words *tx_tail_desc;
327 unsigned int cur_tx, dirty_tx;
329 unsigned int tx_full:1; /* The Tx queue is full. */
330 unsigned int full_duplex:1; /* Full-duplex operation requested. */
331 unsigned int duplex_lock:1;
332 unsigned int medialock:1; /* Do not sense media. */
333 unsigned int default_port:4; /* Last dev->if_port value. */
334 /* MII transceiver section. */
335 int mii_cnt; /* MII device addresses. */
336 u16 advertising; /* NWay media advertisement */
337 unsigned char phys[MII_CNT]; /* MII device addresses, only first one used */
342 static int read_eeprom(void __iomem *ioaddr, int location);
343 static int mdio_read(void __iomem *ioaddr, int phy_id, int location);
344 static void mdio_write(void __iomem *ioaddr, int phy_id, int location, int value);
345 static int netdev_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
346 static int yellowfin_open(struct net_device *dev);
347 static void yellowfin_timer(unsigned long data);
348 static void yellowfin_tx_timeout(struct net_device *dev);
349 static void yellowfin_init_ring(struct net_device *dev);
350 static int yellowfin_start_xmit(struct sk_buff *skb, struct net_device *dev);
351 static irqreturn_t yellowfin_interrupt(int irq, void *dev_instance);
352 static int yellowfin_rx(struct net_device *dev);
353 static void yellowfin_error(struct net_device *dev, int intr_status);
354 static int yellowfin_close(struct net_device *dev);
355 static void set_rx_mode(struct net_device *dev);
356 static const struct ethtool_ops ethtool_ops;
359 static int __devinit yellowfin_init_one(struct pci_dev *pdev,
360 const struct pci_device_id *ent)
362 struct net_device *dev;
363 struct yellowfin_private *np;
365 int chip_idx = ent->driver_data;
367 void __iomem *ioaddr;
368 int i, option = find_cnt < MAX_UNITS ? options[find_cnt] : 0;
369 int drv_flags = pci_id_tbl[chip_idx].drv_flags;
378 /* when built into the kernel, we only print version if device is found */
380 static int printed_version;
381 if (!printed_version++)
385 i = pci_enable_device(pdev);
388 dev = alloc_etherdev(sizeof(*np));
390 printk (KERN_ERR PFX "cannot allocate ethernet device\n");
393 SET_NETDEV_DEV(dev, &pdev->dev);
395 np = netdev_priv(dev);
397 if (pci_request_regions(pdev, DRV_NAME))
398 goto err_out_free_netdev;
400 pci_set_master (pdev);
402 ioaddr = pci_iomap(pdev, bar, YELLOWFIN_SIZE);
404 goto err_out_free_res;
408 if (drv_flags & DontUseEeprom)
409 for (i = 0; i < 6; i++)
410 dev->dev_addr[i] = ioread8(ioaddr + StnAddr + i);
412 int ee_offset = (read_eeprom(ioaddr, 6) == 0xff ? 0x100 : 0);
413 for (i = 0; i < 6; i++)
414 dev->dev_addr[i] = read_eeprom(ioaddr, ee_offset + i);
417 /* Reset the chip. */
418 iowrite32(0x80000000, ioaddr + DMACtrl);
420 dev->base_addr = (unsigned long)ioaddr;
423 pci_set_drvdata(pdev, dev);
424 spin_lock_init(&np->lock);
427 np->chip_id = chip_idx;
428 np->drv_flags = drv_flags;
431 ring_space = pci_alloc_consistent(pdev, TX_TOTAL_SIZE, &ring_dma);
433 goto err_out_cleardev;
434 np->tx_ring = (struct yellowfin_desc *)ring_space;
435 np->tx_ring_dma = ring_dma;
437 ring_space = pci_alloc_consistent(pdev, RX_TOTAL_SIZE, &ring_dma);
439 goto err_out_unmap_tx;
440 np->rx_ring = (struct yellowfin_desc *)ring_space;
441 np->rx_ring_dma = ring_dma;
443 ring_space = pci_alloc_consistent(pdev, STATUS_TOTAL_SIZE, &ring_dma);
445 goto err_out_unmap_rx;
446 np->tx_status = (struct tx_status_words *)ring_space;
447 np->tx_status_dma = ring_dma;
450 option = dev->mem_start;
452 /* The lower four bits are the media type. */
456 np->default_port = option & 15;
457 if (np->default_port)
460 if (find_cnt < MAX_UNITS && full_duplex[find_cnt] > 0)
466 /* The Yellowfin-specific entries in the device structure. */
467 dev->open = &yellowfin_open;
468 dev->hard_start_xmit = &yellowfin_start_xmit;
469 dev->stop = &yellowfin_close;
470 dev->set_multicast_list = &set_rx_mode;
471 dev->do_ioctl = &netdev_ioctl;
472 SET_ETHTOOL_OPS(dev, ðtool_ops);
473 dev->tx_timeout = yellowfin_tx_timeout;
474 dev->watchdog_timeo = TX_TIMEOUT;
479 i = register_netdev(dev);
481 goto err_out_unmap_status;
483 printk(KERN_INFO "%s: %s type %8x at %p, ",
484 dev->name, pci_id_tbl[chip_idx].name,
485 ioread32(ioaddr + ChipRev), ioaddr);
486 for (i = 0; i < 5; i++)
487 printk("%2.2x:", dev->dev_addr[i]);
488 printk("%2.2x, IRQ %d.\n", dev->dev_addr[i], irq);
490 if (np->drv_flags & HasMII) {
491 int phy, phy_idx = 0;
492 for (phy = 0; phy < 32 && phy_idx < MII_CNT; phy++) {
493 int mii_status = mdio_read(ioaddr, phy, 1);
494 if (mii_status != 0xffff && mii_status != 0x0000) {
495 np->phys[phy_idx++] = phy;
496 np->advertising = mdio_read(ioaddr, phy, 4);
497 printk(KERN_INFO "%s: MII PHY found at address %d, status "
498 "0x%4.4x advertising %4.4x.\n",
499 dev->name, phy, mii_status, np->advertising);
502 np->mii_cnt = phy_idx;
509 err_out_unmap_status:
510 pci_free_consistent(pdev, STATUS_TOTAL_SIZE, np->tx_status,
513 pci_free_consistent(pdev, RX_TOTAL_SIZE, np->rx_ring, np->rx_ring_dma);
515 pci_free_consistent(pdev, TX_TOTAL_SIZE, np->tx_ring, np->tx_ring_dma);
517 pci_set_drvdata(pdev, NULL);
518 pci_iounmap(pdev, ioaddr);
520 pci_release_regions(pdev);
526 static int __devinit read_eeprom(void __iomem *ioaddr, int location)
528 int bogus_cnt = 10000; /* Typical 33Mhz: 1050 ticks */
530 iowrite8(location, ioaddr + EEAddr);
531 iowrite8(0x30 | ((location >> 8) & 7), ioaddr + EECtrl);
532 while ((ioread8(ioaddr + EEStatus) & 0x80) && --bogus_cnt > 0)
534 return ioread8(ioaddr + EERead);
537 /* MII Managemen Data I/O accesses.
538 These routines assume the MDIO controller is idle, and do not exit until
539 the command is finished. */
541 static int mdio_read(void __iomem *ioaddr, int phy_id, int location)
545 iowrite16((phy_id<<8) + location, ioaddr + MII_Addr);
546 iowrite16(1, ioaddr + MII_Cmd);
547 for (i = 10000; i >= 0; i--)
548 if ((ioread16(ioaddr + MII_Status) & 1) == 0)
550 return ioread16(ioaddr + MII_Rd_Data);
553 static void mdio_write(void __iomem *ioaddr, int phy_id, int location, int value)
557 iowrite16((phy_id<<8) + location, ioaddr + MII_Addr);
558 iowrite16(value, ioaddr + MII_Wr_Data);
560 /* Wait for the command to finish. */
561 for (i = 10000; i >= 0; i--)
562 if ((ioread16(ioaddr + MII_Status) & 1) == 0)
568 static int yellowfin_open(struct net_device *dev)
570 struct yellowfin_private *yp = netdev_priv(dev);
571 void __iomem *ioaddr = yp->base;
574 /* Reset the chip. */
575 iowrite32(0x80000000, ioaddr + DMACtrl);
577 i = request_irq(dev->irq, &yellowfin_interrupt, IRQF_SHARED, dev->name, dev);
580 if (yellowfin_debug > 1)
581 printk(KERN_DEBUG "%s: yellowfin_open() irq %d.\n",
582 dev->name, dev->irq);
584 yellowfin_init_ring(dev);
586 iowrite32(yp->rx_ring_dma, ioaddr + RxPtr);
587 iowrite32(yp->tx_ring_dma, ioaddr + TxPtr);
589 for (i = 0; i < 6; i++)
590 iowrite8(dev->dev_addr[i], ioaddr + StnAddr + i);
592 /* Set up various condition 'select' registers.
593 There are no options here. */
594 iowrite32(0x00800080, ioaddr + TxIntrSel); /* Interrupt on Tx abort */
595 iowrite32(0x00800080, ioaddr + TxBranchSel); /* Branch on Tx abort */
596 iowrite32(0x00400040, ioaddr + TxWaitSel); /* Wait on Tx status */
597 iowrite32(0x00400040, ioaddr + RxIntrSel); /* Interrupt on Rx done */
598 iowrite32(0x00400040, ioaddr + RxBranchSel); /* Branch on Rx error */
599 iowrite32(0x00400040, ioaddr + RxWaitSel); /* Wait on Rx done */
601 /* Initialize other registers: with so many this eventually this will
602 converted to an offset/value list. */
603 iowrite32(dma_ctrl, ioaddr + DMACtrl);
604 iowrite16(fifo_cfg, ioaddr + FIFOcfg);
605 /* Enable automatic generation of flow control frames, period 0xffff. */
606 iowrite32(0x0030FFFF, ioaddr + FlowCtrl);
608 yp->tx_threshold = 32;
609 iowrite32(yp->tx_threshold, ioaddr + TxThreshold);
611 if (dev->if_port == 0)
612 dev->if_port = yp->default_port;
614 netif_start_queue(dev);
616 /* Setting the Rx mode will start the Rx process. */
617 if (yp->drv_flags & IsGigabit) {
618 /* We are always in full-duplex mode with gigabit! */
620 iowrite16(0x01CF, ioaddr + Cnfg);
622 iowrite16(0x0018, ioaddr + FrameGap0); /* 0060/4060 for non-MII 10baseT */
623 iowrite16(0x1018, ioaddr + FrameGap1);
624 iowrite16(0x101C | (yp->full_duplex ? 2 : 0), ioaddr + Cnfg);
628 /* Enable interrupts by setting the interrupt mask. */
629 iowrite16(0x81ff, ioaddr + IntrEnb); /* See enum intr_status_bits */
630 iowrite16(0x0000, ioaddr + EventStatus); /* Clear non-interrupting events */
631 iowrite32(0x80008000, ioaddr + RxCtrl); /* Start Rx and Tx channels. */
632 iowrite32(0x80008000, ioaddr + TxCtrl);
634 if (yellowfin_debug > 2) {
635 printk(KERN_DEBUG "%s: Done yellowfin_open().\n",
639 /* Set the timer to check for link beat. */
640 init_timer(&yp->timer);
641 yp->timer.expires = jiffies + 3*HZ;
642 yp->timer.data = (unsigned long)dev;
643 yp->timer.function = &yellowfin_timer; /* timer handler */
644 add_timer(&yp->timer);
649 static void yellowfin_timer(unsigned long data)
651 struct net_device *dev = (struct net_device *)data;
652 struct yellowfin_private *yp = netdev_priv(dev);
653 void __iomem *ioaddr = yp->base;
654 int next_tick = 60*HZ;
656 if (yellowfin_debug > 3) {
657 printk(KERN_DEBUG "%s: Yellowfin timer tick, status %8.8x.\n",
658 dev->name, ioread16(ioaddr + IntrStatus));
662 int bmsr = mdio_read(ioaddr, yp->phys[0], MII_BMSR);
663 int lpa = mdio_read(ioaddr, yp->phys[0], MII_LPA);
664 int negotiated = lpa & yp->advertising;
665 if (yellowfin_debug > 1)
666 printk(KERN_DEBUG "%s: MII #%d status register is %4.4x, "
667 "link partner capability %4.4x.\n",
668 dev->name, yp->phys[0], bmsr, lpa);
670 yp->full_duplex = mii_duplex(yp->duplex_lock, negotiated);
672 iowrite16(0x101C | (yp->full_duplex ? 2 : 0), ioaddr + Cnfg);
674 if (bmsr & BMSR_LSTATUS)
680 yp->timer.expires = jiffies + next_tick;
681 add_timer(&yp->timer);
684 static void yellowfin_tx_timeout(struct net_device *dev)
686 struct yellowfin_private *yp = netdev_priv(dev);
687 void __iomem *ioaddr = yp->base;
689 printk(KERN_WARNING "%s: Yellowfin transmit timed out at %d/%d Tx "
690 "status %4.4x, Rx status %4.4x, resetting...\n",
691 dev->name, yp->cur_tx, yp->dirty_tx,
692 ioread32(ioaddr + TxStatus), ioread32(ioaddr + RxStatus));
694 /* Note: these should be KERN_DEBUG. */
695 if (yellowfin_debug) {
697 printk(KERN_WARNING " Rx ring %p: ", yp->rx_ring);
698 for (i = 0; i < RX_RING_SIZE; i++)
699 printk(" %8.8x", yp->rx_ring[i].result_status);
700 printk("\n"KERN_WARNING" Tx ring %p: ", yp->tx_ring);
701 for (i = 0; i < TX_RING_SIZE; i++)
702 printk(" %4.4x /%8.8x", yp->tx_status[i].tx_errs,
703 yp->tx_ring[i].result_status);
707 /* If the hardware is found to hang regularly, we will update the code
708 to reinitialize the chip here. */
711 /* Wake the potentially-idle transmit channel. */
712 iowrite32(0x10001000, yp->base + TxCtrl);
713 if (yp->cur_tx - yp->dirty_tx < TX_QUEUE_SIZE)
714 netif_wake_queue (dev); /* Typical path */
716 dev->trans_start = jiffies;
717 dev->stats.tx_errors++;
720 /* Initialize the Rx and Tx rings, along with various 'dev' bits. */
721 static void yellowfin_init_ring(struct net_device *dev)
723 struct yellowfin_private *yp = netdev_priv(dev);
727 yp->cur_rx = yp->cur_tx = 0;
730 yp->rx_buf_sz = (dev->mtu <= 1500 ? PKT_BUF_SZ : dev->mtu + 32);
732 for (i = 0; i < RX_RING_SIZE; i++) {
733 yp->rx_ring[i].dbdma_cmd =
734 cpu_to_le32(CMD_RX_BUF | INTR_ALWAYS | yp->rx_buf_sz);
735 yp->rx_ring[i].branch_addr = cpu_to_le32(yp->rx_ring_dma +
736 ((i+1)%RX_RING_SIZE)*sizeof(struct yellowfin_desc));
739 for (i = 0; i < RX_RING_SIZE; i++) {
740 struct sk_buff *skb = dev_alloc_skb(yp->rx_buf_sz);
741 yp->rx_skbuff[i] = skb;
744 skb->dev = dev; /* Mark as being used by this device. */
745 skb_reserve(skb, 2); /* 16 byte align the IP header. */
746 yp->rx_ring[i].addr = cpu_to_le32(pci_map_single(yp->pci_dev,
747 skb->data, yp->rx_buf_sz, PCI_DMA_FROMDEVICE));
749 yp->rx_ring[i-1].dbdma_cmd = cpu_to_le32(CMD_STOP);
750 yp->dirty_rx = (unsigned int)(i - RX_RING_SIZE);
754 /* In this mode the Tx ring needs only a single descriptor. */
755 for (i = 0; i < TX_RING_SIZE; i++) {
756 yp->tx_skbuff[i] = NULL;
757 yp->tx_ring[i].dbdma_cmd = cpu_to_le32(CMD_STOP);
758 yp->tx_ring[i].branch_addr = cpu_to_le32(yp->tx_ring_dma +
759 ((i+1)%TX_RING_SIZE)*sizeof(struct yellowfin_desc));
762 yp->tx_ring[--i].dbdma_cmd = cpu_to_le32(CMD_STOP | BRANCH_ALWAYS);
767 /* Tx ring needs a pair of descriptors, the second for the status. */
768 for (i = 0; i < TX_RING_SIZE; i++) {
770 yp->tx_skbuff[i] = 0;
771 /* Branch on Tx error. */
772 yp->tx_ring[j].dbdma_cmd = cpu_to_le32(CMD_STOP);
773 yp->tx_ring[j].branch_addr = cpu_to_le32(yp->tx_ring_dma +
774 (j+1)*sizeof(struct yellowfin_desc);
776 if (yp->flags & FullTxStatus) {
777 yp->tx_ring[j].dbdma_cmd =
778 cpu_to_le32(CMD_TXSTATUS | sizeof(*yp->tx_status));
779 yp->tx_ring[j].request_cnt = sizeof(*yp->tx_status);
780 yp->tx_ring[j].addr = cpu_to_le32(yp->tx_status_dma +
781 i*sizeof(struct tx_status_words);
783 /* Symbios chips write only tx_errs word. */
784 yp->tx_ring[j].dbdma_cmd =
785 cpu_to_le32(CMD_TXSTATUS | INTR_ALWAYS | 2);
786 yp->tx_ring[j].request_cnt = 2;
787 /* Om pade ummmmm... */
788 yp->tx_ring[j].addr = cpu_to_le32(yp->tx_status_dma +
789 i*sizeof(struct tx_status_words) +
790 &(yp->tx_status[0].tx_errs) -
791 &(yp->tx_status[0]));
793 yp->tx_ring[j].branch_addr = cpu_to_le32(yp->tx_ring_dma +
794 ((j+1)%(2*TX_RING_SIZE))*sizeof(struct yellowfin_desc));
797 yp->tx_ring[++j].dbdma_cmd |= cpu_to_le32(BRANCH_ALWAYS | INTR_ALWAYS);
800 yp->tx_tail_desc = &yp->tx_status[0];
804 static int yellowfin_start_xmit(struct sk_buff *skb, struct net_device *dev)
806 struct yellowfin_private *yp = netdev_priv(dev);
810 netif_stop_queue (dev);
812 /* Note: Ordering is important here, set the field with the
813 "ownership" bit last, and only then increment cur_tx. */
815 /* Calculate the next Tx descriptor entry. */
816 entry = yp->cur_tx % TX_RING_SIZE;
818 if (gx_fix) { /* Note: only works for paddable protocols e.g. IP. */
819 int cacheline_end = ((unsigned long)skb->data + skb->len) % 32;
820 /* Fix GX chipset errata. */
821 if (cacheline_end > 24 || cacheline_end == 0) {
822 len = skb->len + 32 - cacheline_end + 1;
823 if (skb_padto(skb, len)) {
824 yp->tx_skbuff[entry] = NULL;
825 netif_wake_queue(dev);
830 yp->tx_skbuff[entry] = skb;
833 yp->tx_ring[entry].addr = cpu_to_le32(pci_map_single(yp->pci_dev,
834 skb->data, len, PCI_DMA_TODEVICE));
835 yp->tx_ring[entry].result_status = 0;
836 if (entry >= TX_RING_SIZE-1) {
837 /* New stop command. */
838 yp->tx_ring[0].dbdma_cmd = cpu_to_le32(CMD_STOP);
839 yp->tx_ring[TX_RING_SIZE-1].dbdma_cmd =
840 cpu_to_le32(CMD_TX_PKT|BRANCH_ALWAYS | len);
842 yp->tx_ring[entry+1].dbdma_cmd = cpu_to_le32(CMD_STOP);
843 yp->tx_ring[entry].dbdma_cmd =
844 cpu_to_le32(CMD_TX_PKT | BRANCH_IFTRUE | len);
848 yp->tx_ring[entry<<1].request_cnt = len;
849 yp->tx_ring[entry<<1].addr = cpu_to_le32(pci_map_single(yp->pci_dev,
850 skb->data, len, PCI_DMA_TODEVICE));
851 /* The input_last (status-write) command is constant, but we must
852 rewrite the subsequent 'stop' command. */
856 unsigned next_entry = yp->cur_tx % TX_RING_SIZE;
857 yp->tx_ring[next_entry<<1].dbdma_cmd = cpu_to_le32(CMD_STOP);
859 /* Final step -- overwrite the old 'stop' command. */
861 yp->tx_ring[entry<<1].dbdma_cmd =
862 cpu_to_le32( ((entry % 6) == 0 ? CMD_TX_PKT|INTR_ALWAYS|BRANCH_IFTRUE :
863 CMD_TX_PKT | BRANCH_IFTRUE) | len);
866 /* Non-x86 Todo: explicitly flush cache lines here. */
868 /* Wake the potentially-idle transmit channel. */
869 iowrite32(0x10001000, yp->base + TxCtrl);
871 if (yp->cur_tx - yp->dirty_tx < TX_QUEUE_SIZE)
872 netif_start_queue (dev); /* Typical path */
875 dev->trans_start = jiffies;
877 if (yellowfin_debug > 4) {
878 printk(KERN_DEBUG "%s: Yellowfin transmit frame #%d queued in slot %d.\n",
879 dev->name, yp->cur_tx, entry);
884 /* The interrupt handler does all of the Rx thread work and cleans up
885 after the Tx thread. */
886 static irqreturn_t yellowfin_interrupt(int irq, void *dev_instance)
888 struct net_device *dev = dev_instance;
889 struct yellowfin_private *yp;
890 void __iomem *ioaddr;
891 int boguscnt = max_interrupt_work;
892 unsigned int handled = 0;
894 yp = netdev_priv(dev);
897 spin_lock (&yp->lock);
900 u16 intr_status = ioread16(ioaddr + IntrClear);
902 if (yellowfin_debug > 4)
903 printk(KERN_DEBUG "%s: Yellowfin interrupt, status %4.4x.\n",
904 dev->name, intr_status);
906 if (intr_status == 0)
910 if (intr_status & (IntrRxDone | IntrEarlyRx)) {
912 iowrite32(0x10001000, ioaddr + RxCtrl); /* Wake Rx engine. */
916 for (; yp->cur_tx - yp->dirty_tx > 0; yp->dirty_tx++) {
917 int entry = yp->dirty_tx % TX_RING_SIZE;
920 if (yp->tx_ring[entry].result_status == 0)
922 skb = yp->tx_skbuff[entry];
923 dev->stats.tx_packets++;
924 dev->stats.tx_bytes += skb->len;
925 /* Free the original skb. */
926 pci_unmap_single(yp->pci_dev, yp->tx_ring[entry].addr,
927 skb->len, PCI_DMA_TODEVICE);
928 dev_kfree_skb_irq(skb);
929 yp->tx_skbuff[entry] = NULL;
932 && yp->cur_tx - yp->dirty_tx < TX_QUEUE_SIZE - 4) {
933 /* The ring is no longer full, clear tbusy. */
935 netif_wake_queue(dev);
938 if ((intr_status & IntrTxDone) || (yp->tx_tail_desc->tx_errs)) {
939 unsigned dirty_tx = yp->dirty_tx;
941 for (dirty_tx = yp->dirty_tx; yp->cur_tx - dirty_tx > 0;
943 /* Todo: optimize this. */
944 int entry = dirty_tx % TX_RING_SIZE;
945 u16 tx_errs = yp->tx_status[entry].tx_errs;
948 #ifndef final_version
949 if (yellowfin_debug > 5)
950 printk(KERN_DEBUG "%s: Tx queue %d check, Tx status "
951 "%4.4x %4.4x %4.4x %4.4x.\n",
953 yp->tx_status[entry].tx_cnt,
954 yp->tx_status[entry].tx_errs,
955 yp->tx_status[entry].total_tx_cnt,
956 yp->tx_status[entry].paused);
959 break; /* It still hasn't been Txed */
960 skb = yp->tx_skbuff[entry];
961 if (tx_errs & 0xF810) {
962 /* There was an major error, log it. */
963 #ifndef final_version
964 if (yellowfin_debug > 1)
965 printk(KERN_DEBUG "%s: Transmit error, Tx status %4.4x.\n",
968 dev->stats.tx_errors++;
969 if (tx_errs & 0xF800) dev->stats.tx_aborted_errors++;
970 if (tx_errs & 0x0800) dev->stats.tx_carrier_errors++;
971 if (tx_errs & 0x2000) dev->stats.tx_window_errors++;
972 if (tx_errs & 0x8000) dev->stats.tx_fifo_errors++;
974 #ifndef final_version
975 if (yellowfin_debug > 4)
976 printk(KERN_DEBUG "%s: Normal transmit, Tx status %4.4x.\n",
979 dev->stats.tx_bytes += skb->len;
980 dev->stats.collisions += tx_errs & 15;
981 dev->stats.tx_packets++;
983 /* Free the original skb. */
984 pci_unmap_single(yp->pci_dev,
985 yp->tx_ring[entry<<1].addr, skb->len,
987 dev_kfree_skb_irq(skb);
988 yp->tx_skbuff[entry] = 0;
989 /* Mark status as empty. */
990 yp->tx_status[entry].tx_errs = 0;
993 #ifndef final_version
994 if (yp->cur_tx - dirty_tx > TX_RING_SIZE) {
995 printk(KERN_ERR "%s: Out-of-sync dirty pointer, %d vs. %d, full=%d.\n",
996 dev->name, dirty_tx, yp->cur_tx, yp->tx_full);
997 dirty_tx += TX_RING_SIZE;
1002 && yp->cur_tx - dirty_tx < TX_QUEUE_SIZE - 2) {
1003 /* The ring is no longer full, clear tbusy. */
1005 netif_wake_queue(dev);
1008 yp->dirty_tx = dirty_tx;
1009 yp->tx_tail_desc = &yp->tx_status[dirty_tx % TX_RING_SIZE];
1013 /* Log errors and other uncommon events. */
1014 if (intr_status & 0x2ee) /* Abnormal error summary. */
1015 yellowfin_error(dev, intr_status);
1017 if (--boguscnt < 0) {
1018 printk(KERN_WARNING "%s: Too much work at interrupt, "
1019 "status=0x%4.4x.\n",
1020 dev->name, intr_status);
1025 if (yellowfin_debug > 3)
1026 printk(KERN_DEBUG "%s: exiting interrupt, status=%#4.4x.\n",
1027 dev->name, ioread16(ioaddr + IntrStatus));
1029 spin_unlock (&yp->lock);
1030 return IRQ_RETVAL(handled);
1033 /* This routine is logically part of the interrupt handler, but separated
1034 for clarity and better register allocation. */
1035 static int yellowfin_rx(struct net_device *dev)
1037 struct yellowfin_private *yp = netdev_priv(dev);
1038 int entry = yp->cur_rx % RX_RING_SIZE;
1039 int boguscnt = yp->dirty_rx + RX_RING_SIZE - yp->cur_rx;
1041 if (yellowfin_debug > 4) {
1042 printk(KERN_DEBUG " In yellowfin_rx(), entry %d status %8.8x.\n",
1043 entry, yp->rx_ring[entry].result_status);
1044 printk(KERN_DEBUG " #%d desc. %8.8x %8.8x %8.8x.\n",
1045 entry, yp->rx_ring[entry].dbdma_cmd, yp->rx_ring[entry].addr,
1046 yp->rx_ring[entry].result_status);
1049 /* If EOP is set on the next entry, it's a new packet. Send it up. */
1051 struct yellowfin_desc *desc = &yp->rx_ring[entry];
1052 struct sk_buff *rx_skb = yp->rx_skbuff[entry];
1058 if(!desc->result_status)
1060 pci_dma_sync_single_for_cpu(yp->pci_dev, desc->addr,
1061 yp->rx_buf_sz, PCI_DMA_FROMDEVICE);
1062 desc_status = le32_to_cpu(desc->result_status) >> 16;
1063 buf_addr = rx_skb->data;
1064 data_size = (le32_to_cpu(desc->dbdma_cmd) -
1065 le32_to_cpu(desc->result_status)) & 0xffff;
1066 frame_status = le16_to_cpu(get_unaligned((s16*)&(buf_addr[data_size - 2])));
1067 if (yellowfin_debug > 4)
1068 printk(KERN_DEBUG " yellowfin_rx() status was %4.4x.\n",
1072 if ( ! (desc_status & RX_EOP)) {
1074 printk(KERN_WARNING "%s: Oversized Ethernet frame spanned multiple buffers,"
1075 " status %4.4x, data_size %d!\n", dev->name, desc_status, data_size);
1076 dev->stats.rx_length_errors++;
1077 } else if ((yp->drv_flags & IsGigabit) && (frame_status & 0x0038)) {
1078 /* There was a error. */
1079 if (yellowfin_debug > 3)
1080 printk(KERN_DEBUG " yellowfin_rx() Rx error was %4.4x.\n",
1082 dev->stats.rx_errors++;
1083 if (frame_status & 0x0060) dev->stats.rx_length_errors++;
1084 if (frame_status & 0x0008) dev->stats.rx_frame_errors++;
1085 if (frame_status & 0x0010) dev->stats.rx_crc_errors++;
1086 if (frame_status < 0) dev->stats.rx_dropped++;
1087 } else if ( !(yp->drv_flags & IsGigabit) &&
1088 ((buf_addr[data_size-1] & 0x85) || buf_addr[data_size-2] & 0xC0)) {
1089 u8 status1 = buf_addr[data_size-2];
1090 u8 status2 = buf_addr[data_size-1];
1091 dev->stats.rx_errors++;
1092 if (status1 & 0xC0) dev->stats.rx_length_errors++;
1093 if (status2 & 0x03) dev->stats.rx_frame_errors++;
1094 if (status2 & 0x04) dev->stats.rx_crc_errors++;
1095 if (status2 & 0x80) dev->stats.rx_dropped++;
1096 #ifdef YF_PROTOTYPE /* Support for prototype hardware errata. */
1097 } else if ((yp->flags & HasMACAddrBug) &&
1098 memcmp(le32_to_cpu(yp->rx_ring_dma +
1099 entry*sizeof(struct yellowfin_desc)),
1100 dev->dev_addr, 6) != 0 &&
1101 memcmp(le32_to_cpu(yp->rx_ring_dma +
1102 entry*sizeof(struct yellowfin_desc)),
1103 "\377\377\377\377\377\377", 6) != 0) {
1104 if (bogus_rx++ == 0)
1105 printk(KERN_WARNING "%s: Bad frame to %2.2x:%2.2x:%2.2x:%2.2x:"
1107 dev->name, buf_addr[0], buf_addr[1], buf_addr[2],
1108 buf_addr[3], buf_addr[4], buf_addr[5]);
1111 struct sk_buff *skb;
1112 int pkt_len = data_size -
1113 (yp->chip_id ? 7 : 8 + buf_addr[data_size - 8]);
1114 /* To verify: Yellowfin Length should omit the CRC! */
1116 #ifndef final_version
1117 if (yellowfin_debug > 4)
1118 printk(KERN_DEBUG " yellowfin_rx() normal Rx pkt length %d"
1119 " of %d, bogus_cnt %d.\n",
1120 pkt_len, data_size, boguscnt);
1122 /* Check if the packet is long enough to just pass up the skbuff
1123 without copying to a properly sized skbuff. */
1124 if (pkt_len > rx_copybreak) {
1125 skb_put(skb = rx_skb, pkt_len);
1126 pci_unmap_single(yp->pci_dev,
1127 yp->rx_ring[entry].addr,
1129 PCI_DMA_FROMDEVICE);
1130 yp->rx_skbuff[entry] = NULL;
1132 skb = dev_alloc_skb(pkt_len + 2);
1135 skb_reserve(skb, 2); /* 16 byte align the IP header */
1136 skb_copy_to_linear_data(skb, rx_skb->data, pkt_len);
1137 skb_put(skb, pkt_len);
1138 pci_dma_sync_single_for_device(yp->pci_dev, desc->addr,
1140 PCI_DMA_FROMDEVICE);
1142 skb->protocol = eth_type_trans(skb, dev);
1144 dev->last_rx = jiffies;
1145 dev->stats.rx_packets++;
1146 dev->stats.rx_bytes += pkt_len;
1148 entry = (++yp->cur_rx) % RX_RING_SIZE;
1151 /* Refill the Rx ring buffers. */
1152 for (; yp->cur_rx - yp->dirty_rx > 0; yp->dirty_rx++) {
1153 entry = yp->dirty_rx % RX_RING_SIZE;
1154 if (yp->rx_skbuff[entry] == NULL) {
1155 struct sk_buff *skb = dev_alloc_skb(yp->rx_buf_sz);
1157 break; /* Better luck next round. */
1158 yp->rx_skbuff[entry] = skb;
1159 skb->dev = dev; /* Mark as being used by this device. */
1160 skb_reserve(skb, 2); /* Align IP on 16 byte boundaries */
1161 yp->rx_ring[entry].addr = cpu_to_le32(pci_map_single(yp->pci_dev,
1162 skb->data, yp->rx_buf_sz, PCI_DMA_FROMDEVICE));
1164 yp->rx_ring[entry].dbdma_cmd = cpu_to_le32(CMD_STOP);
1165 yp->rx_ring[entry].result_status = 0; /* Clear complete bit. */
1167 yp->rx_ring[entry - 1].dbdma_cmd =
1168 cpu_to_le32(CMD_RX_BUF | INTR_ALWAYS | yp->rx_buf_sz);
1170 yp->rx_ring[RX_RING_SIZE - 1].dbdma_cmd =
1171 cpu_to_le32(CMD_RX_BUF | INTR_ALWAYS | BRANCH_ALWAYS
1178 static void yellowfin_error(struct net_device *dev, int intr_status)
1180 printk(KERN_ERR "%s: Something Wicked happened! %4.4x.\n",
1181 dev->name, intr_status);
1182 /* Hmmmmm, it's not clear what to do here. */
1183 if (intr_status & (IntrTxPCIErr | IntrTxPCIFault))
1184 dev->stats.tx_errors++;
1185 if (intr_status & (IntrRxPCIErr | IntrRxPCIFault))
1186 dev->stats.rx_errors++;
1189 static int yellowfin_close(struct net_device *dev)
1191 struct yellowfin_private *yp = netdev_priv(dev);
1192 void __iomem *ioaddr = yp->base;
1195 netif_stop_queue (dev);
1197 if (yellowfin_debug > 1) {
1198 printk(KERN_DEBUG "%s: Shutting down ethercard, status was Tx %4.4x "
1199 "Rx %4.4x Int %2.2x.\n",
1200 dev->name, ioread16(ioaddr + TxStatus),
1201 ioread16(ioaddr + RxStatus),
1202 ioread16(ioaddr + IntrStatus));
1203 printk(KERN_DEBUG "%s: Queue pointers were Tx %d / %d, Rx %d / %d.\n",
1204 dev->name, yp->cur_tx, yp->dirty_tx, yp->cur_rx, yp->dirty_rx);
1207 /* Disable interrupts by clearing the interrupt mask. */
1208 iowrite16(0x0000, ioaddr + IntrEnb);
1210 /* Stop the chip's Tx and Rx processes. */
1211 iowrite32(0x80000000, ioaddr + RxCtrl);
1212 iowrite32(0x80000000, ioaddr + TxCtrl);
1214 del_timer(&yp->timer);
1216 #if defined(__i386__)
1217 if (yellowfin_debug > 2) {
1218 printk("\n"KERN_DEBUG" Tx ring at %8.8llx:\n",
1219 (unsigned long long)yp->tx_ring_dma);
1220 for (i = 0; i < TX_RING_SIZE*2; i++)
1221 printk(" %c #%d desc. %8.8x %8.8x %8.8x %8.8x.\n",
1222 ioread32(ioaddr + TxPtr) == (long)&yp->tx_ring[i] ? '>' : ' ',
1223 i, yp->tx_ring[i].dbdma_cmd, yp->tx_ring[i].addr,
1224 yp->tx_ring[i].branch_addr, yp->tx_ring[i].result_status);
1225 printk(KERN_DEBUG " Tx status %p:\n", yp->tx_status);
1226 for (i = 0; i < TX_RING_SIZE; i++)
1227 printk(" #%d status %4.4x %4.4x %4.4x %4.4x.\n",
1228 i, yp->tx_status[i].tx_cnt, yp->tx_status[i].tx_errs,
1229 yp->tx_status[i].total_tx_cnt, yp->tx_status[i].paused);
1231 printk("\n"KERN_DEBUG " Rx ring %8.8llx:\n",
1232 (unsigned long long)yp->rx_ring_dma);
1233 for (i = 0; i < RX_RING_SIZE; i++) {
1234 printk(KERN_DEBUG " %c #%d desc. %8.8x %8.8x %8.8x\n",
1235 ioread32(ioaddr + RxPtr) == (long)&yp->rx_ring[i] ? '>' : ' ',
1236 i, yp->rx_ring[i].dbdma_cmd, yp->rx_ring[i].addr,
1237 yp->rx_ring[i].result_status);
1238 if (yellowfin_debug > 6) {
1239 if (get_unaligned((u8*)yp->rx_ring[i].addr) != 0x69) {
1241 for (j = 0; j < 0x50; j++)
1243 get_unaligned(((u16*)yp->rx_ring[i].addr) + j));
1249 #endif /* __i386__ debugging only */
1251 free_irq(dev->irq, dev);
1253 /* Free all the skbuffs in the Rx queue. */
1254 for (i = 0; i < RX_RING_SIZE; i++) {
1255 yp->rx_ring[i].dbdma_cmd = cpu_to_le32(CMD_STOP);
1256 yp->rx_ring[i].addr = 0xBADF00D0; /* An invalid address. */
1257 if (yp->rx_skbuff[i]) {
1258 dev_kfree_skb(yp->rx_skbuff[i]);
1260 yp->rx_skbuff[i] = NULL;
1262 for (i = 0; i < TX_RING_SIZE; i++) {
1263 if (yp->tx_skbuff[i])
1264 dev_kfree_skb(yp->tx_skbuff[i]);
1265 yp->tx_skbuff[i] = NULL;
1268 #ifdef YF_PROTOTYPE /* Support for prototype hardware errata. */
1269 if (yellowfin_debug > 0) {
1270 printk(KERN_DEBUG "%s: Received %d frames that we should not have.\n",
1271 dev->name, bogus_rx);
1278 /* Set or clear the multicast filter for this adaptor. */
1280 static void set_rx_mode(struct net_device *dev)
1282 struct yellowfin_private *yp = netdev_priv(dev);
1283 void __iomem *ioaddr = yp->base;
1284 u16 cfg_value = ioread16(ioaddr + Cnfg);
1286 /* Stop the Rx process to change any value. */
1287 iowrite16(cfg_value & ~0x1000, ioaddr + Cnfg);
1288 if (dev->flags & IFF_PROMISC) { /* Set promiscuous. */
1289 iowrite16(0x000F, ioaddr + AddrMode);
1290 } else if ((dev->mc_count > 64) || (dev->flags & IFF_ALLMULTI)) {
1291 /* Too many to filter well, or accept all multicasts. */
1292 iowrite16(0x000B, ioaddr + AddrMode);
1293 } else if (dev->mc_count > 0) { /* Must use the multicast hash table. */
1294 struct dev_mc_list *mclist;
1297 memset(hash_table, 0, sizeof(hash_table));
1298 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
1299 i++, mclist = mclist->next) {
1302 /* Due to a bug in the early chip versions, multiple filter
1303 slots must be set for each address. */
1304 if (yp->drv_flags & HasMulticastBug) {
1305 bit = (ether_crc_le(3, mclist->dmi_addr) >> 3) & 0x3f;
1306 hash_table[bit >> 4] |= (1 << bit);
1307 bit = (ether_crc_le(4, mclist->dmi_addr) >> 3) & 0x3f;
1308 hash_table[bit >> 4] |= (1 << bit);
1309 bit = (ether_crc_le(5, mclist->dmi_addr) >> 3) & 0x3f;
1310 hash_table[bit >> 4] |= (1 << bit);
1312 bit = (ether_crc_le(6, mclist->dmi_addr) >> 3) & 0x3f;
1313 hash_table[bit >> 4] |= (1 << bit);
1315 /* Copy the hash table to the chip. */
1316 for (i = 0; i < 4; i++)
1317 iowrite16(hash_table[i], ioaddr + HashTbl + i*2);
1318 iowrite16(0x0003, ioaddr + AddrMode);
1319 } else { /* Normal, unicast/broadcast-only mode. */
1320 iowrite16(0x0001, ioaddr + AddrMode);
1322 /* Restart the Rx process. */
1323 iowrite16(cfg_value | 0x1000, ioaddr + Cnfg);
1326 static void yellowfin_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
1328 struct yellowfin_private *np = netdev_priv(dev);
1329 strcpy(info->driver, DRV_NAME);
1330 strcpy(info->version, DRV_VERSION);
1331 strcpy(info->bus_info, pci_name(np->pci_dev));
1334 static const struct ethtool_ops ethtool_ops = {
1335 .get_drvinfo = yellowfin_get_drvinfo
1338 static int netdev_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
1340 struct yellowfin_private *np = netdev_priv(dev);
1341 void __iomem *ioaddr = np->base;
1342 struct mii_ioctl_data *data = if_mii(rq);
1345 case SIOCGMIIPHY: /* Get address of MII PHY in use. */
1346 data->phy_id = np->phys[0] & 0x1f;
1349 case SIOCGMIIREG: /* Read MII PHY register. */
1350 data->val_out = mdio_read(ioaddr, data->phy_id & 0x1f, data->reg_num & 0x1f);
1353 case SIOCSMIIREG: /* Write MII PHY register. */
1354 if (!capable(CAP_NET_ADMIN))
1356 if (data->phy_id == np->phys[0]) {
1357 u16 value = data->val_in;
1358 switch (data->reg_num) {
1360 /* Check for autonegotiation on or reset. */
1361 np->medialock = (value & 0x9000) ? 0 : 1;
1363 np->full_duplex = (value & 0x0100) ? 1 : 0;
1365 case 4: np->advertising = value; break;
1367 /* Perhaps check_duplex(dev), depending on chip semantics. */
1369 mdio_write(ioaddr, data->phy_id & 0x1f, data->reg_num & 0x1f, data->val_in);
1377 static void __devexit yellowfin_remove_one (struct pci_dev *pdev)
1379 struct net_device *dev = pci_get_drvdata(pdev);
1380 struct yellowfin_private *np;
1383 np = netdev_priv(dev);
1385 pci_free_consistent(pdev, STATUS_TOTAL_SIZE, np->tx_status,
1387 pci_free_consistent(pdev, RX_TOTAL_SIZE, np->rx_ring, np->rx_ring_dma);
1388 pci_free_consistent(pdev, TX_TOTAL_SIZE, np->tx_ring, np->tx_ring_dma);
1389 unregister_netdev (dev);
1391 pci_iounmap(pdev, np->base);
1393 pci_release_regions (pdev);
1396 pci_set_drvdata(pdev, NULL);
1400 static struct pci_driver yellowfin_driver = {
1402 .id_table = yellowfin_pci_tbl,
1403 .probe = yellowfin_init_one,
1404 .remove = __devexit_p(yellowfin_remove_one),
1408 static int __init yellowfin_init (void)
1410 /* when a module, this is printed whether or not devices are found in probe */
1414 return pci_register_driver(&yellowfin_driver);
1418 static void __exit yellowfin_cleanup (void)
1420 pci_unregister_driver (&yellowfin_driver);
1424 module_init(yellowfin_init);
1425 module_exit(yellowfin_cleanup);
1429 * compile-command: "gcc -DMODULE -Wall -Wstrict-prototypes -O6 -c yellowfin.c"
1430 * compile-command-alphaLX: "gcc -DMODULE -Wall -Wstrict-prototypes -O2 -c yellowfin.c -fomit-frame-pointer -fno-strength-reduce -mno-fp-regs -Wa,-m21164a -DBWX_USABLE -DBWIO_ENABLED"
1431 * simple-compile-command: "gcc -DMODULE -O6 -c yellowfin.c"