2 * Standard Hot Plug Controller Driver
4 * Copyright (C) 1995,2001 Compaq Computer Corporation
5 * Copyright (C) 2001 Greg Kroah-Hartman (greg@kroah.com)
6 * Copyright (C) 2001 IBM
7 * Copyright (C) 2003-2004 Intel Corporation
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or (at
14 * your option) any later version.
16 * This program is distributed in the hope that it will be useful, but
17 * WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
19 * NON INFRINGEMENT. See the GNU General Public License for more
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
26 * Send feedback to <greg@kroah.com>,<kristen.c.accardi@intel.com>
32 #include <linux/types.h>
33 #include <linux/pci.h>
34 #include <linux/pci_hotplug.h>
35 #include <linux/delay.h>
36 #include <linux/sched.h> /* signal_pending(), struct timer_list */
37 #include <linux/mutex.h>
40 #define MY_NAME "shpchp"
42 #define MY_NAME THIS_MODULE->name
45 extern int shpchp_poll_mode;
46 extern int shpchp_poll_time;
47 extern int shpchp_debug;
48 extern struct workqueue_struct *shpchp_wq;
50 /*#define dbg(format, arg...) do { if (shpchp_debug) printk(KERN_DEBUG "%s: " format, MY_NAME , ## arg); } while (0)*/
51 #define dbg(format, arg...) do { if (shpchp_debug) printk("%s: " format, MY_NAME , ## arg); } while (0)
52 #define err(format, arg...) printk(KERN_ERR "%s: " format, MY_NAME , ## arg)
53 #define info(format, arg...) printk(KERN_INFO "%s: " format, MY_NAME , ## arg)
54 #define warn(format, arg...) printk(KERN_WARNING "%s: " format, MY_NAME , ## arg)
56 #define SLOT_NAME_SIZE 10
66 struct timer_list task_event;
68 struct controller *ctrl;
69 struct hpc_ops *hpc_ops;
70 struct hotplug_slot *hotplug_slot;
71 struct list_head slot_list;
72 char name[SLOT_NAME_SIZE];
73 struct delayed_work work; /* work for button event */
80 struct work_struct work;
84 struct mutex crit_sect; /* critical section mutex */
85 struct mutex cmd_lock; /* command lock */
86 int num_slots; /* Number of slots on ctlr */
87 int slot_num_inc; /* 1 or -1 */
88 struct pci_dev *pci_dev;
89 struct list_head slot_list;
90 struct hpc_ops *hpc_ops;
91 wait_queue_head_t queue; /* sleep & wake process */
92 u8 slot_device_offset;
93 u32 pcix_misc2_reg; /* for amd pogo errata */
94 u32 first_slot; /* First physical slot number */
96 unsigned long mmio_base;
97 unsigned long mmio_size;
99 struct timer_list poll_timer;
103 /* Define AMD SHPC ID */
104 #define PCI_DEVICE_ID_AMD_GOLAM_7450 0x7450
105 #define PCI_DEVICE_ID_AMD_POGO_7458 0x7458
107 /* AMD PCIX bridge registers */
109 #define PCIX_MEM_BASE_LIMIT_OFFSET 0x1C
110 #define PCIX_MISCII_OFFSET 0x48
111 #define PCIX_MISC_BRIDGE_ERRORS_OFFSET 0x80
113 /* AMD PCIX_MISCII masks and offsets */
114 #define PERRNONFATALENABLE_MASK 0x00040000
115 #define PERRFATALENABLE_MASK 0x00080000
116 #define PERRFLOODENABLE_MASK 0x00100000
117 #define SERRNONFATALENABLE_MASK 0x00200000
118 #define SERRFATALENABLE_MASK 0x00400000
120 /* AMD PCIX_MISC_BRIDGE_ERRORS masks and offsets */
121 #define PERR_OBSERVED_MASK 0x00000001
123 /* AMD PCIX_MEM_BASE_LIMIT masks */
124 #define RSE_MASK 0x40000000
126 #define INT_BUTTON_IGNORE 0
127 #define INT_PRESENCE_ON 1
128 #define INT_PRESENCE_OFF 2
129 #define INT_SWITCH_CLOSE 3
130 #define INT_SWITCH_OPEN 4
131 #define INT_POWER_FAULT 5
132 #define INT_POWER_FAULT_CLEAR 6
133 #define INT_BUTTON_PRESS 7
134 #define INT_BUTTON_RELEASE 8
135 #define INT_BUTTON_CANCEL 9
137 #define STATIC_STATE 0
138 #define BLINKINGON_STATE 1
139 #define BLINKINGOFF_STATE 2
140 #define POWERON_STATE 3
141 #define POWEROFF_STATE 4
143 #define PCI_TO_PCI_BRIDGE_CLASS 0x00060400
146 #define INTERLOCK_OPEN 0x00000002
147 #define ADD_NOT_SUPPORTED 0x00000003
148 #define CARD_FUNCTIONING 0x00000005
149 #define ADAPTER_NOT_SAME 0x00000006
150 #define NO_ADAPTER_PRESENT 0x00000009
151 #define NOT_ENOUGH_RESOURCES 0x0000000B
152 #define DEVICE_TYPE_NOT_SUPPORTED 0x0000000C
153 #define WRONG_BUS_FREQUENCY 0x0000000D
154 #define POWER_FAILURE 0x0000000E
156 #define REMOVE_NOT_SUPPORTED 0x00000003
158 #define DISABLE_CARD 1
163 #define msg_initialization_err "Initialization failure, error=%d\n"
164 #define msg_button_on "PCI slot #%s - powering on due to button press.\n"
165 #define msg_button_off "PCI slot #%s - powering off due to button press.\n"
166 #define msg_button_cancel "PCI slot #%s - action canceled due to button press.\n"
168 /* sysfs functions for the hotplug controller info */
169 extern int __must_check shpchp_create_ctrl_files(struct controller *ctrl);
171 extern int shpchp_sysfs_enable_slot(struct slot *slot);
172 extern int shpchp_sysfs_disable_slot(struct slot *slot);
174 extern u8 shpchp_handle_attention_button(u8 hp_slot, struct controller *ctrl);
175 extern u8 shpchp_handle_switch_change(u8 hp_slot, struct controller *ctrl);
176 extern u8 shpchp_handle_presence_change(u8 hp_slot, struct controller *ctrl);
177 extern u8 shpchp_handle_power_fault(u8 hp_slot, struct controller *ctrl);
180 extern int shpchp_save_config(struct controller *ctrl, int busnumber, int num_ctlr_slots, int first_device_num);
181 extern int shpchp_configure_device(struct slot *p_slot);
182 extern int shpchp_unconfigure_device(struct slot *p_slot);
183 extern void shpchp_remove_ctrl_files(struct controller *ctrl);
184 extern void cleanup_slots(struct controller *ctrl);
185 extern void queue_pushbutton_work(struct work_struct *work);
189 static inline int get_hp_params_from_firmware(struct pci_dev *dev,
190 struct hotplug_params *hpp)
192 if (ACPI_FAILURE(acpi_get_hp_params_from_firmware(dev->bus, hpp)))
196 #define get_hp_hw_control_from_firmware(pdev) \
198 if (DEVICE_ACPI_HANDLE(&(pdev->dev))) \
199 acpi_run_oshp(DEVICE_ACPI_HANDLE(&(pdev->dev))); \
202 #define get_hp_params_from_firmware(dev, hpp) (-ENODEV)
203 #define get_hp_hw_control_from_firmware(dev) do { } while (0)
207 volatile u32 base_offset;
208 volatile u32 slot_avail1;
209 volatile u32 slot_avail2;
210 volatile u32 slot_config;
211 volatile u16 sec_bus_config;
212 volatile u8 msi_ctrl;
213 volatile u8 prog_interface;
215 volatile u16 cmd_status;
216 volatile u32 intr_loc;
217 volatile u32 serr_loc;
218 volatile u32 serr_intr_enable;
231 } __attribute__ ((packed));
233 /* offsets to the controller registers based on the above structure layout */
235 BASE_OFFSET = offsetof(struct ctrl_reg, base_offset),
236 SLOT_AVAIL1 = offsetof(struct ctrl_reg, slot_avail1),
237 SLOT_AVAIL2 = offsetof(struct ctrl_reg, slot_avail2),
238 SLOT_CONFIG = offsetof(struct ctrl_reg, slot_config),
239 SEC_BUS_CONFIG = offsetof(struct ctrl_reg, sec_bus_config),
240 MSI_CTRL = offsetof(struct ctrl_reg, msi_ctrl),
241 PROG_INTERFACE = offsetof(struct ctrl_reg, prog_interface),
242 CMD = offsetof(struct ctrl_reg, cmd),
243 CMD_STATUS = offsetof(struct ctrl_reg, cmd_status),
244 INTR_LOC = offsetof(struct ctrl_reg, intr_loc),
245 SERR_LOC = offsetof(struct ctrl_reg, serr_loc),
246 SERR_INTR_ENABLE = offsetof(struct ctrl_reg, serr_intr_enable),
247 SLOT1 = offsetof(struct ctrl_reg, slot1),
248 SLOT2 = offsetof(struct ctrl_reg, slot2),
249 SLOT3 = offsetof(struct ctrl_reg, slot3),
250 SLOT4 = offsetof(struct ctrl_reg, slot4),
251 SLOT5 = offsetof(struct ctrl_reg, slot5),
252 SLOT6 = offsetof(struct ctrl_reg, slot6),
253 SLOT7 = offsetof(struct ctrl_reg, slot7),
254 SLOT8 = offsetof(struct ctrl_reg, slot8),
255 SLOT9 = offsetof(struct ctrl_reg, slot9),
256 SLOT10 = offsetof(struct ctrl_reg, slot10),
257 SLOT11 = offsetof(struct ctrl_reg, slot11),
258 SLOT12 = offsetof(struct ctrl_reg, slot12),
261 /* Inline functions to check the sanity of a pointer that is passed to us */
262 static inline int slot_paranoia_check (struct slot *slot, const char *function)
265 dbg("%s - slot == NULL", function);
268 if (!slot->hotplug_slot) {
269 dbg("%s - slot->hotplug_slot == NULL!", function);
275 static inline struct slot *get_slot (struct hotplug_slot *hotplug_slot, const char *function)
280 dbg("%s - hotplug_slot == NULL\n", function);
284 slot = (struct slot *)hotplug_slot->private;
285 if (slot_paranoia_check (slot, function))
290 static inline struct slot *shpchp_find_slot (struct controller *ctrl, u8 device)
297 list_for_each_entry(slot, &ctrl->slot_list, slot_list) {
298 if (slot->device == device)
302 err("%s: slot (device=0x%x) not found\n", __FUNCTION__, device);
307 static inline void amd_pogo_errata_save_misc_reg(struct slot *p_slot)
311 /* save MiscII register */
312 pci_read_config_dword(p_slot->ctrl->pci_dev, PCIX_MISCII_OFFSET, &pcix_misc2_temp);
314 p_slot->ctrl->pcix_misc2_reg = pcix_misc2_temp;
316 /* clear SERR/PERR enable bits */
317 pcix_misc2_temp &= ~SERRFATALENABLE_MASK;
318 pcix_misc2_temp &= ~SERRNONFATALENABLE_MASK;
319 pcix_misc2_temp &= ~PERRFLOODENABLE_MASK;
320 pcix_misc2_temp &= ~PERRFATALENABLE_MASK;
321 pcix_misc2_temp &= ~PERRNONFATALENABLE_MASK;
322 pci_write_config_dword(p_slot->ctrl->pci_dev, PCIX_MISCII_OFFSET, pcix_misc2_temp);
325 static inline void amd_pogo_errata_restore_misc_reg(struct slot *p_slot)
328 u32 pcix_bridge_errors_reg;
329 u32 pcix_mem_base_reg;
333 /* write-one-to-clear Bridge_Errors[ PERR_OBSERVED ] */
334 pci_read_config_dword(p_slot->ctrl->pci_dev, PCIX_MISC_BRIDGE_ERRORS_OFFSET, &pcix_bridge_errors_reg);
335 perr_set = pcix_bridge_errors_reg & PERR_OBSERVED_MASK;
337 dbg ("%s W1C: Bridge_Errors[ PERR_OBSERVED = %08X]\n",__FUNCTION__ , perr_set);
339 pci_write_config_dword(p_slot->ctrl->pci_dev, PCIX_MISC_BRIDGE_ERRORS_OFFSET, perr_set);
342 /* write-one-to-clear Memory_Base_Limit[ RSE ] */
343 pci_read_config_dword(p_slot->ctrl->pci_dev, PCIX_MEM_BASE_LIMIT_OFFSET, &pcix_mem_base_reg);
344 rse_set = pcix_mem_base_reg & RSE_MASK;
346 dbg ("%s W1C: Memory_Base_Limit[ RSE ]\n",__FUNCTION__ );
348 pci_write_config_dword(p_slot->ctrl->pci_dev, PCIX_MEM_BASE_LIMIT_OFFSET, rse_set);
350 /* restore MiscII register */
351 pci_read_config_dword( p_slot->ctrl->pci_dev, PCIX_MISCII_OFFSET, &pcix_misc2_temp );
353 if (p_slot->ctrl->pcix_misc2_reg & SERRFATALENABLE_MASK)
354 pcix_misc2_temp |= SERRFATALENABLE_MASK;
356 pcix_misc2_temp &= ~SERRFATALENABLE_MASK;
358 if (p_slot->ctrl->pcix_misc2_reg & SERRNONFATALENABLE_MASK)
359 pcix_misc2_temp |= SERRNONFATALENABLE_MASK;
361 pcix_misc2_temp &= ~SERRNONFATALENABLE_MASK;
363 if (p_slot->ctrl->pcix_misc2_reg & PERRFLOODENABLE_MASK)
364 pcix_misc2_temp |= PERRFLOODENABLE_MASK;
366 pcix_misc2_temp &= ~PERRFLOODENABLE_MASK;
368 if (p_slot->ctrl->pcix_misc2_reg & PERRFATALENABLE_MASK)
369 pcix_misc2_temp |= PERRFATALENABLE_MASK;
371 pcix_misc2_temp &= ~PERRFATALENABLE_MASK;
373 if (p_slot->ctrl->pcix_misc2_reg & PERRNONFATALENABLE_MASK)
374 pcix_misc2_temp |= PERRNONFATALENABLE_MASK;
376 pcix_misc2_temp &= ~PERRNONFATALENABLE_MASK;
377 pci_write_config_dword(p_slot->ctrl->pci_dev, PCIX_MISCII_OFFSET, pcix_misc2_temp);
380 int shpc_init( struct controller *ctrl, struct pci_dev *pdev);
383 int (*power_on_slot ) (struct slot *slot);
384 int (*slot_enable ) (struct slot *slot);
385 int (*slot_disable ) (struct slot *slot);
386 int (*set_bus_speed_mode) (struct slot *slot, enum pci_bus_speed speed);
387 int (*get_power_status) (struct slot *slot, u8 *status);
388 int (*get_attention_status) (struct slot *slot, u8 *status);
389 int (*set_attention_status) (struct slot *slot, u8 status);
390 int (*get_latch_status) (struct slot *slot, u8 *status);
391 int (*get_adapter_status) (struct slot *slot, u8 *status);
393 int (*get_max_bus_speed) (struct slot *slot, enum pci_bus_speed *speed);
394 int (*get_cur_bus_speed) (struct slot *slot, enum pci_bus_speed *speed);
395 int (*get_adapter_speed) (struct slot *slot, enum pci_bus_speed *speed);
396 int (*get_mode1_ECC_cap) (struct slot *slot, u8 *mode);
397 int (*get_prog_int) (struct slot *slot, u8 *prog_int);
399 int (*query_power_fault) (struct slot *slot);
400 void (*green_led_on) (struct slot *slot);
401 void (*green_led_off) (struct slot *slot);
402 void (*green_led_blink) (struct slot *slot);
403 void (*release_ctlr) (struct controller *ctrl);
404 int (*check_cmd_status) (struct controller *ctrl);
407 #endif /* _SHPCHP_H */