2 * PCI Bus Services, see include/linux/pci.h for further explanation.
4 * Copyright 1993 -- 1997 Drew Eckhardt, Frederic Potter,
7 * Copyright 1997 -- 2000 Martin Mares <mj@ucw.cz>
10 #include <linux/kernel.h>
11 #include <linux/delay.h>
12 #include <linux/init.h>
13 #include <linux/pci.h>
15 #include <linux/module.h>
16 #include <linux/spinlock.h>
17 #include <linux/string.h>
18 #include <linux/log2.h>
19 #include <linux/pci-aspm.h>
20 #include <linux/pm_wakeup.h>
21 #include <linux/interrupt.h>
22 #include <asm/dma.h> /* isa_dma_bridge_buggy */
25 unsigned int pci_pm_d3_delay = 10;
27 #ifdef CONFIG_PCI_DOMAINS
28 int pci_domains_supported = 1;
31 #define DEFAULT_CARDBUS_IO_SIZE (256)
32 #define DEFAULT_CARDBUS_MEM_SIZE (64*1024*1024)
33 /* pci=cbmemsize=nnM,cbiosize=nn can override this */
34 unsigned long pci_cardbus_io_size = DEFAULT_CARDBUS_IO_SIZE;
35 unsigned long pci_cardbus_mem_size = DEFAULT_CARDBUS_MEM_SIZE;
38 * pci_bus_max_busnr - returns maximum PCI bus number of given bus' children
39 * @bus: pointer to PCI bus structure to search
41 * Given a PCI bus, returns the highest PCI bus number present in the set
42 * including the given PCI bus and its list of child PCI buses.
44 unsigned char pci_bus_max_busnr(struct pci_bus* bus)
46 struct list_head *tmp;
49 max = bus->subordinate;
50 list_for_each(tmp, &bus->children) {
51 n = pci_bus_max_busnr(pci_bus_b(tmp));
57 EXPORT_SYMBOL_GPL(pci_bus_max_busnr);
59 #ifdef CONFIG_HAS_IOMEM
60 void __iomem *pci_ioremap_bar(struct pci_dev *pdev, int bar)
63 * Make sure the BAR is actually a memory resource, not an IO resource
65 if (!(pci_resource_flags(pdev, bar) & IORESOURCE_MEM)) {
69 return ioremap_nocache(pci_resource_start(pdev, bar),
70 pci_resource_len(pdev, bar));
72 EXPORT_SYMBOL_GPL(pci_ioremap_bar);
77 * pci_max_busnr - returns maximum PCI bus number
79 * Returns the highest PCI bus number present in the system global list of
82 unsigned char __devinit
85 struct pci_bus *bus = NULL;
89 while ((bus = pci_find_next_bus(bus)) != NULL) {
90 n = pci_bus_max_busnr(bus);
99 #define PCI_FIND_CAP_TTL 48
101 static int __pci_find_next_cap_ttl(struct pci_bus *bus, unsigned int devfn,
102 u8 pos, int cap, int *ttl)
107 pci_bus_read_config_byte(bus, devfn, pos, &pos);
111 pci_bus_read_config_byte(bus, devfn, pos + PCI_CAP_LIST_ID,
117 pos += PCI_CAP_LIST_NEXT;
122 static int __pci_find_next_cap(struct pci_bus *bus, unsigned int devfn,
125 int ttl = PCI_FIND_CAP_TTL;
127 return __pci_find_next_cap_ttl(bus, devfn, pos, cap, &ttl);
130 int pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap)
132 return __pci_find_next_cap(dev->bus, dev->devfn,
133 pos + PCI_CAP_LIST_NEXT, cap);
135 EXPORT_SYMBOL_GPL(pci_find_next_capability);
137 static int __pci_bus_find_cap_start(struct pci_bus *bus,
138 unsigned int devfn, u8 hdr_type)
142 pci_bus_read_config_word(bus, devfn, PCI_STATUS, &status);
143 if (!(status & PCI_STATUS_CAP_LIST))
147 case PCI_HEADER_TYPE_NORMAL:
148 case PCI_HEADER_TYPE_BRIDGE:
149 return PCI_CAPABILITY_LIST;
150 case PCI_HEADER_TYPE_CARDBUS:
151 return PCI_CB_CAPABILITY_LIST;
160 * pci_find_capability - query for devices' capabilities
161 * @dev: PCI device to query
162 * @cap: capability code
164 * Tell if a device supports a given PCI capability.
165 * Returns the address of the requested capability structure within the
166 * device's PCI configuration space or 0 in case the device does not
167 * support it. Possible values for @cap:
169 * %PCI_CAP_ID_PM Power Management
170 * %PCI_CAP_ID_AGP Accelerated Graphics Port
171 * %PCI_CAP_ID_VPD Vital Product Data
172 * %PCI_CAP_ID_SLOTID Slot Identification
173 * %PCI_CAP_ID_MSI Message Signalled Interrupts
174 * %PCI_CAP_ID_CHSWP CompactPCI HotSwap
175 * %PCI_CAP_ID_PCIX PCI-X
176 * %PCI_CAP_ID_EXP PCI Express
178 int pci_find_capability(struct pci_dev *dev, int cap)
182 pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type);
184 pos = __pci_find_next_cap(dev->bus, dev->devfn, pos, cap);
190 * pci_bus_find_capability - query for devices' capabilities
191 * @bus: the PCI bus to query
192 * @devfn: PCI device to query
193 * @cap: capability code
195 * Like pci_find_capability() but works for pci devices that do not have a
196 * pci_dev structure set up yet.
198 * Returns the address of the requested capability structure within the
199 * device's PCI configuration space or 0 in case the device does not
202 int pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap)
207 pci_bus_read_config_byte(bus, devfn, PCI_HEADER_TYPE, &hdr_type);
209 pos = __pci_bus_find_cap_start(bus, devfn, hdr_type & 0x7f);
211 pos = __pci_find_next_cap(bus, devfn, pos, cap);
217 * pci_find_ext_capability - Find an extended capability
218 * @dev: PCI device to query
219 * @cap: capability code
221 * Returns the address of the requested extended capability structure
222 * within the device's PCI configuration space or 0 if the device does
223 * not support it. Possible values for @cap:
225 * %PCI_EXT_CAP_ID_ERR Advanced Error Reporting
226 * %PCI_EXT_CAP_ID_VC Virtual Channel
227 * %PCI_EXT_CAP_ID_DSN Device Serial Number
228 * %PCI_EXT_CAP_ID_PWR Power Budgeting
230 int pci_find_ext_capability(struct pci_dev *dev, int cap)
234 int pos = PCI_CFG_SPACE_SIZE;
236 /* minimum 8 bytes per capability */
237 ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8;
239 if (dev->cfg_size <= PCI_CFG_SPACE_SIZE)
242 if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL)
246 * If we have no capabilities, this is indicated by cap ID,
247 * cap version and next pointer all being 0.
253 if (PCI_EXT_CAP_ID(header) == cap)
256 pos = PCI_EXT_CAP_NEXT(header);
257 if (pos < PCI_CFG_SPACE_SIZE)
260 if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL)
266 EXPORT_SYMBOL_GPL(pci_find_ext_capability);
268 static int __pci_find_next_ht_cap(struct pci_dev *dev, int pos, int ht_cap)
270 int rc, ttl = PCI_FIND_CAP_TTL;
273 if (ht_cap == HT_CAPTYPE_SLAVE || ht_cap == HT_CAPTYPE_HOST)
274 mask = HT_3BIT_CAP_MASK;
276 mask = HT_5BIT_CAP_MASK;
278 pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn, pos,
279 PCI_CAP_ID_HT, &ttl);
281 rc = pci_read_config_byte(dev, pos + 3, &cap);
282 if (rc != PCIBIOS_SUCCESSFUL)
285 if ((cap & mask) == ht_cap)
288 pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn,
289 pos + PCI_CAP_LIST_NEXT,
290 PCI_CAP_ID_HT, &ttl);
296 * pci_find_next_ht_capability - query a device's Hypertransport capabilities
297 * @dev: PCI device to query
298 * @pos: Position from which to continue searching
299 * @ht_cap: Hypertransport capability code
301 * To be used in conjunction with pci_find_ht_capability() to search for
302 * all capabilities matching @ht_cap. @pos should always be a value returned
303 * from pci_find_ht_capability().
305 * NB. To be 100% safe against broken PCI devices, the caller should take
306 * steps to avoid an infinite loop.
308 int pci_find_next_ht_capability(struct pci_dev *dev, int pos, int ht_cap)
310 return __pci_find_next_ht_cap(dev, pos + PCI_CAP_LIST_NEXT, ht_cap);
312 EXPORT_SYMBOL_GPL(pci_find_next_ht_capability);
315 * pci_find_ht_capability - query a device's Hypertransport capabilities
316 * @dev: PCI device to query
317 * @ht_cap: Hypertransport capability code
319 * Tell if a device supports a given Hypertransport capability.
320 * Returns an address within the device's PCI configuration space
321 * or 0 in case the device does not support the request capability.
322 * The address points to the PCI capability, of type PCI_CAP_ID_HT,
323 * which has a Hypertransport capability matching @ht_cap.
325 int pci_find_ht_capability(struct pci_dev *dev, int ht_cap)
329 pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type);
331 pos = __pci_find_next_ht_cap(dev, pos, ht_cap);
335 EXPORT_SYMBOL_GPL(pci_find_ht_capability);
338 * pci_find_parent_resource - return resource region of parent bus of given region
339 * @dev: PCI device structure contains resources to be searched
340 * @res: child resource record for which parent is sought
342 * For given resource region of given device, return the resource
343 * region of parent bus the given region is contained in or where
344 * it should be allocated from.
347 pci_find_parent_resource(const struct pci_dev *dev, struct resource *res)
349 const struct pci_bus *bus = dev->bus;
351 struct resource *best = NULL;
353 for(i = 0; i < PCI_BUS_NUM_RESOURCES; i++) {
354 struct resource *r = bus->resource[i];
357 if (res->start && !(res->start >= r->start && res->end <= r->end))
358 continue; /* Not contained */
359 if ((res->flags ^ r->flags) & (IORESOURCE_IO | IORESOURCE_MEM))
360 continue; /* Wrong type */
361 if (!((res->flags ^ r->flags) & IORESOURCE_PREFETCH))
362 return r; /* Exact match */
363 if ((res->flags & IORESOURCE_PREFETCH) && !(r->flags & IORESOURCE_PREFETCH))
364 best = r; /* Approximating prefetchable by non-prefetchable */
370 * pci_restore_bars - restore a devices BAR values (e.g. after wake-up)
371 * @dev: PCI device to have its BARs restored
373 * Restore the BAR values for a given device, so as to make it
374 * accessible by its driver.
377 pci_restore_bars(struct pci_dev *dev)
381 for (i = 0; i < PCI_BRIDGE_RESOURCES; i++)
382 pci_update_resource(dev, i);
385 static struct pci_platform_pm_ops *pci_platform_pm;
387 int pci_set_platform_pm(struct pci_platform_pm_ops *ops)
389 if (!ops->is_manageable || !ops->set_state || !ops->choose_state
390 || !ops->sleep_wake || !ops->can_wakeup)
392 pci_platform_pm = ops;
396 static inline bool platform_pci_power_manageable(struct pci_dev *dev)
398 return pci_platform_pm ? pci_platform_pm->is_manageable(dev) : false;
401 static inline int platform_pci_set_power_state(struct pci_dev *dev,
404 return pci_platform_pm ? pci_platform_pm->set_state(dev, t) : -ENOSYS;
407 static inline pci_power_t platform_pci_choose_state(struct pci_dev *dev)
409 return pci_platform_pm ?
410 pci_platform_pm->choose_state(dev) : PCI_POWER_ERROR;
413 static inline bool platform_pci_can_wakeup(struct pci_dev *dev)
415 return pci_platform_pm ? pci_platform_pm->can_wakeup(dev) : false;
418 static inline int platform_pci_sleep_wake(struct pci_dev *dev, bool enable)
420 return pci_platform_pm ?
421 pci_platform_pm->sleep_wake(dev, enable) : -ENODEV;
425 * pci_raw_set_power_state - Use PCI PM registers to set the power state of
427 * @dev: PCI device to handle.
428 * @state: PCI power state (D0, D1, D2, D3hot) to put the device into.
431 * -EINVAL if the requested state is invalid.
432 * -EIO if device does not support PCI PM or its PM capabilities register has a
433 * wrong version, or device doesn't support the requested state.
434 * 0 if device already is in the requested state.
435 * 0 if device's power state has been successfully changed.
438 pci_raw_set_power_state(struct pci_dev *dev, pci_power_t state)
441 bool need_restore = false;
446 if (state < PCI_D0 || state > PCI_D3hot)
449 /* Validate current state:
450 * Can enter D0 from any state, but if we can only go deeper
451 * to sleep if we're already in a low power state
453 if (dev->current_state == state) {
454 /* we're already there */
456 } else if (state != PCI_D0 && dev->current_state <= PCI_D3cold
457 && dev->current_state > state) {
458 dev_err(&dev->dev, "invalid power transition "
459 "(from state %d to %d)\n", dev->current_state, state);
463 /* check if this device supports the desired state */
464 if ((state == PCI_D1 && !dev->d1_support)
465 || (state == PCI_D2 && !dev->d2_support))
468 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
470 /* If we're (effectively) in D3, force entire word to 0.
471 * This doesn't affect PME_Status, disables PME_En, and
472 * sets PowerState to 0.
474 switch (dev->current_state) {
478 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
481 case PCI_UNKNOWN: /* Boot-up */
482 if ((pmcsr & PCI_PM_CTRL_STATE_MASK) == PCI_D3hot
483 && !(pmcsr & PCI_PM_CTRL_NO_SOFT_RESET))
485 /* Fall-through: force to D0 */
491 /* enter specified state */
492 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr);
494 /* Mandatory power management transition delays */
495 /* see PCI PM 1.1 5.6.1 table 18 */
496 if (state == PCI_D3hot || dev->current_state == PCI_D3hot)
497 msleep(pci_pm_d3_delay);
498 else if (state == PCI_D2 || dev->current_state == PCI_D2)
501 dev->current_state = state;
503 /* According to section 5.4.1 of the "PCI BUS POWER MANAGEMENT
504 * INTERFACE SPECIFICATION, REV. 1.2", a device transitioning
505 * from D3hot to D0 _may_ perform an internal reset, thereby
506 * going to "D0 Uninitialized" rather than "D0 Initialized".
507 * For example, at least some versions of the 3c905B and the
508 * 3c556B exhibit this behaviour.
510 * At least some laptop BIOSen (e.g. the Thinkpad T21) leave
511 * devices in a D3hot state at boot. Consequently, we need to
512 * restore at least the BARs so that the device will be
513 * accessible to its driver.
516 pci_restore_bars(dev);
519 pcie_aspm_pm_state_change(dev->bus->self);
525 * pci_update_current_state - Read PCI power state of given device from its
526 * PCI PM registers and cache it
527 * @dev: PCI device to handle.
528 * @state: State to cache in case the device doesn't have the PM capability
530 static void pci_update_current_state(struct pci_dev *dev, pci_power_t state)
535 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
536 dev->current_state = (pmcsr & PCI_PM_CTRL_STATE_MASK);
538 dev->current_state = state;
543 * pci_set_power_state - Set the power state of a PCI device
544 * @dev: PCI device to handle.
545 * @state: PCI power state (D0, D1, D2, D3hot) to put the device into.
547 * Transition a device to a new power state, using the platform formware and/or
548 * the device's PCI PM registers.
551 * -EINVAL if the requested state is invalid.
552 * -EIO if device does not support PCI PM or its PM capabilities register has a
553 * wrong version, or device doesn't support the requested state.
554 * 0 if device already is in the requested state.
555 * 0 if device's power state has been successfully changed.
557 int pci_set_power_state(struct pci_dev *dev, pci_power_t state)
561 /* bound the state we're entering */
562 if (state > PCI_D3hot)
564 else if (state < PCI_D0)
566 else if ((state == PCI_D1 || state == PCI_D2) && pci_no_d1d2(dev))
568 * If the device or the parent bridge do not support PCI PM,
569 * ignore the request if we're doing anything other than putting
570 * it into D0 (which would only happen on boot).
574 if (state == PCI_D0 && platform_pci_power_manageable(dev)) {
576 * Allow the platform to change the state, for example via ACPI
577 * _PR0, _PS0 and some such, but do not trust it.
579 int ret = platform_pci_set_power_state(dev, PCI_D0);
581 pci_update_current_state(dev, PCI_D0);
583 /* This device is quirked not to be put into D3, so
584 don't put it in D3 */
585 if (state == PCI_D3hot && (dev->dev_flags & PCI_DEV_FLAGS_NO_D3))
588 error = pci_raw_set_power_state(dev, state);
590 if (state > PCI_D0 && platform_pci_power_manageable(dev)) {
591 /* Allow the platform to finalize the transition */
592 int ret = platform_pci_set_power_state(dev, state);
594 pci_update_current_state(dev, state);
603 * pci_choose_state - Choose the power state of a PCI device
604 * @dev: PCI device to be suspended
605 * @state: target sleep state for the whole system. This is the value
606 * that is passed to suspend() function.
608 * Returns PCI power state suitable for given device and given system
612 pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state)
616 if (!pci_find_capability(dev, PCI_CAP_ID_PM))
619 ret = platform_pci_choose_state(dev);
620 if (ret != PCI_POWER_ERROR)
623 switch (state.event) {
626 case PM_EVENT_FREEZE:
627 case PM_EVENT_PRETHAW:
628 /* REVISIT both freeze and pre-thaw "should" use D0 */
629 case PM_EVENT_SUSPEND:
630 case PM_EVENT_HIBERNATE:
633 dev_info(&dev->dev, "unrecognized suspend event %d\n",
640 EXPORT_SYMBOL(pci_choose_state);
642 static int pci_save_pcie_state(struct pci_dev *dev)
645 struct pci_cap_saved_state *save_state;
648 pos = pci_find_capability(dev, PCI_CAP_ID_EXP);
652 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP);
654 dev_err(&dev->dev, "buffer not found in %s\n", __FUNCTION__);
657 cap = (u16 *)&save_state->data[0];
659 pci_read_config_word(dev, pos + PCI_EXP_DEVCTL, &cap[i++]);
660 pci_read_config_word(dev, pos + PCI_EXP_LNKCTL, &cap[i++]);
661 pci_read_config_word(dev, pos + PCI_EXP_SLTCTL, &cap[i++]);
662 pci_read_config_word(dev, pos + PCI_EXP_RTCTL, &cap[i++]);
667 static void pci_restore_pcie_state(struct pci_dev *dev)
670 struct pci_cap_saved_state *save_state;
673 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP);
674 pos = pci_find_capability(dev, PCI_CAP_ID_EXP);
675 if (!save_state || pos <= 0)
677 cap = (u16 *)&save_state->data[0];
679 pci_write_config_word(dev, pos + PCI_EXP_DEVCTL, cap[i++]);
680 pci_write_config_word(dev, pos + PCI_EXP_LNKCTL, cap[i++]);
681 pci_write_config_word(dev, pos + PCI_EXP_SLTCTL, cap[i++]);
682 pci_write_config_word(dev, pos + PCI_EXP_RTCTL, cap[i++]);
686 static int pci_save_pcix_state(struct pci_dev *dev)
689 struct pci_cap_saved_state *save_state;
691 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
695 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_PCIX);
697 dev_err(&dev->dev, "buffer not found in %s\n", __FUNCTION__);
701 pci_read_config_word(dev, pos + PCI_X_CMD, (u16 *)save_state->data);
706 static void pci_restore_pcix_state(struct pci_dev *dev)
709 struct pci_cap_saved_state *save_state;
712 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_PCIX);
713 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
714 if (!save_state || pos <= 0)
716 cap = (u16 *)&save_state->data[0];
718 pci_write_config_word(dev, pos + PCI_X_CMD, cap[i++]);
723 * pci_save_state - save the PCI configuration space of a device before suspending
724 * @dev: - PCI device that we're dealing with
727 pci_save_state(struct pci_dev *dev)
730 /* XXX: 100% dword access ok here? */
731 for (i = 0; i < 16; i++)
732 pci_read_config_dword(dev, i * 4,&dev->saved_config_space[i]);
733 if ((i = pci_save_pcie_state(dev)) != 0)
735 if ((i = pci_save_pcix_state(dev)) != 0)
741 * pci_restore_state - Restore the saved state of a PCI device
742 * @dev: - PCI device that we're dealing with
745 pci_restore_state(struct pci_dev *dev)
750 /* PCI Express register must be restored first */
751 pci_restore_pcie_state(dev);
754 * The Base Address register should be programmed before the command
757 for (i = 15; i >= 0; i--) {
758 pci_read_config_dword(dev, i * 4, &val);
759 if (val != dev->saved_config_space[i]) {
760 dev_printk(KERN_DEBUG, &dev->dev, "restoring config "
761 "space at offset %#x (was %#x, writing %#x)\n",
762 i, val, (int)dev->saved_config_space[i]);
763 pci_write_config_dword(dev,i * 4,
764 dev->saved_config_space[i]);
767 pci_restore_pcix_state(dev);
768 pci_restore_msi_state(dev);
773 static int do_pci_enable_device(struct pci_dev *dev, int bars)
777 err = pci_set_power_state(dev, PCI_D0);
778 if (err < 0 && err != -EIO)
780 err = pcibios_enable_device(dev, bars);
783 pci_fixup_device(pci_fixup_enable, dev);
789 * pci_reenable_device - Resume abandoned device
790 * @dev: PCI device to be resumed
792 * Note this function is a backend of pci_default_resume and is not supposed
793 * to be called by normal code, write proper resume handler and use it instead.
795 int pci_reenable_device(struct pci_dev *dev)
797 if (atomic_read(&dev->enable_cnt))
798 return do_pci_enable_device(dev, (1 << PCI_NUM_RESOURCES) - 1);
802 static int __pci_enable_device_flags(struct pci_dev *dev,
803 resource_size_t flags)
808 if (atomic_add_return(1, &dev->enable_cnt) > 1)
809 return 0; /* already enabled */
811 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++)
812 if (dev->resource[i].flags & flags)
815 err = do_pci_enable_device(dev, bars);
817 atomic_dec(&dev->enable_cnt);
822 * pci_enable_device_io - Initialize a device for use with IO space
823 * @dev: PCI device to be initialized
825 * Initialize device before it's used by a driver. Ask low-level code
826 * to enable I/O resources. Wake up the device if it was suspended.
827 * Beware, this function can fail.
829 int pci_enable_device_io(struct pci_dev *dev)
831 return __pci_enable_device_flags(dev, IORESOURCE_IO);
835 * pci_enable_device_mem - Initialize a device for use with Memory space
836 * @dev: PCI device to be initialized
838 * Initialize device before it's used by a driver. Ask low-level code
839 * to enable Memory resources. Wake up the device if it was suspended.
840 * Beware, this function can fail.
842 int pci_enable_device_mem(struct pci_dev *dev)
844 return __pci_enable_device_flags(dev, IORESOURCE_MEM);
848 * pci_enable_device - Initialize device before it's used by a driver.
849 * @dev: PCI device to be initialized
851 * Initialize device before it's used by a driver. Ask low-level code
852 * to enable I/O and memory. Wake up the device if it was suspended.
853 * Beware, this function can fail.
855 * Note we don't actually enable the device many times if we call
856 * this function repeatedly (we just increment the count).
858 int pci_enable_device(struct pci_dev *dev)
860 return __pci_enable_device_flags(dev, IORESOURCE_MEM | IORESOURCE_IO);
864 * Managed PCI resources. This manages device on/off, intx/msi/msix
865 * on/off and BAR regions. pci_dev itself records msi/msix status, so
866 * there's no need to track it separately. pci_devres is initialized
867 * when a device is enabled using managed PCI device enable interface.
870 unsigned int enabled:1;
871 unsigned int pinned:1;
872 unsigned int orig_intx:1;
873 unsigned int restore_intx:1;
877 static void pcim_release(struct device *gendev, void *res)
879 struct pci_dev *dev = container_of(gendev, struct pci_dev, dev);
880 struct pci_devres *this = res;
883 if (dev->msi_enabled)
884 pci_disable_msi(dev);
885 if (dev->msix_enabled)
886 pci_disable_msix(dev);
888 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++)
889 if (this->region_mask & (1 << i))
890 pci_release_region(dev, i);
892 if (this->restore_intx)
893 pci_intx(dev, this->orig_intx);
895 if (this->enabled && !this->pinned)
896 pci_disable_device(dev);
899 static struct pci_devres * get_pci_dr(struct pci_dev *pdev)
901 struct pci_devres *dr, *new_dr;
903 dr = devres_find(&pdev->dev, pcim_release, NULL, NULL);
907 new_dr = devres_alloc(pcim_release, sizeof(*new_dr), GFP_KERNEL);
910 return devres_get(&pdev->dev, new_dr, NULL, NULL);
913 static struct pci_devres * find_pci_dr(struct pci_dev *pdev)
915 if (pci_is_managed(pdev))
916 return devres_find(&pdev->dev, pcim_release, NULL, NULL);
921 * pcim_enable_device - Managed pci_enable_device()
922 * @pdev: PCI device to be initialized
924 * Managed pci_enable_device().
926 int pcim_enable_device(struct pci_dev *pdev)
928 struct pci_devres *dr;
931 dr = get_pci_dr(pdev);
937 rc = pci_enable_device(pdev);
939 pdev->is_managed = 1;
946 * pcim_pin_device - Pin managed PCI device
947 * @pdev: PCI device to pin
949 * Pin managed PCI device @pdev. Pinned device won't be disabled on
950 * driver detach. @pdev must have been enabled with
951 * pcim_enable_device().
953 void pcim_pin_device(struct pci_dev *pdev)
955 struct pci_devres *dr;
957 dr = find_pci_dr(pdev);
958 WARN_ON(!dr || !dr->enabled);
964 * pcibios_disable_device - disable arch specific PCI resources for device dev
965 * @dev: the PCI device to disable
967 * Disables architecture specific PCI resources for the device. This
968 * is the default implementation. Architecture implementations can
971 void __attribute__ ((weak)) pcibios_disable_device (struct pci_dev *dev) {}
974 * pci_disable_device - Disable PCI device after use
975 * @dev: PCI device to be disabled
977 * Signal to the system that the PCI device is not in use by the system
978 * anymore. This only involves disabling PCI bus-mastering, if active.
980 * Note we don't actually disable the device until all callers of
981 * pci_device_enable() have called pci_device_disable().
984 pci_disable_device(struct pci_dev *dev)
986 struct pci_devres *dr;
989 dr = find_pci_dr(dev);
993 if (atomic_sub_return(1, &dev->enable_cnt) != 0)
996 pci_read_config_word(dev, PCI_COMMAND, &pci_command);
997 if (pci_command & PCI_COMMAND_MASTER) {
998 pci_command &= ~PCI_COMMAND_MASTER;
999 pci_write_config_word(dev, PCI_COMMAND, pci_command);
1001 dev->is_busmaster = 0;
1003 pcibios_disable_device(dev);
1007 * pcibios_set_pcie_reset_state - set reset state for device dev
1008 * @dev: the PCI-E device reset
1009 * @state: Reset state to enter into
1012 * Sets the PCI-E reset state for the device. This is the default
1013 * implementation. Architecture implementations can override this.
1015 int __attribute__ ((weak)) pcibios_set_pcie_reset_state(struct pci_dev *dev,
1016 enum pcie_reset_state state)
1022 * pci_set_pcie_reset_state - set reset state for device dev
1023 * @dev: the PCI-E device reset
1024 * @state: Reset state to enter into
1027 * Sets the PCI reset state for the device.
1029 int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state)
1031 return pcibios_set_pcie_reset_state(dev, state);
1035 * pci_pme_capable - check the capability of PCI device to generate PME#
1036 * @dev: PCI device to handle.
1037 * @state: PCI state from which device will issue PME#.
1039 bool pci_pme_capable(struct pci_dev *dev, pci_power_t state)
1044 return !!(dev->pme_support & (1 << state));
1048 * pci_pme_active - enable or disable PCI device's PME# function
1049 * @dev: PCI device to handle.
1050 * @enable: 'true' to enable PME# generation; 'false' to disable it.
1052 * The caller must verify that the device is capable of generating PME# before
1053 * calling this function with @enable equal to 'true'.
1055 void pci_pme_active(struct pci_dev *dev, bool enable)
1062 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
1063 /* Clear PME_Status by writing 1 to it and enable PME# */
1064 pmcsr |= PCI_PM_CTRL_PME_STATUS | PCI_PM_CTRL_PME_ENABLE;
1066 pmcsr &= ~PCI_PM_CTRL_PME_ENABLE;
1068 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr);
1070 dev_printk(KERN_INFO, &dev->dev, "PME# %s\n",
1071 enable ? "enabled" : "disabled");
1075 * pci_enable_wake - enable PCI device as wakeup event source
1076 * @dev: PCI device affected
1077 * @state: PCI state from which device will issue wakeup events
1078 * @enable: True to enable event generation; false to disable
1080 * This enables the device as a wakeup event source, or disables it.
1081 * When such events involves platform-specific hooks, those hooks are
1082 * called automatically by this routine.
1084 * Devices with legacy power management (no standard PCI PM capabilities)
1085 * always require such platform hooks.
1088 * 0 is returned on success
1089 * -EINVAL is returned if device is not supposed to wake up the system
1090 * Error code depending on the platform is returned if both the platform and
1091 * the native mechanism fail to enable the generation of wake-up events
1093 int pci_enable_wake(struct pci_dev *dev, pci_power_t state, int enable)
1096 bool pme_done = false;
1098 if (enable && !device_may_wakeup(&dev->dev))
1102 * According to "PCI System Architecture" 4th ed. by Tom Shanley & Don
1103 * Anderson we should be doing PME# wake enable followed by ACPI wake
1104 * enable. To disable wake-up we call the platform first, for symmetry.
1107 if (!enable && platform_pci_can_wakeup(dev))
1108 error = platform_pci_sleep_wake(dev, false);
1110 if (!enable || pci_pme_capable(dev, state)) {
1111 pci_pme_active(dev, enable);
1115 if (enable && platform_pci_can_wakeup(dev))
1116 error = platform_pci_sleep_wake(dev, true);
1118 return pme_done ? 0 : error;
1122 * pci_wake_from_d3 - enable/disable device to wake up from D3_hot or D3_cold
1123 * @dev: PCI device to prepare
1124 * @enable: True to enable wake-up event generation; false to disable
1126 * Many drivers want the device to wake up the system from D3_hot or D3_cold
1127 * and this function allows them to set that up cleanly - pci_enable_wake()
1128 * should not be called twice in a row to enable wake-up due to PCI PM vs ACPI
1129 * ordering constraints.
1131 * This function only returns error code if the device is not capable of
1132 * generating PME# from both D3_hot and D3_cold, and the platform is unable to
1133 * enable wake-up power for it.
1135 int pci_wake_from_d3(struct pci_dev *dev, bool enable)
1137 return pci_pme_capable(dev, PCI_D3cold) ?
1138 pci_enable_wake(dev, PCI_D3cold, enable) :
1139 pci_enable_wake(dev, PCI_D3hot, enable);
1143 * pci_target_state - find an appropriate low power state for a given PCI dev
1146 * Use underlying platform code to find a supported low power state for @dev.
1147 * If the platform can't manage @dev, return the deepest state from which it
1148 * can generate wake events, based on any available PME info.
1150 pci_power_t pci_target_state(struct pci_dev *dev)
1152 pci_power_t target_state = PCI_D3hot;
1154 if (platform_pci_power_manageable(dev)) {
1156 * Call the platform to choose the target state of the device
1157 * and enable wake-up from this state if supported.
1159 pci_power_t state = platform_pci_choose_state(dev);
1162 case PCI_POWER_ERROR:
1167 if (pci_no_d1d2(dev))
1170 target_state = state;
1172 } else if (device_may_wakeup(&dev->dev)) {
1174 * Find the deepest state from which the device can generate
1175 * wake-up events, make it the target state and enable device
1179 return PCI_POWER_ERROR;
1181 if (dev->pme_support) {
1183 && !(dev->pme_support & (1 << target_state)))
1188 return target_state;
1192 * pci_prepare_to_sleep - prepare PCI device for system-wide transition into a sleep state
1193 * @dev: Device to handle.
1195 * Choose the power state appropriate for the device depending on whether
1196 * it can wake up the system and/or is power manageable by the platform
1197 * (PCI_D3hot is the default) and put the device into that state.
1199 int pci_prepare_to_sleep(struct pci_dev *dev)
1201 pci_power_t target_state = pci_target_state(dev);
1204 if (target_state == PCI_POWER_ERROR)
1207 pci_enable_wake(dev, target_state, true);
1209 error = pci_set_power_state(dev, target_state);
1212 pci_enable_wake(dev, target_state, false);
1218 * pci_back_from_sleep - turn PCI device on during system-wide transition into working state
1219 * @dev: Device to handle.
1221 * Disable device's sytem wake-up capability and put it into D0.
1223 int pci_back_from_sleep(struct pci_dev *dev)
1225 pci_enable_wake(dev, PCI_D0, false);
1226 return pci_set_power_state(dev, PCI_D0);
1230 * pci_pm_init - Initialize PM functions of given PCI device
1231 * @dev: PCI device to handle.
1233 void pci_pm_init(struct pci_dev *dev)
1240 /* find PCI PM capability in list */
1241 pm = pci_find_capability(dev, PCI_CAP_ID_PM);
1244 /* Check device's ability to generate PME# */
1245 pci_read_config_word(dev, pm + PCI_PM_PMC, &pmc);
1247 if ((pmc & PCI_PM_CAP_VER_MASK) > 3) {
1248 dev_err(&dev->dev, "unsupported PM cap regs version (%u)\n",
1249 pmc & PCI_PM_CAP_VER_MASK);
1255 dev->d1_support = false;
1256 dev->d2_support = false;
1257 if (!pci_no_d1d2(dev)) {
1258 if (pmc & PCI_PM_CAP_D1)
1259 dev->d1_support = true;
1260 if (pmc & PCI_PM_CAP_D2)
1261 dev->d2_support = true;
1263 if (dev->d1_support || dev->d2_support)
1264 dev_printk(KERN_DEBUG, &dev->dev, "supports%s%s\n",
1265 dev->d1_support ? " D1" : "",
1266 dev->d2_support ? " D2" : "");
1269 pmc &= PCI_PM_CAP_PME_MASK;
1271 dev_info(&dev->dev, "PME# supported from%s%s%s%s%s\n",
1272 (pmc & PCI_PM_CAP_PME_D0) ? " D0" : "",
1273 (pmc & PCI_PM_CAP_PME_D1) ? " D1" : "",
1274 (pmc & PCI_PM_CAP_PME_D2) ? " D2" : "",
1275 (pmc & PCI_PM_CAP_PME_D3) ? " D3hot" : "",
1276 (pmc & PCI_PM_CAP_PME_D3cold) ? " D3cold" : "");
1277 dev->pme_support = pmc >> PCI_PM_CAP_PME_SHIFT;
1279 * Make device's PM flags reflect the wake-up capability, but
1280 * let the user space enable it to wake up the system as needed.
1282 device_set_wakeup_capable(&dev->dev, true);
1283 device_set_wakeup_enable(&dev->dev, false);
1284 /* Disable the PME# generation functionality */
1285 pci_pme_active(dev, false);
1287 dev->pme_support = 0;
1292 * platform_pci_wakeup_init - init platform wakeup if present
1295 * Some devices don't have PCI PM caps but can still generate wakeup
1296 * events through platform methods (like ACPI events). If @dev supports
1297 * platform wakeup events, set the device flag to indicate as much. This
1298 * may be redundant if the device also supports PCI PM caps, but double
1299 * initialization should be safe in that case.
1301 void platform_pci_wakeup_init(struct pci_dev *dev)
1303 if (!platform_pci_can_wakeup(dev))
1306 device_set_wakeup_capable(&dev->dev, true);
1307 device_set_wakeup_enable(&dev->dev, false);
1308 platform_pci_sleep_wake(dev, false);
1312 * pci_add_save_buffer - allocate buffer for saving given capability registers
1313 * @dev: the PCI device
1314 * @cap: the capability to allocate the buffer for
1315 * @size: requested size of the buffer
1317 static int pci_add_cap_save_buffer(
1318 struct pci_dev *dev, char cap, unsigned int size)
1321 struct pci_cap_saved_state *save_state;
1323 pos = pci_find_capability(dev, cap);
1327 save_state = kzalloc(sizeof(*save_state) + size, GFP_KERNEL);
1331 save_state->cap_nr = cap;
1332 pci_add_saved_cap(dev, save_state);
1338 * pci_allocate_cap_save_buffers - allocate buffers for saving capabilities
1339 * @dev: the PCI device
1341 void pci_allocate_cap_save_buffers(struct pci_dev *dev)
1345 error = pci_add_cap_save_buffer(dev, PCI_CAP_ID_EXP, 4 * sizeof(u16));
1348 "unable to preallocate PCI Express save buffer\n");
1350 error = pci_add_cap_save_buffer(dev, PCI_CAP_ID_PCIX, sizeof(u16));
1353 "unable to preallocate PCI-X save buffer\n");
1357 * pci_enable_ari - enable ARI forwarding if hardware support it
1358 * @dev: the PCI device
1360 void pci_enable_ari(struct pci_dev *dev)
1365 struct pci_dev *bridge;
1367 if (!dev->is_pcie || dev->devfn)
1370 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ARI);
1374 bridge = dev->bus->self;
1375 if (!bridge || !bridge->is_pcie)
1378 pos = pci_find_capability(bridge, PCI_CAP_ID_EXP);
1382 pci_read_config_dword(bridge, pos + PCI_EXP_DEVCAP2, &cap);
1383 if (!(cap & PCI_EXP_DEVCAP2_ARI))
1386 pci_read_config_word(bridge, pos + PCI_EXP_DEVCTL2, &ctrl);
1387 ctrl |= PCI_EXP_DEVCTL2_ARI;
1388 pci_write_config_word(bridge, pos + PCI_EXP_DEVCTL2, ctrl);
1390 bridge->ari_enabled = 1;
1394 * pci_swizzle_interrupt_pin - swizzle INTx for device behind bridge
1395 * @dev: the PCI device
1396 * @pin: the INTx pin (1=INTA, 2=INTB, 3=INTD, 4=INTD)
1398 * Perform INTx swizzling for a device behind one level of bridge. This is
1399 * required by section 9.1 of the PCI-to-PCI bridge specification for devices
1400 * behind bridges on add-in cards.
1402 u8 pci_swizzle_interrupt_pin(struct pci_dev *dev, u8 pin)
1404 return (((pin - 1) + PCI_SLOT(dev->devfn)) % 4) + 1;
1408 pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge)
1416 while (dev->bus->self) {
1417 pin = pci_swizzle_interrupt_pin(dev, pin);
1418 dev = dev->bus->self;
1425 * pci_common_swizzle - swizzle INTx all the way to root bridge
1426 * @dev: the PCI device
1427 * @pinp: pointer to the INTx pin value (1=INTA, 2=INTB, 3=INTD, 4=INTD)
1429 * Perform INTx swizzling for a device. This traverses through all PCI-to-PCI
1430 * bridges all the way up to a PCI root bus.
1432 u8 pci_common_swizzle(struct pci_dev *dev, u8 *pinp)
1436 while (dev->bus->self) {
1437 pin = pci_swizzle_interrupt_pin(dev, pin);
1438 dev = dev->bus->self;
1441 return PCI_SLOT(dev->devfn);
1445 * pci_release_region - Release a PCI bar
1446 * @pdev: PCI device whose resources were previously reserved by pci_request_region
1447 * @bar: BAR to release
1449 * Releases the PCI I/O and memory resources previously reserved by a
1450 * successful call to pci_request_region. Call this function only
1451 * after all use of the PCI regions has ceased.
1453 void pci_release_region(struct pci_dev *pdev, int bar)
1455 struct pci_devres *dr;
1457 if (pci_resource_len(pdev, bar) == 0)
1459 if (pci_resource_flags(pdev, bar) & IORESOURCE_IO)
1460 release_region(pci_resource_start(pdev, bar),
1461 pci_resource_len(pdev, bar));
1462 else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM)
1463 release_mem_region(pci_resource_start(pdev, bar),
1464 pci_resource_len(pdev, bar));
1466 dr = find_pci_dr(pdev);
1468 dr->region_mask &= ~(1 << bar);
1472 * pci_request_region - Reserved PCI I/O and memory resource
1473 * @pdev: PCI device whose resources are to be reserved
1474 * @bar: BAR to be reserved
1475 * @res_name: Name to be associated with resource.
1477 * Mark the PCI region associated with PCI device @pdev BR @bar as
1478 * being reserved by owner @res_name. Do not access any
1479 * address inside the PCI regions unless this call returns
1482 * Returns 0 on success, or %EBUSY on error. A warning
1483 * message is also printed on failure.
1485 static int __pci_request_region(struct pci_dev *pdev, int bar, const char *res_name,
1488 struct pci_devres *dr;
1490 if (pci_resource_len(pdev, bar) == 0)
1493 if (pci_resource_flags(pdev, bar) & IORESOURCE_IO) {
1494 if (!request_region(pci_resource_start(pdev, bar),
1495 pci_resource_len(pdev, bar), res_name))
1498 else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM) {
1499 if (!__request_mem_region(pci_resource_start(pdev, bar),
1500 pci_resource_len(pdev, bar), res_name,
1505 dr = find_pci_dr(pdev);
1507 dr->region_mask |= 1 << bar;
1512 dev_warn(&pdev->dev, "BAR %d: can't reserve %s region %pR\n",
1514 pci_resource_flags(pdev, bar) & IORESOURCE_IO ? "I/O" : "mem",
1515 &pdev->resource[bar]);
1520 * pci_request_region - Reserved PCI I/O and memory resource
1521 * @pdev: PCI device whose resources are to be reserved
1522 * @bar: BAR to be reserved
1523 * @res_name: Name to be associated with resource.
1525 * Mark the PCI region associated with PCI device @pdev BR @bar as
1526 * being reserved by owner @res_name. Do not access any
1527 * address inside the PCI regions unless this call returns
1530 * Returns 0 on success, or %EBUSY on error. A warning
1531 * message is also printed on failure.
1533 int pci_request_region(struct pci_dev *pdev, int bar, const char *res_name)
1535 return __pci_request_region(pdev, bar, res_name, 0);
1539 * pci_request_region_exclusive - Reserved PCI I/O and memory resource
1540 * @pdev: PCI device whose resources are to be reserved
1541 * @bar: BAR to be reserved
1542 * @res_name: Name to be associated with resource.
1544 * Mark the PCI region associated with PCI device @pdev BR @bar as
1545 * being reserved by owner @res_name. Do not access any
1546 * address inside the PCI regions unless this call returns
1549 * Returns 0 on success, or %EBUSY on error. A warning
1550 * message is also printed on failure.
1552 * The key difference that _exclusive makes it that userspace is
1553 * explicitly not allowed to map the resource via /dev/mem or
1556 int pci_request_region_exclusive(struct pci_dev *pdev, int bar, const char *res_name)
1558 return __pci_request_region(pdev, bar, res_name, IORESOURCE_EXCLUSIVE);
1561 * pci_release_selected_regions - Release selected PCI I/O and memory resources
1562 * @pdev: PCI device whose resources were previously reserved
1563 * @bars: Bitmask of BARs to be released
1565 * Release selected PCI I/O and memory resources previously reserved.
1566 * Call this function only after all use of the PCI regions has ceased.
1568 void pci_release_selected_regions(struct pci_dev *pdev, int bars)
1572 for (i = 0; i < 6; i++)
1573 if (bars & (1 << i))
1574 pci_release_region(pdev, i);
1577 int __pci_request_selected_regions(struct pci_dev *pdev, int bars,
1578 const char *res_name, int excl)
1582 for (i = 0; i < 6; i++)
1583 if (bars & (1 << i))
1584 if (__pci_request_region(pdev, i, res_name, excl))
1590 if (bars & (1 << i))
1591 pci_release_region(pdev, i);
1598 * pci_request_selected_regions - Reserve selected PCI I/O and memory resources
1599 * @pdev: PCI device whose resources are to be reserved
1600 * @bars: Bitmask of BARs to be requested
1601 * @res_name: Name to be associated with resource
1603 int pci_request_selected_regions(struct pci_dev *pdev, int bars,
1604 const char *res_name)
1606 return __pci_request_selected_regions(pdev, bars, res_name, 0);
1609 int pci_request_selected_regions_exclusive(struct pci_dev *pdev,
1610 int bars, const char *res_name)
1612 return __pci_request_selected_regions(pdev, bars, res_name,
1613 IORESOURCE_EXCLUSIVE);
1617 * pci_release_regions - Release reserved PCI I/O and memory resources
1618 * @pdev: PCI device whose resources were previously reserved by pci_request_regions
1620 * Releases all PCI I/O and memory resources previously reserved by a
1621 * successful call to pci_request_regions. Call this function only
1622 * after all use of the PCI regions has ceased.
1625 void pci_release_regions(struct pci_dev *pdev)
1627 pci_release_selected_regions(pdev, (1 << 6) - 1);
1631 * pci_request_regions - Reserved PCI I/O and memory resources
1632 * @pdev: PCI device whose resources are to be reserved
1633 * @res_name: Name to be associated with resource.
1635 * Mark all PCI regions associated with PCI device @pdev as
1636 * being reserved by owner @res_name. Do not access any
1637 * address inside the PCI regions unless this call returns
1640 * Returns 0 on success, or %EBUSY on error. A warning
1641 * message is also printed on failure.
1643 int pci_request_regions(struct pci_dev *pdev, const char *res_name)
1645 return pci_request_selected_regions(pdev, ((1 << 6) - 1), res_name);
1649 * pci_request_regions_exclusive - Reserved PCI I/O and memory resources
1650 * @pdev: PCI device whose resources are to be reserved
1651 * @res_name: Name to be associated with resource.
1653 * Mark all PCI regions associated with PCI device @pdev as
1654 * being reserved by owner @res_name. Do not access any
1655 * address inside the PCI regions unless this call returns
1658 * pci_request_regions_exclusive() will mark the region so that
1659 * /dev/mem and the sysfs MMIO access will not be allowed.
1661 * Returns 0 on success, or %EBUSY on error. A warning
1662 * message is also printed on failure.
1664 int pci_request_regions_exclusive(struct pci_dev *pdev, const char *res_name)
1666 return pci_request_selected_regions_exclusive(pdev,
1667 ((1 << 6) - 1), res_name);
1672 * pci_set_master - enables bus-mastering for device dev
1673 * @dev: the PCI device to enable
1675 * Enables bus-mastering on the device and calls pcibios_set_master()
1676 * to do the needed arch specific settings.
1679 pci_set_master(struct pci_dev *dev)
1683 pci_read_config_word(dev, PCI_COMMAND, &cmd);
1684 if (! (cmd & PCI_COMMAND_MASTER)) {
1685 dev_dbg(&dev->dev, "enabling bus mastering\n");
1686 cmd |= PCI_COMMAND_MASTER;
1687 pci_write_config_word(dev, PCI_COMMAND, cmd);
1689 dev->is_busmaster = 1;
1690 pcibios_set_master(dev);
1693 #ifdef PCI_DISABLE_MWI
1694 int pci_set_mwi(struct pci_dev *dev)
1699 int pci_try_set_mwi(struct pci_dev *dev)
1704 void pci_clear_mwi(struct pci_dev *dev)
1710 #ifndef PCI_CACHE_LINE_BYTES
1711 #define PCI_CACHE_LINE_BYTES L1_CACHE_BYTES
1714 /* This can be overridden by arch code. */
1715 /* Don't forget this is measured in 32-bit words, not bytes */
1716 u8 pci_cache_line_size = PCI_CACHE_LINE_BYTES / 4;
1719 * pci_set_cacheline_size - ensure the CACHE_LINE_SIZE register is programmed
1720 * @dev: the PCI device for which MWI is to be enabled
1722 * Helper function for pci_set_mwi.
1723 * Originally copied from drivers/net/acenic.c.
1724 * Copyright 1998-2001 by Jes Sorensen, <jes@trained-monkey.org>.
1726 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
1729 pci_set_cacheline_size(struct pci_dev *dev)
1733 if (!pci_cache_line_size)
1734 return -EINVAL; /* The system doesn't support MWI. */
1736 /* Validate current setting: the PCI_CACHE_LINE_SIZE must be
1737 equal to or multiple of the right value. */
1738 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size);
1739 if (cacheline_size >= pci_cache_line_size &&
1740 (cacheline_size % pci_cache_line_size) == 0)
1743 /* Write the correct value. */
1744 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, pci_cache_line_size);
1746 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size);
1747 if (cacheline_size == pci_cache_line_size)
1750 dev_printk(KERN_DEBUG, &dev->dev, "cache line size of %d is not "
1751 "supported\n", pci_cache_line_size << 2);
1757 * pci_set_mwi - enables memory-write-invalidate PCI transaction
1758 * @dev: the PCI device for which MWI is enabled
1760 * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND.
1762 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
1765 pci_set_mwi(struct pci_dev *dev)
1770 rc = pci_set_cacheline_size(dev);
1774 pci_read_config_word(dev, PCI_COMMAND, &cmd);
1775 if (! (cmd & PCI_COMMAND_INVALIDATE)) {
1776 dev_dbg(&dev->dev, "enabling Mem-Wr-Inval\n");
1777 cmd |= PCI_COMMAND_INVALIDATE;
1778 pci_write_config_word(dev, PCI_COMMAND, cmd);
1785 * pci_try_set_mwi - enables memory-write-invalidate PCI transaction
1786 * @dev: the PCI device for which MWI is enabled
1788 * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND.
1789 * Callers are not required to check the return value.
1791 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
1793 int pci_try_set_mwi(struct pci_dev *dev)
1795 int rc = pci_set_mwi(dev);
1800 * pci_clear_mwi - disables Memory-Write-Invalidate for device dev
1801 * @dev: the PCI device to disable
1803 * Disables PCI Memory-Write-Invalidate transaction on the device
1806 pci_clear_mwi(struct pci_dev *dev)
1810 pci_read_config_word(dev, PCI_COMMAND, &cmd);
1811 if (cmd & PCI_COMMAND_INVALIDATE) {
1812 cmd &= ~PCI_COMMAND_INVALIDATE;
1813 pci_write_config_word(dev, PCI_COMMAND, cmd);
1816 #endif /* ! PCI_DISABLE_MWI */
1819 * pci_intx - enables/disables PCI INTx for device dev
1820 * @pdev: the PCI device to operate on
1821 * @enable: boolean: whether to enable or disable PCI INTx
1823 * Enables/disables PCI INTx for device dev
1826 pci_intx(struct pci_dev *pdev, int enable)
1828 u16 pci_command, new;
1830 pci_read_config_word(pdev, PCI_COMMAND, &pci_command);
1833 new = pci_command & ~PCI_COMMAND_INTX_DISABLE;
1835 new = pci_command | PCI_COMMAND_INTX_DISABLE;
1838 if (new != pci_command) {
1839 struct pci_devres *dr;
1841 pci_write_config_word(pdev, PCI_COMMAND, new);
1843 dr = find_pci_dr(pdev);
1844 if (dr && !dr->restore_intx) {
1845 dr->restore_intx = 1;
1846 dr->orig_intx = !enable;
1852 * pci_msi_off - disables any msi or msix capabilities
1853 * @dev: the PCI device to operate on
1855 * If you want to use msi see pci_enable_msi and friends.
1856 * This is a lower level primitive that allows us to disable
1857 * msi operation at the device level.
1859 void pci_msi_off(struct pci_dev *dev)
1864 pos = pci_find_capability(dev, PCI_CAP_ID_MSI);
1866 pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &control);
1867 control &= ~PCI_MSI_FLAGS_ENABLE;
1868 pci_write_config_word(dev, pos + PCI_MSI_FLAGS, control);
1870 pos = pci_find_capability(dev, PCI_CAP_ID_MSIX);
1872 pci_read_config_word(dev, pos + PCI_MSIX_FLAGS, &control);
1873 control &= ~PCI_MSIX_FLAGS_ENABLE;
1874 pci_write_config_word(dev, pos + PCI_MSIX_FLAGS, control);
1878 #ifndef HAVE_ARCH_PCI_SET_DMA_MASK
1880 * These can be overridden by arch-specific implementations
1883 pci_set_dma_mask(struct pci_dev *dev, u64 mask)
1885 if (!pci_dma_supported(dev, mask))
1888 dev->dma_mask = mask;
1894 pci_set_consistent_dma_mask(struct pci_dev *dev, u64 mask)
1896 if (!pci_dma_supported(dev, mask))
1899 dev->dev.coherent_dma_mask = mask;
1905 #ifndef HAVE_ARCH_PCI_SET_DMA_MAX_SEGMENT_SIZE
1906 int pci_set_dma_max_seg_size(struct pci_dev *dev, unsigned int size)
1908 return dma_set_max_seg_size(&dev->dev, size);
1910 EXPORT_SYMBOL(pci_set_dma_max_seg_size);
1913 #ifndef HAVE_ARCH_PCI_SET_DMA_SEGMENT_BOUNDARY
1914 int pci_set_dma_seg_boundary(struct pci_dev *dev, unsigned long mask)
1916 return dma_set_seg_boundary(&dev->dev, mask);
1918 EXPORT_SYMBOL(pci_set_dma_seg_boundary);
1921 static int __pcie_flr(struct pci_dev *dev, int probe)
1925 int exppos = pci_find_capability(dev, PCI_CAP_ID_EXP);
1929 pci_read_config_dword(dev, exppos + PCI_EXP_DEVCAP, &cap);
1930 if (!(cap & PCI_EXP_DEVCAP_FLR))
1936 pci_block_user_cfg_access(dev);
1938 /* Wait for Transaction Pending bit clean */
1940 pci_read_config_word(dev, exppos + PCI_EXP_DEVSTA, &status);
1941 if (status & PCI_EXP_DEVSTA_TRPND) {
1942 dev_info(&dev->dev, "Busy after 100ms while trying to reset; "
1943 "sleeping for 1 second\n");
1945 pci_read_config_word(dev, exppos + PCI_EXP_DEVSTA, &status);
1946 if (status & PCI_EXP_DEVSTA_TRPND)
1947 dev_info(&dev->dev, "Still busy after 1s; "
1948 "proceeding with reset anyway\n");
1951 pci_write_config_word(dev, exppos + PCI_EXP_DEVCTL,
1952 PCI_EXP_DEVCTL_BCR_FLR);
1955 pci_unblock_user_cfg_access(dev);
1959 static int __pci_af_flr(struct pci_dev *dev, int probe)
1961 int cappos = pci_find_capability(dev, PCI_CAP_ID_AF);
1967 pci_read_config_byte(dev, cappos + PCI_AF_CAP, &cap);
1968 if (!(cap & PCI_AF_CAP_TP) || !(cap & PCI_AF_CAP_FLR))
1974 pci_block_user_cfg_access(dev);
1976 /* Wait for Transaction Pending bit clean */
1978 pci_read_config_byte(dev, cappos + PCI_AF_STATUS, &status);
1979 if (status & PCI_AF_STATUS_TP) {
1980 dev_info(&dev->dev, "Busy after 100ms while trying to"
1981 " reset; sleeping for 1 second\n");
1983 pci_read_config_byte(dev,
1984 cappos + PCI_AF_STATUS, &status);
1985 if (status & PCI_AF_STATUS_TP)
1986 dev_info(&dev->dev, "Still busy after 1s; "
1987 "proceeding with reset anyway\n");
1989 pci_write_config_byte(dev, cappos + PCI_AF_CTRL, PCI_AF_CTRL_FLR);
1992 pci_unblock_user_cfg_access(dev);
1996 static int __pci_reset_function(struct pci_dev *pdev, int probe)
2000 res = __pcie_flr(pdev, probe);
2004 res = __pci_af_flr(pdev, probe);
2012 * pci_execute_reset_function() - Reset a PCI device function
2013 * @dev: Device function to reset
2015 * Some devices allow an individual function to be reset without affecting
2016 * other functions in the same device. The PCI device must be responsive
2017 * to PCI config space in order to use this function.
2019 * The device function is presumed to be unused when this function is called.
2020 * Resetting the device will make the contents of PCI configuration space
2021 * random, so any caller of this must be prepared to reinitialise the
2022 * device including MSI, bus mastering, BARs, decoding IO and memory spaces,
2025 * Returns 0 if the device function was successfully reset or -ENOTTY if the
2026 * device doesn't support resetting a single function.
2028 int pci_execute_reset_function(struct pci_dev *dev)
2030 return __pci_reset_function(dev, 0);
2032 EXPORT_SYMBOL_GPL(pci_execute_reset_function);
2035 * pci_reset_function() - quiesce and reset a PCI device function
2036 * @dev: Device function to reset
2038 * Some devices allow an individual function to be reset without affecting
2039 * other functions in the same device. The PCI device must be responsive
2040 * to PCI config space in order to use this function.
2042 * This function does not just reset the PCI portion of a device, but
2043 * clears all the state associated with the device. This function differs
2044 * from pci_execute_reset_function in that it saves and restores device state
2047 * Returns 0 if the device function was successfully reset or -ENOTTY if the
2048 * device doesn't support resetting a single function.
2050 int pci_reset_function(struct pci_dev *dev)
2052 int r = __pci_reset_function(dev, 1);
2057 if (!dev->msi_enabled && !dev->msix_enabled && dev->irq != 0)
2058 disable_irq(dev->irq);
2059 pci_save_state(dev);
2061 pci_write_config_word(dev, PCI_COMMAND, PCI_COMMAND_INTX_DISABLE);
2063 r = pci_execute_reset_function(dev);
2065 pci_restore_state(dev);
2066 if (!dev->msi_enabled && !dev->msix_enabled && dev->irq != 0)
2067 enable_irq(dev->irq);
2071 EXPORT_SYMBOL_GPL(pci_reset_function);
2074 * pcix_get_max_mmrbc - get PCI-X maximum designed memory read byte count
2075 * @dev: PCI device to query
2077 * Returns mmrbc: maximum designed memory read count in bytes
2078 * or appropriate error value.
2080 int pcix_get_max_mmrbc(struct pci_dev *dev)
2085 cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
2089 err = pci_read_config_dword(dev, cap + PCI_X_STATUS, &stat);
2093 return (stat & PCI_X_STATUS_MAX_READ) >> 12;
2095 EXPORT_SYMBOL(pcix_get_max_mmrbc);
2098 * pcix_get_mmrbc - get PCI-X maximum memory read byte count
2099 * @dev: PCI device to query
2101 * Returns mmrbc: maximum memory read count in bytes
2102 * or appropriate error value.
2104 int pcix_get_mmrbc(struct pci_dev *dev)
2109 cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
2113 ret = pci_read_config_dword(dev, cap + PCI_X_CMD, &cmd);
2115 ret = 512 << ((cmd & PCI_X_CMD_MAX_READ) >> 2);
2119 EXPORT_SYMBOL(pcix_get_mmrbc);
2122 * pcix_set_mmrbc - set PCI-X maximum memory read byte count
2123 * @dev: PCI device to query
2124 * @mmrbc: maximum memory read count in bytes
2125 * valid values are 512, 1024, 2048, 4096
2127 * If possible sets maximum memory read byte count, some bridges have erratas
2128 * that prevent this.
2130 int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc)
2132 int cap, err = -EINVAL;
2133 u32 stat, cmd, v, o;
2135 if (mmrbc < 512 || mmrbc > 4096 || !is_power_of_2(mmrbc))
2138 v = ffs(mmrbc) - 10;
2140 cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
2144 err = pci_read_config_dword(dev, cap + PCI_X_STATUS, &stat);
2148 if (v > (stat & PCI_X_STATUS_MAX_READ) >> 21)
2151 err = pci_read_config_dword(dev, cap + PCI_X_CMD, &cmd);
2155 o = (cmd & PCI_X_CMD_MAX_READ) >> 2;
2157 if (v > o && dev->bus &&
2158 (dev->bus->bus_flags & PCI_BUS_FLAGS_NO_MMRBC))
2161 cmd &= ~PCI_X_CMD_MAX_READ;
2163 err = pci_write_config_dword(dev, cap + PCI_X_CMD, cmd);
2168 EXPORT_SYMBOL(pcix_set_mmrbc);
2171 * pcie_get_readrq - get PCI Express read request size
2172 * @dev: PCI device to query
2174 * Returns maximum memory read request in bytes
2175 * or appropriate error value.
2177 int pcie_get_readrq(struct pci_dev *dev)
2182 cap = pci_find_capability(dev, PCI_CAP_ID_EXP);
2186 ret = pci_read_config_word(dev, cap + PCI_EXP_DEVCTL, &ctl);
2188 ret = 128 << ((ctl & PCI_EXP_DEVCTL_READRQ) >> 12);
2192 EXPORT_SYMBOL(pcie_get_readrq);
2195 * pcie_set_readrq - set PCI Express maximum memory read request
2196 * @dev: PCI device to query
2197 * @rq: maximum memory read count in bytes
2198 * valid values are 128, 256, 512, 1024, 2048, 4096
2200 * If possible sets maximum read byte count
2202 int pcie_set_readrq(struct pci_dev *dev, int rq)
2204 int cap, err = -EINVAL;
2207 if (rq < 128 || rq > 4096 || !is_power_of_2(rq))
2210 v = (ffs(rq) - 8) << 12;
2212 cap = pci_find_capability(dev, PCI_CAP_ID_EXP);
2216 err = pci_read_config_word(dev, cap + PCI_EXP_DEVCTL, &ctl);
2220 if ((ctl & PCI_EXP_DEVCTL_READRQ) != v) {
2221 ctl &= ~PCI_EXP_DEVCTL_READRQ;
2223 err = pci_write_config_dword(dev, cap + PCI_EXP_DEVCTL, ctl);
2229 EXPORT_SYMBOL(pcie_set_readrq);
2232 * pci_select_bars - Make BAR mask from the type of resource
2233 * @dev: the PCI device for which BAR mask is made
2234 * @flags: resource type mask to be selected
2236 * This helper routine makes bar mask from the type of resource.
2238 int pci_select_bars(struct pci_dev *dev, unsigned long flags)
2241 for (i = 0; i < PCI_NUM_RESOURCES; i++)
2242 if (pci_resource_flags(dev, i) & flags)
2248 * pci_resource_bar - get position of the BAR associated with a resource
2249 * @dev: the PCI device
2250 * @resno: the resource number
2251 * @type: the BAR type to be filled in
2253 * Returns BAR position in config space, or 0 if the BAR is invalid.
2255 int pci_resource_bar(struct pci_dev *dev, int resno, enum pci_bar_type *type)
2257 if (resno < PCI_ROM_RESOURCE) {
2258 *type = pci_bar_unknown;
2259 return PCI_BASE_ADDRESS_0 + 4 * resno;
2260 } else if (resno == PCI_ROM_RESOURCE) {
2261 *type = pci_bar_mem32;
2262 return dev->rom_base_reg;
2265 dev_err(&dev->dev, "BAR: invalid resource #%d\n", resno);
2269 static void __devinit pci_no_domains(void)
2271 #ifdef CONFIG_PCI_DOMAINS
2272 pci_domains_supported = 0;
2277 * pci_ext_cfg_enabled - can we access extended PCI config space?
2278 * @dev: The PCI device of the root bridge.
2280 * Returns 1 if we can access PCI extended config space (offsets
2281 * greater than 0xff). This is the default implementation. Architecture
2282 * implementations can override this.
2284 int __attribute__ ((weak)) pci_ext_cfg_avail(struct pci_dev *dev)
2289 static int __devinit pci_init(void)
2291 struct pci_dev *dev = NULL;
2293 while ((dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) {
2294 pci_fixup_device(pci_fixup_final, dev);
2300 static int __init pci_setup(char *str)
2303 char *k = strchr(str, ',');
2306 if (*str && (str = pcibios_setup(str)) && *str) {
2307 if (!strcmp(str, "nomsi")) {
2309 } else if (!strcmp(str, "noaer")) {
2311 } else if (!strcmp(str, "nodomains")) {
2313 } else if (!strncmp(str, "cbiosize=", 9)) {
2314 pci_cardbus_io_size = memparse(str + 9, &str);
2315 } else if (!strncmp(str, "cbmemsize=", 10)) {
2316 pci_cardbus_mem_size = memparse(str + 10, &str);
2318 printk(KERN_ERR "PCI: Unknown option `%s'\n",
2326 early_param("pci", pci_setup);
2328 device_initcall(pci_init);
2330 EXPORT_SYMBOL(pci_reenable_device);
2331 EXPORT_SYMBOL(pci_enable_device_io);
2332 EXPORT_SYMBOL(pci_enable_device_mem);
2333 EXPORT_SYMBOL(pci_enable_device);
2334 EXPORT_SYMBOL(pcim_enable_device);
2335 EXPORT_SYMBOL(pcim_pin_device);
2336 EXPORT_SYMBOL(pci_disable_device);
2337 EXPORT_SYMBOL(pci_find_capability);
2338 EXPORT_SYMBOL(pci_bus_find_capability);
2339 EXPORT_SYMBOL(pci_release_regions);
2340 EXPORT_SYMBOL(pci_request_regions);
2341 EXPORT_SYMBOL(pci_request_regions_exclusive);
2342 EXPORT_SYMBOL(pci_release_region);
2343 EXPORT_SYMBOL(pci_request_region);
2344 EXPORT_SYMBOL(pci_request_region_exclusive);
2345 EXPORT_SYMBOL(pci_release_selected_regions);
2346 EXPORT_SYMBOL(pci_request_selected_regions);
2347 EXPORT_SYMBOL(pci_request_selected_regions_exclusive);
2348 EXPORT_SYMBOL(pci_set_master);
2349 EXPORT_SYMBOL(pci_set_mwi);
2350 EXPORT_SYMBOL(pci_try_set_mwi);
2351 EXPORT_SYMBOL(pci_clear_mwi);
2352 EXPORT_SYMBOL_GPL(pci_intx);
2353 EXPORT_SYMBOL(pci_set_dma_mask);
2354 EXPORT_SYMBOL(pci_set_consistent_dma_mask);
2355 EXPORT_SYMBOL(pci_assign_resource);
2356 EXPORT_SYMBOL(pci_find_parent_resource);
2357 EXPORT_SYMBOL(pci_select_bars);
2359 EXPORT_SYMBOL(pci_set_power_state);
2360 EXPORT_SYMBOL(pci_save_state);
2361 EXPORT_SYMBOL(pci_restore_state);
2362 EXPORT_SYMBOL(pci_pme_capable);
2363 EXPORT_SYMBOL(pci_pme_active);
2364 EXPORT_SYMBOL(pci_enable_wake);
2365 EXPORT_SYMBOL(pci_wake_from_d3);
2366 EXPORT_SYMBOL(pci_target_state);
2367 EXPORT_SYMBOL(pci_prepare_to_sleep);
2368 EXPORT_SYMBOL(pci_back_from_sleep);
2369 EXPORT_SYMBOL_GPL(pci_set_pcie_reset_state);