2 * $Id: pci.c,v 1.91 1999/01/21 13:34:01 davem Exp $
4 * PCI Bus Services, see include/linux/pci.h for further explanation.
6 * Copyright 1993 -- 1997 Drew Eckhardt, Frederic Potter,
9 * Copyright 1997 -- 2000 Martin Mares <mj@ucw.cz>
12 #include <linux/kernel.h>
13 #include <linux/delay.h>
14 #include <linux/init.h>
15 #include <linux/pci.h>
16 #include <linux/module.h>
17 #include <linux/spinlock.h>
18 #include <linux/string.h>
19 #include <asm/dma.h> /* isa_dma_bridge_buggy */
22 unsigned int pci_pm_d3_delay = 10;
25 * pci_bus_max_busnr - returns maximum PCI bus number of given bus' children
26 * @bus: pointer to PCI bus structure to search
28 * Given a PCI bus, returns the highest PCI bus number present in the set
29 * including the given PCI bus and its list of child PCI buses.
31 unsigned char __devinit
32 pci_bus_max_busnr(struct pci_bus* bus)
34 struct list_head *tmp;
37 max = bus->subordinate;
38 list_for_each(tmp, &bus->children) {
39 n = pci_bus_max_busnr(pci_bus_b(tmp));
45 EXPORT_SYMBOL_GPL(pci_bus_max_busnr);
49 * pci_max_busnr - returns maximum PCI bus number
51 * Returns the highest PCI bus number present in the system global list of
54 unsigned char __devinit
57 struct pci_bus *bus = NULL;
61 while ((bus = pci_find_next_bus(bus)) != NULL) {
62 n = pci_bus_max_busnr(bus);
71 #define PCI_FIND_CAP_TTL 48
73 static int __pci_find_next_cap_ttl(struct pci_bus *bus, unsigned int devfn,
74 u8 pos, int cap, int *ttl)
79 pci_bus_read_config_byte(bus, devfn, pos, &pos);
83 pci_bus_read_config_byte(bus, devfn, pos + PCI_CAP_LIST_ID,
89 pos += PCI_CAP_LIST_NEXT;
94 static int __pci_find_next_cap(struct pci_bus *bus, unsigned int devfn,
97 int ttl = PCI_FIND_CAP_TTL;
99 return __pci_find_next_cap_ttl(bus, devfn, pos, cap, &ttl);
102 int pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap)
104 return __pci_find_next_cap(dev->bus, dev->devfn,
105 pos + PCI_CAP_LIST_NEXT, cap);
107 EXPORT_SYMBOL_GPL(pci_find_next_capability);
109 static int __pci_bus_find_cap_start(struct pci_bus *bus,
110 unsigned int devfn, u8 hdr_type)
114 pci_bus_read_config_word(bus, devfn, PCI_STATUS, &status);
115 if (!(status & PCI_STATUS_CAP_LIST))
119 case PCI_HEADER_TYPE_NORMAL:
120 case PCI_HEADER_TYPE_BRIDGE:
121 return PCI_CAPABILITY_LIST;
122 case PCI_HEADER_TYPE_CARDBUS:
123 return PCI_CB_CAPABILITY_LIST;
132 * pci_find_capability - query for devices' capabilities
133 * @dev: PCI device to query
134 * @cap: capability code
136 * Tell if a device supports a given PCI capability.
137 * Returns the address of the requested capability structure within the
138 * device's PCI configuration space or 0 in case the device does not
139 * support it. Possible values for @cap:
141 * %PCI_CAP_ID_PM Power Management
142 * %PCI_CAP_ID_AGP Accelerated Graphics Port
143 * %PCI_CAP_ID_VPD Vital Product Data
144 * %PCI_CAP_ID_SLOTID Slot Identification
145 * %PCI_CAP_ID_MSI Message Signalled Interrupts
146 * %PCI_CAP_ID_CHSWP CompactPCI HotSwap
147 * %PCI_CAP_ID_PCIX PCI-X
148 * %PCI_CAP_ID_EXP PCI Express
150 int pci_find_capability(struct pci_dev *dev, int cap)
154 pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type);
156 pos = __pci_find_next_cap(dev->bus, dev->devfn, pos, cap);
162 * pci_bus_find_capability - query for devices' capabilities
163 * @bus: the PCI bus to query
164 * @devfn: PCI device to query
165 * @cap: capability code
167 * Like pci_find_capability() but works for pci devices that do not have a
168 * pci_dev structure set up yet.
170 * Returns the address of the requested capability structure within the
171 * device's PCI configuration space or 0 in case the device does not
174 int pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap)
179 pci_bus_read_config_byte(bus, devfn, PCI_HEADER_TYPE, &hdr_type);
181 pos = __pci_bus_find_cap_start(bus, devfn, hdr_type & 0x7f);
183 pos = __pci_find_next_cap(bus, devfn, pos, cap);
189 * pci_find_ext_capability - Find an extended capability
190 * @dev: PCI device to query
191 * @cap: capability code
193 * Returns the address of the requested extended capability structure
194 * within the device's PCI configuration space or 0 if the device does
195 * not support it. Possible values for @cap:
197 * %PCI_EXT_CAP_ID_ERR Advanced Error Reporting
198 * %PCI_EXT_CAP_ID_VC Virtual Channel
199 * %PCI_EXT_CAP_ID_DSN Device Serial Number
200 * %PCI_EXT_CAP_ID_PWR Power Budgeting
202 int pci_find_ext_capability(struct pci_dev *dev, int cap)
205 int ttl = 480; /* 3840 bytes, minimum 8 bytes per capability */
208 if (dev->cfg_size <= 256)
211 if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL)
215 * If we have no capabilities, this is indicated by cap ID,
216 * cap version and next pointer all being 0.
222 if (PCI_EXT_CAP_ID(header) == cap)
225 pos = PCI_EXT_CAP_NEXT(header);
229 if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL)
235 EXPORT_SYMBOL_GPL(pci_find_ext_capability);
237 static int __pci_find_next_ht_cap(struct pci_dev *dev, int pos, int ht_cap)
239 int rc, ttl = PCI_FIND_CAP_TTL;
242 if (ht_cap == HT_CAPTYPE_SLAVE || ht_cap == HT_CAPTYPE_HOST)
243 mask = HT_3BIT_CAP_MASK;
245 mask = HT_5BIT_CAP_MASK;
247 pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn, pos,
248 PCI_CAP_ID_HT, &ttl);
250 rc = pci_read_config_byte(dev, pos + 3, &cap);
251 if (rc != PCIBIOS_SUCCESSFUL)
254 if ((cap & mask) == ht_cap)
257 pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn, pos,
258 PCI_CAP_ID_HT, &ttl);
264 * pci_find_next_ht_capability - query a device's Hypertransport capabilities
265 * @dev: PCI device to query
266 * @pos: Position from which to continue searching
267 * @ht_cap: Hypertransport capability code
269 * To be used in conjunction with pci_find_ht_capability() to search for
270 * all capabilities matching @ht_cap. @pos should always be a value returned
271 * from pci_find_ht_capability().
273 * NB. To be 100% safe against broken PCI devices, the caller should take
274 * steps to avoid an infinite loop.
276 int pci_find_next_ht_capability(struct pci_dev *dev, int pos, int ht_cap)
278 return __pci_find_next_ht_cap(dev, pos + PCI_CAP_LIST_NEXT, ht_cap);
280 EXPORT_SYMBOL_GPL(pci_find_next_ht_capability);
283 * pci_find_ht_capability - query a device's Hypertransport capabilities
284 * @dev: PCI device to query
285 * @ht_cap: Hypertransport capability code
287 * Tell if a device supports a given Hypertransport capability.
288 * Returns an address within the device's PCI configuration space
289 * or 0 in case the device does not support the request capability.
290 * The address points to the PCI capability, of type PCI_CAP_ID_HT,
291 * which has a Hypertransport capability matching @ht_cap.
293 int pci_find_ht_capability(struct pci_dev *dev, int ht_cap)
297 pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type);
299 pos = __pci_find_next_ht_cap(dev, pos, ht_cap);
303 EXPORT_SYMBOL_GPL(pci_find_ht_capability);
306 * pci_find_parent_resource - return resource region of parent bus of given region
307 * @dev: PCI device structure contains resources to be searched
308 * @res: child resource record for which parent is sought
310 * For given resource region of given device, return the resource
311 * region of parent bus the given region is contained in or where
312 * it should be allocated from.
315 pci_find_parent_resource(const struct pci_dev *dev, struct resource *res)
317 const struct pci_bus *bus = dev->bus;
319 struct resource *best = NULL;
321 for(i = 0; i < PCI_BUS_NUM_RESOURCES; i++) {
322 struct resource *r = bus->resource[i];
325 if (res->start && !(res->start >= r->start && res->end <= r->end))
326 continue; /* Not contained */
327 if ((res->flags ^ r->flags) & (IORESOURCE_IO | IORESOURCE_MEM))
328 continue; /* Wrong type */
329 if (!((res->flags ^ r->flags) & IORESOURCE_PREFETCH))
330 return r; /* Exact match */
331 if ((res->flags & IORESOURCE_PREFETCH) && !(r->flags & IORESOURCE_PREFETCH))
332 best = r; /* Approximating prefetchable by non-prefetchable */
338 * pci_restore_bars - restore a devices BAR values (e.g. after wake-up)
339 * @dev: PCI device to have its BARs restored
341 * Restore the BAR values for a given device, so as to make it
342 * accessible by its driver.
345 pci_restore_bars(struct pci_dev *dev)
349 switch (dev->hdr_type) {
350 case PCI_HEADER_TYPE_NORMAL:
353 case PCI_HEADER_TYPE_BRIDGE:
356 case PCI_HEADER_TYPE_CARDBUS:
360 /* Should never get here, but just in case... */
364 for (i = 0; i < numres; i ++)
365 pci_update_resource(dev, &dev->resource[i], i);
368 int (*platform_pci_set_power_state)(struct pci_dev *dev, pci_power_t t);
371 * pci_set_power_state - Set the power state of a PCI device
372 * @dev: PCI device to be suspended
373 * @state: PCI power state (D0, D1, D2, D3hot, D3cold) we're entering
375 * Transition a device to a new power state, using the Power Management
376 * Capabilities in the device's config space.
379 * -EINVAL if trying to enter a lower state than we're already in.
380 * 0 if we're already in the requested state.
381 * -EIO if device does not support PCI PM.
382 * 0 if we can successfully change the power state.
385 pci_set_power_state(struct pci_dev *dev, pci_power_t state)
387 int pm, need_restore = 0;
390 /* bound the state we're entering */
391 if (state > PCI_D3hot)
394 /* Validate current state:
395 * Can enter D0 from any state, but if we can only go deeper
396 * to sleep if we're already in a low power state
398 if (state != PCI_D0 && dev->current_state > state) {
399 printk(KERN_ERR "%s(): %s: state=%d, current state=%d\n",
400 __FUNCTION__, pci_name(dev), state, dev->current_state);
402 } else if (dev->current_state == state)
403 return 0; /* we're already there */
406 * If the device or the parent bridge can't support PCI PM, ignore
407 * the request if we're doing anything besides putting it into D0
408 * (which would only happen on boot).
410 if ((state == PCI_D1 || state == PCI_D2) && pci_no_d1d2(dev))
413 /* find PCI PM capability in list */
414 pm = pci_find_capability(dev, PCI_CAP_ID_PM);
416 /* abort if the device doesn't support PM capabilities */
420 pci_read_config_word(dev,pm + PCI_PM_PMC,&pmc);
421 if ((pmc & PCI_PM_CAP_VER_MASK) > 3) {
423 "PCI: %s has unsupported PM cap regs version (%u)\n",
424 pci_name(dev), pmc & PCI_PM_CAP_VER_MASK);
428 /* check if this device supports the desired state */
429 if (state == PCI_D1 && !(pmc & PCI_PM_CAP_D1))
431 else if (state == PCI_D2 && !(pmc & PCI_PM_CAP_D2))
434 pci_read_config_word(dev, pm + PCI_PM_CTRL, &pmcsr);
436 /* If we're (effectively) in D3, force entire word to 0.
437 * This doesn't affect PME_Status, disables PME_En, and
438 * sets PowerState to 0.
440 switch (dev->current_state) {
444 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
447 case PCI_UNKNOWN: /* Boot-up */
448 if ((pmcsr & PCI_PM_CTRL_STATE_MASK) == PCI_D3hot
449 && !(pmcsr & PCI_PM_CTRL_NO_SOFT_RESET))
451 /* Fall-through: force to D0 */
457 /* enter specified state */
458 pci_write_config_word(dev, pm + PCI_PM_CTRL, pmcsr);
460 /* Mandatory power management transition delays */
461 /* see PCI PM 1.1 5.6.1 table 18 */
462 if (state == PCI_D3hot || dev->current_state == PCI_D3hot)
463 msleep(pci_pm_d3_delay);
464 else if (state == PCI_D2 || dev->current_state == PCI_D2)
468 * Give firmware a chance to be called, such as ACPI _PRx, _PSx
469 * Firmware method after native method ?
471 if (platform_pci_set_power_state)
472 platform_pci_set_power_state(dev, state);
474 dev->current_state = state;
476 /* According to section 5.4.1 of the "PCI BUS POWER MANAGEMENT
477 * INTERFACE SPECIFICATION, REV. 1.2", a device transitioning
478 * from D3hot to D0 _may_ perform an internal reset, thereby
479 * going to "D0 Uninitialized" rather than "D0 Initialized".
480 * For example, at least some versions of the 3c905B and the
481 * 3c556B exhibit this behaviour.
483 * At least some laptop BIOSen (e.g. the Thinkpad T21) leave
484 * devices in a D3hot state at boot. Consequently, we need to
485 * restore at least the BARs so that the device will be
486 * accessible to its driver.
489 pci_restore_bars(dev);
494 int (*platform_pci_choose_state)(struct pci_dev *dev, pm_message_t state);
497 * pci_choose_state - Choose the power state of a PCI device
498 * @dev: PCI device to be suspended
499 * @state: target sleep state for the whole system. This is the value
500 * that is passed to suspend() function.
502 * Returns PCI power state suitable for given device and given system
506 pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state)
510 if (!pci_find_capability(dev, PCI_CAP_ID_PM))
513 if (platform_pci_choose_state) {
514 ret = platform_pci_choose_state(dev, state);
519 switch (state.event) {
522 case PM_EVENT_FREEZE:
523 case PM_EVENT_PRETHAW:
524 /* REVISIT both freeze and pre-thaw "should" use D0 */
525 case PM_EVENT_SUSPEND:
528 printk("Unrecognized suspend event %d\n", state.event);
534 EXPORT_SYMBOL(pci_choose_state);
536 static int pci_save_pcie_state(struct pci_dev *dev)
539 struct pci_cap_saved_state *save_state;
542 pos = pci_find_capability(dev, PCI_CAP_ID_EXP);
546 save_state = kzalloc(sizeof(*save_state) + sizeof(u16) * 4, GFP_KERNEL);
548 dev_err(&dev->dev, "Out of memory in pci_save_pcie_state\n");
551 cap = (u16 *)&save_state->data[0];
553 pci_read_config_word(dev, pos + PCI_EXP_DEVCTL, &cap[i++]);
554 pci_read_config_word(dev, pos + PCI_EXP_LNKCTL, &cap[i++]);
555 pci_read_config_word(dev, pos + PCI_EXP_SLTCTL, &cap[i++]);
556 pci_read_config_word(dev, pos + PCI_EXP_RTCTL, &cap[i++]);
557 pci_add_saved_cap(dev, save_state);
561 static void pci_restore_pcie_state(struct pci_dev *dev)
564 struct pci_cap_saved_state *save_state;
567 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP);
568 pos = pci_find_capability(dev, PCI_CAP_ID_EXP);
569 if (!save_state || pos <= 0)
571 cap = (u16 *)&save_state->data[0];
573 pci_write_config_word(dev, pos + PCI_EXP_DEVCTL, cap[i++]);
574 pci_write_config_word(dev, pos + PCI_EXP_LNKCTL, cap[i++]);
575 pci_write_config_word(dev, pos + PCI_EXP_SLTCTL, cap[i++]);
576 pci_write_config_word(dev, pos + PCI_EXP_RTCTL, cap[i++]);
577 pci_remove_saved_cap(save_state);
582 static int pci_save_pcix_state(struct pci_dev *dev)
585 struct pci_cap_saved_state *save_state;
588 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
592 save_state = kzalloc(sizeof(*save_state) + sizeof(u16), GFP_KERNEL);
594 dev_err(&dev->dev, "Out of memory in pci_save_pcie_state\n");
597 cap = (u16 *)&save_state->data[0];
599 pci_read_config_word(dev, pos + PCI_X_CMD, &cap[i++]);
600 pci_add_saved_cap(dev, save_state);
604 static void pci_restore_pcix_state(struct pci_dev *dev)
607 struct pci_cap_saved_state *save_state;
610 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_PCIX);
611 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
612 if (!save_state || pos <= 0)
614 cap = (u16 *)&save_state->data[0];
616 pci_write_config_word(dev, pos + PCI_X_CMD, cap[i++]);
617 pci_remove_saved_cap(save_state);
623 * pci_save_state - save the PCI configuration space of a device before suspending
624 * @dev: - PCI device that we're dealing with
627 pci_save_state(struct pci_dev *dev)
630 /* XXX: 100% dword access ok here? */
631 for (i = 0; i < 16; i++)
632 pci_read_config_dword(dev, i * 4,&dev->saved_config_space[i]);
633 if ((i = pci_save_msi_state(dev)) != 0)
635 if ((i = pci_save_msix_state(dev)) != 0)
637 if ((i = pci_save_pcie_state(dev)) != 0)
639 if ((i = pci_save_pcix_state(dev)) != 0)
645 * pci_restore_state - Restore the saved state of a PCI device
646 * @dev: - PCI device that we're dealing with
649 pci_restore_state(struct pci_dev *dev)
654 /* PCI Express register must be restored first */
655 pci_restore_pcie_state(dev);
658 * The Base Address register should be programmed before the command
661 for (i = 15; i >= 0; i--) {
662 pci_read_config_dword(dev, i * 4, &val);
663 if (val != dev->saved_config_space[i]) {
664 printk(KERN_DEBUG "PM: Writing back config space on "
665 "device %s at offset %x (was %x, writing %x)\n",
667 val, (int)dev->saved_config_space[i]);
668 pci_write_config_dword(dev,i * 4,
669 dev->saved_config_space[i]);
672 pci_restore_pcix_state(dev);
673 pci_restore_msi_state(dev);
674 pci_restore_msix_state(dev);
679 * pci_enable_device_bars - Initialize some of a device for use
680 * @dev: PCI device to be initialized
681 * @bars: bitmask of BAR's that must be configured
683 * Initialize device before it's used by a driver. Ask low-level code
684 * to enable selected I/O and memory resources. Wake up the device if it
685 * was suspended. Beware, this function can fail.
689 pci_enable_device_bars(struct pci_dev *dev, int bars)
693 err = pci_set_power_state(dev, PCI_D0);
694 if (err < 0 && err != -EIO)
696 err = pcibios_enable_device(dev, bars);
703 * __pci_enable_device - Initialize device before it's used by a driver.
704 * @dev: PCI device to be initialized
706 * Initialize device before it's used by a driver. Ask low-level code
707 * to enable I/O and memory. Wake up the device if it was suspended.
708 * Beware, this function can fail.
710 * Note this function is a backend and is not supposed to be called by
711 * normal code, use pci_enable_device() instead.
714 __pci_enable_device(struct pci_dev *dev)
718 err = pci_enable_device_bars(dev, (1 << PCI_NUM_RESOURCES) - 1);
721 pci_fixup_device(pci_fixup_enable, dev);
726 * pci_enable_device - Initialize device before it's used by a driver.
727 * @dev: PCI device to be initialized
729 * Initialize device before it's used by a driver. Ask low-level code
730 * to enable I/O and memory. Wake up the device if it was suspended.
731 * Beware, this function can fail.
733 * Note we don't actually enable the device many times if we call
734 * this function repeatedly (we just increment the count).
736 int pci_enable_device(struct pci_dev *dev)
739 if (atomic_add_return(1, &dev->enable_cnt) > 1)
740 return 0; /* already enabled */
741 result = __pci_enable_device(dev);
743 atomic_dec(&dev->enable_cnt);
748 * pcibios_disable_device - disable arch specific PCI resources for device dev
749 * @dev: the PCI device to disable
751 * Disables architecture specific PCI resources for the device. This
752 * is the default implementation. Architecture implementations can
755 void __attribute__ ((weak)) pcibios_disable_device (struct pci_dev *dev) {}
758 * pci_disable_device - Disable PCI device after use
759 * @dev: PCI device to be disabled
761 * Signal to the system that the PCI device is not in use by the system
762 * anymore. This only involves disabling PCI bus-mastering, if active.
764 * Note we don't actually disable the device until all callers of
765 * pci_device_enable() have called pci_device_disable().
768 pci_disable_device(struct pci_dev *dev)
772 if (atomic_sub_return(1, &dev->enable_cnt) != 0)
775 if (dev->msi_enabled)
776 disable_msi_mode(dev, pci_find_capability(dev, PCI_CAP_ID_MSI),
778 if (dev->msix_enabled)
779 disable_msi_mode(dev, pci_find_capability(dev, PCI_CAP_ID_MSI),
782 pci_read_config_word(dev, PCI_COMMAND, &pci_command);
783 if (pci_command & PCI_COMMAND_MASTER) {
784 pci_command &= ~PCI_COMMAND_MASTER;
785 pci_write_config_word(dev, PCI_COMMAND, pci_command);
787 dev->is_busmaster = 0;
789 pcibios_disable_device(dev);
793 * pci_enable_wake - enable device to generate PME# when suspended
794 * @dev: - PCI device to operate on
795 * @state: - Current state of device.
796 * @enable: - Flag to enable or disable generation
798 * Set the bits in the device's PM Capabilities to generate PME# when
799 * the system is suspended.
801 * -EIO is returned if device doesn't have PM Capabilities.
802 * -EINVAL is returned if device supports it, but can't generate wake events.
803 * 0 if operation is successful.
806 int pci_enable_wake(struct pci_dev *dev, pci_power_t state, int enable)
811 /* find PCI PM capability in list */
812 pm = pci_find_capability(dev, PCI_CAP_ID_PM);
814 /* If device doesn't support PM Capabilities, but request is to disable
815 * wake events, it's a nop; otherwise fail */
817 return enable ? -EIO : 0;
819 /* Check device's ability to generate PME# */
820 pci_read_config_word(dev,pm+PCI_PM_PMC,&value);
822 value &= PCI_PM_CAP_PME_MASK;
823 value >>= ffs(PCI_PM_CAP_PME_MASK) - 1; /* First bit of mask */
825 /* Check if it can generate PME# from requested state. */
826 if (!value || !(value & (1 << state)))
827 return enable ? -EINVAL : 0;
829 pci_read_config_word(dev, pm + PCI_PM_CTRL, &value);
831 /* Clear PME_Status by writing 1 to it and enable PME# */
832 value |= PCI_PM_CTRL_PME_STATUS | PCI_PM_CTRL_PME_ENABLE;
835 value &= ~PCI_PM_CTRL_PME_ENABLE;
837 pci_write_config_word(dev, pm + PCI_PM_CTRL, value);
843 pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge)
851 while (dev->bus->self) {
852 pin = (pin + PCI_SLOT(dev->devfn)) % 4;
853 dev = dev->bus->self;
860 * pci_release_region - Release a PCI bar
861 * @pdev: PCI device whose resources were previously reserved by pci_request_region
862 * @bar: BAR to release
864 * Releases the PCI I/O and memory resources previously reserved by a
865 * successful call to pci_request_region. Call this function only
866 * after all use of the PCI regions has ceased.
868 void pci_release_region(struct pci_dev *pdev, int bar)
870 if (pci_resource_len(pdev, bar) == 0)
872 if (pci_resource_flags(pdev, bar) & IORESOURCE_IO)
873 release_region(pci_resource_start(pdev, bar),
874 pci_resource_len(pdev, bar));
875 else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM)
876 release_mem_region(pci_resource_start(pdev, bar),
877 pci_resource_len(pdev, bar));
881 * pci_request_region - Reserved PCI I/O and memory resource
882 * @pdev: PCI device whose resources are to be reserved
883 * @bar: BAR to be reserved
884 * @res_name: Name to be associated with resource.
886 * Mark the PCI region associated with PCI device @pdev BR @bar as
887 * being reserved by owner @res_name. Do not access any
888 * address inside the PCI regions unless this call returns
891 * Returns 0 on success, or %EBUSY on error. A warning
892 * message is also printed on failure.
894 int pci_request_region(struct pci_dev *pdev, int bar, const char *res_name)
896 if (pci_resource_len(pdev, bar) == 0)
899 if (pci_resource_flags(pdev, bar) & IORESOURCE_IO) {
900 if (!request_region(pci_resource_start(pdev, bar),
901 pci_resource_len(pdev, bar), res_name))
904 else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM) {
905 if (!request_mem_region(pci_resource_start(pdev, bar),
906 pci_resource_len(pdev, bar), res_name))
913 printk (KERN_WARNING "PCI: Unable to reserve %s region #%d:%llx@%llx "
915 pci_resource_flags(pdev, bar) & IORESOURCE_IO ? "I/O" : "mem",
916 bar + 1, /* PCI BAR # */
917 (unsigned long long)pci_resource_len(pdev, bar),
918 (unsigned long long)pci_resource_start(pdev, bar),
925 * pci_release_regions - Release reserved PCI I/O and memory resources
926 * @pdev: PCI device whose resources were previously reserved by pci_request_regions
928 * Releases all PCI I/O and memory resources previously reserved by a
929 * successful call to pci_request_regions. Call this function only
930 * after all use of the PCI regions has ceased.
933 void pci_release_regions(struct pci_dev *pdev)
937 for (i = 0; i < 6; i++)
938 pci_release_region(pdev, i);
942 * pci_request_regions - Reserved PCI I/O and memory resources
943 * @pdev: PCI device whose resources are to be reserved
944 * @res_name: Name to be associated with resource.
946 * Mark all PCI regions associated with PCI device @pdev as
947 * being reserved by owner @res_name. Do not access any
948 * address inside the PCI regions unless this call returns
951 * Returns 0 on success, or %EBUSY on error. A warning
952 * message is also printed on failure.
954 int pci_request_regions(struct pci_dev *pdev, const char *res_name)
958 for (i = 0; i < 6; i++)
959 if(pci_request_region(pdev, i, res_name))
965 pci_release_region(pdev, i);
971 * pci_set_master - enables bus-mastering for device dev
972 * @dev: the PCI device to enable
974 * Enables bus-mastering on the device and calls pcibios_set_master()
975 * to do the needed arch specific settings.
978 pci_set_master(struct pci_dev *dev)
982 pci_read_config_word(dev, PCI_COMMAND, &cmd);
983 if (! (cmd & PCI_COMMAND_MASTER)) {
984 pr_debug("PCI: Enabling bus mastering for device %s\n", pci_name(dev));
985 cmd |= PCI_COMMAND_MASTER;
986 pci_write_config_word(dev, PCI_COMMAND, cmd);
988 dev->is_busmaster = 1;
989 pcibios_set_master(dev);
992 #ifdef PCI_DISABLE_MWI
993 int pci_set_mwi(struct pci_dev *dev)
998 void pci_clear_mwi(struct pci_dev *dev)
1004 #ifndef PCI_CACHE_LINE_BYTES
1005 #define PCI_CACHE_LINE_BYTES L1_CACHE_BYTES
1008 /* This can be overridden by arch code. */
1009 /* Don't forget this is measured in 32-bit words, not bytes */
1010 u8 pci_cache_line_size = PCI_CACHE_LINE_BYTES / 4;
1013 * pci_set_cacheline_size - ensure the CACHE_LINE_SIZE register is programmed
1014 * @dev: the PCI device for which MWI is to be enabled
1016 * Helper function for pci_set_mwi.
1017 * Originally copied from drivers/net/acenic.c.
1018 * Copyright 1998-2001 by Jes Sorensen, <jes@trained-monkey.org>.
1020 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
1023 pci_set_cacheline_size(struct pci_dev *dev)
1027 if (!pci_cache_line_size)
1028 return -EINVAL; /* The system doesn't support MWI. */
1030 /* Validate current setting: the PCI_CACHE_LINE_SIZE must be
1031 equal to or multiple of the right value. */
1032 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size);
1033 if (cacheline_size >= pci_cache_line_size &&
1034 (cacheline_size % pci_cache_line_size) == 0)
1037 /* Write the correct value. */
1038 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, pci_cache_line_size);
1040 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size);
1041 if (cacheline_size == pci_cache_line_size)
1044 printk(KERN_DEBUG "PCI: cache line size of %d is not supported "
1045 "by device %s\n", pci_cache_line_size << 2, pci_name(dev));
1051 * pci_set_mwi - enables memory-write-invalidate PCI transaction
1052 * @dev: the PCI device for which MWI is enabled
1054 * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND,
1055 * and then calls @pcibios_set_mwi to do the needed arch specific
1056 * operations or a generic mwi-prep function.
1058 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
1061 pci_set_mwi(struct pci_dev *dev)
1066 rc = pci_set_cacheline_size(dev);
1070 pci_read_config_word(dev, PCI_COMMAND, &cmd);
1071 if (! (cmd & PCI_COMMAND_INVALIDATE)) {
1072 pr_debug("PCI: Enabling Mem-Wr-Inval for device %s\n", pci_name(dev));
1073 cmd |= PCI_COMMAND_INVALIDATE;
1074 pci_write_config_word(dev, PCI_COMMAND, cmd);
1081 * pci_clear_mwi - disables Memory-Write-Invalidate for device dev
1082 * @dev: the PCI device to disable
1084 * Disables PCI Memory-Write-Invalidate transaction on the device
1087 pci_clear_mwi(struct pci_dev *dev)
1091 pci_read_config_word(dev, PCI_COMMAND, &cmd);
1092 if (cmd & PCI_COMMAND_INVALIDATE) {
1093 cmd &= ~PCI_COMMAND_INVALIDATE;
1094 pci_write_config_word(dev, PCI_COMMAND, cmd);
1097 #endif /* ! PCI_DISABLE_MWI */
1100 * pci_intx - enables/disables PCI INTx for device dev
1101 * @pdev: the PCI device to operate on
1102 * @enable: boolean: whether to enable or disable PCI INTx
1104 * Enables/disables PCI INTx for device dev
1107 pci_intx(struct pci_dev *pdev, int enable)
1109 u16 pci_command, new;
1111 pci_read_config_word(pdev, PCI_COMMAND, &pci_command);
1114 new = pci_command & ~PCI_COMMAND_INTX_DISABLE;
1116 new = pci_command | PCI_COMMAND_INTX_DISABLE;
1119 if (new != pci_command) {
1120 pci_write_config_word(pdev, PCI_COMMAND, new);
1124 #ifndef HAVE_ARCH_PCI_SET_DMA_MASK
1126 * These can be overridden by arch-specific implementations
1129 pci_set_dma_mask(struct pci_dev *dev, u64 mask)
1131 if (!pci_dma_supported(dev, mask))
1134 dev->dma_mask = mask;
1140 pci_set_consistent_dma_mask(struct pci_dev *dev, u64 mask)
1142 if (!pci_dma_supported(dev, mask))
1145 dev->dev.coherent_dma_mask = mask;
1151 static int __devinit pci_init(void)
1153 struct pci_dev *dev = NULL;
1155 while ((dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) {
1156 pci_fixup_device(pci_fixup_final, dev);
1161 static int __devinit pci_setup(char *str)
1164 char *k = strchr(str, ',');
1167 if (*str && (str = pcibios_setup(str)) && *str) {
1168 if (!strcmp(str, "nomsi")) {
1171 printk(KERN_ERR "PCI: Unknown option `%s'\n",
1179 early_param("pci", pci_setup);
1181 device_initcall(pci_init);
1183 #if defined(CONFIG_ISA) || defined(CONFIG_EISA)
1184 /* FIXME: Some boxes have multiple ISA bridges! */
1185 struct pci_dev *isa_bridge;
1186 EXPORT_SYMBOL(isa_bridge);
1189 EXPORT_SYMBOL_GPL(pci_restore_bars);
1190 EXPORT_SYMBOL(pci_enable_device_bars);
1191 EXPORT_SYMBOL(pci_enable_device);
1192 EXPORT_SYMBOL(pci_disable_device);
1193 EXPORT_SYMBOL(pci_find_capability);
1194 EXPORT_SYMBOL(pci_bus_find_capability);
1195 EXPORT_SYMBOL(pci_release_regions);
1196 EXPORT_SYMBOL(pci_request_regions);
1197 EXPORT_SYMBOL(pci_release_region);
1198 EXPORT_SYMBOL(pci_request_region);
1199 EXPORT_SYMBOL(pci_set_master);
1200 EXPORT_SYMBOL(pci_set_mwi);
1201 EXPORT_SYMBOL(pci_clear_mwi);
1202 EXPORT_SYMBOL_GPL(pci_intx);
1203 EXPORT_SYMBOL(pci_set_dma_mask);
1204 EXPORT_SYMBOL(pci_set_consistent_dma_mask);
1205 EXPORT_SYMBOL(pci_assign_resource);
1206 EXPORT_SYMBOL(pci_find_parent_resource);
1208 EXPORT_SYMBOL(pci_set_power_state);
1209 EXPORT_SYMBOL(pci_save_state);
1210 EXPORT_SYMBOL(pci_restore_state);
1211 EXPORT_SYMBOL(pci_enable_wake);
1215 EXPORT_SYMBOL(isa_dma_bridge_buggy);
1216 EXPORT_SYMBOL(pci_pci_problems);