2 * PCI Bus Services, see include/linux/pci.h for further explanation.
4 * Copyright 1993 -- 1997 Drew Eckhardt, Frederic Potter,
7 * Copyright 1997 -- 2000 Martin Mares <mj@ucw.cz>
10 #include <linux/kernel.h>
11 #include <linux/delay.h>
12 #include <linux/init.h>
13 #include <linux/pci.h>
15 #include <linux/module.h>
16 #include <linux/spinlock.h>
17 #include <linux/string.h>
18 #include <linux/log2.h>
19 #include <linux/pci-aspm.h>
20 #include <asm/dma.h> /* isa_dma_bridge_buggy */
23 unsigned int pci_pm_d3_delay = 10;
25 #ifdef CONFIG_PCI_DOMAINS
26 int pci_domains_supported = 1;
29 #define DEFAULT_CARDBUS_IO_SIZE (256)
30 #define DEFAULT_CARDBUS_MEM_SIZE (64*1024*1024)
31 /* pci=cbmemsize=nnM,cbiosize=nn can override this */
32 unsigned long pci_cardbus_io_size = DEFAULT_CARDBUS_IO_SIZE;
33 unsigned long pci_cardbus_mem_size = DEFAULT_CARDBUS_MEM_SIZE;
36 * pci_bus_max_busnr - returns maximum PCI bus number of given bus' children
37 * @bus: pointer to PCI bus structure to search
39 * Given a PCI bus, returns the highest PCI bus number present in the set
40 * including the given PCI bus and its list of child PCI buses.
42 unsigned char pci_bus_max_busnr(struct pci_bus* bus)
44 struct list_head *tmp;
47 max = bus->subordinate;
48 list_for_each(tmp, &bus->children) {
49 n = pci_bus_max_busnr(pci_bus_b(tmp));
55 EXPORT_SYMBOL_GPL(pci_bus_max_busnr);
59 * pci_max_busnr - returns maximum PCI bus number
61 * Returns the highest PCI bus number present in the system global list of
64 unsigned char __devinit
67 struct pci_bus *bus = NULL;
71 while ((bus = pci_find_next_bus(bus)) != NULL) {
72 n = pci_bus_max_busnr(bus);
81 #define PCI_FIND_CAP_TTL 48
83 static int __pci_find_next_cap_ttl(struct pci_bus *bus, unsigned int devfn,
84 u8 pos, int cap, int *ttl)
89 pci_bus_read_config_byte(bus, devfn, pos, &pos);
93 pci_bus_read_config_byte(bus, devfn, pos + PCI_CAP_LIST_ID,
99 pos += PCI_CAP_LIST_NEXT;
104 static int __pci_find_next_cap(struct pci_bus *bus, unsigned int devfn,
107 int ttl = PCI_FIND_CAP_TTL;
109 return __pci_find_next_cap_ttl(bus, devfn, pos, cap, &ttl);
112 int pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap)
114 return __pci_find_next_cap(dev->bus, dev->devfn,
115 pos + PCI_CAP_LIST_NEXT, cap);
117 EXPORT_SYMBOL_GPL(pci_find_next_capability);
119 static int __pci_bus_find_cap_start(struct pci_bus *bus,
120 unsigned int devfn, u8 hdr_type)
124 pci_bus_read_config_word(bus, devfn, PCI_STATUS, &status);
125 if (!(status & PCI_STATUS_CAP_LIST))
129 case PCI_HEADER_TYPE_NORMAL:
130 case PCI_HEADER_TYPE_BRIDGE:
131 return PCI_CAPABILITY_LIST;
132 case PCI_HEADER_TYPE_CARDBUS:
133 return PCI_CB_CAPABILITY_LIST;
142 * pci_find_capability - query for devices' capabilities
143 * @dev: PCI device to query
144 * @cap: capability code
146 * Tell if a device supports a given PCI capability.
147 * Returns the address of the requested capability structure within the
148 * device's PCI configuration space or 0 in case the device does not
149 * support it. Possible values for @cap:
151 * %PCI_CAP_ID_PM Power Management
152 * %PCI_CAP_ID_AGP Accelerated Graphics Port
153 * %PCI_CAP_ID_VPD Vital Product Data
154 * %PCI_CAP_ID_SLOTID Slot Identification
155 * %PCI_CAP_ID_MSI Message Signalled Interrupts
156 * %PCI_CAP_ID_CHSWP CompactPCI HotSwap
157 * %PCI_CAP_ID_PCIX PCI-X
158 * %PCI_CAP_ID_EXP PCI Express
160 int pci_find_capability(struct pci_dev *dev, int cap)
164 pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type);
166 pos = __pci_find_next_cap(dev->bus, dev->devfn, pos, cap);
172 * pci_bus_find_capability - query for devices' capabilities
173 * @bus: the PCI bus to query
174 * @devfn: PCI device to query
175 * @cap: capability code
177 * Like pci_find_capability() but works for pci devices that do not have a
178 * pci_dev structure set up yet.
180 * Returns the address of the requested capability structure within the
181 * device's PCI configuration space or 0 in case the device does not
184 int pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap)
189 pci_bus_read_config_byte(bus, devfn, PCI_HEADER_TYPE, &hdr_type);
191 pos = __pci_bus_find_cap_start(bus, devfn, hdr_type & 0x7f);
193 pos = __pci_find_next_cap(bus, devfn, pos, cap);
199 * pci_find_ext_capability - Find an extended capability
200 * @dev: PCI device to query
201 * @cap: capability code
203 * Returns the address of the requested extended capability structure
204 * within the device's PCI configuration space or 0 if the device does
205 * not support it. Possible values for @cap:
207 * %PCI_EXT_CAP_ID_ERR Advanced Error Reporting
208 * %PCI_EXT_CAP_ID_VC Virtual Channel
209 * %PCI_EXT_CAP_ID_DSN Device Serial Number
210 * %PCI_EXT_CAP_ID_PWR Power Budgeting
212 int pci_find_ext_capability(struct pci_dev *dev, int cap)
215 int ttl = 480; /* 3840 bytes, minimum 8 bytes per capability */
218 if (dev->cfg_size <= 256)
221 if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL)
225 * If we have no capabilities, this is indicated by cap ID,
226 * cap version and next pointer all being 0.
232 if (PCI_EXT_CAP_ID(header) == cap)
235 pos = PCI_EXT_CAP_NEXT(header);
239 if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL)
245 EXPORT_SYMBOL_GPL(pci_find_ext_capability);
247 static int __pci_find_next_ht_cap(struct pci_dev *dev, int pos, int ht_cap)
249 int rc, ttl = PCI_FIND_CAP_TTL;
252 if (ht_cap == HT_CAPTYPE_SLAVE || ht_cap == HT_CAPTYPE_HOST)
253 mask = HT_3BIT_CAP_MASK;
255 mask = HT_5BIT_CAP_MASK;
257 pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn, pos,
258 PCI_CAP_ID_HT, &ttl);
260 rc = pci_read_config_byte(dev, pos + 3, &cap);
261 if (rc != PCIBIOS_SUCCESSFUL)
264 if ((cap & mask) == ht_cap)
267 pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn,
268 pos + PCI_CAP_LIST_NEXT,
269 PCI_CAP_ID_HT, &ttl);
275 * pci_find_next_ht_capability - query a device's Hypertransport capabilities
276 * @dev: PCI device to query
277 * @pos: Position from which to continue searching
278 * @ht_cap: Hypertransport capability code
280 * To be used in conjunction with pci_find_ht_capability() to search for
281 * all capabilities matching @ht_cap. @pos should always be a value returned
282 * from pci_find_ht_capability().
284 * NB. To be 100% safe against broken PCI devices, the caller should take
285 * steps to avoid an infinite loop.
287 int pci_find_next_ht_capability(struct pci_dev *dev, int pos, int ht_cap)
289 return __pci_find_next_ht_cap(dev, pos + PCI_CAP_LIST_NEXT, ht_cap);
291 EXPORT_SYMBOL_GPL(pci_find_next_ht_capability);
294 * pci_find_ht_capability - query a device's Hypertransport capabilities
295 * @dev: PCI device to query
296 * @ht_cap: Hypertransport capability code
298 * Tell if a device supports a given Hypertransport capability.
299 * Returns an address within the device's PCI configuration space
300 * or 0 in case the device does not support the request capability.
301 * The address points to the PCI capability, of type PCI_CAP_ID_HT,
302 * which has a Hypertransport capability matching @ht_cap.
304 int pci_find_ht_capability(struct pci_dev *dev, int ht_cap)
308 pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type);
310 pos = __pci_find_next_ht_cap(dev, pos, ht_cap);
314 EXPORT_SYMBOL_GPL(pci_find_ht_capability);
317 * pci_find_parent_resource - return resource region of parent bus of given region
318 * @dev: PCI device structure contains resources to be searched
319 * @res: child resource record for which parent is sought
321 * For given resource region of given device, return the resource
322 * region of parent bus the given region is contained in or where
323 * it should be allocated from.
326 pci_find_parent_resource(const struct pci_dev *dev, struct resource *res)
328 const struct pci_bus *bus = dev->bus;
330 struct resource *best = NULL;
332 for(i = 0; i < PCI_BUS_NUM_RESOURCES; i++) {
333 struct resource *r = bus->resource[i];
336 if (res->start && !(res->start >= r->start && res->end <= r->end))
337 continue; /* Not contained */
338 if ((res->flags ^ r->flags) & (IORESOURCE_IO | IORESOURCE_MEM))
339 continue; /* Wrong type */
340 if (!((res->flags ^ r->flags) & IORESOURCE_PREFETCH))
341 return r; /* Exact match */
342 if ((res->flags & IORESOURCE_PREFETCH) && !(r->flags & IORESOURCE_PREFETCH))
343 best = r; /* Approximating prefetchable by non-prefetchable */
349 * pci_restore_bars - restore a devices BAR values (e.g. after wake-up)
350 * @dev: PCI device to have its BARs restored
352 * Restore the BAR values for a given device, so as to make it
353 * accessible by its driver.
356 pci_restore_bars(struct pci_dev *dev)
360 switch (dev->hdr_type) {
361 case PCI_HEADER_TYPE_NORMAL:
364 case PCI_HEADER_TYPE_BRIDGE:
367 case PCI_HEADER_TYPE_CARDBUS:
371 /* Should never get here, but just in case... */
375 for (i = 0; i < numres; i ++)
376 pci_update_resource(dev, &dev->resource[i], i);
379 static struct pci_platform_pm_ops *pci_platform_pm;
381 int pci_set_platform_pm(struct pci_platform_pm_ops *ops)
383 if (!ops->is_manageable || !ops->set_state || !ops->choose_state)
385 pci_platform_pm = ops;
389 static inline bool platform_pci_power_manageable(struct pci_dev *dev)
391 return pci_platform_pm ? pci_platform_pm->is_manageable(dev) : false;
394 static inline int platform_pci_set_power_state(struct pci_dev *dev,
397 return pci_platform_pm ? pci_platform_pm->set_state(dev, t) : -ENOSYS;
400 static inline pci_power_t platform_pci_choose_state(struct pci_dev *dev)
402 return pci_platform_pm ?
403 pci_platform_pm->choose_state(dev) : PCI_POWER_ERROR;
407 * pci_set_power_state - Set the power state of a PCI device
408 * @dev: PCI device to be suspended
409 * @state: PCI power state (D0, D1, D2, D3hot, D3cold) we're entering
411 * Transition a device to a new power state, using the Power Management
412 * Capabilities in the device's config space.
415 * -EINVAL if trying to enter a lower state than we're already in.
416 * 0 if we're already in the requested state.
417 * -EIO if device does not support PCI PM.
418 * 0 if we can successfully change the power state.
421 pci_set_power_state(struct pci_dev *dev, pci_power_t state)
423 int pm, need_restore = 0;
426 /* bound the state we're entering */
427 if (state > PCI_D3hot)
431 * If the device or the parent bridge can't support PCI PM, ignore
432 * the request if we're doing anything besides putting it into D0
433 * (which would only happen on boot).
435 if ((state == PCI_D1 || state == PCI_D2) && pci_no_d1d2(dev))
438 /* find PCI PM capability in list */
439 pm = pci_find_capability(dev, PCI_CAP_ID_PM);
441 /* abort if the device doesn't support PM capabilities */
445 /* Validate current state:
446 * Can enter D0 from any state, but if we can only go deeper
447 * to sleep if we're already in a low power state
449 if (state != PCI_D0 && dev->current_state > state) {
450 dev_err(&dev->dev, "invalid power transition "
451 "(from state %d to %d)\n", dev->current_state, state);
453 } else if (dev->current_state == state)
454 return 0; /* we're already there */
457 pci_read_config_word(dev,pm + PCI_PM_PMC,&pmc);
458 if ((pmc & PCI_PM_CAP_VER_MASK) > 3) {
459 dev_printk(KERN_DEBUG, &dev->dev, "unsupported PM cap regs "
460 "version (%u)\n", pmc & PCI_PM_CAP_VER_MASK);
464 /* check if this device supports the desired state */
465 if (state == PCI_D1 && !(pmc & PCI_PM_CAP_D1))
467 else if (state == PCI_D2 && !(pmc & PCI_PM_CAP_D2))
470 pci_read_config_word(dev, pm + PCI_PM_CTRL, &pmcsr);
472 /* If we're (effectively) in D3, force entire word to 0.
473 * This doesn't affect PME_Status, disables PME_En, and
474 * sets PowerState to 0.
476 switch (dev->current_state) {
480 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
483 case PCI_UNKNOWN: /* Boot-up */
484 if ((pmcsr & PCI_PM_CTRL_STATE_MASK) == PCI_D3hot
485 && !(pmcsr & PCI_PM_CTRL_NO_SOFT_RESET))
487 /* Fall-through: force to D0 */
493 /* enter specified state */
494 pci_write_config_word(dev, pm + PCI_PM_CTRL, pmcsr);
496 /* Mandatory power management transition delays */
497 /* see PCI PM 1.1 5.6.1 table 18 */
498 if (state == PCI_D3hot || dev->current_state == PCI_D3hot)
499 msleep(pci_pm_d3_delay);
500 else if (state == PCI_D2 || dev->current_state == PCI_D2)
504 * Give firmware a chance to be called, such as ACPI _PRx, _PSx
505 * Firmware method after native method ?
507 platform_pci_set_power_state(dev, state);
509 dev->current_state = state;
511 /* According to section 5.4.1 of the "PCI BUS POWER MANAGEMENT
512 * INTERFACE SPECIFICATION, REV. 1.2", a device transitioning
513 * from D3hot to D0 _may_ perform an internal reset, thereby
514 * going to "D0 Uninitialized" rather than "D0 Initialized".
515 * For example, at least some versions of the 3c905B and the
516 * 3c556B exhibit this behaviour.
518 * At least some laptop BIOSen (e.g. the Thinkpad T21) leave
519 * devices in a D3hot state at boot. Consequently, we need to
520 * restore at least the BARs so that the device will be
521 * accessible to its driver.
524 pci_restore_bars(dev);
527 pcie_aspm_pm_state_change(dev->bus->self);
533 * pci_choose_state - Choose the power state of a PCI device
534 * @dev: PCI device to be suspended
535 * @state: target sleep state for the whole system. This is the value
536 * that is passed to suspend() function.
538 * Returns PCI power state suitable for given device and given system
542 pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state)
546 if (!pci_find_capability(dev, PCI_CAP_ID_PM))
549 ret = platform_pci_choose_state(dev);
550 if (ret != PCI_POWER_ERROR)
553 switch (state.event) {
556 case PM_EVENT_FREEZE:
557 case PM_EVENT_PRETHAW:
558 /* REVISIT both freeze and pre-thaw "should" use D0 */
559 case PM_EVENT_SUSPEND:
560 case PM_EVENT_HIBERNATE:
563 dev_info(&dev->dev, "unrecognized suspend event %d\n",
570 EXPORT_SYMBOL(pci_choose_state);
572 static int pci_save_pcie_state(struct pci_dev *dev)
575 struct pci_cap_saved_state *save_state;
579 pos = pci_find_capability(dev, PCI_CAP_ID_EXP);
583 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP);
585 save_state = kzalloc(sizeof(*save_state) + sizeof(u16) * 4, GFP_KERNEL);
589 dev_err(&dev->dev, "out of memory in pci_save_pcie_state\n");
592 cap = (u16 *)&save_state->data[0];
594 pci_read_config_word(dev, pos + PCI_EXP_DEVCTL, &cap[i++]);
595 pci_read_config_word(dev, pos + PCI_EXP_LNKCTL, &cap[i++]);
596 pci_read_config_word(dev, pos + PCI_EXP_SLTCTL, &cap[i++]);
597 pci_read_config_word(dev, pos + PCI_EXP_RTCTL, &cap[i++]);
598 save_state->cap_nr = PCI_CAP_ID_EXP;
600 pci_add_saved_cap(dev, save_state);
604 static void pci_restore_pcie_state(struct pci_dev *dev)
607 struct pci_cap_saved_state *save_state;
610 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP);
611 pos = pci_find_capability(dev, PCI_CAP_ID_EXP);
612 if (!save_state || pos <= 0)
614 cap = (u16 *)&save_state->data[0];
616 pci_write_config_word(dev, pos + PCI_EXP_DEVCTL, cap[i++]);
617 pci_write_config_word(dev, pos + PCI_EXP_LNKCTL, cap[i++]);
618 pci_write_config_word(dev, pos + PCI_EXP_SLTCTL, cap[i++]);
619 pci_write_config_word(dev, pos + PCI_EXP_RTCTL, cap[i++]);
623 static int pci_save_pcix_state(struct pci_dev *dev)
626 struct pci_cap_saved_state *save_state;
630 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
634 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_PCIX);
636 save_state = kzalloc(sizeof(*save_state) + sizeof(u16), GFP_KERNEL);
640 dev_err(&dev->dev, "out of memory in pci_save_pcie_state\n");
643 cap = (u16 *)&save_state->data[0];
645 pci_read_config_word(dev, pos + PCI_X_CMD, &cap[i++]);
646 save_state->cap_nr = PCI_CAP_ID_PCIX;
648 pci_add_saved_cap(dev, save_state);
652 static void pci_restore_pcix_state(struct pci_dev *dev)
655 struct pci_cap_saved_state *save_state;
658 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_PCIX);
659 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
660 if (!save_state || pos <= 0)
662 cap = (u16 *)&save_state->data[0];
664 pci_write_config_word(dev, pos + PCI_X_CMD, cap[i++]);
669 * pci_save_state - save the PCI configuration space of a device before suspending
670 * @dev: - PCI device that we're dealing with
673 pci_save_state(struct pci_dev *dev)
676 /* XXX: 100% dword access ok here? */
677 for (i = 0; i < 16; i++)
678 pci_read_config_dword(dev, i * 4,&dev->saved_config_space[i]);
679 if ((i = pci_save_pcie_state(dev)) != 0)
681 if ((i = pci_save_pcix_state(dev)) != 0)
687 * pci_restore_state - Restore the saved state of a PCI device
688 * @dev: - PCI device that we're dealing with
691 pci_restore_state(struct pci_dev *dev)
696 /* PCI Express register must be restored first */
697 pci_restore_pcie_state(dev);
700 * The Base Address register should be programmed before the command
703 for (i = 15; i >= 0; i--) {
704 pci_read_config_dword(dev, i * 4, &val);
705 if (val != dev->saved_config_space[i]) {
706 dev_printk(KERN_DEBUG, &dev->dev, "restoring config "
707 "space at offset %#x (was %#x, writing %#x)\n",
708 i, val, (int)dev->saved_config_space[i]);
709 pci_write_config_dword(dev,i * 4,
710 dev->saved_config_space[i]);
713 pci_restore_pcix_state(dev);
714 pci_restore_msi_state(dev);
719 static int do_pci_enable_device(struct pci_dev *dev, int bars)
723 err = pci_set_power_state(dev, PCI_D0);
724 if (err < 0 && err != -EIO)
726 err = pcibios_enable_device(dev, bars);
729 pci_fixup_device(pci_fixup_enable, dev);
735 * pci_reenable_device - Resume abandoned device
736 * @dev: PCI device to be resumed
738 * Note this function is a backend of pci_default_resume and is not supposed
739 * to be called by normal code, write proper resume handler and use it instead.
741 int pci_reenable_device(struct pci_dev *dev)
743 if (atomic_read(&dev->enable_cnt))
744 return do_pci_enable_device(dev, (1 << PCI_NUM_RESOURCES) - 1);
748 static int __pci_enable_device_flags(struct pci_dev *dev,
749 resource_size_t flags)
754 if (atomic_add_return(1, &dev->enable_cnt) > 1)
755 return 0; /* already enabled */
757 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++)
758 if (dev->resource[i].flags & flags)
761 err = do_pci_enable_device(dev, bars);
763 atomic_dec(&dev->enable_cnt);
768 * pci_enable_device_io - Initialize a device for use with IO space
769 * @dev: PCI device to be initialized
771 * Initialize device before it's used by a driver. Ask low-level code
772 * to enable I/O resources. Wake up the device if it was suspended.
773 * Beware, this function can fail.
775 int pci_enable_device_io(struct pci_dev *dev)
777 return __pci_enable_device_flags(dev, IORESOURCE_IO);
781 * pci_enable_device_mem - Initialize a device for use with Memory space
782 * @dev: PCI device to be initialized
784 * Initialize device before it's used by a driver. Ask low-level code
785 * to enable Memory resources. Wake up the device if it was suspended.
786 * Beware, this function can fail.
788 int pci_enable_device_mem(struct pci_dev *dev)
790 return __pci_enable_device_flags(dev, IORESOURCE_MEM);
794 * pci_enable_device - Initialize device before it's used by a driver.
795 * @dev: PCI device to be initialized
797 * Initialize device before it's used by a driver. Ask low-level code
798 * to enable I/O and memory. Wake up the device if it was suspended.
799 * Beware, this function can fail.
801 * Note we don't actually enable the device many times if we call
802 * this function repeatedly (we just increment the count).
804 int pci_enable_device(struct pci_dev *dev)
806 return __pci_enable_device_flags(dev, IORESOURCE_MEM | IORESOURCE_IO);
810 * Managed PCI resources. This manages device on/off, intx/msi/msix
811 * on/off and BAR regions. pci_dev itself records msi/msix status, so
812 * there's no need to track it separately. pci_devres is initialized
813 * when a device is enabled using managed PCI device enable interface.
816 unsigned int enabled:1;
817 unsigned int pinned:1;
818 unsigned int orig_intx:1;
819 unsigned int restore_intx:1;
823 static void pcim_release(struct device *gendev, void *res)
825 struct pci_dev *dev = container_of(gendev, struct pci_dev, dev);
826 struct pci_devres *this = res;
829 if (dev->msi_enabled)
830 pci_disable_msi(dev);
831 if (dev->msix_enabled)
832 pci_disable_msix(dev);
834 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++)
835 if (this->region_mask & (1 << i))
836 pci_release_region(dev, i);
838 if (this->restore_intx)
839 pci_intx(dev, this->orig_intx);
841 if (this->enabled && !this->pinned)
842 pci_disable_device(dev);
845 static struct pci_devres * get_pci_dr(struct pci_dev *pdev)
847 struct pci_devres *dr, *new_dr;
849 dr = devres_find(&pdev->dev, pcim_release, NULL, NULL);
853 new_dr = devres_alloc(pcim_release, sizeof(*new_dr), GFP_KERNEL);
856 return devres_get(&pdev->dev, new_dr, NULL, NULL);
859 static struct pci_devres * find_pci_dr(struct pci_dev *pdev)
861 if (pci_is_managed(pdev))
862 return devres_find(&pdev->dev, pcim_release, NULL, NULL);
867 * pcim_enable_device - Managed pci_enable_device()
868 * @pdev: PCI device to be initialized
870 * Managed pci_enable_device().
872 int pcim_enable_device(struct pci_dev *pdev)
874 struct pci_devres *dr;
877 dr = get_pci_dr(pdev);
883 rc = pci_enable_device(pdev);
885 pdev->is_managed = 1;
892 * pcim_pin_device - Pin managed PCI device
893 * @pdev: PCI device to pin
895 * Pin managed PCI device @pdev. Pinned device won't be disabled on
896 * driver detach. @pdev must have been enabled with
897 * pcim_enable_device().
899 void pcim_pin_device(struct pci_dev *pdev)
901 struct pci_devres *dr;
903 dr = find_pci_dr(pdev);
904 WARN_ON(!dr || !dr->enabled);
910 * pcibios_disable_device - disable arch specific PCI resources for device dev
911 * @dev: the PCI device to disable
913 * Disables architecture specific PCI resources for the device. This
914 * is the default implementation. Architecture implementations can
917 void __attribute__ ((weak)) pcibios_disable_device (struct pci_dev *dev) {}
920 * pci_disable_device - Disable PCI device after use
921 * @dev: PCI device to be disabled
923 * Signal to the system that the PCI device is not in use by the system
924 * anymore. This only involves disabling PCI bus-mastering, if active.
926 * Note we don't actually disable the device until all callers of
927 * pci_device_enable() have called pci_device_disable().
930 pci_disable_device(struct pci_dev *dev)
932 struct pci_devres *dr;
935 dr = find_pci_dr(dev);
939 if (atomic_sub_return(1, &dev->enable_cnt) != 0)
942 pci_read_config_word(dev, PCI_COMMAND, &pci_command);
943 if (pci_command & PCI_COMMAND_MASTER) {
944 pci_command &= ~PCI_COMMAND_MASTER;
945 pci_write_config_word(dev, PCI_COMMAND, pci_command);
947 dev->is_busmaster = 0;
949 pcibios_disable_device(dev);
953 * pcibios_set_pcie_reset_state - set reset state for device dev
954 * @dev: the PCI-E device reset
955 * @state: Reset state to enter into
958 * Sets the PCI-E reset state for the device. This is the default
959 * implementation. Architecture implementations can override this.
961 int __attribute__ ((weak)) pcibios_set_pcie_reset_state(struct pci_dev *dev,
962 enum pcie_reset_state state)
968 * pci_set_pcie_reset_state - set reset state for device dev
969 * @dev: the PCI-E device reset
970 * @state: Reset state to enter into
973 * Sets the PCI reset state for the device.
975 int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state)
977 return pcibios_set_pcie_reset_state(dev, state);
981 * pci_enable_wake - enable PCI device as wakeup event source
982 * @dev: PCI device affected
983 * @state: PCI state from which device will issue wakeup events
984 * @enable: True to enable event generation; false to disable
986 * This enables the device as a wakeup event source, or disables it.
987 * When such events involves platform-specific hooks, those hooks are
988 * called automatically by this routine.
990 * Devices with legacy power management (no standard PCI PM capabilities)
991 * always require such platform hooks. Depending on the platform, devices
992 * supporting the standard PCI PME# signal may require such platform hooks;
993 * they always update bits in config space to allow PME# generation.
995 * -EIO is returned if the device can't ever be a wakeup event source.
996 * -EINVAL is returned if the device can't generate wakeup events from
997 * the specified PCI state. Returns zero if the operation is successful.
999 int pci_enable_wake(struct pci_dev *dev, pci_power_t state, int enable)
1005 /* Note that drivers should verify device_may_wakeup(&dev->dev)
1006 * before calling this function. Platform code should report
1007 * errors when drivers try to enable wakeup on devices that
1008 * can't issue wakeups, or on which wakeups were disabled by
1009 * userspace updating the /sys/devices.../power/wakeup file.
1012 status = call_platform_enable_wakeup(&dev->dev, enable);
1014 /* find PCI PM capability in list */
1015 pm = pci_find_capability(dev, PCI_CAP_ID_PM);
1017 /* If device doesn't support PM Capabilities, but caller wants to
1018 * disable wake events, it's a NOP. Otherwise fail unless the
1019 * platform hooks handled this legacy device already.
1022 return enable ? status : 0;
1024 /* Check device's ability to generate PME# */
1025 pci_read_config_word(dev,pm+PCI_PM_PMC,&value);
1027 value &= PCI_PM_CAP_PME_MASK;
1028 value >>= ffs(PCI_PM_CAP_PME_MASK) - 1; /* First bit of mask */
1030 /* Check if it can generate PME# from requested state. */
1031 if (!value || !(value & (1 << state))) {
1032 /* if it can't, revert what the platform hook changed,
1033 * always reporting the base "EINVAL, can't PME#" error
1036 call_platform_enable_wakeup(&dev->dev, 0);
1037 return enable ? -EINVAL : 0;
1040 pci_read_config_word(dev, pm + PCI_PM_CTRL, &value);
1042 /* Clear PME_Status by writing 1 to it and enable PME# */
1043 value |= PCI_PM_CTRL_PME_STATUS | PCI_PM_CTRL_PME_ENABLE;
1046 value &= ~PCI_PM_CTRL_PME_ENABLE;
1048 pci_write_config_word(dev, pm + PCI_PM_CTRL, value);
1054 pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge)
1062 while (dev->bus->self) {
1063 pin = (pin + PCI_SLOT(dev->devfn)) % 4;
1064 dev = dev->bus->self;
1071 * pci_release_region - Release a PCI bar
1072 * @pdev: PCI device whose resources were previously reserved by pci_request_region
1073 * @bar: BAR to release
1075 * Releases the PCI I/O and memory resources previously reserved by a
1076 * successful call to pci_request_region. Call this function only
1077 * after all use of the PCI regions has ceased.
1079 void pci_release_region(struct pci_dev *pdev, int bar)
1081 struct pci_devres *dr;
1083 if (pci_resource_len(pdev, bar) == 0)
1085 if (pci_resource_flags(pdev, bar) & IORESOURCE_IO)
1086 release_region(pci_resource_start(pdev, bar),
1087 pci_resource_len(pdev, bar));
1088 else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM)
1089 release_mem_region(pci_resource_start(pdev, bar),
1090 pci_resource_len(pdev, bar));
1092 dr = find_pci_dr(pdev);
1094 dr->region_mask &= ~(1 << bar);
1098 * pci_request_region - Reserved PCI I/O and memory resource
1099 * @pdev: PCI device whose resources are to be reserved
1100 * @bar: BAR to be reserved
1101 * @res_name: Name to be associated with resource.
1103 * Mark the PCI region associated with PCI device @pdev BR @bar as
1104 * being reserved by owner @res_name. Do not access any
1105 * address inside the PCI regions unless this call returns
1108 * Returns 0 on success, or %EBUSY on error. A warning
1109 * message is also printed on failure.
1111 int pci_request_region(struct pci_dev *pdev, int bar, const char *res_name)
1113 struct pci_devres *dr;
1115 if (pci_resource_len(pdev, bar) == 0)
1118 if (pci_resource_flags(pdev, bar) & IORESOURCE_IO) {
1119 if (!request_region(pci_resource_start(pdev, bar),
1120 pci_resource_len(pdev, bar), res_name))
1123 else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM) {
1124 if (!request_mem_region(pci_resource_start(pdev, bar),
1125 pci_resource_len(pdev, bar), res_name))
1129 dr = find_pci_dr(pdev);
1131 dr->region_mask |= 1 << bar;
1136 dev_warn(&pdev->dev, "BAR %d: can't reserve %s region [%#llx-%#llx]\n",
1138 pci_resource_flags(pdev, bar) & IORESOURCE_IO ? "I/O" : "mem",
1139 (unsigned long long)pci_resource_start(pdev, bar),
1140 (unsigned long long)pci_resource_end(pdev, bar));
1145 * pci_release_selected_regions - Release selected PCI I/O and memory resources
1146 * @pdev: PCI device whose resources were previously reserved
1147 * @bars: Bitmask of BARs to be released
1149 * Release selected PCI I/O and memory resources previously reserved.
1150 * Call this function only after all use of the PCI regions has ceased.
1152 void pci_release_selected_regions(struct pci_dev *pdev, int bars)
1156 for (i = 0; i < 6; i++)
1157 if (bars & (1 << i))
1158 pci_release_region(pdev, i);
1162 * pci_request_selected_regions - Reserve selected PCI I/O and memory resources
1163 * @pdev: PCI device whose resources are to be reserved
1164 * @bars: Bitmask of BARs to be requested
1165 * @res_name: Name to be associated with resource
1167 int pci_request_selected_regions(struct pci_dev *pdev, int bars,
1168 const char *res_name)
1172 for (i = 0; i < 6; i++)
1173 if (bars & (1 << i))
1174 if(pci_request_region(pdev, i, res_name))
1180 if (bars & (1 << i))
1181 pci_release_region(pdev, i);
1187 * pci_release_regions - Release reserved PCI I/O and memory resources
1188 * @pdev: PCI device whose resources were previously reserved by pci_request_regions
1190 * Releases all PCI I/O and memory resources previously reserved by a
1191 * successful call to pci_request_regions. Call this function only
1192 * after all use of the PCI regions has ceased.
1195 void pci_release_regions(struct pci_dev *pdev)
1197 pci_release_selected_regions(pdev, (1 << 6) - 1);
1201 * pci_request_regions - Reserved PCI I/O and memory resources
1202 * @pdev: PCI device whose resources are to be reserved
1203 * @res_name: Name to be associated with resource.
1205 * Mark all PCI regions associated with PCI device @pdev as
1206 * being reserved by owner @res_name. Do not access any
1207 * address inside the PCI regions unless this call returns
1210 * Returns 0 on success, or %EBUSY on error. A warning
1211 * message is also printed on failure.
1213 int pci_request_regions(struct pci_dev *pdev, const char *res_name)
1215 return pci_request_selected_regions(pdev, ((1 << 6) - 1), res_name);
1219 * pci_set_master - enables bus-mastering for device dev
1220 * @dev: the PCI device to enable
1222 * Enables bus-mastering on the device and calls pcibios_set_master()
1223 * to do the needed arch specific settings.
1226 pci_set_master(struct pci_dev *dev)
1230 pci_read_config_word(dev, PCI_COMMAND, &cmd);
1231 if (! (cmd & PCI_COMMAND_MASTER)) {
1232 dev_dbg(&dev->dev, "enabling bus mastering\n");
1233 cmd |= PCI_COMMAND_MASTER;
1234 pci_write_config_word(dev, PCI_COMMAND, cmd);
1236 dev->is_busmaster = 1;
1237 pcibios_set_master(dev);
1240 #ifdef PCI_DISABLE_MWI
1241 int pci_set_mwi(struct pci_dev *dev)
1246 int pci_try_set_mwi(struct pci_dev *dev)
1251 void pci_clear_mwi(struct pci_dev *dev)
1257 #ifndef PCI_CACHE_LINE_BYTES
1258 #define PCI_CACHE_LINE_BYTES L1_CACHE_BYTES
1261 /* This can be overridden by arch code. */
1262 /* Don't forget this is measured in 32-bit words, not bytes */
1263 u8 pci_cache_line_size = PCI_CACHE_LINE_BYTES / 4;
1266 * pci_set_cacheline_size - ensure the CACHE_LINE_SIZE register is programmed
1267 * @dev: the PCI device for which MWI is to be enabled
1269 * Helper function for pci_set_mwi.
1270 * Originally copied from drivers/net/acenic.c.
1271 * Copyright 1998-2001 by Jes Sorensen, <jes@trained-monkey.org>.
1273 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
1276 pci_set_cacheline_size(struct pci_dev *dev)
1280 if (!pci_cache_line_size)
1281 return -EINVAL; /* The system doesn't support MWI. */
1283 /* Validate current setting: the PCI_CACHE_LINE_SIZE must be
1284 equal to or multiple of the right value. */
1285 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size);
1286 if (cacheline_size >= pci_cache_line_size &&
1287 (cacheline_size % pci_cache_line_size) == 0)
1290 /* Write the correct value. */
1291 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, pci_cache_line_size);
1293 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size);
1294 if (cacheline_size == pci_cache_line_size)
1297 dev_printk(KERN_DEBUG, &dev->dev, "cache line size of %d is not "
1298 "supported\n", pci_cache_line_size << 2);
1304 * pci_set_mwi - enables memory-write-invalidate PCI transaction
1305 * @dev: the PCI device for which MWI is enabled
1307 * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND.
1309 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
1312 pci_set_mwi(struct pci_dev *dev)
1317 rc = pci_set_cacheline_size(dev);
1321 pci_read_config_word(dev, PCI_COMMAND, &cmd);
1322 if (! (cmd & PCI_COMMAND_INVALIDATE)) {
1323 dev_dbg(&dev->dev, "enabling Mem-Wr-Inval\n");
1324 cmd |= PCI_COMMAND_INVALIDATE;
1325 pci_write_config_word(dev, PCI_COMMAND, cmd);
1332 * pci_try_set_mwi - enables memory-write-invalidate PCI transaction
1333 * @dev: the PCI device for which MWI is enabled
1335 * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND.
1336 * Callers are not required to check the return value.
1338 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
1340 int pci_try_set_mwi(struct pci_dev *dev)
1342 int rc = pci_set_mwi(dev);
1347 * pci_clear_mwi - disables Memory-Write-Invalidate for device dev
1348 * @dev: the PCI device to disable
1350 * Disables PCI Memory-Write-Invalidate transaction on the device
1353 pci_clear_mwi(struct pci_dev *dev)
1357 pci_read_config_word(dev, PCI_COMMAND, &cmd);
1358 if (cmd & PCI_COMMAND_INVALIDATE) {
1359 cmd &= ~PCI_COMMAND_INVALIDATE;
1360 pci_write_config_word(dev, PCI_COMMAND, cmd);
1363 #endif /* ! PCI_DISABLE_MWI */
1366 * pci_intx - enables/disables PCI INTx for device dev
1367 * @pdev: the PCI device to operate on
1368 * @enable: boolean: whether to enable or disable PCI INTx
1370 * Enables/disables PCI INTx for device dev
1373 pci_intx(struct pci_dev *pdev, int enable)
1375 u16 pci_command, new;
1377 pci_read_config_word(pdev, PCI_COMMAND, &pci_command);
1380 new = pci_command & ~PCI_COMMAND_INTX_DISABLE;
1382 new = pci_command | PCI_COMMAND_INTX_DISABLE;
1385 if (new != pci_command) {
1386 struct pci_devres *dr;
1388 pci_write_config_word(pdev, PCI_COMMAND, new);
1390 dr = find_pci_dr(pdev);
1391 if (dr && !dr->restore_intx) {
1392 dr->restore_intx = 1;
1393 dr->orig_intx = !enable;
1399 * pci_msi_off - disables any msi or msix capabilities
1400 * @dev: the PCI device to operate on
1402 * If you want to use msi see pci_enable_msi and friends.
1403 * This is a lower level primitive that allows us to disable
1404 * msi operation at the device level.
1406 void pci_msi_off(struct pci_dev *dev)
1411 pos = pci_find_capability(dev, PCI_CAP_ID_MSI);
1413 pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &control);
1414 control &= ~PCI_MSI_FLAGS_ENABLE;
1415 pci_write_config_word(dev, pos + PCI_MSI_FLAGS, control);
1417 pos = pci_find_capability(dev, PCI_CAP_ID_MSIX);
1419 pci_read_config_word(dev, pos + PCI_MSIX_FLAGS, &control);
1420 control &= ~PCI_MSIX_FLAGS_ENABLE;
1421 pci_write_config_word(dev, pos + PCI_MSIX_FLAGS, control);
1425 #ifndef HAVE_ARCH_PCI_SET_DMA_MASK
1427 * These can be overridden by arch-specific implementations
1430 pci_set_dma_mask(struct pci_dev *dev, u64 mask)
1432 if (!pci_dma_supported(dev, mask))
1435 dev->dma_mask = mask;
1441 pci_set_consistent_dma_mask(struct pci_dev *dev, u64 mask)
1443 if (!pci_dma_supported(dev, mask))
1446 dev->dev.coherent_dma_mask = mask;
1452 #ifndef HAVE_ARCH_PCI_SET_DMA_MAX_SEGMENT_SIZE
1453 int pci_set_dma_max_seg_size(struct pci_dev *dev, unsigned int size)
1455 return dma_set_max_seg_size(&dev->dev, size);
1457 EXPORT_SYMBOL(pci_set_dma_max_seg_size);
1460 #ifndef HAVE_ARCH_PCI_SET_DMA_SEGMENT_BOUNDARY
1461 int pci_set_dma_seg_boundary(struct pci_dev *dev, unsigned long mask)
1463 return dma_set_seg_boundary(&dev->dev, mask);
1465 EXPORT_SYMBOL(pci_set_dma_seg_boundary);
1469 * pcix_get_max_mmrbc - get PCI-X maximum designed memory read byte count
1470 * @dev: PCI device to query
1472 * Returns mmrbc: maximum designed memory read count in bytes
1473 * or appropriate error value.
1475 int pcix_get_max_mmrbc(struct pci_dev *dev)
1480 cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
1484 err = pci_read_config_dword(dev, cap + PCI_X_STATUS, &stat);
1488 return (stat & PCI_X_STATUS_MAX_READ) >> 12;
1490 EXPORT_SYMBOL(pcix_get_max_mmrbc);
1493 * pcix_get_mmrbc - get PCI-X maximum memory read byte count
1494 * @dev: PCI device to query
1496 * Returns mmrbc: maximum memory read count in bytes
1497 * or appropriate error value.
1499 int pcix_get_mmrbc(struct pci_dev *dev)
1504 cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
1508 ret = pci_read_config_dword(dev, cap + PCI_X_CMD, &cmd);
1510 ret = 512 << ((cmd & PCI_X_CMD_MAX_READ) >> 2);
1514 EXPORT_SYMBOL(pcix_get_mmrbc);
1517 * pcix_set_mmrbc - set PCI-X maximum memory read byte count
1518 * @dev: PCI device to query
1519 * @mmrbc: maximum memory read count in bytes
1520 * valid values are 512, 1024, 2048, 4096
1522 * If possible sets maximum memory read byte count, some bridges have erratas
1523 * that prevent this.
1525 int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc)
1527 int cap, err = -EINVAL;
1528 u32 stat, cmd, v, o;
1530 if (mmrbc < 512 || mmrbc > 4096 || !is_power_of_2(mmrbc))
1533 v = ffs(mmrbc) - 10;
1535 cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
1539 err = pci_read_config_dword(dev, cap + PCI_X_STATUS, &stat);
1543 if (v > (stat & PCI_X_STATUS_MAX_READ) >> 21)
1546 err = pci_read_config_dword(dev, cap + PCI_X_CMD, &cmd);
1550 o = (cmd & PCI_X_CMD_MAX_READ) >> 2;
1552 if (v > o && dev->bus &&
1553 (dev->bus->bus_flags & PCI_BUS_FLAGS_NO_MMRBC))
1556 cmd &= ~PCI_X_CMD_MAX_READ;
1558 err = pci_write_config_dword(dev, cap + PCI_X_CMD, cmd);
1563 EXPORT_SYMBOL(pcix_set_mmrbc);
1566 * pcie_get_readrq - get PCI Express read request size
1567 * @dev: PCI device to query
1569 * Returns maximum memory read request in bytes
1570 * or appropriate error value.
1572 int pcie_get_readrq(struct pci_dev *dev)
1577 cap = pci_find_capability(dev, PCI_CAP_ID_EXP);
1581 ret = pci_read_config_word(dev, cap + PCI_EXP_DEVCTL, &ctl);
1583 ret = 128 << ((ctl & PCI_EXP_DEVCTL_READRQ) >> 12);
1587 EXPORT_SYMBOL(pcie_get_readrq);
1590 * pcie_set_readrq - set PCI Express maximum memory read request
1591 * @dev: PCI device to query
1592 * @rq: maximum memory read count in bytes
1593 * valid values are 128, 256, 512, 1024, 2048, 4096
1595 * If possible sets maximum read byte count
1597 int pcie_set_readrq(struct pci_dev *dev, int rq)
1599 int cap, err = -EINVAL;
1602 if (rq < 128 || rq > 4096 || !is_power_of_2(rq))
1605 v = (ffs(rq) - 8) << 12;
1607 cap = pci_find_capability(dev, PCI_CAP_ID_EXP);
1611 err = pci_read_config_word(dev, cap + PCI_EXP_DEVCTL, &ctl);
1615 if ((ctl & PCI_EXP_DEVCTL_READRQ) != v) {
1616 ctl &= ~PCI_EXP_DEVCTL_READRQ;
1618 err = pci_write_config_dword(dev, cap + PCI_EXP_DEVCTL, ctl);
1624 EXPORT_SYMBOL(pcie_set_readrq);
1627 * pci_select_bars - Make BAR mask from the type of resource
1628 * @dev: the PCI device for which BAR mask is made
1629 * @flags: resource type mask to be selected
1631 * This helper routine makes bar mask from the type of resource.
1633 int pci_select_bars(struct pci_dev *dev, unsigned long flags)
1636 for (i = 0; i < PCI_NUM_RESOURCES; i++)
1637 if (pci_resource_flags(dev, i) & flags)
1642 static void __devinit pci_no_domains(void)
1644 #ifdef CONFIG_PCI_DOMAINS
1645 pci_domains_supported = 0;
1649 static int __devinit pci_init(void)
1651 struct pci_dev *dev = NULL;
1653 while ((dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) {
1654 pci_fixup_device(pci_fixup_final, dev);
1659 static int __devinit pci_setup(char *str)
1662 char *k = strchr(str, ',');
1665 if (*str && (str = pcibios_setup(str)) && *str) {
1666 if (!strcmp(str, "nomsi")) {
1668 } else if (!strcmp(str, "noaer")) {
1670 } else if (!strcmp(str, "nodomains")) {
1672 } else if (!strncmp(str, "cbiosize=", 9)) {
1673 pci_cardbus_io_size = memparse(str + 9, &str);
1674 } else if (!strncmp(str, "cbmemsize=", 10)) {
1675 pci_cardbus_mem_size = memparse(str + 10, &str);
1677 printk(KERN_ERR "PCI: Unknown option `%s'\n",
1685 early_param("pci", pci_setup);
1687 device_initcall(pci_init);
1689 EXPORT_SYMBOL(pci_reenable_device);
1690 EXPORT_SYMBOL(pci_enable_device_io);
1691 EXPORT_SYMBOL(pci_enable_device_mem);
1692 EXPORT_SYMBOL(pci_enable_device);
1693 EXPORT_SYMBOL(pcim_enable_device);
1694 EXPORT_SYMBOL(pcim_pin_device);
1695 EXPORT_SYMBOL(pci_disable_device);
1696 EXPORT_SYMBOL(pci_find_capability);
1697 EXPORT_SYMBOL(pci_bus_find_capability);
1698 EXPORT_SYMBOL(pci_release_regions);
1699 EXPORT_SYMBOL(pci_request_regions);
1700 EXPORT_SYMBOL(pci_release_region);
1701 EXPORT_SYMBOL(pci_request_region);
1702 EXPORT_SYMBOL(pci_release_selected_regions);
1703 EXPORT_SYMBOL(pci_request_selected_regions);
1704 EXPORT_SYMBOL(pci_set_master);
1705 EXPORT_SYMBOL(pci_set_mwi);
1706 EXPORT_SYMBOL(pci_try_set_mwi);
1707 EXPORT_SYMBOL(pci_clear_mwi);
1708 EXPORT_SYMBOL_GPL(pci_intx);
1709 EXPORT_SYMBOL(pci_set_dma_mask);
1710 EXPORT_SYMBOL(pci_set_consistent_dma_mask);
1711 EXPORT_SYMBOL(pci_assign_resource);
1712 EXPORT_SYMBOL(pci_find_parent_resource);
1713 EXPORT_SYMBOL(pci_select_bars);
1715 EXPORT_SYMBOL(pci_set_power_state);
1716 EXPORT_SYMBOL(pci_save_state);
1717 EXPORT_SYMBOL(pci_restore_state);
1718 EXPORT_SYMBOL(pci_enable_wake);
1719 EXPORT_SYMBOL_GPL(pci_set_pcie_reset_state);