1 #define DRV_NAME "advansys"
2 #define ASC_VERSION "3.4" /* AdvanSys Driver Version */
5 * advansys.c - Linux Host Driver for AdvanSys SCSI Adapters
7 * Copyright (c) 1995-2000 Advanced System Products, Inc.
8 * Copyright (c) 2000-2001 ConnectCom Solutions, Inc.
9 * Copyright (c) 2007 Matthew Wilcox <matthew@wil.cx>
10 * All Rights Reserved.
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2 of the License, or
15 * (at your option) any later version.
19 * As of March 8, 2000 Advanced System Products, Inc. (AdvanSys)
20 * changed its name to ConnectCom Solutions, Inc.
21 * On June 18, 2001 Initio Corp. acquired ConnectCom's SCSI assets
24 #include <linux/module.h>
25 #include <linux/string.h>
26 #include <linux/kernel.h>
27 #include <linux/types.h>
28 #include <linux/ioport.h>
29 #include <linux/interrupt.h>
30 #include <linux/delay.h>
31 #include <linux/slab.h>
33 #include <linux/proc_fs.h>
34 #include <linux/init.h>
35 #include <linux/blkdev.h>
36 #include <linux/isa.h>
37 #include <linux/eisa.h>
38 #include <linux/pci.h>
39 #include <linux/spinlock.h>
40 #include <linux/dma-mapping.h>
43 #include <asm/system.h>
46 #include <scsi/scsi_cmnd.h>
47 #include <scsi/scsi_device.h>
48 #include <scsi/scsi_tcq.h>
49 #include <scsi/scsi.h>
50 #include <scsi/scsi_host.h>
54 * 1. Although all of the necessary command mapping places have the
55 * appropriate dma_map.. APIs, the driver still processes its internal
56 * queue using bus_to_virt() and virt_to_bus() which are illegal under
57 * the API. The entire queue processing structure will need to be
58 * altered to fix this.
59 * 2. Need to add memory mapping workaround. Test the memory mapping.
60 * If it doesn't work revert to I/O port access. Can a test be done
62 * 3. Handle an interrupt not working. Keep an interrupt counter in
63 * the interrupt handler. In the timeout function if the interrupt
64 * has not occurred then print a message and run in polled mode.
65 * 4. Need to add support for target mode commands, cf. CAM XPT.
66 * 5. check DMA mapping functions for failure
67 * 6. Use scsi_transport_spi
68 * 7. advansys_info is not safe against multiple simultaneous callers
70 * 9. Add module_param to override ISA/VLB ioport array
72 #warning this driver is still not properly converted to the DMA API
74 /* Enable driver /proc statistics. */
75 #define ADVANSYS_STATS
77 /* Enable driver tracing. */
78 /* #define ADVANSYS_DEBUG */
80 #define ASC_LIB_VERSION_MAJOR 1
81 #define ASC_LIB_VERSION_MINOR 24
82 #define ASC_LIB_SERIAL_NUMBER 123
87 * Any instance where a 32-bit long or pointer type is assumed
88 * for precision or HW defined structures, the following define
89 * types must be used. In Linux the char, short, and int types
90 * are all consistent at 8, 16, and 32 bits respectively. Pointers
91 * and long types are 64 bits on Alpha and UltraSPARC.
93 #define ASC_PADDR __u32 /* Physical/Bus address data type. */
94 #define ASC_VADDR __u32 /* Virtual address data type. */
95 #define ASC_DCNT __u32 /* Unsigned Data count type. */
96 #define ASC_SDCNT __s32 /* Signed Data count type. */
99 * These macros are used to convert a virtual address to a
100 * 32-bit value. This currently can be used on Linux Alpha
101 * which uses 64-bit virtual address but a 32-bit bus address.
102 * This is likely to break in the future, but doing this now
103 * will give us time to change the HW and FW to handle 64-bit
106 #define ASC_VADDR_TO_U32 virt_to_bus
107 #define ASC_U32_TO_VADDR bus_to_virt
109 typedef unsigned char uchar;
119 #define UW_ERR (uint)(0xFFFF)
120 #define isodd_word(val) ((((uint)val) & (uint)0x0001) != 0)
122 #define PCI_VENDOR_ID_ASP 0x10cd
123 #define PCI_DEVICE_ID_ASP_1200A 0x1100
124 #define PCI_DEVICE_ID_ASP_ABP940 0x1200
125 #define PCI_DEVICE_ID_ASP_ABP940U 0x1300
126 #define PCI_DEVICE_ID_ASP_ABP940UW 0x2300
127 #define PCI_DEVICE_ID_38C0800_REV1 0x2500
128 #define PCI_DEVICE_ID_38C1600_REV1 0x2700
131 * Enable CC_VERY_LONG_SG_LIST to support up to 64K element SG lists.
132 * The SRB structure will have to be changed and the ASC_SRB2SCSIQ()
133 * macro re-defined to be able to obtain a ASC_SCSI_Q pointer from the
136 #define CC_VERY_LONG_SG_LIST 0
137 #define ASC_SRB2SCSIQ(srb_ptr) (srb_ptr)
139 #define PortAddr unsigned short /* port address size */
140 #define inp(port) inb(port)
141 #define outp(port, byte) outb((byte), (port))
143 #define inpw(port) inw(port)
144 #define outpw(port, word) outw((word), (port))
146 #define ASC_MAX_SG_QUEUE 7
147 #define ASC_MAX_SG_LIST 255
149 #define ASC_CS_TYPE unsigned short
151 #define ASC_IS_ISA (0x0001)
152 #define ASC_IS_ISAPNP (0x0081)
153 #define ASC_IS_EISA (0x0002)
154 #define ASC_IS_PCI (0x0004)
155 #define ASC_IS_PCI_ULTRA (0x0104)
156 #define ASC_IS_PCMCIA (0x0008)
157 #define ASC_IS_MCA (0x0020)
158 #define ASC_IS_VL (0x0040)
159 #define ASC_IS_WIDESCSI_16 (0x0100)
160 #define ASC_IS_WIDESCSI_32 (0x0200)
161 #define ASC_IS_BIG_ENDIAN (0x8000)
163 #define ASC_CHIP_MIN_VER_VL (0x01)
164 #define ASC_CHIP_MAX_VER_VL (0x07)
165 #define ASC_CHIP_MIN_VER_PCI (0x09)
166 #define ASC_CHIP_MAX_VER_PCI (0x0F)
167 #define ASC_CHIP_VER_PCI_BIT (0x08)
168 #define ASC_CHIP_MIN_VER_ISA (0x11)
169 #define ASC_CHIP_MIN_VER_ISA_PNP (0x21)
170 #define ASC_CHIP_MAX_VER_ISA (0x27)
171 #define ASC_CHIP_VER_ISA_BIT (0x30)
172 #define ASC_CHIP_VER_ISAPNP_BIT (0x20)
173 #define ASC_CHIP_VER_ASYN_BUG (0x21)
174 #define ASC_CHIP_VER_PCI 0x08
175 #define ASC_CHIP_VER_PCI_ULTRA_3150 (ASC_CHIP_VER_PCI | 0x02)
176 #define ASC_CHIP_VER_PCI_ULTRA_3050 (ASC_CHIP_VER_PCI | 0x03)
177 #define ASC_CHIP_MIN_VER_EISA (0x41)
178 #define ASC_CHIP_MAX_VER_EISA (0x47)
179 #define ASC_CHIP_VER_EISA_BIT (0x40)
180 #define ASC_CHIP_LATEST_VER_EISA ((ASC_CHIP_MIN_VER_EISA - 1) + 3)
181 #define ASC_MAX_VL_DMA_COUNT (0x07FFFFFFL)
182 #define ASC_MAX_PCI_DMA_COUNT (0xFFFFFFFFL)
183 #define ASC_MAX_ISA_DMA_COUNT (0x00FFFFFFL)
185 #define ASC_SCSI_ID_BITS 3
186 #define ASC_SCSI_TIX_TYPE uchar
187 #define ASC_ALL_DEVICE_BIT_SET 0xFF
188 #define ASC_SCSI_BIT_ID_TYPE uchar
189 #define ASC_MAX_TID 7
190 #define ASC_MAX_LUN 7
191 #define ASC_SCSI_WIDTH_BIT_SET 0xFF
192 #define ASC_MAX_SENSE_LEN 32
193 #define ASC_MIN_SENSE_LEN 14
194 #define ASC_SCSI_RESET_HOLD_TIME_US 60
197 * Narrow boards only support 12-byte commands, while wide boards
198 * extend to 16-byte commands.
200 #define ASC_MAX_CDB_LEN 12
201 #define ADV_MAX_CDB_LEN 16
203 #define MS_SDTR_LEN 0x03
204 #define MS_WDTR_LEN 0x02
206 #define ASC_SG_LIST_PER_Q 7
208 #define QS_READY 0x01
209 #define QS_DISC1 0x02
210 #define QS_DISC2 0x04
212 #define QS_ABORTED 0x40
214 #define QC_NO_CALLBACK 0x01
215 #define QC_SG_SWAP_QUEUE 0x02
216 #define QC_SG_HEAD 0x04
217 #define QC_DATA_IN 0x08
218 #define QC_DATA_OUT 0x10
219 #define QC_URGENT 0x20
220 #define QC_MSG_OUT 0x40
221 #define QC_REQ_SENSE 0x80
222 #define QCSG_SG_XFER_LIST 0x02
223 #define QCSG_SG_XFER_MORE 0x04
224 #define QCSG_SG_XFER_END 0x08
225 #define QD_IN_PROGRESS 0x00
226 #define QD_NO_ERROR 0x01
227 #define QD_ABORTED_BY_HOST 0x02
228 #define QD_WITH_ERROR 0x04
229 #define QD_INVALID_REQUEST 0x80
230 #define QD_INVALID_HOST_NUM 0x81
231 #define QD_INVALID_DEVICE 0x82
232 #define QD_ERR_INTERNAL 0xFF
233 #define QHSTA_NO_ERROR 0x00
234 #define QHSTA_M_SEL_TIMEOUT 0x11
235 #define QHSTA_M_DATA_OVER_RUN 0x12
236 #define QHSTA_M_DATA_UNDER_RUN 0x12
237 #define QHSTA_M_UNEXPECTED_BUS_FREE 0x13
238 #define QHSTA_M_BAD_BUS_PHASE_SEQ 0x14
239 #define QHSTA_D_QDONE_SG_LIST_CORRUPTED 0x21
240 #define QHSTA_D_ASC_DVC_ERROR_CODE_SET 0x22
241 #define QHSTA_D_HOST_ABORT_FAILED 0x23
242 #define QHSTA_D_EXE_SCSI_Q_FAILED 0x24
243 #define QHSTA_D_EXE_SCSI_Q_BUSY_TIMEOUT 0x25
244 #define QHSTA_D_ASPI_NO_BUF_POOL 0x26
245 #define QHSTA_M_WTM_TIMEOUT 0x41
246 #define QHSTA_M_BAD_CMPL_STATUS_IN 0x42
247 #define QHSTA_M_NO_AUTO_REQ_SENSE 0x43
248 #define QHSTA_M_AUTO_REQ_SENSE_FAIL 0x44
249 #define QHSTA_M_TARGET_STATUS_BUSY 0x45
250 #define QHSTA_M_BAD_TAG_CODE 0x46
251 #define QHSTA_M_BAD_QUEUE_FULL_OR_BUSY 0x47
252 #define QHSTA_M_HUNG_REQ_SCSI_BUS_RESET 0x48
253 #define QHSTA_D_LRAM_CMP_ERROR 0x81
254 #define QHSTA_M_MICRO_CODE_ERROR_HALT 0xA1
255 #define ASC_FLAG_SCSIQ_REQ 0x01
256 #define ASC_FLAG_BIOS_SCSIQ_REQ 0x02
257 #define ASC_FLAG_BIOS_ASYNC_IO 0x04
258 #define ASC_FLAG_SRB_LINEAR_ADDR 0x08
259 #define ASC_FLAG_WIN16 0x10
260 #define ASC_FLAG_WIN32 0x20
261 #define ASC_FLAG_ISA_OVER_16MB 0x40
262 #define ASC_FLAG_DOS_VM_CALLBACK 0x80
263 #define ASC_TAG_FLAG_EXTRA_BYTES 0x10
264 #define ASC_TAG_FLAG_DISABLE_DISCONNECT 0x04
265 #define ASC_TAG_FLAG_DISABLE_ASYN_USE_SYN_FIX 0x08
266 #define ASC_TAG_FLAG_DISABLE_CHK_COND_INT_HOST 0x40
267 #define ASC_SCSIQ_CPY_BEG 4
268 #define ASC_SCSIQ_SGHD_CPY_BEG 2
269 #define ASC_SCSIQ_B_FWD 0
270 #define ASC_SCSIQ_B_BWD 1
271 #define ASC_SCSIQ_B_STATUS 2
272 #define ASC_SCSIQ_B_QNO 3
273 #define ASC_SCSIQ_B_CNTL 4
274 #define ASC_SCSIQ_B_SG_QUEUE_CNT 5
275 #define ASC_SCSIQ_D_DATA_ADDR 8
276 #define ASC_SCSIQ_D_DATA_CNT 12
277 #define ASC_SCSIQ_B_SENSE_LEN 20
278 #define ASC_SCSIQ_DONE_INFO_BEG 22
279 #define ASC_SCSIQ_D_SRBPTR 22
280 #define ASC_SCSIQ_B_TARGET_IX 26
281 #define ASC_SCSIQ_B_CDB_LEN 28
282 #define ASC_SCSIQ_B_TAG_CODE 29
283 #define ASC_SCSIQ_W_VM_ID 30
284 #define ASC_SCSIQ_DONE_STATUS 32
285 #define ASC_SCSIQ_HOST_STATUS 33
286 #define ASC_SCSIQ_SCSI_STATUS 34
287 #define ASC_SCSIQ_CDB_BEG 36
288 #define ASC_SCSIQ_DW_REMAIN_XFER_ADDR 56
289 #define ASC_SCSIQ_DW_REMAIN_XFER_CNT 60
290 #define ASC_SCSIQ_B_FIRST_SG_WK_QP 48
291 #define ASC_SCSIQ_B_SG_WK_QP 49
292 #define ASC_SCSIQ_B_SG_WK_IX 50
293 #define ASC_SCSIQ_W_ALT_DC1 52
294 #define ASC_SCSIQ_B_LIST_CNT 6
295 #define ASC_SCSIQ_B_CUR_LIST_CNT 7
296 #define ASC_SGQ_B_SG_CNTL 4
297 #define ASC_SGQ_B_SG_HEAD_QP 5
298 #define ASC_SGQ_B_SG_LIST_CNT 6
299 #define ASC_SGQ_B_SG_CUR_LIST_CNT 7
300 #define ASC_SGQ_LIST_BEG 8
301 #define ASC_DEF_SCSI1_QNG 4
302 #define ASC_MAX_SCSI1_QNG 4
303 #define ASC_DEF_SCSI2_QNG 16
304 #define ASC_MAX_SCSI2_QNG 32
305 #define ASC_TAG_CODE_MASK 0x23
306 #define ASC_STOP_REQ_RISC_STOP 0x01
307 #define ASC_STOP_ACK_RISC_STOP 0x03
308 #define ASC_STOP_CLEAN_UP_BUSY_Q 0x10
309 #define ASC_STOP_CLEAN_UP_DISC_Q 0x20
310 #define ASC_STOP_HOST_REQ_RISC_HALT 0x40
311 #define ASC_TIDLUN_TO_IX(tid, lun) (ASC_SCSI_TIX_TYPE)((tid) + ((lun)<<ASC_SCSI_ID_BITS))
312 #define ASC_TID_TO_TARGET_ID(tid) (ASC_SCSI_BIT_ID_TYPE)(0x01 << (tid))
313 #define ASC_TIX_TO_TARGET_ID(tix) (0x01 << ((tix) & ASC_MAX_TID))
314 #define ASC_TIX_TO_TID(tix) ((tix) & ASC_MAX_TID)
315 #define ASC_TID_TO_TIX(tid) ((tid) & ASC_MAX_TID)
316 #define ASC_TIX_TO_LUN(tix) (((tix) >> ASC_SCSI_ID_BITS) & ASC_MAX_LUN)
317 #define ASC_QNO_TO_QADDR(q_no) ((ASC_QADR_BEG)+((int)(q_no) << 6))
319 typedef struct asc_scsiq_1 {
328 ASC_PADDR sense_addr;
333 typedef struct asc_scsiq_2 {
342 typedef struct asc_scsiq_3 {
349 typedef struct asc_scsiq_4 {
350 uchar cdb[ASC_MAX_CDB_LEN];
351 uchar y_first_sg_list_qp;
352 uchar y_working_sg_qp;
353 uchar y_working_sg_ix;
356 ushort x_reconnect_rtn;
357 ASC_PADDR x_saved_data_addr;
358 ASC_DCNT x_saved_data_cnt;
361 typedef struct asc_q_done_info {
370 ASC_DCNT remain_bytes;
373 typedef struct asc_sg_list {
378 typedef struct asc_sg_head {
381 ushort entry_to_copy;
383 ASC_SG_LIST sg_list[ASC_MAX_SG_LIST];
386 typedef struct asc_scsi_q {
390 ASC_SG_HEAD *sg_head;
391 ushort remain_sg_entry_cnt;
392 ushort next_sg_index;
395 typedef struct asc_scsi_req_q {
399 ASC_SG_HEAD *sg_head;
402 uchar cdb[ASC_MAX_CDB_LEN];
403 uchar sense[ASC_MIN_SENSE_LEN];
406 typedef struct asc_scsi_bios_req_q {
410 ASC_SG_HEAD *sg_head;
413 uchar cdb[ASC_MAX_CDB_LEN];
414 uchar sense[ASC_MIN_SENSE_LEN];
415 } ASC_SCSI_BIOS_REQ_Q;
417 typedef struct asc_risc_q {
426 typedef struct asc_sg_list_q {
432 uchar sg_cur_list_cnt;
435 typedef struct asc_risc_sg_list_q {
439 ASC_SG_LIST sg_list[7];
440 } ASC_RISC_SG_LIST_Q;
442 #define ASCQ_ERR_Q_STATUS 0x0D
443 #define ASCQ_ERR_CUR_QNG 0x17
444 #define ASCQ_ERR_SG_Q_LINKS 0x18
445 #define ASCQ_ERR_ISR_RE_ENTRY 0x1A
446 #define ASCQ_ERR_CRITICAL_RE_ENTRY 0x1B
447 #define ASCQ_ERR_ISR_ON_CRITICAL 0x1C
450 * Warning code values are set in ASC_DVC_VAR 'warn_code'.
452 #define ASC_WARN_NO_ERROR 0x0000
453 #define ASC_WARN_IO_PORT_ROTATE 0x0001
454 #define ASC_WARN_EEPROM_CHKSUM 0x0002
455 #define ASC_WARN_IRQ_MODIFIED 0x0004
456 #define ASC_WARN_AUTO_CONFIG 0x0008
457 #define ASC_WARN_CMD_QNG_CONFLICT 0x0010
458 #define ASC_WARN_EEPROM_RECOVER 0x0020
459 #define ASC_WARN_CFG_MSW_RECOVER 0x0040
462 * Error code values are set in ASC_DVC_VAR 'err_code'.
464 #define ASC_IERR_WRITE_EEPROM 0x0001
465 #define ASC_IERR_MCODE_CHKSUM 0x0002
466 #define ASC_IERR_SET_PC_ADDR 0x0004
467 #define ASC_IERR_START_STOP_CHIP 0x0008
468 #define ASC_IERR_IRQ_NO 0x0010
469 #define ASC_IERR_SET_IRQ_NO 0x0020
470 #define ASC_IERR_CHIP_VERSION 0x0040
471 #define ASC_IERR_SET_SCSI_ID 0x0080
472 #define ASC_IERR_GET_PHY_ADDR 0x0100
473 #define ASC_IERR_BAD_SIGNATURE 0x0200
474 #define ASC_IERR_NO_BUS_TYPE 0x0400
475 #define ASC_IERR_SCAM 0x0800
476 #define ASC_IERR_SET_SDTR 0x1000
477 #define ASC_IERR_RW_LRAM 0x8000
479 #define ASC_MAX_IRQ_NO 15
480 #define ASC_MIN_IRQ_NO 10
481 #define ASC_DEF_MAX_TOTAL_QNG (0xF0)
482 #define ASC_MIN_TAG_Q_PER_DVC (0x04)
483 #define ASC_MIN_FREE_Q (0x02)
484 #define ASC_MIN_TOTAL_QNG ((ASC_MAX_SG_QUEUE)+(ASC_MIN_FREE_Q))
485 #define ASC_MAX_TOTAL_QNG 240
486 #define ASC_MAX_PCI_ULTRA_INRAM_TOTAL_QNG 16
487 #define ASC_MAX_PCI_ULTRA_INRAM_TAG_QNG 8
488 #define ASC_MAX_PCI_INRAM_TOTAL_QNG 20
489 #define ASC_MAX_INRAM_TAG_QNG 16
490 #define ASC_IOADR_GAP 0x10
491 #define ASC_MAX_SYN_XFER_NO 16
492 #define ASC_SYN_MAX_OFFSET 0x0F
493 #define ASC_DEF_SDTR_OFFSET 0x0F
494 #define ASC_SDTR_ULTRA_PCI_10MB_INDEX 0x02
495 #define SYN_XFER_NS_0 25
496 #define SYN_XFER_NS_1 30
497 #define SYN_XFER_NS_2 35
498 #define SYN_XFER_NS_3 40
499 #define SYN_XFER_NS_4 50
500 #define SYN_XFER_NS_5 60
501 #define SYN_XFER_NS_6 70
502 #define SYN_XFER_NS_7 85
503 #define SYN_ULTRA_XFER_NS_0 12
504 #define SYN_ULTRA_XFER_NS_1 19
505 #define SYN_ULTRA_XFER_NS_2 25
506 #define SYN_ULTRA_XFER_NS_3 32
507 #define SYN_ULTRA_XFER_NS_4 38
508 #define SYN_ULTRA_XFER_NS_5 44
509 #define SYN_ULTRA_XFER_NS_6 50
510 #define SYN_ULTRA_XFER_NS_7 57
511 #define SYN_ULTRA_XFER_NS_8 63
512 #define SYN_ULTRA_XFER_NS_9 69
513 #define SYN_ULTRA_XFER_NS_10 75
514 #define SYN_ULTRA_XFER_NS_11 82
515 #define SYN_ULTRA_XFER_NS_12 88
516 #define SYN_ULTRA_XFER_NS_13 94
517 #define SYN_ULTRA_XFER_NS_14 100
518 #define SYN_ULTRA_XFER_NS_15 107
520 typedef struct ext_msg {
526 uchar sdtr_xfer_period;
527 uchar sdtr_req_ack_offset;
542 #define xfer_period u_ext_msg.sdtr.sdtr_xfer_period
543 #define req_ack_offset u_ext_msg.sdtr.sdtr_req_ack_offset
544 #define wdtr_width u_ext_msg.wdtr.wdtr_width
545 #define mdp_b3 u_ext_msg.mdp_b3
546 #define mdp_b2 u_ext_msg.mdp_b2
547 #define mdp_b1 u_ext_msg.mdp_b1
548 #define mdp_b0 u_ext_msg.mdp_b0
550 typedef struct asc_dvc_cfg {
551 ASC_SCSI_BIT_ID_TYPE can_tagged_qng;
552 ASC_SCSI_BIT_ID_TYPE cmd_qng_enabled;
553 ASC_SCSI_BIT_ID_TYPE disc_enable;
554 ASC_SCSI_BIT_ID_TYPE sdtr_enable;
557 uchar isa_dma_channel;
559 ushort lib_serial_no;
562 ushort mcode_version;
563 uchar max_tag_qng[ASC_MAX_TID + 1];
565 uchar sdtr_period_offset[ASC_MAX_TID + 1];
566 uchar adapter_info[6];
569 #define ASC_DEF_DVC_CNTL 0xFFFF
570 #define ASC_DEF_CHIP_SCSI_ID 7
571 #define ASC_DEF_ISA_DMA_SPEED 4
572 #define ASC_INIT_STATE_BEG_GET_CFG 0x0001
573 #define ASC_INIT_STATE_END_GET_CFG 0x0002
574 #define ASC_INIT_STATE_BEG_SET_CFG 0x0004
575 #define ASC_INIT_STATE_END_SET_CFG 0x0008
576 #define ASC_INIT_STATE_BEG_LOAD_MC 0x0010
577 #define ASC_INIT_STATE_END_LOAD_MC 0x0020
578 #define ASC_INIT_STATE_BEG_INQUIRY 0x0040
579 #define ASC_INIT_STATE_END_INQUIRY 0x0080
580 #define ASC_INIT_RESET_SCSI_DONE 0x0100
581 #define ASC_INIT_STATE_WITHOUT_EEP 0x8000
582 #define ASC_BUG_FIX_IF_NOT_DWB 0x0001
583 #define ASC_BUG_FIX_ASYN_USE_SYN 0x0002
584 #define ASYN_SDTR_DATA_FIX_PCI_REV_AB 0x41
585 #define ASC_MIN_TAGGED_CMD 7
586 #define ASC_MAX_SCSI_RESET_WAIT 30
588 struct asc_dvc_var; /* Forward Declaration. */
590 typedef struct asc_dvc_var {
596 ASC_SCSI_BIT_ID_TYPE init_sdtr;
597 ASC_SCSI_BIT_ID_TYPE sdtr_done;
598 ASC_SCSI_BIT_ID_TYPE use_tagged_qng;
599 ASC_SCSI_BIT_ID_TYPE unit_not_ready;
600 ASC_SCSI_BIT_ID_TYPE queue_full_or_busy;
601 ASC_SCSI_BIT_ID_TYPE start_motor;
602 uchar scsi_reset_wait;
607 uchar in_critical_cnt;
609 uchar last_q_shortage;
611 uchar cur_dvc_qng[ASC_MAX_TID + 1];
612 uchar max_dvc_qng[ASC_MAX_TID + 1];
613 ASC_SCSI_Q *scsiq_busy_head[ASC_MAX_TID + 1];
614 ASC_SCSI_Q *scsiq_busy_tail[ASC_MAX_TID + 1];
615 uchar sdtr_period_tbl[ASC_MAX_SYN_XFER_NO];
617 ASC_SCSI_BIT_ID_TYPE pci_fix_asyn_xfer_always;
620 uchar dos_int13_table[ASC_MAX_TID + 1];
621 ASC_DCNT max_dma_count;
622 ASC_SCSI_BIT_ID_TYPE no_scam;
623 ASC_SCSI_BIT_ID_TYPE pci_fix_asyn_xfer;
624 uchar max_sdtr_index;
625 uchar host_init_sdtr_index;
626 struct asc_board *drv_ptr;
630 typedef struct asc_dvc_inq_info {
631 uchar type[ASC_MAX_TID + 1][ASC_MAX_LUN + 1];
634 typedef struct asc_cap_info {
639 typedef struct asc_cap_info_array {
640 ASC_CAP_INFO cap_info[ASC_MAX_TID + 1][ASC_MAX_LUN + 1];
641 } ASC_CAP_INFO_ARRAY;
643 #define ASC_MCNTL_NO_SEL_TIMEOUT (ushort)0x0001
644 #define ASC_MCNTL_NULL_TARGET (ushort)0x0002
645 #define ASC_CNTL_INITIATOR (ushort)0x0001
646 #define ASC_CNTL_BIOS_GT_1GB (ushort)0x0002
647 #define ASC_CNTL_BIOS_GT_2_DISK (ushort)0x0004
648 #define ASC_CNTL_BIOS_REMOVABLE (ushort)0x0008
649 #define ASC_CNTL_NO_SCAM (ushort)0x0010
650 #define ASC_CNTL_INT_MULTI_Q (ushort)0x0080
651 #define ASC_CNTL_NO_LUN_SUPPORT (ushort)0x0040
652 #define ASC_CNTL_NO_VERIFY_COPY (ushort)0x0100
653 #define ASC_CNTL_RESET_SCSI (ushort)0x0200
654 #define ASC_CNTL_INIT_INQUIRY (ushort)0x0400
655 #define ASC_CNTL_INIT_VERBOSE (ushort)0x0800
656 #define ASC_CNTL_SCSI_PARITY (ushort)0x1000
657 #define ASC_CNTL_BURST_MODE (ushort)0x2000
658 #define ASC_CNTL_SDTR_ENABLE_ULTRA (ushort)0x4000
659 #define ASC_EEP_DVC_CFG_BEG_VL 2
660 #define ASC_EEP_MAX_DVC_ADDR_VL 15
661 #define ASC_EEP_DVC_CFG_BEG 32
662 #define ASC_EEP_MAX_DVC_ADDR 45
663 #define ASC_EEP_MAX_RETRY 20
666 * These macros keep the chip SCSI id and ISA DMA speed
667 * bitfields in board order. C bitfields aren't portable
668 * between big and little-endian platforms so they are
672 #define ASC_EEP_GET_CHIP_ID(cfg) ((cfg)->id_speed & 0x0f)
673 #define ASC_EEP_GET_DMA_SPD(cfg) (((cfg)->id_speed & 0xf0) >> 4)
674 #define ASC_EEP_SET_CHIP_ID(cfg, sid) \
675 ((cfg)->id_speed = ((cfg)->id_speed & 0xf0) | ((sid) & ASC_MAX_TID))
676 #define ASC_EEP_SET_DMA_SPD(cfg, spd) \
677 ((cfg)->id_speed = ((cfg)->id_speed & 0x0f) | ((spd) & 0x0f) << 4)
679 typedef struct asceep_config {
691 uchar id_speed; /* low order 4 bits is chip scsi id */
692 /* high order 4 bits is isa dma speed */
693 uchar dos_int13_table[ASC_MAX_TID + 1];
694 uchar adapter_info[6];
699 #define ASC_EEP_CMD_READ 0x80
700 #define ASC_EEP_CMD_WRITE 0x40
701 #define ASC_EEP_CMD_WRITE_ABLE 0x30
702 #define ASC_EEP_CMD_WRITE_DISABLE 0x00
703 #define ASC_OVERRUN_BSIZE 0x00000048UL
704 #define ASCV_MSGOUT_BEG 0x0000
705 #define ASCV_MSGOUT_SDTR_PERIOD (ASCV_MSGOUT_BEG+3)
706 #define ASCV_MSGOUT_SDTR_OFFSET (ASCV_MSGOUT_BEG+4)
707 #define ASCV_BREAK_SAVED_CODE (ushort)0x0006
708 #define ASCV_MSGIN_BEG (ASCV_MSGOUT_BEG+8)
709 #define ASCV_MSGIN_SDTR_PERIOD (ASCV_MSGIN_BEG+3)
710 #define ASCV_MSGIN_SDTR_OFFSET (ASCV_MSGIN_BEG+4)
711 #define ASCV_SDTR_DATA_BEG (ASCV_MSGIN_BEG+8)
712 #define ASCV_SDTR_DONE_BEG (ASCV_SDTR_DATA_BEG+8)
713 #define ASCV_MAX_DVC_QNG_BEG (ushort)0x0020
714 #define ASCV_BREAK_ADDR (ushort)0x0028
715 #define ASCV_BREAK_NOTIFY_COUNT (ushort)0x002A
716 #define ASCV_BREAK_CONTROL (ushort)0x002C
717 #define ASCV_BREAK_HIT_COUNT (ushort)0x002E
719 #define ASCV_ASCDVC_ERR_CODE_W (ushort)0x0030
720 #define ASCV_MCODE_CHKSUM_W (ushort)0x0032
721 #define ASCV_MCODE_SIZE_W (ushort)0x0034
722 #define ASCV_STOP_CODE_B (ushort)0x0036
723 #define ASCV_DVC_ERR_CODE_B (ushort)0x0037
724 #define ASCV_OVERRUN_PADDR_D (ushort)0x0038
725 #define ASCV_OVERRUN_BSIZE_D (ushort)0x003C
726 #define ASCV_HALTCODE_W (ushort)0x0040
727 #define ASCV_CHKSUM_W (ushort)0x0042
728 #define ASCV_MC_DATE_W (ushort)0x0044
729 #define ASCV_MC_VER_W (ushort)0x0046
730 #define ASCV_NEXTRDY_B (ushort)0x0048
731 #define ASCV_DONENEXT_B (ushort)0x0049
732 #define ASCV_USE_TAGGED_QNG_B (ushort)0x004A
733 #define ASCV_SCSIBUSY_B (ushort)0x004B
734 #define ASCV_Q_DONE_IN_PROGRESS_B (ushort)0x004C
735 #define ASCV_CURCDB_B (ushort)0x004D
736 #define ASCV_RCLUN_B (ushort)0x004E
737 #define ASCV_BUSY_QHEAD_B (ushort)0x004F
738 #define ASCV_DISC1_QHEAD_B (ushort)0x0050
739 #define ASCV_DISC_ENABLE_B (ushort)0x0052
740 #define ASCV_CAN_TAGGED_QNG_B (ushort)0x0053
741 #define ASCV_HOSTSCSI_ID_B (ushort)0x0055
742 #define ASCV_MCODE_CNTL_B (ushort)0x0056
743 #define ASCV_NULL_TARGET_B (ushort)0x0057
744 #define ASCV_FREE_Q_HEAD_W (ushort)0x0058
745 #define ASCV_DONE_Q_TAIL_W (ushort)0x005A
746 #define ASCV_FREE_Q_HEAD_B (ushort)(ASCV_FREE_Q_HEAD_W+1)
747 #define ASCV_DONE_Q_TAIL_B (ushort)(ASCV_DONE_Q_TAIL_W+1)
748 #define ASCV_HOST_FLAG_B (ushort)0x005D
749 #define ASCV_TOTAL_READY_Q_B (ushort)0x0064
750 #define ASCV_VER_SERIAL_B (ushort)0x0065
751 #define ASCV_HALTCODE_SAVED_W (ushort)0x0066
752 #define ASCV_WTM_FLAG_B (ushort)0x0068
753 #define ASCV_RISC_FLAG_B (ushort)0x006A
754 #define ASCV_REQ_SG_LIST_QP (ushort)0x006B
755 #define ASC_HOST_FLAG_IN_ISR 0x01
756 #define ASC_HOST_FLAG_ACK_INT 0x02
757 #define ASC_RISC_FLAG_GEN_INT 0x01
758 #define ASC_RISC_FLAG_REQ_SG_LIST 0x02
759 #define IOP_CTRL (0x0F)
760 #define IOP_STATUS (0x0E)
761 #define IOP_INT_ACK IOP_STATUS
762 #define IOP_REG_IFC (0x0D)
763 #define IOP_SYN_OFFSET (0x0B)
764 #define IOP_EXTRA_CONTROL (0x0D)
765 #define IOP_REG_PC (0x0C)
766 #define IOP_RAM_ADDR (0x0A)
767 #define IOP_RAM_DATA (0x08)
768 #define IOP_EEP_DATA (0x06)
769 #define IOP_EEP_CMD (0x07)
770 #define IOP_VERSION (0x03)
771 #define IOP_CONFIG_HIGH (0x04)
772 #define IOP_CONFIG_LOW (0x02)
773 #define IOP_SIG_BYTE (0x01)
774 #define IOP_SIG_WORD (0x00)
775 #define IOP_REG_DC1 (0x0E)
776 #define IOP_REG_DC0 (0x0C)
777 #define IOP_REG_SB (0x0B)
778 #define IOP_REG_DA1 (0x0A)
779 #define IOP_REG_DA0 (0x08)
780 #define IOP_REG_SC (0x09)
781 #define IOP_DMA_SPEED (0x07)
782 #define IOP_REG_FLAG (0x07)
783 #define IOP_FIFO_H (0x06)
784 #define IOP_FIFO_L (0x04)
785 #define IOP_REG_ID (0x05)
786 #define IOP_REG_QP (0x03)
787 #define IOP_REG_IH (0x02)
788 #define IOP_REG_IX (0x01)
789 #define IOP_REG_AX (0x00)
790 #define IFC_REG_LOCK (0x00)
791 #define IFC_REG_UNLOCK (0x09)
792 #define IFC_WR_EN_FILTER (0x10)
793 #define IFC_RD_NO_EEPROM (0x10)
794 #define IFC_SLEW_RATE (0x20)
795 #define IFC_ACT_NEG (0x40)
796 #define IFC_INP_FILTER (0x80)
797 #define IFC_INIT_DEFAULT (IFC_ACT_NEG | IFC_REG_UNLOCK)
798 #define SC_SEL (uchar)(0x80)
799 #define SC_BSY (uchar)(0x40)
800 #define SC_ACK (uchar)(0x20)
801 #define SC_REQ (uchar)(0x10)
802 #define SC_ATN (uchar)(0x08)
803 #define SC_IO (uchar)(0x04)
804 #define SC_CD (uchar)(0x02)
805 #define SC_MSG (uchar)(0x01)
806 #define SEC_SCSI_CTL (uchar)(0x80)
807 #define SEC_ACTIVE_NEGATE (uchar)(0x40)
808 #define SEC_SLEW_RATE (uchar)(0x20)
809 #define SEC_ENABLE_FILTER (uchar)(0x10)
810 #define ASC_HALT_EXTMSG_IN (ushort)0x8000
811 #define ASC_HALT_CHK_CONDITION (ushort)0x8100
812 #define ASC_HALT_SS_QUEUE_FULL (ushort)0x8200
813 #define ASC_HALT_DISABLE_ASYN_USE_SYN_FIX (ushort)0x8300
814 #define ASC_HALT_ENABLE_ASYN_USE_SYN_FIX (ushort)0x8400
815 #define ASC_HALT_SDTR_REJECTED (ushort)0x4000
816 #define ASC_HALT_HOST_COPY_SG_LIST_TO_RISC ( ushort )0x2000
817 #define ASC_MAX_QNO 0xF8
818 #define ASC_DATA_SEC_BEG (ushort)0x0080
819 #define ASC_DATA_SEC_END (ushort)0x0080
820 #define ASC_CODE_SEC_BEG (ushort)0x0080
821 #define ASC_CODE_SEC_END (ushort)0x0080
822 #define ASC_QADR_BEG (0x4000)
823 #define ASC_QADR_USED (ushort)(ASC_MAX_QNO * 64)
824 #define ASC_QADR_END (ushort)0x7FFF
825 #define ASC_QLAST_ADR (ushort)0x7FC0
826 #define ASC_QBLK_SIZE 0x40
827 #define ASC_BIOS_DATA_QBEG 0xF8
828 #define ASC_MIN_ACTIVE_QNO 0x01
829 #define ASC_QLINK_END 0xFF
830 #define ASC_EEPROM_WORDS 0x10
831 #define ASC_MAX_MGS_LEN 0x10
832 #define ASC_BIOS_ADDR_DEF 0xDC00
833 #define ASC_BIOS_SIZE 0x3800
834 #define ASC_BIOS_RAM_OFF 0x3800
835 #define ASC_BIOS_RAM_SIZE 0x800
836 #define ASC_BIOS_MIN_ADDR 0xC000
837 #define ASC_BIOS_MAX_ADDR 0xEC00
838 #define ASC_BIOS_BANK_SIZE 0x0400
839 #define ASC_MCODE_START_ADDR 0x0080
840 #define ASC_CFG0_HOST_INT_ON 0x0020
841 #define ASC_CFG0_BIOS_ON 0x0040
842 #define ASC_CFG0_VERA_BURST_ON 0x0080
843 #define ASC_CFG0_SCSI_PARITY_ON 0x0800
844 #define ASC_CFG1_SCSI_TARGET_ON 0x0080
845 #define ASC_CFG1_LRAM_8BITS_ON 0x0800
846 #define ASC_CFG_MSW_CLR_MASK 0x3080
847 #define CSW_TEST1 (ASC_CS_TYPE)0x8000
848 #define CSW_AUTO_CONFIG (ASC_CS_TYPE)0x4000
849 #define CSW_RESERVED1 (ASC_CS_TYPE)0x2000
850 #define CSW_IRQ_WRITTEN (ASC_CS_TYPE)0x1000
851 #define CSW_33MHZ_SELECTED (ASC_CS_TYPE)0x0800
852 #define CSW_TEST2 (ASC_CS_TYPE)0x0400
853 #define CSW_TEST3 (ASC_CS_TYPE)0x0200
854 #define CSW_RESERVED2 (ASC_CS_TYPE)0x0100
855 #define CSW_DMA_DONE (ASC_CS_TYPE)0x0080
856 #define CSW_FIFO_RDY (ASC_CS_TYPE)0x0040
857 #define CSW_EEP_READ_DONE (ASC_CS_TYPE)0x0020
858 #define CSW_HALTED (ASC_CS_TYPE)0x0010
859 #define CSW_SCSI_RESET_ACTIVE (ASC_CS_TYPE)0x0008
860 #define CSW_PARITY_ERR (ASC_CS_TYPE)0x0004
861 #define CSW_SCSI_RESET_LATCH (ASC_CS_TYPE)0x0002
862 #define CSW_INT_PENDING (ASC_CS_TYPE)0x0001
863 #define CIW_CLR_SCSI_RESET_INT (ASC_CS_TYPE)0x1000
864 #define CIW_INT_ACK (ASC_CS_TYPE)0x0100
865 #define CIW_TEST1 (ASC_CS_TYPE)0x0200
866 #define CIW_TEST2 (ASC_CS_TYPE)0x0400
867 #define CIW_SEL_33MHZ (ASC_CS_TYPE)0x0800
868 #define CIW_IRQ_ACT (ASC_CS_TYPE)0x1000
869 #define CC_CHIP_RESET (uchar)0x80
870 #define CC_SCSI_RESET (uchar)0x40
871 #define CC_HALT (uchar)0x20
872 #define CC_SINGLE_STEP (uchar)0x10
873 #define CC_DMA_ABLE (uchar)0x08
874 #define CC_TEST (uchar)0x04
875 #define CC_BANK_ONE (uchar)0x02
876 #define CC_DIAG (uchar)0x01
877 #define ASC_1000_ID0W 0x04C1
878 #define ASC_1000_ID0W_FIX 0x00C1
879 #define ASC_1000_ID1B 0x25
880 #define ASC_EISA_REV_IOP_MASK (0x0C83)
881 #define ASC_EISA_CFG_IOP_MASK (0x0C86)
882 #define ASC_GET_EISA_SLOT(iop) (PortAddr)((iop) & 0xF000)
883 #define INS_HALTINT (ushort)0x6281
884 #define INS_HALT (ushort)0x6280
885 #define INS_SINT (ushort)0x6200
886 #define INS_RFLAG_WTM (ushort)0x7380
887 #define ASC_MC_SAVE_CODE_WSIZE 0x500
888 #define ASC_MC_SAVE_DATA_WSIZE 0x40
890 typedef struct asc_mc_saved {
891 ushort data[ASC_MC_SAVE_DATA_WSIZE];
892 ushort code[ASC_MC_SAVE_CODE_WSIZE];
895 #define AscGetQDoneInProgress(port) AscReadLramByte((port), ASCV_Q_DONE_IN_PROGRESS_B)
896 #define AscPutQDoneInProgress(port, val) AscWriteLramByte((port), ASCV_Q_DONE_IN_PROGRESS_B, val)
897 #define AscGetVarFreeQHead(port) AscReadLramWord((port), ASCV_FREE_Q_HEAD_W)
898 #define AscGetVarDoneQTail(port) AscReadLramWord((port), ASCV_DONE_Q_TAIL_W)
899 #define AscPutVarFreeQHead(port, val) AscWriteLramWord((port), ASCV_FREE_Q_HEAD_W, val)
900 #define AscPutVarDoneQTail(port, val) AscWriteLramWord((port), ASCV_DONE_Q_TAIL_W, val)
901 #define AscGetRiscVarFreeQHead(port) AscReadLramByte((port), ASCV_NEXTRDY_B)
902 #define AscGetRiscVarDoneQTail(port) AscReadLramByte((port), ASCV_DONENEXT_B)
903 #define AscPutRiscVarFreeQHead(port, val) AscWriteLramByte((port), ASCV_NEXTRDY_B, val)
904 #define AscPutRiscVarDoneQTail(port, val) AscWriteLramByte((port), ASCV_DONENEXT_B, val)
905 #define AscPutMCodeSDTRDoneAtID(port, id, data) AscWriteLramByte((port), (ushort)((ushort)ASCV_SDTR_DONE_BEG+(ushort)id), (data))
906 #define AscGetMCodeSDTRDoneAtID(port, id) AscReadLramByte((port), (ushort)((ushort)ASCV_SDTR_DONE_BEG+(ushort)id))
907 #define AscPutMCodeInitSDTRAtID(port, id, data) AscWriteLramByte((port), (ushort)((ushort)ASCV_SDTR_DATA_BEG+(ushort)id), data)
908 #define AscGetMCodeInitSDTRAtID(port, id) AscReadLramByte((port), (ushort)((ushort)ASCV_SDTR_DATA_BEG+(ushort)id))
909 #define AscSynIndexToPeriod(index) (uchar)(asc_dvc->sdtr_period_tbl[ (index) ])
910 #define AscGetChipSignatureByte(port) (uchar)inp((port)+IOP_SIG_BYTE)
911 #define AscGetChipSignatureWord(port) (ushort)inpw((port)+IOP_SIG_WORD)
912 #define AscGetChipVerNo(port) (uchar)inp((port)+IOP_VERSION)
913 #define AscGetChipCfgLsw(port) (ushort)inpw((port)+IOP_CONFIG_LOW)
914 #define AscGetChipCfgMsw(port) (ushort)inpw((port)+IOP_CONFIG_HIGH)
915 #define AscSetChipCfgLsw(port, data) outpw((port)+IOP_CONFIG_LOW, data)
916 #define AscSetChipCfgMsw(port, data) outpw((port)+IOP_CONFIG_HIGH, data)
917 #define AscGetChipEEPCmd(port) (uchar)inp((port)+IOP_EEP_CMD)
918 #define AscSetChipEEPCmd(port, data) outp((port)+IOP_EEP_CMD, data)
919 #define AscGetChipEEPData(port) (ushort)inpw((port)+IOP_EEP_DATA)
920 #define AscSetChipEEPData(port, data) outpw((port)+IOP_EEP_DATA, data)
921 #define AscGetChipLramAddr(port) (ushort)inpw((PortAddr)((port)+IOP_RAM_ADDR))
922 #define AscSetChipLramAddr(port, addr) outpw((PortAddr)((port)+IOP_RAM_ADDR), addr)
923 #define AscGetChipLramData(port) (ushort)inpw((port)+IOP_RAM_DATA)
924 #define AscSetChipLramData(port, data) outpw((port)+IOP_RAM_DATA, data)
925 #define AscGetChipIFC(port) (uchar)inp((port)+IOP_REG_IFC)
926 #define AscSetChipIFC(port, data) outp((port)+IOP_REG_IFC, data)
927 #define AscGetChipStatus(port) (ASC_CS_TYPE)inpw((port)+IOP_STATUS)
928 #define AscSetChipStatus(port, cs_val) outpw((port)+IOP_STATUS, cs_val)
929 #define AscGetChipControl(port) (uchar)inp((port)+IOP_CTRL)
930 #define AscSetChipControl(port, cc_val) outp((port)+IOP_CTRL, cc_val)
931 #define AscGetChipSyn(port) (uchar)inp((port)+IOP_SYN_OFFSET)
932 #define AscSetChipSyn(port, data) outp((port)+IOP_SYN_OFFSET, data)
933 #define AscSetPCAddr(port, data) outpw((port)+IOP_REG_PC, data)
934 #define AscGetPCAddr(port) (ushort)inpw((port)+IOP_REG_PC)
935 #define AscIsIntPending(port) (AscGetChipStatus(port) & (CSW_INT_PENDING | CSW_SCSI_RESET_LATCH))
936 #define AscGetChipScsiID(port) ((AscGetChipCfgLsw(port) >> 8) & ASC_MAX_TID)
937 #define AscGetExtraControl(port) (uchar)inp((port)+IOP_EXTRA_CONTROL)
938 #define AscSetExtraControl(port, data) outp((port)+IOP_EXTRA_CONTROL, data)
939 #define AscReadChipAX(port) (ushort)inpw((port)+IOP_REG_AX)
940 #define AscWriteChipAX(port, data) outpw((port)+IOP_REG_AX, data)
941 #define AscReadChipIX(port) (uchar)inp((port)+IOP_REG_IX)
942 #define AscWriteChipIX(port, data) outp((port)+IOP_REG_IX, data)
943 #define AscReadChipIH(port) (ushort)inpw((port)+IOP_REG_IH)
944 #define AscWriteChipIH(port, data) outpw((port)+IOP_REG_IH, data)
945 #define AscReadChipQP(port) (uchar)inp((port)+IOP_REG_QP)
946 #define AscWriteChipQP(port, data) outp((port)+IOP_REG_QP, data)
947 #define AscReadChipFIFO_L(port) (ushort)inpw((port)+IOP_REG_FIFO_L)
948 #define AscWriteChipFIFO_L(port, data) outpw((port)+IOP_REG_FIFO_L, data)
949 #define AscReadChipFIFO_H(port) (ushort)inpw((port)+IOP_REG_FIFO_H)
950 #define AscWriteChipFIFO_H(port, data) outpw((port)+IOP_REG_FIFO_H, data)
951 #define AscReadChipDmaSpeed(port) (uchar)inp((port)+IOP_DMA_SPEED)
952 #define AscWriteChipDmaSpeed(port, data) outp((port)+IOP_DMA_SPEED, data)
953 #define AscReadChipDA0(port) (ushort)inpw((port)+IOP_REG_DA0)
954 #define AscWriteChipDA0(port) outpw((port)+IOP_REG_DA0, data)
955 #define AscReadChipDA1(port) (ushort)inpw((port)+IOP_REG_DA1)
956 #define AscWriteChipDA1(port) outpw((port)+IOP_REG_DA1, data)
957 #define AscReadChipDC0(port) (ushort)inpw((port)+IOP_REG_DC0)
958 #define AscWriteChipDC0(port) outpw((port)+IOP_REG_DC0, data)
959 #define AscReadChipDC1(port) (ushort)inpw((port)+IOP_REG_DC1)
960 #define AscWriteChipDC1(port) outpw((port)+IOP_REG_DC1, data)
961 #define AscReadChipDvcID(port) (uchar)inp((port)+IOP_REG_ID)
962 #define AscWriteChipDvcID(port, data) outp((port)+IOP_REG_ID, data)
964 #define ADV_LIB_VERSION_MAJOR 5
965 #define ADV_LIB_VERSION_MINOR 14
968 * Define Adv Library required special types.
972 * Portable Data Types
974 * Any instance where a 32-bit long or pointer type is assumed
975 * for precision or HW defined structures, the following define
976 * types must be used. In Linux the char, short, and int types
977 * are all consistent at 8, 16, and 32 bits respectively. Pointers
978 * and long types are 64 bits on Alpha and UltraSPARC.
980 #define ADV_PADDR __u32 /* Physical address data type. */
981 #define ADV_VADDR __u32 /* Virtual address data type. */
982 #define ADV_DCNT __u32 /* Unsigned Data count type. */
983 #define ADV_SDCNT __s32 /* Signed Data count type. */
986 * These macros are used to convert a virtual address to a
987 * 32-bit value. This currently can be used on Linux Alpha
988 * which uses 64-bit virtual address but a 32-bit bus address.
989 * This is likely to break in the future, but doing this now
990 * will give us time to change the HW and FW to handle 64-bit
993 #define ADV_VADDR_TO_U32 virt_to_bus
994 #define ADV_U32_TO_VADDR bus_to_virt
996 #define AdvPortAddr void __iomem * /* Virtual memory address size */
999 * Define Adv Library required memory access macros.
1001 #define ADV_MEM_READB(addr) readb(addr)
1002 #define ADV_MEM_READW(addr) readw(addr)
1003 #define ADV_MEM_WRITEB(addr, byte) writeb(byte, addr)
1004 #define ADV_MEM_WRITEW(addr, word) writew(word, addr)
1005 #define ADV_MEM_WRITEDW(addr, dword) writel(dword, addr)
1007 #define ADV_CARRIER_COUNT (ASC_DEF_MAX_HOST_QNG + 15)
1010 * Define total number of simultaneous maximum element scatter-gather
1011 * request blocks per wide adapter. ASC_DEF_MAX_HOST_QNG (253) is the
1012 * maximum number of outstanding commands per wide host adapter. Each
1013 * command uses one or more ADV_SG_BLOCK each with 15 scatter-gather
1014 * elements. Allow each command to have at least one ADV_SG_BLOCK structure.
1015 * This allows about 15 commands to have the maximum 17 ADV_SG_BLOCK
1016 * structures or 255 scatter-gather elements.
1019 #define ADV_TOT_SG_BLOCK ASC_DEF_MAX_HOST_QNG
1022 * Define Adv Library required maximum number of scatter-gather
1023 * elements per request.
1025 #define ADV_MAX_SG_LIST 255
1027 /* Number of SG blocks needed. */
1028 #define ADV_NUM_SG_BLOCK \
1029 ((ADV_MAX_SG_LIST + (NO_OF_SG_PER_BLOCK - 1))/NO_OF_SG_PER_BLOCK)
1031 /* Total contiguous memory needed for SG blocks. */
1032 #define ADV_SG_TOTAL_MEM_SIZE \
1033 (sizeof(ADV_SG_BLOCK) * ADV_NUM_SG_BLOCK)
1035 #define ADV_PAGE_SIZE PAGE_SIZE
1037 #define ADV_NUM_PAGE_CROSSING \
1038 ((ADV_SG_TOTAL_MEM_SIZE + (ADV_PAGE_SIZE - 1))/ADV_PAGE_SIZE)
1040 #define ADV_EEP_DVC_CFG_BEGIN (0x00)
1041 #define ADV_EEP_DVC_CFG_END (0x15)
1042 #define ADV_EEP_DVC_CTL_BEGIN (0x16) /* location of OEM name */
1043 #define ADV_EEP_MAX_WORD_ADDR (0x1E)
1045 #define ADV_EEP_DELAY_MS 100
1047 #define ADV_EEPROM_BIG_ENDIAN 0x8000 /* EEPROM Bit 15 */
1048 #define ADV_EEPROM_BIOS_ENABLE 0x4000 /* EEPROM Bit 14 */
1050 * For the ASC3550 Bit 13 is Termination Polarity control bit.
1051 * For later ICs Bit 13 controls whether the CIS (Card Information
1052 * Service Section) is loaded from EEPROM.
1054 #define ADV_EEPROM_TERM_POL 0x2000 /* EEPROM Bit 13 */
1055 #define ADV_EEPROM_CIS_LD 0x2000 /* EEPROM Bit 13 */
1059 * If EEPROM Bit 11 is 0 for Function 0, then Function 0 will specify
1060 * INT A in the PCI Configuration Space Int Pin field. If it is 1, then
1061 * Function 0 will specify INT B.
1063 * If EEPROM Bit 11 is 0 for Function 1, then Function 1 will specify
1064 * INT B in the PCI Configuration Space Int Pin field. If it is 1, then
1065 * Function 1 will specify INT A.
1067 #define ADV_EEPROM_INTAB 0x0800 /* EEPROM Bit 11 */
1069 typedef struct adveep_3550_config {
1070 /* Word Offset, Description */
1072 ushort cfg_lsw; /* 00 power up initialization */
1073 /* bit 13 set - Term Polarity Control */
1074 /* bit 14 set - BIOS Enable */
1075 /* bit 15 set - Big Endian Mode */
1076 ushort cfg_msw; /* 01 unused */
1077 ushort disc_enable; /* 02 disconnect enable */
1078 ushort wdtr_able; /* 03 Wide DTR able */
1079 ushort sdtr_able; /* 04 Synchronous DTR able */
1080 ushort start_motor; /* 05 send start up motor */
1081 ushort tagqng_able; /* 06 tag queuing able */
1082 ushort bios_scan; /* 07 BIOS device control */
1083 ushort scam_tolerant; /* 08 no scam */
1085 uchar adapter_scsi_id; /* 09 Host Adapter ID */
1086 uchar bios_boot_delay; /* power up wait */
1088 uchar scsi_reset_delay; /* 10 reset delay */
1089 uchar bios_id_lun; /* first boot device scsi id & lun */
1090 /* high nibble is lun */
1091 /* low nibble is scsi id */
1093 uchar termination; /* 11 0 - automatic */
1094 /* 1 - low off / high off */
1095 /* 2 - low off / high on */
1096 /* 3 - low on / high on */
1097 /* There is no low on / high off */
1099 uchar reserved1; /* reserved byte (not used) */
1101 ushort bios_ctrl; /* 12 BIOS control bits */
1102 /* bit 0 BIOS don't act as initiator. */
1103 /* bit 1 BIOS > 1 GB support */
1104 /* bit 2 BIOS > 2 Disk Support */
1105 /* bit 3 BIOS don't support removables */
1106 /* bit 4 BIOS support bootable CD */
1107 /* bit 5 BIOS scan enabled */
1108 /* bit 6 BIOS support multiple LUNs */
1109 /* bit 7 BIOS display of message */
1110 /* bit 8 SCAM disabled */
1111 /* bit 9 Reset SCSI bus during init. */
1113 /* bit 11 No verbose initialization. */
1114 /* bit 12 SCSI parity enabled */
1118 ushort ultra_able; /* 13 ULTRA speed able */
1119 ushort reserved2; /* 14 reserved */
1120 uchar max_host_qng; /* 15 maximum host queuing */
1121 uchar max_dvc_qng; /* maximum per device queuing */
1122 ushort dvc_cntl; /* 16 control bit for driver */
1123 ushort bug_fix; /* 17 control bit for bug fix */
1124 ushort serial_number_word1; /* 18 Board serial number word 1 */
1125 ushort serial_number_word2; /* 19 Board serial number word 2 */
1126 ushort serial_number_word3; /* 20 Board serial number word 3 */
1127 ushort check_sum; /* 21 EEP check sum */
1128 uchar oem_name[16]; /* 22 OEM name */
1129 ushort dvc_err_code; /* 30 last device driver error code */
1130 ushort adv_err_code; /* 31 last uc and Adv Lib error code */
1131 ushort adv_err_addr; /* 32 last uc error address */
1132 ushort saved_dvc_err_code; /* 33 saved last dev. driver error code */
1133 ushort saved_adv_err_code; /* 34 saved last uc and Adv Lib error code */
1134 ushort saved_adv_err_addr; /* 35 saved last uc error address */
1135 ushort num_of_err; /* 36 number of error */
1136 } ADVEEP_3550_CONFIG;
1138 typedef struct adveep_38C0800_config {
1139 /* Word Offset, Description */
1141 ushort cfg_lsw; /* 00 power up initialization */
1142 /* bit 13 set - Load CIS */
1143 /* bit 14 set - BIOS Enable */
1144 /* bit 15 set - Big Endian Mode */
1145 ushort cfg_msw; /* 01 unused */
1146 ushort disc_enable; /* 02 disconnect enable */
1147 ushort wdtr_able; /* 03 Wide DTR able */
1148 ushort sdtr_speed1; /* 04 SDTR Speed TID 0-3 */
1149 ushort start_motor; /* 05 send start up motor */
1150 ushort tagqng_able; /* 06 tag queuing able */
1151 ushort bios_scan; /* 07 BIOS device control */
1152 ushort scam_tolerant; /* 08 no scam */
1154 uchar adapter_scsi_id; /* 09 Host Adapter ID */
1155 uchar bios_boot_delay; /* power up wait */
1157 uchar scsi_reset_delay; /* 10 reset delay */
1158 uchar bios_id_lun; /* first boot device scsi id & lun */
1159 /* high nibble is lun */
1160 /* low nibble is scsi id */
1162 uchar termination_se; /* 11 0 - automatic */
1163 /* 1 - low off / high off */
1164 /* 2 - low off / high on */
1165 /* 3 - low on / high on */
1166 /* There is no low on / high off */
1168 uchar termination_lvd; /* 11 0 - automatic */
1169 /* 1 - low off / high off */
1170 /* 2 - low off / high on */
1171 /* 3 - low on / high on */
1172 /* There is no low on / high off */
1174 ushort bios_ctrl; /* 12 BIOS control bits */
1175 /* bit 0 BIOS don't act as initiator. */
1176 /* bit 1 BIOS > 1 GB support */
1177 /* bit 2 BIOS > 2 Disk Support */
1178 /* bit 3 BIOS don't support removables */
1179 /* bit 4 BIOS support bootable CD */
1180 /* bit 5 BIOS scan enabled */
1181 /* bit 6 BIOS support multiple LUNs */
1182 /* bit 7 BIOS display of message */
1183 /* bit 8 SCAM disabled */
1184 /* bit 9 Reset SCSI bus during init. */
1186 /* bit 11 No verbose initialization. */
1187 /* bit 12 SCSI parity enabled */
1191 ushort sdtr_speed2; /* 13 SDTR speed TID 4-7 */
1192 ushort sdtr_speed3; /* 14 SDTR speed TID 8-11 */
1193 uchar max_host_qng; /* 15 maximum host queueing */
1194 uchar max_dvc_qng; /* maximum per device queuing */
1195 ushort dvc_cntl; /* 16 control bit for driver */
1196 ushort sdtr_speed4; /* 17 SDTR speed 4 TID 12-15 */
1197 ushort serial_number_word1; /* 18 Board serial number word 1 */
1198 ushort serial_number_word2; /* 19 Board serial number word 2 */
1199 ushort serial_number_word3; /* 20 Board serial number word 3 */
1200 ushort check_sum; /* 21 EEP check sum */
1201 uchar oem_name[16]; /* 22 OEM name */
1202 ushort dvc_err_code; /* 30 last device driver error code */
1203 ushort adv_err_code; /* 31 last uc and Adv Lib error code */
1204 ushort adv_err_addr; /* 32 last uc error address */
1205 ushort saved_dvc_err_code; /* 33 saved last dev. driver error code */
1206 ushort saved_adv_err_code; /* 34 saved last uc and Adv Lib error code */
1207 ushort saved_adv_err_addr; /* 35 saved last uc error address */
1208 ushort reserved36; /* 36 reserved */
1209 ushort reserved37; /* 37 reserved */
1210 ushort reserved38; /* 38 reserved */
1211 ushort reserved39; /* 39 reserved */
1212 ushort reserved40; /* 40 reserved */
1213 ushort reserved41; /* 41 reserved */
1214 ushort reserved42; /* 42 reserved */
1215 ushort reserved43; /* 43 reserved */
1216 ushort reserved44; /* 44 reserved */
1217 ushort reserved45; /* 45 reserved */
1218 ushort reserved46; /* 46 reserved */
1219 ushort reserved47; /* 47 reserved */
1220 ushort reserved48; /* 48 reserved */
1221 ushort reserved49; /* 49 reserved */
1222 ushort reserved50; /* 50 reserved */
1223 ushort reserved51; /* 51 reserved */
1224 ushort reserved52; /* 52 reserved */
1225 ushort reserved53; /* 53 reserved */
1226 ushort reserved54; /* 54 reserved */
1227 ushort reserved55; /* 55 reserved */
1228 ushort cisptr_lsw; /* 56 CIS PTR LSW */
1229 ushort cisprt_msw; /* 57 CIS PTR MSW */
1230 ushort subsysvid; /* 58 SubSystem Vendor ID */
1231 ushort subsysid; /* 59 SubSystem ID */
1232 ushort reserved60; /* 60 reserved */
1233 ushort reserved61; /* 61 reserved */
1234 ushort reserved62; /* 62 reserved */
1235 ushort reserved63; /* 63 reserved */
1236 } ADVEEP_38C0800_CONFIG;
1238 typedef struct adveep_38C1600_config {
1239 /* Word Offset, Description */
1241 ushort cfg_lsw; /* 00 power up initialization */
1242 /* bit 11 set - Func. 0 INTB, Func. 1 INTA */
1243 /* clear - Func. 0 INTA, Func. 1 INTB */
1244 /* bit 13 set - Load CIS */
1245 /* bit 14 set - BIOS Enable */
1246 /* bit 15 set - Big Endian Mode */
1247 ushort cfg_msw; /* 01 unused */
1248 ushort disc_enable; /* 02 disconnect enable */
1249 ushort wdtr_able; /* 03 Wide DTR able */
1250 ushort sdtr_speed1; /* 04 SDTR Speed TID 0-3 */
1251 ushort start_motor; /* 05 send start up motor */
1252 ushort tagqng_able; /* 06 tag queuing able */
1253 ushort bios_scan; /* 07 BIOS device control */
1254 ushort scam_tolerant; /* 08 no scam */
1256 uchar adapter_scsi_id; /* 09 Host Adapter ID */
1257 uchar bios_boot_delay; /* power up wait */
1259 uchar scsi_reset_delay; /* 10 reset delay */
1260 uchar bios_id_lun; /* first boot device scsi id & lun */
1261 /* high nibble is lun */
1262 /* low nibble is scsi id */
1264 uchar termination_se; /* 11 0 - automatic */
1265 /* 1 - low off / high off */
1266 /* 2 - low off / high on */
1267 /* 3 - low on / high on */
1268 /* There is no low on / high off */
1270 uchar termination_lvd; /* 11 0 - automatic */
1271 /* 1 - low off / high off */
1272 /* 2 - low off / high on */
1273 /* 3 - low on / high on */
1274 /* There is no low on / high off */
1276 ushort bios_ctrl; /* 12 BIOS control bits */
1277 /* bit 0 BIOS don't act as initiator. */
1278 /* bit 1 BIOS > 1 GB support */
1279 /* bit 2 BIOS > 2 Disk Support */
1280 /* bit 3 BIOS don't support removables */
1281 /* bit 4 BIOS support bootable CD */
1282 /* bit 5 BIOS scan enabled */
1283 /* bit 6 BIOS support multiple LUNs */
1284 /* bit 7 BIOS display of message */
1285 /* bit 8 SCAM disabled */
1286 /* bit 9 Reset SCSI bus during init. */
1287 /* bit 10 Basic Integrity Checking disabled */
1288 /* bit 11 No verbose initialization. */
1289 /* bit 12 SCSI parity enabled */
1290 /* bit 13 AIPP (Asyn. Info. Ph. Prot.) dis. */
1293 ushort sdtr_speed2; /* 13 SDTR speed TID 4-7 */
1294 ushort sdtr_speed3; /* 14 SDTR speed TID 8-11 */
1295 uchar max_host_qng; /* 15 maximum host queueing */
1296 uchar max_dvc_qng; /* maximum per device queuing */
1297 ushort dvc_cntl; /* 16 control bit for driver */
1298 ushort sdtr_speed4; /* 17 SDTR speed 4 TID 12-15 */
1299 ushort serial_number_word1; /* 18 Board serial number word 1 */
1300 ushort serial_number_word2; /* 19 Board serial number word 2 */
1301 ushort serial_number_word3; /* 20 Board serial number word 3 */
1302 ushort check_sum; /* 21 EEP check sum */
1303 uchar oem_name[16]; /* 22 OEM name */
1304 ushort dvc_err_code; /* 30 last device driver error code */
1305 ushort adv_err_code; /* 31 last uc and Adv Lib error code */
1306 ushort adv_err_addr; /* 32 last uc error address */
1307 ushort saved_dvc_err_code; /* 33 saved last dev. driver error code */
1308 ushort saved_adv_err_code; /* 34 saved last uc and Adv Lib error code */
1309 ushort saved_adv_err_addr; /* 35 saved last uc error address */
1310 ushort reserved36; /* 36 reserved */
1311 ushort reserved37; /* 37 reserved */
1312 ushort reserved38; /* 38 reserved */
1313 ushort reserved39; /* 39 reserved */
1314 ushort reserved40; /* 40 reserved */
1315 ushort reserved41; /* 41 reserved */
1316 ushort reserved42; /* 42 reserved */
1317 ushort reserved43; /* 43 reserved */
1318 ushort reserved44; /* 44 reserved */
1319 ushort reserved45; /* 45 reserved */
1320 ushort reserved46; /* 46 reserved */
1321 ushort reserved47; /* 47 reserved */
1322 ushort reserved48; /* 48 reserved */
1323 ushort reserved49; /* 49 reserved */
1324 ushort reserved50; /* 50 reserved */
1325 ushort reserved51; /* 51 reserved */
1326 ushort reserved52; /* 52 reserved */
1327 ushort reserved53; /* 53 reserved */
1328 ushort reserved54; /* 54 reserved */
1329 ushort reserved55; /* 55 reserved */
1330 ushort cisptr_lsw; /* 56 CIS PTR LSW */
1331 ushort cisprt_msw; /* 57 CIS PTR MSW */
1332 ushort subsysvid; /* 58 SubSystem Vendor ID */
1333 ushort subsysid; /* 59 SubSystem ID */
1334 ushort reserved60; /* 60 reserved */
1335 ushort reserved61; /* 61 reserved */
1336 ushort reserved62; /* 62 reserved */
1337 ushort reserved63; /* 63 reserved */
1338 } ADVEEP_38C1600_CONFIG;
1343 #define ASC_EEP_CMD_DONE 0x0200
1346 #define BIOS_CTRL_BIOS 0x0001
1347 #define BIOS_CTRL_EXTENDED_XLAT 0x0002
1348 #define BIOS_CTRL_GT_2_DISK 0x0004
1349 #define BIOS_CTRL_BIOS_REMOVABLE 0x0008
1350 #define BIOS_CTRL_BOOTABLE_CD 0x0010
1351 #define BIOS_CTRL_MULTIPLE_LUN 0x0040
1352 #define BIOS_CTRL_DISPLAY_MSG 0x0080
1353 #define BIOS_CTRL_NO_SCAM 0x0100
1354 #define BIOS_CTRL_RESET_SCSI_BUS 0x0200
1355 #define BIOS_CTRL_INIT_VERBOSE 0x0800
1356 #define BIOS_CTRL_SCSI_PARITY 0x1000
1357 #define BIOS_CTRL_AIPP_DIS 0x2000
1359 #define ADV_3550_MEMSIZE 0x2000 /* 8 KB Internal Memory */
1361 #define ADV_38C0800_MEMSIZE 0x4000 /* 16 KB Internal Memory */
1364 * XXX - Since ASC38C1600 Rev.3 has a local RAM failure issue, there is
1365 * a special 16K Adv Library and Microcode version. After the issue is
1366 * resolved, should restore 32K support.
1368 * #define ADV_38C1600_MEMSIZE 0x8000L * 32 KB Internal Memory *
1370 #define ADV_38C1600_MEMSIZE 0x4000 /* 16 KB Internal Memory */
1373 * Byte I/O register address from base of 'iop_base'.
1375 #define IOPB_INTR_STATUS_REG 0x00
1376 #define IOPB_CHIP_ID_1 0x01
1377 #define IOPB_INTR_ENABLES 0x02
1378 #define IOPB_CHIP_TYPE_REV 0x03
1379 #define IOPB_RES_ADDR_4 0x04
1380 #define IOPB_RES_ADDR_5 0x05
1381 #define IOPB_RAM_DATA 0x06
1382 #define IOPB_RES_ADDR_7 0x07
1383 #define IOPB_FLAG_REG 0x08
1384 #define IOPB_RES_ADDR_9 0x09
1385 #define IOPB_RISC_CSR 0x0A
1386 #define IOPB_RES_ADDR_B 0x0B
1387 #define IOPB_RES_ADDR_C 0x0C
1388 #define IOPB_RES_ADDR_D 0x0D
1389 #define IOPB_SOFT_OVER_WR 0x0E
1390 #define IOPB_RES_ADDR_F 0x0F
1391 #define IOPB_MEM_CFG 0x10
1392 #define IOPB_RES_ADDR_11 0x11
1393 #define IOPB_GPIO_DATA 0x12
1394 #define IOPB_RES_ADDR_13 0x13
1395 #define IOPB_FLASH_PAGE 0x14
1396 #define IOPB_RES_ADDR_15 0x15
1397 #define IOPB_GPIO_CNTL 0x16
1398 #define IOPB_RES_ADDR_17 0x17
1399 #define IOPB_FLASH_DATA 0x18
1400 #define IOPB_RES_ADDR_19 0x19
1401 #define IOPB_RES_ADDR_1A 0x1A
1402 #define IOPB_RES_ADDR_1B 0x1B
1403 #define IOPB_RES_ADDR_1C 0x1C
1404 #define IOPB_RES_ADDR_1D 0x1D
1405 #define IOPB_RES_ADDR_1E 0x1E
1406 #define IOPB_RES_ADDR_1F 0x1F
1407 #define IOPB_DMA_CFG0 0x20
1408 #define IOPB_DMA_CFG1 0x21
1409 #define IOPB_TICKLE 0x22
1410 #define IOPB_DMA_REG_WR 0x23
1411 #define IOPB_SDMA_STATUS 0x24
1412 #define IOPB_SCSI_BYTE_CNT 0x25
1413 #define IOPB_HOST_BYTE_CNT 0x26
1414 #define IOPB_BYTE_LEFT_TO_XFER 0x27
1415 #define IOPB_BYTE_TO_XFER_0 0x28
1416 #define IOPB_BYTE_TO_XFER_1 0x29
1417 #define IOPB_BYTE_TO_XFER_2 0x2A
1418 #define IOPB_BYTE_TO_XFER_3 0x2B
1419 #define IOPB_ACC_GRP 0x2C
1420 #define IOPB_RES_ADDR_2D 0x2D
1421 #define IOPB_DEV_ID 0x2E
1422 #define IOPB_RES_ADDR_2F 0x2F
1423 #define IOPB_SCSI_DATA 0x30
1424 #define IOPB_RES_ADDR_31 0x31
1425 #define IOPB_RES_ADDR_32 0x32
1426 #define IOPB_SCSI_DATA_HSHK 0x33
1427 #define IOPB_SCSI_CTRL 0x34
1428 #define IOPB_RES_ADDR_35 0x35
1429 #define IOPB_RES_ADDR_36 0x36
1430 #define IOPB_RES_ADDR_37 0x37
1431 #define IOPB_RAM_BIST 0x38
1432 #define IOPB_PLL_TEST 0x39
1433 #define IOPB_PCI_INT_CFG 0x3A
1434 #define IOPB_RES_ADDR_3B 0x3B
1435 #define IOPB_RFIFO_CNT 0x3C
1436 #define IOPB_RES_ADDR_3D 0x3D
1437 #define IOPB_RES_ADDR_3E 0x3E
1438 #define IOPB_RES_ADDR_3F 0x3F
1441 * Word I/O register address from base of 'iop_base'.
1443 #define IOPW_CHIP_ID_0 0x00 /* CID0 */
1444 #define IOPW_CTRL_REG 0x02 /* CC */
1445 #define IOPW_RAM_ADDR 0x04 /* LA */
1446 #define IOPW_RAM_DATA 0x06 /* LD */
1447 #define IOPW_RES_ADDR_08 0x08
1448 #define IOPW_RISC_CSR 0x0A /* CSR */
1449 #define IOPW_SCSI_CFG0 0x0C /* CFG0 */
1450 #define IOPW_SCSI_CFG1 0x0E /* CFG1 */
1451 #define IOPW_RES_ADDR_10 0x10
1452 #define IOPW_SEL_MASK 0x12 /* SM */
1453 #define IOPW_RES_ADDR_14 0x14
1454 #define IOPW_FLASH_ADDR 0x16 /* FA */
1455 #define IOPW_RES_ADDR_18 0x18
1456 #define IOPW_EE_CMD 0x1A /* EC */
1457 #define IOPW_EE_DATA 0x1C /* ED */
1458 #define IOPW_SFIFO_CNT 0x1E /* SFC */
1459 #define IOPW_RES_ADDR_20 0x20
1460 #define IOPW_Q_BASE 0x22 /* QB */
1461 #define IOPW_QP 0x24 /* QP */
1462 #define IOPW_IX 0x26 /* IX */
1463 #define IOPW_SP 0x28 /* SP */
1464 #define IOPW_PC 0x2A /* PC */
1465 #define IOPW_RES_ADDR_2C 0x2C
1466 #define IOPW_RES_ADDR_2E 0x2E
1467 #define IOPW_SCSI_DATA 0x30 /* SD */
1468 #define IOPW_SCSI_DATA_HSHK 0x32 /* SDH */
1469 #define IOPW_SCSI_CTRL 0x34 /* SC */
1470 #define IOPW_HSHK_CFG 0x36 /* HCFG */
1471 #define IOPW_SXFR_STATUS 0x36 /* SXS */
1472 #define IOPW_SXFR_CNTL 0x38 /* SXL */
1473 #define IOPW_SXFR_CNTH 0x3A /* SXH */
1474 #define IOPW_RES_ADDR_3C 0x3C
1475 #define IOPW_RFIFO_DATA 0x3E /* RFD */
1478 * Doubleword I/O register address from base of 'iop_base'.
1480 #define IOPDW_RES_ADDR_0 0x00
1481 #define IOPDW_RAM_DATA 0x04
1482 #define IOPDW_RES_ADDR_8 0x08
1483 #define IOPDW_RES_ADDR_C 0x0C
1484 #define IOPDW_RES_ADDR_10 0x10
1485 #define IOPDW_COMMA 0x14
1486 #define IOPDW_COMMB 0x18
1487 #define IOPDW_RES_ADDR_1C 0x1C
1488 #define IOPDW_SDMA_ADDR0 0x20
1489 #define IOPDW_SDMA_ADDR1 0x24
1490 #define IOPDW_SDMA_COUNT 0x28
1491 #define IOPDW_SDMA_ERROR 0x2C
1492 #define IOPDW_RDMA_ADDR0 0x30
1493 #define IOPDW_RDMA_ADDR1 0x34
1494 #define IOPDW_RDMA_COUNT 0x38
1495 #define IOPDW_RDMA_ERROR 0x3C
1497 #define ADV_CHIP_ID_BYTE 0x25
1498 #define ADV_CHIP_ID_WORD 0x04C1
1500 #define ADV_INTR_ENABLE_HOST_INTR 0x01
1501 #define ADV_INTR_ENABLE_SEL_INTR 0x02
1502 #define ADV_INTR_ENABLE_DPR_INTR 0x04
1503 #define ADV_INTR_ENABLE_RTA_INTR 0x08
1504 #define ADV_INTR_ENABLE_RMA_INTR 0x10
1505 #define ADV_INTR_ENABLE_RST_INTR 0x20
1506 #define ADV_INTR_ENABLE_DPE_INTR 0x40
1507 #define ADV_INTR_ENABLE_GLOBAL_INTR 0x80
1509 #define ADV_INTR_STATUS_INTRA 0x01
1510 #define ADV_INTR_STATUS_INTRB 0x02
1511 #define ADV_INTR_STATUS_INTRC 0x04
1513 #define ADV_RISC_CSR_STOP (0x0000)
1514 #define ADV_RISC_TEST_COND (0x2000)
1515 #define ADV_RISC_CSR_RUN (0x4000)
1516 #define ADV_RISC_CSR_SINGLE_STEP (0x8000)
1518 #define ADV_CTRL_REG_HOST_INTR 0x0100
1519 #define ADV_CTRL_REG_SEL_INTR 0x0200
1520 #define ADV_CTRL_REG_DPR_INTR 0x0400
1521 #define ADV_CTRL_REG_RTA_INTR 0x0800
1522 #define ADV_CTRL_REG_RMA_INTR 0x1000
1523 #define ADV_CTRL_REG_RES_BIT14 0x2000
1524 #define ADV_CTRL_REG_DPE_INTR 0x4000
1525 #define ADV_CTRL_REG_POWER_DONE 0x8000
1526 #define ADV_CTRL_REG_ANY_INTR 0xFF00
1528 #define ADV_CTRL_REG_CMD_RESET 0x00C6
1529 #define ADV_CTRL_REG_CMD_WR_IO_REG 0x00C5
1530 #define ADV_CTRL_REG_CMD_RD_IO_REG 0x00C4
1531 #define ADV_CTRL_REG_CMD_WR_PCI_CFG_SPACE 0x00C3
1532 #define ADV_CTRL_REG_CMD_RD_PCI_CFG_SPACE 0x00C2
1534 #define ADV_TICKLE_NOP 0x00
1535 #define ADV_TICKLE_A 0x01
1536 #define ADV_TICKLE_B 0x02
1537 #define ADV_TICKLE_C 0x03
1539 #define AdvIsIntPending(port) \
1540 (AdvReadWordRegister(port, IOPW_CTRL_REG) & ADV_CTRL_REG_HOST_INTR)
1543 * SCSI_CFG0 Register bit definitions
1545 #define TIMER_MODEAB 0xC000 /* Watchdog, Second, and Select. Timer Ctrl. */
1546 #define PARITY_EN 0x2000 /* Enable SCSI Parity Error detection */
1547 #define EVEN_PARITY 0x1000 /* Select Even Parity */
1548 #define WD_LONG 0x0800 /* Watchdog Interval, 1: 57 min, 0: 13 sec */
1549 #define QUEUE_128 0x0400 /* Queue Size, 1: 128 byte, 0: 64 byte */
1550 #define PRIM_MODE 0x0100 /* Primitive SCSI mode */
1551 #define SCAM_EN 0x0080 /* Enable SCAM selection */
1552 #define SEL_TMO_LONG 0x0040 /* Sel/Resel Timeout, 1: 400 ms, 0: 1.6 ms */
1553 #define CFRM_ID 0x0020 /* SCAM id sel. confirm., 1: fast, 0: 6.4 ms */
1554 #define OUR_ID_EN 0x0010 /* Enable OUR_ID bits */
1555 #define OUR_ID 0x000F /* SCSI ID */
1558 * SCSI_CFG1 Register bit definitions
1560 #define BIG_ENDIAN 0x8000 /* Enable Big Endian Mode MIO:15, EEP:15 */
1561 #define TERM_POL 0x2000 /* Terminator Polarity Ctrl. MIO:13, EEP:13 */
1562 #define SLEW_RATE 0x1000 /* SCSI output buffer slew rate */
1563 #define FILTER_SEL 0x0C00 /* Filter Period Selection */
1564 #define FLTR_DISABLE 0x0000 /* Input Filtering Disabled */
1565 #define FLTR_11_TO_20NS 0x0800 /* Input Filtering 11ns to 20ns */
1566 #define FLTR_21_TO_39NS 0x0C00 /* Input Filtering 21ns to 39ns */
1567 #define ACTIVE_DBL 0x0200 /* Disable Active Negation */
1568 #define DIFF_MODE 0x0100 /* SCSI differential Mode (Read-Only) */
1569 #define DIFF_SENSE 0x0080 /* 1: No SE cables, 0: SE cable (Read-Only) */
1570 #define TERM_CTL_SEL 0x0040 /* Enable TERM_CTL_H and TERM_CTL_L */
1571 #define TERM_CTL 0x0030 /* External SCSI Termination Bits */
1572 #define TERM_CTL_H 0x0020 /* Enable External SCSI Upper Termination */
1573 #define TERM_CTL_L 0x0010 /* Enable External SCSI Lower Termination */
1574 #define CABLE_DETECT 0x000F /* External SCSI Cable Connection Status */
1577 * Addendum for ASC-38C0800 Chip
1579 * The ASC-38C1600 Chip uses the same definitions except that the
1580 * bus mode override bits [12:10] have been moved to byte register
1581 * offset 0xE (IOPB_SOFT_OVER_WR) bits [12:10]. The [12:10] bits in
1582 * SCSI_CFG1 are read-only and always available. Bit 14 (DIS_TERM_DRV)
1583 * is not needed. The [12:10] bits in IOPB_SOFT_OVER_WR are write-only.
1584 * Also each ASC-38C1600 function or channel uses only cable bits [5:4]
1585 * and [1:0]. Bits [14], [7:6], [3:2] are unused.
1587 #define DIS_TERM_DRV 0x4000 /* 1: Read c_det[3:0], 0: cannot read */
1588 #define HVD_LVD_SE 0x1C00 /* Device Detect Bits */
1589 #define HVD 0x1000 /* HVD Device Detect */
1590 #define LVD 0x0800 /* LVD Device Detect */
1591 #define SE 0x0400 /* SE Device Detect */
1592 #define TERM_LVD 0x00C0 /* LVD Termination Bits */
1593 #define TERM_LVD_HI 0x0080 /* Enable LVD Upper Termination */
1594 #define TERM_LVD_LO 0x0040 /* Enable LVD Lower Termination */
1595 #define TERM_SE 0x0030 /* SE Termination Bits */
1596 #define TERM_SE_HI 0x0020 /* Enable SE Upper Termination */
1597 #define TERM_SE_LO 0x0010 /* Enable SE Lower Termination */
1598 #define C_DET_LVD 0x000C /* LVD Cable Detect Bits */
1599 #define C_DET3 0x0008 /* Cable Detect for LVD External Wide */
1600 #define C_DET2 0x0004 /* Cable Detect for LVD Internal Wide */
1601 #define C_DET_SE 0x0003 /* SE Cable Detect Bits */
1602 #define C_DET1 0x0002 /* Cable Detect for SE Internal Wide */
1603 #define C_DET0 0x0001 /* Cable Detect for SE Internal Narrow */
1605 #define CABLE_ILLEGAL_A 0x7
1606 /* x 0 0 0 | on on | Illegal (all 3 connectors are used) */
1608 #define CABLE_ILLEGAL_B 0xB
1609 /* 0 x 0 0 | on on | Illegal (all 3 connectors are used) */
1612 * MEM_CFG Register bit definitions
1614 #define BIOS_EN 0x40 /* BIOS Enable MIO:14,EEP:14 */
1615 #define FAST_EE_CLK 0x20 /* Diagnostic Bit */
1616 #define RAM_SZ 0x1C /* Specify size of RAM to RISC */
1617 #define RAM_SZ_2KB 0x00 /* 2 KB */
1618 #define RAM_SZ_4KB 0x04 /* 4 KB */
1619 #define RAM_SZ_8KB 0x08 /* 8 KB */
1620 #define RAM_SZ_16KB 0x0C /* 16 KB */
1621 #define RAM_SZ_32KB 0x10 /* 32 KB */
1622 #define RAM_SZ_64KB 0x14 /* 64 KB */
1625 * DMA_CFG0 Register bit definitions
1627 * This register is only accessible to the host.
1629 #define BC_THRESH_ENB 0x80 /* PCI DMA Start Conditions */
1630 #define FIFO_THRESH 0x70 /* PCI DMA FIFO Threshold */
1631 #define FIFO_THRESH_16B 0x00 /* 16 bytes */
1632 #define FIFO_THRESH_32B 0x20 /* 32 bytes */
1633 #define FIFO_THRESH_48B 0x30 /* 48 bytes */
1634 #define FIFO_THRESH_64B 0x40 /* 64 bytes */
1635 #define FIFO_THRESH_80B 0x50 /* 80 bytes (default) */
1636 #define FIFO_THRESH_96B 0x60 /* 96 bytes */
1637 #define FIFO_THRESH_112B 0x70 /* 112 bytes */
1638 #define START_CTL 0x0C /* DMA start conditions */
1639 #define START_CTL_TH 0x00 /* Wait threshold level (default) */
1640 #define START_CTL_ID 0x04 /* Wait SDMA/SBUS idle */
1641 #define START_CTL_THID 0x08 /* Wait threshold and SDMA/SBUS idle */
1642 #define START_CTL_EMFU 0x0C /* Wait SDMA FIFO empty/full */
1643 #define READ_CMD 0x03 /* Memory Read Method */
1644 #define READ_CMD_MR 0x00 /* Memory Read */
1645 #define READ_CMD_MRL 0x02 /* Memory Read Long */
1646 #define READ_CMD_MRM 0x03 /* Memory Read Multiple (default) */
1649 * ASC-38C0800 RAM BIST Register bit definitions
1651 #define RAM_TEST_MODE 0x80
1652 #define PRE_TEST_MODE 0x40
1653 #define NORMAL_MODE 0x00
1654 #define RAM_TEST_DONE 0x10
1655 #define RAM_TEST_STATUS 0x0F
1656 #define RAM_TEST_HOST_ERROR 0x08
1657 #define RAM_TEST_INTRAM_ERROR 0x04
1658 #define RAM_TEST_RISC_ERROR 0x02
1659 #define RAM_TEST_SCSI_ERROR 0x01
1660 #define RAM_TEST_SUCCESS 0x00
1661 #define PRE_TEST_VALUE 0x05
1662 #define NORMAL_VALUE 0x00
1665 * ASC38C1600 Definitions
1667 * IOPB_PCI_INT_CFG Bit Field Definitions
1670 #define INTAB_LD 0x80 /* Value loaded from EEPROM Bit 11. */
1673 * Bit 1 can be set to change the interrupt for the Function to operate in
1674 * Totem Pole mode. By default Bit 1 is 0 and the interrupt operates in
1675 * Open Drain mode. Both functions of the ASC38C1600 must be set to the same
1676 * mode, otherwise the operating mode is undefined.
1678 #define TOTEMPOLE 0x02
1681 * Bit 0 can be used to change the Int Pin for the Function. The value is
1682 * 0 by default for both Functions with Function 0 using INT A and Function
1683 * B using INT B. For Function 0 if set, INT B is used. For Function 1 if set,
1686 * EEPROM Word 0 Bit 11 for each Function may change the initial Int Pin
1687 * value specified in the PCI Configuration Space.
1692 * Adv Library Status Definitions
1696 #define ADV_SUCCESS 1
1698 #define ADV_ERROR (-1)
1701 * ADV_DVC_VAR 'warn_code' values
1703 #define ASC_WARN_BUSRESET_ERROR 0x0001 /* SCSI Bus Reset error */
1704 #define ASC_WARN_EEPROM_CHKSUM 0x0002 /* EEP check sum error */
1705 #define ASC_WARN_EEPROM_TERMINATION 0x0004 /* EEP termination bad field */
1706 #define ASC_WARN_ERROR 0xFFFF /* ADV_ERROR return */
1708 #define ADV_MAX_TID 15 /* max. target identifier */
1709 #define ADV_MAX_LUN 7 /* max. logical unit number */
1712 * Error code values are set in ADV_DVC_VAR 'err_code'.
1714 #define ASC_IERR_WRITE_EEPROM 0x0001 /* write EEPROM error */
1715 #define ASC_IERR_MCODE_CHKSUM 0x0002 /* micro code check sum error */
1716 #define ASC_IERR_NO_CARRIER 0x0004 /* No more carrier memory. */
1717 #define ASC_IERR_START_STOP_CHIP 0x0008 /* start/stop chip failed */
1718 #define ASC_IERR_CHIP_VERSION 0x0040 /* wrong chip version */
1719 #define ASC_IERR_SET_SCSI_ID 0x0080 /* set SCSI ID failed */
1720 #define ASC_IERR_HVD_DEVICE 0x0100 /* HVD attached to LVD connector. */
1721 #define ASC_IERR_BAD_SIGNATURE 0x0200 /* signature not found */
1722 #define ASC_IERR_ILLEGAL_CONNECTION 0x0400 /* Illegal cable connection */
1723 #define ASC_IERR_SINGLE_END_DEVICE 0x0800 /* Single-end used w/differential */
1724 #define ASC_IERR_REVERSED_CABLE 0x1000 /* Narrow flat cable reversed */
1725 #define ASC_IERR_BIST_PRE_TEST 0x2000 /* BIST pre-test error */
1726 #define ASC_IERR_BIST_RAM_TEST 0x4000 /* BIST RAM test error */
1727 #define ASC_IERR_BAD_CHIPTYPE 0x8000 /* Invalid 'chip_type' setting. */
1730 * Fixed locations of microcode operating variables.
1732 #define ASC_MC_CODE_BEGIN_ADDR 0x0028 /* microcode start address */
1733 #define ASC_MC_CODE_END_ADDR 0x002A /* microcode end address */
1734 #define ASC_MC_CODE_CHK_SUM 0x002C /* microcode code checksum */
1735 #define ASC_MC_VERSION_DATE 0x0038 /* microcode version */
1736 #define ASC_MC_VERSION_NUM 0x003A /* microcode number */
1737 #define ASC_MC_BIOSMEM 0x0040 /* BIOS RISC Memory Start */
1738 #define ASC_MC_BIOSLEN 0x0050 /* BIOS RISC Memory Length */
1739 #define ASC_MC_BIOS_SIGNATURE 0x0058 /* BIOS Signature 0x55AA */
1740 #define ASC_MC_BIOS_VERSION 0x005A /* BIOS Version (2 bytes) */
1741 #define ASC_MC_SDTR_SPEED1 0x0090 /* SDTR Speed for TID 0-3 */
1742 #define ASC_MC_SDTR_SPEED2 0x0092 /* SDTR Speed for TID 4-7 */
1743 #define ASC_MC_SDTR_SPEED3 0x0094 /* SDTR Speed for TID 8-11 */
1744 #define ASC_MC_SDTR_SPEED4 0x0096 /* SDTR Speed for TID 12-15 */
1745 #define ASC_MC_CHIP_TYPE 0x009A
1746 #define ASC_MC_INTRB_CODE 0x009B
1747 #define ASC_MC_WDTR_ABLE 0x009C
1748 #define ASC_MC_SDTR_ABLE 0x009E
1749 #define ASC_MC_TAGQNG_ABLE 0x00A0
1750 #define ASC_MC_DISC_ENABLE 0x00A2
1751 #define ASC_MC_IDLE_CMD_STATUS 0x00A4
1752 #define ASC_MC_IDLE_CMD 0x00A6
1753 #define ASC_MC_IDLE_CMD_PARAMETER 0x00A8
1754 #define ASC_MC_DEFAULT_SCSI_CFG0 0x00AC
1755 #define ASC_MC_DEFAULT_SCSI_CFG1 0x00AE
1756 #define ASC_MC_DEFAULT_MEM_CFG 0x00B0
1757 #define ASC_MC_DEFAULT_SEL_MASK 0x00B2
1758 #define ASC_MC_SDTR_DONE 0x00B6
1759 #define ASC_MC_NUMBER_OF_QUEUED_CMD 0x00C0
1760 #define ASC_MC_NUMBER_OF_MAX_CMD 0x00D0
1761 #define ASC_MC_DEVICE_HSHK_CFG_TABLE 0x0100
1762 #define ASC_MC_CONTROL_FLAG 0x0122 /* Microcode control flag. */
1763 #define ASC_MC_WDTR_DONE 0x0124
1764 #define ASC_MC_CAM_MODE_MASK 0x015E /* CAM mode TID bitmask. */
1765 #define ASC_MC_ICQ 0x0160
1766 #define ASC_MC_IRQ 0x0164
1767 #define ASC_MC_PPR_ABLE 0x017A
1770 * BIOS LRAM variable absolute offsets.
1772 #define BIOS_CODESEG 0x54
1773 #define BIOS_CODELEN 0x56
1774 #define BIOS_SIGNATURE 0x58
1775 #define BIOS_VERSION 0x5A
1778 * Microcode Control Flags
1780 * Flags set by the Adv Library in RISC variable 'control_flag' (0x122)
1781 * and handled by the microcode.
1783 #define CONTROL_FLAG_IGNORE_PERR 0x0001 /* Ignore DMA Parity Errors */
1784 #define CONTROL_FLAG_ENABLE_AIPP 0x0002 /* Enabled AIPP checking. */
1787 * ASC_MC_DEVICE_HSHK_CFG_TABLE microcode table or HSHK_CFG register format
1789 #define HSHK_CFG_WIDE_XFR 0x8000
1790 #define HSHK_CFG_RATE 0x0F00
1791 #define HSHK_CFG_OFFSET 0x001F
1793 #define ASC_DEF_MAX_HOST_QNG 0xFD /* Max. number of host commands (253) */
1794 #define ASC_DEF_MIN_HOST_QNG 0x10 /* Min. number of host commands (16) */
1795 #define ASC_DEF_MAX_DVC_QNG 0x3F /* Max. number commands per device (63) */
1796 #define ASC_DEF_MIN_DVC_QNG 0x04 /* Min. number commands per device (4) */
1798 #define ASC_QC_DATA_CHECK 0x01 /* Require ASC_QC_DATA_OUT set or clear. */
1799 #define ASC_QC_DATA_OUT 0x02 /* Data out DMA transfer. */
1800 #define ASC_QC_START_MOTOR 0x04 /* Send auto-start motor before request. */
1801 #define ASC_QC_NO_OVERRUN 0x08 /* Don't report overrun. */
1802 #define ASC_QC_FREEZE_TIDQ 0x10 /* Freeze TID queue after request. XXX TBD */
1804 #define ASC_QSC_NO_DISC 0x01 /* Don't allow disconnect for request. */
1805 #define ASC_QSC_NO_TAGMSG 0x02 /* Don't allow tag queuing for request. */
1806 #define ASC_QSC_NO_SYNC 0x04 /* Don't use Synch. transfer on request. */
1807 #define ASC_QSC_NO_WIDE 0x08 /* Don't use Wide transfer on request. */
1808 #define ASC_QSC_REDO_DTR 0x10 /* Renegotiate WDTR/SDTR before request. */
1810 * Note: If a Tag Message is to be sent and neither ASC_QSC_HEAD_TAG or
1811 * ASC_QSC_ORDERED_TAG is set, then a Simple Tag Message (0x20) is used.
1813 #define ASC_QSC_HEAD_TAG 0x40 /* Use Head Tag Message (0x21). */
1814 #define ASC_QSC_ORDERED_TAG 0x80 /* Use Ordered Tag Message (0x22). */
1817 * All fields here are accessed by the board microcode and need to be
1820 typedef struct adv_carr_t {
1821 ADV_VADDR carr_va; /* Carrier Virtual Address */
1822 ADV_PADDR carr_pa; /* Carrier Physical Address */
1823 ADV_VADDR areq_vpa; /* ASC_SCSI_REQ_Q Virtual or Physical Address */
1825 * next_vpa [31:4] Carrier Virtual or Physical Next Pointer
1827 * next_vpa [3:1] Reserved Bits
1828 * next_vpa [0] Done Flag set in Response Queue.
1834 * Mask used to eliminate low 4 bits of carrier 'next_vpa' field.
1836 #define ASC_NEXT_VPA_MASK 0xFFFFFFF0
1838 #define ASC_RQ_DONE 0x00000001
1839 #define ASC_RQ_GOOD 0x00000002
1840 #define ASC_CQ_STOPPER 0x00000000
1842 #define ASC_GET_CARRP(carrp) ((carrp) & ASC_NEXT_VPA_MASK)
1844 #define ADV_CARRIER_NUM_PAGE_CROSSING \
1845 (((ADV_CARRIER_COUNT * sizeof(ADV_CARR_T)) + \
1846 (ADV_PAGE_SIZE - 1))/ADV_PAGE_SIZE)
1848 #define ADV_CARRIER_BUFSIZE \
1849 ((ADV_CARRIER_COUNT + ADV_CARRIER_NUM_PAGE_CROSSING) * sizeof(ADV_CARR_T))
1852 * ASC_SCSI_REQ_Q 'a_flag' definitions
1854 * The Adv Library should limit use to the lower nibble (4 bits) of
1855 * a_flag. Drivers are free to use the upper nibble (4 bits) of a_flag.
1857 #define ADV_POLL_REQUEST 0x01 /* poll for request completion */
1858 #define ADV_SCSIQ_DONE 0x02 /* request done */
1859 #define ADV_DONT_RETRY 0x08 /* don't do retry */
1861 #define ADV_CHIP_ASC3550 0x01 /* Ultra-Wide IC */
1862 #define ADV_CHIP_ASC38C0800 0x02 /* Ultra2-Wide/LVD IC */
1863 #define ADV_CHIP_ASC38C1600 0x03 /* Ultra3-Wide/LVD2 IC */
1866 * Adapter temporary configuration structure
1868 * This structure can be discarded after initialization. Don't add
1869 * fields here needed after initialization.
1871 * Field naming convention:
1873 * *_enable indicates the field enables or disables a feature. The
1874 * value of the field is never reset.
1876 typedef struct adv_dvc_cfg {
1877 ushort disc_enable; /* enable disconnection */
1878 uchar chip_version; /* chip version */
1879 uchar termination; /* Term. Ctrl. bits 6-5 of SCSI_CFG1 register */
1880 ushort lib_version; /* Adv Library version number */
1881 ushort control_flag; /* Microcode Control Flag */
1882 ushort mcode_date; /* Microcode date */
1883 ushort mcode_version; /* Microcode version */
1884 ushort serial1; /* EEPROM serial number word 1 */
1885 ushort serial2; /* EEPROM serial number word 2 */
1886 ushort serial3; /* EEPROM serial number word 3 */
1890 struct adv_scsi_req_q;
1893 * Adapter operation variable structure.
1895 * One structure is required per host adapter.
1897 * Field naming convention:
1899 * *_able indicates both whether a feature should be enabled or disabled
1900 * and whether a device isi capable of the feature. At initialization
1901 * this field may be set, but later if a device is found to be incapable
1902 * of the feature, the field is cleared.
1904 typedef struct adv_dvc_var {
1905 AdvPortAddr iop_base; /* I/O port address */
1906 ushort err_code; /* fatal error code */
1907 ushort bios_ctrl; /* BIOS control word, EEPROM word 12 */
1908 ushort wdtr_able; /* try WDTR for a device */
1909 ushort sdtr_able; /* try SDTR for a device */
1910 ushort ultra_able; /* try SDTR Ultra speed for a device */
1911 ushort sdtr_speed1; /* EEPROM SDTR Speed for TID 0-3 */
1912 ushort sdtr_speed2; /* EEPROM SDTR Speed for TID 4-7 */
1913 ushort sdtr_speed3; /* EEPROM SDTR Speed for TID 8-11 */
1914 ushort sdtr_speed4; /* EEPROM SDTR Speed for TID 12-15 */
1915 ushort tagqng_able; /* try tagged queuing with a device */
1916 ushort ppr_able; /* PPR message capable per TID bitmask. */
1917 uchar max_dvc_qng; /* maximum number of tagged commands per device */
1918 ushort start_motor; /* start motor command allowed */
1919 uchar scsi_reset_wait; /* delay in seconds after scsi bus reset */
1920 uchar chip_no; /* should be assigned by caller */
1921 uchar max_host_qng; /* maximum number of Q'ed command allowed */
1922 uchar irq_no; /* IRQ number */
1923 ushort no_scam; /* scam_tolerant of EEPROM */
1924 struct asc_board *drv_ptr; /* driver pointer to private structure */
1925 uchar chip_scsi_id; /* chip SCSI target ID */
1927 uchar bist_err_code;
1928 ADV_CARR_T *carrier_buf;
1929 ADV_CARR_T *carr_freelist; /* Carrier free list. */
1930 ADV_CARR_T *icq_sp; /* Initiator command queue stopper pointer. */
1931 ADV_CARR_T *irq_sp; /* Initiator response queue stopper pointer. */
1932 ushort carr_pending_cnt; /* Count of pending carriers. */
1934 * Note: The following fields will not be used after initialization. The
1935 * driver may discard the buffer after initialization is done.
1937 ADV_DVC_CFG *cfg; /* temporary configuration structure */
1940 #define NO_OF_SG_PER_BLOCK 15
1942 typedef struct asc_sg_block {
1946 uchar sg_cnt; /* Valid entries in block. */
1947 ADV_PADDR sg_ptr; /* Pointer to next sg block. */
1949 ADV_PADDR sg_addr; /* SG element address. */
1950 ADV_DCNT sg_count; /* SG element count. */
1951 } sg_list[NO_OF_SG_PER_BLOCK];
1955 * ADV_SCSI_REQ_Q - microcode request structure
1957 * All fields in this structure up to byte 60 are used by the microcode.
1958 * The microcode makes assumptions about the size and ordering of fields
1959 * in this structure. Do not change the structure definition here without
1960 * coordinating the change with the microcode.
1962 * All fields accessed by microcode must be maintained in little_endian
1965 typedef struct adv_scsi_req_q {
1966 uchar cntl; /* Ucode flags and state (ASC_MC_QC_*). */
1968 uchar target_id; /* Device target identifier. */
1969 uchar target_lun; /* Device target logical unit number. */
1970 ADV_PADDR data_addr; /* Data buffer physical address. */
1971 ADV_DCNT data_cnt; /* Data count. Ucode sets to residual. */
1972 ADV_PADDR sense_addr;
1976 uchar cdb_len; /* SCSI CDB length. Must <= 16 bytes. */
1978 uchar done_status; /* Completion status. */
1979 uchar scsi_status; /* SCSI status byte. */
1980 uchar host_status; /* Ucode host status. */
1981 uchar sg_working_ix;
1982 uchar cdb[12]; /* SCSI CDB bytes 0-11. */
1983 ADV_PADDR sg_real_addr; /* SG list physical address. */
1984 ADV_PADDR scsiq_rptr;
1985 uchar cdb16[4]; /* SCSI CDB bytes 12-15. */
1986 ADV_VADDR scsiq_ptr;
1989 * End of microcode structure - 60 bytes. The rest of the structure
1990 * is used by the Adv Library and ignored by the microcode.
1993 ADV_SG_BLOCK *sg_list_ptr; /* SG list virtual address. */
1994 char *vdata_addr; /* Data buffer virtual address. */
1996 uchar pad[2]; /* Pad out to a word boundary. */
2000 * Microcode idle loop commands
2002 #define IDLE_CMD_COMPLETED 0
2003 #define IDLE_CMD_STOP_CHIP 0x0001
2004 #define IDLE_CMD_STOP_CHIP_SEND_INT 0x0002
2005 #define IDLE_CMD_SEND_INT 0x0004
2006 #define IDLE_CMD_ABORT 0x0008
2007 #define IDLE_CMD_DEVICE_RESET 0x0010
2008 #define IDLE_CMD_SCSI_RESET_START 0x0020 /* Assert SCSI Bus Reset */
2009 #define IDLE_CMD_SCSI_RESET_END 0x0040 /* Deassert SCSI Bus Reset */
2010 #define IDLE_CMD_SCSIREQ 0x0080
2012 #define IDLE_CMD_STATUS_SUCCESS 0x0001
2013 #define IDLE_CMD_STATUS_FAILURE 0x0002
2016 * AdvSendIdleCmd() flag definitions.
2018 #define ADV_NOWAIT 0x01
2021 * Wait loop time out values.
2023 #define SCSI_WAIT_100_MSEC 100UL /* 100 milliseconds */
2024 #define SCSI_US_PER_MSEC 1000 /* microseconds per millisecond */
2025 #define SCSI_MAX_RETRY 10 /* retry count */
2027 #define ADV_ASYNC_RDMA_FAILURE 0x01 /* Fatal RDMA failure. */
2028 #define ADV_ASYNC_SCSI_BUS_RESET_DET 0x02 /* Detected SCSI Bus Reset. */
2029 #define ADV_ASYNC_CARRIER_READY_FAILURE 0x03 /* Carrier Ready failure. */
2030 #define ADV_RDMA_IN_CARR_AND_Q_INVALID 0x04 /* RDMAed-in data invalid. */
2032 #define ADV_HOST_SCSI_BUS_RESET 0x80 /* Host Initiated SCSI Bus Reset. */
2034 /* Read byte from a register. */
2035 #define AdvReadByteRegister(iop_base, reg_off) \
2036 (ADV_MEM_READB((iop_base) + (reg_off)))
2038 /* Write byte to a register. */
2039 #define AdvWriteByteRegister(iop_base, reg_off, byte) \
2040 (ADV_MEM_WRITEB((iop_base) + (reg_off), (byte)))
2042 /* Read word (2 bytes) from a register. */
2043 #define AdvReadWordRegister(iop_base, reg_off) \
2044 (ADV_MEM_READW((iop_base) + (reg_off)))
2046 /* Write word (2 bytes) to a register. */
2047 #define AdvWriteWordRegister(iop_base, reg_off, word) \
2048 (ADV_MEM_WRITEW((iop_base) + (reg_off), (word)))
2050 /* Write dword (4 bytes) to a register. */
2051 #define AdvWriteDWordRegister(iop_base, reg_off, dword) \
2052 (ADV_MEM_WRITEDW((iop_base) + (reg_off), (dword)))
2054 /* Read byte from LRAM. */
2055 #define AdvReadByteLram(iop_base, addr, byte) \
2057 ADV_MEM_WRITEW((iop_base) + IOPW_RAM_ADDR, (addr)); \
2058 (byte) = ADV_MEM_READB((iop_base) + IOPB_RAM_DATA); \
2061 /* Write byte to LRAM. */
2062 #define AdvWriteByteLram(iop_base, addr, byte) \
2063 (ADV_MEM_WRITEW((iop_base) + IOPW_RAM_ADDR, (addr)), \
2064 ADV_MEM_WRITEB((iop_base) + IOPB_RAM_DATA, (byte)))
2066 /* Read word (2 bytes) from LRAM. */
2067 #define AdvReadWordLram(iop_base, addr, word) \
2069 ADV_MEM_WRITEW((iop_base) + IOPW_RAM_ADDR, (addr)); \
2070 (word) = (ADV_MEM_READW((iop_base) + IOPW_RAM_DATA)); \
2073 /* Write word (2 bytes) to LRAM. */
2074 #define AdvWriteWordLram(iop_base, addr, word) \
2075 (ADV_MEM_WRITEW((iop_base) + IOPW_RAM_ADDR, (addr)), \
2076 ADV_MEM_WRITEW((iop_base) + IOPW_RAM_DATA, (word)))
2078 /* Write little-endian double word (4 bytes) to LRAM */
2079 /* Because of unspecified C language ordering don't use auto-increment. */
2080 #define AdvWriteDWordLramNoSwap(iop_base, addr, dword) \
2081 ((ADV_MEM_WRITEW((iop_base) + IOPW_RAM_ADDR, (addr)), \
2082 ADV_MEM_WRITEW((iop_base) + IOPW_RAM_DATA, \
2083 cpu_to_le16((ushort) ((dword) & 0xFFFF)))), \
2084 (ADV_MEM_WRITEW((iop_base) + IOPW_RAM_ADDR, (addr) + 2), \
2085 ADV_MEM_WRITEW((iop_base) + IOPW_RAM_DATA, \
2086 cpu_to_le16((ushort) ((dword >> 16) & 0xFFFF)))))
2088 /* Read word (2 bytes) from LRAM assuming that the address is already set. */
2089 #define AdvReadWordAutoIncLram(iop_base) \
2090 (ADV_MEM_READW((iop_base) + IOPW_RAM_DATA))
2092 /* Write word (2 bytes) to LRAM assuming that the address is already set. */
2093 #define AdvWriteWordAutoIncLram(iop_base, word) \
2094 (ADV_MEM_WRITEW((iop_base) + IOPW_RAM_DATA, (word)))
2097 * Define macro to check for Condor signature.
2099 * Evaluate to ADV_TRUE if a Condor chip is found the specified port
2100 * address 'iop_base'. Otherwise evalue to ADV_FALSE.
2102 #define AdvFindSignature(iop_base) \
2103 (((AdvReadByteRegister((iop_base), IOPB_CHIP_ID_1) == \
2104 ADV_CHIP_ID_BYTE) && \
2105 (AdvReadWordRegister((iop_base), IOPW_CHIP_ID_0) == \
2106 ADV_CHIP_ID_WORD)) ? ADV_TRUE : ADV_FALSE)
2109 * Define macro to Return the version number of the chip at 'iop_base'.
2111 * The second parameter 'bus_type' is currently unused.
2113 #define AdvGetChipVersion(iop_base, bus_type) \
2114 AdvReadByteRegister((iop_base), IOPB_CHIP_TYPE_REV)
2117 * Abort an SRB in the chip's RISC Memory. The 'srb_ptr' argument must
2118 * match the ASC_SCSI_REQ_Q 'srb_ptr' field.
2120 * If the request has not yet been sent to the device it will simply be
2121 * aborted from RISC memory. If the request is disconnected it will be
2122 * aborted on reselection by sending an Abort Message to the target ID.
2125 * ADV_TRUE(1) - Queue was successfully aborted.
2126 * ADV_FALSE(0) - Queue was not found on the active queue list.
2128 #define AdvAbortQueue(asc_dvc, scsiq) \
2129 AdvSendIdleCmd((asc_dvc), (ushort) IDLE_CMD_ABORT, \
2133 * Send a Bus Device Reset Message to the specified target ID.
2135 * All outstanding commands will be purged if sending the
2136 * Bus Device Reset Message is successful.
2139 * ADV_TRUE(1) - All requests on the target are purged.
2140 * ADV_FALSE(0) - Couldn't issue Bus Device Reset Message; Requests
2143 #define AdvResetDevice(asc_dvc, target_id) \
2144 AdvSendIdleCmd((asc_dvc), (ushort) IDLE_CMD_DEVICE_RESET, \
2145 (ADV_DCNT) (target_id))
2148 * SCSI Wide Type definition.
2150 #define ADV_SCSI_BIT_ID_TYPE ushort
2153 * AdvInitScsiTarget() 'cntl_flag' options.
2155 #define ADV_SCAN_LUN 0x01
2156 #define ADV_CAPINFO_NOLUN 0x02
2159 * Convert target id to target id bit mask.
2161 #define ADV_TID_TO_TIDMASK(tid) (0x01 << ((tid) & ADV_MAX_TID))
2164 * ASC_SCSI_REQ_Q 'done_status' and 'host_status' return values.
2167 #define QD_NO_STATUS 0x00 /* Request not completed yet. */
2168 #define QD_NO_ERROR 0x01
2169 #define QD_ABORTED_BY_HOST 0x02
2170 #define QD_WITH_ERROR 0x04
2172 #define QHSTA_NO_ERROR 0x00
2173 #define QHSTA_M_SEL_TIMEOUT 0x11
2174 #define QHSTA_M_DATA_OVER_RUN 0x12
2175 #define QHSTA_M_UNEXPECTED_BUS_FREE 0x13
2176 #define QHSTA_M_QUEUE_ABORTED 0x15
2177 #define QHSTA_M_SXFR_SDMA_ERR 0x16 /* SXFR_STATUS SCSI DMA Error */
2178 #define QHSTA_M_SXFR_SXFR_PERR 0x17 /* SXFR_STATUS SCSI Bus Parity Error */
2179 #define QHSTA_M_RDMA_PERR 0x18 /* RISC PCI DMA parity error */
2180 #define QHSTA_M_SXFR_OFF_UFLW 0x19 /* SXFR_STATUS Offset Underflow */
2181 #define QHSTA_M_SXFR_OFF_OFLW 0x20 /* SXFR_STATUS Offset Overflow */
2182 #define QHSTA_M_SXFR_WD_TMO 0x21 /* SXFR_STATUS Watchdog Timeout */
2183 #define QHSTA_M_SXFR_DESELECTED 0x22 /* SXFR_STATUS Deselected */
2184 /* Note: QHSTA_M_SXFR_XFR_OFLW is identical to QHSTA_M_DATA_OVER_RUN. */
2185 #define QHSTA_M_SXFR_XFR_OFLW 0x12 /* SXFR_STATUS Transfer Overflow */
2186 #define QHSTA_M_SXFR_XFR_PH_ERR 0x24 /* SXFR_STATUS Transfer Phase Error */
2187 #define QHSTA_M_SXFR_UNKNOWN_ERROR 0x25 /* SXFR_STATUS Unknown Error */
2188 #define QHSTA_M_SCSI_BUS_RESET 0x30 /* Request aborted from SBR */
2189 #define QHSTA_M_SCSI_BUS_RESET_UNSOL 0x31 /* Request aborted from unsol. SBR */
2190 #define QHSTA_M_BUS_DEVICE_RESET 0x32 /* Request aborted from BDR */
2191 #define QHSTA_M_DIRECTION_ERR 0x35 /* Data Phase mismatch */
2192 #define QHSTA_M_DIRECTION_ERR_HUNG 0x36 /* Data Phase mismatch and bus hang */
2193 #define QHSTA_M_WTM_TIMEOUT 0x41
2194 #define QHSTA_M_BAD_CMPL_STATUS_IN 0x42
2195 #define QHSTA_M_NO_AUTO_REQ_SENSE 0x43
2196 #define QHSTA_M_AUTO_REQ_SENSE_FAIL 0x44
2197 #define QHSTA_M_INVALID_DEVICE 0x45 /* Bad target ID */
2198 #define QHSTA_M_FROZEN_TIDQ 0x46 /* TID Queue frozen. */
2199 #define QHSTA_M_SGBACKUP_ERROR 0x47 /* Scatter-Gather backup error */
2202 * DvcGetPhyAddr() flag arguments
2204 #define ADV_IS_SCSIQ_FLAG 0x01 /* 'addr' is ASC_SCSI_REQ_Q pointer */
2205 #define ADV_ASCGETSGLIST_VADDR 0x02 /* 'addr' is AscGetSGList() virtual addr */
2206 #define ADV_IS_SENSE_FLAG 0x04 /* 'addr' is sense virtual pointer */
2207 #define ADV_IS_DATA_FLAG 0x08 /* 'addr' is data virtual pointer */
2208 #define ADV_IS_SGLIST_FLAG 0x10 /* 'addr' is sglist virtual pointer */
2209 #define ADV_IS_CARRIER_FLAG 0x20 /* 'addr' is ADV_CARR_T pointer */
2211 /* Return the address that is aligned at the next doubleword >= to 'addr'. */
2212 #define ADV_8BALIGN(addr) (((ulong) (addr) + 0x7) & ~0x7)
2213 #define ADV_16BALIGN(addr) (((ulong) (addr) + 0xF) & ~0xF)
2214 #define ADV_32BALIGN(addr) (((ulong) (addr) + 0x1F) & ~0x1F)
2217 * Total contiguous memory needed for driver SG blocks.
2219 * ADV_MAX_SG_LIST must be defined by a driver. It is the maximum
2220 * number of scatter-gather elements the driver supports in a
2224 #define ADV_SG_LIST_MAX_BYTE_SIZE \
2225 (sizeof(ADV_SG_BLOCK) * \
2226 ((ADV_MAX_SG_LIST + (NO_OF_SG_PER_BLOCK - 1))/NO_OF_SG_PER_BLOCK))
2228 /* Reference Scsi_Host hostdata */
2229 #define ASC_BOARDP(host) ((asc_board_t *) &((host)->hostdata))
2231 /* asc_board_t flags */
2232 #define ASC_HOST_IN_RESET 0x01
2233 #define ASC_IS_WIDE_BOARD 0x04 /* AdvanSys Wide Board */
2234 #define ASC_SELECT_QUEUE_DEPTHS 0x08
2236 #define ASC_NARROW_BOARD(boardp) (((boardp)->flags & ASC_IS_WIDE_BOARD) == 0)
2237 #define ASC_WIDE_BOARD(boardp) ((boardp)->flags & ASC_IS_WIDE_BOARD)
2239 #define NO_ISA_DMA 0xff /* No ISA DMA Channel Used */
2241 #define ASC_INFO_SIZE 128 /* advansys_info() line size */
2243 #ifdef CONFIG_PROC_FS
2244 /* /proc/scsi/advansys/[0...] related definitions */
2245 #define ASC_PRTBUF_SIZE 2048
2246 #define ASC_PRTLINE_SIZE 160
2248 #define ASC_PRT_NEXT() \
2252 if (leftlen == 0) { \
2257 #endif /* CONFIG_PROC_FS */
2259 /* Asc Library return codes */
2262 #define ASC_NOERROR 1
2264 #define ASC_ERROR (-1)
2266 /* struct scsi_cmnd function return codes */
2267 #define STATUS_BYTE(byte) (byte)
2268 #define MSG_BYTE(byte) ((byte) << 8)
2269 #define HOST_BYTE(byte) ((byte) << 16)
2270 #define DRIVER_BYTE(byte) ((byte) << 24)
2272 #ifndef ADVANSYS_STATS
2273 #define ASC_STATS(shost, counter)
2274 #define ASC_STATS_ADD(shost, counter, count)
2275 #else /* ADVANSYS_STATS */
2276 #define ASC_STATS(shost, counter) \
2277 (ASC_BOARDP(shost)->asc_stats.counter++)
2279 #define ASC_STATS_ADD(shost, counter, count) \
2280 (ASC_BOARDP(shost)->asc_stats.counter += (count))
2281 #endif /* ADVANSYS_STATS */
2283 #define ASC_CEILING(val, unit) (((val) + ((unit) - 1))/(unit))
2285 /* If the result wraps when calculating tenths, return 0. */
2286 #define ASC_TENTHS(num, den) \
2287 (((10 * ((num)/(den))) > (((num) * 10)/(den))) ? \
2288 0 : ((((num) * 10)/(den)) - (10 * ((num)/(den)))))
2291 * Display a message to the console.
2293 #define ASC_PRINT(s) \
2295 printk("advansys: "); \
2299 #define ASC_PRINT1(s, a1) \
2301 printk("advansys: "); \
2302 printk((s), (a1)); \
2305 #define ASC_PRINT2(s, a1, a2) \
2307 printk("advansys: "); \
2308 printk((s), (a1), (a2)); \
2311 #define ASC_PRINT3(s, a1, a2, a3) \
2313 printk("advansys: "); \
2314 printk((s), (a1), (a2), (a3)); \
2317 #define ASC_PRINT4(s, a1, a2, a3, a4) \
2319 printk("advansys: "); \
2320 printk((s), (a1), (a2), (a3), (a4)); \
2323 #ifndef ADVANSYS_DEBUG
2325 #define ASC_DBG(lvl, s)
2326 #define ASC_DBG1(lvl, s, a1)
2327 #define ASC_DBG2(lvl, s, a1, a2)
2328 #define ASC_DBG3(lvl, s, a1, a2, a3)
2329 #define ASC_DBG4(lvl, s, a1, a2, a3, a4)
2330 #define ASC_DBG_PRT_SCSI_HOST(lvl, s)
2331 #define ASC_DBG_PRT_SCSI_CMND(lvl, s)
2332 #define ASC_DBG_PRT_ASC_SCSI_Q(lvl, scsiqp)
2333 #define ASC_DBG_PRT_ADV_SCSI_REQ_Q(lvl, scsiqp)
2334 #define ASC_DBG_PRT_ASC_QDONE_INFO(lvl, qdone)
2335 #define ADV_DBG_PRT_ADV_SCSI_REQ_Q(lvl, scsiqp)
2336 #define ASC_DBG_PRT_HEX(lvl, name, start, length)
2337 #define ASC_DBG_PRT_CDB(lvl, cdb, len)
2338 #define ASC_DBG_PRT_SENSE(lvl, sense, len)
2339 #define ASC_DBG_PRT_INQUIRY(lvl, inq, len)
2341 #else /* ADVANSYS_DEBUG */
2344 * Debugging Message Levels:
2346 * 1: High-Level Tracing
2347 * 2-N: Verbose Tracing
2350 #define ASC_DBG(lvl, s) \
2352 if (asc_dbglvl >= (lvl)) { \
2357 #define ASC_DBG1(lvl, s, a1) \
2359 if (asc_dbglvl >= (lvl)) { \
2360 printk((s), (a1)); \
2364 #define ASC_DBG2(lvl, s, a1, a2) \
2366 if (asc_dbglvl >= (lvl)) { \
2367 printk((s), (a1), (a2)); \
2371 #define ASC_DBG3(lvl, s, a1, a2, a3) \
2373 if (asc_dbglvl >= (lvl)) { \
2374 printk((s), (a1), (a2), (a3)); \
2378 #define ASC_DBG4(lvl, s, a1, a2, a3, a4) \
2380 if (asc_dbglvl >= (lvl)) { \
2381 printk((s), (a1), (a2), (a3), (a4)); \
2385 #define ASC_DBG_PRT_SCSI_HOST(lvl, s) \
2387 if (asc_dbglvl >= (lvl)) { \
2388 asc_prt_scsi_host(s); \
2392 #define ASC_DBG_PRT_SCSI_CMND(lvl, s) \
2394 if (asc_dbglvl >= (lvl)) { \
2395 asc_prt_scsi_cmnd(s); \
2399 #define ASC_DBG_PRT_ASC_SCSI_Q(lvl, scsiqp) \
2401 if (asc_dbglvl >= (lvl)) { \
2402 asc_prt_asc_scsi_q(scsiqp); \
2406 #define ASC_DBG_PRT_ASC_QDONE_INFO(lvl, qdone) \
2408 if (asc_dbglvl >= (lvl)) { \
2409 asc_prt_asc_qdone_info(qdone); \
2413 #define ASC_DBG_PRT_ADV_SCSI_REQ_Q(lvl, scsiqp) \
2415 if (asc_dbglvl >= (lvl)) { \
2416 asc_prt_adv_scsi_req_q(scsiqp); \
2420 #define ASC_DBG_PRT_HEX(lvl, name, start, length) \
2422 if (asc_dbglvl >= (lvl)) { \
2423 asc_prt_hex((name), (start), (length)); \
2427 #define ASC_DBG_PRT_CDB(lvl, cdb, len) \
2428 ASC_DBG_PRT_HEX((lvl), "CDB", (uchar *) (cdb), (len));
2430 #define ASC_DBG_PRT_SENSE(lvl, sense, len) \
2431 ASC_DBG_PRT_HEX((lvl), "SENSE", (uchar *) (sense), (len));
2433 #define ASC_DBG_PRT_INQUIRY(lvl, inq, len) \
2434 ASC_DBG_PRT_HEX((lvl), "INQUIRY", (uchar *) (inq), (len));
2435 #endif /* ADVANSYS_DEBUG */
2437 #ifdef ADVANSYS_STATS
2439 /* Per board statistics structure */
2441 /* Driver Entrypoint Statistics */
2442 ADV_DCNT queuecommand; /* # calls to advansys_queuecommand() */
2443 ADV_DCNT reset; /* # calls to advansys_eh_bus_reset() */
2444 ADV_DCNT biosparam; /* # calls to advansys_biosparam() */
2445 ADV_DCNT interrupt; /* # advansys_interrupt() calls */
2446 ADV_DCNT callback; /* # calls to asc/adv_isr_callback() */
2447 ADV_DCNT done; /* # calls to request's scsi_done function */
2448 ADV_DCNT build_error; /* # asc/adv_build_req() ASC_ERROR returns. */
2449 ADV_DCNT adv_build_noreq; /* # adv_build_req() adv_req_t alloc. fail. */
2450 ADV_DCNT adv_build_nosg; /* # adv_build_req() adv_sgblk_t alloc. fail. */
2451 /* AscExeScsiQueue()/AdvExeScsiQueue() Statistics */
2452 ADV_DCNT exe_noerror; /* # ASC_NOERROR returns. */
2453 ADV_DCNT exe_busy; /* # ASC_BUSY returns. */
2454 ADV_DCNT exe_error; /* # ASC_ERROR returns. */
2455 ADV_DCNT exe_unknown; /* # unknown returns. */
2456 /* Data Transfer Statistics */
2457 ADV_DCNT cont_cnt; /* # non-scatter-gather I/O requests received */
2458 ADV_DCNT cont_xfer; /* # contiguous transfer 512-bytes */
2459 ADV_DCNT sg_cnt; /* # scatter-gather I/O requests received */
2460 ADV_DCNT sg_elem; /* # scatter-gather elements */
2461 ADV_DCNT sg_xfer; /* # scatter-gather transfer 512-bytes */
2463 #endif /* ADVANSYS_STATS */
2466 * Adv Library Request Structures
2468 * The following two structures are used to process Wide Board requests.
2470 * The ADV_SCSI_REQ_Q structure in adv_req_t is passed to the Adv Library
2471 * and microcode with the ADV_SCSI_REQ_Q field 'srb_ptr' pointing to the
2472 * adv_req_t. The adv_req_t structure 'cmndp' field in turn points to the
2473 * Mid-Level SCSI request structure.
2475 * Zero or more ADV_SG_BLOCK are used with each ADV_SCSI_REQ_Q. Each
2476 * ADV_SG_BLOCK structure holds 15 scatter-gather elements. Under Linux
2477 * up to 255 scatter-gather elements may be used per request or
2480 * Both structures must be 32 byte aligned.
2482 typedef struct adv_sgblk {
2483 ADV_SG_BLOCK sg_block; /* Sgblock structure. */
2484 uchar align[32]; /* Sgblock structure padding. */
2485 struct adv_sgblk *next_sgblkp; /* Next scatter-gather structure. */
2488 typedef struct adv_req {
2489 ADV_SCSI_REQ_Q scsi_req_q; /* Adv Library request structure. */
2490 uchar align[32]; /* Request structure padding. */
2491 struct scsi_cmnd *cmndp; /* Mid-Level SCSI command pointer. */
2492 adv_sgblk_t *sgblkp; /* Adv Library scatter-gather pointer. */
2493 struct adv_req *next_reqp; /* Next Request Structure. */
2497 * Structure allocated for each board.
2499 * This structure is allocated by scsi_host_alloc() at the end
2500 * of the 'Scsi_Host' structure starting at the 'hostdata'
2501 * field. It is guaranteed to be allocated from DMA-able memory.
2503 typedef struct asc_board {
2505 int id; /* Board Id */
2506 uint flags; /* Board flags */
2508 ASC_DVC_VAR asc_dvc_var; /* Narrow board */
2509 ADV_DVC_VAR adv_dvc_var; /* Wide board */
2512 ASC_DVC_CFG asc_dvc_cfg; /* Narrow board */
2513 ADV_DVC_CFG adv_dvc_cfg; /* Wide board */
2515 ushort asc_n_io_port; /* Number I/O ports. */
2516 ADV_SCSI_BIT_ID_TYPE init_tidmask; /* Target init./valid mask */
2517 ushort reqcnt[ADV_MAX_TID + 1]; /* Starvation request count */
2518 ADV_SCSI_BIT_ID_TYPE queue_full; /* Queue full mask */
2519 ushort queue_full_cnt[ADV_MAX_TID + 1]; /* Queue full count */
2521 ASCEEP_CONFIG asc_eep; /* Narrow EEPROM config. */
2522 ADVEEP_3550_CONFIG adv_3550_eep; /* 3550 EEPROM config. */
2523 ADVEEP_38C0800_CONFIG adv_38C0800_eep; /* 38C0800 EEPROM config. */
2524 ADVEEP_38C1600_CONFIG adv_38C1600_eep; /* 38C1600 EEPROM config. */
2526 ulong last_reset; /* Saved last reset time */
2527 spinlock_t lock; /* Board spinlock */
2528 /* /proc/scsi/advansys/[0...] */
2529 char *prtbuf; /* /proc print buffer */
2530 #ifdef ADVANSYS_STATS
2531 struct asc_stats asc_stats; /* Board statistics */
2532 #endif /* ADVANSYS_STATS */
2534 * The following fields are used only for Narrow Boards.
2536 uchar sdtr_data[ASC_MAX_TID + 1]; /* SDTR information */
2538 * The following fields are used only for Wide Boards.
2540 void __iomem *ioremap_addr; /* I/O Memory remap address. */
2541 ushort ioport; /* I/O Port address. */
2542 ADV_CARR_T *carrp; /* ADV_CARR_T memory block. */
2543 adv_req_t *orig_reqp; /* adv_req_t memory block. */
2544 adv_req_t *adv_reqp; /* Request structures. */
2545 adv_sgblk_t *adv_sgblkp; /* Scatter-gather structures. */
2546 ushort bios_signature; /* BIOS Signature. */
2547 ushort bios_version; /* BIOS Version. */
2548 ushort bios_codeseg; /* BIOS Code Segment. */
2549 ushort bios_codelen; /* BIOS Code Segment Length. */
2552 #define adv_dvc_to_board(adv_dvc) container_of(adv_dvc, struct asc_board, \
2553 dvc_var.adv_dvc_var)
2554 #define adv_dvc_to_pdev(adv_dvc) to_pci_dev(adv_dvc_to_board(adv_dvc)->dev)
2556 /* Number of boards detected in system. */
2557 static int asc_board_count;
2559 /* Overrun buffer used by all narrow boards. */
2560 static uchar overrun_buf[ASC_OVERRUN_BSIZE] = { 0 };
2563 * Global structures required to issue a command.
2565 static ASC_SCSI_Q asc_scsi_q = { {0} };
2566 static ASC_SG_HEAD asc_sg_head = { 0 };
2568 #ifdef ADVANSYS_DEBUG
2569 static int asc_dbglvl = 3;
2572 * asc_prt_scsi_host()
2574 static void asc_prt_scsi_host(struct Scsi_Host *s)
2576 asc_board_t *boardp;
2578 boardp = ASC_BOARDP(s);
2580 printk("Scsi_Host at addr 0x%lx\n", (ulong)s);
2581 printk(" host_busy %u, host_no %d, last_reset %d,\n",
2582 s->host_busy, s->host_no, (unsigned)s->last_reset);
2584 printk(" base 0x%lx, io_port 0x%lx, irq 0x%x,\n",
2585 (ulong)s->base, (ulong)s->io_port, s->irq);
2587 printk(" dma_channel %d, this_id %d, can_queue %d,\n",
2588 s->dma_channel, s->this_id, s->can_queue);
2590 printk(" cmd_per_lun %d, sg_tablesize %d, unchecked_isa_dma %d\n",
2591 s->cmd_per_lun, s->sg_tablesize, s->unchecked_isa_dma);
2593 if (ASC_NARROW_BOARD(boardp)) {
2594 asc_prt_asc_dvc_var(&ASC_BOARDP(s)->dvc_var.asc_dvc_var);
2595 asc_prt_asc_dvc_cfg(&ASC_BOARDP(s)->dvc_cfg.asc_dvc_cfg);
2597 asc_prt_adv_dvc_var(&ASC_BOARDP(s)->dvc_var.adv_dvc_var);
2598 asc_prt_adv_dvc_cfg(&ASC_BOARDP(s)->dvc_cfg.adv_dvc_cfg);
2603 * asc_prt_scsi_cmnd()
2605 static void asc_prt_scsi_cmnd(struct scsi_cmnd *s)
2607 printk("struct scsi_cmnd at addr 0x%lx\n", (ulong)s);
2609 printk(" host 0x%lx, device 0x%lx, target %u, lun %u, channel %u,\n",
2610 (ulong)s->device->host, (ulong)s->device, s->device->id,
2611 s->device->lun, s->device->channel);
2613 asc_prt_hex(" CDB", s->cmnd, s->cmd_len);
2615 printk("sc_data_direction %u, resid %d\n",
2616 s->sc_data_direction, s->resid);
2618 printk(" use_sg %u, sglist_len %u\n", s->use_sg, s->sglist_len);
2620 printk(" serial_number 0x%x, retries %d, allowed %d\n",
2621 (unsigned)s->serial_number, s->retries, s->allowed);
2623 printk(" timeout_per_command %d\n", s->timeout_per_command);
2625 printk(" scsi_done 0x%p, done 0x%p, host_scribble 0x%p, result 0x%x\n",
2626 s->scsi_done, s->done, s->host_scribble, s->result);
2628 printk(" tag %u, pid %u\n", (unsigned)s->tag, (unsigned)s->pid);
2632 * asc_prt_asc_dvc_var()
2634 static void asc_prt_asc_dvc_var(ASC_DVC_VAR *h)
2636 printk("ASC_DVC_VAR at addr 0x%lx\n", (ulong)h);
2638 printk(" iop_base 0x%x, err_code 0x%x, dvc_cntl 0x%x, bug_fix_cntl "
2639 "%d,\n", h->iop_base, h->err_code, h->dvc_cntl, h->bug_fix_cntl);
2641 printk(" bus_type %d, init_sdtr 0x%x,\n", h->bus_type,
2642 (unsigned)h->init_sdtr);
2644 printk(" sdtr_done 0x%x, use_tagged_qng 0x%x, unit_not_ready 0x%x, "
2645 "chip_no 0x%x,\n", (unsigned)h->sdtr_done,
2646 (unsigned)h->use_tagged_qng, (unsigned)h->unit_not_ready,
2647 (unsigned)h->chip_no);
2649 printk(" queue_full_or_busy 0x%x, start_motor 0x%x, scsi_reset_wait "
2650 "%u,\n", (unsigned)h->queue_full_or_busy,
2651 (unsigned)h->start_motor, (unsigned)h->scsi_reset_wait);
2653 printk(" is_in_int %u, max_total_qng %u, cur_total_qng %u, "
2654 "in_critical_cnt %u,\n", (unsigned)h->is_in_int,
2655 (unsigned)h->max_total_qng, (unsigned)h->cur_total_qng,
2656 (unsigned)h->in_critical_cnt);
2658 printk(" last_q_shortage %u, init_state 0x%x, no_scam 0x%x, "
2659 "pci_fix_asyn_xfer 0x%x,\n", (unsigned)h->last_q_shortage,
2660 (unsigned)h->init_state, (unsigned)h->no_scam,
2661 (unsigned)h->pci_fix_asyn_xfer);
2663 printk(" cfg 0x%lx, irq_no 0x%x\n", (ulong)h->cfg, (unsigned)h->irq_no);
2667 * asc_prt_asc_dvc_cfg()
2669 static void asc_prt_asc_dvc_cfg(ASC_DVC_CFG *h)
2671 printk("ASC_DVC_CFG at addr 0x%lx\n", (ulong)h);
2673 printk(" can_tagged_qng 0x%x, cmd_qng_enabled 0x%x,\n",
2674 h->can_tagged_qng, h->cmd_qng_enabled);
2675 printk(" disc_enable 0x%x, sdtr_enable 0x%x,\n",
2676 h->disc_enable, h->sdtr_enable);
2679 (" chip_scsi_id %d, isa_dma_speed %d, isa_dma_channel %d, chip_version %d,\n",
2680 h->chip_scsi_id, h->isa_dma_speed, h->isa_dma_channel,
2684 (" pci_device_id %d, lib_serial_no %u, lib_version %u, mcode_date 0x%x,\n",
2685 to_pci_dev(h->dev)->device, h->lib_serial_no, h->lib_version,
2688 printk(" mcode_version %d, overrun_buf 0x%lx\n",
2689 h->mcode_version, (ulong)h->overrun_buf);
2693 * asc_prt_asc_scsi_q()
2695 static void asc_prt_asc_scsi_q(ASC_SCSI_Q *q)
2700 printk("ASC_SCSI_Q at addr 0x%lx\n", (ulong)q);
2703 (" target_ix 0x%x, target_lun %u, srb_ptr 0x%lx, tag_code 0x%x,\n",
2704 q->q2.target_ix, q->q1.target_lun, (ulong)q->q2.srb_ptr,
2708 (" data_addr 0x%lx, data_cnt %lu, sense_addr 0x%lx, sense_len %u,\n",
2709 (ulong)le32_to_cpu(q->q1.data_addr),
2710 (ulong)le32_to_cpu(q->q1.data_cnt),
2711 (ulong)le32_to_cpu(q->q1.sense_addr), q->q1.sense_len);
2713 printk(" cdbptr 0x%lx, cdb_len %u, sg_head 0x%lx, sg_queue_cnt %u\n",
2714 (ulong)q->cdbptr, q->q2.cdb_len,
2715 (ulong)q->sg_head, q->q1.sg_queue_cnt);
2719 printk("ASC_SG_HEAD at addr 0x%lx\n", (ulong)sgp);
2720 printk(" entry_cnt %u, queue_cnt %u\n", sgp->entry_cnt,
2722 for (i = 0; i < sgp->entry_cnt; i++) {
2723 printk(" [%u]: addr 0x%lx, bytes %lu\n",
2724 i, (ulong)le32_to_cpu(sgp->sg_list[i].addr),
2725 (ulong)le32_to_cpu(sgp->sg_list[i].bytes));
2732 * asc_prt_asc_qdone_info()
2734 static void asc_prt_asc_qdone_info(ASC_QDONE_INFO *q)
2736 printk("ASC_QDONE_INFO at addr 0x%lx\n", (ulong)q);
2737 printk(" srb_ptr 0x%lx, target_ix %u, cdb_len %u, tag_code %u,\n",
2738 (ulong)q->d2.srb_ptr, q->d2.target_ix, q->d2.cdb_len,
2741 (" done_stat 0x%x, host_stat 0x%x, scsi_stat 0x%x, scsi_msg 0x%x\n",
2742 q->d3.done_stat, q->d3.host_stat, q->d3.scsi_stat, q->d3.scsi_msg);
2746 * asc_prt_adv_dvc_var()
2748 * Display an ADV_DVC_VAR structure.
2750 static void asc_prt_adv_dvc_var(ADV_DVC_VAR *h)
2752 printk(" ADV_DVC_VAR at addr 0x%lx\n", (ulong)h);
2754 printk(" iop_base 0x%lx, err_code 0x%x, ultra_able 0x%x\n",
2755 (ulong)h->iop_base, h->err_code, (unsigned)h->ultra_able);
2757 printk(" isr_callback 0x%lx, sdtr_able 0x%x, wdtr_able 0x%x\n",
2758 (ulong)h->isr_callback, (unsigned)h->sdtr_able,
2759 (unsigned)h->wdtr_able);
2761 printk(" start_motor 0x%x, scsi_reset_wait 0x%x, irq_no 0x%x,\n",
2762 (unsigned)h->start_motor,
2763 (unsigned)h->scsi_reset_wait, (unsigned)h->irq_no);
2765 printk(" max_host_qng %u, max_dvc_qng %u, carr_freelist 0x%lxn\n",
2766 (unsigned)h->max_host_qng, (unsigned)h->max_dvc_qng,
2767 (ulong)h->carr_freelist);
2769 printk(" icq_sp 0x%lx, irq_sp 0x%lx\n",
2770 (ulong)h->icq_sp, (ulong)h->irq_sp);
2772 printk(" no_scam 0x%x, tagqng_able 0x%x\n",
2773 (unsigned)h->no_scam, (unsigned)h->tagqng_able);
2775 printk(" chip_scsi_id 0x%x, cfg 0x%lx\n",
2776 (unsigned)h->chip_scsi_id, (ulong)h->cfg);
2780 * asc_prt_adv_dvc_cfg()
2782 * Display an ADV_DVC_CFG structure.
2784 static void asc_prt_adv_dvc_cfg(ADV_DVC_CFG *h)
2786 printk(" ADV_DVC_CFG at addr 0x%lx\n", (ulong)h);
2788 printk(" disc_enable 0x%x, termination 0x%x\n",
2789 h->disc_enable, h->termination);
2791 printk(" chip_version 0x%x, mcode_date 0x%x\n",
2792 h->chip_version, h->mcode_date);
2794 printk(" mcode_version 0x%x, pci_device_id 0x%x, lib_version %u\n",
2795 h->mcode_version, to_pci_dev(h->dev)->device, h->lib_version);
2797 printk(" control_flag 0x%x\n", h->control_flag);
2801 * asc_prt_adv_scsi_req_q()
2803 * Display an ADV_SCSI_REQ_Q structure.
2805 static void asc_prt_adv_scsi_req_q(ADV_SCSI_REQ_Q *q)
2808 struct asc_sg_block *sg_ptr;
2810 printk("ADV_SCSI_REQ_Q at addr 0x%lx\n", (ulong)q);
2812 printk(" target_id %u, target_lun %u, srb_ptr 0x%lx, a_flag 0x%x\n",
2813 q->target_id, q->target_lun, (ulong)q->srb_ptr, q->a_flag);
2815 printk(" cntl 0x%x, data_addr 0x%lx, vdata_addr 0x%lx\n",
2816 q->cntl, (ulong)le32_to_cpu(q->data_addr), (ulong)q->vdata_addr);
2818 printk(" data_cnt %lu, sense_addr 0x%lx, sense_len %u,\n",
2819 (ulong)le32_to_cpu(q->data_cnt),
2820 (ulong)le32_to_cpu(q->sense_addr), q->sense_len);
2823 (" cdb_len %u, done_status 0x%x, host_status 0x%x, scsi_status 0x%x\n",
2824 q->cdb_len, q->done_status, q->host_status, q->scsi_status);
2826 printk(" sg_working_ix 0x%x, target_cmd %u\n",
2827 q->sg_working_ix, q->target_cmd);
2829 printk(" scsiq_rptr 0x%lx, sg_real_addr 0x%lx, sg_list_ptr 0x%lx\n",
2830 (ulong)le32_to_cpu(q->scsiq_rptr),
2831 (ulong)le32_to_cpu(q->sg_real_addr), (ulong)q->sg_list_ptr);
2833 /* Display the request's ADV_SG_BLOCK structures. */
2834 if (q->sg_list_ptr != NULL) {
2838 * 'sg_ptr' is a physical address. Convert it to a virtual
2839 * address by indexing 'sg_blk_cnt' into the virtual address
2840 * array 'sg_list_ptr'.
2842 * XXX - Assumes all SG physical blocks are virtually contiguous.
2845 &(((ADV_SG_BLOCK *)(q->sg_list_ptr))[sg_blk_cnt]);
2846 asc_prt_adv_sgblock(sg_blk_cnt, sg_ptr);
2847 if (sg_ptr->sg_ptr == 0) {
2856 * asc_prt_adv_sgblock()
2858 * Display an ADV_SG_BLOCK structure.
2860 static void asc_prt_adv_sgblock(int sgblockno, ADV_SG_BLOCK *b)
2864 printk(" ASC_SG_BLOCK at addr 0x%lx (sgblockno %d)\n",
2865 (ulong)b, sgblockno);
2866 printk(" sg_cnt %u, sg_ptr 0x%lx\n",
2867 b->sg_cnt, (ulong)le32_to_cpu(b->sg_ptr));
2868 BUG_ON(b->sg_cnt > NO_OF_SG_PER_BLOCK);
2870 BUG_ON(b->sg_cnt != NO_OF_SG_PER_BLOCK);
2871 for (i = 0; i < b->sg_cnt; i++) {
2872 printk(" [%u]: sg_addr 0x%lx, sg_count 0x%lx\n",
2873 i, (ulong)b->sg_list[i].sg_addr,
2874 (ulong)b->sg_list[i].sg_count);
2881 * Print hexadecimal output in 4 byte groupings 32 bytes
2882 * or 8 double-words per line.
2884 static void asc_prt_hex(char *f, uchar *s, int l)
2891 printk("%s: (%d bytes)\n", f, l);
2893 for (i = 0; i < l; i += 32) {
2895 /* Display a maximum of 8 double-words per line. */
2896 if ((k = (l - i) / 4) >= 8) {
2903 for (j = 0; j < k; j++) {
2904 printk(" %2.2X%2.2X%2.2X%2.2X",
2905 (unsigned)s[i + (j * 4)],
2906 (unsigned)s[i + (j * 4) + 1],
2907 (unsigned)s[i + (j * 4) + 2],
2908 (unsigned)s[i + (j * 4) + 3]);
2916 printk(" %2.2X", (unsigned)s[i + (j * 4)]);
2919 printk(" %2.2X%2.2X",
2920 (unsigned)s[i + (j * 4)],
2921 (unsigned)s[i + (j * 4) + 1]);
2924 printk(" %2.2X%2.2X%2.2X",
2925 (unsigned)s[i + (j * 4) + 1],
2926 (unsigned)s[i + (j * 4) + 2],
2927 (unsigned)s[i + (j * 4) + 3]);
2934 #endif /* ADVANSYS_DEBUG */
2939 * Return suitable for printing on the console with the argument
2940 * adapter's configuration information.
2942 * Note: The information line should not exceed ASC_INFO_SIZE bytes,
2943 * otherwise the static 'info' array will be overrun.
2945 static const char *advansys_info(struct Scsi_Host *shost)
2947 static char info[ASC_INFO_SIZE];
2948 asc_board_t *boardp;
2949 ASC_DVC_VAR *asc_dvc_varp;
2950 ADV_DVC_VAR *adv_dvc_varp;
2952 char *widename = NULL;
2954 boardp = ASC_BOARDP(shost);
2955 if (ASC_NARROW_BOARD(boardp)) {
2956 asc_dvc_varp = &boardp->dvc_var.asc_dvc_var;
2957 ASC_DBG(1, "advansys_info: begin\n");
2958 if (asc_dvc_varp->bus_type & ASC_IS_ISA) {
2959 if ((asc_dvc_varp->bus_type & ASC_IS_ISAPNP) ==
2961 busname = "ISA PnP";
2966 "AdvanSys SCSI %s: %s: IO 0x%lX-0x%lX, IRQ 0x%X, DMA 0x%X",
2967 ASC_VERSION, busname,
2968 (ulong)shost->io_port,
2969 (ulong)shost->io_port + ASC_IOADR_GAP - 1,
2970 shost->irq, shost->dma_channel);
2972 if (asc_dvc_varp->bus_type & ASC_IS_VL) {
2974 } else if (asc_dvc_varp->bus_type & ASC_IS_EISA) {
2976 } else if (asc_dvc_varp->bus_type & ASC_IS_PCI) {
2977 if ((asc_dvc_varp->bus_type & ASC_IS_PCI_ULTRA)
2978 == ASC_IS_PCI_ULTRA) {
2979 busname = "PCI Ultra";
2985 ASC_PRINT2("advansys_info: board %d: unknown "
2986 "bus type %d\n", boardp->id,
2987 asc_dvc_varp->bus_type);
2990 "AdvanSys SCSI %s: %s: IO 0x%lX-0x%lX, IRQ 0x%X",
2991 ASC_VERSION, busname, (ulong)shost->io_port,
2992 (ulong)shost->io_port + ASC_IOADR_GAP - 1,
2997 * Wide Adapter Information
2999 * Memory-mapped I/O is used instead of I/O space to access
3000 * the adapter, but display the I/O Port range. The Memory
3001 * I/O address is displayed through the driver /proc file.
3003 adv_dvc_varp = &boardp->dvc_var.adv_dvc_var;
3004 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
3005 widename = "Ultra-Wide";
3006 } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
3007 widename = "Ultra2-Wide";
3009 widename = "Ultra3-Wide";
3012 "AdvanSys SCSI %s: PCI %s: PCIMEM 0x%lX-0x%lX, IRQ 0x%X",
3013 ASC_VERSION, widename, (ulong)adv_dvc_varp->iop_base,
3014 (ulong)adv_dvc_varp->iop_base + boardp->asc_n_io_port - 1, shost->irq);
3016 BUG_ON(strlen(info) >= ASC_INFO_SIZE);
3017 ASC_DBG(1, "advansys_info: end\n");
3021 #ifdef CONFIG_PROC_FS
3025 * If 'cp' is NULL print to the console, otherwise print to a buffer.
3027 * Return 0 if printing to the console, otherwise return the number of
3028 * bytes written to the buffer.
3030 * Note: If any single line is greater than ASC_PRTLINE_SIZE bytes the stack
3031 * will be corrupted. 's[]' is defined to be ASC_PRTLINE_SIZE bytes.
3033 static int asc_prt_line(char *buf, int buflen, char *fmt, ...)
3037 char s[ASC_PRTLINE_SIZE];
3039 va_start(args, fmt);
3040 ret = vsprintf(s, fmt, args);
3041 BUG_ON(ret >= ASC_PRTLINE_SIZE);
3046 ret = min(buflen, ret);
3047 memcpy(buf, s, ret);
3054 * asc_prt_board_devices()
3056 * Print driver information for devices attached to the board.
3058 * Note: no single line should be greater than ASC_PRTLINE_SIZE,
3059 * cf. asc_prt_line().
3061 * Return the number of characters copied into 'cp'. No more than
3062 * 'cplen' characters will be copied to 'cp'.
3064 static int asc_prt_board_devices(struct Scsi_Host *shost, char *cp, int cplen)
3066 asc_board_t *boardp;
3073 boardp = ASC_BOARDP(shost);
3077 len = asc_prt_line(cp, leftlen,
3078 "\nDevice Information for AdvanSys SCSI Host %d:\n",
3082 if (ASC_NARROW_BOARD(boardp)) {
3083 chip_scsi_id = boardp->dvc_cfg.asc_dvc_cfg.chip_scsi_id;
3085 chip_scsi_id = boardp->dvc_var.adv_dvc_var.chip_scsi_id;
3088 len = asc_prt_line(cp, leftlen, "Target IDs Detected:");
3090 for (i = 0; i <= ADV_MAX_TID; i++) {
3091 if (boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) {
3092 len = asc_prt_line(cp, leftlen, " %X,", i);
3096 len = asc_prt_line(cp, leftlen, " (%X=Host Adapter)\n", chip_scsi_id);
3103 * Display Wide Board BIOS Information.
3105 static int asc_prt_adv_bios(struct Scsi_Host *shost, char *cp, int cplen)
3107 asc_board_t *boardp;
3111 ushort major, minor, letter;
3113 boardp = ASC_BOARDP(shost);
3117 len = asc_prt_line(cp, leftlen, "\nROM BIOS Version: ");
3121 * If the BIOS saved a valid signature, then fill in
3122 * the BIOS code segment base address.
3124 if (boardp->bios_signature != 0x55AA) {
3125 len = asc_prt_line(cp, leftlen, "Disabled or Pre-3.1\n");
3127 len = asc_prt_line(cp, leftlen,
3128 "BIOS either disabled or Pre-3.1. If it is pre-3.1, then a newer version\n");
3130 len = asc_prt_line(cp, leftlen,
3131 "can be found at the ConnectCom FTP site: ftp://ftp.connectcom.net/pub\n");
3134 major = (boardp->bios_version >> 12) & 0xF;
3135 minor = (boardp->bios_version >> 8) & 0xF;
3136 letter = (boardp->bios_version & 0xFF);
3138 len = asc_prt_line(cp, leftlen, "%d.%d%c\n",
3140 letter >= 26 ? '?' : letter + 'A');
3144 * Current available ROM BIOS release is 3.1I for UW
3145 * and 3.2I for U2W. This code doesn't differentiate
3146 * UW and U2W boards.
3148 if (major < 3 || (major <= 3 && minor < 1) ||
3149 (major <= 3 && minor <= 1 && letter < ('I' - 'A'))) {
3150 len = asc_prt_line(cp, leftlen,
3151 "Newer version of ROM BIOS is available at the ConnectCom FTP site:\n");
3153 len = asc_prt_line(cp, leftlen,
3154 "ftp://ftp.connectcom.net/pub\n");
3163 * Add serial number to information bar if signature AAh
3164 * is found in at bit 15-9 (7 bits) of word 1.
3166 * Serial Number consists fo 12 alpha-numeric digits.
3168 * 1 - Product type (A,B,C,D..) Word0: 15-13 (3 bits)
3169 * 2 - MFG Location (A,B,C,D..) Word0: 12-10 (3 bits)
3170 * 3-4 - Product ID (0-99) Word0: 9-0 (10 bits)
3171 * 5 - Product revision (A-J) Word0: " "
3173 * Signature Word1: 15-9 (7 bits)
3174 * 6 - Year (0-9) Word1: 8-6 (3 bits) & Word2: 15 (1 bit)
3175 * 7-8 - Week of the year (1-52) Word1: 5-0 (6 bits)
3177 * 9-12 - Serial Number (A001-Z999) Word2: 14-0 (15 bits)
3179 * Note 1: Only production cards will have a serial number.
3181 * Note 2: Signature is most significant 7 bits (0xFE).
3183 * Returns ASC_TRUE if serial number found, otherwise returns ASC_FALSE.
3185 static int asc_get_eeprom_string(ushort *serialnum, uchar *cp)
3189 if ((serialnum[1] & 0xFE00) != ((ushort)0xAA << 8)) {
3193 * First word - 6 digits.
3197 /* Product type - 1st digit. */
3198 if ((*cp = 'A' + ((w & 0xE000) >> 13)) == 'H') {
3199 /* Product type is P=Prototype */
3204 /* Manufacturing location - 2nd digit. */
3205 *cp++ = 'A' + ((w & 0x1C00) >> 10);
3207 /* Product ID - 3rd, 4th digits. */
3209 *cp++ = '0' + (num / 100);
3211 *cp++ = '0' + (num / 10);
3213 /* Product revision - 5th digit. */
3214 *cp++ = 'A' + (num % 10);
3224 * If bit 15 of third word is set, then the
3225 * last digit of the year is greater than 7.
3227 if (serialnum[2] & 0x8000) {
3228 *cp++ = '8' + ((w & 0x1C0) >> 6);
3230 *cp++ = '0' + ((w & 0x1C0) >> 6);
3233 /* Week of year - 7th, 8th digits. */
3235 *cp++ = '0' + num / 10;
3242 w = serialnum[2] & 0x7FFF;
3244 /* Serial number - 9th digit. */
3245 *cp++ = 'A' + (w / 1000);
3247 /* 10th, 11th, 12th digits. */
3249 *cp++ = '0' + num / 100;
3251 *cp++ = '0' + num / 10;
3255 *cp = '\0'; /* Null Terminate the string. */
3261 * asc_prt_asc_board_eeprom()
3263 * Print board EEPROM configuration.
3265 * Note: no single line should be greater than ASC_PRTLINE_SIZE,
3266 * cf. asc_prt_line().
3268 * Return the number of characters copied into 'cp'. No more than
3269 * 'cplen' characters will be copied to 'cp'.
3271 static int asc_prt_asc_board_eeprom(struct Scsi_Host *shost, char *cp, int cplen)
3273 asc_board_t *boardp;
3274 ASC_DVC_VAR *asc_dvc_varp;
3281 int isa_dma_speed[] = { 10, 8, 7, 6, 5, 4, 3, 2 };
3282 #endif /* CONFIG_ISA */
3283 uchar serialstr[13];
3285 boardp = ASC_BOARDP(shost);
3286 asc_dvc_varp = &boardp->dvc_var.asc_dvc_var;
3287 ep = &boardp->eep_config.asc_eep;
3292 len = asc_prt_line(cp, leftlen,
3293 "\nEEPROM Settings for AdvanSys SCSI Host %d:\n",
3297 if (asc_get_eeprom_string((ushort *)&ep->adapter_info[0], serialstr)
3300 asc_prt_line(cp, leftlen, " Serial Number: %s\n",
3304 if (ep->adapter_info[5] == 0xBB) {
3305 len = asc_prt_line(cp, leftlen,
3306 " Default Settings Used for EEPROM-less Adapter.\n");
3309 len = asc_prt_line(cp, leftlen,
3310 " Serial Number Signature Not Present.\n");
3315 len = asc_prt_line(cp, leftlen,
3316 " Host SCSI ID: %u, Host Queue Size: %u, Device Queue Size: %u\n",
3317 ASC_EEP_GET_CHIP_ID(ep), ep->max_total_qng,
3321 len = asc_prt_line(cp, leftlen,
3322 " cntl 0x%x, no_scam 0x%x\n", ep->cntl, ep->no_scam);
3325 len = asc_prt_line(cp, leftlen, " Target ID: ");
3327 for (i = 0; i <= ASC_MAX_TID; i++) {
3328 len = asc_prt_line(cp, leftlen, " %d", i);
3331 len = asc_prt_line(cp, leftlen, "\n");
3334 len = asc_prt_line(cp, leftlen, " Disconnects: ");
3336 for (i = 0; i <= ASC_MAX_TID; i++) {
3337 len = asc_prt_line(cp, leftlen, " %c",
3339 disc_enable & ADV_TID_TO_TIDMASK(i)) ? 'Y' :
3343 len = asc_prt_line(cp, leftlen, "\n");
3346 len = asc_prt_line(cp, leftlen, " Command Queuing: ");
3348 for (i = 0; i <= ASC_MAX_TID; i++) {
3349 len = asc_prt_line(cp, leftlen, " %c",
3351 use_cmd_qng & ADV_TID_TO_TIDMASK(i)) ? 'Y' :
3355 len = asc_prt_line(cp, leftlen, "\n");
3358 len = asc_prt_line(cp, leftlen, " Start Motor: ");
3360 for (i = 0; i <= ASC_MAX_TID; i++) {
3361 len = asc_prt_line(cp, leftlen, " %c",
3363 start_motor & ADV_TID_TO_TIDMASK(i)) ? 'Y' :
3367 len = asc_prt_line(cp, leftlen, "\n");
3370 len = asc_prt_line(cp, leftlen, " Synchronous Transfer:");
3372 for (i = 0; i <= ASC_MAX_TID; i++) {
3373 len = asc_prt_line(cp, leftlen, " %c",
3375 init_sdtr & ADV_TID_TO_TIDMASK(i)) ? 'Y' :
3379 len = asc_prt_line(cp, leftlen, "\n");
3383 if (asc_dvc_varp->bus_type & ASC_IS_ISA) {
3384 len = asc_prt_line(cp, leftlen,
3385 " Host ISA DMA speed: %d MB/S\n",
3386 isa_dma_speed[ASC_EEP_GET_DMA_SPD(ep)]);
3389 #endif /* CONFIG_ISA */
3395 * asc_prt_adv_board_eeprom()
3397 * Print board EEPROM configuration.
3399 * Note: no single line should be greater than ASC_PRTLINE_SIZE,
3400 * cf. asc_prt_line().
3402 * Return the number of characters copied into 'cp'. No more than
3403 * 'cplen' characters will be copied to 'cp'.
3405 static int asc_prt_adv_board_eeprom(struct Scsi_Host *shost, char *cp, int cplen)
3407 asc_board_t *boardp;
3408 ADV_DVC_VAR *adv_dvc_varp;
3414 uchar serialstr[13];
3415 ADVEEP_3550_CONFIG *ep_3550 = NULL;
3416 ADVEEP_38C0800_CONFIG *ep_38C0800 = NULL;
3417 ADVEEP_38C1600_CONFIG *ep_38C1600 = NULL;
3420 ushort sdtr_speed = 0;
3422 boardp = ASC_BOARDP(shost);
3423 adv_dvc_varp = &boardp->dvc_var.adv_dvc_var;
3424 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
3425 ep_3550 = &boardp->eep_config.adv_3550_eep;
3426 } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
3427 ep_38C0800 = &boardp->eep_config.adv_38C0800_eep;
3429 ep_38C1600 = &boardp->eep_config.adv_38C1600_eep;
3435 len = asc_prt_line(cp, leftlen,
3436 "\nEEPROM Settings for AdvanSys SCSI Host %d:\n",
3440 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
3441 wordp = &ep_3550->serial_number_word1;
3442 } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
3443 wordp = &ep_38C0800->serial_number_word1;
3445 wordp = &ep_38C1600->serial_number_word1;
3448 if (asc_get_eeprom_string(wordp, serialstr) == ASC_TRUE) {
3450 asc_prt_line(cp, leftlen, " Serial Number: %s\n",
3454 len = asc_prt_line(cp, leftlen,
3455 " Serial Number Signature Not Present.\n");
3459 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
3460 len = asc_prt_line(cp, leftlen,
3461 " Host SCSI ID: %u, Host Queue Size: %u, Device Queue Size: %u\n",
3462 ep_3550->adapter_scsi_id,
3463 ep_3550->max_host_qng, ep_3550->max_dvc_qng);
3465 } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
3466 len = asc_prt_line(cp, leftlen,
3467 " Host SCSI ID: %u, Host Queue Size: %u, Device Queue Size: %u\n",
3468 ep_38C0800->adapter_scsi_id,
3469 ep_38C0800->max_host_qng,
3470 ep_38C0800->max_dvc_qng);
3473 len = asc_prt_line(cp, leftlen,
3474 " Host SCSI ID: %u, Host Queue Size: %u, Device Queue Size: %u\n",
3475 ep_38C1600->adapter_scsi_id,
3476 ep_38C1600->max_host_qng,
3477 ep_38C1600->max_dvc_qng);
3480 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
3481 word = ep_3550->termination;
3482 } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
3483 word = ep_38C0800->termination_lvd;
3485 word = ep_38C1600->termination_lvd;
3489 termstr = "Low Off/High Off";
3492 termstr = "Low Off/High On";
3495 termstr = "Low On/High On";
3499 termstr = "Automatic";
3503 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
3504 len = asc_prt_line(cp, leftlen,
3505 " termination: %u (%s), bios_ctrl: 0x%x\n",
3506 ep_3550->termination, termstr,
3507 ep_3550->bios_ctrl);
3509 } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
3510 len = asc_prt_line(cp, leftlen,
3511 " termination: %u (%s), bios_ctrl: 0x%x\n",
3512 ep_38C0800->termination_lvd, termstr,
3513 ep_38C0800->bios_ctrl);
3516 len = asc_prt_line(cp, leftlen,
3517 " termination: %u (%s), bios_ctrl: 0x%x\n",
3518 ep_38C1600->termination_lvd, termstr,
3519 ep_38C1600->bios_ctrl);
3523 len = asc_prt_line(cp, leftlen, " Target ID: ");
3525 for (i = 0; i <= ADV_MAX_TID; i++) {
3526 len = asc_prt_line(cp, leftlen, " %X", i);
3529 len = asc_prt_line(cp, leftlen, "\n");
3532 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
3533 word = ep_3550->disc_enable;
3534 } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
3535 word = ep_38C0800->disc_enable;
3537 word = ep_38C1600->disc_enable;
3539 len = asc_prt_line(cp, leftlen, " Disconnects: ");
3541 for (i = 0; i <= ADV_MAX_TID; i++) {
3542 len = asc_prt_line(cp, leftlen, " %c",
3543 (word & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
3546 len = asc_prt_line(cp, leftlen, "\n");
3549 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
3550 word = ep_3550->tagqng_able;
3551 } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
3552 word = ep_38C0800->tagqng_able;
3554 word = ep_38C1600->tagqng_able;
3556 len = asc_prt_line(cp, leftlen, " Command Queuing: ");
3558 for (i = 0; i <= ADV_MAX_TID; i++) {
3559 len = asc_prt_line(cp, leftlen, " %c",
3560 (word & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
3563 len = asc_prt_line(cp, leftlen, "\n");
3566 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
3567 word = ep_3550->start_motor;
3568 } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
3569 word = ep_38C0800->start_motor;
3571 word = ep_38C1600->start_motor;
3573 len = asc_prt_line(cp, leftlen, " Start Motor: ");
3575 for (i = 0; i <= ADV_MAX_TID; i++) {
3576 len = asc_prt_line(cp, leftlen, " %c",
3577 (word & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
3580 len = asc_prt_line(cp, leftlen, "\n");
3583 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
3584 len = asc_prt_line(cp, leftlen, " Synchronous Transfer:");
3586 for (i = 0; i <= ADV_MAX_TID; i++) {
3587 len = asc_prt_line(cp, leftlen, " %c",
3589 sdtr_able & ADV_TID_TO_TIDMASK(i)) ?
3593 len = asc_prt_line(cp, leftlen, "\n");
3597 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
3598 len = asc_prt_line(cp, leftlen, " Ultra Transfer: ");
3600 for (i = 0; i <= ADV_MAX_TID; i++) {
3601 len = asc_prt_line(cp, leftlen, " %c",
3603 ultra_able & ADV_TID_TO_TIDMASK(i))
3607 len = asc_prt_line(cp, leftlen, "\n");
3611 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
3612 word = ep_3550->wdtr_able;
3613 } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
3614 word = ep_38C0800->wdtr_able;
3616 word = ep_38C1600->wdtr_able;
3618 len = asc_prt_line(cp, leftlen, " Wide Transfer: ");
3620 for (i = 0; i <= ADV_MAX_TID; i++) {
3621 len = asc_prt_line(cp, leftlen, " %c",
3622 (word & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
3625 len = asc_prt_line(cp, leftlen, "\n");
3628 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800 ||
3629 adv_dvc_varp->chip_type == ADV_CHIP_ASC38C1600) {
3630 len = asc_prt_line(cp, leftlen,
3631 " Synchronous Transfer Speed (Mhz):\n ");
3633 for (i = 0; i <= ADV_MAX_TID; i++) {
3637 sdtr_speed = adv_dvc_varp->sdtr_speed1;
3638 } else if (i == 4) {
3639 sdtr_speed = adv_dvc_varp->sdtr_speed2;
3640 } else if (i == 8) {
3641 sdtr_speed = adv_dvc_varp->sdtr_speed3;
3642 } else if (i == 12) {
3643 sdtr_speed = adv_dvc_varp->sdtr_speed4;
3645 switch (sdtr_speed & ADV_MAX_TID) {
3668 len = asc_prt_line(cp, leftlen, "%X:%s ", i, speed_str);
3671 len = asc_prt_line(cp, leftlen, "\n ");
3676 len = asc_prt_line(cp, leftlen, "\n");
3684 * asc_prt_driver_conf()
3686 * Note: no single line should be greater than ASC_PRTLINE_SIZE,
3687 * cf. asc_prt_line().
3689 * Return the number of characters copied into 'cp'. No more than
3690 * 'cplen' characters will be copied to 'cp'.
3692 static int asc_prt_driver_conf(struct Scsi_Host *shost, char *cp, int cplen)
3694 asc_board_t *boardp;
3700 boardp = ASC_BOARDP(shost);
3705 len = asc_prt_line(cp, leftlen,
3706 "\nLinux Driver Configuration and Information for AdvanSys SCSI Host %d:\n",
3710 len = asc_prt_line(cp, leftlen,
3711 " host_busy %u, last_reset %u, max_id %u, max_lun %u, max_channel %u\n",
3712 shost->host_busy, shost->last_reset, shost->max_id,
3713 shost->max_lun, shost->max_channel);
3716 len = asc_prt_line(cp, leftlen,
3717 " unique_id %d, can_queue %d, this_id %d, sg_tablesize %u, cmd_per_lun %u\n",
3718 shost->unique_id, shost->can_queue, shost->this_id,
3719 shost->sg_tablesize, shost->cmd_per_lun);
3722 len = asc_prt_line(cp, leftlen,
3723 " unchecked_isa_dma %d, use_clustering %d\n",
3724 shost->unchecked_isa_dma, shost->use_clustering);
3727 len = asc_prt_line(cp, leftlen,
3728 " flags 0x%x, last_reset 0x%x, jiffies 0x%x, asc_n_io_port 0x%x\n",
3729 boardp->flags, boardp->last_reset, jiffies,
3730 boardp->asc_n_io_port);
3733 len = asc_prt_line(cp, leftlen, " io_port 0x%x\n", shost->io_port);
3736 if (ASC_NARROW_BOARD(boardp)) {
3737 chip_scsi_id = boardp->dvc_cfg.asc_dvc_cfg.chip_scsi_id;
3739 chip_scsi_id = boardp->dvc_var.adv_dvc_var.chip_scsi_id;
3746 * asc_prt_asc_board_info()
3748 * Print dynamic board configuration information.
3750 * Note: no single line should be greater than ASC_PRTLINE_SIZE,
3751 * cf. asc_prt_line().
3753 * Return the number of characters copied into 'cp'. No more than
3754 * 'cplen' characters will be copied to 'cp'.
3756 static int asc_prt_asc_board_info(struct Scsi_Host *shost, char *cp, int cplen)
3758 asc_board_t *boardp;
3766 int renegotiate = 0;
3768 boardp = ASC_BOARDP(shost);
3769 v = &boardp->dvc_var.asc_dvc_var;
3770 c = &boardp->dvc_cfg.asc_dvc_cfg;
3771 chip_scsi_id = c->chip_scsi_id;
3776 len = asc_prt_line(cp, leftlen,
3777 "\nAsc Library Configuration and Statistics for AdvanSys SCSI Host %d:\n",
3781 len = asc_prt_line(cp, leftlen,
3782 " chip_version %u, lib_version 0x%x, lib_serial_no %u, mcode_date 0x%x\n",
3783 c->chip_version, c->lib_version, c->lib_serial_no,
3787 len = asc_prt_line(cp, leftlen,
3788 " mcode_version 0x%x, err_code %u\n",
3789 c->mcode_version, v->err_code);
3792 /* Current number of commands waiting for the host. */
3793 len = asc_prt_line(cp, leftlen,
3794 " Total Command Pending: %d\n", v->cur_total_qng);
3797 len = asc_prt_line(cp, leftlen, " Command Queuing:");
3799 for (i = 0; i <= ASC_MAX_TID; i++) {
3800 if ((chip_scsi_id == i) ||
3801 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
3804 len = asc_prt_line(cp, leftlen, " %X:%c",
3807 use_tagged_qng & ADV_TID_TO_TIDMASK(i)) ?
3811 len = asc_prt_line(cp, leftlen, "\n");
3814 /* Current number of commands waiting for a device. */
3815 len = asc_prt_line(cp, leftlen, " Command Queue Pending:");
3817 for (i = 0; i <= ASC_MAX_TID; i++) {
3818 if ((chip_scsi_id == i) ||
3819 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
3822 len = asc_prt_line(cp, leftlen, " %X:%u", i, v->cur_dvc_qng[i]);
3825 len = asc_prt_line(cp, leftlen, "\n");
3828 /* Current limit on number of commands that can be sent to a device. */
3829 len = asc_prt_line(cp, leftlen, " Command Queue Limit:");
3831 for (i = 0; i <= ASC_MAX_TID; i++) {
3832 if ((chip_scsi_id == i) ||
3833 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
3836 len = asc_prt_line(cp, leftlen, " %X:%u", i, v->max_dvc_qng[i]);
3839 len = asc_prt_line(cp, leftlen, "\n");
3842 /* Indicate whether the device has returned queue full status. */
3843 len = asc_prt_line(cp, leftlen, " Command Queue Full:");
3845 for (i = 0; i <= ASC_MAX_TID; i++) {
3846 if ((chip_scsi_id == i) ||
3847 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
3850 if (boardp->queue_full & ADV_TID_TO_TIDMASK(i)) {
3851 len = asc_prt_line(cp, leftlen, " %X:Y-%d",
3852 i, boardp->queue_full_cnt[i]);
3854 len = asc_prt_line(cp, leftlen, " %X:N", i);
3858 len = asc_prt_line(cp, leftlen, "\n");
3861 len = asc_prt_line(cp, leftlen, " Synchronous Transfer:");
3863 for (i = 0; i <= ASC_MAX_TID; i++) {
3864 if ((chip_scsi_id == i) ||
3865 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
3868 len = asc_prt_line(cp, leftlen, " %X:%c",
3871 sdtr_done & ADV_TID_TO_TIDMASK(i)) ? 'Y' :
3875 len = asc_prt_line(cp, leftlen, "\n");
3878 for (i = 0; i <= ASC_MAX_TID; i++) {
3879 uchar syn_period_ix;
3881 if ((chip_scsi_id == i) ||
3882 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0) ||
3883 ((v->init_sdtr & ADV_TID_TO_TIDMASK(i)) == 0)) {
3887 len = asc_prt_line(cp, leftlen, " %X:", i);
3890 if ((boardp->sdtr_data[i] & ASC_SYN_MAX_OFFSET) == 0) {
3891 len = asc_prt_line(cp, leftlen, " Asynchronous");
3895 (boardp->sdtr_data[i] >> 4) & (v->max_sdtr_index -
3898 len = asc_prt_line(cp, leftlen,
3899 " Transfer Period Factor: %d (%d.%d Mhz),",
3900 v->sdtr_period_tbl[syn_period_ix],
3902 v->sdtr_period_tbl[syn_period_ix],
3909 len = asc_prt_line(cp, leftlen, " REQ/ACK Offset: %d",
3911 sdtr_data[i] & ASC_SYN_MAX_OFFSET);
3915 if ((v->sdtr_done & ADV_TID_TO_TIDMASK(i)) == 0) {
3916 len = asc_prt_line(cp, leftlen, "*\n");
3919 len = asc_prt_line(cp, leftlen, "\n");
3925 len = asc_prt_line(cp, leftlen,
3926 " * = Re-negotiation pending before next command.\n");
3934 * asc_prt_adv_board_info()
3936 * Print dynamic board configuration information.
3938 * Note: no single line should be greater than ASC_PRTLINE_SIZE,
3939 * cf. asc_prt_line().
3941 * Return the number of characters copied into 'cp'. No more than
3942 * 'cplen' characters will be copied to 'cp'.
3944 static int asc_prt_adv_board_info(struct Scsi_Host *shost, char *cp, int cplen)
3946 asc_board_t *boardp;
3953 AdvPortAddr iop_base;
3954 ushort chip_scsi_id;
3958 ushort sdtr_able, wdtr_able;
3959 ushort wdtr_done, sdtr_done;
3961 int renegotiate = 0;
3963 boardp = ASC_BOARDP(shost);
3964 v = &boardp->dvc_var.adv_dvc_var;
3965 c = &boardp->dvc_cfg.adv_dvc_cfg;
3966 iop_base = v->iop_base;
3967 chip_scsi_id = v->chip_scsi_id;
3972 len = asc_prt_line(cp, leftlen,
3973 "\nAdv Library Configuration and Statistics for AdvanSys SCSI Host %d:\n",
3977 len = asc_prt_line(cp, leftlen,
3978 " iop_base 0x%lx, cable_detect: %X, err_code %u\n",
3980 AdvReadWordRegister(iop_base,
3981 IOPW_SCSI_CFG1) & CABLE_DETECT,
3985 len = asc_prt_line(cp, leftlen,
3986 " chip_version %u, lib_version 0x%x, mcode_date 0x%x, mcode_version 0x%x\n",
3987 c->chip_version, c->lib_version, c->mcode_date,
3991 AdvReadWordLram(iop_base, ASC_MC_TAGQNG_ABLE, tagqng_able);
3992 len = asc_prt_line(cp, leftlen, " Queuing Enabled:");
3994 for (i = 0; i <= ADV_MAX_TID; i++) {
3995 if ((chip_scsi_id == i) ||
3996 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
4000 len = asc_prt_line(cp, leftlen, " %X:%c",
4002 (tagqng_able & ADV_TID_TO_TIDMASK(i)) ? 'Y' :
4006 len = asc_prt_line(cp, leftlen, "\n");
4009 len = asc_prt_line(cp, leftlen, " Queue Limit:");
4011 for (i = 0; i <= ADV_MAX_TID; i++) {
4012 if ((chip_scsi_id == i) ||
4013 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
4017 AdvReadByteLram(iop_base, ASC_MC_NUMBER_OF_MAX_CMD + i,
4020 len = asc_prt_line(cp, leftlen, " %X:%d", i, lrambyte);
4023 len = asc_prt_line(cp, leftlen, "\n");
4026 len = asc_prt_line(cp, leftlen, " Command Pending:");
4028 for (i = 0; i <= ADV_MAX_TID; i++) {
4029 if ((chip_scsi_id == i) ||
4030 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
4034 AdvReadByteLram(iop_base, ASC_MC_NUMBER_OF_QUEUED_CMD + i,
4037 len = asc_prt_line(cp, leftlen, " %X:%d", i, lrambyte);
4040 len = asc_prt_line(cp, leftlen, "\n");
4043 AdvReadWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able);
4044 len = asc_prt_line(cp, leftlen, " Wide Enabled:");
4046 for (i = 0; i <= ADV_MAX_TID; i++) {
4047 if ((chip_scsi_id == i) ||
4048 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
4052 len = asc_prt_line(cp, leftlen, " %X:%c",
4054 (wdtr_able & ADV_TID_TO_TIDMASK(i)) ? 'Y' :
4058 len = asc_prt_line(cp, leftlen, "\n");
4061 AdvReadWordLram(iop_base, ASC_MC_WDTR_DONE, wdtr_done);
4062 len = asc_prt_line(cp, leftlen, " Transfer Bit Width:");
4064 for (i = 0; i <= ADV_MAX_TID; i++) {
4065 if ((chip_scsi_id == i) ||
4066 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
4070 AdvReadWordLram(iop_base,
4071 ASC_MC_DEVICE_HSHK_CFG_TABLE + (2 * i),
4074 len = asc_prt_line(cp, leftlen, " %X:%d",
4075 i, (lramword & 0x8000) ? 16 : 8);
4078 if ((wdtr_able & ADV_TID_TO_TIDMASK(i)) &&
4079 (wdtr_done & ADV_TID_TO_TIDMASK(i)) == 0) {
4080 len = asc_prt_line(cp, leftlen, "*");
4085 len = asc_prt_line(cp, leftlen, "\n");
4088 AdvReadWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
4089 len = asc_prt_line(cp, leftlen, " Synchronous Enabled:");
4091 for (i = 0; i <= ADV_MAX_TID; i++) {
4092 if ((chip_scsi_id == i) ||
4093 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
4097 len = asc_prt_line(cp, leftlen, " %X:%c",
4099 (sdtr_able & ADV_TID_TO_TIDMASK(i)) ? 'Y' :
4103 len = asc_prt_line(cp, leftlen, "\n");
4106 AdvReadWordLram(iop_base, ASC_MC_SDTR_DONE, sdtr_done);
4107 for (i = 0; i <= ADV_MAX_TID; i++) {
4109 AdvReadWordLram(iop_base,
4110 ASC_MC_DEVICE_HSHK_CFG_TABLE + (2 * i),
4112 lramword &= ~0x8000;
4114 if ((chip_scsi_id == i) ||
4115 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0) ||
4116 ((sdtr_able & ADV_TID_TO_TIDMASK(i)) == 0)) {
4120 len = asc_prt_line(cp, leftlen, " %X:", i);
4123 if ((lramword & 0x1F) == 0) { /* Check for REQ/ACK Offset 0. */
4124 len = asc_prt_line(cp, leftlen, " Asynchronous");
4128 asc_prt_line(cp, leftlen,
4129 " Transfer Period Factor: ");
4132 if ((lramword & 0x1F00) == 0x1100) { /* 80 Mhz */
4134 asc_prt_line(cp, leftlen, "9 (80.0 Mhz),");
4136 } else if ((lramword & 0x1F00) == 0x1000) { /* 40 Mhz */
4138 asc_prt_line(cp, leftlen, "10 (40.0 Mhz),");
4140 } else { /* 20 Mhz or below. */
4142 period = (((lramword >> 8) * 25) + 50) / 4;
4144 if (period == 0) { /* Should never happen. */
4146 asc_prt_line(cp, leftlen,
4150 len = asc_prt_line(cp, leftlen,
4152 period, 250 / period,
4159 len = asc_prt_line(cp, leftlen, " REQ/ACK Offset: %d",
4164 if ((sdtr_done & ADV_TID_TO_TIDMASK(i)) == 0) {
4165 len = asc_prt_line(cp, leftlen, "*\n");
4168 len = asc_prt_line(cp, leftlen, "\n");
4174 len = asc_prt_line(cp, leftlen,
4175 " * = Re-negotiation pending before next command.\n");
4185 * Copy proc information to a read buffer taking into account the current
4186 * read offset in the file and the remaining space in the read buffer.
4189 asc_proc_copy(off_t advoffset, off_t offset, char *curbuf, int leftlen,
4190 char *cp, int cplen)
4194 ASC_DBG3(2, "asc_proc_copy: offset %d, advoffset %d, cplen %d\n",
4195 (unsigned)offset, (unsigned)advoffset, cplen);
4196 if (offset <= advoffset) {
4197 /* Read offset below current offset, copy everything. */
4198 cnt = min(cplen, leftlen);
4199 ASC_DBG3(2, "asc_proc_copy: curbuf 0x%lx, cp 0x%lx, cnt %d\n",
4200 (ulong)curbuf, (ulong)cp, cnt);
4201 memcpy(curbuf, cp, cnt);
4202 } else if (offset < advoffset + cplen) {
4203 /* Read offset within current range, partial copy. */
4204 cnt = (advoffset + cplen) - offset;
4205 cp = (cp + cplen) - cnt;
4206 cnt = min(cnt, leftlen);
4207 ASC_DBG3(2, "asc_proc_copy: curbuf 0x%lx, cp 0x%lx, cnt %d\n",
4208 (ulong)curbuf, (ulong)cp, cnt);
4209 memcpy(curbuf, cp, cnt);
4214 #ifdef ADVANSYS_STATS
4216 * asc_prt_board_stats()
4218 * Note: no single line should be greater than ASC_PRTLINE_SIZE,
4219 * cf. asc_prt_line().
4221 * Return the number of characters copied into 'cp'. No more than
4222 * 'cplen' characters will be copied to 'cp'.
4224 static int asc_prt_board_stats(struct Scsi_Host *shost, char *cp, int cplen)
4229 struct asc_stats *s;
4230 asc_board_t *boardp;
4235 boardp = ASC_BOARDP(shost);
4236 s = &boardp->asc_stats;
4238 len = asc_prt_line(cp, leftlen,
4239 "\nLinux Driver Statistics for AdvanSys SCSI Host %d:\n",
4243 len = asc_prt_line(cp, leftlen,
4244 " queuecommand %lu, reset %lu, biosparam %lu, interrupt %lu\n",
4245 s->queuecommand, s->reset, s->biosparam,
4249 len = asc_prt_line(cp, leftlen,
4250 " callback %lu, done %lu, build_error %lu, build_noreq %lu, build_nosg %lu\n",
4251 s->callback, s->done, s->build_error,
4252 s->adv_build_noreq, s->adv_build_nosg);
4255 len = asc_prt_line(cp, leftlen,
4256 " exe_noerror %lu, exe_busy %lu, exe_error %lu, exe_unknown %lu\n",
4257 s->exe_noerror, s->exe_busy, s->exe_error,
4262 * Display data transfer statistics.
4264 if (s->cont_cnt > 0) {
4265 len = asc_prt_line(cp, leftlen, " cont_cnt %lu, ", s->cont_cnt);
4268 len = asc_prt_line(cp, leftlen, "cont_xfer %lu.%01lu kb ",
4270 ASC_TENTHS(s->cont_xfer, 2));
4273 /* Contiguous transfer average size */
4274 len = asc_prt_line(cp, leftlen, "avg_xfer %lu.%01lu kb\n",
4275 (s->cont_xfer / 2) / s->cont_cnt,
4276 ASC_TENTHS((s->cont_xfer / 2), s->cont_cnt));
4280 if (s->sg_cnt > 0) {
4282 len = asc_prt_line(cp, leftlen, " sg_cnt %lu, sg_elem %lu, ",
4283 s->sg_cnt, s->sg_elem);
4286 len = asc_prt_line(cp, leftlen, "sg_xfer %lu.%01lu kb\n",
4287 s->sg_xfer / 2, ASC_TENTHS(s->sg_xfer, 2));
4290 /* Scatter gather transfer statistics */
4291 len = asc_prt_line(cp, leftlen, " avg_num_elem %lu.%01lu, ",
4292 s->sg_elem / s->sg_cnt,
4293 ASC_TENTHS(s->sg_elem, s->sg_cnt));
4296 len = asc_prt_line(cp, leftlen, "avg_elem_size %lu.%01lu kb, ",
4297 (s->sg_xfer / 2) / s->sg_elem,
4298 ASC_TENTHS((s->sg_xfer / 2), s->sg_elem));
4301 len = asc_prt_line(cp, leftlen, "avg_xfer_size %lu.%01lu kb\n",
4302 (s->sg_xfer / 2) / s->sg_cnt,
4303 ASC_TENTHS((s->sg_xfer / 2), s->sg_cnt));
4308 * Display request queuing statistics.
4310 len = asc_prt_line(cp, leftlen,
4311 " Active and Waiting Request Queues (Time Unit: %d HZ):\n",
4317 #endif /* ADVANSYS_STATS */
4320 * advansys_proc_info() - /proc/scsi/advansys/{0,1,2,3,...}
4322 * *buffer: I/O buffer
4323 * **start: if inout == FALSE pointer into buffer where user read should start
4324 * offset: current offset into a /proc/scsi/advansys/[0...] file
4325 * length: length of buffer
4326 * hostno: Scsi_Host host_no
4327 * inout: TRUE - user is writing; FALSE - user is reading
4329 * Return the number of bytes read from or written to a
4330 * /proc/scsi/advansys/[0...] file.
4332 * Note: This function uses the per board buffer 'prtbuf' which is
4333 * allocated when the board is initialized in advansys_detect(). The
4334 * buffer is ASC_PRTBUF_SIZE bytes. The function asc_proc_copy() is
4335 * used to write to the buffer. The way asc_proc_copy() is written
4336 * if 'prtbuf' is too small it will not be overwritten. Instead the
4337 * user just won't get all the available statistics.
4340 advansys_proc_info(struct Scsi_Host *shost, char *buffer, char **start,
4341 off_t offset, int length, int inout)
4343 asc_board_t *boardp;
4352 ASC_DBG(1, "advansys_proc_info: begin\n");
4355 * User write not supported.
4357 if (inout == TRUE) {
4362 * User read of /proc/scsi/advansys/[0...] file.
4365 boardp = ASC_BOARDP(shost);
4367 /* Copy read data starting at the beginning of the buffer. */
4375 * Get board configuration information.
4377 * advansys_info() returns the board string from its own static buffer.
4379 cp = (char *)advansys_info(shost);
4382 /* Copy board information. */
4383 cnt = asc_proc_copy(advoffset, offset, curbuf, leftlen, cp, cplen);
4387 ASC_DBG1(1, "advansys_proc_info: totcnt %d\n", totcnt);
4394 * Display Wide Board BIOS Information.
4396 if (ASC_WIDE_BOARD(boardp)) {
4397 cp = boardp->prtbuf;
4398 cplen = asc_prt_adv_bios(shost, cp, ASC_PRTBUF_SIZE);
4399 BUG_ON(cplen >= ASC_PRTBUF_SIZE);
4400 cnt = asc_proc_copy(advoffset, offset, curbuf, leftlen, cp,
4405 ASC_DBG1(1, "advansys_proc_info: totcnt %d\n", totcnt);
4413 * Display driver information for each device attached to the board.
4415 cp = boardp->prtbuf;
4416 cplen = asc_prt_board_devices(shost, cp, ASC_PRTBUF_SIZE);
4417 BUG_ON(cplen >= ASC_PRTBUF_SIZE);
4418 cnt = asc_proc_copy(advoffset, offset, curbuf, leftlen, cp, cplen);
4422 ASC_DBG1(1, "advansys_proc_info: totcnt %d\n", totcnt);
4429 * Display EEPROM configuration for the board.
4431 cp = boardp->prtbuf;
4432 if (ASC_NARROW_BOARD(boardp)) {
4433 cplen = asc_prt_asc_board_eeprom(shost, cp, ASC_PRTBUF_SIZE);
4435 cplen = asc_prt_adv_board_eeprom(shost, cp, ASC_PRTBUF_SIZE);
4437 BUG_ON(cplen >= ASC_PRTBUF_SIZE);
4438 cnt = asc_proc_copy(advoffset, offset, curbuf, leftlen, cp, cplen);
4442 ASC_DBG1(1, "advansys_proc_info: totcnt %d\n", totcnt);
4449 * Display driver configuration and information for the board.
4451 cp = boardp->prtbuf;
4452 cplen = asc_prt_driver_conf(shost, cp, ASC_PRTBUF_SIZE);
4453 BUG_ON(cplen >= ASC_PRTBUF_SIZE);
4454 cnt = asc_proc_copy(advoffset, offset, curbuf, leftlen, cp, cplen);
4458 ASC_DBG1(1, "advansys_proc_info: totcnt %d\n", totcnt);
4464 #ifdef ADVANSYS_STATS
4466 * Display driver statistics for the board.
4468 cp = boardp->prtbuf;
4469 cplen = asc_prt_board_stats(shost, cp, ASC_PRTBUF_SIZE);
4470 BUG_ON(cplen >= ASC_PRTBUF_SIZE);
4471 cnt = asc_proc_copy(advoffset, offset, curbuf, leftlen, cp, cplen);
4475 ASC_DBG1(1, "advansys_proc_info: totcnt %d\n", totcnt);
4480 #endif /* ADVANSYS_STATS */
4483 * Display Asc Library dynamic configuration information
4486 cp = boardp->prtbuf;
4487 if (ASC_NARROW_BOARD(boardp)) {
4488 cplen = asc_prt_asc_board_info(shost, cp, ASC_PRTBUF_SIZE);
4490 cplen = asc_prt_adv_board_info(shost, cp, ASC_PRTBUF_SIZE);
4492 BUG_ON(cplen >= ASC_PRTBUF_SIZE);
4493 cnt = asc_proc_copy(advoffset, offset, curbuf, leftlen, cp, cplen);
4497 ASC_DBG1(1, "advansys_proc_info: totcnt %d\n", totcnt);
4503 ASC_DBG1(1, "advansys_proc_info: totcnt %d\n", totcnt);
4507 #endif /* CONFIG_PROC_FS */
4509 static void asc_scsi_done(struct scsi_cmnd *scp)
4511 struct asc_board *boardp = ASC_BOARDP(scp->device->host);
4514 dma_unmap_sg(boardp->dev,
4515 (struct scatterlist *)scp->request_buffer,
4516 scp->use_sg, scp->sc_data_direction);
4517 else if (scp->request_bufflen)
4518 dma_unmap_single(boardp->dev, scp->SCp.dma_handle,
4519 scp->request_bufflen, scp->sc_data_direction);
4521 ASC_STATS(scp->device->host, done);
4523 scp->scsi_done(scp);
4526 static void AscSetBank(PortAddr iop_base, uchar bank)
4530 val = AscGetChipControl(iop_base) &
4532 (CC_SINGLE_STEP | CC_TEST | CC_DIAG | CC_SCSI_RESET |
4536 } else if (bank == 2) {
4537 val |= CC_DIAG | CC_BANK_ONE;
4539 val &= ~CC_BANK_ONE;
4541 AscSetChipControl(iop_base, val);
4545 static void AscSetChipIH(PortAddr iop_base, ushort ins_code)
4547 AscSetBank(iop_base, 1);
4548 AscWriteChipIH(iop_base, ins_code);
4549 AscSetBank(iop_base, 0);
4553 static int AscStartChip(PortAddr iop_base)
4555 AscSetChipControl(iop_base, 0);
4556 if ((AscGetChipStatus(iop_base) & CSW_HALTED) != 0) {
4562 static int AscStopChip(PortAddr iop_base)
4567 AscGetChipControl(iop_base) &
4568 (~(CC_SINGLE_STEP | CC_TEST | CC_DIAG));
4569 AscSetChipControl(iop_base, (uchar)(cc_val | CC_HALT));
4570 AscSetChipIH(iop_base, INS_HALT);
4571 AscSetChipIH(iop_base, INS_RFLAG_WTM);
4572 if ((AscGetChipStatus(iop_base) & CSW_HALTED) == 0) {
4578 static int AscIsChipHalted(PortAddr iop_base)
4580 if ((AscGetChipStatus(iop_base) & CSW_HALTED) != 0) {
4581 if ((AscGetChipControl(iop_base) & CC_HALT) != 0) {
4588 static int AscResetChipAndScsiBus(ASC_DVC_VAR *asc_dvc)
4593 iop_base = asc_dvc->iop_base;
4594 while ((AscGetChipStatus(iop_base) & CSW_SCSI_RESET_ACTIVE)
4598 AscStopChip(iop_base);
4599 AscSetChipControl(iop_base, CC_CHIP_RESET | CC_SCSI_RESET | CC_HALT);
4601 AscSetChipIH(iop_base, INS_RFLAG_WTM);
4602 AscSetChipIH(iop_base, INS_HALT);
4603 AscSetChipControl(iop_base, CC_CHIP_RESET | CC_HALT);
4604 AscSetChipControl(iop_base, CC_HALT);
4606 AscSetChipStatus(iop_base, CIW_CLR_SCSI_RESET_INT);
4607 AscSetChipStatus(iop_base, 0);
4608 return (AscIsChipHalted(iop_base));
4611 static int AscFindSignature(PortAddr iop_base)
4615 ASC_DBG2(1, "AscFindSignature: AscGetChipSignatureByte(0x%x) 0x%x\n",
4616 iop_base, AscGetChipSignatureByte(iop_base));
4617 if (AscGetChipSignatureByte(iop_base) == (uchar)ASC_1000_ID1B) {
4619 "AscFindSignature: AscGetChipSignatureWord(0x%x) 0x%x\n",
4620 iop_base, AscGetChipSignatureWord(iop_base));
4621 sig_word = AscGetChipSignatureWord(iop_base);
4622 if ((sig_word == (ushort)ASC_1000_ID0W) ||
4623 (sig_word == (ushort)ASC_1000_ID0W_FIX)) {
4630 static void AscEnableInterrupt(PortAddr iop_base)
4634 cfg = AscGetChipCfgLsw(iop_base);
4635 AscSetChipCfgLsw(iop_base, cfg | ASC_CFG0_HOST_INT_ON);
4639 static void AscDisableInterrupt(PortAddr iop_base)
4643 cfg = AscGetChipCfgLsw(iop_base);
4644 AscSetChipCfgLsw(iop_base, cfg & (~ASC_CFG0_HOST_INT_ON));
4648 static uchar AscReadLramByte(PortAddr iop_base, ushort addr)
4650 unsigned char byte_data;
4651 unsigned short word_data;
4653 if (isodd_word(addr)) {
4654 AscSetChipLramAddr(iop_base, addr - 1);
4655 word_data = AscGetChipLramData(iop_base);
4656 byte_data = (word_data >> 8) & 0xFF;
4658 AscSetChipLramAddr(iop_base, addr);
4659 word_data = AscGetChipLramData(iop_base);
4660 byte_data = word_data & 0xFF;
4665 static ushort AscReadLramWord(PortAddr iop_base, ushort addr)
4669 AscSetChipLramAddr(iop_base, addr);
4670 word_data = AscGetChipLramData(iop_base);
4674 #if CC_VERY_LONG_SG_LIST
4675 static ASC_DCNT AscReadLramDWord(PortAddr iop_base, ushort addr)
4677 ushort val_low, val_high;
4678 ASC_DCNT dword_data;
4680 AscSetChipLramAddr(iop_base, addr);
4681 val_low = AscGetChipLramData(iop_base);
4682 val_high = AscGetChipLramData(iop_base);
4683 dword_data = ((ASC_DCNT) val_high << 16) | (ASC_DCNT) val_low;
4684 return (dword_data);
4686 #endif /* CC_VERY_LONG_SG_LIST */
4689 AscMemWordSetLram(PortAddr iop_base, ushort s_addr, ushort set_wval, int words)
4693 AscSetChipLramAddr(iop_base, s_addr);
4694 for (i = 0; i < words; i++) {
4695 AscSetChipLramData(iop_base, set_wval);
4699 static void AscWriteLramWord(PortAddr iop_base, ushort addr, ushort word_val)
4701 AscSetChipLramAddr(iop_base, addr);
4702 AscSetChipLramData(iop_base, word_val);
4706 static void AscWriteLramByte(PortAddr iop_base, ushort addr, uchar byte_val)
4710 if (isodd_word(addr)) {
4712 word_data = AscReadLramWord(iop_base, addr);
4713 word_data &= 0x00FF;
4714 word_data |= (((ushort)byte_val << 8) & 0xFF00);
4716 word_data = AscReadLramWord(iop_base, addr);
4717 word_data &= 0xFF00;
4718 word_data |= ((ushort)byte_val & 0x00FF);
4720 AscWriteLramWord(iop_base, addr, word_data);
4725 * Copy 2 bytes to LRAM.
4727 * The source data is assumed to be in little-endian order in memory
4728 * and is maintained in little-endian order when written to LRAM.
4731 AscMemWordCopyPtrToLram(PortAddr iop_base,
4732 ushort s_addr, uchar *s_buffer, int words)
4736 AscSetChipLramAddr(iop_base, s_addr);
4737 for (i = 0; i < 2 * words; i += 2) {
4739 * On a little-endian system the second argument below
4740 * produces a little-endian ushort which is written to
4741 * LRAM in little-endian order. On a big-endian system
4742 * the second argument produces a big-endian ushort which
4743 * is "transparently" byte-swapped by outpw() and written
4744 * in little-endian order to LRAM.
4746 outpw(iop_base + IOP_RAM_DATA,
4747 ((ushort)s_buffer[i + 1] << 8) | s_buffer[i]);
4753 * Copy 4 bytes to LRAM.
4755 * The source data is assumed to be in little-endian order in memory
4756 * and is maintained in little-endian order when writen to LRAM.
4759 AscMemDWordCopyPtrToLram(PortAddr iop_base,
4760 ushort s_addr, uchar *s_buffer, int dwords)
4764 AscSetChipLramAddr(iop_base, s_addr);
4765 for (i = 0; i < 4 * dwords; i += 4) {
4766 outpw(iop_base + IOP_RAM_DATA, ((ushort)s_buffer[i + 1] << 8) | s_buffer[i]); /* LSW */
4767 outpw(iop_base + IOP_RAM_DATA, ((ushort)s_buffer[i + 3] << 8) | s_buffer[i + 2]); /* MSW */
4773 * Copy 2 bytes from LRAM.
4775 * The source data is assumed to be in little-endian order in LRAM
4776 * and is maintained in little-endian order when written to memory.
4779 AscMemWordCopyPtrFromLram(PortAddr iop_base,
4780 ushort s_addr, uchar *d_buffer, int words)
4785 AscSetChipLramAddr(iop_base, s_addr);
4786 for (i = 0; i < 2 * words; i += 2) {
4787 word = inpw(iop_base + IOP_RAM_DATA);
4788 d_buffer[i] = word & 0xff;
4789 d_buffer[i + 1] = (word >> 8) & 0xff;
4794 static ASC_DCNT AscMemSumLramWord(PortAddr iop_base, ushort s_addr, int words)
4800 for (i = 0; i < words; i++, s_addr += 2) {
4801 sum += AscReadLramWord(iop_base, s_addr);
4806 static ushort AscInitLram(ASC_DVC_VAR *asc_dvc)
4813 iop_base = asc_dvc->iop_base;
4815 AscMemWordSetLram(iop_base, ASC_QADR_BEG, 0,
4816 (ushort)(((int)(asc_dvc->max_total_qng + 2 + 1) *
4818 i = ASC_MIN_ACTIVE_QNO;
4819 s_addr = ASC_QADR_BEG + ASC_QBLK_SIZE;
4820 AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_FWD),
4822 AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_BWD),
4823 (uchar)(asc_dvc->max_total_qng));
4824 AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_QNO),
4827 s_addr += ASC_QBLK_SIZE;
4828 for (; i < asc_dvc->max_total_qng; i++, s_addr += ASC_QBLK_SIZE) {
4829 AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_FWD),
4831 AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_BWD),
4833 AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_QNO),
4836 AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_FWD),
4837 (uchar)ASC_QLINK_END);
4838 AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_BWD),
4839 (uchar)(asc_dvc->max_total_qng - 1));
4840 AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_QNO),
4841 (uchar)asc_dvc->max_total_qng);
4843 s_addr += ASC_QBLK_SIZE;
4844 for (; i <= (uchar)(asc_dvc->max_total_qng + 3);
4845 i++, s_addr += ASC_QBLK_SIZE) {
4846 AscWriteLramByte(iop_base,
4847 (ushort)(s_addr + (ushort)ASC_SCSIQ_B_FWD), i);
4848 AscWriteLramByte(iop_base,
4849 (ushort)(s_addr + (ushort)ASC_SCSIQ_B_BWD), i);
4850 AscWriteLramByte(iop_base,
4851 (ushort)(s_addr + (ushort)ASC_SCSIQ_B_QNO), i);
4857 AscLoadMicroCode(PortAddr iop_base,
4858 ushort s_addr, uchar *mcode_buf, ushort mcode_size)
4861 ushort mcode_word_size;
4862 ushort mcode_chksum;
4864 /* Write the microcode buffer starting at LRAM address 0. */
4865 mcode_word_size = (ushort)(mcode_size >> 1);
4866 AscMemWordSetLram(iop_base, s_addr, 0, mcode_word_size);
4867 AscMemWordCopyPtrToLram(iop_base, s_addr, mcode_buf, mcode_word_size);
4869 chksum = AscMemSumLramWord(iop_base, s_addr, mcode_word_size);
4870 ASC_DBG1(1, "AscLoadMicroCode: chksum 0x%lx\n", (ulong)chksum);
4871 mcode_chksum = (ushort)AscMemSumLramWord(iop_base,
4872 (ushort)ASC_CODE_SEC_BEG,
4873 (ushort)((mcode_size -
4877 ASC_DBG1(1, "AscLoadMicroCode: mcode_chksum 0x%lx\n",
4878 (ulong)mcode_chksum);
4879 AscWriteLramWord(iop_base, ASCV_MCODE_CHKSUM_W, mcode_chksum);
4880 AscWriteLramWord(iop_base, ASCV_MCODE_SIZE_W, mcode_size);
4884 /* Microcode buffer is kept after initialization for error recovery. */
4885 static uchar _asc_mcode_buf[] = {
4886 0x01, 0x03, 0x01, 0x19, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
4887 0x00, 0x00, 0x00, 0x00, 0x0F, 0x0F, 0x0F, 0x0F, 0x0F, 0x0F, 0x0F, 0x0F,
4888 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
4889 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
4890 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
4891 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC3, 0x12, 0x0D, 0x05,
4892 0x01, 0x00, 0x00, 0x00, 0x00, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
4893 0xFF, 0x80, 0xFF, 0xFF, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
4894 0x00, 0x00, 0x00, 0x23, 0x00, 0x00, 0x00, 0x00, 0x00, 0x07, 0x00, 0xFF,
4895 0x00, 0x00, 0x00, 0x00, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00,
4896 0x00, 0x00, 0xE4, 0x88, 0x00, 0x00, 0x00, 0x00, 0x80, 0x73, 0x48, 0x04,
4897 0x36, 0x00, 0x00, 0xA2, 0xC2, 0x00, 0x80, 0x73, 0x03, 0x23, 0x36, 0x40,
4898 0xB6, 0x00, 0x36, 0x00, 0x05, 0xD6, 0x0C, 0xD2, 0x12, 0xDA, 0x00, 0xA2,
4899 0xC2, 0x00, 0x92, 0x80, 0x1E, 0x98, 0x50, 0x00, 0xF5, 0x00, 0x48, 0x98,
4900 0xDF, 0x23, 0x36, 0x60, 0xB6, 0x00, 0x92, 0x80, 0x4F, 0x00, 0xF5, 0x00,
4901 0x48, 0x98, 0xEF, 0x23, 0x36, 0x60, 0xB6, 0x00, 0x92, 0x80, 0x80, 0x62,
4902 0x92, 0x80, 0x00, 0x46, 0x15, 0xEE, 0x13, 0xEA, 0x02, 0x01, 0x09, 0xD8,
4903 0xCD, 0x04, 0x4D, 0x00, 0x00, 0xA3, 0xD6, 0x00, 0xA6, 0x97, 0x7F, 0x23,
4904 0x04, 0x61, 0x84, 0x01, 0xE6, 0x84, 0xD2, 0xC1, 0x80, 0x73, 0xCD, 0x04,
4905 0x4D, 0x00, 0x00, 0xA3, 0xDA, 0x01, 0xA6, 0x97, 0xC6, 0x81, 0xC2, 0x88,
4906 0x80, 0x73, 0x80, 0x77, 0x00, 0x01, 0x01, 0xA1, 0xFE, 0x00, 0x4F, 0x00,
4907 0x84, 0x97, 0x07, 0xA6, 0x08, 0x01, 0x00, 0x33, 0x03, 0x00, 0xC2, 0x88,
4908 0x03, 0x03, 0x01, 0xDE, 0xC2, 0x88, 0xCE, 0x00, 0x69, 0x60, 0xCE, 0x00,
4909 0x02, 0x03, 0x4A, 0x60, 0x00, 0xA2, 0x78, 0x01, 0x80, 0x63, 0x07, 0xA6,
4910 0x24, 0x01, 0x78, 0x81, 0x03, 0x03, 0x80, 0x63, 0xE2, 0x00, 0x07, 0xA6,
4911 0x34, 0x01, 0x00, 0x33, 0x04, 0x00, 0xC2, 0x88, 0x03, 0x07, 0x02, 0x01,
4912 0x04, 0xCA, 0x0D, 0x23, 0x68, 0x98, 0x4D, 0x04, 0x04, 0x85, 0x05, 0xD8,
4913 0x0D, 0x23, 0x68, 0x98, 0xCD, 0x04, 0x15, 0x23, 0xF8, 0x88, 0xFB, 0x23,
4914 0x02, 0x61, 0x82, 0x01, 0x80, 0x63, 0x02, 0x03, 0x06, 0xA3, 0x62, 0x01,
4915 0x00, 0x33, 0x0A, 0x00, 0xC2, 0x88, 0x4E, 0x00, 0x07, 0xA3, 0x6E, 0x01,
4916 0x00, 0x33, 0x0B, 0x00, 0xC2, 0x88, 0xCD, 0x04, 0x36, 0x2D, 0x00, 0x33,
4917 0x1A, 0x00, 0xC2, 0x88, 0x50, 0x04, 0x88, 0x81, 0x06, 0xAB, 0x82, 0x01,
4918 0x88, 0x81, 0x4E, 0x00, 0x07, 0xA3, 0x92, 0x01, 0x50, 0x00, 0x00, 0xA3,
4919 0x3C, 0x01, 0x00, 0x05, 0x7C, 0x81, 0x46, 0x97, 0x02, 0x01, 0x05, 0xC6,
4920 0x04, 0x23, 0xA0, 0x01, 0x15, 0x23, 0xA1, 0x01, 0xBE, 0x81, 0xFD, 0x23,
4921 0x02, 0x61, 0x82, 0x01, 0x0A, 0xDA, 0x4A, 0x00, 0x06, 0x61, 0x00, 0xA0,
4922 0xB4, 0x01, 0x80, 0x63, 0xCD, 0x04, 0x36, 0x2D, 0x00, 0x33, 0x1B, 0x00,
4923 0xC2, 0x88, 0x06, 0x23, 0x68, 0x98, 0xCD, 0x04, 0xE6, 0x84, 0x06, 0x01,
4924 0x00, 0xA2, 0xD4, 0x01, 0x57, 0x60, 0x00, 0xA0, 0xDA, 0x01, 0xE6, 0x84,
4925 0x80, 0x23, 0xA0, 0x01, 0xE6, 0x84, 0x80, 0x73, 0x4B, 0x00, 0x06, 0x61,
4926 0x00, 0xA2, 0x00, 0x02, 0x04, 0x01, 0x0C, 0xDE, 0x02, 0x01, 0x03, 0xCC,
4927 0x4F, 0x00, 0x84, 0x97, 0xFC, 0x81, 0x08, 0x23, 0x02, 0x41, 0x82, 0x01,
4928 0x4F, 0x00, 0x62, 0x97, 0x48, 0x04, 0x84, 0x80, 0xF0, 0x97, 0x00, 0x46,
4929 0x56, 0x00, 0x03, 0xC0, 0x01, 0x23, 0xE8, 0x00, 0x81, 0x73, 0x06, 0x29,
4930 0x03, 0x42, 0x06, 0xE2, 0x03, 0xEE, 0x6B, 0xEB, 0x11, 0x23, 0xF8, 0x88,
4931 0x04, 0x98, 0xF0, 0x80, 0x80, 0x73, 0x80, 0x77, 0x07, 0xA4, 0x2A, 0x02,
4932 0x7C, 0x95, 0x06, 0xA6, 0x34, 0x02, 0x03, 0xA6, 0x4C, 0x04, 0x46, 0x82,
4933 0x04, 0x01, 0x03, 0xD8, 0xB4, 0x98, 0x6A, 0x96, 0x46, 0x82, 0xFE, 0x95,
4934 0x80, 0x67, 0x83, 0x03, 0x80, 0x63, 0xB6, 0x2D, 0x02, 0xA6, 0x6C, 0x02,
4935 0x07, 0xA6, 0x5A, 0x02, 0x06, 0xA6, 0x5E, 0x02, 0x03, 0xA6, 0x62, 0x02,
4936 0xC2, 0x88, 0x7C, 0x95, 0x48, 0x82, 0x60, 0x96, 0x48, 0x82, 0x04, 0x23,
4937 0xA0, 0x01, 0x14, 0x23, 0xA1, 0x01, 0x3C, 0x84, 0x04, 0x01, 0x0C, 0xDC,
4938 0xE0, 0x23, 0x25, 0x61, 0xEF, 0x00, 0x14, 0x01, 0x4F, 0x04, 0xA8, 0x01,
4939 0x6F, 0x00, 0xA5, 0x01, 0x03, 0x23, 0xA4, 0x01, 0x06, 0x23, 0x9C, 0x01,
4940 0x24, 0x2B, 0x1C, 0x01, 0x02, 0xA6, 0xAA, 0x02, 0x07, 0xA6, 0x5A, 0x02,
4941 0x06, 0xA6, 0x5E, 0x02, 0x03, 0xA6, 0x20, 0x04, 0x01, 0xA6, 0xB4, 0x02,
4942 0x00, 0xA6, 0xB4, 0x02, 0x00, 0x33, 0x12, 0x00, 0xC2, 0x88, 0x00, 0x0E,
4943 0x80, 0x63, 0x00, 0x43, 0x00, 0xA0, 0x8C, 0x02, 0x4D, 0x04, 0x04, 0x01,
4944 0x0B, 0xDC, 0xE7, 0x23, 0x04, 0x61, 0x84, 0x01, 0x10, 0x31, 0x12, 0x35,
4945 0x14, 0x01, 0xEC, 0x00, 0x6C, 0x38, 0x00, 0x3F, 0x00, 0x00, 0xEA, 0x82,
4946 0x18, 0x23, 0x04, 0x61, 0x18, 0xA0, 0xE2, 0x02, 0x04, 0x01, 0xA2, 0xC8,
4947 0x00, 0x33, 0x1F, 0x00, 0xC2, 0x88, 0x08, 0x31, 0x0A, 0x35, 0x0C, 0x39,
4948 0x0E, 0x3D, 0x7E, 0x98, 0xB6, 0x2D, 0x01, 0xA6, 0x14, 0x03, 0x00, 0xA6,
4949 0x14, 0x03, 0x07, 0xA6, 0x0C, 0x03, 0x06, 0xA6, 0x10, 0x03, 0x03, 0xA6,
4950 0x20, 0x04, 0x02, 0xA6, 0x6C, 0x02, 0x00, 0x33, 0x33, 0x00, 0xC2, 0x88,
4951 0x7C, 0x95, 0xEE, 0x82, 0x60, 0x96, 0xEE, 0x82, 0x82, 0x98, 0x80, 0x42,
4952 0x7E, 0x98, 0x64, 0xE4, 0x04, 0x01, 0x2D, 0xC8, 0x31, 0x05, 0x07, 0x01,
4953 0x00, 0xA2, 0x54, 0x03, 0x00, 0x43, 0x87, 0x01, 0x05, 0x05, 0x86, 0x98,
4954 0x7E, 0x98, 0x00, 0xA6, 0x16, 0x03, 0x07, 0xA6, 0x4C, 0x03, 0x03, 0xA6,
4955 0x3C, 0x04, 0x06, 0xA6, 0x50, 0x03, 0x01, 0xA6, 0x16, 0x03, 0x00, 0x33,
4956 0x25, 0x00, 0xC2, 0x88, 0x7C, 0x95, 0x32, 0x83, 0x60, 0x96, 0x32, 0x83,
4957 0x04, 0x01, 0x10, 0xCE, 0x07, 0xC8, 0x05, 0x05, 0xEB, 0x04, 0x00, 0x33,
4958 0x00, 0x20, 0xC0, 0x20, 0x81, 0x62, 0x72, 0x83, 0x00, 0x01, 0x05, 0x05,
4959 0xFF, 0xA2, 0x7A, 0x03, 0xB1, 0x01, 0x08, 0x23, 0xB2, 0x01, 0x2E, 0x83,
4960 0x05, 0x05, 0x15, 0x01, 0x00, 0xA2, 0x9A, 0x03, 0xEC, 0x00, 0x6E, 0x00,
4961 0x95, 0x01, 0x6C, 0x38, 0x00, 0x3F, 0x00, 0x00, 0x01, 0xA6, 0x96, 0x03,
4962 0x00, 0xA6, 0x96, 0x03, 0x10, 0x84, 0x80, 0x42, 0x7E, 0x98, 0x01, 0xA6,
4963 0xA4, 0x03, 0x00, 0xA6, 0xBC, 0x03, 0x10, 0x84, 0xA8, 0x98, 0x80, 0x42,
4964 0x01, 0xA6, 0xA4, 0x03, 0x07, 0xA6, 0xB2, 0x03, 0xD4, 0x83, 0x7C, 0x95,
4965 0xA8, 0x83, 0x00, 0x33, 0x2F, 0x00, 0xC2, 0x88, 0xA8, 0x98, 0x80, 0x42,
4966 0x00, 0xA6, 0xBC, 0x03, 0x07, 0xA6, 0xCA, 0x03, 0xD4, 0x83, 0x7C, 0x95,
4967 0xC0, 0x83, 0x00, 0x33, 0x26, 0x00, 0xC2, 0x88, 0x38, 0x2B, 0x80, 0x32,
4968 0x80, 0x36, 0x04, 0x23, 0xA0, 0x01, 0x12, 0x23, 0xA1, 0x01, 0x10, 0x84,
4969 0x07, 0xF0, 0x06, 0xA4, 0xF4, 0x03, 0x80, 0x6B, 0x80, 0x67, 0x05, 0x23,
4970 0x83, 0x03, 0x80, 0x63, 0x03, 0xA6, 0x0E, 0x04, 0x07, 0xA6, 0x06, 0x04,
4971 0x06, 0xA6, 0x0A, 0x04, 0x00, 0x33, 0x17, 0x00, 0xC2, 0x88, 0x7C, 0x95,
4972 0xF4, 0x83, 0x60, 0x96, 0xF4, 0x83, 0x20, 0x84, 0x07, 0xF0, 0x06, 0xA4,
4973 0x20, 0x04, 0x80, 0x6B, 0x80, 0x67, 0x05, 0x23, 0x83, 0x03, 0x80, 0x63,
4974 0xB6, 0x2D, 0x03, 0xA6, 0x3C, 0x04, 0x07, 0xA6, 0x34, 0x04, 0x06, 0xA6,
4975 0x38, 0x04, 0x00, 0x33, 0x30, 0x00, 0xC2, 0x88, 0x7C, 0x95, 0x20, 0x84,
4976 0x60, 0x96, 0x20, 0x84, 0x1D, 0x01, 0x06, 0xCC, 0x00, 0x33, 0x00, 0x84,
4977 0xC0, 0x20, 0x00, 0x23, 0xEA, 0x00, 0x81, 0x62, 0xA2, 0x0D, 0x80, 0x63,
4978 0x07, 0xA6, 0x5A, 0x04, 0x00, 0x33, 0x18, 0x00, 0xC2, 0x88, 0x03, 0x03,
4979 0x80, 0x63, 0xA3, 0x01, 0x07, 0xA4, 0x64, 0x04, 0x23, 0x01, 0x00, 0xA2,
4980 0x86, 0x04, 0x0A, 0xA0, 0x76, 0x04, 0xE0, 0x00, 0x00, 0x33, 0x1D, 0x00,
4981 0xC2, 0x88, 0x0B, 0xA0, 0x82, 0x04, 0xE0, 0x00, 0x00, 0x33, 0x1E, 0x00,
4982 0xC2, 0x88, 0x42, 0x23, 0xF8, 0x88, 0x00, 0x23, 0x22, 0xA3, 0xE6, 0x04,
4983 0x08, 0x23, 0x22, 0xA3, 0xA2, 0x04, 0x28, 0x23, 0x22, 0xA3, 0xAE, 0x04,
4984 0x02, 0x23, 0x22, 0xA3, 0xC4, 0x04, 0x42, 0x23, 0xF8, 0x88, 0x4A, 0x00,
4985 0x06, 0x61, 0x00, 0xA0, 0xAE, 0x04, 0x45, 0x23, 0xF8, 0x88, 0x04, 0x98,
4986 0x00, 0xA2, 0xC0, 0x04, 0xB4, 0x98, 0x00, 0x33, 0x00, 0x82, 0xC0, 0x20,
4987 0x81, 0x62, 0xE8, 0x81, 0x47, 0x23, 0xF8, 0x88, 0x04, 0x01, 0x0B, 0xDE,
4988 0x04, 0x98, 0xB4, 0x98, 0x00, 0x33, 0x00, 0x81, 0xC0, 0x20, 0x81, 0x62,
4989 0x14, 0x01, 0x00, 0xA0, 0x00, 0x02, 0x43, 0x23, 0xF8, 0x88, 0x04, 0x23,
4990 0xA0, 0x01, 0x44, 0x23, 0xA1, 0x01, 0x80, 0x73, 0x4D, 0x00, 0x03, 0xA3,
4991 0xF4, 0x04, 0x00, 0x33, 0x27, 0x00, 0xC2, 0x88, 0x04, 0x01, 0x04, 0xDC,
4992 0x02, 0x23, 0xA2, 0x01, 0x04, 0x23, 0xA0, 0x01, 0x04, 0x98, 0x26, 0x95,
4993 0x4B, 0x00, 0xF6, 0x00, 0x4F, 0x04, 0x4F, 0x00, 0x00, 0xA3, 0x22, 0x05,
4994 0x00, 0x05, 0x76, 0x00, 0x06, 0x61, 0x00, 0xA2, 0x1C, 0x05, 0x0A, 0x85,
4995 0x46, 0x97, 0xCD, 0x04, 0x24, 0x85, 0x48, 0x04, 0x84, 0x80, 0x02, 0x01,
4996 0x03, 0xDA, 0x80, 0x23, 0x82, 0x01, 0x34, 0x85, 0x02, 0x23, 0xA0, 0x01,
4997 0x4A, 0x00, 0x06, 0x61, 0x00, 0xA2, 0x40, 0x05, 0x1D, 0x01, 0x04, 0xD6,
4998 0xFF, 0x23, 0x86, 0x41, 0x4B, 0x60, 0xCB, 0x00, 0xFF, 0x23, 0x80, 0x01,
4999 0x49, 0x00, 0x81, 0x01, 0x04, 0x01, 0x02, 0xC8, 0x30, 0x01, 0x80, 0x01,
5000 0xF7, 0x04, 0x03, 0x01, 0x49, 0x04, 0x80, 0x01, 0xC9, 0x00, 0x00, 0x05,
5001 0x00, 0x01, 0xFF, 0xA0, 0x60, 0x05, 0x77, 0x04, 0x01, 0x23, 0xEA, 0x00,
5002 0x5D, 0x00, 0xFE, 0xC7, 0x00, 0x62, 0x00, 0x23, 0xEA, 0x00, 0x00, 0x63,
5003 0x07, 0xA4, 0xF8, 0x05, 0x03, 0x03, 0x02, 0xA0, 0x8E, 0x05, 0xF4, 0x85,
5004 0x00, 0x33, 0x2D, 0x00, 0xC2, 0x88, 0x04, 0xA0, 0xB8, 0x05, 0x80, 0x63,
5005 0x00, 0x23, 0xDF, 0x00, 0x4A, 0x00, 0x06, 0x61, 0x00, 0xA2, 0xA4, 0x05,
5006 0x1D, 0x01, 0x06, 0xD6, 0x02, 0x23, 0x02, 0x41, 0x82, 0x01, 0x50, 0x00,
5007 0x62, 0x97, 0x04, 0x85, 0x04, 0x23, 0x02, 0x41, 0x82, 0x01, 0x04, 0x85,
5008 0x08, 0xA0, 0xBE, 0x05, 0xF4, 0x85, 0x03, 0xA0, 0xC4, 0x05, 0xF4, 0x85,
5009 0x01, 0xA0, 0xCE, 0x05, 0x88, 0x00, 0x80, 0x63, 0xCC, 0x86, 0x07, 0xA0,
5010 0xEE, 0x05, 0x5F, 0x00, 0x00, 0x2B, 0xDF, 0x08, 0x00, 0xA2, 0xE6, 0x05,
5011 0x80, 0x67, 0x80, 0x63, 0x01, 0xA2, 0x7A, 0x06, 0x7C, 0x85, 0x06, 0x23,
5012 0x68, 0x98, 0x48, 0x23, 0xF8, 0x88, 0x07, 0x23, 0x80, 0x00, 0x06, 0x87,
5013 0x80, 0x63, 0x7C, 0x85, 0x00, 0x23, 0xDF, 0x00, 0x00, 0x63, 0x4A, 0x00,
5014 0x06, 0x61, 0x00, 0xA2, 0x36, 0x06, 0x1D, 0x01, 0x16, 0xD4, 0xC0, 0x23,
5015 0x07, 0x41, 0x83, 0x03, 0x80, 0x63, 0x06, 0xA6, 0x1C, 0x06, 0x00, 0x33,
5016 0x37, 0x00, 0xC2, 0x88, 0x1D, 0x01, 0x01, 0xD6, 0x20, 0x23, 0x63, 0x60,
5017 0x83, 0x03, 0x80, 0x63, 0x02, 0x23, 0xDF, 0x00, 0x07, 0xA6, 0x7C, 0x05,
5018 0xEF, 0x04, 0x6F, 0x00, 0x00, 0x63, 0x4B, 0x00, 0x06, 0x41, 0xCB, 0x00,
5019 0x52, 0x00, 0x06, 0x61, 0x00, 0xA2, 0x4E, 0x06, 0x1D, 0x01, 0x03, 0xCA,
5020 0xC0, 0x23, 0x07, 0x41, 0x00, 0x63, 0x1D, 0x01, 0x04, 0xCC, 0x00, 0x33,
5021 0x00, 0x83, 0xC0, 0x20, 0x81, 0x62, 0x80, 0x23, 0x07, 0x41, 0x00, 0x63,
5022 0x80, 0x67, 0x08, 0x23, 0x83, 0x03, 0x80, 0x63, 0x00, 0x63, 0x01, 0x23,
5023 0xDF, 0x00, 0x06, 0xA6, 0x84, 0x06, 0x07, 0xA6, 0x7C, 0x05, 0x80, 0x67,
5024 0x80, 0x63, 0x00, 0x33, 0x00, 0x40, 0xC0, 0x20, 0x81, 0x62, 0x00, 0x63,
5025 0x00, 0x00, 0xFE, 0x95, 0x83, 0x03, 0x80, 0x63, 0x06, 0xA6, 0x94, 0x06,
5026 0x07, 0xA6, 0x7C, 0x05, 0x00, 0x00, 0x01, 0xA0, 0x14, 0x07, 0x00, 0x2B,
5027 0x40, 0x0E, 0x80, 0x63, 0x01, 0x00, 0x06, 0xA6, 0xAA, 0x06, 0x07, 0xA6,
5028 0x7C, 0x05, 0x40, 0x0E, 0x80, 0x63, 0x00, 0x43, 0x00, 0xA0, 0xA2, 0x06,
5029 0x06, 0xA6, 0xBC, 0x06, 0x07, 0xA6, 0x7C, 0x05, 0x80, 0x67, 0x40, 0x0E,
5030 0x80, 0x63, 0x07, 0xA6, 0x7C, 0x05, 0x00, 0x23, 0xDF, 0x00, 0x00, 0x63,
5031 0x07, 0xA6, 0xD6, 0x06, 0x00, 0x33, 0x2A, 0x00, 0xC2, 0x88, 0x03, 0x03,
5032 0x80, 0x63, 0x89, 0x00, 0x0A, 0x2B, 0x07, 0xA6, 0xE8, 0x06, 0x00, 0x33,
5033 0x29, 0x00, 0xC2, 0x88, 0x00, 0x43, 0x00, 0xA2, 0xF4, 0x06, 0xC0, 0x0E,
5034 0x80, 0x63, 0xDE, 0x86, 0xC0, 0x0E, 0x00, 0x33, 0x00, 0x80, 0xC0, 0x20,
5035 0x81, 0x62, 0x04, 0x01, 0x02, 0xDA, 0x80, 0x63, 0x7C, 0x85, 0x80, 0x7B,
5036 0x80, 0x63, 0x06, 0xA6, 0x8C, 0x06, 0x00, 0x33, 0x2C, 0x00, 0xC2, 0x88,
5037 0x0C, 0xA2, 0x2E, 0x07, 0xFE, 0x95, 0x83, 0x03, 0x80, 0x63, 0x06, 0xA6,
5038 0x2C, 0x07, 0x07, 0xA6, 0x7C, 0x05, 0x00, 0x33, 0x3D, 0x00, 0xC2, 0x88,
5039 0x00, 0x00, 0x80, 0x67, 0x83, 0x03, 0x80, 0x63, 0x0C, 0xA0, 0x44, 0x07,
5040 0x07, 0xA6, 0x7C, 0x05, 0xBF, 0x23, 0x04, 0x61, 0x84, 0x01, 0xE6, 0x84,
5041 0x00, 0x63, 0xF0, 0x04, 0x01, 0x01, 0xF1, 0x00, 0x00, 0x01, 0xF2, 0x00,
5042 0x01, 0x05, 0x80, 0x01, 0x72, 0x04, 0x71, 0x00, 0x81, 0x01, 0x70, 0x04,
5043 0x80, 0x05, 0x81, 0x05, 0x00, 0x63, 0xF0, 0x04, 0xF2, 0x00, 0x72, 0x04,
5044 0x01, 0x01, 0xF1, 0x00, 0x70, 0x00, 0x81, 0x01, 0x70, 0x04, 0x71, 0x00,
5045 0x81, 0x01, 0x72, 0x00, 0x80, 0x01, 0x71, 0x04, 0x70, 0x00, 0x80, 0x01,
5046 0x70, 0x04, 0x00, 0x63, 0xF0, 0x04, 0xF2, 0x00, 0x72, 0x04, 0x00, 0x01,
5047 0xF1, 0x00, 0x70, 0x00, 0x80, 0x01, 0x70, 0x04, 0x71, 0x00, 0x80, 0x01,
5048 0x72, 0x00, 0x81, 0x01, 0x71, 0x04, 0x70, 0x00, 0x81, 0x01, 0x70, 0x04,
5049 0x00, 0x63, 0x00, 0x23, 0xB3, 0x01, 0x83, 0x05, 0xA3, 0x01, 0xA2, 0x01,
5050 0xA1, 0x01, 0x01, 0x23, 0xA0, 0x01, 0x00, 0x01, 0xC8, 0x00, 0x03, 0xA1,
5051 0xC4, 0x07, 0x00, 0x33, 0x07, 0x00, 0xC2, 0x88, 0x80, 0x05, 0x81, 0x05,
5052 0x04, 0x01, 0x11, 0xC8, 0x48, 0x00, 0xB0, 0x01, 0xB1, 0x01, 0x08, 0x23,
5053 0xB2, 0x01, 0x05, 0x01, 0x48, 0x04, 0x00, 0x43, 0x00, 0xA2, 0xE4, 0x07,
5054 0x00, 0x05, 0xDA, 0x87, 0x00, 0x01, 0xC8, 0x00, 0xFF, 0x23, 0x80, 0x01,
5055 0x05, 0x05, 0x00, 0x63, 0xF7, 0x04, 0x1A, 0x09, 0xF6, 0x08, 0x6E, 0x04,
5056 0x00, 0x02, 0x80, 0x43, 0x76, 0x08, 0x80, 0x02, 0x77, 0x04, 0x00, 0x63,
5057 0xF7, 0x04, 0x1A, 0x09, 0xF6, 0x08, 0x6E, 0x04, 0x00, 0x02, 0x00, 0xA0,
5058 0x14, 0x08, 0x16, 0x88, 0x00, 0x43, 0x76, 0x08, 0x80, 0x02, 0x77, 0x04,
5059 0x00, 0x63, 0xF3, 0x04, 0x00, 0x23, 0xF4, 0x00, 0x74, 0x00, 0x80, 0x43,
5060 0xF4, 0x00, 0xCF, 0x40, 0x00, 0xA2, 0x44, 0x08, 0x74, 0x04, 0x02, 0x01,
5061 0xF7, 0xC9, 0xF6, 0xD9, 0x00, 0x01, 0x01, 0xA1, 0x24, 0x08, 0x04, 0x98,
5062 0x26, 0x95, 0x24, 0x88, 0x73, 0x04, 0x00, 0x63, 0xF3, 0x04, 0x75, 0x04,
5063 0x5A, 0x88, 0x02, 0x01, 0x04, 0xD8, 0x46, 0x97, 0x04, 0x98, 0x26, 0x95,
5064 0x4A, 0x88, 0x75, 0x00, 0x00, 0xA3, 0x64, 0x08, 0x00, 0x05, 0x4E, 0x88,
5065 0x73, 0x04, 0x00, 0x63, 0x80, 0x7B, 0x80, 0x63, 0x06, 0xA6, 0x76, 0x08,
5066 0x00, 0x33, 0x3E, 0x00, 0xC2, 0x88, 0x80, 0x67, 0x83, 0x03, 0x80, 0x63,
5067 0x00, 0x63, 0x38, 0x2B, 0x9C, 0x88, 0x38, 0x2B, 0x92, 0x88, 0x32, 0x09,
5068 0x31, 0x05, 0x92, 0x98, 0x05, 0x05, 0xB2, 0x09, 0x00, 0x63, 0x00, 0x32,
5069 0x00, 0x36, 0x00, 0x3A, 0x00, 0x3E, 0x00, 0x63, 0x80, 0x32, 0x80, 0x36,
5070 0x80, 0x3A, 0x80, 0x3E, 0xB4, 0x3D, 0x00, 0x63, 0x38, 0x2B, 0x40, 0x32,
5071 0x40, 0x36, 0x40, 0x3A, 0x40, 0x3E, 0x00, 0x63, 0x5A, 0x20, 0xC9, 0x40,
5072 0x00, 0xA0, 0xB4, 0x08, 0x5D, 0x00, 0xFE, 0xC3, 0x00, 0x63, 0x80, 0x73,
5073 0xE6, 0x20, 0x02, 0x23, 0xE8, 0x00, 0x82, 0x73, 0xFF, 0xFD, 0x80, 0x73,
5074 0x13, 0x23, 0xF8, 0x88, 0x66, 0x20, 0xC0, 0x20, 0x04, 0x23, 0xA0, 0x01,
5075 0xA1, 0x23, 0xA1, 0x01, 0x81, 0x62, 0xE2, 0x88, 0x80, 0x73, 0x80, 0x77,
5076 0x68, 0x00, 0x00, 0xA2, 0x80, 0x00, 0x03, 0xC2, 0xF1, 0xC7, 0x41, 0x23,
5077 0xF8, 0x88, 0x11, 0x23, 0xA1, 0x01, 0x04, 0x23, 0xA0, 0x01, 0xE6, 0x84,
5080 static unsigned short _asc_mcode_size = sizeof(_asc_mcode_buf);
5081 static ADV_DCNT _asc_mcode_chksum = 0x012C453FUL;
5083 /* Microcode buffer is kept after initialization for error recovery. */
5084 static unsigned char _adv_asc3550_buf[] = {
5085 0x00, 0x00, 0x00, 0xf2, 0x00, 0xf0, 0x00, 0x16, 0x18, 0xe4, 0x00, 0xfc,
5086 0x01, 0x00, 0x48, 0xe4, 0xbe, 0x18, 0x18, 0x80, 0x03, 0xf6, 0x02, 0x00,
5087 0x00, 0xfa, 0xff, 0xff, 0x28, 0x0e, 0x9e, 0xe7, 0xff, 0x00, 0x82, 0xe7,
5088 0x00, 0xea, 0x00, 0xf6, 0x01, 0xe6, 0x09, 0xe7, 0x55, 0xf0, 0x01, 0xf6,
5089 0x01, 0xfa, 0x08, 0x00, 0x03, 0x00, 0x04, 0x00, 0x18, 0xf4, 0x10, 0x00,
5090 0x00, 0xec, 0x85, 0xf0, 0xbc, 0x00, 0xd5, 0xf0, 0x8e, 0x0c, 0x38, 0x54,
5091 0x00, 0xe6, 0x1e, 0xf0, 0x86, 0xf0, 0xb4, 0x00, 0x98, 0x57, 0xd0, 0x01,
5092 0x0c, 0x1c, 0x3e, 0x1c, 0x0c, 0x00, 0xbb, 0x00, 0xaa, 0x18, 0x02, 0x80,
5093 0x32, 0xf0, 0x01, 0xfc, 0x88, 0x0c, 0xc6, 0x12, 0x02, 0x13, 0x18, 0x40,
5094 0x00, 0x57, 0x01, 0xea, 0x3c, 0x00, 0x6c, 0x01, 0x6e, 0x01, 0x04, 0x12,
5095 0x3e, 0x57, 0x00, 0x80, 0x03, 0xe6, 0xb6, 0x00, 0xc0, 0x00, 0x01, 0x01,
5096 0x3e, 0x01, 0xda, 0x0f, 0x22, 0x10, 0x08, 0x12, 0x02, 0x4a, 0xb9, 0x54,
5097 0x03, 0x58, 0x1b, 0x80, 0x30, 0xe4, 0x4b, 0xe4, 0x20, 0x00, 0x32, 0x00,
5098 0x3e, 0x00, 0x80, 0x00, 0x24, 0x01, 0x3c, 0x01, 0x68, 0x01, 0x6a, 0x01,
5099 0x70, 0x01, 0x72, 0x01, 0x74, 0x01, 0x76, 0x01, 0x78, 0x01, 0x62, 0x0a,
5100 0x92, 0x0c, 0x2c, 0x10, 0x2e, 0x10, 0x06, 0x13, 0x4c, 0x1c, 0xbb, 0x55,
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5396 0xfe, 0xbb, 0x45, 0x4b, 0x00, 0x45, 0x3e, 0x06, 0x78, 0x3d, 0xfe, 0xda,
5397 0x14, 0x01, 0x6e, 0x87, 0xfe, 0x4b, 0x45, 0xe2, 0x2f, 0x07, 0x9a, 0xe1,
5398 0x05, 0xc6, 0x28, 0x84, 0x05, 0x3f, 0x28, 0x34, 0x5e, 0x02, 0x5b, 0xfe,
5399 0xc0, 0x5d, 0xfe, 0xf8, 0x14, 0xfe, 0x03, 0x17, 0x05, 0x50, 0xb4, 0x0c,
5400 0x50, 0x5e, 0x2b, 0x01, 0x08, 0x26, 0x5c, 0x01, 0xfe, 0xaa, 0x14, 0x02,
5401 0x5c, 0x01, 0x08, 0x25, 0x32, 0x1f, 0x44, 0x30, 0x2e, 0xd6, 0x07, 0x06,
5402 0x21, 0x44, 0x01, 0xfe, 0x8e, 0x13, 0xfe, 0x42, 0x58, 0xfe, 0x82, 0x14,
5403 0xfe, 0xa4, 0x14, 0x87, 0xfe, 0x4a, 0xf4, 0x0b, 0x16, 0x44, 0xfe, 0x4a,
5404 0xf4, 0x06, 0xfe, 0x0c, 0x12, 0x2f, 0x07, 0x9a, 0x85, 0x02, 0x5b, 0x05,
5405 0x3f, 0xb4, 0x0c, 0x3f, 0x5e, 0x2b, 0x01, 0x08, 0x26, 0x5c, 0x01, 0xfe,
5406 0xd8, 0x14, 0x02, 0x5c, 0x13, 0x06, 0x65, 0xfe, 0xca, 0x12, 0x26, 0xfe,
5407 0xe0, 0x12, 0x72, 0xf1, 0x01, 0x08, 0x23, 0x72, 0x03, 0x8f, 0xfe, 0xdc,
5408 0x12, 0x25, 0xfe, 0xdc, 0x12, 0x1f, 0xfe, 0xca, 0x12, 0x5e, 0x2b, 0x01,
5409 0x08, 0xfe, 0xd5, 0x10, 0x13, 0x6c, 0xff, 0x02, 0x00, 0x57, 0x48, 0x8b,
5410 0x1c, 0xfe, 0xff, 0x7f, 0xfe, 0x30, 0x56, 0xfe, 0x00, 0x5c, 0x03, 0x13,
5411 0x6c, 0xff, 0x02, 0x00, 0x57, 0x48, 0x8b, 0x1c, 0x3d, 0xfe, 0x30, 0x56,
5412 0xfe, 0x00, 0x5c, 0x03, 0x13, 0x6c, 0xff, 0x02, 0x00, 0x57, 0x48, 0x8b,
5413 0x03, 0x13, 0x6c, 0xff, 0x02, 0x00, 0x57, 0x48, 0x8b, 0xfe, 0x0b, 0x58,
5414 0x03, 0x0a, 0x50, 0x01, 0x82, 0x0a, 0x3f, 0x01, 0x82, 0x03, 0xfc, 0x1c,
5415 0x10, 0xff, 0x03, 0x00, 0x54, 0xfe, 0x00, 0xf4, 0x19, 0x48, 0xfe, 0x00,
5416 0x7d, 0xfe, 0x01, 0x7d, 0xfe, 0x02, 0x7d, 0xfe, 0x03, 0x7c, 0x63, 0x27,
5417 0x0c, 0x52, 0x18, 0x53, 0xbe, 0x56, 0xbf, 0x57, 0x03, 0xfe, 0x62, 0x08,
5418 0xfe, 0x82, 0x4a, 0xfe, 0xe1, 0x1a, 0xfe, 0x83, 0x5a, 0x74, 0x03, 0x01,
5419 0xfe, 0x14, 0x18, 0xfe, 0x42, 0x48, 0x5f, 0x60, 0x89, 0x01, 0x08, 0x1f,
5420 0xfe, 0xa2, 0x14, 0x30, 0x2e, 0xd8, 0x01, 0x08, 0x1f, 0xfe, 0xa2, 0x14,
5421 0x30, 0x2e, 0xfe, 0xe8, 0x0a, 0xfe, 0xc1, 0x59, 0x05, 0xc6, 0x28, 0xfe,
5422 0xcc, 0x12, 0x49, 0x04, 0x1b, 0xfe, 0xc4, 0x13, 0x23, 0x62, 0x1b, 0xe2,
5423 0x4b, 0xc3, 0x64, 0xfe, 0xe8, 0x13, 0x3b, 0x13, 0x06, 0x17, 0xc3, 0x78,
5424 0xdb, 0xfe, 0x78, 0x10, 0xff, 0x02, 0x83, 0x55, 0xa1, 0xff, 0x02, 0x83,
5425 0x55, 0x62, 0x1a, 0xa4, 0xbb, 0xfe, 0x30, 0x00, 0x8e, 0xe4, 0x17, 0x2c,
5426 0x13, 0x06, 0xfe, 0x56, 0x10, 0x62, 0x0b, 0xe1, 0xbb, 0xfe, 0x64, 0x00,
5427 0x8e, 0xe4, 0x0a, 0xfe, 0x64, 0x00, 0x17, 0x93, 0x13, 0x06, 0xfe, 0x28,
5428 0x10, 0x62, 0x06, 0xfe, 0x60, 0x13, 0xbb, 0xfe, 0xc8, 0x00, 0x8e, 0xe4,
5429 0x0a, 0xfe, 0xc8, 0x00, 0x17, 0x4d, 0x13, 0x06, 0x83, 0xbb, 0xfe, 0x90,
5430 0x01, 0xba, 0xfe, 0x4e, 0x14, 0x89, 0xfe, 0x12, 0x10, 0xfe, 0x43, 0xf4,
5431 0x94, 0xfe, 0x56, 0xf0, 0xfe, 0x60, 0x14, 0xfe, 0x04, 0xf4, 0x6c, 0xfe,
5432 0x43, 0xf4, 0x93, 0xfe, 0xf3, 0x10, 0xf9, 0x01, 0xfe, 0x22, 0x13, 0x1c,
5433 0x3d, 0xfe, 0x10, 0x13, 0xfe, 0x00, 0x17, 0xfe, 0x4d, 0xe4, 0x69, 0xba,
5434 0xfe, 0x9c, 0x14, 0xb7, 0x69, 0xfe, 0x1c, 0x10, 0xfe, 0x00, 0x17, 0xfe,
5435 0x4d, 0xe4, 0x19, 0xba, 0xfe, 0x9c, 0x14, 0xb7, 0x19, 0x83, 0x60, 0x23,
5436 0xfe, 0x4d, 0xf4, 0x00, 0xdf, 0x89, 0x13, 0x06, 0xfe, 0xb4, 0x56, 0xfe,
5437 0xc3, 0x58, 0x03, 0x60, 0x13, 0x0b, 0x03, 0x15, 0x06, 0x01, 0x08, 0x26,
5438 0xe5, 0x15, 0x0b, 0x01, 0x08, 0x26, 0xe5, 0x15, 0x1a, 0x01, 0x08, 0x26,
5439 0xe5, 0x72, 0xfe, 0x89, 0x49, 0x01, 0x08, 0x03, 0x15, 0x06, 0x01, 0x08,
5440 0x26, 0xa6, 0x15, 0x1a, 0x01, 0x08, 0x26, 0xa6, 0x15, 0x06, 0x01, 0x08,
5441 0x26, 0xa6, 0xfe, 0x89, 0x49, 0x01, 0x08, 0x26, 0xa6, 0x72, 0xfe, 0x89,
5442 0x4a, 0x01, 0x08, 0x03, 0x60, 0x03, 0x1e, 0xcc, 0x07, 0x06, 0xfe, 0x44,
5443 0x13, 0xad, 0x12, 0xcc, 0xfe, 0x49, 0xf4, 0x00, 0x3b, 0x72, 0x9f, 0x5e,
5444 0xfe, 0x01, 0xec, 0xfe, 0x27, 0x01, 0xf1, 0x01, 0x08, 0x2f, 0x07, 0xfe,
5445 0xe3, 0x00, 0xfe, 0x20, 0x13, 0x1f, 0xfe, 0x5a, 0x15, 0x23, 0x12, 0xcd,
5446 0x01, 0x43, 0x1e, 0xcd, 0x07, 0x06, 0x45, 0x09, 0x4a, 0x06, 0x35, 0x03,
5447 0x0a, 0x42, 0x01, 0x0e, 0xed, 0x88, 0x07, 0x10, 0xa4, 0x0a, 0x80, 0x01,
5448 0x0e, 0x88, 0x0a, 0x51, 0x01, 0x9e, 0x03, 0x0a, 0x80, 0x01, 0x0e, 0x88,
5449 0xfe, 0x80, 0xe7, 0x10, 0x07, 0x10, 0x84, 0xfe, 0x45, 0x58, 0x01, 0xe3,
5450 0x88, 0x03, 0x0a, 0x42, 0x01, 0x0e, 0x88, 0x0a, 0x51, 0x01, 0x9e, 0x03,
5451 0x0a, 0x42, 0x01, 0x0e, 0xfe, 0x80, 0x80, 0xf2, 0xfe, 0x49, 0xe4, 0x10,
5452 0xa4, 0x0a, 0x80, 0x01, 0x0e, 0xf2, 0x0a, 0x51, 0x01, 0x82, 0x03, 0x17,
5453 0x10, 0x71, 0x66, 0xfe, 0x60, 0x01, 0xfe, 0x18, 0xdf, 0xfe, 0x19, 0xde,
5454 0xfe, 0x24, 0x1c, 0xfe, 0x1d, 0xf7, 0x1d, 0x90, 0xfe, 0xf6, 0x15, 0x01,
5455 0xfe, 0xfc, 0x16, 0xe0, 0x91, 0x1d, 0x66, 0xfe, 0x2c, 0x01, 0xfe, 0x2f,
5456 0x19, 0x03, 0xae, 0x21, 0xfe, 0xe6, 0x15, 0xfe, 0xda, 0x10, 0x17, 0x10,
5457 0x71, 0x05, 0xfe, 0x64, 0x01, 0xfe, 0x00, 0xf4, 0x19, 0xfe, 0x18, 0x58,
5458 0x05, 0xfe, 0x66, 0x01, 0xfe, 0x19, 0x58, 0x91, 0x19, 0xfe, 0x3c, 0x90,
5459 0xfe, 0x30, 0xf4, 0x06, 0xfe, 0x3c, 0x50, 0x66, 0xfe, 0x38, 0x00, 0xfe,
5460 0x0f, 0x79, 0xfe, 0x1c, 0xf7, 0x19, 0x90, 0xfe, 0x40, 0x16, 0xfe, 0xb6,
5461 0x14, 0x34, 0x03, 0xae, 0x21, 0xfe, 0x18, 0x16, 0xfe, 0x9c, 0x10, 0x17,
5462 0x10, 0x71, 0xfe, 0x83, 0x5a, 0xfe, 0x18, 0xdf, 0xfe, 0x19, 0xde, 0xfe,
5463 0x1d, 0xf7, 0x38, 0x90, 0xfe, 0x62, 0x16, 0xfe, 0x94, 0x14, 0xfe, 0x10,
5464 0x13, 0x91, 0x38, 0x66, 0x1b, 0xfe, 0xaf, 0x19, 0xfe, 0x98, 0xe7, 0x00,
5465 0x03, 0xae, 0x21, 0xfe, 0x56, 0x16, 0xfe, 0x6c, 0x10, 0x17, 0x10, 0x71,
5466 0xfe, 0x30, 0xbc, 0xfe, 0xb2, 0xbc, 0x91, 0xc5, 0x66, 0x1b, 0xfe, 0x0f,
5467 0x79, 0xfe, 0x1c, 0xf7, 0xc5, 0x90, 0xfe, 0x9a, 0x16, 0xfe, 0x5c, 0x14,
5468 0x34, 0x03, 0xae, 0x21, 0xfe, 0x86, 0x16, 0xfe, 0x42, 0x10, 0xfe, 0x02,
5469 0xf6, 0x10, 0x71, 0xfe, 0x18, 0xfe, 0x54, 0xfe, 0x19, 0xfe, 0x55, 0xfc,
5470 0xfe, 0x1d, 0xf7, 0x4f, 0x90, 0xfe, 0xc0, 0x16, 0xfe, 0x36, 0x14, 0xfe,
5471 0x1c, 0x13, 0x91, 0x4f, 0x47, 0xfe, 0x83, 0x58, 0xfe, 0xaf, 0x19, 0xfe,
5472 0x80, 0xe7, 0x10, 0xfe, 0x81, 0xe7, 0x10, 0x11, 0xfe, 0xdd, 0x00, 0x63,
5473 0x27, 0x03, 0x63, 0x27, 0xfe, 0x12, 0x45, 0x21, 0xfe, 0xb0, 0x16, 0x14,
5474 0x06, 0x37, 0x95, 0xa9, 0x02, 0x29, 0xfe, 0x39, 0xf0, 0xfe, 0x04, 0x17,
5475 0x23, 0x03, 0xfe, 0x7e, 0x18, 0x1c, 0x1a, 0x5d, 0x13, 0x0d, 0x03, 0x71,
5476 0x05, 0xcb, 0x1c, 0x06, 0xfe, 0xef, 0x12, 0xfe, 0xe1, 0x10, 0x78, 0x2c,
5477 0x46, 0x2f, 0x07, 0x2d, 0xfe, 0x3c, 0x13, 0xfe, 0x82, 0x14, 0xfe, 0x42,
5478 0x13, 0x3c, 0x8a, 0x0a, 0x42, 0x01, 0x0e, 0xb0, 0xfe, 0x3e, 0x12, 0xf0,
5479 0xfe, 0x45, 0x48, 0x01, 0xe3, 0xfe, 0x00, 0xcc, 0xb0, 0xfe, 0xf3, 0x13,
5480 0x3d, 0x75, 0x07, 0x10, 0xa3, 0x0a, 0x80, 0x01, 0x0e, 0xf2, 0x01, 0x6f,
5481 0xfe, 0x16, 0x10, 0x07, 0x7e, 0x85, 0xfe, 0x40, 0x14, 0xfe, 0x24, 0x12,
5482 0xf6, 0xfe, 0xd6, 0xf0, 0xfe, 0x24, 0x17, 0x17, 0x0b, 0x03, 0xfe, 0x9c,
5483 0xe7, 0x0b, 0x0f, 0xfe, 0x15, 0x00, 0x59, 0x76, 0x27, 0x01, 0xda, 0x17,
5484 0x06, 0x03, 0x3c, 0x8a, 0x09, 0x4a, 0x1d, 0x35, 0x11, 0x2d, 0x01, 0x6f,
5485 0x17, 0x06, 0x03, 0xfe, 0x38, 0x90, 0xfe, 0xba, 0x90, 0x79, 0xc7, 0x68,
5486 0xc8, 0xfe, 0x48, 0x55, 0x34, 0xfe, 0xc9, 0x55, 0x03, 0x1e, 0x98, 0x73,
5487 0x12, 0x98, 0x03, 0x0a, 0x99, 0x01, 0x0e, 0xf0, 0x0a, 0x40, 0x01, 0x0e,
5488 0xfe, 0x49, 0x44, 0x16, 0xfe, 0xf0, 0x17, 0x73, 0x75, 0x03, 0x0a, 0x42,
5489 0x01, 0x0e, 0x07, 0x10, 0x45, 0x0a, 0x51, 0x01, 0x9e, 0x0a, 0x40, 0x01,
5490 0x0e, 0x73, 0x75, 0x03, 0xfe, 0x4e, 0xe4, 0x1a, 0x64, 0xfe, 0x24, 0x18,
5491 0x05, 0xfe, 0x90, 0x00, 0xfe, 0x3a, 0x45, 0x5b, 0xfe, 0x4e, 0xe4, 0xc2,
5492 0x64, 0xfe, 0x36, 0x18, 0x05, 0xfe, 0x92, 0x00, 0xfe, 0x02, 0xe6, 0x1b,
5493 0xdc, 0xfe, 0x4e, 0xe4, 0xfe, 0x0b, 0x00, 0x64, 0xfe, 0x48, 0x18, 0x05,
5494 0xfe, 0x94, 0x00, 0xfe, 0x02, 0xe6, 0x19, 0xfe, 0x08, 0x10, 0x05, 0xfe,
5495 0x96, 0x00, 0xfe, 0x02, 0xe6, 0x2c, 0xfe, 0x4e, 0x45, 0xfe, 0x0c, 0x12,
5496 0xaf, 0xff, 0x04, 0x68, 0x54, 0xde, 0x1c, 0x69, 0x03, 0x07, 0x7a, 0xfe,
5497 0x5a, 0xf0, 0xfe, 0x74, 0x18, 0x24, 0xfe, 0x09, 0x00, 0xfe, 0x34, 0x10,
5498 0x07, 0x1b, 0xfe, 0x5a, 0xf0, 0xfe, 0x82, 0x18, 0x24, 0xc3, 0xfe, 0x26,
5499 0x10, 0x07, 0x1a, 0x5d, 0x24, 0x2c, 0xdc, 0x07, 0x0b, 0x5d, 0x24, 0x93,
5500 0xfe, 0x0e, 0x10, 0x07, 0x06, 0x5d, 0x24, 0x4d, 0x9f, 0xad, 0x03, 0x14,
5501 0xfe, 0x09, 0x00, 0x01, 0x33, 0xfe, 0x04, 0xfe, 0x7d, 0x05, 0x7f, 0xf9,
5502 0x03, 0x25, 0xfe, 0xca, 0x18, 0xfe, 0x14, 0xf0, 0x08, 0x65, 0xfe, 0xc6,
5503 0x18, 0x03, 0xff, 0x1a, 0x00, 0x00,
5506 static unsigned short _adv_asc3550_size = sizeof(_adv_asc3550_buf); /* 0x13AD */
5507 static ADV_DCNT _adv_asc3550_chksum = 0x04D52DDDUL; /* Expanded little-endian checksum. */
5509 /* Microcode buffer is kept after initialization for error recovery. */
5510 static unsigned char _adv_asc38C0800_buf[] = {
5511 0x00, 0x00, 0x00, 0xf2, 0x00, 0xf0, 0x00, 0xfc, 0x00, 0x16, 0x18, 0xe4,
5512 0x01, 0x00, 0x48, 0xe4, 0x18, 0x80, 0x03, 0xf6, 0x02, 0x00, 0xce, 0x19,
5513 0x00, 0xfa, 0xff, 0xff, 0x1c, 0x0f, 0x00, 0xf6, 0x9e, 0xe7, 0xff, 0x00,
5514 0x82, 0xe7, 0x00, 0xea, 0x01, 0xfa, 0x01, 0xe6, 0x09, 0xe7, 0x55, 0xf0,
5515 0x01, 0xf6, 0x03, 0x00, 0x04, 0x00, 0x10, 0x00, 0x1e, 0xf0, 0x85, 0xf0,
5516 0x18, 0xf4, 0x08, 0x00, 0xbc, 0x00, 0x38, 0x54, 0x00, 0xec, 0xd5, 0xf0,
5517 0x82, 0x0d, 0x00, 0xe6, 0x86, 0xf0, 0xb1, 0xf0, 0x98, 0x57, 0x01, 0xfc,
5518 0xb4, 0x00, 0xd4, 0x01, 0x0c, 0x1c, 0x3e, 0x1c, 0x3c, 0x00, 0xbb, 0x00,
5519 0x00, 0x10, 0xba, 0x19, 0x02, 0x80, 0x32, 0xf0, 0x7c, 0x0d, 0x02, 0x13,
5520 0xba, 0x13, 0x18, 0x40, 0x00, 0x57, 0x01, 0xea, 0x02, 0xfc, 0x03, 0xfc,
5521 0x3e, 0x00, 0x6c, 0x01, 0x6e, 0x01, 0x74, 0x01, 0x76, 0x01, 0xb9, 0x54,
5522 0x3e, 0x57, 0x00, 0x80, 0x03, 0xe6, 0xb6, 0x00, 0xc0, 0x00, 0x01, 0x01,
5523 0x3e, 0x01, 0x7a, 0x01, 0xca, 0x08, 0xce, 0x10, 0x16, 0x11, 0x04, 0x12,
5524 0x08, 0x12, 0x02, 0x4a, 0xbb, 0x55, 0x3c, 0x56, 0x03, 0x58, 0x1b, 0x80,
5525 0x30, 0xe4, 0x4b, 0xe4, 0x5d, 0xf0, 0x02, 0xfa, 0x20, 0x00, 0x32, 0x00,
5526 0x40, 0x00, 0x80, 0x00, 0x24, 0x01, 0x3c, 0x01, 0x68, 0x01, 0x6a, 0x01,
5527 0x70, 0x01, 0x72, 0x01, 0x78, 0x01, 0x7c, 0x01, 0x62, 0x0a, 0x86, 0x0d,
5528 0x06, 0x13, 0x4c, 0x1c, 0x04, 0x80, 0x4a, 0xe4, 0x02, 0xee, 0x5b, 0xf0,
5529 0x03, 0xf7, 0x0c, 0x00, 0x0f, 0x00, 0x47, 0x00, 0xbe, 0x00, 0x00, 0x01,
5530 0x20, 0x11, 0x5c, 0x16, 0x32, 0x1c, 0x38, 0x1c, 0x4e, 0x1c, 0x10, 0x44,
5531 0x00, 0x4c, 0x04, 0xea, 0x5c, 0xf0, 0xa7, 0xf0, 0x04, 0xf6, 0x03, 0xfa,
5532 0x05, 0x00, 0x34, 0x00, 0x36, 0x00, 0x98, 0x00, 0xcc, 0x00, 0x20, 0x01,
5533 0x4e, 0x01, 0x4a, 0x0b, 0x42, 0x0c, 0x12, 0x0f, 0x0c, 0x10, 0x22, 0x11,
5534 0x0a, 0x12, 0x04, 0x13, 0x30, 0x1c, 0x02, 0x48, 0x00, 0x4e, 0x42, 0x54,
5535 0x44, 0x55, 0xbd, 0x56, 0x06, 0x83, 0x00, 0xdc, 0x05, 0xf0, 0x09, 0xf0,
5536 0x59, 0xf0, 0xb8, 0xf0, 0x4b, 0xf4, 0x06, 0xf7, 0x0e, 0xf7, 0x04, 0xfc,
5537 0x05, 0xfc, 0x06, 0x00, 0x19, 0x00, 0x33, 0x00, 0x9b, 0x00, 0xa4, 0x00,
5538 0xb5, 0x00, 0xba, 0x00, 0xd0, 0x00, 0xe1, 0x00, 0xe7, 0x00, 0xe2, 0x03,
5539 0x08, 0x0f, 0x02, 0x10, 0x04, 0x10, 0x0a, 0x10, 0x0a, 0x13, 0x0c, 0x13,
5540 0x12, 0x13, 0x24, 0x14, 0x34, 0x14, 0x04, 0x16, 0x08, 0x16, 0xa4, 0x17,
5541 0x20, 0x1c, 0x34, 0x1c, 0x36, 0x1c, 0x08, 0x44, 0x38, 0x44, 0x91, 0x44,
5542 0x0a, 0x45, 0x48, 0x46, 0x01, 0x48, 0x68, 0x54, 0x3a, 0x55, 0x83, 0x55,
5543 0xe5, 0x55, 0xb0, 0x57, 0x01, 0x58, 0x83, 0x59, 0x05, 0xe6, 0x0b, 0xf0,
5544 0x0c, 0xf0, 0x04, 0xf8, 0x05, 0xf8, 0x07, 0x00, 0x0a, 0x00, 0x1c, 0x00,
5545 0x1e, 0x00, 0x9e, 0x00, 0xa8, 0x00, 0xaa, 0x00, 0xb9, 0x00, 0xe0, 0x00,
5546 0x22, 0x01, 0x26, 0x01, 0x79, 0x01, 0x7e, 0x01, 0xc4, 0x01, 0xc6, 0x01,
5547 0x80, 0x02, 0x5e, 0x03, 0xee, 0x04, 0x9a, 0x06, 0xf8, 0x07, 0x62, 0x08,
5548 0x68, 0x08, 0x69, 0x08, 0xd6, 0x08, 0xe9, 0x09, 0xfa, 0x0b, 0x2e, 0x0f,
5549 0x12, 0x10, 0x1a, 0x10, 0xed, 0x10, 0xf1, 0x10, 0x2a, 0x11, 0x06, 0x12,
5550 0x0c, 0x12, 0x3e, 0x12, 0x10, 0x13, 0x16, 0x13, 0x1e, 0x13, 0x46, 0x14,
5551 0x76, 0x14, 0x82, 0x14, 0x36, 0x15, 0xca, 0x15, 0x6b, 0x18, 0xbe, 0x18,
5552 0xca, 0x18, 0xe6, 0x19, 0x12, 0x1c, 0x46, 0x1c, 0x9c, 0x32, 0x00, 0x40,
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5848 0x03, 0x5c, 0xc1, 0x0c, 0x5c, 0x67, 0x2d, 0x01, 0x0b, 0x26, 0x89, 0x01,
5849 0xfe, 0x9e, 0x15, 0x02, 0x89, 0x01, 0x0b, 0x1c, 0x34, 0x1d, 0x4c, 0x33,
5850 0x31, 0xdf, 0x07, 0x06, 0x23, 0x4c, 0x01, 0xf1, 0xfe, 0x42, 0x58, 0xf1,
5851 0xfe, 0xa4, 0x14, 0x8c, 0xfe, 0x4a, 0xf4, 0x0a, 0x17, 0x4c, 0xfe, 0x4a,
5852 0xf4, 0x06, 0xea, 0x32, 0x07, 0xa5, 0x8b, 0x02, 0x72, 0x03, 0x45, 0xc1,
5853 0x0c, 0x45, 0x67, 0x2d, 0x01, 0x0b, 0x26, 0x89, 0x01, 0xfe, 0xcc, 0x15,
5854 0x02, 0x89, 0x0f, 0x06, 0x27, 0xfe, 0xbe, 0x13, 0x26, 0xfe, 0xd4, 0x13,
5855 0x76, 0xfe, 0x89, 0x48, 0x01, 0x0b, 0x21, 0x76, 0x04, 0x7b, 0xfe, 0xd0,
5856 0x13, 0x1c, 0xfe, 0xd0, 0x13, 0x1d, 0xfe, 0xbe, 0x13, 0x67, 0x2d, 0x01,
5857 0x0b, 0xfe, 0xd5, 0x10, 0x0f, 0x71, 0xff, 0x02, 0x00, 0x57, 0x52, 0x93,
5858 0x1e, 0xfe, 0xff, 0x7f, 0xfe, 0x30, 0x56, 0xfe, 0x00, 0x5c, 0x04, 0x0f,
5859 0x71, 0xff, 0x02, 0x00, 0x57, 0x52, 0x93, 0x1e, 0x43, 0xfe, 0x30, 0x56,
5860 0xfe, 0x00, 0x5c, 0x04, 0x0f, 0x71, 0xff, 0x02, 0x00, 0x57, 0x52, 0x93,
5861 0x04, 0x0f, 0x71, 0xff, 0x02, 0x00, 0x57, 0x52, 0x93, 0xfe, 0x0b, 0x58,
5862 0x04, 0x09, 0x5c, 0x01, 0x87, 0x09, 0x45, 0x01, 0x87, 0x04, 0xfe, 0x03,
5863 0xa1, 0x1e, 0x11, 0xff, 0x03, 0x00, 0x54, 0xfe, 0x00, 0xf4, 0x1f, 0x52,
5864 0xfe, 0x00, 0x7d, 0xfe, 0x01, 0x7d, 0xfe, 0x02, 0x7d, 0xfe, 0x03, 0x7c,
5865 0x6a, 0x2a, 0x0c, 0x5e, 0x14, 0x5f, 0x57, 0x3f, 0x7d, 0x40, 0x04, 0xdd,
5866 0xfe, 0x82, 0x4a, 0xfe, 0xe1, 0x1a, 0xfe, 0x83, 0x5a, 0x8d, 0x04, 0x01,
5867 0xfe, 0x0c, 0x19, 0xfe, 0x42, 0x48, 0x50, 0x51, 0x91, 0x01, 0x0b, 0x1d,
5868 0xfe, 0x96, 0x15, 0x33, 0x31, 0xe1, 0x01, 0x0b, 0x1d, 0xfe, 0x96, 0x15,
5869 0x33, 0x31, 0xfe, 0xe8, 0x0a, 0xfe, 0xc1, 0x59, 0x03, 0xcd, 0x28, 0xfe,
5870 0xcc, 0x12, 0x53, 0x05, 0x1a, 0xfe, 0xc4, 0x13, 0x21, 0x69, 0x1a, 0xee,
5871 0x55, 0xca, 0x6b, 0xfe, 0xdc, 0x14, 0x4d, 0x0f, 0x06, 0x18, 0xca, 0x7c,
5872 0x30, 0xfe, 0x78, 0x10, 0xff, 0x02, 0x83, 0x55, 0xab, 0xff, 0x02, 0x83,
5873 0x55, 0x69, 0x19, 0xae, 0x98, 0xfe, 0x30, 0x00, 0x96, 0xf2, 0x18, 0x6d,
5874 0x0f, 0x06, 0xfe, 0x56, 0x10, 0x69, 0x0a, 0xed, 0x98, 0xfe, 0x64, 0x00,
5875 0x96, 0xf2, 0x09, 0xfe, 0x64, 0x00, 0x18, 0x9e, 0x0f, 0x06, 0xfe, 0x28,
5876 0x10, 0x69, 0x06, 0xfe, 0x60, 0x13, 0x98, 0xfe, 0xc8, 0x00, 0x96, 0xf2,
5877 0x09, 0xfe, 0xc8, 0x00, 0x18, 0x59, 0x0f, 0x06, 0x88, 0x98, 0xfe, 0x90,
5878 0x01, 0x7a, 0xfe, 0x42, 0x15, 0x91, 0xe4, 0xfe, 0x43, 0xf4, 0x9f, 0xfe,
5879 0x56, 0xf0, 0xfe, 0x54, 0x15, 0xfe, 0x04, 0xf4, 0x71, 0xfe, 0x43, 0xf4,
5880 0x9e, 0xfe, 0xf3, 0x10, 0xfe, 0x40, 0x5c, 0x01, 0xfe, 0x16, 0x14, 0x1e,
5881 0x43, 0xec, 0xfe, 0x00, 0x17, 0xfe, 0x4d, 0xe4, 0x6e, 0x7a, 0xfe, 0x90,
5882 0x15, 0xc4, 0x6e, 0xfe, 0x1c, 0x10, 0xfe, 0x00, 0x17, 0xfe, 0x4d, 0xe4,
5883 0xcc, 0x7a, 0xfe, 0x90, 0x15, 0xc4, 0xcc, 0x88, 0x51, 0x21, 0xfe, 0x4d,
5884 0xf4, 0x00, 0xe9, 0x91, 0x0f, 0x06, 0xfe, 0xb4, 0x56, 0xfe, 0xc3, 0x58,
5885 0x04, 0x51, 0x0f, 0x0a, 0x04, 0x16, 0x06, 0x01, 0x0b, 0x26, 0xf3, 0x16,
5886 0x0a, 0x01, 0x0b, 0x26, 0xf3, 0x16, 0x19, 0x01, 0x0b, 0x26, 0xf3, 0x76,
5887 0xfe, 0x89, 0x49, 0x01, 0x0b, 0x04, 0x16, 0x06, 0x01, 0x0b, 0x26, 0xb1,
5888 0x16, 0x19, 0x01, 0x0b, 0x26, 0xb1, 0x16, 0x06, 0x01, 0x0b, 0x26, 0xb1,
5889 0xfe, 0x89, 0x49, 0x01, 0x0b, 0x26, 0xb1, 0x76, 0xfe, 0x89, 0x4a, 0x01,
5890 0x0b, 0x04, 0x51, 0x04, 0x22, 0xd3, 0x07, 0x06, 0xfe, 0x48, 0x13, 0xb8,
5891 0x13, 0xd3, 0xfe, 0x49, 0xf4, 0x00, 0x4d, 0x76, 0xa9, 0x67, 0xfe, 0x01,
5892 0xec, 0xfe, 0x27, 0x01, 0xfe, 0x89, 0x48, 0xff, 0x02, 0x00, 0x10, 0x27,
5893 0xfe, 0x2e, 0x16, 0x32, 0x07, 0xfe, 0xe3, 0x00, 0xfe, 0x20, 0x13, 0x1d,
5894 0xfe, 0x52, 0x16, 0x21, 0x13, 0xd4, 0x01, 0x4b, 0x22, 0xd4, 0x07, 0x06,
5895 0x4e, 0x08, 0x54, 0x06, 0x37, 0x04, 0x09, 0x48, 0x01, 0x0e, 0xfb, 0x8e,
5896 0x07, 0x11, 0xae, 0x09, 0x84, 0x01, 0x0e, 0x8e, 0x09, 0x5d, 0x01, 0xa8,
5897 0x04, 0x09, 0x84, 0x01, 0x0e, 0x8e, 0xfe, 0x80, 0xe7, 0x11, 0x07, 0x11,
5898 0x8a, 0xfe, 0x45, 0x58, 0x01, 0xf0, 0x8e, 0x04, 0x09, 0x48, 0x01, 0x0e,
5899 0x8e, 0x09, 0x5d, 0x01, 0xa8, 0x04, 0x09, 0x48, 0x01, 0x0e, 0xfe, 0x80,
5900 0x80, 0xfe, 0x80, 0x4c, 0xfe, 0x49, 0xe4, 0x11, 0xae, 0x09, 0x84, 0x01,
5901 0x0e, 0xfe, 0x80, 0x4c, 0x09, 0x5d, 0x01, 0x87, 0x04, 0x18, 0x11, 0x75,
5902 0x6c, 0xfe, 0x60, 0x01, 0xfe, 0x18, 0xdf, 0xfe, 0x19, 0xde, 0xfe, 0x24,
5903 0x1c, 0xfe, 0x1d, 0xf7, 0x1b, 0x97, 0xfe, 0xee, 0x16, 0x01, 0xfe, 0xf4,
5904 0x17, 0xad, 0x9a, 0x1b, 0x6c, 0xfe, 0x2c, 0x01, 0xfe, 0x2f, 0x19, 0x04,
5905 0xb9, 0x23, 0xfe, 0xde, 0x16, 0xfe, 0xda, 0x10, 0x18, 0x11, 0x75, 0x03,
5906 0xfe, 0x64, 0x01, 0xfe, 0x00, 0xf4, 0x1f, 0xfe, 0x18, 0x58, 0x03, 0xfe,
5907 0x66, 0x01, 0xfe, 0x19, 0x58, 0x9a, 0x1f, 0xfe, 0x3c, 0x90, 0xfe, 0x30,
5908 0xf4, 0x06, 0xfe, 0x3c, 0x50, 0x6c, 0xfe, 0x38, 0x00, 0xfe, 0x0f, 0x79,
5909 0xfe, 0x1c, 0xf7, 0x1f, 0x97, 0xfe, 0x38, 0x17, 0xfe, 0xb6, 0x14, 0x35,
5910 0x04, 0xb9, 0x23, 0xfe, 0x10, 0x17, 0xfe, 0x9c, 0x10, 0x18, 0x11, 0x75,
5911 0xfe, 0x83, 0x5a, 0xfe, 0x18, 0xdf, 0xfe, 0x19, 0xde, 0xfe, 0x1d, 0xf7,
5912 0x2e, 0x97, 0xfe, 0x5a, 0x17, 0xfe, 0x94, 0x14, 0xec, 0x9a, 0x2e, 0x6c,
5913 0x1a, 0xfe, 0xaf, 0x19, 0xfe, 0x98, 0xe7, 0x00, 0x04, 0xb9, 0x23, 0xfe,
5914 0x4e, 0x17, 0xfe, 0x6c, 0x10, 0x18, 0x11, 0x75, 0xfe, 0x30, 0xbc, 0xfe,
5915 0xb2, 0xbc, 0x9a, 0xcb, 0x6c, 0x1a, 0xfe, 0x0f, 0x79, 0xfe, 0x1c, 0xf7,
5916 0xcb, 0x97, 0xfe, 0x92, 0x17, 0xfe, 0x5c, 0x14, 0x35, 0x04, 0xb9, 0x23,
5917 0xfe, 0x7e, 0x17, 0xfe, 0x42, 0x10, 0xfe, 0x02, 0xf6, 0x11, 0x75, 0xfe,
5918 0x18, 0xfe, 0x60, 0xfe, 0x19, 0xfe, 0x61, 0xfe, 0x03, 0xa1, 0xfe, 0x1d,
5919 0xf7, 0x5b, 0x97, 0xfe, 0xb8, 0x17, 0xfe, 0x36, 0x14, 0xfe, 0x1c, 0x13,
5920 0x9a, 0x5b, 0x41, 0xfe, 0x83, 0x58, 0xfe, 0xaf, 0x19, 0xfe, 0x80, 0xe7,
5921 0x11, 0xfe, 0x81, 0xe7, 0x11, 0x12, 0xfe, 0xdd, 0x00, 0x6a, 0x2a, 0x04,
5922 0x6a, 0x2a, 0xfe, 0x12, 0x45, 0x23, 0xfe, 0xa8, 0x17, 0x15, 0x06, 0x39,
5923 0xa0, 0xb4, 0x02, 0x2b, 0xfe, 0x39, 0xf0, 0xfe, 0xfc, 0x17, 0x21, 0x04,
5924 0xfe, 0x7e, 0x18, 0x1e, 0x19, 0x66, 0x0f, 0x0d, 0x04, 0x75, 0x03, 0xd2,
5925 0x1e, 0x06, 0xfe, 0xef, 0x12, 0xfe, 0xe1, 0x10, 0x7c, 0x6f, 0x4f, 0x32,
5926 0x07, 0x2f, 0xfe, 0x3c, 0x13, 0xf1, 0xfe, 0x42, 0x13, 0x42, 0x92, 0x09,
5927 0x48, 0x01, 0x0e, 0xbb, 0xeb, 0xfe, 0x41, 0x48, 0xfe, 0x45, 0x48, 0x01,
5928 0xf0, 0xfe, 0x00, 0xcc, 0xbb, 0xfe, 0xf3, 0x13, 0x43, 0x78, 0x07, 0x11,
5929 0xac, 0x09, 0x84, 0x01, 0x0e, 0xfe, 0x80, 0x4c, 0x01, 0x73, 0xfe, 0x16,
5930 0x10, 0x07, 0x82, 0x8b, 0xfe, 0x40, 0x14, 0xfe, 0x24, 0x12, 0xfe, 0x14,
5931 0x56, 0xfe, 0xd6, 0xf0, 0xfe, 0x1c, 0x18, 0x18, 0x0a, 0x04, 0xfe, 0x9c,
5932 0xe7, 0x0a, 0x10, 0xfe, 0x15, 0x00, 0x64, 0x79, 0x2a, 0x01, 0xe3, 0x18,
5933 0x06, 0x04, 0x42, 0x92, 0x08, 0x54, 0x1b, 0x37, 0x12, 0x2f, 0x01, 0x73,
5934 0x18, 0x06, 0x04, 0xfe, 0x38, 0x90, 0xfe, 0xba, 0x90, 0x3a, 0xce, 0x3b,
5935 0xcf, 0xfe, 0x48, 0x55, 0x35, 0xfe, 0xc9, 0x55, 0x04, 0x22, 0xa3, 0x77,
5936 0x13, 0xa3, 0x04, 0x09, 0xa4, 0x01, 0x0e, 0xfe, 0x41, 0x48, 0x09, 0x46,
5937 0x01, 0x0e, 0xfe, 0x49, 0x44, 0x17, 0xfe, 0xe8, 0x18, 0x77, 0x78, 0x04,
5938 0x09, 0x48, 0x01, 0x0e, 0x07, 0x11, 0x4e, 0x09, 0x5d, 0x01, 0xa8, 0x09,
5939 0x46, 0x01, 0x0e, 0x77, 0x78, 0x04, 0xfe, 0x4e, 0xe4, 0x19, 0x6b, 0xfe,
5940 0x1c, 0x19, 0x03, 0xfe, 0x90, 0x00, 0xfe, 0x3a, 0x45, 0xfe, 0x2c, 0x10,
5941 0xfe, 0x4e, 0xe4, 0xc9, 0x6b, 0xfe, 0x2e, 0x19, 0x03, 0xfe, 0x92, 0x00,
5942 0xfe, 0x02, 0xe6, 0x1a, 0xe5, 0xfe, 0x4e, 0xe4, 0xfe, 0x0b, 0x00, 0x6b,
5943 0xfe, 0x40, 0x19, 0x03, 0xfe, 0x94, 0x00, 0xfe, 0x02, 0xe6, 0x1f, 0xfe,
5944 0x08, 0x10, 0x03, 0xfe, 0x96, 0x00, 0xfe, 0x02, 0xe6, 0x6d, 0xfe, 0x4e,
5945 0x45, 0xea, 0xba, 0xff, 0x04, 0x68, 0x54, 0xe7, 0x1e, 0x6e, 0xfe, 0x08,
5946 0x1c, 0xfe, 0x67, 0x19, 0xfe, 0x0a, 0x1c, 0xfe, 0x1a, 0xf4, 0xfe, 0x00,
5947 0x04, 0xea, 0xfe, 0x48, 0xf4, 0x19, 0x7a, 0xfe, 0x74, 0x19, 0x0f, 0x19,
5948 0x04, 0x07, 0x7e, 0xfe, 0x5a, 0xf0, 0xfe, 0x84, 0x19, 0x25, 0xfe, 0x09,
5949 0x00, 0xfe, 0x34, 0x10, 0x07, 0x1a, 0xfe, 0x5a, 0xf0, 0xfe, 0x92, 0x19,
5950 0x25, 0xca, 0xfe, 0x26, 0x10, 0x07, 0x19, 0x66, 0x25, 0x6d, 0xe5, 0x07,
5951 0x0a, 0x66, 0x25, 0x9e, 0xfe, 0x0e, 0x10, 0x07, 0x06, 0x66, 0x25, 0x59,
5952 0xa9, 0xb8, 0x04, 0x15, 0xfe, 0x09, 0x00, 0x01, 0x36, 0xfe, 0x04, 0xfe,
5953 0x81, 0x03, 0x83, 0xfe, 0x40, 0x5c, 0x04, 0x1c, 0xf7, 0xfe, 0x14, 0xf0,
5954 0x0b, 0x27, 0xfe, 0xd6, 0x19, 0x1c, 0xf7, 0x7b, 0xf7, 0xfe, 0x82, 0xf0,
5955 0xfe, 0xda, 0x19, 0x04, 0xff, 0xcc, 0x00, 0x00,
5958 static unsigned short _adv_asc38C0800_size = sizeof(_adv_asc38C0800_buf); /* 0x14E1 */
5959 static ADV_DCNT _adv_asc38C0800_chksum = 0x050D3FD8UL; /* Expanded little-endian checksum. */
5961 /* Microcode buffer is kept after initialization for error recovery. */
5962 static unsigned char _adv_asc38C1600_buf[] = {
5963 0x00, 0x00, 0x00, 0xf2, 0x00, 0x16, 0x00, 0xfc, 0x00, 0x10, 0x00, 0xf0,
5964 0x18, 0xe4, 0x01, 0x00, 0x04, 0x1e, 0x48, 0xe4, 0x03, 0xf6, 0xf7, 0x13,
5965 0x2e, 0x1e, 0x02, 0x00, 0x07, 0x17, 0xc0, 0x5f, 0x00, 0xfa, 0xff, 0xff,
5966 0x04, 0x00, 0x00, 0xf6, 0x09, 0xe7, 0x82, 0xe7, 0x85, 0xf0, 0x86, 0xf0,
5967 0x4e, 0x10, 0x9e, 0xe7, 0xff, 0x00, 0x55, 0xf0, 0x01, 0xf6, 0x03, 0x00,
5968 0x98, 0x57, 0x01, 0xe6, 0x00, 0xea, 0x00, 0xec, 0x01, 0xfa, 0x18, 0xf4,
5969 0x08, 0x00, 0xf0, 0x1d, 0x38, 0x54, 0x32, 0xf0, 0x10, 0x00, 0xc2, 0x0e,
5970 0x1e, 0xf0, 0xd5, 0xf0, 0xbc, 0x00, 0x4b, 0xe4, 0x00, 0xe6, 0xb1, 0xf0,
5971 0xb4, 0x00, 0x02, 0x13, 0x3e, 0x1c, 0xc8, 0x47, 0x3e, 0x00, 0xd8, 0x01,
5972 0x06, 0x13, 0x0c, 0x1c, 0x5e, 0x1e, 0x00, 0x57, 0xc8, 0x57, 0x01, 0xfc,
5973 0xbc, 0x0e, 0xa2, 0x12, 0xb9, 0x54, 0x00, 0x80, 0x62, 0x0a, 0x5a, 0x12,
5974 0xc8, 0x15, 0x3e, 0x1e, 0x18, 0x40, 0xbd, 0x56, 0x03, 0xe6, 0x01, 0xea,
5975 0x5c, 0xf0, 0x0f, 0x00, 0x20, 0x00, 0x6c, 0x01, 0x6e, 0x01, 0x04, 0x12,
5976 0x04, 0x13, 0xbb, 0x55, 0x3c, 0x56, 0x3e, 0x57, 0x03, 0x58, 0x4a, 0xe4,
5977 0x40, 0x00, 0xb6, 0x00, 0xbb, 0x00, 0xc0, 0x00, 0x00, 0x01, 0x01, 0x01,
5978 0x3e, 0x01, 0x58, 0x0a, 0x44, 0x10, 0x0a, 0x12, 0x4c, 0x1c, 0x4e, 0x1c,
5979 0x02, 0x4a, 0x30, 0xe4, 0x05, 0xe6, 0x0c, 0x00, 0x3c, 0x00, 0x80, 0x00,
5980 0x24, 0x01, 0x3c, 0x01, 0x68, 0x01, 0x6a, 0x01, 0x70, 0x01, 0x72, 0x01,
5981 0x74, 0x01, 0x76, 0x01, 0x78, 0x01, 0x7c, 0x01, 0xc6, 0x0e, 0x0c, 0x10,
5982 0xac, 0x12, 0xae, 0x12, 0x16, 0x1a, 0x32, 0x1c, 0x6e, 0x1e, 0x02, 0x48,
5983 0x3a, 0x55, 0xc9, 0x57, 0x02, 0xee, 0x5b, 0xf0, 0x03, 0xf7, 0x06, 0xf7,
5984 0x03, 0xfc, 0x06, 0x00, 0x1e, 0x00, 0xbe, 0x00, 0xe1, 0x00, 0x0c, 0x12,
5985 0x18, 0x1a, 0x70, 0x1a, 0x30, 0x1c, 0x38, 0x1c, 0x10, 0x44, 0x00, 0x4c,
5986 0xb0, 0x57, 0x40, 0x5c, 0x4d, 0xe4, 0x04, 0xea, 0x5d, 0xf0, 0xa7, 0xf0,
5987 0x04, 0xf6, 0x02, 0xfc, 0x05, 0x00, 0x09, 0x00, 0x19, 0x00, 0x32, 0x00,
5988 0x33, 0x00, 0x34, 0x00, 0x36, 0x00, 0x98, 0x00, 0x9e, 0x00, 0xcc, 0x00,
5989 0x20, 0x01, 0x4e, 0x01, 0x79, 0x01, 0x3c, 0x09, 0x68, 0x0d, 0x02, 0x10,
5990 0x04, 0x10, 0x3a, 0x10, 0x08, 0x12, 0x0a, 0x13, 0x40, 0x16, 0x50, 0x16,
5991 0x00, 0x17, 0x4a, 0x19, 0x00, 0x4e, 0x00, 0x54, 0x01, 0x58, 0x00, 0xdc,
5992 0x05, 0xf0, 0x09, 0xf0, 0x59, 0xf0, 0xb8, 0xf0, 0x48, 0xf4, 0x0e, 0xf7,
5993 0x0a, 0x00, 0x9b, 0x00, 0x9c, 0x00, 0xa4, 0x00, 0xb5, 0x00, 0xba, 0x00,
5994 0xd0, 0x00, 0xe7, 0x00, 0xf0, 0x03, 0x69, 0x08, 0xe9, 0x09, 0x5c, 0x0c,
5995 0xb6, 0x12, 0xbc, 0x19, 0xd8, 0x1b, 0x20, 0x1c, 0x34, 0x1c, 0x36, 0x1c,
5996 0x42, 0x1d, 0x08, 0x44, 0x38, 0x44, 0x91, 0x44, 0x0a, 0x45, 0x48, 0x46,
5997 0x89, 0x48, 0x68, 0x54, 0x83, 0x55, 0x83, 0x59, 0x31, 0xe4, 0x02, 0xe6,
5998 0x07, 0xf0, 0x08, 0xf0, 0x0b, 0xf0, 0x0c, 0xf0, 0x4b, 0xf4, 0x04, 0xf8,
5999 0x05, 0xf8, 0x02, 0xfa, 0x03, 0xfa, 0x04, 0xfc, 0x05, 0xfc, 0x07, 0x00,
6000 0xa8, 0x00, 0xaa, 0x00, 0xb9, 0x00, 0xe0, 0x00, 0xe5, 0x00, 0x22, 0x01,
6001 0x26, 0x01, 0x60, 0x01, 0x7a, 0x01, 0x82, 0x01, 0xc8, 0x01, 0xca, 0x01,
6002 0x86, 0x02, 0x6a, 0x03, 0x18, 0x05, 0xb2, 0x07, 0x68, 0x08, 0x10, 0x0d,
6003 0x06, 0x10, 0x0a, 0x10, 0x0e, 0x10, 0x12, 0x10, 0x60, 0x10, 0xed, 0x10,
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6448 0x12, 0xfe, 0x14, 0x56, 0xfe, 0xd6, 0xf0, 0xfe, 0x52, 0x1c, 0x1c, 0x0d,
6449 0x02, 0xfe, 0x9c, 0xe7, 0x0d, 0x19, 0xfe, 0x15, 0x00, 0x40, 0x8d, 0x30,
6450 0x01, 0xf4, 0x1c, 0x07, 0x02, 0x51, 0xfe, 0x06, 0x83, 0xfe, 0x18, 0x80,
6451 0x61, 0x28, 0x44, 0x15, 0x56, 0x01, 0x85, 0x1c, 0x07, 0x02, 0xfe, 0x38,
6452 0x90, 0xfe, 0xba, 0x90, 0x91, 0xde, 0x7e, 0xdf, 0xfe, 0x48, 0x55, 0x31,
6453 0xfe, 0xc9, 0x55, 0x02, 0x21, 0xb9, 0x88, 0x20, 0xb9, 0x02, 0x0a, 0xba,
6454 0x01, 0x18, 0xfe, 0x41, 0x48, 0x0a, 0x57, 0x01, 0x18, 0xfe, 0x49, 0x44,
6455 0x1b, 0xfe, 0x1e, 0x1d, 0x88, 0x89, 0x02, 0x0a, 0x5a, 0x01, 0x18, 0x09,
6456 0x1a, 0xa4, 0x0a, 0x67, 0x01, 0xa3, 0x0a, 0x57, 0x01, 0x18, 0x88, 0x89,
6457 0x02, 0xfe, 0x4e, 0xe4, 0x1d, 0x7b, 0xfe, 0x52, 0x1d, 0x03, 0xfe, 0x90,
6458 0x00, 0xfe, 0x3a, 0x45, 0xfe, 0x2c, 0x10, 0xfe, 0x4e, 0xe4, 0xdd, 0x7b,
6459 0xfe, 0x64, 0x1d, 0x03, 0xfe, 0x92, 0x00, 0xd1, 0x12, 0xfe, 0x1a, 0x10,
6460 0xfe, 0x4e, 0xe4, 0xfe, 0x0b, 0x00, 0x7b, 0xfe, 0x76, 0x1d, 0x03, 0xfe,
6461 0x94, 0x00, 0xd1, 0x24, 0xfe, 0x08, 0x10, 0x03, 0xfe, 0x96, 0x00, 0xd1,
6462 0x63, 0xfe, 0x4e, 0x45, 0x83, 0xca, 0xff, 0x04, 0x68, 0x54, 0xfe, 0xf1,
6463 0x10, 0x23, 0x49, 0xfe, 0x08, 0x1c, 0xfe, 0x67, 0x19, 0xfe, 0x0a, 0x1c,
6464 0xfe, 0x1a, 0xf4, 0xfe, 0x00, 0x04, 0x83, 0xb2, 0x1d, 0x48, 0xfe, 0xaa,
6465 0x1d, 0x13, 0x1d, 0x02, 0x09, 0x92, 0xfe, 0x5a, 0xf0, 0xfe, 0xba, 0x1d,
6466 0x2e, 0x93, 0xfe, 0x34, 0x10, 0x09, 0x12, 0xfe, 0x5a, 0xf0, 0xfe, 0xc8,
6467 0x1d, 0x2e, 0xb4, 0xfe, 0x26, 0x10, 0x09, 0x1d, 0x36, 0x2e, 0x63, 0xfe,
6468 0x1a, 0x10, 0x09, 0x0d, 0x36, 0x2e, 0x94, 0xf2, 0x09, 0x07, 0x36, 0x2e,
6469 0x95, 0xa1, 0xc8, 0x02, 0x1f, 0x93, 0x01, 0x42, 0xfe, 0x04, 0xfe, 0x99,
6470 0x03, 0x9c, 0x8b, 0x02, 0x2a, 0xfe, 0x1c, 0x1e, 0xfe, 0x14, 0xf0, 0x08,
6471 0x2f, 0xfe, 0x0c, 0x1e, 0x2a, 0xfe, 0x1c, 0x1e, 0x8f, 0xfe, 0x1c, 0x1e,
6472 0xfe, 0x82, 0xf0, 0xfe, 0x10, 0x1e, 0x02, 0x0f, 0x3f, 0x04, 0xfe, 0x80,
6473 0x83, 0x33, 0x0b, 0x0e, 0x02, 0x0f, 0xfe, 0x18, 0x80, 0x04, 0xfe, 0x98,
6474 0x83, 0x33, 0x0b, 0x0e, 0x02, 0x0f, 0xfe, 0x02, 0x80, 0x04, 0xfe, 0x82,
6475 0x83, 0x33, 0x0b, 0x0e, 0x02, 0x0f, 0xfe, 0x06, 0x80, 0x04, 0xfe, 0x86,
6476 0x83, 0x33, 0x0b, 0x0e, 0x02, 0x0f, 0xfe, 0x1b, 0x80, 0x04, 0xfe, 0x9b,
6477 0x83, 0x33, 0x0b, 0x0e, 0x02, 0x0f, 0xfe, 0x04, 0x80, 0x04, 0xfe, 0x84,
6478 0x83, 0x33, 0x0b, 0x0e, 0x02, 0x0f, 0xfe, 0x80, 0x80, 0x04, 0xfe, 0x80,
6479 0x83, 0xfe, 0xc9, 0x47, 0x0b, 0x0e, 0x02, 0x0f, 0xfe, 0x19, 0x81, 0x04,
6480 0xfe, 0x99, 0x83, 0xfe, 0xca, 0x47, 0x0b, 0x0e, 0x02, 0x0f, 0xfe, 0x06,
6481 0x83, 0x04, 0xfe, 0x86, 0x83, 0xfe, 0xce, 0x47, 0x0b, 0x0e, 0x02, 0x0f,
6482 0xfe, 0x2c, 0x90, 0x04, 0xfe, 0xac, 0x93, 0x3a, 0x0b, 0x0e, 0x02, 0x0f,
6483 0xfe, 0xae, 0x90, 0x04, 0xfe, 0xae, 0x93, 0x79, 0x0b, 0x0e, 0x02, 0x0f,
6484 0xfe, 0x08, 0x90, 0x04, 0xfe, 0x88, 0x93, 0x3a, 0x0b, 0x0e, 0x02, 0x0f,
6485 0xfe, 0x8a, 0x90, 0x04, 0xfe, 0x8a, 0x93, 0x79, 0x0b, 0x0e, 0x02, 0x0f,
6486 0xfe, 0x0c, 0x90, 0x04, 0xfe, 0x8c, 0x93, 0x3a, 0x0b, 0x0e, 0x02, 0x0f,
6487 0xfe, 0x8e, 0x90, 0x04, 0xfe, 0x8e, 0x93, 0x79, 0x0b, 0x0e, 0x02, 0x0f,
6488 0xfe, 0x3c, 0x90, 0x04, 0xfe, 0xbc, 0x93, 0x3a, 0x0b, 0x0e, 0x02, 0x8b,
6489 0x0f, 0xfe, 0x03, 0x80, 0x04, 0xfe, 0x83, 0x83, 0x33, 0x0b, 0x77, 0x0e,
6490 0xa8, 0x02, 0xff, 0x66, 0x00, 0x00,
6493 static unsigned short _adv_asc38C1600_size = sizeof(_adv_asc38C1600_buf); /* 0x1673 */
6494 static ADV_DCNT _adv_asc38C1600_chksum = 0x0604EF77UL; /* Expanded little-endian checksum. */
6496 static void AscInitQLinkVar(ASC_DVC_VAR *asc_dvc)
6502 iop_base = asc_dvc->iop_base;
6503 AscPutRiscVarFreeQHead(iop_base, 1);
6504 AscPutRiscVarDoneQTail(iop_base, asc_dvc->max_total_qng);
6505 AscPutVarFreeQHead(iop_base, 1);
6506 AscPutVarDoneQTail(iop_base, asc_dvc->max_total_qng);
6507 AscWriteLramByte(iop_base, ASCV_BUSY_QHEAD_B,
6508 (uchar)((int)asc_dvc->max_total_qng + 1));
6509 AscWriteLramByte(iop_base, ASCV_DISC1_QHEAD_B,
6510 (uchar)((int)asc_dvc->max_total_qng + 2));
6511 AscWriteLramByte(iop_base, (ushort)ASCV_TOTAL_READY_Q_B,
6512 asc_dvc->max_total_qng);
6513 AscWriteLramWord(iop_base, ASCV_ASCDVC_ERR_CODE_W, 0);
6514 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
6515 AscWriteLramByte(iop_base, ASCV_STOP_CODE_B, 0);
6516 AscWriteLramByte(iop_base, ASCV_SCSIBUSY_B, 0);
6517 AscWriteLramByte(iop_base, ASCV_WTM_FLAG_B, 0);
6518 AscPutQDoneInProgress(iop_base, 0);
6519 lram_addr = ASC_QADR_BEG;
6520 for (i = 0; i < 32; i++, lram_addr += 2) {
6521 AscWriteLramWord(iop_base, lram_addr, 0);
6525 static ushort AscInitMicroCodeVar(ASC_DVC_VAR *asc_dvc)
6533 iop_base = asc_dvc->iop_base;
6535 for (i = 0; i <= ASC_MAX_TID; i++) {
6536 AscPutMCodeInitSDTRAtID(iop_base, i,
6537 asc_dvc->cfg->sdtr_period_offset[i]);
6540 AscInitQLinkVar(asc_dvc);
6541 AscWriteLramByte(iop_base, ASCV_DISC_ENABLE_B,
6542 asc_dvc->cfg->disc_enable);
6543 AscWriteLramByte(iop_base, ASCV_HOSTSCSI_ID_B,
6544 ASC_TID_TO_TARGET_ID(asc_dvc->cfg->chip_scsi_id));
6546 /* Align overrun buffer on an 8 byte boundary. */
6547 phy_addr = virt_to_bus(asc_dvc->cfg->overrun_buf);
6548 phy_addr = cpu_to_le32((phy_addr + 7) & ~0x7);
6549 AscMemDWordCopyPtrToLram(iop_base, ASCV_OVERRUN_PADDR_D,
6550 (uchar *)&phy_addr, 1);
6551 phy_size = cpu_to_le32(ASC_OVERRUN_BSIZE - 8);
6552 AscMemDWordCopyPtrToLram(iop_base, ASCV_OVERRUN_BSIZE_D,
6553 (uchar *)&phy_size, 1);
6555 asc_dvc->cfg->mcode_date =
6556 AscReadLramWord(iop_base, (ushort)ASCV_MC_DATE_W);
6557 asc_dvc->cfg->mcode_version =
6558 AscReadLramWord(iop_base, (ushort)ASCV_MC_VER_W);
6560 AscSetPCAddr(iop_base, ASC_MCODE_START_ADDR);
6561 if (AscGetPCAddr(iop_base) != ASC_MCODE_START_ADDR) {
6562 asc_dvc->err_code |= ASC_IERR_SET_PC_ADDR;
6565 if (AscStartChip(iop_base) != 1) {
6566 asc_dvc->err_code |= ASC_IERR_START_STOP_CHIP;
6573 static ushort AscInitAsc1000Driver(ASC_DVC_VAR *asc_dvc)
6578 iop_base = asc_dvc->iop_base;
6580 if ((asc_dvc->dvc_cntl & ASC_CNTL_RESET_SCSI) &&
6581 !(asc_dvc->init_state & ASC_INIT_RESET_SCSI_DONE)) {
6582 AscResetChipAndScsiBus(asc_dvc);
6583 mdelay(asc_dvc->scsi_reset_wait * 1000); /* XXX: msleep? */
6585 asc_dvc->init_state |= ASC_INIT_STATE_BEG_LOAD_MC;
6586 if (asc_dvc->err_code != 0)
6588 if (!AscFindSignature(asc_dvc->iop_base)) {
6589 asc_dvc->err_code = ASC_IERR_BAD_SIGNATURE;
6592 AscDisableInterrupt(iop_base);
6593 warn_code |= AscInitLram(asc_dvc);
6594 if (asc_dvc->err_code != 0)
6596 ASC_DBG1(1, "AscInitAsc1000Driver: _asc_mcode_chksum 0x%lx\n",
6597 (ulong)_asc_mcode_chksum);
6598 if (AscLoadMicroCode(iop_base, 0, _asc_mcode_buf,
6599 _asc_mcode_size) != _asc_mcode_chksum) {
6600 asc_dvc->err_code |= ASC_IERR_MCODE_CHKSUM;
6603 warn_code |= AscInitMicroCodeVar(asc_dvc);
6604 asc_dvc->init_state |= ASC_INIT_STATE_END_LOAD_MC;
6605 AscEnableInterrupt(iop_base);
6610 * Load the Microcode
6612 * Write the microcode image to RISC memory starting at address 0.
6614 * The microcode is stored compressed in the following format:
6616 * 254 word (508 byte) table indexed by byte code followed
6617 * by the following byte codes:
6620 * 00: Emit word 0 in table.
6621 * 01: Emit word 1 in table.
6623 * FD: Emit word 253 in table.
6626 * FE WW WW: (3 byte code) Word to emit is the next word WW WW.
6627 * FF BB WW WW: (4 byte code) Emit BB count times next word WW WW.
6629 * Returns 0 or an error if the checksum doesn't match
6631 static int AdvLoadMicrocode(AdvPortAddr iop_base, unsigned char *buf, int size,
6632 int memsize, int chksum)
6634 int i, j, end, len = 0;
6637 AdvWriteWordRegister(iop_base, IOPW_RAM_ADDR, 0);
6639 for (i = 253 * 2; i < size; i++) {
6640 if (buf[i] == 0xff) {
6641 unsigned short word = (buf[i + 3] << 8) | buf[i + 2];
6642 for (j = 0; j < buf[i + 1]; j++) {
6643 AdvWriteWordAutoIncLram(iop_base, word);
6647 } else if (buf[i] == 0xfe) {
6648 unsigned short word = (buf[i + 2] << 8) | buf[i + 1];
6649 AdvWriteWordAutoIncLram(iop_base, word);
6653 unsigned char off = buf[i] * 2;
6654 unsigned short word = (buf[off + 1] << 8) | buf[off];
6655 AdvWriteWordAutoIncLram(iop_base, word);
6662 while (len < memsize) {
6663 AdvWriteWordAutoIncLram(iop_base, 0);
6667 /* Verify the microcode checksum. */
6669 AdvWriteWordRegister(iop_base, IOPW_RAM_ADDR, 0);
6671 for (len = 0; len < end; len += 2) {
6672 sum += AdvReadWordAutoIncLram(iop_base);
6676 return ASC_IERR_MCODE_CHKSUM;
6684 * Return the physical address of 'vaddr' and set '*lenp' to the
6685 * number of physically contiguous bytes that follow 'vaddr'.
6686 * 'flag' indicates the type of structure whose physical address
6687 * is being translated.
6689 * Note: Because Linux currently doesn't page the kernel and all
6690 * kernel buffers are physically contiguous, leave '*lenp' unchanged.
6693 DvcGetPhyAddr(ADV_DVC_VAR *asc_dvc, ADV_SCSI_REQ_Q *scsiq,
6694 uchar *vaddr, ADV_SDCNT *lenp, int flag)
6696 ADV_PADDR paddr = virt_to_bus(vaddr);
6698 ASC_DBG4(4, "DvcGetPhyAddr: vaddr 0x%p, lenp 0x%p *lenp %lu, paddr 0x%lx\n",
6699 vaddr, lenp, (ulong)*((ulong *)lenp), (ulong)paddr);
6704 static void AdvBuildCarrierFreelist(struct adv_dvc_var *asc_dvc)
6708 ADV_PADDR carr_paddr;
6710 BUG_ON(!asc_dvc->carrier_buf);
6712 carrp = (ADV_CARR_T *) ADV_16BALIGN(asc_dvc->carrier_buf);
6713 asc_dvc->carr_freelist = NULL;
6714 if (carrp == asc_dvc->carrier_buf) {
6715 buf_size = ADV_CARRIER_BUFSIZE;
6717 buf_size = ADV_CARRIER_BUFSIZE - sizeof(ADV_CARR_T);
6721 /* Get physical address of the carrier 'carrp'. */
6722 ADV_DCNT contig_len = sizeof(ADV_CARR_T);
6723 carr_paddr = cpu_to_le32(DvcGetPhyAddr(asc_dvc, NULL,
6725 (ADV_SDCNT *)&contig_len,
6726 ADV_IS_CARRIER_FLAG));
6728 buf_size -= sizeof(ADV_CARR_T);
6731 * If the current carrier is not physically contiguous, then
6732 * maybe there was a page crossing. Try the next carrier
6733 * aligned start address.
6735 if (contig_len < sizeof(ADV_CARR_T)) {
6740 carrp->carr_pa = carr_paddr;
6741 carrp->carr_va = cpu_to_le32(ADV_VADDR_TO_U32(carrp));
6744 * Insert the carrier at the beginning of the freelist.
6747 cpu_to_le32(ADV_VADDR_TO_U32(asc_dvc->carr_freelist));
6748 asc_dvc->carr_freelist = carrp;
6751 } while (buf_size > 0);
6755 * Send an idle command to the chip and wait for completion.
6757 * Command completion is polled for once per microsecond.
6759 * The function can be called from anywhere including an interrupt handler.
6760 * But the function is not re-entrant, so it uses the DvcEnter/LeaveCritical()
6761 * functions to prevent reentrancy.
6764 * ADV_TRUE - command completed successfully
6765 * ADV_FALSE - command failed
6766 * ADV_ERROR - command timed out
6769 AdvSendIdleCmd(ADV_DVC_VAR *asc_dvc,
6770 ushort idle_cmd, ADV_DCNT idle_cmd_parameter)
6774 AdvPortAddr iop_base;
6776 iop_base = asc_dvc->iop_base;
6779 * Clear the idle command status which is set by the microcode
6780 * to a non-zero value to indicate when the command is completed.
6781 * The non-zero result is one of the IDLE_CMD_STATUS_* values
6783 AdvWriteWordLram(iop_base, ASC_MC_IDLE_CMD_STATUS, (ushort)0);
6786 * Write the idle command value after the idle command parameter
6787 * has been written to avoid a race condition. If the order is not
6788 * followed, the microcode may process the idle command before the
6789 * parameters have been written to LRAM.
6791 AdvWriteDWordLramNoSwap(iop_base, ASC_MC_IDLE_CMD_PARAMETER,
6792 cpu_to_le32(idle_cmd_parameter));
6793 AdvWriteWordLram(iop_base, ASC_MC_IDLE_CMD, idle_cmd);
6796 * Tickle the RISC to tell it to process the idle command.
6798 AdvWriteByteRegister(iop_base, IOPB_TICKLE, ADV_TICKLE_B);
6799 if (asc_dvc->chip_type == ADV_CHIP_ASC3550) {
6801 * Clear the tickle value. In the ASC-3550 the RISC flag
6802 * command 'clr_tickle_b' does not work unless the host
6805 AdvWriteByteRegister(iop_base, IOPB_TICKLE, ADV_TICKLE_NOP);
6808 /* Wait for up to 100 millisecond for the idle command to timeout. */
6809 for (i = 0; i < SCSI_WAIT_100_MSEC; i++) {
6810 /* Poll once each microsecond for command completion. */
6811 for (j = 0; j < SCSI_US_PER_MSEC; j++) {
6812 AdvReadWordLram(iop_base, ASC_MC_IDLE_CMD_STATUS,
6820 BUG(); /* The idle command should never timeout. */
6825 * Reset SCSI Bus and purge all outstanding requests.
6828 * ADV_TRUE(1) - All requests are purged and SCSI Bus is reset.
6829 * ADV_FALSE(0) - Microcode command failed.
6830 * ADV_ERROR(-1) - Microcode command timed-out. Microcode or IC
6831 * may be hung which requires driver recovery.
6833 static int AdvResetSB(ADV_DVC_VAR *asc_dvc)
6838 * Send the SCSI Bus Reset idle start idle command which asserts
6839 * the SCSI Bus Reset signal.
6841 status = AdvSendIdleCmd(asc_dvc, (ushort)IDLE_CMD_SCSI_RESET_START, 0L);
6842 if (status != ADV_TRUE) {
6847 * Delay for the specified SCSI Bus Reset hold time.
6849 * The hold time delay is done on the host because the RISC has no
6850 * microsecond accurate timer.
6852 udelay(ASC_SCSI_RESET_HOLD_TIME_US);
6855 * Send the SCSI Bus Reset end idle command which de-asserts
6856 * the SCSI Bus Reset signal and purges any pending requests.
6858 status = AdvSendIdleCmd(asc_dvc, (ushort)IDLE_CMD_SCSI_RESET_END, 0L);
6859 if (status != ADV_TRUE) {
6863 mdelay(asc_dvc->scsi_reset_wait * 1000); /* XXX: msleep? */
6869 * Initialize the ASC-3550.
6871 * On failure set the ADV_DVC_VAR field 'err_code' and return ADV_ERROR.
6873 * For a non-fatal error return a warning code. If there are no warnings
6874 * then 0 is returned.
6876 * Needed after initialization for error recovery.
6878 static int AdvInitAsc3550Driver(ADV_DVC_VAR *asc_dvc)
6880 AdvPortAddr iop_base;
6889 ushort bios_mem[ASC_MC_BIOSLEN / 2]; /* BIOS RISC Memory 0x40-0x8F. */
6890 ushort wdtr_able = 0, sdtr_able, tagqng_able;
6891 uchar max_cmd[ADV_MAX_TID + 1];
6893 /* If there is already an error, don't continue. */
6894 if (asc_dvc->err_code != 0)
6898 * The caller must set 'chip_type' to ADV_CHIP_ASC3550.
6900 if (asc_dvc->chip_type != ADV_CHIP_ASC3550) {
6901 asc_dvc->err_code = ASC_IERR_BAD_CHIPTYPE;
6906 iop_base = asc_dvc->iop_base;
6909 * Save the RISC memory BIOS region before writing the microcode.
6910 * The BIOS may already be loaded and using its RISC LRAM region
6911 * so its region must be saved and restored.
6913 * Note: This code makes the assumption, which is currently true,
6914 * that a chip reset does not clear RISC LRAM.
6916 for (i = 0; i < ASC_MC_BIOSLEN / 2; i++) {
6917 AdvReadWordLram(iop_base, ASC_MC_BIOSMEM + (2 * i),
6922 * Save current per TID negotiated values.
6924 if (bios_mem[(ASC_MC_BIOS_SIGNATURE - ASC_MC_BIOSMEM) / 2] == 0x55AA) {
6925 ushort bios_version, major, minor;
6928 bios_mem[(ASC_MC_BIOS_VERSION - ASC_MC_BIOSMEM) / 2];
6929 major = (bios_version >> 12) & 0xF;
6930 minor = (bios_version >> 8) & 0xF;
6931 if (major < 3 || (major == 3 && minor == 1)) {
6932 /* BIOS 3.1 and earlier location of 'wdtr_able' variable. */
6933 AdvReadWordLram(iop_base, 0x120, wdtr_able);
6935 AdvReadWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able);
6938 AdvReadWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
6939 AdvReadWordLram(iop_base, ASC_MC_TAGQNG_ABLE, tagqng_able);
6940 for (tid = 0; tid <= ADV_MAX_TID; tid++) {
6941 AdvReadByteLram(iop_base, ASC_MC_NUMBER_OF_MAX_CMD + tid,
6945 asc_dvc->err_code = AdvLoadMicrocode(iop_base, _adv_asc3550_buf,
6946 _adv_asc3550_size, ADV_3550_MEMSIZE,
6947 _adv_asc3550_chksum);
6948 if (asc_dvc->err_code)
6952 * Restore the RISC memory BIOS region.
6954 for (i = 0; i < ASC_MC_BIOSLEN / 2; i++) {
6955 AdvWriteWordLram(iop_base, ASC_MC_BIOSMEM + (2 * i),
6960 * Calculate and write the microcode code checksum to the microcode
6961 * code checksum location ASC_MC_CODE_CHK_SUM (0x2C).
6963 AdvReadWordLram(iop_base, ASC_MC_CODE_BEGIN_ADDR, begin_addr);
6964 AdvReadWordLram(iop_base, ASC_MC_CODE_END_ADDR, end_addr);
6966 AdvWriteWordRegister(iop_base, IOPW_RAM_ADDR, begin_addr);
6967 for (word = begin_addr; word < end_addr; word += 2) {
6968 code_sum += AdvReadWordAutoIncLram(iop_base);
6970 AdvWriteWordLram(iop_base, ASC_MC_CODE_CHK_SUM, code_sum);
6973 * Read and save microcode version and date.
6975 AdvReadWordLram(iop_base, ASC_MC_VERSION_DATE,
6976 asc_dvc->cfg->mcode_date);
6977 AdvReadWordLram(iop_base, ASC_MC_VERSION_NUM,
6978 asc_dvc->cfg->mcode_version);
6981 * Set the chip type to indicate the ASC3550.
6983 AdvWriteWordLram(iop_base, ASC_MC_CHIP_TYPE, ADV_CHIP_ASC3550);
6986 * If the PCI Configuration Command Register "Parity Error Response
6987 * Control" Bit was clear (0), then set the microcode variable
6988 * 'control_flag' CONTROL_FLAG_IGNORE_PERR flag to tell the microcode
6989 * to ignore DMA parity errors.
6991 if (asc_dvc->cfg->control_flag & CONTROL_FLAG_IGNORE_PERR) {
6992 AdvReadWordLram(iop_base, ASC_MC_CONTROL_FLAG, word);
6993 word |= CONTROL_FLAG_IGNORE_PERR;
6994 AdvWriteWordLram(iop_base, ASC_MC_CONTROL_FLAG, word);
6998 * For ASC-3550, setting the START_CTL_EMFU [3:2] bits sets a FIFO
6999 * threshold of 128 bytes. This register is only accessible to the host.
7001 AdvWriteByteRegister(iop_base, IOPB_DMA_CFG0,
7002 START_CTL_EMFU | READ_CMD_MRM);
7005 * Microcode operating variables for WDTR, SDTR, and command tag
7006 * queuing will be set in slave_configure() based on what a
7007 * device reports it is capable of in Inquiry byte 7.
7009 * If SCSI Bus Resets have been disabled, then directly set
7010 * SDTR and WDTR from the EEPROM configuration. This will allow
7011 * the BIOS and warm boot to work without a SCSI bus hang on
7012 * the Inquiry caused by host and target mismatched DTR values.
7013 * Without the SCSI Bus Reset, before an Inquiry a device can't
7014 * be assumed to be in Asynchronous, Narrow mode.
7016 if ((asc_dvc->bios_ctrl & BIOS_CTRL_RESET_SCSI_BUS) == 0) {
7017 AdvWriteWordLram(iop_base, ASC_MC_WDTR_ABLE,
7018 asc_dvc->wdtr_able);
7019 AdvWriteWordLram(iop_base, ASC_MC_SDTR_ABLE,
7020 asc_dvc->sdtr_able);
7024 * Set microcode operating variables for SDTR_SPEED1, SDTR_SPEED2,
7025 * SDTR_SPEED3, and SDTR_SPEED4 based on the ULTRA EEPROM per TID
7026 * bitmask. These values determine the maximum SDTR speed negotiated
7029 * The SDTR per TID bitmask overrides the SDTR_SPEED1, SDTR_SPEED2,
7030 * SDTR_SPEED3, and SDTR_SPEED4 values so it is safe to set them
7031 * without determining here whether the device supports SDTR.
7033 * 4-bit speed SDTR speed name
7034 * =========== ===============
7035 * 0000b (0x0) SDTR disabled
7037 * 0010b (0x2) 10 Mhz
7038 * 0011b (0x3) 20 Mhz (Ultra)
7039 * 0100b (0x4) 40 Mhz (LVD/Ultra2)
7040 * 0101b (0x5) 80 Mhz (LVD2/Ultra3)
7041 * 0110b (0x6) Undefined
7043 * 1111b (0xF) Undefined
7046 for (tid = 0; tid <= ADV_MAX_TID; tid++) {
7047 if (ADV_TID_TO_TIDMASK(tid) & asc_dvc->ultra_able) {
7048 /* Set Ultra speed for TID 'tid'. */
7049 word |= (0x3 << (4 * (tid % 4)));
7051 /* Set Fast speed for TID 'tid'. */
7052 word |= (0x2 << (4 * (tid % 4)));
7054 if (tid == 3) { /* Check if done with sdtr_speed1. */
7055 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED1, word);
7057 } else if (tid == 7) { /* Check if done with sdtr_speed2. */
7058 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED2, word);
7060 } else if (tid == 11) { /* Check if done with sdtr_speed3. */
7061 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED3, word);
7063 } else if (tid == 15) { /* Check if done with sdtr_speed4. */
7064 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED4, word);
7070 * Set microcode operating variable for the disconnect per TID bitmask.
7072 AdvWriteWordLram(iop_base, ASC_MC_DISC_ENABLE,
7073 asc_dvc->cfg->disc_enable);
7076 * Set SCSI_CFG0 Microcode Default Value.
7078 * The microcode will set the SCSI_CFG0 register using this value
7079 * after it is started below.
7081 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SCSI_CFG0,
7082 PARITY_EN | QUEUE_128 | SEL_TMO_LONG | OUR_ID_EN |
7083 asc_dvc->chip_scsi_id);
7086 * Determine SCSI_CFG1 Microcode Default Value.
7088 * The microcode will set the SCSI_CFG1 register using this value
7089 * after it is started below.
7092 /* Read current SCSI_CFG1 Register value. */
7093 scsi_cfg1 = AdvReadWordRegister(iop_base, IOPW_SCSI_CFG1);
7096 * If all three connectors are in use, return an error.
7098 if ((scsi_cfg1 & CABLE_ILLEGAL_A) == 0 ||
7099 (scsi_cfg1 & CABLE_ILLEGAL_B) == 0) {
7100 asc_dvc->err_code |= ASC_IERR_ILLEGAL_CONNECTION;
7105 * If the internal narrow cable is reversed all of the SCSI_CTRL
7106 * register signals will be set. Check for and return an error if
7107 * this condition is found.
7109 if ((AdvReadWordRegister(iop_base, IOPW_SCSI_CTRL) & 0x3F07) == 0x3F07) {
7110 asc_dvc->err_code |= ASC_IERR_REVERSED_CABLE;
7115 * If this is a differential board and a single-ended device
7116 * is attached to one of the connectors, return an error.
7118 if ((scsi_cfg1 & DIFF_MODE) && (scsi_cfg1 & DIFF_SENSE) == 0) {
7119 asc_dvc->err_code |= ASC_IERR_SINGLE_END_DEVICE;
7124 * If automatic termination control is enabled, then set the
7125 * termination value based on a table listed in a_condor.h.
7127 * If manual termination was specified with an EEPROM setting
7128 * then 'termination' was set-up in AdvInitFrom3550EEPROM() and
7129 * is ready to be 'ored' into SCSI_CFG1.
7131 if (asc_dvc->cfg->termination == 0) {
7133 * The software always controls termination by setting TERM_CTL_SEL.
7134 * If TERM_CTL_SEL were set to 0, the hardware would set termination.
7136 asc_dvc->cfg->termination |= TERM_CTL_SEL;
7138 switch (scsi_cfg1 & CABLE_DETECT) {
7139 /* TERM_CTL_H: on, TERM_CTL_L: on */
7146 asc_dvc->cfg->termination |= (TERM_CTL_H | TERM_CTL_L);
7149 /* TERM_CTL_H: on, TERM_CTL_L: off */
7155 asc_dvc->cfg->termination |= TERM_CTL_H;
7158 /* TERM_CTL_H: off, TERM_CTL_L: off */
7166 * Clear any set TERM_CTL_H and TERM_CTL_L bits.
7168 scsi_cfg1 &= ~TERM_CTL;
7171 * Invert the TERM_CTL_H and TERM_CTL_L bits and then
7172 * set 'scsi_cfg1'. The TERM_POL bit does not need to be
7173 * referenced, because the hardware internally inverts
7174 * the Termination High and Low bits if TERM_POL is set.
7176 scsi_cfg1 |= (TERM_CTL_SEL | (~asc_dvc->cfg->termination & TERM_CTL));
7179 * Set SCSI_CFG1 Microcode Default Value
7181 * Set filter value and possibly modified termination control
7182 * bits in the Microcode SCSI_CFG1 Register Value.
7184 * The microcode will set the SCSI_CFG1 register using this value
7185 * after it is started below.
7187 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SCSI_CFG1,
7188 FLTR_DISABLE | scsi_cfg1);
7191 * Set MEM_CFG Microcode Default Value
7193 * The microcode will set the MEM_CFG register using this value
7194 * after it is started below.
7196 * MEM_CFG may be accessed as a word or byte, but only bits 0-7
7199 * ASC-3550 has 8KB internal memory.
7201 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_MEM_CFG,
7202 BIOS_EN | RAM_SZ_8KB);
7205 * Set SEL_MASK Microcode Default Value
7207 * The microcode will set the SEL_MASK register using this value
7208 * after it is started below.
7210 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SEL_MASK,
7211 ADV_TID_TO_TIDMASK(asc_dvc->chip_scsi_id));
7213 AdvBuildCarrierFreelist(asc_dvc);
7216 * Set-up the Host->RISC Initiator Command Queue (ICQ).
7219 if ((asc_dvc->icq_sp = asc_dvc->carr_freelist) == NULL) {
7220 asc_dvc->err_code |= ASC_IERR_NO_CARRIER;
7223 asc_dvc->carr_freelist = (ADV_CARR_T *)
7224 ADV_U32_TO_VADDR(le32_to_cpu(asc_dvc->icq_sp->next_vpa));
7227 * The first command issued will be placed in the stopper carrier.
7229 asc_dvc->icq_sp->next_vpa = cpu_to_le32(ASC_CQ_STOPPER);
7232 * Set RISC ICQ physical address start value.
7234 AdvWriteDWordLramNoSwap(iop_base, ASC_MC_ICQ, asc_dvc->icq_sp->carr_pa);
7237 * Set-up the RISC->Host Initiator Response Queue (IRQ).
7239 if ((asc_dvc->irq_sp = asc_dvc->carr_freelist) == NULL) {
7240 asc_dvc->err_code |= ASC_IERR_NO_CARRIER;
7243 asc_dvc->carr_freelist = (ADV_CARR_T *)
7244 ADV_U32_TO_VADDR(le32_to_cpu(asc_dvc->irq_sp->next_vpa));
7247 * The first command completed by the RISC will be placed in
7250 * Note: Set 'next_vpa' to ASC_CQ_STOPPER. When the request is
7251 * completed the RISC will set the ASC_RQ_STOPPER bit.
7253 asc_dvc->irq_sp->next_vpa = cpu_to_le32(ASC_CQ_STOPPER);
7256 * Set RISC IRQ physical address start value.
7258 AdvWriteDWordLramNoSwap(iop_base, ASC_MC_IRQ, asc_dvc->irq_sp->carr_pa);
7259 asc_dvc->carr_pending_cnt = 0;
7261 AdvWriteByteRegister(iop_base, IOPB_INTR_ENABLES,
7262 (ADV_INTR_ENABLE_HOST_INTR |
7263 ADV_INTR_ENABLE_GLOBAL_INTR));
7265 AdvReadWordLram(iop_base, ASC_MC_CODE_BEGIN_ADDR, word);
7266 AdvWriteWordRegister(iop_base, IOPW_PC, word);
7268 /* finally, finally, gentlemen, start your engine */
7269 AdvWriteWordRegister(iop_base, IOPW_RISC_CSR, ADV_RISC_CSR_RUN);
7272 * Reset the SCSI Bus if the EEPROM indicates that SCSI Bus
7273 * Resets should be performed. The RISC has to be running
7274 * to issue a SCSI Bus Reset.
7276 if (asc_dvc->bios_ctrl & BIOS_CTRL_RESET_SCSI_BUS) {
7278 * If the BIOS Signature is present in memory, restore the
7279 * BIOS Handshake Configuration Table and do not perform
7282 if (bios_mem[(ASC_MC_BIOS_SIGNATURE - ASC_MC_BIOSMEM) / 2] ==
7285 * Restore per TID negotiated values.
7287 AdvWriteWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able);
7288 AdvWriteWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
7289 AdvWriteWordLram(iop_base, ASC_MC_TAGQNG_ABLE,
7291 for (tid = 0; tid <= ADV_MAX_TID; tid++) {
7292 AdvWriteByteLram(iop_base,
7293 ASC_MC_NUMBER_OF_MAX_CMD + tid,
7297 if (AdvResetSB(asc_dvc) != ADV_TRUE) {
7298 warn_code = ASC_WARN_BUSRESET_ERROR;
7307 * Initialize the ASC-38C0800.
7309 * On failure set the ADV_DVC_VAR field 'err_code' and return ADV_ERROR.
7311 * For a non-fatal error return a warning code. If there are no warnings
7312 * then 0 is returned.
7314 * Needed after initialization for error recovery.
7316 static int AdvInitAsc38C0800Driver(ADV_DVC_VAR *asc_dvc)
7318 AdvPortAddr iop_base;
7328 ushort bios_mem[ASC_MC_BIOSLEN / 2]; /* BIOS RISC Memory 0x40-0x8F. */
7329 ushort wdtr_able, sdtr_able, tagqng_able;
7330 uchar max_cmd[ADV_MAX_TID + 1];
7332 /* If there is already an error, don't continue. */
7333 if (asc_dvc->err_code != 0)
7337 * The caller must set 'chip_type' to ADV_CHIP_ASC38C0800.
7339 if (asc_dvc->chip_type != ADV_CHIP_ASC38C0800) {
7340 asc_dvc->err_code = ASC_IERR_BAD_CHIPTYPE;
7345 iop_base = asc_dvc->iop_base;
7348 * Save the RISC memory BIOS region before writing the microcode.
7349 * The BIOS may already be loaded and using its RISC LRAM region
7350 * so its region must be saved and restored.
7352 * Note: This code makes the assumption, which is currently true,
7353 * that a chip reset does not clear RISC LRAM.
7355 for (i = 0; i < ASC_MC_BIOSLEN / 2; i++) {
7356 AdvReadWordLram(iop_base, ASC_MC_BIOSMEM + (2 * i),
7361 * Save current per TID negotiated values.
7363 AdvReadWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able);
7364 AdvReadWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
7365 AdvReadWordLram(iop_base, ASC_MC_TAGQNG_ABLE, tagqng_able);
7366 for (tid = 0; tid <= ADV_MAX_TID; tid++) {
7367 AdvReadByteLram(iop_base, ASC_MC_NUMBER_OF_MAX_CMD + tid,
7372 * RAM BIST (RAM Built-In Self Test)
7374 * Address : I/O base + offset 0x38h register (byte).
7375 * Function: Bit 7-6(RW) : RAM mode
7376 * Normal Mode : 0x00
7377 * Pre-test Mode : 0x40
7378 * RAM Test Mode : 0x80
7380 * Bit 4(RO) : Done bit
7381 * Bit 3-0(RO) : Status
7383 * Int_RAM Error : 0x04
7388 * Note: RAM BIST code should be put right here, before loading the
7389 * microcode and after saving the RISC memory BIOS region.
7395 * Write PRE_TEST_MODE (0x40) to register and wait for 10 milliseconds.
7396 * If Done bit not set or low nibble not PRE_TEST_VALUE (0x05), return
7397 * an error. Reset to NORMAL_MODE (0x00) and do again. If cannot reset
7398 * to NORMAL_MODE, return an error too.
7400 for (i = 0; i < 2; i++) {
7401 AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, PRE_TEST_MODE);
7402 mdelay(10); /* Wait for 10ms before reading back. */
7403 byte = AdvReadByteRegister(iop_base, IOPB_RAM_BIST);
7404 if ((byte & RAM_TEST_DONE) == 0
7405 || (byte & 0x0F) != PRE_TEST_VALUE) {
7406 asc_dvc->err_code = ASC_IERR_BIST_PRE_TEST;
7410 AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, NORMAL_MODE);
7411 mdelay(10); /* Wait for 10ms before reading back. */
7412 if (AdvReadByteRegister(iop_base, IOPB_RAM_BIST)
7414 asc_dvc->err_code = ASC_IERR_BIST_PRE_TEST;
7420 * LRAM Test - It takes about 1.5 ms to run through the test.
7422 * Write RAM_TEST_MODE (0x80) to register and wait for 10 milliseconds.
7423 * If Done bit not set or Status not 0, save register byte, set the
7424 * err_code, and return an error.
7426 AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, RAM_TEST_MODE);
7427 mdelay(10); /* Wait for 10ms before checking status. */
7429 byte = AdvReadByteRegister(iop_base, IOPB_RAM_BIST);
7430 if ((byte & RAM_TEST_DONE) == 0 || (byte & RAM_TEST_STATUS) != 0) {
7431 /* Get here if Done bit not set or Status not 0. */
7432 asc_dvc->bist_err_code = byte; /* for BIOS display message */
7433 asc_dvc->err_code = ASC_IERR_BIST_RAM_TEST;
7437 /* We need to reset back to normal mode after LRAM test passes. */
7438 AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, NORMAL_MODE);
7440 asc_dvc->err_code = AdvLoadMicrocode(iop_base, _adv_asc38C0800_buf,
7441 _adv_asc38C0800_size, ADV_38C0800_MEMSIZE,
7442 _adv_asc38C0800_chksum);
7443 if (asc_dvc->err_code)
7447 * Restore the RISC memory BIOS region.
7449 for (i = 0; i < ASC_MC_BIOSLEN / 2; i++) {
7450 AdvWriteWordLram(iop_base, ASC_MC_BIOSMEM + (2 * i),
7455 * Calculate and write the microcode code checksum to the microcode
7456 * code checksum location ASC_MC_CODE_CHK_SUM (0x2C).
7458 AdvReadWordLram(iop_base, ASC_MC_CODE_BEGIN_ADDR, begin_addr);
7459 AdvReadWordLram(iop_base, ASC_MC_CODE_END_ADDR, end_addr);
7461 AdvWriteWordRegister(iop_base, IOPW_RAM_ADDR, begin_addr);
7462 for (word = begin_addr; word < end_addr; word += 2) {
7463 code_sum += AdvReadWordAutoIncLram(iop_base);
7465 AdvWriteWordLram(iop_base, ASC_MC_CODE_CHK_SUM, code_sum);
7468 * Read microcode version and date.
7470 AdvReadWordLram(iop_base, ASC_MC_VERSION_DATE,
7471 asc_dvc->cfg->mcode_date);
7472 AdvReadWordLram(iop_base, ASC_MC_VERSION_NUM,
7473 asc_dvc->cfg->mcode_version);
7476 * Set the chip type to indicate the ASC38C0800.
7478 AdvWriteWordLram(iop_base, ASC_MC_CHIP_TYPE, ADV_CHIP_ASC38C0800);
7481 * Write 1 to bit 14 'DIS_TERM_DRV' in the SCSI_CFG1 register.
7482 * When DIS_TERM_DRV set to 1, C_DET[3:0] will reflect current
7483 * cable detection and then we are able to read C_DET[3:0].
7485 * Note: We will reset DIS_TERM_DRV to 0 in the 'Set SCSI_CFG1
7486 * Microcode Default Value' section below.
7488 scsi_cfg1 = AdvReadWordRegister(iop_base, IOPW_SCSI_CFG1);
7489 AdvWriteWordRegister(iop_base, IOPW_SCSI_CFG1,
7490 scsi_cfg1 | DIS_TERM_DRV);
7493 * If the PCI Configuration Command Register "Parity Error Response
7494 * Control" Bit was clear (0), then set the microcode variable
7495 * 'control_flag' CONTROL_FLAG_IGNORE_PERR flag to tell the microcode
7496 * to ignore DMA parity errors.
7498 if (asc_dvc->cfg->control_flag & CONTROL_FLAG_IGNORE_PERR) {
7499 AdvReadWordLram(iop_base, ASC_MC_CONTROL_FLAG, word);
7500 word |= CONTROL_FLAG_IGNORE_PERR;
7501 AdvWriteWordLram(iop_base, ASC_MC_CONTROL_FLAG, word);
7505 * For ASC-38C0800, set FIFO_THRESH_80B [6:4] bits and START_CTL_TH [3:2]
7506 * bits for the default FIFO threshold.
7508 * Note: ASC-38C0800 FIFO threshold has been changed to 256 bytes.
7510 * For DMA Errata #4 set the BC_THRESH_ENB bit.
7512 AdvWriteByteRegister(iop_base, IOPB_DMA_CFG0,
7513 BC_THRESH_ENB | FIFO_THRESH_80B | START_CTL_TH |
7517 * Microcode operating variables for WDTR, SDTR, and command tag
7518 * queuing will be set in slave_configure() based on what a
7519 * device reports it is capable of in Inquiry byte 7.
7521 * If SCSI Bus Resets have been disabled, then directly set
7522 * SDTR and WDTR from the EEPROM configuration. This will allow
7523 * the BIOS and warm boot to work without a SCSI bus hang on
7524 * the Inquiry caused by host and target mismatched DTR values.
7525 * Without the SCSI Bus Reset, before an Inquiry a device can't
7526 * be assumed to be in Asynchronous, Narrow mode.
7528 if ((asc_dvc->bios_ctrl & BIOS_CTRL_RESET_SCSI_BUS) == 0) {
7529 AdvWriteWordLram(iop_base, ASC_MC_WDTR_ABLE,
7530 asc_dvc->wdtr_able);
7531 AdvWriteWordLram(iop_base, ASC_MC_SDTR_ABLE,
7532 asc_dvc->sdtr_able);
7536 * Set microcode operating variables for DISC and SDTR_SPEED1,
7537 * SDTR_SPEED2, SDTR_SPEED3, and SDTR_SPEED4 based on the EEPROM
7538 * configuration values.
7540 * The SDTR per TID bitmask overrides the SDTR_SPEED1, SDTR_SPEED2,
7541 * SDTR_SPEED3, and SDTR_SPEED4 values so it is safe to set them
7542 * without determining here whether the device supports SDTR.
7544 AdvWriteWordLram(iop_base, ASC_MC_DISC_ENABLE,
7545 asc_dvc->cfg->disc_enable);
7546 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED1, asc_dvc->sdtr_speed1);
7547 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED2, asc_dvc->sdtr_speed2);
7548 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED3, asc_dvc->sdtr_speed3);
7549 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED4, asc_dvc->sdtr_speed4);
7552 * Set SCSI_CFG0 Microcode Default Value.
7554 * The microcode will set the SCSI_CFG0 register using this value
7555 * after it is started below.
7557 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SCSI_CFG0,
7558 PARITY_EN | QUEUE_128 | SEL_TMO_LONG | OUR_ID_EN |
7559 asc_dvc->chip_scsi_id);
7562 * Determine SCSI_CFG1 Microcode Default Value.
7564 * The microcode will set the SCSI_CFG1 register using this value
7565 * after it is started below.
7568 /* Read current SCSI_CFG1 Register value. */
7569 scsi_cfg1 = AdvReadWordRegister(iop_base, IOPW_SCSI_CFG1);
7572 * If the internal narrow cable is reversed all of the SCSI_CTRL
7573 * register signals will be set. Check for and return an error if
7574 * this condition is found.
7576 if ((AdvReadWordRegister(iop_base, IOPW_SCSI_CTRL) & 0x3F07) == 0x3F07) {
7577 asc_dvc->err_code |= ASC_IERR_REVERSED_CABLE;
7582 * All kind of combinations of devices attached to one of four
7583 * connectors are acceptable except HVD device attached. For example,
7584 * LVD device can be attached to SE connector while SE device attached
7585 * to LVD connector. If LVD device attached to SE connector, it only
7586 * runs up to Ultra speed.
7588 * If an HVD device is attached to one of LVD connectors, return an
7589 * error. However, there is no way to detect HVD device attached to
7592 if (scsi_cfg1 & HVD) {
7593 asc_dvc->err_code = ASC_IERR_HVD_DEVICE;
7598 * If either SE or LVD automatic termination control is enabled, then
7599 * set the termination value based on a table listed in a_condor.h.
7601 * If manual termination was specified with an EEPROM setting then
7602 * 'termination' was set-up in AdvInitFrom38C0800EEPROM() and is ready
7603 * to be 'ored' into SCSI_CFG1.
7605 if ((asc_dvc->cfg->termination & TERM_SE) == 0) {
7606 /* SE automatic termination control is enabled. */
7607 switch (scsi_cfg1 & C_DET_SE) {
7608 /* TERM_SE_HI: on, TERM_SE_LO: on */
7612 asc_dvc->cfg->termination |= TERM_SE;
7615 /* TERM_SE_HI: on, TERM_SE_LO: off */
7617 asc_dvc->cfg->termination |= TERM_SE_HI;
7622 if ((asc_dvc->cfg->termination & TERM_LVD) == 0) {
7623 /* LVD automatic termination control is enabled. */
7624 switch (scsi_cfg1 & C_DET_LVD) {
7625 /* TERM_LVD_HI: on, TERM_LVD_LO: on */
7629 asc_dvc->cfg->termination |= TERM_LVD;
7632 /* TERM_LVD_HI: off, TERM_LVD_LO: off */
7639 * Clear any set TERM_SE and TERM_LVD bits.
7641 scsi_cfg1 &= (~TERM_SE & ~TERM_LVD);
7644 * Invert the TERM_SE and TERM_LVD bits and then set 'scsi_cfg1'.
7646 scsi_cfg1 |= (~asc_dvc->cfg->termination & 0xF0);
7649 * Clear BIG_ENDIAN, DIS_TERM_DRV, Terminator Polarity and HVD/LVD/SE
7650 * bits and set possibly modified termination control bits in the
7651 * Microcode SCSI_CFG1 Register Value.
7653 scsi_cfg1 &= (~BIG_ENDIAN & ~DIS_TERM_DRV & ~TERM_POL & ~HVD_LVD_SE);
7656 * Set SCSI_CFG1 Microcode Default Value
7658 * Set possibly modified termination control and reset DIS_TERM_DRV
7659 * bits in the Microcode SCSI_CFG1 Register Value.
7661 * The microcode will set the SCSI_CFG1 register using this value
7662 * after it is started below.
7664 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SCSI_CFG1, scsi_cfg1);
7667 * Set MEM_CFG Microcode Default Value
7669 * The microcode will set the MEM_CFG register using this value
7670 * after it is started below.
7672 * MEM_CFG may be accessed as a word or byte, but only bits 0-7
7675 * ASC-38C0800 has 16KB internal memory.
7677 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_MEM_CFG,
7678 BIOS_EN | RAM_SZ_16KB);
7681 * Set SEL_MASK Microcode Default Value
7683 * The microcode will set the SEL_MASK register using this value
7684 * after it is started below.
7686 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SEL_MASK,
7687 ADV_TID_TO_TIDMASK(asc_dvc->chip_scsi_id));
7689 AdvBuildCarrierFreelist(asc_dvc);
7692 * Set-up the Host->RISC Initiator Command Queue (ICQ).
7695 if ((asc_dvc->icq_sp = asc_dvc->carr_freelist) == NULL) {
7696 asc_dvc->err_code |= ASC_IERR_NO_CARRIER;
7699 asc_dvc->carr_freelist = (ADV_CARR_T *)
7700 ADV_U32_TO_VADDR(le32_to_cpu(asc_dvc->icq_sp->next_vpa));
7703 * The first command issued will be placed in the stopper carrier.
7705 asc_dvc->icq_sp->next_vpa = cpu_to_le32(ASC_CQ_STOPPER);
7708 * Set RISC ICQ physical address start value.
7709 * carr_pa is LE, must be native before write
7711 AdvWriteDWordLramNoSwap(iop_base, ASC_MC_ICQ, asc_dvc->icq_sp->carr_pa);
7714 * Set-up the RISC->Host Initiator Response Queue (IRQ).
7716 if ((asc_dvc->irq_sp = asc_dvc->carr_freelist) == NULL) {
7717 asc_dvc->err_code |= ASC_IERR_NO_CARRIER;
7720 asc_dvc->carr_freelist = (ADV_CARR_T *)
7721 ADV_U32_TO_VADDR(le32_to_cpu(asc_dvc->irq_sp->next_vpa));
7724 * The first command completed by the RISC will be placed in
7727 * Note: Set 'next_vpa' to ASC_CQ_STOPPER. When the request is
7728 * completed the RISC will set the ASC_RQ_STOPPER bit.
7730 asc_dvc->irq_sp->next_vpa = cpu_to_le32(ASC_CQ_STOPPER);
7733 * Set RISC IRQ physical address start value.
7735 * carr_pa is LE, must be native before write *
7737 AdvWriteDWordLramNoSwap(iop_base, ASC_MC_IRQ, asc_dvc->irq_sp->carr_pa);
7738 asc_dvc->carr_pending_cnt = 0;
7740 AdvWriteByteRegister(iop_base, IOPB_INTR_ENABLES,
7741 (ADV_INTR_ENABLE_HOST_INTR |
7742 ADV_INTR_ENABLE_GLOBAL_INTR));
7744 AdvReadWordLram(iop_base, ASC_MC_CODE_BEGIN_ADDR, word);
7745 AdvWriteWordRegister(iop_base, IOPW_PC, word);
7747 /* finally, finally, gentlemen, start your engine */
7748 AdvWriteWordRegister(iop_base, IOPW_RISC_CSR, ADV_RISC_CSR_RUN);
7751 * Reset the SCSI Bus if the EEPROM indicates that SCSI Bus
7752 * Resets should be performed. The RISC has to be running
7753 * to issue a SCSI Bus Reset.
7755 if (asc_dvc->bios_ctrl & BIOS_CTRL_RESET_SCSI_BUS) {
7757 * If the BIOS Signature is present in memory, restore the
7758 * BIOS Handshake Configuration Table and do not perform
7761 if (bios_mem[(ASC_MC_BIOS_SIGNATURE - ASC_MC_BIOSMEM) / 2] ==
7764 * Restore per TID negotiated values.
7766 AdvWriteWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able);
7767 AdvWriteWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
7768 AdvWriteWordLram(iop_base, ASC_MC_TAGQNG_ABLE,
7770 for (tid = 0; tid <= ADV_MAX_TID; tid++) {
7771 AdvWriteByteLram(iop_base,
7772 ASC_MC_NUMBER_OF_MAX_CMD + tid,
7776 if (AdvResetSB(asc_dvc) != ADV_TRUE) {
7777 warn_code = ASC_WARN_BUSRESET_ERROR;
7786 * Initialize the ASC-38C1600.
7788 * On failure set the ASC_DVC_VAR field 'err_code' and return ADV_ERROR.
7790 * For a non-fatal error return a warning code. If there are no warnings
7791 * then 0 is returned.
7793 * Needed after initialization for error recovery.
7795 static int AdvInitAsc38C1600Driver(ADV_DVC_VAR *asc_dvc)
7797 AdvPortAddr iop_base;
7807 ushort bios_mem[ASC_MC_BIOSLEN / 2]; /* BIOS RISC Memory 0x40-0x8F. */
7808 ushort wdtr_able, sdtr_able, ppr_able, tagqng_able;
7809 uchar max_cmd[ASC_MAX_TID + 1];
7811 /* If there is already an error, don't continue. */
7812 if (asc_dvc->err_code != 0) {
7817 * The caller must set 'chip_type' to ADV_CHIP_ASC38C1600.
7819 if (asc_dvc->chip_type != ADV_CHIP_ASC38C1600) {
7820 asc_dvc->err_code = ASC_IERR_BAD_CHIPTYPE;
7825 iop_base = asc_dvc->iop_base;
7828 * Save the RISC memory BIOS region before writing the microcode.
7829 * The BIOS may already be loaded and using its RISC LRAM region
7830 * so its region must be saved and restored.
7832 * Note: This code makes the assumption, which is currently true,
7833 * that a chip reset does not clear RISC LRAM.
7835 for (i = 0; i < ASC_MC_BIOSLEN / 2; i++) {
7836 AdvReadWordLram(iop_base, ASC_MC_BIOSMEM + (2 * i),
7841 * Save current per TID negotiated values.
7843 AdvReadWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able);
7844 AdvReadWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
7845 AdvReadWordLram(iop_base, ASC_MC_PPR_ABLE, ppr_able);
7846 AdvReadWordLram(iop_base, ASC_MC_TAGQNG_ABLE, tagqng_able);
7847 for (tid = 0; tid <= ASC_MAX_TID; tid++) {
7848 AdvReadByteLram(iop_base, ASC_MC_NUMBER_OF_MAX_CMD + tid,
7853 * RAM BIST (Built-In Self Test)
7855 * Address : I/O base + offset 0x38h register (byte).
7856 * Function: Bit 7-6(RW) : RAM mode
7857 * Normal Mode : 0x00
7858 * Pre-test Mode : 0x40
7859 * RAM Test Mode : 0x80
7861 * Bit 4(RO) : Done bit
7862 * Bit 3-0(RO) : Status
7864 * Int_RAM Error : 0x04
7869 * Note: RAM BIST code should be put right here, before loading the
7870 * microcode and after saving the RISC memory BIOS region.
7876 * Write PRE_TEST_MODE (0x40) to register and wait for 10 milliseconds.
7877 * If Done bit not set or low nibble not PRE_TEST_VALUE (0x05), return
7878 * an error. Reset to NORMAL_MODE (0x00) and do again. If cannot reset
7879 * to NORMAL_MODE, return an error too.
7881 for (i = 0; i < 2; i++) {
7882 AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, PRE_TEST_MODE);
7883 mdelay(10); /* Wait for 10ms before reading back. */
7884 byte = AdvReadByteRegister(iop_base, IOPB_RAM_BIST);
7885 if ((byte & RAM_TEST_DONE) == 0
7886 || (byte & 0x0F) != PRE_TEST_VALUE) {
7887 asc_dvc->err_code = ASC_IERR_BIST_PRE_TEST;
7891 AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, NORMAL_MODE);
7892 mdelay(10); /* Wait for 10ms before reading back. */
7893 if (AdvReadByteRegister(iop_base, IOPB_RAM_BIST)
7895 asc_dvc->err_code = ASC_IERR_BIST_PRE_TEST;
7901 * LRAM Test - It takes about 1.5 ms to run through the test.
7903 * Write RAM_TEST_MODE (0x80) to register and wait for 10 milliseconds.
7904 * If Done bit not set or Status not 0, save register byte, set the
7905 * err_code, and return an error.
7907 AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, RAM_TEST_MODE);
7908 mdelay(10); /* Wait for 10ms before checking status. */
7910 byte = AdvReadByteRegister(iop_base, IOPB_RAM_BIST);
7911 if ((byte & RAM_TEST_DONE) == 0 || (byte & RAM_TEST_STATUS) != 0) {
7912 /* Get here if Done bit not set or Status not 0. */
7913 asc_dvc->bist_err_code = byte; /* for BIOS display message */
7914 asc_dvc->err_code = ASC_IERR_BIST_RAM_TEST;
7918 /* We need to reset back to normal mode after LRAM test passes. */
7919 AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, NORMAL_MODE);
7921 asc_dvc->err_code = AdvLoadMicrocode(iop_base, _adv_asc38C1600_buf,
7922 _adv_asc38C1600_size, ADV_38C1600_MEMSIZE,
7923 _adv_asc38C1600_chksum);
7924 if (asc_dvc->err_code)
7928 * Restore the RISC memory BIOS region.
7930 for (i = 0; i < ASC_MC_BIOSLEN / 2; i++) {
7931 AdvWriteWordLram(iop_base, ASC_MC_BIOSMEM + (2 * i),
7936 * Calculate and write the microcode code checksum to the microcode
7937 * code checksum location ASC_MC_CODE_CHK_SUM (0x2C).
7939 AdvReadWordLram(iop_base, ASC_MC_CODE_BEGIN_ADDR, begin_addr);
7940 AdvReadWordLram(iop_base, ASC_MC_CODE_END_ADDR, end_addr);
7942 AdvWriteWordRegister(iop_base, IOPW_RAM_ADDR, begin_addr);
7943 for (word = begin_addr; word < end_addr; word += 2) {
7944 code_sum += AdvReadWordAutoIncLram(iop_base);
7946 AdvWriteWordLram(iop_base, ASC_MC_CODE_CHK_SUM, code_sum);
7949 * Read microcode version and date.
7951 AdvReadWordLram(iop_base, ASC_MC_VERSION_DATE,
7952 asc_dvc->cfg->mcode_date);
7953 AdvReadWordLram(iop_base, ASC_MC_VERSION_NUM,
7954 asc_dvc->cfg->mcode_version);
7957 * Set the chip type to indicate the ASC38C1600.
7959 AdvWriteWordLram(iop_base, ASC_MC_CHIP_TYPE, ADV_CHIP_ASC38C1600);
7962 * Write 1 to bit 14 'DIS_TERM_DRV' in the SCSI_CFG1 register.
7963 * When DIS_TERM_DRV set to 1, C_DET[3:0] will reflect current
7964 * cable detection and then we are able to read C_DET[3:0].
7966 * Note: We will reset DIS_TERM_DRV to 0 in the 'Set SCSI_CFG1
7967 * Microcode Default Value' section below.
7969 scsi_cfg1 = AdvReadWordRegister(iop_base, IOPW_SCSI_CFG1);
7970 AdvWriteWordRegister(iop_base, IOPW_SCSI_CFG1,
7971 scsi_cfg1 | DIS_TERM_DRV);
7974 * If the PCI Configuration Command Register "Parity Error Response
7975 * Control" Bit was clear (0), then set the microcode variable
7976 * 'control_flag' CONTROL_FLAG_IGNORE_PERR flag to tell the microcode
7977 * to ignore DMA parity errors.
7979 if (asc_dvc->cfg->control_flag & CONTROL_FLAG_IGNORE_PERR) {
7980 AdvReadWordLram(iop_base, ASC_MC_CONTROL_FLAG, word);
7981 word |= CONTROL_FLAG_IGNORE_PERR;
7982 AdvWriteWordLram(iop_base, ASC_MC_CONTROL_FLAG, word);
7986 * If the BIOS control flag AIPP (Asynchronous Information
7987 * Phase Protection) disable bit is not set, then set the firmware
7988 * 'control_flag' CONTROL_FLAG_ENABLE_AIPP bit to enable
7989 * AIPP checking and encoding.
7991 if ((asc_dvc->bios_ctrl & BIOS_CTRL_AIPP_DIS) == 0) {
7992 AdvReadWordLram(iop_base, ASC_MC_CONTROL_FLAG, word);
7993 word |= CONTROL_FLAG_ENABLE_AIPP;
7994 AdvWriteWordLram(iop_base, ASC_MC_CONTROL_FLAG, word);
7998 * For ASC-38C1600 use DMA_CFG0 default values: FIFO_THRESH_80B [6:4],
7999 * and START_CTL_TH [3:2].
8001 AdvWriteByteRegister(iop_base, IOPB_DMA_CFG0,
8002 FIFO_THRESH_80B | START_CTL_TH | READ_CMD_MRM);
8005 * Microcode operating variables for WDTR, SDTR, and command tag
8006 * queuing will be set in slave_configure() based on what a
8007 * device reports it is capable of in Inquiry byte 7.
8009 * If SCSI Bus Resets have been disabled, then directly set
8010 * SDTR and WDTR from the EEPROM configuration. This will allow
8011 * the BIOS and warm boot to work without a SCSI bus hang on
8012 * the Inquiry caused by host and target mismatched DTR values.
8013 * Without the SCSI Bus Reset, before an Inquiry a device can't
8014 * be assumed to be in Asynchronous, Narrow mode.
8016 if ((asc_dvc->bios_ctrl & BIOS_CTRL_RESET_SCSI_BUS) == 0) {
8017 AdvWriteWordLram(iop_base, ASC_MC_WDTR_ABLE,
8018 asc_dvc->wdtr_able);
8019 AdvWriteWordLram(iop_base, ASC_MC_SDTR_ABLE,
8020 asc_dvc->sdtr_able);
8024 * Set microcode operating variables for DISC and SDTR_SPEED1,
8025 * SDTR_SPEED2, SDTR_SPEED3, and SDTR_SPEED4 based on the EEPROM
8026 * configuration values.
8028 * The SDTR per TID bitmask overrides the SDTR_SPEED1, SDTR_SPEED2,
8029 * SDTR_SPEED3, and SDTR_SPEED4 values so it is safe to set them
8030 * without determining here whether the device supports SDTR.
8032 AdvWriteWordLram(iop_base, ASC_MC_DISC_ENABLE,
8033 asc_dvc->cfg->disc_enable);
8034 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED1, asc_dvc->sdtr_speed1);
8035 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED2, asc_dvc->sdtr_speed2);
8036 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED3, asc_dvc->sdtr_speed3);
8037 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED4, asc_dvc->sdtr_speed4);
8040 * Set SCSI_CFG0 Microcode Default Value.
8042 * The microcode will set the SCSI_CFG0 register using this value
8043 * after it is started below.
8045 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SCSI_CFG0,
8046 PARITY_EN | QUEUE_128 | SEL_TMO_LONG | OUR_ID_EN |
8047 asc_dvc->chip_scsi_id);
8050 * Calculate SCSI_CFG1 Microcode Default Value.
8052 * The microcode will set the SCSI_CFG1 register using this value
8053 * after it is started below.
8055 * Each ASC-38C1600 function has only two cable detect bits.
8056 * The bus mode override bits are in IOPB_SOFT_OVER_WR.
8058 scsi_cfg1 = AdvReadWordRegister(iop_base, IOPW_SCSI_CFG1);
8061 * If the cable is reversed all of the SCSI_CTRL register signals
8062 * will be set. Check for and return an error if this condition is
8065 if ((AdvReadWordRegister(iop_base, IOPW_SCSI_CTRL) & 0x3F07) == 0x3F07) {
8066 asc_dvc->err_code |= ASC_IERR_REVERSED_CABLE;
8071 * Each ASC-38C1600 function has two connectors. Only an HVD device
8072 * can not be connected to either connector. An LVD device or SE device
8073 * may be connected to either connecor. If an SE device is connected,
8074 * then at most Ultra speed (20 Mhz) can be used on both connectors.
8076 * If an HVD device is attached, return an error.
8078 if (scsi_cfg1 & HVD) {
8079 asc_dvc->err_code |= ASC_IERR_HVD_DEVICE;
8084 * Each function in the ASC-38C1600 uses only the SE cable detect and
8085 * termination because there are two connectors for each function. Each
8086 * function may use either LVD or SE mode. Corresponding the SE automatic
8087 * termination control EEPROM bits are used for each function. Each
8088 * function has its own EEPROM. If SE automatic control is enabled for
8089 * the function, then set the termination value based on a table listed
8092 * If manual termination is specified in the EEPROM for the function,
8093 * then 'termination' was set-up in AscInitFrom38C1600EEPROM() and is
8094 * ready to be 'ored' into SCSI_CFG1.
8096 if ((asc_dvc->cfg->termination & TERM_SE) == 0) {
8097 struct pci_dev *pdev = adv_dvc_to_pdev(asc_dvc);
8098 /* SE automatic termination control is enabled. */
8099 switch (scsi_cfg1 & C_DET_SE) {
8100 /* TERM_SE_HI: on, TERM_SE_LO: on */
8104 asc_dvc->cfg->termination |= TERM_SE;
8108 if (PCI_FUNC(pdev->devfn) == 0) {
8109 /* Function 0 - TERM_SE_HI: off, TERM_SE_LO: off */
8111 /* Function 1 - TERM_SE_HI: on, TERM_SE_LO: off */
8112 asc_dvc->cfg->termination |= TERM_SE_HI;
8119 * Clear any set TERM_SE bits.
8121 scsi_cfg1 &= ~TERM_SE;
8124 * Invert the TERM_SE bits and then set 'scsi_cfg1'.
8126 scsi_cfg1 |= (~asc_dvc->cfg->termination & TERM_SE);
8129 * Clear Big Endian and Terminator Polarity bits and set possibly
8130 * modified termination control bits in the Microcode SCSI_CFG1
8133 * Big Endian bit is not used even on big endian machines.
8135 scsi_cfg1 &= (~BIG_ENDIAN & ~DIS_TERM_DRV & ~TERM_POL);
8138 * Set SCSI_CFG1 Microcode Default Value
8140 * Set possibly modified termination control bits in the Microcode
8141 * SCSI_CFG1 Register Value.
8143 * The microcode will set the SCSI_CFG1 register using this value
8144 * after it is started below.
8146 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SCSI_CFG1, scsi_cfg1);
8149 * Set MEM_CFG Microcode Default Value
8151 * The microcode will set the MEM_CFG register using this value
8152 * after it is started below.
8154 * MEM_CFG may be accessed as a word or byte, but only bits 0-7
8157 * ASC-38C1600 has 32KB internal memory.
8159 * XXX - Since ASC38C1600 Rev.3 has a Local RAM failure issue, we come
8160 * out a special 16K Adv Library and Microcode version. After the issue
8161 * resolved, we should turn back to the 32K support. Both a_condor.h and
8162 * mcode.sas files also need to be updated.
8164 * AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_MEM_CFG,
8165 * BIOS_EN | RAM_SZ_32KB);
8167 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_MEM_CFG,
8168 BIOS_EN | RAM_SZ_16KB);
8171 * Set SEL_MASK Microcode Default Value
8173 * The microcode will set the SEL_MASK register using this value
8174 * after it is started below.
8176 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SEL_MASK,
8177 ADV_TID_TO_TIDMASK(asc_dvc->chip_scsi_id));
8179 AdvBuildCarrierFreelist(asc_dvc);
8182 * Set-up the Host->RISC Initiator Command Queue (ICQ).
8184 if ((asc_dvc->icq_sp = asc_dvc->carr_freelist) == NULL) {
8185 asc_dvc->err_code |= ASC_IERR_NO_CARRIER;
8188 asc_dvc->carr_freelist = (ADV_CARR_T *)
8189 ADV_U32_TO_VADDR(le32_to_cpu(asc_dvc->icq_sp->next_vpa));
8192 * The first command issued will be placed in the stopper carrier.
8194 asc_dvc->icq_sp->next_vpa = cpu_to_le32(ASC_CQ_STOPPER);
8197 * Set RISC ICQ physical address start value. Initialize the
8198 * COMMA register to the same value otherwise the RISC will
8199 * prematurely detect a command is available.
8201 AdvWriteDWordLramNoSwap(iop_base, ASC_MC_ICQ, asc_dvc->icq_sp->carr_pa);
8202 AdvWriteDWordRegister(iop_base, IOPDW_COMMA,
8203 le32_to_cpu(asc_dvc->icq_sp->carr_pa));
8206 * Set-up the RISC->Host Initiator Response Queue (IRQ).
8208 if ((asc_dvc->irq_sp = asc_dvc->carr_freelist) == NULL) {
8209 asc_dvc->err_code |= ASC_IERR_NO_CARRIER;
8212 asc_dvc->carr_freelist = (ADV_CARR_T *)
8213 ADV_U32_TO_VADDR(le32_to_cpu(asc_dvc->irq_sp->next_vpa));
8216 * The first command completed by the RISC will be placed in
8219 * Note: Set 'next_vpa' to ASC_CQ_STOPPER. When the request is
8220 * completed the RISC will set the ASC_RQ_STOPPER bit.
8222 asc_dvc->irq_sp->next_vpa = cpu_to_le32(ASC_CQ_STOPPER);
8225 * Set RISC IRQ physical address start value.
8227 AdvWriteDWordLramNoSwap(iop_base, ASC_MC_IRQ, asc_dvc->irq_sp->carr_pa);
8228 asc_dvc->carr_pending_cnt = 0;
8230 AdvWriteByteRegister(iop_base, IOPB_INTR_ENABLES,
8231 (ADV_INTR_ENABLE_HOST_INTR |
8232 ADV_INTR_ENABLE_GLOBAL_INTR));
8233 AdvReadWordLram(iop_base, ASC_MC_CODE_BEGIN_ADDR, word);
8234 AdvWriteWordRegister(iop_base, IOPW_PC, word);
8236 /* finally, finally, gentlemen, start your engine */
8237 AdvWriteWordRegister(iop_base, IOPW_RISC_CSR, ADV_RISC_CSR_RUN);
8240 * Reset the SCSI Bus if the EEPROM indicates that SCSI Bus
8241 * Resets should be performed. The RISC has to be running
8242 * to issue a SCSI Bus Reset.
8244 if (asc_dvc->bios_ctrl & BIOS_CTRL_RESET_SCSI_BUS) {
8246 * If the BIOS Signature is present in memory, restore the
8247 * per TID microcode operating variables.
8249 if (bios_mem[(ASC_MC_BIOS_SIGNATURE - ASC_MC_BIOSMEM) / 2] ==
8252 * Restore per TID negotiated values.
8254 AdvWriteWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able);
8255 AdvWriteWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
8256 AdvWriteWordLram(iop_base, ASC_MC_PPR_ABLE, ppr_able);
8257 AdvWriteWordLram(iop_base, ASC_MC_TAGQNG_ABLE,
8259 for (tid = 0; tid <= ASC_MAX_TID; tid++) {
8260 AdvWriteByteLram(iop_base,
8261 ASC_MC_NUMBER_OF_MAX_CMD + tid,
8265 if (AdvResetSB(asc_dvc) != ADV_TRUE) {
8266 warn_code = ASC_WARN_BUSRESET_ERROR;
8275 * Reset chip and SCSI Bus.
8278 * ADV_TRUE(1) - Chip re-initialization and SCSI Bus Reset successful.
8279 * ADV_FALSE(0) - Chip re-initialization and SCSI Bus Reset failure.
8281 static int AdvResetChipAndSB(ADV_DVC_VAR *asc_dvc)
8284 ushort wdtr_able, sdtr_able, tagqng_able;
8285 ushort ppr_able = 0;
8286 uchar tid, max_cmd[ADV_MAX_TID + 1];
8287 AdvPortAddr iop_base;
8290 iop_base = asc_dvc->iop_base;
8293 * Save current per TID negotiated values.
8295 AdvReadWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able);
8296 AdvReadWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
8297 if (asc_dvc->chip_type == ADV_CHIP_ASC38C1600) {
8298 AdvReadWordLram(iop_base, ASC_MC_PPR_ABLE, ppr_able);
8300 AdvReadWordLram(iop_base, ASC_MC_TAGQNG_ABLE, tagqng_able);
8301 for (tid = 0; tid <= ADV_MAX_TID; tid++) {
8302 AdvReadByteLram(iop_base, ASC_MC_NUMBER_OF_MAX_CMD + tid,
8307 * Force the AdvInitAsc3550/38C0800Driver() function to
8308 * perform a SCSI Bus Reset by clearing the BIOS signature word.
8309 * The initialization functions assumes a SCSI Bus Reset is not
8310 * needed if the BIOS signature word is present.
8312 AdvReadWordLram(iop_base, ASC_MC_BIOS_SIGNATURE, bios_sig);
8313 AdvWriteWordLram(iop_base, ASC_MC_BIOS_SIGNATURE, 0);
8316 * Stop chip and reset it.
8318 AdvWriteWordRegister(iop_base, IOPW_RISC_CSR, ADV_RISC_CSR_STOP);
8319 AdvWriteWordRegister(iop_base, IOPW_CTRL_REG, ADV_CTRL_REG_CMD_RESET);
8321 AdvWriteWordRegister(iop_base, IOPW_CTRL_REG,
8322 ADV_CTRL_REG_CMD_WR_IO_REG);
8325 * Reset Adv Library error code, if any, and try
8326 * re-initializing the chip.
8328 asc_dvc->err_code = 0;
8329 if (asc_dvc->chip_type == ADV_CHIP_ASC38C1600) {
8330 status = AdvInitAsc38C1600Driver(asc_dvc);
8331 } else if (asc_dvc->chip_type == ADV_CHIP_ASC38C0800) {
8332 status = AdvInitAsc38C0800Driver(asc_dvc);
8334 status = AdvInitAsc3550Driver(asc_dvc);
8337 /* Translate initialization return value to status value. */
8345 * Restore the BIOS signature word.
8347 AdvWriteWordLram(iop_base, ASC_MC_BIOS_SIGNATURE, bios_sig);
8350 * Restore per TID negotiated values.
8352 AdvWriteWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able);
8353 AdvWriteWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
8354 if (asc_dvc->chip_type == ADV_CHIP_ASC38C1600) {
8355 AdvWriteWordLram(iop_base, ASC_MC_PPR_ABLE, ppr_able);
8357 AdvWriteWordLram(iop_base, ASC_MC_TAGQNG_ABLE, tagqng_able);
8358 for (tid = 0; tid <= ADV_MAX_TID; tid++) {
8359 AdvWriteByteLram(iop_base, ASC_MC_NUMBER_OF_MAX_CMD + tid,
8367 * adv_async_callback() - Adv Library asynchronous event callback function.
8369 static void adv_async_callback(ADV_DVC_VAR *adv_dvc_varp, uchar code)
8372 case ADV_ASYNC_SCSI_BUS_RESET_DET:
8374 * The firmware detected a SCSI Bus reset.
8377 "adv_async_callback: ADV_ASYNC_SCSI_BUS_RESET_DET\n");
8380 case ADV_ASYNC_RDMA_FAILURE:
8382 * Handle RDMA failure by resetting the SCSI Bus and
8383 * possibly the chip if it is unresponsive. Log the error
8384 * with a unique code.
8386 ASC_DBG(0, "adv_async_callback: ADV_ASYNC_RDMA_FAILURE\n");
8387 AdvResetChipAndSB(adv_dvc_varp);
8390 case ADV_HOST_SCSI_BUS_RESET:
8392 * Host generated SCSI bus reset occurred.
8394 ASC_DBG(0, "adv_async_callback: ADV_HOST_SCSI_BUS_RESET\n");
8398 ASC_DBG1(0, "DvcAsyncCallBack: unknown code 0x%x\n", code);
8404 * adv_isr_callback() - Second Level Interrupt Handler called by AdvISR().
8406 * Callback function for the Wide SCSI Adv Library.
8408 static void adv_isr_callback(ADV_DVC_VAR *adv_dvc_varp, ADV_SCSI_REQ_Q *scsiqp)
8410 asc_board_t *boardp;
8412 adv_sgblk_t *sgblkp;
8413 struct scsi_cmnd *scp;
8414 struct Scsi_Host *shost;
8417 ASC_DBG2(1, "adv_isr_callback: adv_dvc_varp 0x%lx, scsiqp 0x%lx\n",
8418 (ulong)adv_dvc_varp, (ulong)scsiqp);
8419 ASC_DBG_PRT_ADV_SCSI_REQ_Q(2, scsiqp);
8422 * Get the adv_req_t structure for the command that has been
8423 * completed. The adv_req_t structure actually contains the
8424 * completed ADV_SCSI_REQ_Q structure.
8426 reqp = (adv_req_t *)ADV_U32_TO_VADDR(scsiqp->srb_ptr);
8427 ASC_DBG1(1, "adv_isr_callback: reqp 0x%lx\n", (ulong)reqp);
8429 ASC_PRINT("adv_isr_callback: reqp is NULL\n");
8434 * Get the struct scsi_cmnd structure and Scsi_Host structure for the
8435 * command that has been completed.
8437 * Note: The adv_req_t request structure and adv_sgblk_t structure,
8438 * if any, are dropped, because a board structure pointer can not be
8442 ASC_DBG1(1, "adv_isr_callback: scp 0x%lx\n", (ulong)scp);
8445 ("adv_isr_callback: scp is NULL; adv_req_t dropped.\n");
8448 ASC_DBG_PRT_CDB(2, scp->cmnd, scp->cmd_len);
8450 shost = scp->device->host;
8451 ASC_STATS(shost, callback);
8452 ASC_DBG1(1, "adv_isr_callback: shost 0x%lx\n", (ulong)shost);
8454 boardp = ASC_BOARDP(shost);
8455 BUG_ON(adv_dvc_varp != &boardp->dvc_var.adv_dvc_var);
8458 * 'done_status' contains the command's ending status.
8460 switch (scsiqp->done_status) {
8462 ASC_DBG(2, "adv_isr_callback: QD_NO_ERROR\n");
8466 * Check for an underrun condition.
8468 * If there was no error and an underrun condition, then
8469 * then return the number of underrun bytes.
8471 resid_cnt = le32_to_cpu(scsiqp->data_cnt);
8472 if (scp->request_bufflen != 0 && resid_cnt != 0 &&
8473 resid_cnt <= scp->request_bufflen) {
8475 "adv_isr_callback: underrun condition %lu bytes\n",
8477 scp->resid = resid_cnt;
8482 ASC_DBG(2, "adv_isr_callback: QD_WITH_ERROR\n");
8483 switch (scsiqp->host_status) {
8484 case QHSTA_NO_ERROR:
8485 if (scsiqp->scsi_status == SAM_STAT_CHECK_CONDITION) {
8487 "adv_isr_callback: SAM_STAT_CHECK_CONDITION\n");
8488 ASC_DBG_PRT_SENSE(2, scp->sense_buffer,
8489 sizeof(scp->sense_buffer));
8491 * Note: The 'status_byte()' macro used by
8492 * target drivers defined in scsi.h shifts the
8493 * status byte returned by host drivers right
8494 * by 1 bit. This is why target drivers also
8495 * use right shifted status byte definitions.
8496 * For instance target drivers use
8497 * CHECK_CONDITION, defined to 0x1, instead of
8498 * the SCSI defined check condition value of
8499 * 0x2. Host drivers are supposed to return
8500 * the status byte as it is defined by SCSI.
8502 scp->result = DRIVER_BYTE(DRIVER_SENSE) |
8503 STATUS_BYTE(scsiqp->scsi_status);
8505 scp->result = STATUS_BYTE(scsiqp->scsi_status);
8510 /* Some other QHSTA error occurred. */
8511 ASC_DBG1(1, "adv_isr_callback: host_status 0x%x\n",
8512 scsiqp->host_status);
8513 scp->result = HOST_BYTE(DID_BAD_TARGET);
8518 case QD_ABORTED_BY_HOST:
8519 ASC_DBG(1, "adv_isr_callback: QD_ABORTED_BY_HOST\n");
8521 HOST_BYTE(DID_ABORT) | STATUS_BYTE(scsiqp->scsi_status);
8525 ASC_DBG1(1, "adv_isr_callback: done_status 0x%x\n",
8526 scsiqp->done_status);
8528 HOST_BYTE(DID_ERROR) | STATUS_BYTE(scsiqp->scsi_status);
8533 * If the 'init_tidmask' bit isn't already set for the target and the
8534 * current request finished normally, then set the bit for the target
8535 * to indicate that a device is present.
8537 if ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(scp->device->id)) == 0 &&
8538 scsiqp->done_status == QD_NO_ERROR &&
8539 scsiqp->host_status == QHSTA_NO_ERROR) {
8540 boardp->init_tidmask |= ADV_TID_TO_TIDMASK(scp->device->id);
8546 * Free all 'adv_sgblk_t' structures allocated for the request.
8548 while ((sgblkp = reqp->sgblkp) != NULL) {
8549 /* Remove 'sgblkp' from the request list. */
8550 reqp->sgblkp = sgblkp->next_sgblkp;
8552 /* Add 'sgblkp' to the board free list. */
8553 sgblkp->next_sgblkp = boardp->adv_sgblkp;
8554 boardp->adv_sgblkp = sgblkp;
8558 * Free the adv_req_t structure used with the command by adding
8559 * it back to the board free list.
8561 reqp->next_reqp = boardp->adv_reqp;
8562 boardp->adv_reqp = reqp;
8564 ASC_DBG(1, "adv_isr_callback: done\n");
8570 * Adv Library Interrupt Service Routine
8572 * This function is called by a driver's interrupt service routine.
8573 * The function disables and re-enables interrupts.
8575 * When a microcode idle command is completed, the ADV_DVC_VAR
8576 * 'idle_cmd_done' field is set to ADV_TRUE.
8578 * Note: AdvISR() can be called when interrupts are disabled or even
8579 * when there is no hardware interrupt condition present. It will
8580 * always check for completed idle commands and microcode requests.
8581 * This is an important feature that shouldn't be changed because it
8582 * allows commands to be completed from polling mode loops.
8585 * ADV_TRUE(1) - interrupt was pending
8586 * ADV_FALSE(0) - no interrupt was pending
8588 static int AdvISR(ADV_DVC_VAR *asc_dvc)
8590 AdvPortAddr iop_base;
8593 ADV_CARR_T *free_carrp;
8594 ADV_VADDR irq_next_vpa;
8595 ADV_SCSI_REQ_Q *scsiq;
8597 iop_base = asc_dvc->iop_base;
8599 /* Reading the register clears the interrupt. */
8600 int_stat = AdvReadByteRegister(iop_base, IOPB_INTR_STATUS_REG);
8602 if ((int_stat & (ADV_INTR_STATUS_INTRA | ADV_INTR_STATUS_INTRB |
8603 ADV_INTR_STATUS_INTRC)) == 0) {
8608 * Notify the driver of an asynchronous microcode condition by
8609 * calling the adv_async_callback function. The function
8610 * is passed the microcode ASC_MC_INTRB_CODE byte value.
8612 if (int_stat & ADV_INTR_STATUS_INTRB) {
8615 AdvReadByteLram(iop_base, ASC_MC_INTRB_CODE, intrb_code);
8617 if (asc_dvc->chip_type == ADV_CHIP_ASC3550 ||
8618 asc_dvc->chip_type == ADV_CHIP_ASC38C0800) {
8619 if (intrb_code == ADV_ASYNC_CARRIER_READY_FAILURE &&
8620 asc_dvc->carr_pending_cnt != 0) {
8621 AdvWriteByteRegister(iop_base, IOPB_TICKLE,
8623 if (asc_dvc->chip_type == ADV_CHIP_ASC3550) {
8624 AdvWriteByteRegister(iop_base,
8631 adv_async_callback(asc_dvc, intrb_code);
8635 * Check if the IRQ stopper carrier contains a completed request.
8637 while (((irq_next_vpa =
8638 le32_to_cpu(asc_dvc->irq_sp->next_vpa)) & ASC_RQ_DONE) != 0) {
8640 * Get a pointer to the newly completed ADV_SCSI_REQ_Q structure.
8641 * The RISC will have set 'areq_vpa' to a virtual address.
8643 * The firmware will have copied the ASC_SCSI_REQ_Q.scsiq_ptr
8644 * field to the carrier ADV_CARR_T.areq_vpa field. The conversion
8645 * below complements the conversion of ASC_SCSI_REQ_Q.scsiq_ptr'
8646 * in AdvExeScsiQueue().
8648 scsiq = (ADV_SCSI_REQ_Q *)
8649 ADV_U32_TO_VADDR(le32_to_cpu(asc_dvc->irq_sp->areq_vpa));
8652 * Request finished with good status and the queue was not
8653 * DMAed to host memory by the firmware. Set all status fields
8654 * to indicate good status.
8656 if ((irq_next_vpa & ASC_RQ_GOOD) != 0) {
8657 scsiq->done_status = QD_NO_ERROR;
8658 scsiq->host_status = scsiq->scsi_status = 0;
8659 scsiq->data_cnt = 0L;
8663 * Advance the stopper pointer to the next carrier
8664 * ignoring the lower four bits. Free the previous
8667 free_carrp = asc_dvc->irq_sp;
8668 asc_dvc->irq_sp = (ADV_CARR_T *)
8669 ADV_U32_TO_VADDR(ASC_GET_CARRP(irq_next_vpa));
8671 free_carrp->next_vpa =
8672 cpu_to_le32(ADV_VADDR_TO_U32(asc_dvc->carr_freelist));
8673 asc_dvc->carr_freelist = free_carrp;
8674 asc_dvc->carr_pending_cnt--;
8676 target_bit = ADV_TID_TO_TIDMASK(scsiq->target_id);
8679 * Clear request microcode control flag.
8684 * Notify the driver of the completed request by passing
8685 * the ADV_SCSI_REQ_Q pointer to its callback function.
8687 scsiq->a_flag |= ADV_SCSIQ_DONE;
8688 adv_isr_callback(asc_dvc, scsiq);
8690 * Note: After the driver callback function is called, 'scsiq'
8691 * can no longer be referenced.
8693 * Fall through and continue processing other completed
8700 static int AscSetLibErrorCode(ASC_DVC_VAR *asc_dvc, ushort err_code)
8702 if (asc_dvc->err_code == 0) {
8703 asc_dvc->err_code = err_code;
8704 AscWriteLramWord(asc_dvc->iop_base, ASCV_ASCDVC_ERR_CODE_W,
8710 static void AscAckInterrupt(PortAddr iop_base)
8718 risc_flag = AscReadLramByte(iop_base, ASCV_RISC_FLAG_B);
8719 if (loop++ > 0x7FFF) {
8722 } while ((risc_flag & ASC_RISC_FLAG_GEN_INT) != 0);
8724 AscReadLramByte(iop_base,
8725 ASCV_HOST_FLAG_B) & (~ASC_HOST_FLAG_ACK_INT);
8726 AscWriteLramByte(iop_base, ASCV_HOST_FLAG_B,
8727 (uchar)(host_flag | ASC_HOST_FLAG_ACK_INT));
8728 AscSetChipStatus(iop_base, CIW_INT_ACK);
8730 while (AscGetChipStatus(iop_base) & CSW_INT_PENDING) {
8731 AscSetChipStatus(iop_base, CIW_INT_ACK);
8736 AscWriteLramByte(iop_base, ASCV_HOST_FLAG_B, host_flag);
8740 static uchar AscGetSynPeriodIndex(ASC_DVC_VAR *asc_dvc, uchar syn_time)
8742 uchar *period_table;
8747 period_table = asc_dvc->sdtr_period_tbl;
8748 max_index = (int)asc_dvc->max_sdtr_index;
8749 min_index = (int)asc_dvc->host_init_sdtr_index;
8750 if ((syn_time <= period_table[max_index])) {
8751 for (i = min_index; i < (max_index - 1); i++) {
8752 if (syn_time <= period_table[i]) {
8756 return (uchar)max_index;
8758 return (uchar)(max_index + 1);
8763 AscMsgOutSDTR(ASC_DVC_VAR *asc_dvc, uchar sdtr_period, uchar sdtr_offset)
8766 uchar sdtr_period_index;
8769 iop_base = asc_dvc->iop_base;
8770 sdtr_buf.msg_type = EXTENDED_MESSAGE;
8771 sdtr_buf.msg_len = MS_SDTR_LEN;
8772 sdtr_buf.msg_req = EXTENDED_SDTR;
8773 sdtr_buf.xfer_period = sdtr_period;
8774 sdtr_offset &= ASC_SYN_MAX_OFFSET;
8775 sdtr_buf.req_ack_offset = sdtr_offset;
8776 sdtr_period_index = AscGetSynPeriodIndex(asc_dvc, sdtr_period);
8777 if (sdtr_period_index <= asc_dvc->max_sdtr_index) {
8778 AscMemWordCopyPtrToLram(iop_base, ASCV_MSGOUT_BEG,
8780 sizeof(EXT_MSG) >> 1);
8781 return ((sdtr_period_index << 4) | sdtr_offset);
8783 sdtr_buf.req_ack_offset = 0;
8784 AscMemWordCopyPtrToLram(iop_base, ASCV_MSGOUT_BEG,
8786 sizeof(EXT_MSG) >> 1);
8792 AscCalSDTRData(ASC_DVC_VAR *asc_dvc, uchar sdtr_period, uchar syn_offset)
8795 uchar sdtr_period_ix;
8797 sdtr_period_ix = AscGetSynPeriodIndex(asc_dvc, sdtr_period);
8798 if (sdtr_period_ix > asc_dvc->max_sdtr_index) {
8801 byte = (sdtr_period_ix << 4) | (syn_offset & ASC_SYN_MAX_OFFSET);
8805 static int AscSetChipSynRegAtID(PortAddr iop_base, uchar id, uchar sdtr_data)
8807 ASC_SCSI_BIT_ID_TYPE org_id;
8811 AscSetBank(iop_base, 1);
8812 org_id = AscReadChipDvcID(iop_base);
8813 for (i = 0; i <= ASC_MAX_TID; i++) {
8814 if (org_id == (0x01 << i))
8817 org_id = (ASC_SCSI_BIT_ID_TYPE) i;
8818 AscWriteChipDvcID(iop_base, id);
8819 if (AscReadChipDvcID(iop_base) == (0x01 << id)) {
8820 AscSetBank(iop_base, 0);
8821 AscSetChipSyn(iop_base, sdtr_data);
8822 if (AscGetChipSyn(iop_base) != sdtr_data) {
8828 AscSetBank(iop_base, 1);
8829 AscWriteChipDvcID(iop_base, org_id);
8830 AscSetBank(iop_base, 0);
8834 static void AscSetChipSDTR(PortAddr iop_base, uchar sdtr_data, uchar tid_no)
8836 AscSetChipSynRegAtID(iop_base, tid_no, sdtr_data);
8837 AscPutMCodeSDTRDoneAtID(iop_base, tid_no, sdtr_data);
8840 static int AscIsrChipHalted(ASC_DVC_VAR *asc_dvc)
8846 ushort int_halt_code;
8847 ASC_SCSI_BIT_ID_TYPE scsi_busy;
8848 ASC_SCSI_BIT_ID_TYPE target_id;
8855 uchar q_cntl, tid_no;
8859 asc_board_t *boardp;
8861 BUG_ON(!asc_dvc->drv_ptr);
8862 boardp = asc_dvc->drv_ptr;
8864 iop_base = asc_dvc->iop_base;
8865 int_halt_code = AscReadLramWord(iop_base, ASCV_HALTCODE_W);
8867 halt_qp = AscReadLramByte(iop_base, ASCV_CURCDB_B);
8868 halt_q_addr = ASC_QNO_TO_QADDR(halt_qp);
8869 target_ix = AscReadLramByte(iop_base,
8870 (ushort)(halt_q_addr +
8871 (ushort)ASC_SCSIQ_B_TARGET_IX));
8872 q_cntl = AscReadLramByte(iop_base,
8873 (ushort)(halt_q_addr + (ushort)ASC_SCSIQ_B_CNTL));
8874 tid_no = ASC_TIX_TO_TID(target_ix);
8875 target_id = (uchar)ASC_TID_TO_TARGET_ID(tid_no);
8876 if (asc_dvc->pci_fix_asyn_xfer & target_id) {
8877 asyn_sdtr = ASYN_SDTR_DATA_FIX_PCI_REV_AB;
8881 if (int_halt_code == ASC_HALT_DISABLE_ASYN_USE_SYN_FIX) {
8882 if (asc_dvc->pci_fix_asyn_xfer & target_id) {
8883 AscSetChipSDTR(iop_base, 0, tid_no);
8884 boardp->sdtr_data[tid_no] = 0;
8886 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
8888 } else if (int_halt_code == ASC_HALT_ENABLE_ASYN_USE_SYN_FIX) {
8889 if (asc_dvc->pci_fix_asyn_xfer & target_id) {
8890 AscSetChipSDTR(iop_base, asyn_sdtr, tid_no);
8891 boardp->sdtr_data[tid_no] = asyn_sdtr;
8893 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
8895 } else if (int_halt_code == ASC_HALT_EXTMSG_IN) {
8896 AscMemWordCopyPtrFromLram(iop_base,
8899 sizeof(EXT_MSG) >> 1);
8901 if (ext_msg.msg_type == EXTENDED_MESSAGE &&
8902 ext_msg.msg_req == EXTENDED_SDTR &&
8903 ext_msg.msg_len == MS_SDTR_LEN) {
8905 if ((ext_msg.req_ack_offset > ASC_SYN_MAX_OFFSET)) {
8907 sdtr_accept = FALSE;
8908 ext_msg.req_ack_offset = ASC_SYN_MAX_OFFSET;
8910 if ((ext_msg.xfer_period <
8911 asc_dvc->sdtr_period_tbl[asc_dvc->
8912 host_init_sdtr_index])
8913 || (ext_msg.xfer_period >
8914 asc_dvc->sdtr_period_tbl[asc_dvc->
8916 sdtr_accept = FALSE;
8917 ext_msg.xfer_period =
8918 asc_dvc->sdtr_period_tbl[asc_dvc->
8919 host_init_sdtr_index];
8923 AscCalSDTRData(asc_dvc, ext_msg.xfer_period,
8924 ext_msg.req_ack_offset);
8925 if ((sdtr_data == 0xFF)) {
8927 q_cntl |= QC_MSG_OUT;
8928 asc_dvc->init_sdtr &= ~target_id;
8929 asc_dvc->sdtr_done &= ~target_id;
8930 AscSetChipSDTR(iop_base, asyn_sdtr,
8932 boardp->sdtr_data[tid_no] = asyn_sdtr;
8935 if (ext_msg.req_ack_offset == 0) {
8937 q_cntl &= ~QC_MSG_OUT;
8938 asc_dvc->init_sdtr &= ~target_id;
8939 asc_dvc->sdtr_done &= ~target_id;
8940 AscSetChipSDTR(iop_base, asyn_sdtr, tid_no);
8942 if (sdtr_accept && (q_cntl & QC_MSG_OUT)) {
8944 q_cntl &= ~QC_MSG_OUT;
8945 asc_dvc->sdtr_done |= target_id;
8946 asc_dvc->init_sdtr |= target_id;
8947 asc_dvc->pci_fix_asyn_xfer &=
8950 AscCalSDTRData(asc_dvc,
8951 ext_msg.xfer_period,
8954 AscSetChipSDTR(iop_base, sdtr_data,
8956 boardp->sdtr_data[tid_no] = sdtr_data;
8959 q_cntl |= QC_MSG_OUT;
8960 AscMsgOutSDTR(asc_dvc,
8961 ext_msg.xfer_period,
8962 ext_msg.req_ack_offset);
8963 asc_dvc->pci_fix_asyn_xfer &=
8966 AscCalSDTRData(asc_dvc,
8967 ext_msg.xfer_period,
8970 AscSetChipSDTR(iop_base, sdtr_data,
8972 boardp->sdtr_data[tid_no] = sdtr_data;
8973 asc_dvc->sdtr_done |= target_id;
8974 asc_dvc->init_sdtr |= target_id;
8978 AscWriteLramByte(iop_base,
8979 (ushort)(halt_q_addr +
8980 (ushort)ASC_SCSIQ_B_CNTL),
8982 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
8984 } else if (ext_msg.msg_type == EXTENDED_MESSAGE &&
8985 ext_msg.msg_req == EXTENDED_WDTR &&
8986 ext_msg.msg_len == MS_WDTR_LEN) {
8988 ext_msg.wdtr_width = 0;
8989 AscMemWordCopyPtrToLram(iop_base,
8992 sizeof(EXT_MSG) >> 1);
8993 q_cntl |= QC_MSG_OUT;
8994 AscWriteLramByte(iop_base,
8995 (ushort)(halt_q_addr +
8996 (ushort)ASC_SCSIQ_B_CNTL),
8998 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
9002 ext_msg.msg_type = MESSAGE_REJECT;
9003 AscMemWordCopyPtrToLram(iop_base,
9006 sizeof(EXT_MSG) >> 1);
9007 q_cntl |= QC_MSG_OUT;
9008 AscWriteLramByte(iop_base,
9009 (ushort)(halt_q_addr +
9010 (ushort)ASC_SCSIQ_B_CNTL),
9012 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
9015 } else if (int_halt_code == ASC_HALT_CHK_CONDITION) {
9017 q_cntl |= QC_REQ_SENSE;
9019 if ((asc_dvc->init_sdtr & target_id) != 0) {
9021 asc_dvc->sdtr_done &= ~target_id;
9023 sdtr_data = AscGetMCodeInitSDTRAtID(iop_base, tid_no);
9024 q_cntl |= QC_MSG_OUT;
9025 AscMsgOutSDTR(asc_dvc,
9027 sdtr_period_tbl[(sdtr_data >> 4) &
9031 (uchar)(sdtr_data & (uchar)
9032 ASC_SYN_MAX_OFFSET));
9035 AscWriteLramByte(iop_base,
9036 (ushort)(halt_q_addr +
9037 (ushort)ASC_SCSIQ_B_CNTL), q_cntl);
9039 tag_code = AscReadLramByte(iop_base,
9040 (ushort)(halt_q_addr + (ushort)
9041 ASC_SCSIQ_B_TAG_CODE));
9043 if ((asc_dvc->pci_fix_asyn_xfer & target_id)
9044 && !(asc_dvc->pci_fix_asyn_xfer_always & target_id)
9047 tag_code |= (ASC_TAG_FLAG_DISABLE_DISCONNECT
9048 | ASC_TAG_FLAG_DISABLE_ASYN_USE_SYN_FIX);
9051 AscWriteLramByte(iop_base,
9052 (ushort)(halt_q_addr +
9053 (ushort)ASC_SCSIQ_B_TAG_CODE),
9056 q_status = AscReadLramByte(iop_base,
9057 (ushort)(halt_q_addr + (ushort)
9058 ASC_SCSIQ_B_STATUS));
9059 q_status |= (QS_READY | QS_BUSY);
9060 AscWriteLramByte(iop_base,
9061 (ushort)(halt_q_addr +
9062 (ushort)ASC_SCSIQ_B_STATUS),
9065 scsi_busy = AscReadLramByte(iop_base, (ushort)ASCV_SCSIBUSY_B);
9066 scsi_busy &= ~target_id;
9067 AscWriteLramByte(iop_base, (ushort)ASCV_SCSIBUSY_B, scsi_busy);
9069 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
9071 } else if (int_halt_code == ASC_HALT_SDTR_REJECTED) {
9073 AscMemWordCopyPtrFromLram(iop_base,
9076 sizeof(EXT_MSG) >> 1);
9078 if ((out_msg.msg_type == EXTENDED_MESSAGE) &&
9079 (out_msg.msg_len == MS_SDTR_LEN) &&
9080 (out_msg.msg_req == EXTENDED_SDTR)) {
9082 asc_dvc->init_sdtr &= ~target_id;
9083 asc_dvc->sdtr_done &= ~target_id;
9084 AscSetChipSDTR(iop_base, asyn_sdtr, tid_no);
9085 boardp->sdtr_data[tid_no] = asyn_sdtr;
9087 q_cntl &= ~QC_MSG_OUT;
9088 AscWriteLramByte(iop_base,
9089 (ushort)(halt_q_addr +
9090 (ushort)ASC_SCSIQ_B_CNTL), q_cntl);
9091 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
9093 } else if (int_halt_code == ASC_HALT_SS_QUEUE_FULL) {
9095 scsi_status = AscReadLramByte(iop_base,
9096 (ushort)((ushort)halt_q_addr +
9098 ASC_SCSIQ_SCSI_STATUS));
9100 AscReadLramByte(iop_base,
9101 (ushort)((ushort)ASC_QADR_BEG +
9102 (ushort)target_ix));
9103 if ((cur_dvc_qng > 0) && (asc_dvc->cur_dvc_qng[tid_no] > 0)) {
9105 scsi_busy = AscReadLramByte(iop_base,
9106 (ushort)ASCV_SCSIBUSY_B);
9107 scsi_busy |= target_id;
9108 AscWriteLramByte(iop_base,
9109 (ushort)ASCV_SCSIBUSY_B, scsi_busy);
9110 asc_dvc->queue_full_or_busy |= target_id;
9112 if (scsi_status == SAM_STAT_TASK_SET_FULL) {
9113 if (cur_dvc_qng > ASC_MIN_TAGGED_CMD) {
9115 asc_dvc->max_dvc_qng[tid_no] =
9118 AscWriteLramByte(iop_base,
9120 ASCV_MAX_DVC_QNG_BEG
9126 * Set the device queue depth to the
9127 * number of active requests when the
9128 * QUEUE FULL condition was encountered.
9130 boardp->queue_full |= target_id;
9131 boardp->queue_full_cnt[tid_no] =
9136 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
9139 #if CC_VERY_LONG_SG_LIST
9140 else if (int_halt_code == ASC_HALT_HOST_COPY_SG_LIST_TO_RISC) {
9144 uchar first_sg_wk_q_no;
9145 ASC_SCSI_Q *scsiq; /* Ptr to driver request. */
9146 ASC_SG_HEAD *sg_head; /* Ptr to driver SG request. */
9147 ASC_SG_LIST_Q scsi_sg_q; /* Structure written to queue. */
9148 ushort sg_list_dwords;
9149 ushort sg_entry_cnt;
9153 q_no = AscReadLramByte(iop_base, (ushort)ASCV_REQ_SG_LIST_QP);
9154 if (q_no == ASC_QLINK_END)
9157 q_addr = ASC_QNO_TO_QADDR(q_no);
9160 * Convert the request's SRB pointer to a host ASC_SCSI_REQ
9161 * structure pointer using a macro provided by the driver.
9162 * The ASC_SCSI_REQ pointer provides a pointer to the
9163 * host ASC_SG_HEAD structure.
9165 /* Read request's SRB pointer. */
9166 scsiq = (ASC_SCSI_Q *)
9167 ASC_SRB2SCSIQ(ASC_U32_TO_VADDR(AscReadLramDWord(iop_base,
9170 ASC_SCSIQ_D_SRBPTR))));
9173 * Get request's first and working SG queue.
9175 sg_wk_q_no = AscReadLramByte(iop_base,
9177 ASC_SCSIQ_B_SG_WK_QP));
9179 first_sg_wk_q_no = AscReadLramByte(iop_base,
9181 ASC_SCSIQ_B_FIRST_SG_WK_QP));
9184 * Reset request's working SG queue back to the
9187 AscWriteLramByte(iop_base,
9189 (ushort)ASC_SCSIQ_B_SG_WK_QP),
9192 sg_head = scsiq->sg_head;
9195 * Set sg_entry_cnt to the number of SG elements
9196 * that will be completed on this interrupt.
9198 * Note: The allocated SG queues contain ASC_MAX_SG_LIST - 1
9199 * SG elements. The data_cnt and data_addr fields which
9200 * add 1 to the SG element capacity are not used when
9201 * restarting SG handling after a halt.
9203 if (scsiq->remain_sg_entry_cnt > (ASC_MAX_SG_LIST - 1)) {
9204 sg_entry_cnt = ASC_MAX_SG_LIST - 1;
9207 * Keep track of remaining number of SG elements that
9208 * will need to be handled on the next interrupt.
9210 scsiq->remain_sg_entry_cnt -= (ASC_MAX_SG_LIST - 1);
9212 sg_entry_cnt = scsiq->remain_sg_entry_cnt;
9213 scsiq->remain_sg_entry_cnt = 0;
9217 * Copy SG elements into the list of allocated SG queues.
9219 * Last index completed is saved in scsiq->next_sg_index.
9221 next_qp = first_sg_wk_q_no;
9222 q_addr = ASC_QNO_TO_QADDR(next_qp);
9223 scsi_sg_q.sg_head_qp = q_no;
9224 scsi_sg_q.cntl = QCSG_SG_XFER_LIST;
9225 for (i = 0; i < sg_head->queue_cnt; i++) {
9226 scsi_sg_q.seq_no = i + 1;
9227 if (sg_entry_cnt > ASC_SG_LIST_PER_Q) {
9228 sg_list_dwords = (uchar)(ASC_SG_LIST_PER_Q * 2);
9229 sg_entry_cnt -= ASC_SG_LIST_PER_Q;
9231 * After very first SG queue RISC FW uses next
9232 * SG queue first element then checks sg_list_cnt
9233 * against zero and then decrements, so set
9234 * sg_list_cnt 1 less than number of SG elements
9237 scsi_sg_q.sg_list_cnt = ASC_SG_LIST_PER_Q - 1;
9238 scsi_sg_q.sg_cur_list_cnt =
9239 ASC_SG_LIST_PER_Q - 1;
9242 * This is the last SG queue in the list of
9243 * allocated SG queues. If there are more
9244 * SG elements than will fit in the allocated
9245 * queues, then set the QCSG_SG_XFER_MORE flag.
9247 if (scsiq->remain_sg_entry_cnt != 0) {
9248 scsi_sg_q.cntl |= QCSG_SG_XFER_MORE;
9250 scsi_sg_q.cntl |= QCSG_SG_XFER_END;
9252 /* equals sg_entry_cnt * 2 */
9253 sg_list_dwords = sg_entry_cnt << 1;
9254 scsi_sg_q.sg_list_cnt = sg_entry_cnt - 1;
9255 scsi_sg_q.sg_cur_list_cnt = sg_entry_cnt - 1;
9259 scsi_sg_q.q_no = next_qp;
9260 AscMemWordCopyPtrToLram(iop_base,
9261 q_addr + ASC_SCSIQ_SGHD_CPY_BEG,
9262 (uchar *)&scsi_sg_q,
9263 sizeof(ASC_SG_LIST_Q) >> 1);
9265 AscMemDWordCopyPtrToLram(iop_base,
9266 q_addr + ASC_SGQ_LIST_BEG,
9268 sg_list[scsiq->next_sg_index],
9271 scsiq->next_sg_index += ASC_SG_LIST_PER_Q;
9274 * If the just completed SG queue contained the
9275 * last SG element, then no more SG queues need
9278 if (scsi_sg_q.cntl & QCSG_SG_XFER_END) {
9282 next_qp = AscReadLramByte(iop_base,
9285 q_addr = ASC_QNO_TO_QADDR(next_qp);
9289 * Clear the halt condition so the RISC will be restarted
9292 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
9295 #endif /* CC_VERY_LONG_SG_LIST */
9301 * DvcGetQinfo(PortAddr iop_base, ushort s_addr, uchar *inbuf, int words)
9303 * Calling/Exit State:
9307 * Input an ASC_QDONE_INFO structure from the chip
9310 DvcGetQinfo(PortAddr iop_base, ushort s_addr, uchar *inbuf, int words)
9315 AscSetChipLramAddr(iop_base, s_addr);
9316 for (i = 0; i < 2 * words; i += 2) {
9320 word = inpw(iop_base + IOP_RAM_DATA);
9321 inbuf[i] = word & 0xff;
9322 inbuf[i + 1] = (word >> 8) & 0xff;
9324 ASC_DBG_PRT_HEX(2, "DvcGetQinfo", inbuf, 2 * words);
9328 _AscCopyLramScsiDoneQ(PortAddr iop_base,
9330 ASC_QDONE_INFO *scsiq, ASC_DCNT max_dma_count)
9335 DvcGetQinfo(iop_base,
9336 q_addr + ASC_SCSIQ_DONE_INFO_BEG,
9338 (sizeof(ASC_SCSIQ_2) + sizeof(ASC_SCSIQ_3)) / 2);
9340 _val = AscReadLramWord(iop_base,
9341 (ushort)(q_addr + (ushort)ASC_SCSIQ_B_STATUS));
9342 scsiq->q_status = (uchar)_val;
9343 scsiq->q_no = (uchar)(_val >> 8);
9344 _val = AscReadLramWord(iop_base,
9345 (ushort)(q_addr + (ushort)ASC_SCSIQ_B_CNTL));
9346 scsiq->cntl = (uchar)_val;
9347 sg_queue_cnt = (uchar)(_val >> 8);
9348 _val = AscReadLramWord(iop_base,
9350 (ushort)ASC_SCSIQ_B_SENSE_LEN));
9351 scsiq->sense_len = (uchar)_val;
9352 scsiq->extra_bytes = (uchar)(_val >> 8);
9355 * Read high word of remain bytes from alternate location.
9357 scsiq->remain_bytes = (((ADV_DCNT)AscReadLramWord(iop_base,
9360 ASC_SCSIQ_W_ALT_DC1)))
9363 * Read low word of remain bytes from original location.
9365 scsiq->remain_bytes += AscReadLramWord(iop_base,
9366 (ushort)(q_addr + (ushort)
9367 ASC_SCSIQ_DW_REMAIN_XFER_CNT));
9369 scsiq->remain_bytes &= max_dma_count;
9370 return sg_queue_cnt;
9374 * asc_isr_callback() - Second Level Interrupt Handler called by AscISR().
9376 * Interrupt callback function for the Narrow SCSI Asc Library.
9378 static void asc_isr_callback(ASC_DVC_VAR *asc_dvc_varp, ASC_QDONE_INFO *qdonep)
9380 asc_board_t *boardp;
9381 struct scsi_cmnd *scp;
9382 struct Scsi_Host *shost;
9384 ASC_DBG2(1, "asc_isr_callback: asc_dvc_varp 0x%lx, qdonep 0x%lx\n",
9385 (ulong)asc_dvc_varp, (ulong)qdonep);
9386 ASC_DBG_PRT_ASC_QDONE_INFO(2, qdonep);
9389 * Get the struct scsi_cmnd structure and Scsi_Host structure for the
9390 * command that has been completed.
9392 scp = (struct scsi_cmnd *)ASC_U32_TO_VADDR(qdonep->d2.srb_ptr);
9393 ASC_DBG1(1, "asc_isr_callback: scp 0x%lx\n", (ulong)scp);
9396 ASC_PRINT("asc_isr_callback: scp is NULL\n");
9399 ASC_DBG_PRT_CDB(2, scp->cmnd, scp->cmd_len);
9401 shost = scp->device->host;
9402 ASC_STATS(shost, callback);
9403 ASC_DBG1(1, "asc_isr_callback: shost 0x%lx\n", (ulong)shost);
9405 boardp = ASC_BOARDP(shost);
9406 BUG_ON(asc_dvc_varp != &boardp->dvc_var.asc_dvc_var);
9409 * 'qdonep' contains the command's ending status.
9411 switch (qdonep->d3.done_stat) {
9413 ASC_DBG(2, "asc_isr_callback: QD_NO_ERROR\n");
9417 * Check for an underrun condition.
9419 * If there was no error and an underrun condition, then
9420 * return the number of underrun bytes.
9422 if (scp->request_bufflen != 0 && qdonep->remain_bytes != 0 &&
9423 qdonep->remain_bytes <= scp->request_bufflen) {
9425 "asc_isr_callback: underrun condition %u bytes\n",
9426 (unsigned)qdonep->remain_bytes);
9427 scp->resid = qdonep->remain_bytes;
9432 ASC_DBG(2, "asc_isr_callback: QD_WITH_ERROR\n");
9433 switch (qdonep->d3.host_stat) {
9434 case QHSTA_NO_ERROR:
9435 if (qdonep->d3.scsi_stat == SAM_STAT_CHECK_CONDITION) {
9437 "asc_isr_callback: SAM_STAT_CHECK_CONDITION\n");
9438 ASC_DBG_PRT_SENSE(2, scp->sense_buffer,
9439 sizeof(scp->sense_buffer));
9441 * Note: The 'status_byte()' macro used by
9442 * target drivers defined in scsi.h shifts the
9443 * status byte returned by host drivers right
9444 * by 1 bit. This is why target drivers also
9445 * use right shifted status byte definitions.
9446 * For instance target drivers use
9447 * CHECK_CONDITION, defined to 0x1, instead of
9448 * the SCSI defined check condition value of
9449 * 0x2. Host drivers are supposed to return
9450 * the status byte as it is defined by SCSI.
9452 scp->result = DRIVER_BYTE(DRIVER_SENSE) |
9453 STATUS_BYTE(qdonep->d3.scsi_stat);
9455 scp->result = STATUS_BYTE(qdonep->d3.scsi_stat);
9460 /* QHSTA error occurred */
9461 ASC_DBG1(1, "asc_isr_callback: host_stat 0x%x\n",
9462 qdonep->d3.host_stat);
9463 scp->result = HOST_BYTE(DID_BAD_TARGET);
9468 case QD_ABORTED_BY_HOST:
9469 ASC_DBG(1, "asc_isr_callback: QD_ABORTED_BY_HOST\n");
9471 HOST_BYTE(DID_ABORT) | MSG_BYTE(qdonep->d3.
9473 STATUS_BYTE(qdonep->d3.scsi_stat);
9477 ASC_DBG1(1, "asc_isr_callback: done_stat 0x%x\n",
9478 qdonep->d3.done_stat);
9480 HOST_BYTE(DID_ERROR) | MSG_BYTE(qdonep->d3.
9482 STATUS_BYTE(qdonep->d3.scsi_stat);
9487 * If the 'init_tidmask' bit isn't already set for the target and the
9488 * current request finished normally, then set the bit for the target
9489 * to indicate that a device is present.
9491 if ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(scp->device->id)) == 0 &&
9492 qdonep->d3.done_stat == QD_NO_ERROR &&
9493 qdonep->d3.host_stat == QHSTA_NO_ERROR) {
9494 boardp->init_tidmask |= ADV_TID_TO_TIDMASK(scp->device->id);
9502 static int AscIsrQDone(ASC_DVC_VAR *asc_dvc)
9511 ASC_SCSI_BIT_ID_TYPE scsi_busy;
9512 ASC_SCSI_BIT_ID_TYPE target_id;
9516 uchar cur_target_qng;
9517 ASC_QDONE_INFO scsiq_buf;
9518 ASC_QDONE_INFO *scsiq;
9521 iop_base = asc_dvc->iop_base;
9523 scsiq = (ASC_QDONE_INFO *)&scsiq_buf;
9524 done_q_tail = (uchar)AscGetVarDoneQTail(iop_base);
9525 q_addr = ASC_QNO_TO_QADDR(done_q_tail);
9526 next_qp = AscReadLramByte(iop_base,
9527 (ushort)(q_addr + (ushort)ASC_SCSIQ_B_FWD));
9528 if (next_qp != ASC_QLINK_END) {
9529 AscPutVarDoneQTail(iop_base, next_qp);
9530 q_addr = ASC_QNO_TO_QADDR(next_qp);
9531 sg_queue_cnt = _AscCopyLramScsiDoneQ(iop_base, q_addr, scsiq,
9532 asc_dvc->max_dma_count);
9533 AscWriteLramByte(iop_base,
9535 (ushort)ASC_SCSIQ_B_STATUS),
9537 q_status & (uchar)~(QS_READY |
9539 tid_no = ASC_TIX_TO_TID(scsiq->d2.target_ix);
9540 target_id = ASC_TIX_TO_TARGET_ID(scsiq->d2.target_ix);
9541 if ((scsiq->cntl & QC_SG_HEAD) != 0) {
9543 sg_list_qp = next_qp;
9544 for (q_cnt = 0; q_cnt < sg_queue_cnt; q_cnt++) {
9545 sg_list_qp = AscReadLramByte(iop_base,
9549 sg_q_addr = ASC_QNO_TO_QADDR(sg_list_qp);
9550 if (sg_list_qp == ASC_QLINK_END) {
9551 AscSetLibErrorCode(asc_dvc,
9552 ASCQ_ERR_SG_Q_LINKS);
9553 scsiq->d3.done_stat = QD_WITH_ERROR;
9554 scsiq->d3.host_stat =
9555 QHSTA_D_QDONE_SG_LIST_CORRUPTED;
9556 goto FATAL_ERR_QDONE;
9558 AscWriteLramByte(iop_base,
9559 (ushort)(sg_q_addr + (ushort)
9560 ASC_SCSIQ_B_STATUS),
9563 n_q_used = sg_queue_cnt + 1;
9564 AscPutVarDoneQTail(iop_base, sg_list_qp);
9566 if (asc_dvc->queue_full_or_busy & target_id) {
9567 cur_target_qng = AscReadLramByte(iop_base,
9573 if (cur_target_qng < asc_dvc->max_dvc_qng[tid_no]) {
9574 scsi_busy = AscReadLramByte(iop_base, (ushort)
9576 scsi_busy &= ~target_id;
9577 AscWriteLramByte(iop_base,
9578 (ushort)ASCV_SCSIBUSY_B,
9580 asc_dvc->queue_full_or_busy &= ~target_id;
9583 if (asc_dvc->cur_total_qng >= n_q_used) {
9584 asc_dvc->cur_total_qng -= n_q_used;
9585 if (asc_dvc->cur_dvc_qng[tid_no] != 0) {
9586 asc_dvc->cur_dvc_qng[tid_no]--;
9589 AscSetLibErrorCode(asc_dvc, ASCQ_ERR_CUR_QNG);
9590 scsiq->d3.done_stat = QD_WITH_ERROR;
9591 goto FATAL_ERR_QDONE;
9593 if ((scsiq->d2.srb_ptr == 0UL) ||
9594 ((scsiq->q_status & QS_ABORTED) != 0)) {
9596 } else if (scsiq->q_status == QS_DONE) {
9597 false_overrun = FALSE;
9598 if (scsiq->extra_bytes != 0) {
9599 scsiq->remain_bytes +=
9600 (ADV_DCNT)scsiq->extra_bytes;
9602 if (scsiq->d3.done_stat == QD_WITH_ERROR) {
9603 if (scsiq->d3.host_stat ==
9604 QHSTA_M_DATA_OVER_RUN) {
9606 cntl & (QC_DATA_IN | QC_DATA_OUT))
9608 scsiq->d3.done_stat =
9610 scsiq->d3.host_stat =
9612 } else if (false_overrun) {
9613 scsiq->d3.done_stat =
9615 scsiq->d3.host_stat =
9618 } else if (scsiq->d3.host_stat ==
9619 QHSTA_M_HUNG_REQ_SCSI_BUS_RESET) {
9620 AscStopChip(iop_base);
9621 AscSetChipControl(iop_base,
9622 (uchar)(CC_SCSI_RESET
9625 AscSetChipControl(iop_base, CC_HALT);
9626 AscSetChipStatus(iop_base,
9627 CIW_CLR_SCSI_RESET_INT);
9628 AscSetChipStatus(iop_base, 0);
9629 AscSetChipControl(iop_base, 0);
9632 if ((scsiq->cntl & QC_NO_CALLBACK) == 0) {
9633 asc_isr_callback(asc_dvc, scsiq);
9635 if ((AscReadLramByte(iop_base,
9636 (ushort)(q_addr + (ushort)
9639 asc_dvc->unit_not_ready &= ~target_id;
9640 if (scsiq->d3.done_stat != QD_NO_ERROR) {
9641 asc_dvc->start_motor &=
9648 AscSetLibErrorCode(asc_dvc, ASCQ_ERR_Q_STATUS);
9650 if ((scsiq->cntl & QC_NO_CALLBACK) == 0) {
9651 asc_isr_callback(asc_dvc, scsiq);
9659 static int AscISR(ASC_DVC_VAR *asc_dvc)
9661 ASC_CS_TYPE chipstat;
9663 ushort saved_ram_addr;
9665 uchar saved_ctrl_reg;
9670 iop_base = asc_dvc->iop_base;
9671 int_pending = FALSE;
9673 if (AscIsIntPending(iop_base) == 0)
9676 if ((asc_dvc->init_state & ASC_INIT_STATE_END_LOAD_MC) == 0) {
9679 if (asc_dvc->in_critical_cnt != 0) {
9680 AscSetLibErrorCode(asc_dvc, ASCQ_ERR_ISR_ON_CRITICAL);
9683 if (asc_dvc->is_in_int) {
9684 AscSetLibErrorCode(asc_dvc, ASCQ_ERR_ISR_RE_ENTRY);
9687 asc_dvc->is_in_int = TRUE;
9688 ctrl_reg = AscGetChipControl(iop_base);
9689 saved_ctrl_reg = ctrl_reg & (~(CC_SCSI_RESET | CC_CHIP_RESET |
9690 CC_SINGLE_STEP | CC_DIAG | CC_TEST));
9691 chipstat = AscGetChipStatus(iop_base);
9692 if (chipstat & CSW_SCSI_RESET_LATCH) {
9693 if (!(asc_dvc->bus_type & (ASC_IS_VL | ASC_IS_EISA))) {
9696 asc_dvc->sdtr_done = 0;
9697 saved_ctrl_reg &= (uchar)(~CC_HALT);
9698 while ((AscGetChipStatus(iop_base) &
9699 CSW_SCSI_RESET_ACTIVE) && (i-- > 0)) {
9702 AscSetChipControl(iop_base, (CC_CHIP_RESET | CC_HALT));
9703 AscSetChipControl(iop_base, CC_HALT);
9704 AscSetChipStatus(iop_base, CIW_CLR_SCSI_RESET_INT);
9705 AscSetChipStatus(iop_base, 0);
9706 chipstat = AscGetChipStatus(iop_base);
9709 saved_ram_addr = AscGetChipLramAddr(iop_base);
9710 host_flag = AscReadLramByte(iop_base,
9712 (uchar)(~ASC_HOST_FLAG_IN_ISR);
9713 AscWriteLramByte(iop_base, ASCV_HOST_FLAG_B,
9714 (uchar)(host_flag | (uchar)ASC_HOST_FLAG_IN_ISR));
9715 if ((chipstat & CSW_INT_PENDING) || (int_pending)) {
9716 AscAckInterrupt(iop_base);
9718 if ((chipstat & CSW_HALTED) && (ctrl_reg & CC_SINGLE_STEP)) {
9719 if (AscIsrChipHalted(asc_dvc) == ERR) {
9720 goto ISR_REPORT_QDONE_FATAL_ERROR;
9722 saved_ctrl_reg &= (uchar)(~CC_HALT);
9725 ISR_REPORT_QDONE_FATAL_ERROR:
9726 if ((asc_dvc->dvc_cntl & ASC_CNTL_INT_MULTI_Q) != 0) {
9728 AscIsrQDone(asc_dvc)) & 0x01) != 0) {
9733 AscIsrQDone(asc_dvc)) == 1) {
9736 } while (status == 0x11);
9738 if ((status & 0x80) != 0)
9742 AscWriteLramByte(iop_base, ASCV_HOST_FLAG_B, host_flag);
9743 AscSetChipLramAddr(iop_base, saved_ram_addr);
9744 AscSetChipControl(iop_base, saved_ctrl_reg);
9745 asc_dvc->is_in_int = FALSE;
9752 * Reset the bus associated with the command 'scp'.
9754 * This function runs its own thread. Interrupts must be blocked but
9755 * sleeping is allowed and no locking other than for host structures is
9756 * required. Returns SUCCESS or FAILED.
9758 static int advansys_reset(struct scsi_cmnd *scp)
9760 struct Scsi_Host *shost;
9761 asc_board_t *boardp;
9762 ASC_DVC_VAR *asc_dvc_varp;
9763 ADV_DVC_VAR *adv_dvc_varp;
9768 ASC_DBG1(1, "advansys_reset: 0x%lx\n", (ulong)scp);
9770 #ifdef ADVANSYS_STATS
9771 if (scp->device->host != NULL) {
9772 ASC_STATS(scp->device->host, reset);
9774 #endif /* ADVANSYS_STATS */
9776 if ((shost = scp->device->host) == NULL) {
9777 scp->result = HOST_BYTE(DID_ERROR);
9781 boardp = ASC_BOARDP(shost);
9783 ASC_PRINT1("advansys_reset: board %d: SCSI bus reset started...\n",
9786 * Check for re-entrancy.
9788 spin_lock_irqsave(&boardp->lock, flags);
9789 if (boardp->flags & ASC_HOST_IN_RESET) {
9790 spin_unlock_irqrestore(&boardp->lock, flags);
9793 boardp->flags |= ASC_HOST_IN_RESET;
9794 spin_unlock_irqrestore(&boardp->lock, flags);
9796 if (ASC_NARROW_BOARD(boardp)) {
9800 asc_dvc_varp = &boardp->dvc_var.asc_dvc_var;
9803 * Reset the chip and SCSI bus.
9805 ASC_DBG(1, "advansys_reset: before AscInitAsc1000Driver()\n");
9806 status = AscInitAsc1000Driver(asc_dvc_varp);
9808 /* Refer to ASC_IERR_* defintions for meaning of 'err_code'. */
9809 if (asc_dvc_varp->err_code) {
9810 ASC_PRINT2("advansys_reset: board %d: SCSI bus reset "
9811 "error: 0x%x\n", boardp->id,
9812 asc_dvc_varp->err_code);
9814 } else if (status) {
9815 ASC_PRINT2("advansys_reset: board %d: SCSI bus reset "
9816 "warning: 0x%x\n", boardp->id, status);
9818 ASC_PRINT1("advansys_reset: board %d: SCSI bus reset "
9819 "successful.\n", boardp->id);
9822 ASC_DBG(1, "advansys_reset: after AscInitAsc1000Driver()\n");
9823 spin_lock_irqsave(&boardp->lock, flags);
9829 * If the suggest reset bus flags are set, then reset the bus.
9830 * Otherwise only reset the device.
9832 adv_dvc_varp = &boardp->dvc_var.adv_dvc_var;
9835 * Reset the target's SCSI bus.
9837 ASC_DBG(1, "advansys_reset: before AdvResetChipAndSB()\n");
9838 switch (AdvResetChipAndSB(adv_dvc_varp)) {
9840 ASC_PRINT1("advansys_reset: board %d: SCSI bus reset "
9841 "successful.\n", boardp->id);
9845 ASC_PRINT1("advansys_reset: board %d: SCSI bus reset "
9846 "error.\n", boardp->id);
9850 spin_lock_irqsave(&boardp->lock, flags);
9851 AdvISR(adv_dvc_varp);
9853 /* Board lock is held. */
9855 /* Save the time of the most recently completed reset. */
9856 boardp->last_reset = jiffies;
9858 /* Clear reset flag. */
9859 boardp->flags &= ~ASC_HOST_IN_RESET;
9860 spin_unlock_irqrestore(&boardp->lock, flags);
9862 ASC_DBG1(1, "advansys_reset: ret %d\n", ret);
9868 * advansys_biosparam()
9870 * Translate disk drive geometry if the "BIOS greater than 1 GB"
9871 * support is enabled for a drive.
9873 * ip (information pointer) is an int array with the following definition:
9879 advansys_biosparam(struct scsi_device *sdev, struct block_device *bdev,
9880 sector_t capacity, int ip[])
9882 asc_board_t *boardp;
9884 ASC_DBG(1, "advansys_biosparam: begin\n");
9885 ASC_STATS(sdev->host, biosparam);
9886 boardp = ASC_BOARDP(sdev->host);
9887 if (ASC_NARROW_BOARD(boardp)) {
9888 if ((boardp->dvc_var.asc_dvc_var.dvc_cntl &
9889 ASC_CNTL_BIOS_GT_1GB) && capacity > 0x200000) {
9897 if ((boardp->dvc_var.adv_dvc_var.bios_ctrl &
9898 BIOS_CTRL_EXTENDED_XLAT) && capacity > 0x200000) {
9906 ip[2] = (unsigned long)capacity / (ip[0] * ip[1]);
9907 ASC_DBG(1, "advansys_biosparam: end\n");
9912 * First-level interrupt handler.
9914 * 'dev_id' is a pointer to the interrupting adapter's Scsi_Host.
9916 static irqreturn_t advansys_interrupt(int irq, void *dev_id)
9918 unsigned long flags;
9919 struct Scsi_Host *shost = dev_id;
9920 asc_board_t *boardp = ASC_BOARDP(shost);
9921 irqreturn_t result = IRQ_NONE;
9923 ASC_DBG1(2, "advansys_interrupt: boardp 0x%p\n", boardp);
9924 spin_lock_irqsave(&boardp->lock, flags);
9925 if (ASC_NARROW_BOARD(boardp)) {
9926 if (AscIsIntPending(shost->io_port)) {
9927 result = IRQ_HANDLED;
9928 ASC_STATS(shost, interrupt);
9929 ASC_DBG(1, "advansys_interrupt: before AscISR()\n");
9930 AscISR(&boardp->dvc_var.asc_dvc_var);
9933 ASC_DBG(1, "advansys_interrupt: before AdvISR()\n");
9934 if (AdvISR(&boardp->dvc_var.adv_dvc_var)) {
9935 result = IRQ_HANDLED;
9936 ASC_STATS(shost, interrupt);
9939 spin_unlock_irqrestore(&boardp->lock, flags);
9941 ASC_DBG(1, "advansys_interrupt: end\n");
9945 static int AscHostReqRiscHalt(PortAddr iop_base)
9949 uchar saved_stop_code;
9951 if (AscIsChipHalted(iop_base))
9953 saved_stop_code = AscReadLramByte(iop_base, ASCV_STOP_CODE_B);
9954 AscWriteLramByte(iop_base, ASCV_STOP_CODE_B,
9955 ASC_STOP_HOST_REQ_RISC_HALT | ASC_STOP_REQ_RISC_STOP);
9957 if (AscIsChipHalted(iop_base)) {
9962 } while (count++ < 20);
9963 AscWriteLramByte(iop_base, ASCV_STOP_CODE_B, saved_stop_code);
9968 AscSetRunChipSynRegAtID(PortAddr iop_base, uchar tid_no, uchar sdtr_data)
9972 if (AscHostReqRiscHalt(iop_base)) {
9973 sta = AscSetChipSynRegAtID(iop_base, tid_no, sdtr_data);
9974 AscStartChip(iop_base);
9979 static void AscAsyncFix(ASC_DVC_VAR *asc_dvc, struct scsi_device *sdev)
9981 char type = sdev->type;
9982 ASC_SCSI_BIT_ID_TYPE tid_bits = 1 << sdev->id;
9984 if (!(asc_dvc->bug_fix_cntl & ASC_BUG_FIX_ASYN_USE_SYN))
9986 if (asc_dvc->init_sdtr & tid_bits)
9989 if ((type == TYPE_ROM) && (strncmp(sdev->vendor, "HP ", 3) == 0))
9990 asc_dvc->pci_fix_asyn_xfer_always |= tid_bits;
9992 asc_dvc->pci_fix_asyn_xfer |= tid_bits;
9993 if ((type == TYPE_PROCESSOR) || (type == TYPE_SCANNER) ||
9994 (type == TYPE_ROM) || (type == TYPE_TAPE))
9995 asc_dvc->pci_fix_asyn_xfer &= ~tid_bits;
9997 if (asc_dvc->pci_fix_asyn_xfer & tid_bits)
9998 AscSetRunChipSynRegAtID(asc_dvc->iop_base, sdev->id,
9999 ASYN_SDTR_DATA_FIX_PCI_REV_AB);
10003 advansys_narrow_slave_configure(struct scsi_device *sdev, ASC_DVC_VAR *asc_dvc)
10005 ASC_SCSI_BIT_ID_TYPE tid_bit = 1 << sdev->id;
10006 ASC_SCSI_BIT_ID_TYPE orig_use_tagged_qng = asc_dvc->use_tagged_qng;
10008 if (sdev->lun == 0) {
10009 ASC_SCSI_BIT_ID_TYPE orig_init_sdtr = asc_dvc->init_sdtr;
10010 if ((asc_dvc->cfg->sdtr_enable & tid_bit) && sdev->sdtr) {
10011 asc_dvc->init_sdtr |= tid_bit;
10013 asc_dvc->init_sdtr &= ~tid_bit;
10016 if (orig_init_sdtr != asc_dvc->init_sdtr)
10017 AscAsyncFix(asc_dvc, sdev);
10020 if (sdev->tagged_supported) {
10021 if (asc_dvc->cfg->cmd_qng_enabled & tid_bit) {
10022 if (sdev->lun == 0) {
10023 asc_dvc->cfg->can_tagged_qng |= tid_bit;
10024 asc_dvc->use_tagged_qng |= tid_bit;
10026 scsi_adjust_queue_depth(sdev, MSG_ORDERED_TAG,
10027 asc_dvc->max_dvc_qng[sdev->id]);
10030 if (sdev->lun == 0) {
10031 asc_dvc->cfg->can_tagged_qng &= ~tid_bit;
10032 asc_dvc->use_tagged_qng &= ~tid_bit;
10034 scsi_adjust_queue_depth(sdev, 0, sdev->host->cmd_per_lun);
10037 if ((sdev->lun == 0) &&
10038 (orig_use_tagged_qng != asc_dvc->use_tagged_qng)) {
10039 AscWriteLramByte(asc_dvc->iop_base, ASCV_DISC_ENABLE_B,
10040 asc_dvc->cfg->disc_enable);
10041 AscWriteLramByte(asc_dvc->iop_base, ASCV_USE_TAGGED_QNG_B,
10042 asc_dvc->use_tagged_qng);
10043 AscWriteLramByte(asc_dvc->iop_base, ASCV_CAN_TAGGED_QNG_B,
10044 asc_dvc->cfg->can_tagged_qng);
10046 asc_dvc->max_dvc_qng[sdev->id] =
10047 asc_dvc->cfg->max_tag_qng[sdev->id];
10048 AscWriteLramByte(asc_dvc->iop_base,
10049 (ushort)(ASCV_MAX_DVC_QNG_BEG + sdev->id),
10050 asc_dvc->max_dvc_qng[sdev->id]);
10057 * If the EEPROM enabled WDTR for the device and the device supports wide
10058 * bus (16 bit) transfers, then turn on the device's 'wdtr_able' bit and
10059 * write the new value to the microcode.
10062 advansys_wide_enable_wdtr(AdvPortAddr iop_base, unsigned short tidmask)
10064 unsigned short cfg_word;
10065 AdvReadWordLram(iop_base, ASC_MC_WDTR_ABLE, cfg_word);
10066 if ((cfg_word & tidmask) != 0)
10069 cfg_word |= tidmask;
10070 AdvWriteWordLram(iop_base, ASC_MC_WDTR_ABLE, cfg_word);
10073 * Clear the microcode SDTR and WDTR negotiation done indicators for
10074 * the target to cause it to negotiate with the new setting set above.
10075 * WDTR when accepted causes the target to enter asynchronous mode, so
10076 * SDTR must be negotiated.
10078 AdvReadWordLram(iop_base, ASC_MC_SDTR_DONE, cfg_word);
10079 cfg_word &= ~tidmask;
10080 AdvWriteWordLram(iop_base, ASC_MC_SDTR_DONE, cfg_word);
10081 AdvReadWordLram(iop_base, ASC_MC_WDTR_DONE, cfg_word);
10082 cfg_word &= ~tidmask;
10083 AdvWriteWordLram(iop_base, ASC_MC_WDTR_DONE, cfg_word);
10087 * Synchronous Transfers
10089 * If the EEPROM enabled SDTR for the device and the device
10090 * supports synchronous transfers, then turn on the device's
10091 * 'sdtr_able' bit. Write the new value to the microcode.
10094 advansys_wide_enable_sdtr(AdvPortAddr iop_base, unsigned short tidmask)
10096 unsigned short cfg_word;
10097 AdvReadWordLram(iop_base, ASC_MC_SDTR_ABLE, cfg_word);
10098 if ((cfg_word & tidmask) != 0)
10101 cfg_word |= tidmask;
10102 AdvWriteWordLram(iop_base, ASC_MC_SDTR_ABLE, cfg_word);
10105 * Clear the microcode "SDTR negotiation" done indicator for the
10106 * target to cause it to negotiate with the new setting set above.
10108 AdvReadWordLram(iop_base, ASC_MC_SDTR_DONE, cfg_word);
10109 cfg_word &= ~tidmask;
10110 AdvWriteWordLram(iop_base, ASC_MC_SDTR_DONE, cfg_word);
10114 * PPR (Parallel Protocol Request) Capable
10116 * If the device supports DT mode, then it must be PPR capable.
10117 * The PPR message will be used in place of the SDTR and WDTR
10118 * messages to negotiate synchronous speed and offset, transfer
10119 * width, and protocol options.
10121 static void advansys_wide_enable_ppr(ADV_DVC_VAR *adv_dvc,
10122 AdvPortAddr iop_base, unsigned short tidmask)
10124 AdvReadWordLram(iop_base, ASC_MC_PPR_ABLE, adv_dvc->ppr_able);
10125 adv_dvc->ppr_able |= tidmask;
10126 AdvWriteWordLram(iop_base, ASC_MC_PPR_ABLE, adv_dvc->ppr_able);
10130 advansys_wide_slave_configure(struct scsi_device *sdev, ADV_DVC_VAR *adv_dvc)
10132 AdvPortAddr iop_base = adv_dvc->iop_base;
10133 unsigned short tidmask = 1 << sdev->id;
10135 if (sdev->lun == 0) {
10137 * Handle WDTR, SDTR, and Tag Queuing. If the feature
10138 * is enabled in the EEPROM and the device supports the
10139 * feature, then enable it in the microcode.
10142 if ((adv_dvc->wdtr_able & tidmask) && sdev->wdtr)
10143 advansys_wide_enable_wdtr(iop_base, tidmask);
10144 if ((adv_dvc->sdtr_able & tidmask) && sdev->sdtr)
10145 advansys_wide_enable_sdtr(iop_base, tidmask);
10146 if (adv_dvc->chip_type == ADV_CHIP_ASC38C1600 && sdev->ppr)
10147 advansys_wide_enable_ppr(adv_dvc, iop_base, tidmask);
10150 * Tag Queuing is disabled for the BIOS which runs in polled
10151 * mode and would see no benefit from Tag Queuing. Also by
10152 * disabling Tag Queuing in the BIOS devices with Tag Queuing
10153 * bugs will at least work with the BIOS.
10155 if ((adv_dvc->tagqng_able & tidmask) &&
10156 sdev->tagged_supported) {
10157 unsigned short cfg_word;
10158 AdvReadWordLram(iop_base, ASC_MC_TAGQNG_ABLE, cfg_word);
10159 cfg_word |= tidmask;
10160 AdvWriteWordLram(iop_base, ASC_MC_TAGQNG_ABLE,
10162 AdvWriteByteLram(iop_base,
10163 ASC_MC_NUMBER_OF_MAX_CMD + sdev->id,
10164 adv_dvc->max_dvc_qng);
10168 if ((adv_dvc->tagqng_able & tidmask) && sdev->tagged_supported) {
10169 scsi_adjust_queue_depth(sdev, MSG_ORDERED_TAG,
10170 adv_dvc->max_dvc_qng);
10172 scsi_adjust_queue_depth(sdev, 0, sdev->host->cmd_per_lun);
10177 * Set the number of commands to queue per device for the
10178 * specified host adapter.
10180 static int advansys_slave_configure(struct scsi_device *sdev)
10182 asc_board_t *boardp = ASC_BOARDP(sdev->host);
10183 boardp->flags |= ASC_SELECT_QUEUE_DEPTHS;
10185 if (ASC_NARROW_BOARD(boardp))
10186 advansys_narrow_slave_configure(sdev,
10187 &boardp->dvc_var.asc_dvc_var);
10189 advansys_wide_slave_configure(sdev,
10190 &boardp->dvc_var.adv_dvc_var);
10196 * Build a request structure for the Asc Library (Narrow Board).
10198 * The global structures 'asc_scsi_q' and 'asc_sg_head' are
10199 * used to build the request.
10201 * If an error occurs, then return ASC_ERROR.
10203 static int asc_build_req(asc_board_t *boardp, struct scsi_cmnd *scp)
10206 * Mutually exclusive access is required to 'asc_scsi_q' and
10207 * 'asc_sg_head' until after the request is started.
10209 memset(&asc_scsi_q, 0, sizeof(ASC_SCSI_Q));
10212 * Point the ASC_SCSI_Q to the 'struct scsi_cmnd'.
10214 asc_scsi_q.q2.srb_ptr = ASC_VADDR_TO_U32(scp);
10217 * Build the ASC_SCSI_Q request.
10219 asc_scsi_q.cdbptr = &scp->cmnd[0];
10220 asc_scsi_q.q2.cdb_len = scp->cmd_len;
10221 asc_scsi_q.q1.target_id = ASC_TID_TO_TARGET_ID(scp->device->id);
10222 asc_scsi_q.q1.target_lun = scp->device->lun;
10223 asc_scsi_q.q2.target_ix =
10224 ASC_TIDLUN_TO_IX(scp->device->id, scp->device->lun);
10225 asc_scsi_q.q1.sense_addr =
10226 cpu_to_le32(virt_to_bus(&scp->sense_buffer[0]));
10227 asc_scsi_q.q1.sense_len = sizeof(scp->sense_buffer);
10230 * If there are any outstanding requests for the current target,
10231 * then every 255th request send an ORDERED request. This heuristic
10232 * tries to retain the benefit of request sorting while preventing
10233 * request starvation. 255 is the max number of tags or pending commands
10234 * a device may have outstanding.
10236 * The request count is incremented below for every successfully
10240 if ((boardp->dvc_var.asc_dvc_var.cur_dvc_qng[scp->device->id] > 0) &&
10241 (boardp->reqcnt[scp->device->id] % 255) == 0) {
10242 asc_scsi_q.q2.tag_code = MSG_ORDERED_TAG;
10244 asc_scsi_q.q2.tag_code = MSG_SIMPLE_TAG;
10248 * Build ASC_SCSI_Q for a contiguous buffer or a scatter-gather
10251 if (scp->use_sg == 0) {
10253 * CDB request of single contiguous buffer.
10255 ASC_STATS(scp->device->host, cont_cnt);
10256 scp->SCp.dma_handle = scp->request_bufflen ?
10257 dma_map_single(boardp->dev, scp->request_buffer,
10258 scp->request_bufflen,
10259 scp->sc_data_direction) : 0;
10260 asc_scsi_q.q1.data_addr = cpu_to_le32(scp->SCp.dma_handle);
10261 asc_scsi_q.q1.data_cnt = cpu_to_le32(scp->request_bufflen);
10262 ASC_STATS_ADD(scp->device->host, cont_xfer,
10263 ASC_CEILING(scp->request_bufflen, 512));
10264 asc_scsi_q.q1.sg_queue_cnt = 0;
10265 asc_scsi_q.sg_head = NULL;
10268 * CDB scatter-gather request list.
10272 struct scatterlist *slp;
10274 slp = (struct scatterlist *)scp->request_buffer;
10275 use_sg = dma_map_sg(boardp->dev, slp, scp->use_sg,
10276 scp->sc_data_direction);
10278 if (use_sg > scp->device->host->sg_tablesize) {
10279 ASC_PRINT3("asc_build_req: board %d: use_sg %d > "
10280 "sg_tablesize %d\n", boardp->id, use_sg,
10281 scp->device->host->sg_tablesize);
10282 dma_unmap_sg(boardp->dev, slp, scp->use_sg,
10283 scp->sc_data_direction);
10284 scp->result = HOST_BYTE(DID_ERROR);
10288 ASC_STATS(scp->device->host, sg_cnt);
10291 * Use global ASC_SG_HEAD structure and set the ASC_SCSI_Q
10292 * structure to point to it.
10294 memset(&asc_sg_head, 0, sizeof(ASC_SG_HEAD));
10296 asc_scsi_q.q1.cntl |= QC_SG_HEAD;
10297 asc_scsi_q.sg_head = &asc_sg_head;
10298 asc_scsi_q.q1.data_cnt = 0;
10299 asc_scsi_q.q1.data_addr = 0;
10300 /* This is a byte value, otherwise it would need to be swapped. */
10301 asc_sg_head.entry_cnt = asc_scsi_q.q1.sg_queue_cnt = use_sg;
10302 ASC_STATS_ADD(scp->device->host, sg_elem,
10303 asc_sg_head.entry_cnt);
10306 * Convert scatter-gather list into ASC_SG_HEAD list.
10308 for (sgcnt = 0; sgcnt < use_sg; sgcnt++, slp++) {
10309 asc_sg_head.sg_list[sgcnt].addr =
10310 cpu_to_le32(sg_dma_address(slp));
10311 asc_sg_head.sg_list[sgcnt].bytes =
10312 cpu_to_le32(sg_dma_len(slp));
10313 ASC_STATS_ADD(scp->device->host, sg_xfer,
10314 ASC_CEILING(sg_dma_len(slp), 512));
10318 ASC_DBG_PRT_ASC_SCSI_Q(2, &asc_scsi_q);
10319 ASC_DBG_PRT_CDB(1, scp->cmnd, scp->cmd_len);
10321 return ASC_NOERROR;
10325 * Build scatter-gather list for Adv Library (Wide Board).
10327 * Additional ADV_SG_BLOCK structures will need to be allocated
10328 * if the total number of scatter-gather elements exceeds
10329 * NO_OF_SG_PER_BLOCK (15). The ADV_SG_BLOCK structures are
10330 * assumed to be physically contiguous.
10333 * ADV_SUCCESS(1) - SG List successfully created
10334 * ADV_ERROR(-1) - SG List creation failed
10337 adv_get_sglist(asc_board_t *boardp, adv_req_t *reqp, struct scsi_cmnd *scp,
10340 adv_sgblk_t *sgblkp;
10341 ADV_SCSI_REQ_Q *scsiqp;
10342 struct scatterlist *slp;
10344 ADV_SG_BLOCK *sg_block, *prev_sg_block;
10345 ADV_PADDR sg_block_paddr;
10348 scsiqp = (ADV_SCSI_REQ_Q *)ADV_32BALIGN(&reqp->scsi_req_q);
10349 slp = (struct scatterlist *)scp->request_buffer;
10350 sg_elem_cnt = use_sg;
10351 prev_sg_block = NULL;
10352 reqp->sgblkp = NULL;
10356 * Allocate a 'adv_sgblk_t' structure from the board free
10357 * list. One 'adv_sgblk_t' structure holds NO_OF_SG_PER_BLOCK
10358 * (15) scatter-gather elements.
10360 if ((sgblkp = boardp->adv_sgblkp) == NULL) {
10361 ASC_DBG(1, "adv_get_sglist: no free adv_sgblk_t\n");
10362 ASC_STATS(scp->device->host, adv_build_nosg);
10365 * Allocation failed. Free 'adv_sgblk_t' structures
10366 * already allocated for the request.
10368 while ((sgblkp = reqp->sgblkp) != NULL) {
10369 /* Remove 'sgblkp' from the request list. */
10370 reqp->sgblkp = sgblkp->next_sgblkp;
10372 /* Add 'sgblkp' to the board free list. */
10373 sgblkp->next_sgblkp = boardp->adv_sgblkp;
10374 boardp->adv_sgblkp = sgblkp;
10379 /* Complete 'adv_sgblk_t' board allocation. */
10380 boardp->adv_sgblkp = sgblkp->next_sgblkp;
10381 sgblkp->next_sgblkp = NULL;
10384 * Get 8 byte aligned virtual and physical addresses
10385 * for the allocated ADV_SG_BLOCK structure.
10387 sg_block = (ADV_SG_BLOCK *)ADV_8BALIGN(&sgblkp->sg_block);
10388 sg_block_paddr = virt_to_bus(sg_block);
10391 * Check if this is the first 'adv_sgblk_t' for the
10394 if (reqp->sgblkp == NULL) {
10395 /* Request's first scatter-gather block. */
10396 reqp->sgblkp = sgblkp;
10399 * Set ADV_SCSI_REQ_T ADV_SG_BLOCK virtual and physical
10400 * address pointers.
10402 scsiqp->sg_list_ptr = sg_block;
10403 scsiqp->sg_real_addr = cpu_to_le32(sg_block_paddr);
10405 /* Request's second or later scatter-gather block. */
10406 sgblkp->next_sgblkp = reqp->sgblkp;
10407 reqp->sgblkp = sgblkp;
10410 * Point the previous ADV_SG_BLOCK structure to
10411 * the newly allocated ADV_SG_BLOCK structure.
10413 prev_sg_block->sg_ptr = cpu_to_le32(sg_block_paddr);
10416 for (i = 0; i < NO_OF_SG_PER_BLOCK; i++) {
10417 sg_block->sg_list[i].sg_addr =
10418 cpu_to_le32(sg_dma_address(slp));
10419 sg_block->sg_list[i].sg_count =
10420 cpu_to_le32(sg_dma_len(slp));
10421 ASC_STATS_ADD(scp->device->host, sg_xfer,
10422 ASC_CEILING(sg_dma_len(slp), 512));
10424 if (--sg_elem_cnt == 0) { /* Last ADV_SG_BLOCK and scatter-gather entry. */
10425 sg_block->sg_cnt = i + 1;
10426 sg_block->sg_ptr = 0L; /* Last ADV_SG_BLOCK in list. */
10427 return ADV_SUCCESS;
10431 sg_block->sg_cnt = NO_OF_SG_PER_BLOCK;
10432 prev_sg_block = sg_block;
10437 * Build a request structure for the Adv Library (Wide Board).
10439 * If an adv_req_t can not be allocated to issue the request,
10440 * then return ASC_BUSY. If an error occurs, then return ASC_ERROR.
10442 * Multi-byte fields in the ASC_SCSI_REQ_Q that are used by the
10443 * microcode for DMA addresses or math operations are byte swapped
10444 * to little-endian order.
10447 adv_build_req(asc_board_t *boardp, struct scsi_cmnd *scp,
10448 ADV_SCSI_REQ_Q **adv_scsiqpp)
10451 ADV_SCSI_REQ_Q *scsiqp;
10456 * Allocate an adv_req_t structure from the board to execute
10459 if (boardp->adv_reqp == NULL) {
10460 ASC_DBG(1, "adv_build_req: no free adv_req_t\n");
10461 ASC_STATS(scp->device->host, adv_build_noreq);
10464 reqp = boardp->adv_reqp;
10465 boardp->adv_reqp = reqp->next_reqp;
10466 reqp->next_reqp = NULL;
10470 * Get 32-byte aligned ADV_SCSI_REQ_Q and ADV_SG_BLOCK pointers.
10472 scsiqp = (ADV_SCSI_REQ_Q *)ADV_32BALIGN(&reqp->scsi_req_q);
10475 * Initialize the structure.
10477 scsiqp->cntl = scsiqp->scsi_cntl = scsiqp->done_status = 0;
10480 * Set the ADV_SCSI_REQ_Q 'srb_ptr' to point to the adv_req_t structure.
10482 scsiqp->srb_ptr = ASC_VADDR_TO_U32(reqp);
10485 * Set the adv_req_t 'cmndp' to point to the struct scsi_cmnd structure.
10490 * Build the ADV_SCSI_REQ_Q request.
10493 /* Set CDB length and copy it to the request structure. */
10494 scsiqp->cdb_len = scp->cmd_len;
10495 /* Copy first 12 CDB bytes to cdb[]. */
10496 for (i = 0; i < scp->cmd_len && i < 12; i++) {
10497 scsiqp->cdb[i] = scp->cmnd[i];
10499 /* Copy last 4 CDB bytes, if present, to cdb16[]. */
10500 for (; i < scp->cmd_len; i++) {
10501 scsiqp->cdb16[i - 12] = scp->cmnd[i];
10504 scsiqp->target_id = scp->device->id;
10505 scsiqp->target_lun = scp->device->lun;
10507 scsiqp->sense_addr = cpu_to_le32(virt_to_bus(&scp->sense_buffer[0]));
10508 scsiqp->sense_len = sizeof(scp->sense_buffer);
10511 * Build ADV_SCSI_REQ_Q for a contiguous buffer or a scatter-gather
10515 scsiqp->data_cnt = cpu_to_le32(scp->request_bufflen);
10516 scsiqp->vdata_addr = scp->request_buffer;
10517 scsiqp->data_addr = cpu_to_le32(virt_to_bus(scp->request_buffer));
10519 if (scp->use_sg == 0) {
10521 * CDB request of single contiguous buffer.
10523 reqp->sgblkp = NULL;
10524 scsiqp->data_cnt = cpu_to_le32(scp->request_bufflen);
10525 if (scp->request_bufflen) {
10526 scsiqp->vdata_addr = scp->request_buffer;
10527 scp->SCp.dma_handle =
10528 dma_map_single(boardp->dev, scp->request_buffer,
10529 scp->request_bufflen,
10530 scp->sc_data_direction);
10532 scsiqp->vdata_addr = NULL;
10533 scp->SCp.dma_handle = 0;
10535 scsiqp->data_addr = cpu_to_le32(scp->SCp.dma_handle);
10536 scsiqp->sg_list_ptr = NULL;
10537 scsiqp->sg_real_addr = 0;
10538 ASC_STATS(scp->device->host, cont_cnt);
10539 ASC_STATS_ADD(scp->device->host, cont_xfer,
10540 ASC_CEILING(scp->request_bufflen, 512));
10543 * CDB scatter-gather request list.
10545 struct scatterlist *slp;
10548 slp = (struct scatterlist *)scp->request_buffer;
10549 use_sg = dma_map_sg(boardp->dev, slp, scp->use_sg,
10550 scp->sc_data_direction);
10552 if (use_sg > ADV_MAX_SG_LIST) {
10553 ASC_PRINT3("adv_build_req: board %d: use_sg %d > "
10554 "ADV_MAX_SG_LIST %d\n", boardp->id, use_sg,
10555 scp->device->host->sg_tablesize);
10556 dma_unmap_sg(boardp->dev, slp, scp->use_sg,
10557 scp->sc_data_direction);
10558 scp->result = HOST_BYTE(DID_ERROR);
10561 * Free the 'adv_req_t' structure by adding it back
10562 * to the board free list.
10564 reqp->next_reqp = boardp->adv_reqp;
10565 boardp->adv_reqp = reqp;
10570 ret = adv_get_sglist(boardp, reqp, scp, use_sg);
10571 if (ret != ADV_SUCCESS) {
10573 * Free the adv_req_t structure by adding it back to
10574 * the board free list.
10576 reqp->next_reqp = boardp->adv_reqp;
10577 boardp->adv_reqp = reqp;
10582 ASC_STATS(scp->device->host, sg_cnt);
10583 ASC_STATS_ADD(scp->device->host, sg_elem, use_sg);
10586 ASC_DBG_PRT_ADV_SCSI_REQ_Q(2, scsiqp);
10587 ASC_DBG_PRT_CDB(1, scp->cmnd, scp->cmd_len);
10589 *adv_scsiqpp = scsiqp;
10591 return ASC_NOERROR;
10594 static int AscSgListToQueue(int sg_list)
10598 n_sg_list_qs = ((sg_list - 1) / ASC_SG_LIST_PER_Q);
10599 if (((sg_list - 1) % ASC_SG_LIST_PER_Q) != 0)
10601 return n_sg_list_qs + 1;
10605 AscGetNumOfFreeQueue(ASC_DVC_VAR *asc_dvc, uchar target_ix, uchar n_qs)
10609 ASC_SCSI_BIT_ID_TYPE target_id;
10612 target_id = ASC_TIX_TO_TARGET_ID(target_ix);
10613 tid_no = ASC_TIX_TO_TID(target_ix);
10614 if ((asc_dvc->unit_not_ready & target_id) ||
10615 (asc_dvc->queue_full_or_busy & target_id)) {
10619 cur_used_qs = (uint) asc_dvc->cur_total_qng +
10620 (uint) asc_dvc->last_q_shortage + (uint) ASC_MIN_FREE_Q;
10622 cur_used_qs = (uint) asc_dvc->cur_total_qng +
10623 (uint) ASC_MIN_FREE_Q;
10625 if ((uint) (cur_used_qs + n_qs) <= (uint) asc_dvc->max_total_qng) {
10626 cur_free_qs = (uint) asc_dvc->max_total_qng - cur_used_qs;
10627 if (asc_dvc->cur_dvc_qng[tid_no] >=
10628 asc_dvc->max_dvc_qng[tid_no]) {
10631 return cur_free_qs;
10634 if ((n_qs > asc_dvc->last_q_shortage)
10635 && (n_qs <= (asc_dvc->max_total_qng - ASC_MIN_FREE_Q))) {
10636 asc_dvc->last_q_shortage = n_qs;
10642 static uchar AscAllocFreeQueue(PortAddr iop_base, uchar free_q_head)
10648 q_addr = ASC_QNO_TO_QADDR(free_q_head);
10649 q_status = (uchar)AscReadLramByte(iop_base,
10651 ASC_SCSIQ_B_STATUS));
10652 next_qp = AscReadLramByte(iop_base, (ushort)(q_addr + ASC_SCSIQ_B_FWD));
10653 if (((q_status & QS_READY) == 0) && (next_qp != ASC_QLINK_END))
10655 return ASC_QLINK_END;
10659 AscAllocMultipleFreeQueue(PortAddr iop_base, uchar free_q_head, uchar n_free_q)
10663 for (i = 0; i < n_free_q; i++) {
10664 free_q_head = AscAllocFreeQueue(iop_base, free_q_head);
10665 if (free_q_head == ASC_QLINK_END)
10668 return free_q_head;
10673 * DvcPutScsiQ(PortAddr iop_base, ushort s_addr, uchar *outbuf, int words)
10675 * Calling/Exit State:
10679 * Output an ASC_SCSI_Q structure to the chip
10682 DvcPutScsiQ(PortAddr iop_base, ushort s_addr, uchar *outbuf, int words)
10686 ASC_DBG_PRT_HEX(2, "DvcPutScsiQ", outbuf, 2 * words);
10687 AscSetChipLramAddr(iop_base, s_addr);
10688 for (i = 0; i < 2 * words; i += 2) {
10689 if (i == 4 || i == 20) {
10692 outpw(iop_base + IOP_RAM_DATA,
10693 ((ushort)outbuf[i + 1] << 8) | outbuf[i]);
10697 static int AscPutReadyQueue(ASC_DVC_VAR *asc_dvc, ASC_SCSI_Q *scsiq, uchar q_no)
10702 uchar syn_period_ix;
10706 iop_base = asc_dvc->iop_base;
10707 if (((asc_dvc->init_sdtr & scsiq->q1.target_id) != 0) &&
10708 ((asc_dvc->sdtr_done & scsiq->q1.target_id) == 0)) {
10709 tid_no = ASC_TIX_TO_TID(scsiq->q2.target_ix);
10710 sdtr_data = AscGetMCodeInitSDTRAtID(iop_base, tid_no);
10712 (sdtr_data >> 4) & (asc_dvc->max_sdtr_index - 1);
10713 syn_offset = sdtr_data & ASC_SYN_MAX_OFFSET;
10714 AscMsgOutSDTR(asc_dvc,
10715 asc_dvc->sdtr_period_tbl[syn_period_ix],
10717 scsiq->q1.cntl |= QC_MSG_OUT;
10719 q_addr = ASC_QNO_TO_QADDR(q_no);
10720 if ((scsiq->q1.target_id & asc_dvc->use_tagged_qng) == 0) {
10721 scsiq->q2.tag_code &= ~MSG_SIMPLE_TAG;
10723 scsiq->q1.status = QS_FREE;
10724 AscMemWordCopyPtrToLram(iop_base,
10725 q_addr + ASC_SCSIQ_CDB_BEG,
10726 (uchar *)scsiq->cdbptr, scsiq->q2.cdb_len >> 1);
10728 DvcPutScsiQ(iop_base,
10729 q_addr + ASC_SCSIQ_CPY_BEG,
10730 (uchar *)&scsiq->q1.cntl,
10731 ((sizeof(ASC_SCSIQ_1) + sizeof(ASC_SCSIQ_2)) / 2) - 1);
10732 AscWriteLramWord(iop_base,
10733 (ushort)(q_addr + (ushort)ASC_SCSIQ_B_STATUS),
10734 (ushort)(((ushort)scsiq->q1.
10735 q_no << 8) | (ushort)QS_READY));
10740 AscPutReadySgListQueue(ASC_DVC_VAR *asc_dvc, ASC_SCSI_Q *scsiq, uchar q_no)
10744 ASC_SG_HEAD *sg_head;
10745 ASC_SG_LIST_Q scsi_sg_q;
10746 ASC_DCNT saved_data_addr;
10747 ASC_DCNT saved_data_cnt;
10749 ushort sg_list_dwords;
10751 ushort sg_entry_cnt;
10755 iop_base = asc_dvc->iop_base;
10756 sg_head = scsiq->sg_head;
10757 saved_data_addr = scsiq->q1.data_addr;
10758 saved_data_cnt = scsiq->q1.data_cnt;
10759 scsiq->q1.data_addr = (ASC_PADDR) sg_head->sg_list[0].addr;
10760 scsiq->q1.data_cnt = (ASC_DCNT) sg_head->sg_list[0].bytes;
10761 #if CC_VERY_LONG_SG_LIST
10763 * If sg_head->entry_cnt is greater than ASC_MAX_SG_LIST
10764 * then not all SG elements will fit in the allocated queues.
10765 * The rest of the SG elements will be copied when the RISC
10766 * completes the SG elements that fit and halts.
10768 if (sg_head->entry_cnt > ASC_MAX_SG_LIST) {
10770 * Set sg_entry_cnt to be the number of SG elements that
10771 * will fit in the allocated SG queues. It is minus 1, because
10772 * the first SG element is handled above. ASC_MAX_SG_LIST is
10773 * already inflated by 1 to account for this. For example it
10774 * may be 50 which is 1 + 7 queues * 7 SG elements.
10776 sg_entry_cnt = ASC_MAX_SG_LIST - 1;
10779 * Keep track of remaining number of SG elements that will
10780 * need to be handled from a_isr.c.
10782 scsiq->remain_sg_entry_cnt =
10783 sg_head->entry_cnt - ASC_MAX_SG_LIST;
10785 #endif /* CC_VERY_LONG_SG_LIST */
10787 * Set sg_entry_cnt to be the number of SG elements that
10788 * will fit in the allocated SG queues. It is minus 1, because
10789 * the first SG element is handled above.
10791 sg_entry_cnt = sg_head->entry_cnt - 1;
10792 #if CC_VERY_LONG_SG_LIST
10794 #endif /* CC_VERY_LONG_SG_LIST */
10795 if (sg_entry_cnt != 0) {
10796 scsiq->q1.cntl |= QC_SG_HEAD;
10797 q_addr = ASC_QNO_TO_QADDR(q_no);
10799 scsiq->q1.sg_queue_cnt = sg_head->queue_cnt;
10800 scsi_sg_q.sg_head_qp = q_no;
10801 scsi_sg_q.cntl = QCSG_SG_XFER_LIST;
10802 for (i = 0; i < sg_head->queue_cnt; i++) {
10803 scsi_sg_q.seq_no = i + 1;
10804 if (sg_entry_cnt > ASC_SG_LIST_PER_Q) {
10805 sg_list_dwords = (uchar)(ASC_SG_LIST_PER_Q * 2);
10806 sg_entry_cnt -= ASC_SG_LIST_PER_Q;
10808 scsi_sg_q.sg_list_cnt =
10810 scsi_sg_q.sg_cur_list_cnt =
10813 scsi_sg_q.sg_list_cnt =
10814 ASC_SG_LIST_PER_Q - 1;
10815 scsi_sg_q.sg_cur_list_cnt =
10816 ASC_SG_LIST_PER_Q - 1;
10819 #if CC_VERY_LONG_SG_LIST
10821 * This is the last SG queue in the list of
10822 * allocated SG queues. If there are more
10823 * SG elements than will fit in the allocated
10824 * queues, then set the QCSG_SG_XFER_MORE flag.
10826 if (sg_head->entry_cnt > ASC_MAX_SG_LIST) {
10827 scsi_sg_q.cntl |= QCSG_SG_XFER_MORE;
10829 #endif /* CC_VERY_LONG_SG_LIST */
10830 scsi_sg_q.cntl |= QCSG_SG_XFER_END;
10831 #if CC_VERY_LONG_SG_LIST
10833 #endif /* CC_VERY_LONG_SG_LIST */
10834 sg_list_dwords = sg_entry_cnt << 1;
10836 scsi_sg_q.sg_list_cnt = sg_entry_cnt;
10837 scsi_sg_q.sg_cur_list_cnt =
10840 scsi_sg_q.sg_list_cnt =
10842 scsi_sg_q.sg_cur_list_cnt =
10847 next_qp = AscReadLramByte(iop_base,
10850 scsi_sg_q.q_no = next_qp;
10851 q_addr = ASC_QNO_TO_QADDR(next_qp);
10852 AscMemWordCopyPtrToLram(iop_base,
10853 q_addr + ASC_SCSIQ_SGHD_CPY_BEG,
10854 (uchar *)&scsi_sg_q,
10855 sizeof(ASC_SG_LIST_Q) >> 1);
10856 AscMemDWordCopyPtrToLram(iop_base,
10857 q_addr + ASC_SGQ_LIST_BEG,
10858 (uchar *)&sg_head->
10861 sg_index += ASC_SG_LIST_PER_Q;
10862 scsiq->next_sg_index = sg_index;
10865 scsiq->q1.cntl &= ~QC_SG_HEAD;
10867 sta = AscPutReadyQueue(asc_dvc, scsiq, q_no);
10868 scsiq->q1.data_addr = saved_data_addr;
10869 scsiq->q1.data_cnt = saved_data_cnt;
10874 AscSendScsiQueue(ASC_DVC_VAR *asc_dvc, ASC_SCSI_Q *scsiq, uchar n_q_required)
10883 iop_base = asc_dvc->iop_base;
10884 target_ix = scsiq->q2.target_ix;
10885 tid_no = ASC_TIX_TO_TID(target_ix);
10887 free_q_head = (uchar)AscGetVarFreeQHead(iop_base);
10888 if (n_q_required > 1) {
10889 next_qp = AscAllocMultipleFreeQueue(iop_base, free_q_head,
10890 (uchar)n_q_required);
10891 if (next_qp != ASC_QLINK_END) {
10892 asc_dvc->last_q_shortage = 0;
10893 scsiq->sg_head->queue_cnt = n_q_required - 1;
10894 scsiq->q1.q_no = free_q_head;
10895 sta = AscPutReadySgListQueue(asc_dvc, scsiq,
10898 } else if (n_q_required == 1) {
10899 next_qp = AscAllocFreeQueue(iop_base, free_q_head);
10900 if (next_qp != ASC_QLINK_END) {
10901 scsiq->q1.q_no = free_q_head;
10902 sta = AscPutReadyQueue(asc_dvc, scsiq, free_q_head);
10906 AscPutVarFreeQHead(iop_base, next_qp);
10907 asc_dvc->cur_total_qng += n_q_required;
10908 asc_dvc->cur_dvc_qng[tid_no]++;
10913 #define ASC_SYN_OFFSET_ONE_DISABLE_LIST 16
10914 static uchar _syn_offset_one_disable_cmd[ASC_SYN_OFFSET_ONE_DISABLE_LIST] = {
10933 static int AscExeScsiQueue(ASC_DVC_VAR *asc_dvc, ASC_SCSI_Q *scsiq)
10938 int disable_syn_offset_one_fix;
10941 ushort sg_entry_cnt = 0;
10942 ushort sg_entry_cnt_minus_one = 0;
10949 ASC_SG_HEAD *sg_head;
10952 iop_base = asc_dvc->iop_base;
10953 sg_head = scsiq->sg_head;
10954 if (asc_dvc->err_code != 0)
10956 scsiq->q1.q_no = 0;
10957 if ((scsiq->q2.tag_code & ASC_TAG_FLAG_EXTRA_BYTES) == 0) {
10958 scsiq->q1.extra_bytes = 0;
10961 target_ix = scsiq->q2.target_ix;
10962 tid_no = ASC_TIX_TO_TID(target_ix);
10964 if (scsiq->cdbptr[0] == REQUEST_SENSE) {
10965 if ((asc_dvc->init_sdtr & scsiq->q1.target_id) != 0) {
10966 asc_dvc->sdtr_done &= ~scsiq->q1.target_id;
10967 sdtr_data = AscGetMCodeInitSDTRAtID(iop_base, tid_no);
10968 AscMsgOutSDTR(asc_dvc,
10970 sdtr_period_tbl[(sdtr_data >> 4) &
10974 (uchar)(sdtr_data & (uchar)
10975 ASC_SYN_MAX_OFFSET));
10976 scsiq->q1.cntl |= (QC_MSG_OUT | QC_URGENT);
10979 if (asc_dvc->in_critical_cnt != 0) {
10980 AscSetLibErrorCode(asc_dvc, ASCQ_ERR_CRITICAL_RE_ENTRY);
10983 asc_dvc->in_critical_cnt++;
10984 if ((scsiq->q1.cntl & QC_SG_HEAD) != 0) {
10985 if ((sg_entry_cnt = sg_head->entry_cnt) == 0) {
10986 asc_dvc->in_critical_cnt--;
10989 #if !CC_VERY_LONG_SG_LIST
10990 if (sg_entry_cnt > ASC_MAX_SG_LIST) {
10991 asc_dvc->in_critical_cnt--;
10994 #endif /* !CC_VERY_LONG_SG_LIST */
10995 if (sg_entry_cnt == 1) {
10996 scsiq->q1.data_addr =
10997 (ADV_PADDR)sg_head->sg_list[0].addr;
10998 scsiq->q1.data_cnt =
10999 (ADV_DCNT)sg_head->sg_list[0].bytes;
11000 scsiq->q1.cntl &= ~(QC_SG_HEAD | QC_SG_SWAP_QUEUE);
11002 sg_entry_cnt_minus_one = sg_entry_cnt - 1;
11004 scsi_cmd = scsiq->cdbptr[0];
11005 disable_syn_offset_one_fix = FALSE;
11006 if ((asc_dvc->pci_fix_asyn_xfer & scsiq->q1.target_id) &&
11007 !(asc_dvc->pci_fix_asyn_xfer_always & scsiq->q1.target_id)) {
11008 if (scsiq->q1.cntl & QC_SG_HEAD) {
11010 for (i = 0; i < sg_entry_cnt; i++) {
11012 (ADV_DCNT)le32_to_cpu(sg_head->sg_list[i].
11016 data_cnt = le32_to_cpu(scsiq->q1.data_cnt);
11018 if (data_cnt != 0UL) {
11019 if (data_cnt < 512UL) {
11020 disable_syn_offset_one_fix = TRUE;
11022 for (i = 0; i < ASC_SYN_OFFSET_ONE_DISABLE_LIST;
11025 _syn_offset_one_disable_cmd[i];
11026 if (disable_cmd == 0xFF) {
11029 if (scsi_cmd == disable_cmd) {
11030 disable_syn_offset_one_fix =
11038 if (disable_syn_offset_one_fix) {
11039 scsiq->q2.tag_code &= ~MSG_SIMPLE_TAG;
11040 scsiq->q2.tag_code |= (ASC_TAG_FLAG_DISABLE_ASYN_USE_SYN_FIX |
11041 ASC_TAG_FLAG_DISABLE_DISCONNECT);
11043 scsiq->q2.tag_code &= 0x27;
11045 if ((scsiq->q1.cntl & QC_SG_HEAD) != 0) {
11046 if (asc_dvc->bug_fix_cntl) {
11047 if (asc_dvc->bug_fix_cntl & ASC_BUG_FIX_IF_NOT_DWB) {
11048 if ((scsi_cmd == READ_6) ||
11049 (scsi_cmd == READ_10)) {
11051 (ADV_PADDR)le32_to_cpu(sg_head->
11053 [sg_entry_cnt_minus_one].
11055 (ADV_DCNT)le32_to_cpu(sg_head->
11057 [sg_entry_cnt_minus_one].
11060 (uchar)((ushort)addr & 0x0003);
11061 if ((extra_bytes != 0)
11065 ASC_TAG_FLAG_EXTRA_BYTES)
11067 scsiq->q2.tag_code |=
11068 ASC_TAG_FLAG_EXTRA_BYTES;
11069 scsiq->q1.extra_bytes =
11072 le32_to_cpu(sg_head->
11074 [sg_entry_cnt_minus_one].
11077 (ASC_DCNT) extra_bytes;
11080 [sg_entry_cnt_minus_one].
11082 cpu_to_le32(data_cnt);
11087 sg_head->entry_to_copy = sg_head->entry_cnt;
11088 #if CC_VERY_LONG_SG_LIST
11090 * Set the sg_entry_cnt to the maximum possible. The rest of
11091 * the SG elements will be copied when the RISC completes the
11092 * SG elements that fit and halts.
11094 if (sg_entry_cnt > ASC_MAX_SG_LIST) {
11095 sg_entry_cnt = ASC_MAX_SG_LIST;
11097 #endif /* CC_VERY_LONG_SG_LIST */
11098 n_q_required = AscSgListToQueue(sg_entry_cnt);
11099 if ((AscGetNumOfFreeQueue(asc_dvc, target_ix, n_q_required) >=
11100 (uint) n_q_required)
11101 || ((scsiq->q1.cntl & QC_URGENT) != 0)) {
11103 AscSendScsiQueue(asc_dvc, scsiq,
11104 n_q_required)) == 1) {
11105 asc_dvc->in_critical_cnt--;
11110 if (asc_dvc->bug_fix_cntl) {
11111 if (asc_dvc->bug_fix_cntl & ASC_BUG_FIX_IF_NOT_DWB) {
11112 if ((scsi_cmd == READ_6) ||
11113 (scsi_cmd == READ_10)) {
11115 le32_to_cpu(scsiq->q1.data_addr) +
11116 le32_to_cpu(scsiq->q1.data_cnt);
11118 (uchar)((ushort)addr & 0x0003);
11119 if ((extra_bytes != 0)
11123 ASC_TAG_FLAG_EXTRA_BYTES)
11126 le32_to_cpu(scsiq->q1.
11128 if (((ushort)data_cnt & 0x01FF)
11130 scsiq->q2.tag_code |=
11131 ASC_TAG_FLAG_EXTRA_BYTES;
11132 data_cnt -= (ASC_DCNT)
11134 scsiq->q1.data_cnt =
11137 scsiq->q1.extra_bytes =
11145 if ((AscGetNumOfFreeQueue(asc_dvc, target_ix, 1) >= 1) ||
11146 ((scsiq->q1.cntl & QC_URGENT) != 0)) {
11147 if ((sta = AscSendScsiQueue(asc_dvc, scsiq,
11148 n_q_required)) == 1) {
11149 asc_dvc->in_critical_cnt--;
11154 asc_dvc->in_critical_cnt--;
11159 * AdvExeScsiQueue() - Send a request to the RISC microcode program.
11161 * Allocate a carrier structure, point the carrier to the ADV_SCSI_REQ_Q,
11162 * add the carrier to the ICQ (Initiator Command Queue), and tickle the
11163 * RISC to notify it a new command is ready to be executed.
11165 * If 'done_status' is not set to QD_DO_RETRY, then 'error_retry' will be
11166 * set to SCSI_MAX_RETRY.
11168 * Multi-byte fields in the ASC_SCSI_REQ_Q that are used by the microcode
11169 * for DMA addresses or math operations are byte swapped to little-endian
11173 * ADV_SUCCESS(1) - The request was successfully queued.
11174 * ADV_BUSY(0) - Resource unavailable; Retry again after pending
11175 * request completes.
11176 * ADV_ERROR(-1) - Invalid ADV_SCSI_REQ_Q request structure
11179 static int AdvExeScsiQueue(ADV_DVC_VAR *asc_dvc, ADV_SCSI_REQ_Q *scsiq)
11181 AdvPortAddr iop_base;
11183 ADV_PADDR req_paddr;
11184 ADV_CARR_T *new_carrp;
11187 * The ADV_SCSI_REQ_Q 'target_id' field should never exceed ADV_MAX_TID.
11189 if (scsiq->target_id > ADV_MAX_TID) {
11190 scsiq->host_status = QHSTA_M_INVALID_DEVICE;
11191 scsiq->done_status = QD_WITH_ERROR;
11195 iop_base = asc_dvc->iop_base;
11198 * Allocate a carrier ensuring at least one carrier always
11199 * remains on the freelist and initialize fields.
11201 if ((new_carrp = asc_dvc->carr_freelist) == NULL) {
11204 asc_dvc->carr_freelist = (ADV_CARR_T *)
11205 ADV_U32_TO_VADDR(le32_to_cpu(new_carrp->next_vpa));
11206 asc_dvc->carr_pending_cnt++;
11209 * Set the carrier to be a stopper by setting 'next_vpa'
11210 * to the stopper value. The current stopper will be changed
11211 * below to point to the new stopper.
11213 new_carrp->next_vpa = cpu_to_le32(ASC_CQ_STOPPER);
11216 * Clear the ADV_SCSI_REQ_Q done flag.
11218 scsiq->a_flag &= ~ADV_SCSIQ_DONE;
11220 req_size = sizeof(ADV_SCSI_REQ_Q);
11221 req_paddr = DvcGetPhyAddr(asc_dvc, scsiq, (uchar *)scsiq,
11222 (ADV_SDCNT *)&req_size, ADV_IS_SCSIQ_FLAG);
11224 BUG_ON(req_paddr & 31);
11225 BUG_ON(req_size < sizeof(ADV_SCSI_REQ_Q));
11227 /* Wait for assertion before making little-endian */
11228 req_paddr = cpu_to_le32(req_paddr);
11230 /* Save virtual and physical address of ADV_SCSI_REQ_Q and carrier. */
11231 scsiq->scsiq_ptr = cpu_to_le32(ADV_VADDR_TO_U32(scsiq));
11232 scsiq->scsiq_rptr = req_paddr;
11234 scsiq->carr_va = cpu_to_le32(ADV_VADDR_TO_U32(asc_dvc->icq_sp));
11236 * Every ADV_CARR_T.carr_pa is byte swapped to little-endian
11237 * order during initialization.
11239 scsiq->carr_pa = asc_dvc->icq_sp->carr_pa;
11242 * Use the current stopper to send the ADV_SCSI_REQ_Q command to
11243 * the microcode. The newly allocated stopper will become the new
11246 asc_dvc->icq_sp->areq_vpa = req_paddr;
11249 * Set the 'next_vpa' pointer for the old stopper to be the
11250 * physical address of the new stopper. The RISC can only
11251 * follow physical addresses.
11253 asc_dvc->icq_sp->next_vpa = new_carrp->carr_pa;
11256 * Set the host adapter stopper pointer to point to the new carrier.
11258 asc_dvc->icq_sp = new_carrp;
11260 if (asc_dvc->chip_type == ADV_CHIP_ASC3550 ||
11261 asc_dvc->chip_type == ADV_CHIP_ASC38C0800) {
11263 * Tickle the RISC to tell it to read its Command Queue Head pointer.
11265 AdvWriteByteRegister(iop_base, IOPB_TICKLE, ADV_TICKLE_A);
11266 if (asc_dvc->chip_type == ADV_CHIP_ASC3550) {
11268 * Clear the tickle value. In the ASC-3550 the RISC flag
11269 * command 'clr_tickle_a' does not work unless the host
11270 * value is cleared.
11272 AdvWriteByteRegister(iop_base, IOPB_TICKLE,
11275 } else if (asc_dvc->chip_type == ADV_CHIP_ASC38C1600) {
11277 * Notify the RISC a carrier is ready by writing the physical
11278 * address of the new carrier stopper to the COMMA register.
11280 AdvWriteDWordRegister(iop_base, IOPDW_COMMA,
11281 le32_to_cpu(new_carrp->carr_pa));
11284 return ADV_SUCCESS;
11288 * Execute a single 'Scsi_Cmnd'.
11290 * The function 'done' is called when the request has been completed.
11294 * host - board controlling device
11295 * device - device to send command
11296 * target - target of device
11297 * lun - lun of device
11298 * cmd_len - length of SCSI CDB
11299 * cmnd - buffer for SCSI 8, 10, or 12 byte CDB
11300 * use_sg - if non-zero indicates scatter-gather request with use_sg elements
11302 * if (use_sg == 0) {
11303 * request_buffer - buffer address for request
11304 * request_bufflen - length of request buffer
11306 * request_buffer - pointer to scatterlist structure
11309 * sense_buffer - sense command buffer
11311 * result (4 bytes of an int):
11313 * 0 SCSI Status Byte Code
11314 * 1 SCSI One Byte Message Code
11315 * 2 Host Error Code
11316 * 3 Mid-Level Error Code
11318 * host driver fields:
11319 * SCp - Scsi_Pointer used for command processing status
11320 * scsi_done - used to save caller's done function
11321 * host_scribble - used for pointer to another struct scsi_cmnd
11323 * If this function returns ASC_NOERROR the request will be completed
11324 * from the interrupt handler.
11326 * If this function returns ASC_ERROR the host error code has been set,
11327 * and the called must call asc_scsi_done.
11329 * If ASC_BUSY is returned the request will be returned to the midlayer
11330 * and re-tried later.
11332 static int asc_execute_scsi_cmnd(struct scsi_cmnd *scp)
11334 asc_board_t *boardp;
11335 ASC_DVC_VAR *asc_dvc_varp;
11336 ADV_DVC_VAR *adv_dvc_varp;
11337 ADV_SCSI_REQ_Q *adv_scsiqp;
11340 ASC_DBG2(1, "asc_execute_scsi_cmnd: scp 0x%lx, done 0x%lx\n",
11341 (ulong)scp, (ulong)scp->scsi_done);
11343 boardp = ASC_BOARDP(scp->device->host);
11345 if (ASC_NARROW_BOARD(boardp)) {
11347 * Build and execute Narrow Board request.
11350 asc_dvc_varp = &boardp->dvc_var.asc_dvc_var;
11353 * Build Asc Library request structure using the
11354 * global structures 'asc_scsi_req' and 'asc_sg_head'.
11356 * If an error is returned, then the request has been
11357 * queued on the board done queue. It will be completed
11360 * asc_build_req() can not return ASC_BUSY.
11362 if (asc_build_req(boardp, scp) == ASC_ERROR) {
11363 ASC_STATS(scp->device->host, build_error);
11367 switch (ret = AscExeScsiQueue(asc_dvc_varp, &asc_scsi_q)) {
11369 ASC_STATS(scp->device->host, exe_noerror);
11371 * Increment monotonically increasing per device
11372 * successful request counter. Wrapping doesn't matter.
11374 boardp->reqcnt[scp->device->id]++;
11375 ASC_DBG(1, "asc_execute_scsi_cmnd: AscExeScsiQueue(), "
11379 ASC_STATS(scp->device->host, exe_busy);
11382 ASC_PRINT2("asc_execute_scsi_cmnd: board %d: "
11383 "AscExeScsiQueue() ASC_ERROR, err_code 0x%x\n",
11384 boardp->id, asc_dvc_varp->err_code);
11385 ASC_STATS(scp->device->host, exe_error);
11386 scp->result = HOST_BYTE(DID_ERROR);
11389 ASC_PRINT2("asc_execute_scsi_cmnd: board %d: "
11390 "AscExeScsiQueue() unknown, err_code 0x%x\n",
11391 boardp->id, asc_dvc_varp->err_code);
11392 ASC_STATS(scp->device->host, exe_unknown);
11393 scp->result = HOST_BYTE(DID_ERROR);
11398 * Build and execute Wide Board request.
11400 adv_dvc_varp = &boardp->dvc_var.adv_dvc_var;
11403 * Build and get a pointer to an Adv Library request structure.
11405 * If the request is successfully built then send it below,
11406 * otherwise return with an error.
11408 switch (adv_build_req(boardp, scp, &adv_scsiqp)) {
11410 ASC_DBG(3, "asc_execute_scsi_cmnd: adv_build_req "
11414 ASC_DBG(1, "asc_execute_scsi_cmnd: adv_build_req "
11417 * The asc_stats fields 'adv_build_noreq' and
11418 * 'adv_build_nosg' count wide board busy conditions.
11419 * They are updated in adv_build_req and
11420 * adv_get_sglist, respectively.
11425 ASC_DBG(1, "asc_execute_scsi_cmnd: adv_build_req "
11427 ASC_STATS(scp->device->host, build_error);
11431 switch (ret = AdvExeScsiQueue(adv_dvc_varp, adv_scsiqp)) {
11433 ASC_STATS(scp->device->host, exe_noerror);
11435 * Increment monotonically increasing per device
11436 * successful request counter. Wrapping doesn't matter.
11438 boardp->reqcnt[scp->device->id]++;
11439 ASC_DBG(1, "asc_execute_scsi_cmnd: AdvExeScsiQueue(), "
11443 ASC_STATS(scp->device->host, exe_busy);
11446 ASC_PRINT2("asc_execute_scsi_cmnd: board %d: "
11447 "AdvExeScsiQueue() ASC_ERROR, err_code 0x%x\n",
11448 boardp->id, adv_dvc_varp->err_code);
11449 ASC_STATS(scp->device->host, exe_error);
11450 scp->result = HOST_BYTE(DID_ERROR);
11453 ASC_PRINT2("asc_execute_scsi_cmnd: board %d: "
11454 "AdvExeScsiQueue() unknown, err_code 0x%x\n",
11455 boardp->id, adv_dvc_varp->err_code);
11456 ASC_STATS(scp->device->host, exe_unknown);
11457 scp->result = HOST_BYTE(DID_ERROR);
11462 ASC_DBG(1, "asc_execute_scsi_cmnd: end\n");
11467 * advansys_queuecommand() - interrupt-driven I/O entrypoint.
11469 * This function always returns 0. Command return status is saved
11470 * in the 'scp' result field.
11473 advansys_queuecommand(struct scsi_cmnd *scp, void (*done)(struct scsi_cmnd *))
11475 struct Scsi_Host *shost = scp->device->host;
11476 asc_board_t *boardp = ASC_BOARDP(shost);
11477 unsigned long flags;
11478 int asc_res, result = 0;
11480 ASC_STATS(shost, queuecommand);
11481 scp->scsi_done = done;
11484 * host_lock taken by mid-level prior to call, but need
11485 * to protect against own ISR
11487 spin_lock_irqsave(&boardp->lock, flags);
11488 asc_res = asc_execute_scsi_cmnd(scp);
11489 spin_unlock_irqrestore(&boardp->lock, flags);
11495 result = SCSI_MLQUEUE_HOST_BUSY;
11499 asc_scsi_done(scp);
11506 static ushort __devinit AscGetEisaChipCfg(PortAddr iop_base)
11508 PortAddr eisa_cfg_iop = (PortAddr) ASC_GET_EISA_SLOT(iop_base) |
11509 (PortAddr) (ASC_EISA_CFG_IOP_MASK);
11510 return inpw(eisa_cfg_iop);
11514 * Return the BIOS address of the adapter at the specified
11515 * I/O port and with the specified bus type.
11517 static unsigned short __devinit
11518 AscGetChipBiosAddress(PortAddr iop_base, unsigned short bus_type)
11520 unsigned short cfg_lsw;
11521 unsigned short bios_addr;
11524 * The PCI BIOS is re-located by the motherboard BIOS. Because
11525 * of this the driver can not determine where a PCI BIOS is
11526 * loaded and executes.
11528 if (bus_type & ASC_IS_PCI)
11531 if ((bus_type & ASC_IS_EISA) != 0) {
11532 cfg_lsw = AscGetEisaChipCfg(iop_base);
11534 bios_addr = ASC_BIOS_MIN_ADDR + cfg_lsw * ASC_BIOS_BANK_SIZE;
11538 cfg_lsw = AscGetChipCfgLsw(iop_base);
11541 * ISA PnP uses the top bit as the 32K BIOS flag
11543 if (bus_type == ASC_IS_ISAPNP)
11545 bios_addr = ASC_BIOS_MIN_ADDR + (cfg_lsw >> 12) * ASC_BIOS_BANK_SIZE;
11549 static uchar __devinit AscSetChipScsiID(PortAddr iop_base, uchar new_host_id)
11553 if (AscGetChipScsiID(iop_base) == new_host_id) {
11554 return (new_host_id);
11556 cfg_lsw = AscGetChipCfgLsw(iop_base);
11558 cfg_lsw |= (ushort)((new_host_id & ASC_MAX_TID) << 8);
11559 AscSetChipCfgLsw(iop_base, cfg_lsw);
11560 return (AscGetChipScsiID(iop_base));
11563 static unsigned char __devinit AscGetChipScsiCtrl(PortAddr iop_base)
11567 AscSetBank(iop_base, 1);
11568 sc = inp(iop_base + IOP_REG_SC);
11569 AscSetBank(iop_base, 0);
11573 static unsigned char __devinit
11574 AscGetChipVersion(PortAddr iop_base, unsigned short bus_type)
11576 if (bus_type & ASC_IS_EISA) {
11578 unsigned char revision;
11579 eisa_iop = (PortAddr) ASC_GET_EISA_SLOT(iop_base) |
11580 (PortAddr) ASC_EISA_REV_IOP_MASK;
11581 revision = inp(eisa_iop);
11582 return ASC_CHIP_MIN_VER_EISA - 1 + revision;
11584 return AscGetChipVerNo(iop_base);
11587 static void __devinit AscToggleIRQAct(PortAddr iop_base)
11589 AscSetChipStatus(iop_base, CIW_IRQ_ACT);
11590 AscSetChipStatus(iop_base, 0);
11594 static uchar __devinit AscGetChipIRQ(PortAddr iop_base, ushort bus_type)
11599 if ((bus_type & ASC_IS_EISA) != 0) {
11600 cfg_lsw = AscGetEisaChipCfg(iop_base);
11601 chip_irq = (uchar)(((cfg_lsw >> 8) & 0x07) + 10);
11602 if ((chip_irq == 13) || (chip_irq > 15)) {
11607 if ((bus_type & ASC_IS_VL) != 0) {
11608 cfg_lsw = AscGetChipCfgLsw(iop_base);
11609 chip_irq = (uchar)(((cfg_lsw >> 2) & 0x07));
11610 if ((chip_irq == 0) || (chip_irq == 4) || (chip_irq == 7)) {
11613 return ((uchar)(chip_irq + (ASC_MIN_IRQ_NO - 1)));
11615 cfg_lsw = AscGetChipCfgLsw(iop_base);
11616 chip_irq = (uchar)(((cfg_lsw >> 2) & 0x03));
11618 chip_irq += (uchar)2;
11619 return ((uchar)(chip_irq + ASC_MIN_IRQ_NO));
11622 static uchar __devinit
11623 AscSetChipIRQ(PortAddr iop_base, uchar irq_no, ushort bus_type)
11627 if ((bus_type & ASC_IS_VL) != 0) {
11629 if ((irq_no < ASC_MIN_IRQ_NO)
11630 || (irq_no > ASC_MAX_IRQ_NO)) {
11633 irq_no -= (uchar)((ASC_MIN_IRQ_NO - 1));
11636 cfg_lsw = (ushort)(AscGetChipCfgLsw(iop_base) & 0xFFE3);
11637 cfg_lsw |= (ushort)0x0010;
11638 AscSetChipCfgLsw(iop_base, cfg_lsw);
11639 AscToggleIRQAct(iop_base);
11640 cfg_lsw = (ushort)(AscGetChipCfgLsw(iop_base) & 0xFFE0);
11641 cfg_lsw |= (ushort)((irq_no & 0x07) << 2);
11642 AscSetChipCfgLsw(iop_base, cfg_lsw);
11643 AscToggleIRQAct(iop_base);
11644 return (AscGetChipIRQ(iop_base, bus_type));
11646 if ((bus_type & (ASC_IS_ISA)) != 0) {
11648 irq_no -= (uchar)2;
11649 irq_no -= (uchar)ASC_MIN_IRQ_NO;
11650 cfg_lsw = (ushort)(AscGetChipCfgLsw(iop_base) & 0xFFF3);
11651 cfg_lsw |= (ushort)((irq_no & 0x03) << 2);
11652 AscSetChipCfgLsw(iop_base, cfg_lsw);
11653 return (AscGetChipIRQ(iop_base, bus_type));
11659 static void __devinit AscEnableIsaDma(uchar dma_channel)
11661 if (dma_channel < 4) {
11662 outp(0x000B, (ushort)(0xC0 | dma_channel));
11663 outp(0x000A, dma_channel);
11664 } else if (dma_channel < 8) {
11665 outp(0x00D6, (ushort)(0xC0 | (dma_channel - 4)));
11666 outp(0x00D4, (ushort)(dma_channel - 4));
11670 #endif /* CONFIG_ISA */
11672 static int AscStopQueueExe(PortAddr iop_base)
11676 if (AscReadLramByte(iop_base, ASCV_STOP_CODE_B) == 0) {
11677 AscWriteLramByte(iop_base, ASCV_STOP_CODE_B,
11678 ASC_STOP_REQ_RISC_STOP);
11680 if (AscReadLramByte(iop_base, ASCV_STOP_CODE_B) &
11681 ASC_STOP_ACK_RISC_STOP) {
11685 } while (count++ < 20);
11690 static ASC_DCNT __devinit AscGetMaxDmaCount(ushort bus_type)
11692 if (bus_type & ASC_IS_ISA)
11693 return ASC_MAX_ISA_DMA_COUNT;
11694 else if (bus_type & (ASC_IS_EISA | ASC_IS_VL))
11695 return ASC_MAX_VL_DMA_COUNT;
11696 return ASC_MAX_PCI_DMA_COUNT;
11700 static ushort __devinit AscGetIsaDmaChannel(PortAddr iop_base)
11704 channel = AscGetChipCfgLsw(iop_base) & 0x0003;
11705 if (channel == 0x03)
11707 else if (channel == 0x00)
11709 return (channel + 4);
11712 static ushort __devinit AscSetIsaDmaChannel(PortAddr iop_base, ushort dma_channel)
11717 if ((dma_channel >= 5) && (dma_channel <= 7)) {
11718 if (dma_channel == 7)
11721 value = dma_channel - 4;
11722 cfg_lsw = AscGetChipCfgLsw(iop_base) & 0xFFFC;
11724 AscSetChipCfgLsw(iop_base, cfg_lsw);
11725 return (AscGetIsaDmaChannel(iop_base));
11730 static uchar __devinit AscGetIsaDmaSpeed(PortAddr iop_base)
11734 AscSetBank(iop_base, 1);
11735 speed_value = AscReadChipDmaSpeed(iop_base);
11736 speed_value &= 0x07;
11737 AscSetBank(iop_base, 0);
11738 return speed_value;
11741 static uchar __devinit AscSetIsaDmaSpeed(PortAddr iop_base, uchar speed_value)
11743 speed_value &= 0x07;
11744 AscSetBank(iop_base, 1);
11745 AscWriteChipDmaSpeed(iop_base, speed_value);
11746 AscSetBank(iop_base, 0);
11747 return AscGetIsaDmaSpeed(iop_base);
11749 #endif /* CONFIG_ISA */
11751 static ushort __devinit AscInitAscDvcVar(ASC_DVC_VAR *asc_dvc)
11756 uchar chip_version;
11758 iop_base = asc_dvc->iop_base;
11760 asc_dvc->err_code = 0;
11761 if ((asc_dvc->bus_type &
11762 (ASC_IS_ISA | ASC_IS_PCI | ASC_IS_EISA | ASC_IS_VL)) == 0) {
11763 asc_dvc->err_code |= ASC_IERR_NO_BUS_TYPE;
11765 AscSetChipControl(iop_base, CC_HALT);
11766 AscSetChipStatus(iop_base, 0);
11767 asc_dvc->bug_fix_cntl = 0;
11768 asc_dvc->pci_fix_asyn_xfer = 0;
11769 asc_dvc->pci_fix_asyn_xfer_always = 0;
11770 /* asc_dvc->init_state initalized in AscInitGetConfig(). */
11771 asc_dvc->sdtr_done = 0;
11772 asc_dvc->cur_total_qng = 0;
11773 asc_dvc->is_in_int = 0;
11774 asc_dvc->in_critical_cnt = 0;
11775 asc_dvc->last_q_shortage = 0;
11776 asc_dvc->use_tagged_qng = 0;
11777 asc_dvc->no_scam = 0;
11778 asc_dvc->unit_not_ready = 0;
11779 asc_dvc->queue_full_or_busy = 0;
11780 asc_dvc->redo_scam = 0;
11782 asc_dvc->host_init_sdtr_index = 0;
11783 asc_dvc->cfg->can_tagged_qng = 0;
11784 asc_dvc->cfg->cmd_qng_enabled = 0;
11785 asc_dvc->dvc_cntl = ASC_DEF_DVC_CNTL;
11786 asc_dvc->init_sdtr = 0;
11787 asc_dvc->max_total_qng = ASC_DEF_MAX_TOTAL_QNG;
11788 asc_dvc->scsi_reset_wait = 3;
11789 asc_dvc->start_motor = ASC_SCSI_WIDTH_BIT_SET;
11790 asc_dvc->max_dma_count = AscGetMaxDmaCount(asc_dvc->bus_type);
11791 asc_dvc->cfg->sdtr_enable = ASC_SCSI_WIDTH_BIT_SET;
11792 asc_dvc->cfg->disc_enable = ASC_SCSI_WIDTH_BIT_SET;
11793 asc_dvc->cfg->chip_scsi_id = ASC_DEF_CHIP_SCSI_ID;
11794 asc_dvc->cfg->lib_serial_no = ASC_LIB_SERIAL_NUMBER;
11795 asc_dvc->cfg->lib_version = (ASC_LIB_VERSION_MAJOR << 8) |
11796 ASC_LIB_VERSION_MINOR;
11797 chip_version = AscGetChipVersion(iop_base, asc_dvc->bus_type);
11798 asc_dvc->cfg->chip_version = chip_version;
11799 asc_dvc->sdtr_period_tbl[0] = SYN_XFER_NS_0;
11800 asc_dvc->sdtr_period_tbl[1] = SYN_XFER_NS_1;
11801 asc_dvc->sdtr_period_tbl[2] = SYN_XFER_NS_2;
11802 asc_dvc->sdtr_period_tbl[3] = SYN_XFER_NS_3;
11803 asc_dvc->sdtr_period_tbl[4] = SYN_XFER_NS_4;
11804 asc_dvc->sdtr_period_tbl[5] = SYN_XFER_NS_5;
11805 asc_dvc->sdtr_period_tbl[6] = SYN_XFER_NS_6;
11806 asc_dvc->sdtr_period_tbl[7] = SYN_XFER_NS_7;
11807 asc_dvc->max_sdtr_index = 7;
11808 if ((asc_dvc->bus_type & ASC_IS_PCI) &&
11809 (chip_version >= ASC_CHIP_VER_PCI_ULTRA_3150)) {
11810 asc_dvc->bus_type = ASC_IS_PCI_ULTRA;
11811 asc_dvc->sdtr_period_tbl[0] = SYN_ULTRA_XFER_NS_0;
11812 asc_dvc->sdtr_period_tbl[1] = SYN_ULTRA_XFER_NS_1;
11813 asc_dvc->sdtr_period_tbl[2] = SYN_ULTRA_XFER_NS_2;
11814 asc_dvc->sdtr_period_tbl[3] = SYN_ULTRA_XFER_NS_3;
11815 asc_dvc->sdtr_period_tbl[4] = SYN_ULTRA_XFER_NS_4;
11816 asc_dvc->sdtr_period_tbl[5] = SYN_ULTRA_XFER_NS_5;
11817 asc_dvc->sdtr_period_tbl[6] = SYN_ULTRA_XFER_NS_6;
11818 asc_dvc->sdtr_period_tbl[7] = SYN_ULTRA_XFER_NS_7;
11819 asc_dvc->sdtr_period_tbl[8] = SYN_ULTRA_XFER_NS_8;
11820 asc_dvc->sdtr_period_tbl[9] = SYN_ULTRA_XFER_NS_9;
11821 asc_dvc->sdtr_period_tbl[10] = SYN_ULTRA_XFER_NS_10;
11822 asc_dvc->sdtr_period_tbl[11] = SYN_ULTRA_XFER_NS_11;
11823 asc_dvc->sdtr_period_tbl[12] = SYN_ULTRA_XFER_NS_12;
11824 asc_dvc->sdtr_period_tbl[13] = SYN_ULTRA_XFER_NS_13;
11825 asc_dvc->sdtr_period_tbl[14] = SYN_ULTRA_XFER_NS_14;
11826 asc_dvc->sdtr_period_tbl[15] = SYN_ULTRA_XFER_NS_15;
11827 asc_dvc->max_sdtr_index = 15;
11828 if (chip_version == ASC_CHIP_VER_PCI_ULTRA_3150) {
11829 AscSetExtraControl(iop_base,
11830 (SEC_ACTIVE_NEGATE | SEC_SLEW_RATE));
11831 } else if (chip_version >= ASC_CHIP_VER_PCI_ULTRA_3050) {
11832 AscSetExtraControl(iop_base,
11833 (SEC_ACTIVE_NEGATE |
11834 SEC_ENABLE_FILTER));
11837 if (asc_dvc->bus_type == ASC_IS_PCI) {
11838 AscSetExtraControl(iop_base,
11839 (SEC_ACTIVE_NEGATE | SEC_SLEW_RATE));
11842 asc_dvc->cfg->isa_dma_speed = ASC_DEF_ISA_DMA_SPEED;
11844 if ((asc_dvc->bus_type & ASC_IS_ISA) != 0) {
11845 if (chip_version >= ASC_CHIP_MIN_VER_ISA_PNP) {
11846 AscSetChipIFC(iop_base, IFC_INIT_DEFAULT);
11847 asc_dvc->bus_type = ASC_IS_ISAPNP;
11849 asc_dvc->cfg->isa_dma_channel =
11850 (uchar)AscGetIsaDmaChannel(iop_base);
11852 #endif /* CONFIG_ISA */
11853 for (i = 0; i <= ASC_MAX_TID; i++) {
11854 asc_dvc->cur_dvc_qng[i] = 0;
11855 asc_dvc->max_dvc_qng[i] = ASC_MAX_SCSI1_QNG;
11856 asc_dvc->scsiq_busy_head[i] = (ASC_SCSI_Q *)0L;
11857 asc_dvc->scsiq_busy_tail[i] = (ASC_SCSI_Q *)0L;
11858 asc_dvc->cfg->max_tag_qng[i] = ASC_MAX_INRAM_TAG_QNG;
11863 static int __devinit AscWriteEEPCmdReg(PortAddr iop_base, uchar cmd_reg)
11867 for (retry = 0; retry < ASC_EEP_MAX_RETRY; retry++) {
11868 unsigned char read_back;
11869 AscSetChipEEPCmd(iop_base, cmd_reg);
11871 read_back = AscGetChipEEPCmd(iop_base);
11872 if (read_back == cmd_reg)
11878 static void __devinit AscWaitEEPRead(void)
11883 static ushort __devinit AscReadEEPWord(PortAddr iop_base, uchar addr)
11888 AscWriteEEPCmdReg(iop_base, ASC_EEP_CMD_WRITE_DISABLE);
11890 cmd_reg = addr | ASC_EEP_CMD_READ;
11891 AscWriteEEPCmdReg(iop_base, cmd_reg);
11893 read_wval = AscGetChipEEPData(iop_base);
11898 static ushort __devinit
11899 AscGetEEPConfig(PortAddr iop_base, ASCEEP_CONFIG *cfg_buf, ushort bus_type)
11906 int uchar_end_in_config = ASC_EEP_MAX_DVC_ADDR - 2;
11909 wbuf = (ushort *)cfg_buf;
11911 /* Read two config words; Byte-swapping done by AscReadEEPWord(). */
11912 for (s_addr = 0; s_addr < 2; s_addr++, wbuf++) {
11913 *wbuf = AscReadEEPWord(iop_base, (uchar)s_addr);
11916 if (bus_type & ASC_IS_VL) {
11917 cfg_beg = ASC_EEP_DVC_CFG_BEG_VL;
11918 cfg_end = ASC_EEP_MAX_DVC_ADDR_VL;
11920 cfg_beg = ASC_EEP_DVC_CFG_BEG;
11921 cfg_end = ASC_EEP_MAX_DVC_ADDR;
11923 for (s_addr = cfg_beg; s_addr <= (cfg_end - 1); s_addr++, wbuf++) {
11924 wval = AscReadEEPWord(iop_base, (uchar)s_addr);
11925 if (s_addr <= uchar_end_in_config) {
11927 * Swap all char fields - must unswap bytes already swapped
11928 * by AscReadEEPWord().
11930 *wbuf = le16_to_cpu(wval);
11932 /* Don't swap word field at the end - cntl field. */
11935 sum += wval; /* Checksum treats all EEPROM data as words. */
11938 * Read the checksum word which will be compared against 'sum'
11939 * by the caller. Word field already swapped.
11941 *wbuf = AscReadEEPWord(iop_base, (uchar)s_addr);
11945 static int __devinit AscTestExternalLram(ASC_DVC_VAR *asc_dvc)
11952 iop_base = asc_dvc->iop_base;
11954 q_addr = ASC_QNO_TO_QADDR(241);
11955 saved_word = AscReadLramWord(iop_base, q_addr);
11956 AscSetChipLramAddr(iop_base, q_addr);
11957 AscSetChipLramData(iop_base, 0x55AA);
11959 AscSetChipLramAddr(iop_base, q_addr);
11960 if (AscGetChipLramData(iop_base) == 0x55AA) {
11962 AscWriteLramWord(iop_base, q_addr, saved_word);
11967 static void __devinit AscWaitEEPWrite(void)
11973 static int __devinit AscWriteEEPDataReg(PortAddr iop_base, ushort data_reg)
11980 AscSetChipEEPData(iop_base, data_reg);
11982 read_back = AscGetChipEEPData(iop_base);
11983 if (read_back == data_reg) {
11986 if (retry++ > ASC_EEP_MAX_RETRY) {
11992 static ushort __devinit
11993 AscWriteEEPWord(PortAddr iop_base, uchar addr, ushort word_val)
11997 read_wval = AscReadEEPWord(iop_base, addr);
11998 if (read_wval != word_val) {
11999 AscWriteEEPCmdReg(iop_base, ASC_EEP_CMD_WRITE_ABLE);
12001 AscWriteEEPDataReg(iop_base, word_val);
12003 AscWriteEEPCmdReg(iop_base,
12004 (uchar)((uchar)ASC_EEP_CMD_WRITE | addr));
12006 AscWriteEEPCmdReg(iop_base, ASC_EEP_CMD_WRITE_DISABLE);
12008 return (AscReadEEPWord(iop_base, addr));
12010 return (read_wval);
12013 static int __devinit
12014 AscSetEEPConfigOnce(PortAddr iop_base, ASCEEP_CONFIG *cfg_buf, ushort bus_type)
12023 int uchar_end_in_config = ASC_EEP_MAX_DVC_ADDR - 2;
12025 wbuf = (ushort *)cfg_buf;
12028 /* Write two config words; AscWriteEEPWord() will swap bytes. */
12029 for (s_addr = 0; s_addr < 2; s_addr++, wbuf++) {
12031 if (*wbuf != AscWriteEEPWord(iop_base, (uchar)s_addr, *wbuf)) {
12035 if (bus_type & ASC_IS_VL) {
12036 cfg_beg = ASC_EEP_DVC_CFG_BEG_VL;
12037 cfg_end = ASC_EEP_MAX_DVC_ADDR_VL;
12039 cfg_beg = ASC_EEP_DVC_CFG_BEG;
12040 cfg_end = ASC_EEP_MAX_DVC_ADDR;
12042 for (s_addr = cfg_beg; s_addr <= (cfg_end - 1); s_addr++, wbuf++) {
12043 if (s_addr <= uchar_end_in_config) {
12045 * This is a char field. Swap char fields before they are
12046 * swapped again by AscWriteEEPWord().
12048 word = cpu_to_le16(*wbuf);
12050 AscWriteEEPWord(iop_base, (uchar)s_addr, word)) {
12054 /* Don't swap word field at the end - cntl field. */
12056 AscWriteEEPWord(iop_base, (uchar)s_addr, *wbuf)) {
12060 sum += *wbuf; /* Checksum calculated from word values. */
12062 /* Write checksum word. It will be swapped by AscWriteEEPWord(). */
12064 if (sum != AscWriteEEPWord(iop_base, (uchar)s_addr, sum)) {
12068 /* Read EEPROM back again. */
12069 wbuf = (ushort *)cfg_buf;
12071 * Read two config words; Byte-swapping done by AscReadEEPWord().
12073 for (s_addr = 0; s_addr < 2; s_addr++, wbuf++) {
12074 if (*wbuf != AscReadEEPWord(iop_base, (uchar)s_addr)) {
12078 if (bus_type & ASC_IS_VL) {
12079 cfg_beg = ASC_EEP_DVC_CFG_BEG_VL;
12080 cfg_end = ASC_EEP_MAX_DVC_ADDR_VL;
12082 cfg_beg = ASC_EEP_DVC_CFG_BEG;
12083 cfg_end = ASC_EEP_MAX_DVC_ADDR;
12085 for (s_addr = cfg_beg; s_addr <= (cfg_end - 1); s_addr++, wbuf++) {
12086 if (s_addr <= uchar_end_in_config) {
12088 * Swap all char fields. Must unswap bytes already swapped
12089 * by AscReadEEPWord().
12092 le16_to_cpu(AscReadEEPWord
12093 (iop_base, (uchar)s_addr));
12095 /* Don't swap word field at the end - cntl field. */
12096 word = AscReadEEPWord(iop_base, (uchar)s_addr);
12098 if (*wbuf != word) {
12102 /* Read checksum; Byte swapping not needed. */
12103 if (AscReadEEPWord(iop_base, (uchar)s_addr) != sum) {
12109 static int __devinit
12110 AscSetEEPConfig(PortAddr iop_base, ASCEEP_CONFIG *cfg_buf, ushort bus_type)
12117 if ((n_error = AscSetEEPConfigOnce(iop_base, cfg_buf,
12121 if (++retry > ASC_EEP_MAX_RETRY) {
12128 static ushort __devinit AscInitFromEEP(ASC_DVC_VAR *asc_dvc)
12130 ASCEEP_CONFIG eep_config_buf;
12131 ASCEEP_CONFIG *eep_config;
12135 ushort cfg_msw, cfg_lsw;
12139 iop_base = asc_dvc->iop_base;
12141 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0x00FE);
12142 AscStopQueueExe(iop_base);
12143 if ((AscStopChip(iop_base) == FALSE) ||
12144 (AscGetChipScsiCtrl(iop_base) != 0)) {
12145 asc_dvc->init_state |= ASC_INIT_RESET_SCSI_DONE;
12146 AscResetChipAndScsiBus(asc_dvc);
12147 mdelay(asc_dvc->scsi_reset_wait * 1000); /* XXX: msleep? */
12149 if (AscIsChipHalted(iop_base) == FALSE) {
12150 asc_dvc->err_code |= ASC_IERR_START_STOP_CHIP;
12151 return (warn_code);
12153 AscSetPCAddr(iop_base, ASC_MCODE_START_ADDR);
12154 if (AscGetPCAddr(iop_base) != ASC_MCODE_START_ADDR) {
12155 asc_dvc->err_code |= ASC_IERR_SET_PC_ADDR;
12156 return (warn_code);
12158 eep_config = (ASCEEP_CONFIG *)&eep_config_buf;
12159 cfg_msw = AscGetChipCfgMsw(iop_base);
12160 cfg_lsw = AscGetChipCfgLsw(iop_base);
12161 if ((cfg_msw & ASC_CFG_MSW_CLR_MASK) != 0) {
12162 cfg_msw &= ~ASC_CFG_MSW_CLR_MASK;
12163 warn_code |= ASC_WARN_CFG_MSW_RECOVER;
12164 AscSetChipCfgMsw(iop_base, cfg_msw);
12166 chksum = AscGetEEPConfig(iop_base, eep_config, asc_dvc->bus_type);
12167 ASC_DBG1(1, "AscInitFromEEP: chksum 0x%x\n", chksum);
12171 if (AscGetChipStatus(iop_base) & CSW_AUTO_CONFIG) {
12172 warn_code |= ASC_WARN_AUTO_CONFIG;
12173 if (asc_dvc->cfg->chip_version == 3) {
12174 if (eep_config->cfg_lsw != cfg_lsw) {
12175 warn_code |= ASC_WARN_EEPROM_RECOVER;
12176 eep_config->cfg_lsw =
12177 AscGetChipCfgLsw(iop_base);
12179 if (eep_config->cfg_msw != cfg_msw) {
12180 warn_code |= ASC_WARN_EEPROM_RECOVER;
12181 eep_config->cfg_msw =
12182 AscGetChipCfgMsw(iop_base);
12186 eep_config->cfg_msw &= ~ASC_CFG_MSW_CLR_MASK;
12187 eep_config->cfg_lsw |= ASC_CFG0_HOST_INT_ON;
12188 ASC_DBG1(1, "AscInitFromEEP: eep_config->chksum 0x%x\n",
12189 eep_config->chksum);
12190 if (chksum != eep_config->chksum) {
12191 if (AscGetChipVersion(iop_base, asc_dvc->bus_type) ==
12192 ASC_CHIP_VER_PCI_ULTRA_3050) {
12194 "AscInitFromEEP: chksum error ignored; EEPROM-less board\n");
12195 eep_config->init_sdtr = 0xFF;
12196 eep_config->disc_enable = 0xFF;
12197 eep_config->start_motor = 0xFF;
12198 eep_config->use_cmd_qng = 0;
12199 eep_config->max_total_qng = 0xF0;
12200 eep_config->max_tag_qng = 0x20;
12201 eep_config->cntl = 0xBFFF;
12202 ASC_EEP_SET_CHIP_ID(eep_config, 7);
12203 eep_config->no_scam = 0;
12204 eep_config->adapter_info[0] = 0;
12205 eep_config->adapter_info[1] = 0;
12206 eep_config->adapter_info[2] = 0;
12207 eep_config->adapter_info[3] = 0;
12208 eep_config->adapter_info[4] = 0;
12209 /* Indicate EEPROM-less board. */
12210 eep_config->adapter_info[5] = 0xBB;
12213 ("AscInitFromEEP: EEPROM checksum error; Will try to re-write EEPROM.\n");
12215 warn_code |= ASC_WARN_EEPROM_CHKSUM;
12218 asc_dvc->cfg->sdtr_enable = eep_config->init_sdtr;
12219 asc_dvc->cfg->disc_enable = eep_config->disc_enable;
12220 asc_dvc->cfg->cmd_qng_enabled = eep_config->use_cmd_qng;
12221 asc_dvc->cfg->isa_dma_speed = ASC_EEP_GET_DMA_SPD(eep_config);
12222 asc_dvc->start_motor = eep_config->start_motor;
12223 asc_dvc->dvc_cntl = eep_config->cntl;
12224 asc_dvc->no_scam = eep_config->no_scam;
12225 asc_dvc->cfg->adapter_info[0] = eep_config->adapter_info[0];
12226 asc_dvc->cfg->adapter_info[1] = eep_config->adapter_info[1];
12227 asc_dvc->cfg->adapter_info[2] = eep_config->adapter_info[2];
12228 asc_dvc->cfg->adapter_info[3] = eep_config->adapter_info[3];
12229 asc_dvc->cfg->adapter_info[4] = eep_config->adapter_info[4];
12230 asc_dvc->cfg->adapter_info[5] = eep_config->adapter_info[5];
12231 if (!AscTestExternalLram(asc_dvc)) {
12232 if (((asc_dvc->bus_type & ASC_IS_PCI_ULTRA) ==
12233 ASC_IS_PCI_ULTRA)) {
12234 eep_config->max_total_qng =
12235 ASC_MAX_PCI_ULTRA_INRAM_TOTAL_QNG;
12236 eep_config->max_tag_qng =
12237 ASC_MAX_PCI_ULTRA_INRAM_TAG_QNG;
12239 eep_config->cfg_msw |= 0x0800;
12241 AscSetChipCfgMsw(iop_base, cfg_msw);
12242 eep_config->max_total_qng = ASC_MAX_PCI_INRAM_TOTAL_QNG;
12243 eep_config->max_tag_qng = ASC_MAX_INRAM_TAG_QNG;
12247 if (eep_config->max_total_qng < ASC_MIN_TOTAL_QNG) {
12248 eep_config->max_total_qng = ASC_MIN_TOTAL_QNG;
12250 if (eep_config->max_total_qng > ASC_MAX_TOTAL_QNG) {
12251 eep_config->max_total_qng = ASC_MAX_TOTAL_QNG;
12253 if (eep_config->max_tag_qng > eep_config->max_total_qng) {
12254 eep_config->max_tag_qng = eep_config->max_total_qng;
12256 if (eep_config->max_tag_qng < ASC_MIN_TAG_Q_PER_DVC) {
12257 eep_config->max_tag_qng = ASC_MIN_TAG_Q_PER_DVC;
12259 asc_dvc->max_total_qng = eep_config->max_total_qng;
12260 if ((eep_config->use_cmd_qng & eep_config->disc_enable) !=
12261 eep_config->use_cmd_qng) {
12262 eep_config->disc_enable = eep_config->use_cmd_qng;
12263 warn_code |= ASC_WARN_CMD_QNG_CONFLICT;
12265 if (asc_dvc->bus_type & (ASC_IS_ISA | ASC_IS_VL | ASC_IS_EISA)) {
12266 asc_dvc->irq_no = AscGetChipIRQ(iop_base, asc_dvc->bus_type);
12268 ASC_EEP_SET_CHIP_ID(eep_config,
12269 ASC_EEP_GET_CHIP_ID(eep_config) & ASC_MAX_TID);
12270 asc_dvc->cfg->chip_scsi_id = ASC_EEP_GET_CHIP_ID(eep_config);
12271 if (((asc_dvc->bus_type & ASC_IS_PCI_ULTRA) == ASC_IS_PCI_ULTRA) &&
12272 !(asc_dvc->dvc_cntl & ASC_CNTL_SDTR_ENABLE_ULTRA)) {
12273 asc_dvc->host_init_sdtr_index = ASC_SDTR_ULTRA_PCI_10MB_INDEX;
12276 for (i = 0; i <= ASC_MAX_TID; i++) {
12277 asc_dvc->dos_int13_table[i] = eep_config->dos_int13_table[i];
12278 asc_dvc->cfg->max_tag_qng[i] = eep_config->max_tag_qng;
12279 asc_dvc->cfg->sdtr_period_offset[i] =
12280 (uchar)(ASC_DEF_SDTR_OFFSET |
12281 (asc_dvc->host_init_sdtr_index << 4));
12283 eep_config->cfg_msw = AscGetChipCfgMsw(iop_base);
12285 if ((i = AscSetEEPConfig(iop_base, eep_config,
12286 asc_dvc->bus_type)) != 0) {
12288 ("AscInitFromEEP: Failed to re-write EEPROM with %d errors.\n",
12292 ("AscInitFromEEP: Successfully re-wrote EEPROM.\n");
12295 return (warn_code);
12298 static int __devinit AscInitGetConfig(asc_board_t *boardp)
12300 ASC_DVC_VAR *asc_dvc = &boardp->dvc_var.asc_dvc_var;
12301 unsigned short warn_code = 0;
12303 asc_dvc->init_state = ASC_INIT_STATE_BEG_GET_CFG;
12304 if (asc_dvc->err_code != 0)
12305 return asc_dvc->err_code;
12307 if (AscFindSignature(asc_dvc->iop_base)) {
12308 warn_code |= AscInitAscDvcVar(asc_dvc);
12309 warn_code |= AscInitFromEEP(asc_dvc);
12310 asc_dvc->init_state |= ASC_INIT_STATE_END_GET_CFG;
12311 if (asc_dvc->scsi_reset_wait > ASC_MAX_SCSI_RESET_WAIT)
12312 asc_dvc->scsi_reset_wait = ASC_MAX_SCSI_RESET_WAIT;
12314 asc_dvc->err_code = ASC_IERR_BAD_SIGNATURE;
12317 switch (warn_code) {
12318 case 0: /* No error */
12320 case ASC_WARN_IO_PORT_ROTATE:
12321 ASC_PRINT1("AscInitGetConfig: board %d: I/O port address "
12322 "modified\n", boardp->id);
12324 case ASC_WARN_AUTO_CONFIG:
12325 ASC_PRINT1("AscInitGetConfig: board %d: I/O port increment "
12326 "switch enabled\n", boardp->id);
12328 case ASC_WARN_EEPROM_CHKSUM:
12329 ASC_PRINT1("AscInitGetConfig: board %d: EEPROM checksum "
12330 "error\n", boardp->id);
12332 case ASC_WARN_IRQ_MODIFIED:
12333 ASC_PRINT1("AscInitGetConfig: board %d: IRQ modified\n",
12336 case ASC_WARN_CMD_QNG_CONFLICT:
12337 ASC_PRINT1("AscInitGetConfig: board %d: tag queuing enabled "
12338 "w/o disconnects\n", boardp->id);
12341 ASC_PRINT2("AscInitGetConfig: board %d: unknown warning: "
12342 "0x%x\n", boardp->id, warn_code);
12346 if (asc_dvc->err_code != 0) {
12347 ASC_PRINT3("AscInitGetConfig: board %d error: init_state 0x%x, "
12348 "err_code 0x%x\n", boardp->id, asc_dvc->init_state,
12349 asc_dvc->err_code);
12352 return asc_dvc->err_code;
12355 static int __devinit AscInitSetConfig(struct pci_dev *pdev, asc_board_t *boardp)
12357 ASC_DVC_VAR *asc_dvc = &boardp->dvc_var.asc_dvc_var;
12358 PortAddr iop_base = asc_dvc->iop_base;
12359 unsigned short cfg_msw;
12360 unsigned short warn_code = 0;
12362 asc_dvc->init_state |= ASC_INIT_STATE_BEG_SET_CFG;
12363 if (asc_dvc->err_code != 0)
12364 return asc_dvc->err_code;
12365 if (!AscFindSignature(asc_dvc->iop_base)) {
12366 asc_dvc->err_code = ASC_IERR_BAD_SIGNATURE;
12367 return asc_dvc->err_code;
12370 cfg_msw = AscGetChipCfgMsw(iop_base);
12371 if ((cfg_msw & ASC_CFG_MSW_CLR_MASK) != 0) {
12372 cfg_msw &= ~ASC_CFG_MSW_CLR_MASK;
12373 warn_code |= ASC_WARN_CFG_MSW_RECOVER;
12374 AscSetChipCfgMsw(iop_base, cfg_msw);
12376 if ((asc_dvc->cfg->cmd_qng_enabled & asc_dvc->cfg->disc_enable) !=
12377 asc_dvc->cfg->cmd_qng_enabled) {
12378 asc_dvc->cfg->disc_enable = asc_dvc->cfg->cmd_qng_enabled;
12379 warn_code |= ASC_WARN_CMD_QNG_CONFLICT;
12381 if (AscGetChipStatus(iop_base) & CSW_AUTO_CONFIG) {
12382 warn_code |= ASC_WARN_AUTO_CONFIG;
12384 if ((asc_dvc->bus_type & (ASC_IS_ISA | ASC_IS_VL)) != 0) {
12385 if (AscSetChipIRQ(iop_base, asc_dvc->irq_no, asc_dvc->bus_type)
12386 != asc_dvc->irq_no) {
12387 asc_dvc->err_code |= ASC_IERR_SET_IRQ_NO;
12391 if (asc_dvc->bus_type & ASC_IS_PCI) {
12393 AscSetChipCfgMsw(iop_base, cfg_msw);
12394 if ((asc_dvc->bus_type & ASC_IS_PCI_ULTRA) == ASC_IS_PCI_ULTRA) {
12396 if ((pdev->device == PCI_DEVICE_ID_ASP_1200A) ||
12397 (pdev->device == PCI_DEVICE_ID_ASP_ABP940)) {
12398 asc_dvc->bug_fix_cntl |= ASC_BUG_FIX_IF_NOT_DWB;
12399 asc_dvc->bug_fix_cntl |=
12400 ASC_BUG_FIX_ASYN_USE_SYN;
12404 #endif /* CONFIG_PCI */
12405 if (asc_dvc->bus_type == ASC_IS_ISAPNP) {
12406 if (AscGetChipVersion(iop_base, asc_dvc->bus_type)
12407 == ASC_CHIP_VER_ASYN_BUG) {
12408 asc_dvc->bug_fix_cntl |= ASC_BUG_FIX_ASYN_USE_SYN;
12411 if (AscSetChipScsiID(iop_base, asc_dvc->cfg->chip_scsi_id) !=
12412 asc_dvc->cfg->chip_scsi_id) {
12413 asc_dvc->err_code |= ASC_IERR_SET_SCSI_ID;
12416 if (asc_dvc->bus_type & ASC_IS_ISA) {
12417 AscSetIsaDmaChannel(iop_base, asc_dvc->cfg->isa_dma_channel);
12418 AscSetIsaDmaSpeed(iop_base, asc_dvc->cfg->isa_dma_speed);
12420 #endif /* CONFIG_ISA */
12422 asc_dvc->init_state |= ASC_INIT_STATE_END_SET_CFG;
12424 switch (warn_code) {
12425 case 0: /* No error. */
12427 case ASC_WARN_IO_PORT_ROTATE:
12428 ASC_PRINT1("AscInitSetConfig: board %d: I/O port address "
12429 "modified\n", boardp->id);
12431 case ASC_WARN_AUTO_CONFIG:
12432 ASC_PRINT1("AscInitSetConfig: board %d: I/O port increment "
12433 "switch enabled\n", boardp->id);
12435 case ASC_WARN_EEPROM_CHKSUM:
12436 ASC_PRINT1("AscInitSetConfig: board %d: EEPROM checksum "
12437 "error\n", boardp->id);
12439 case ASC_WARN_IRQ_MODIFIED:
12440 ASC_PRINT1("AscInitSetConfig: board %d: IRQ modified\n",
12443 case ASC_WARN_CMD_QNG_CONFLICT:
12444 ASC_PRINT1("AscInitSetConfig: board %d: tag queuing w/o "
12449 ASC_PRINT2("AscInitSetConfig: board %d: unknown warning: "
12450 "0x%x\n", boardp->id, warn_code);
12454 if (asc_dvc->err_code != 0) {
12455 ASC_PRINT3("AscInitSetConfig: board %d error: init_state 0x%x, "
12456 "err_code 0x%x\n", boardp->id, asc_dvc->init_state,
12457 asc_dvc->err_code);
12460 return asc_dvc->err_code;
12464 * EEPROM Configuration.
12466 * All drivers should use this structure to set the default EEPROM
12467 * configuration. The BIOS now uses this structure when it is built.
12468 * Additional structure information can be found in a_condor.h where
12469 * the structure is defined.
12471 * The *_Field_IsChar structs are needed to correct for endianness.
12472 * These values are read from the board 16 bits at a time directly
12473 * into the structs. Because some fields are char, the values will be
12474 * in the wrong order. The *_Field_IsChar tells when to flip the
12475 * bytes. Data read and written to PCI memory is automatically swapped
12476 * on big-endian platforms so char fields read as words are actually being
12477 * unswapped on big-endian platforms.
12479 static ADVEEP_3550_CONFIG Default_3550_EEPROM_Config __devinitdata = {
12480 ADV_EEPROM_BIOS_ENABLE, /* cfg_lsw */
12481 0x0000, /* cfg_msw */
12482 0xFFFF, /* disc_enable */
12483 0xFFFF, /* wdtr_able */
12484 0xFFFF, /* sdtr_able */
12485 0xFFFF, /* start_motor */
12486 0xFFFF, /* tagqng_able */
12487 0xFFFF, /* bios_scan */
12488 0, /* scam_tolerant */
12489 7, /* adapter_scsi_id */
12490 0, /* bios_boot_delay */
12491 3, /* scsi_reset_delay */
12492 0, /* bios_id_lun */
12493 0, /* termination */
12495 0xFFE7, /* bios_ctrl */
12496 0xFFFF, /* ultra_able */
12498 ASC_DEF_MAX_HOST_QNG, /* max_host_qng */
12499 ASC_DEF_MAX_DVC_QNG, /* max_dvc_qng */
12502 0, /* serial_number_word1 */
12503 0, /* serial_number_word2 */
12504 0, /* serial_number_word3 */
12506 {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
12507 , /* oem_name[16] */
12508 0, /* dvc_err_code */
12509 0, /* adv_err_code */
12510 0, /* adv_err_addr */
12511 0, /* saved_dvc_err_code */
12512 0, /* saved_adv_err_code */
12513 0, /* saved_adv_err_addr */
12517 static ADVEEP_3550_CONFIG ADVEEP_3550_Config_Field_IsChar __devinitdata = {
12520 0, /* -disc_enable */
12523 0, /* start_motor */
12524 0, /* tagqng_able */
12526 0, /* scam_tolerant */
12527 1, /* adapter_scsi_id */
12528 1, /* bios_boot_delay */
12529 1, /* scsi_reset_delay */
12530 1, /* bios_id_lun */
12531 1, /* termination */
12534 0, /* ultra_able */
12536 1, /* max_host_qng */
12537 1, /* max_dvc_qng */
12540 0, /* serial_number_word1 */
12541 0, /* serial_number_word2 */
12542 0, /* serial_number_word3 */
12544 {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1}
12545 , /* oem_name[16] */
12546 0, /* dvc_err_code */
12547 0, /* adv_err_code */
12548 0, /* adv_err_addr */
12549 0, /* saved_dvc_err_code */
12550 0, /* saved_adv_err_code */
12551 0, /* saved_adv_err_addr */
12555 static ADVEEP_38C0800_CONFIG Default_38C0800_EEPROM_Config __devinitdata = {
12556 ADV_EEPROM_BIOS_ENABLE, /* 00 cfg_lsw */
12557 0x0000, /* 01 cfg_msw */
12558 0xFFFF, /* 02 disc_enable */
12559 0xFFFF, /* 03 wdtr_able */
12560 0x4444, /* 04 sdtr_speed1 */
12561 0xFFFF, /* 05 start_motor */
12562 0xFFFF, /* 06 tagqng_able */
12563 0xFFFF, /* 07 bios_scan */
12564 0, /* 08 scam_tolerant */
12565 7, /* 09 adapter_scsi_id */
12566 0, /* bios_boot_delay */
12567 3, /* 10 scsi_reset_delay */
12568 0, /* bios_id_lun */
12569 0, /* 11 termination_se */
12570 0, /* termination_lvd */
12571 0xFFE7, /* 12 bios_ctrl */
12572 0x4444, /* 13 sdtr_speed2 */
12573 0x4444, /* 14 sdtr_speed3 */
12574 ASC_DEF_MAX_HOST_QNG, /* 15 max_host_qng */
12575 ASC_DEF_MAX_DVC_QNG, /* max_dvc_qng */
12576 0, /* 16 dvc_cntl */
12577 0x4444, /* 17 sdtr_speed4 */
12578 0, /* 18 serial_number_word1 */
12579 0, /* 19 serial_number_word2 */
12580 0, /* 20 serial_number_word3 */
12581 0, /* 21 check_sum */
12582 {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
12583 , /* 22-29 oem_name[16] */
12584 0, /* 30 dvc_err_code */
12585 0, /* 31 adv_err_code */
12586 0, /* 32 adv_err_addr */
12587 0, /* 33 saved_dvc_err_code */
12588 0, /* 34 saved_adv_err_code */
12589 0, /* 35 saved_adv_err_addr */
12590 0, /* 36 reserved */
12591 0, /* 37 reserved */
12592 0, /* 38 reserved */
12593 0, /* 39 reserved */
12594 0, /* 40 reserved */
12595 0, /* 41 reserved */
12596 0, /* 42 reserved */
12597 0, /* 43 reserved */
12598 0, /* 44 reserved */
12599 0, /* 45 reserved */
12600 0, /* 46 reserved */
12601 0, /* 47 reserved */
12602 0, /* 48 reserved */
12603 0, /* 49 reserved */
12604 0, /* 50 reserved */
12605 0, /* 51 reserved */
12606 0, /* 52 reserved */
12607 0, /* 53 reserved */
12608 0, /* 54 reserved */
12609 0, /* 55 reserved */
12610 0, /* 56 cisptr_lsw */
12611 0, /* 57 cisprt_msw */
12612 PCI_VENDOR_ID_ASP, /* 58 subsysvid */
12613 PCI_DEVICE_ID_38C0800_REV1, /* 59 subsysid */
12614 0, /* 60 reserved */
12615 0, /* 61 reserved */
12616 0, /* 62 reserved */
12617 0 /* 63 reserved */
12620 static ADVEEP_38C0800_CONFIG ADVEEP_38C0800_Config_Field_IsChar __devinitdata = {
12621 0, /* 00 cfg_lsw */
12622 0, /* 01 cfg_msw */
12623 0, /* 02 disc_enable */
12624 0, /* 03 wdtr_able */
12625 0, /* 04 sdtr_speed1 */
12626 0, /* 05 start_motor */
12627 0, /* 06 tagqng_able */
12628 0, /* 07 bios_scan */
12629 0, /* 08 scam_tolerant */
12630 1, /* 09 adapter_scsi_id */
12631 1, /* bios_boot_delay */
12632 1, /* 10 scsi_reset_delay */
12633 1, /* bios_id_lun */
12634 1, /* 11 termination_se */
12635 1, /* termination_lvd */
12636 0, /* 12 bios_ctrl */
12637 0, /* 13 sdtr_speed2 */
12638 0, /* 14 sdtr_speed3 */
12639 1, /* 15 max_host_qng */
12640 1, /* max_dvc_qng */
12641 0, /* 16 dvc_cntl */
12642 0, /* 17 sdtr_speed4 */
12643 0, /* 18 serial_number_word1 */
12644 0, /* 19 serial_number_word2 */
12645 0, /* 20 serial_number_word3 */
12646 0, /* 21 check_sum */
12647 {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1}
12648 , /* 22-29 oem_name[16] */
12649 0, /* 30 dvc_err_code */
12650 0, /* 31 adv_err_code */
12651 0, /* 32 adv_err_addr */
12652 0, /* 33 saved_dvc_err_code */
12653 0, /* 34 saved_adv_err_code */
12654 0, /* 35 saved_adv_err_addr */
12655 0, /* 36 reserved */
12656 0, /* 37 reserved */
12657 0, /* 38 reserved */
12658 0, /* 39 reserved */
12659 0, /* 40 reserved */
12660 0, /* 41 reserved */
12661 0, /* 42 reserved */
12662 0, /* 43 reserved */
12663 0, /* 44 reserved */
12664 0, /* 45 reserved */
12665 0, /* 46 reserved */
12666 0, /* 47 reserved */
12667 0, /* 48 reserved */
12668 0, /* 49 reserved */
12669 0, /* 50 reserved */
12670 0, /* 51 reserved */
12671 0, /* 52 reserved */
12672 0, /* 53 reserved */
12673 0, /* 54 reserved */
12674 0, /* 55 reserved */
12675 0, /* 56 cisptr_lsw */
12676 0, /* 57 cisprt_msw */
12677 0, /* 58 subsysvid */
12678 0, /* 59 subsysid */
12679 0, /* 60 reserved */
12680 0, /* 61 reserved */
12681 0, /* 62 reserved */
12682 0 /* 63 reserved */
12685 static ADVEEP_38C1600_CONFIG Default_38C1600_EEPROM_Config __devinitdata = {
12686 ADV_EEPROM_BIOS_ENABLE, /* 00 cfg_lsw */
12687 0x0000, /* 01 cfg_msw */
12688 0xFFFF, /* 02 disc_enable */
12689 0xFFFF, /* 03 wdtr_able */
12690 0x5555, /* 04 sdtr_speed1 */
12691 0xFFFF, /* 05 start_motor */
12692 0xFFFF, /* 06 tagqng_able */
12693 0xFFFF, /* 07 bios_scan */
12694 0, /* 08 scam_tolerant */
12695 7, /* 09 adapter_scsi_id */
12696 0, /* bios_boot_delay */
12697 3, /* 10 scsi_reset_delay */
12698 0, /* bios_id_lun */
12699 0, /* 11 termination_se */
12700 0, /* termination_lvd */
12701 0xFFE7, /* 12 bios_ctrl */
12702 0x5555, /* 13 sdtr_speed2 */
12703 0x5555, /* 14 sdtr_speed3 */
12704 ASC_DEF_MAX_HOST_QNG, /* 15 max_host_qng */
12705 ASC_DEF_MAX_DVC_QNG, /* max_dvc_qng */
12706 0, /* 16 dvc_cntl */
12707 0x5555, /* 17 sdtr_speed4 */
12708 0, /* 18 serial_number_word1 */
12709 0, /* 19 serial_number_word2 */
12710 0, /* 20 serial_number_word3 */
12711 0, /* 21 check_sum */
12712 {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
12713 , /* 22-29 oem_name[16] */
12714 0, /* 30 dvc_err_code */
12715 0, /* 31 adv_err_code */
12716 0, /* 32 adv_err_addr */
12717 0, /* 33 saved_dvc_err_code */
12718 0, /* 34 saved_adv_err_code */
12719 0, /* 35 saved_adv_err_addr */
12720 0, /* 36 reserved */
12721 0, /* 37 reserved */
12722 0, /* 38 reserved */
12723 0, /* 39 reserved */
12724 0, /* 40 reserved */
12725 0, /* 41 reserved */
12726 0, /* 42 reserved */
12727 0, /* 43 reserved */
12728 0, /* 44 reserved */
12729 0, /* 45 reserved */
12730 0, /* 46 reserved */
12731 0, /* 47 reserved */
12732 0, /* 48 reserved */
12733 0, /* 49 reserved */
12734 0, /* 50 reserved */
12735 0, /* 51 reserved */
12736 0, /* 52 reserved */
12737 0, /* 53 reserved */
12738 0, /* 54 reserved */
12739 0, /* 55 reserved */
12740 0, /* 56 cisptr_lsw */
12741 0, /* 57 cisprt_msw */
12742 PCI_VENDOR_ID_ASP, /* 58 subsysvid */
12743 PCI_DEVICE_ID_38C1600_REV1, /* 59 subsysid */
12744 0, /* 60 reserved */
12745 0, /* 61 reserved */
12746 0, /* 62 reserved */
12747 0 /* 63 reserved */
12750 static ADVEEP_38C1600_CONFIG ADVEEP_38C1600_Config_Field_IsChar __devinitdata = {
12751 0, /* 00 cfg_lsw */
12752 0, /* 01 cfg_msw */
12753 0, /* 02 disc_enable */
12754 0, /* 03 wdtr_able */
12755 0, /* 04 sdtr_speed1 */
12756 0, /* 05 start_motor */
12757 0, /* 06 tagqng_able */
12758 0, /* 07 bios_scan */
12759 0, /* 08 scam_tolerant */
12760 1, /* 09 adapter_scsi_id */
12761 1, /* bios_boot_delay */
12762 1, /* 10 scsi_reset_delay */
12763 1, /* bios_id_lun */
12764 1, /* 11 termination_se */
12765 1, /* termination_lvd */
12766 0, /* 12 bios_ctrl */
12767 0, /* 13 sdtr_speed2 */
12768 0, /* 14 sdtr_speed3 */
12769 1, /* 15 max_host_qng */
12770 1, /* max_dvc_qng */
12771 0, /* 16 dvc_cntl */
12772 0, /* 17 sdtr_speed4 */
12773 0, /* 18 serial_number_word1 */
12774 0, /* 19 serial_number_word2 */
12775 0, /* 20 serial_number_word3 */
12776 0, /* 21 check_sum */
12777 {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1}
12778 , /* 22-29 oem_name[16] */
12779 0, /* 30 dvc_err_code */
12780 0, /* 31 adv_err_code */
12781 0, /* 32 adv_err_addr */
12782 0, /* 33 saved_dvc_err_code */
12783 0, /* 34 saved_adv_err_code */
12784 0, /* 35 saved_adv_err_addr */
12785 0, /* 36 reserved */
12786 0, /* 37 reserved */
12787 0, /* 38 reserved */
12788 0, /* 39 reserved */
12789 0, /* 40 reserved */
12790 0, /* 41 reserved */
12791 0, /* 42 reserved */
12792 0, /* 43 reserved */
12793 0, /* 44 reserved */
12794 0, /* 45 reserved */
12795 0, /* 46 reserved */
12796 0, /* 47 reserved */
12797 0, /* 48 reserved */
12798 0, /* 49 reserved */
12799 0, /* 50 reserved */
12800 0, /* 51 reserved */
12801 0, /* 52 reserved */
12802 0, /* 53 reserved */
12803 0, /* 54 reserved */
12804 0, /* 55 reserved */
12805 0, /* 56 cisptr_lsw */
12806 0, /* 57 cisprt_msw */
12807 0, /* 58 subsysvid */
12808 0, /* 59 subsysid */
12809 0, /* 60 reserved */
12810 0, /* 61 reserved */
12811 0, /* 62 reserved */
12812 0 /* 63 reserved */
12817 * Wait for EEPROM command to complete
12819 static void __devinit AdvWaitEEPCmd(AdvPortAddr iop_base)
12823 for (eep_delay_ms = 0; eep_delay_ms < ADV_EEP_DELAY_MS; eep_delay_ms++) {
12824 if (AdvReadWordRegister(iop_base, IOPW_EE_CMD) &
12825 ASC_EEP_CMD_DONE) {
12830 if ((AdvReadWordRegister(iop_base, IOPW_EE_CMD) & ASC_EEP_CMD_DONE) ==
12836 * Read the EEPROM from specified location
12838 static ushort __devinit AdvReadEEPWord(AdvPortAddr iop_base, int eep_word_addr)
12840 AdvWriteWordRegister(iop_base, IOPW_EE_CMD,
12841 ASC_EEP_CMD_READ | eep_word_addr);
12842 AdvWaitEEPCmd(iop_base);
12843 return AdvReadWordRegister(iop_base, IOPW_EE_DATA);
12847 * Write the EEPROM from 'cfg_buf'.
12850 AdvSet3550EEPConfig(AdvPortAddr iop_base, ADVEEP_3550_CONFIG *cfg_buf)
12853 ushort addr, chksum;
12854 ushort *charfields;
12856 wbuf = (ushort *)cfg_buf;
12857 charfields = (ushort *)&ADVEEP_3550_Config_Field_IsChar;
12860 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE_ABLE);
12861 AdvWaitEEPCmd(iop_base);
12864 * Write EEPROM from word 0 to word 20.
12866 for (addr = ADV_EEP_DVC_CFG_BEGIN;
12867 addr < ADV_EEP_DVC_CFG_END; addr++, wbuf++) {
12870 if (*charfields++) {
12871 word = cpu_to_le16(*wbuf);
12875 chksum += *wbuf; /* Checksum is calculated from word values. */
12876 AdvWriteWordRegister(iop_base, IOPW_EE_DATA, word);
12877 AdvWriteWordRegister(iop_base, IOPW_EE_CMD,
12878 ASC_EEP_CMD_WRITE | addr);
12879 AdvWaitEEPCmd(iop_base);
12880 mdelay(ADV_EEP_DELAY_MS);
12884 * Write EEPROM checksum at word 21.
12886 AdvWriteWordRegister(iop_base, IOPW_EE_DATA, chksum);
12887 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE | addr);
12888 AdvWaitEEPCmd(iop_base);
12893 * Write EEPROM OEM name at words 22 to 29.
12895 for (addr = ADV_EEP_DVC_CTL_BEGIN;
12896 addr < ADV_EEP_MAX_WORD_ADDR; addr++, wbuf++) {
12899 if (*charfields++) {
12900 word = cpu_to_le16(*wbuf);
12904 AdvWriteWordRegister(iop_base, IOPW_EE_DATA, word);
12905 AdvWriteWordRegister(iop_base, IOPW_EE_CMD,
12906 ASC_EEP_CMD_WRITE | addr);
12907 AdvWaitEEPCmd(iop_base);
12909 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE_DISABLE);
12910 AdvWaitEEPCmd(iop_base);
12914 * Write the EEPROM from 'cfg_buf'.
12917 AdvSet38C0800EEPConfig(AdvPortAddr iop_base, ADVEEP_38C0800_CONFIG *cfg_buf)
12920 ushort *charfields;
12921 ushort addr, chksum;
12923 wbuf = (ushort *)cfg_buf;
12924 charfields = (ushort *)&ADVEEP_38C0800_Config_Field_IsChar;
12927 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE_ABLE);
12928 AdvWaitEEPCmd(iop_base);
12931 * Write EEPROM from word 0 to word 20.
12933 for (addr = ADV_EEP_DVC_CFG_BEGIN;
12934 addr < ADV_EEP_DVC_CFG_END; addr++, wbuf++) {
12937 if (*charfields++) {
12938 word = cpu_to_le16(*wbuf);
12942 chksum += *wbuf; /* Checksum is calculated from word values. */
12943 AdvWriteWordRegister(iop_base, IOPW_EE_DATA, word);
12944 AdvWriteWordRegister(iop_base, IOPW_EE_CMD,
12945 ASC_EEP_CMD_WRITE | addr);
12946 AdvWaitEEPCmd(iop_base);
12947 mdelay(ADV_EEP_DELAY_MS);
12951 * Write EEPROM checksum at word 21.
12953 AdvWriteWordRegister(iop_base, IOPW_EE_DATA, chksum);
12954 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE | addr);
12955 AdvWaitEEPCmd(iop_base);
12960 * Write EEPROM OEM name at words 22 to 29.
12962 for (addr = ADV_EEP_DVC_CTL_BEGIN;
12963 addr < ADV_EEP_MAX_WORD_ADDR; addr++, wbuf++) {
12966 if (*charfields++) {
12967 word = cpu_to_le16(*wbuf);
12971 AdvWriteWordRegister(iop_base, IOPW_EE_DATA, word);
12972 AdvWriteWordRegister(iop_base, IOPW_EE_CMD,
12973 ASC_EEP_CMD_WRITE | addr);
12974 AdvWaitEEPCmd(iop_base);
12976 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE_DISABLE);
12977 AdvWaitEEPCmd(iop_base);
12981 * Write the EEPROM from 'cfg_buf'.
12984 AdvSet38C1600EEPConfig(AdvPortAddr iop_base, ADVEEP_38C1600_CONFIG *cfg_buf)
12987 ushort *charfields;
12988 ushort addr, chksum;
12990 wbuf = (ushort *)cfg_buf;
12991 charfields = (ushort *)&ADVEEP_38C1600_Config_Field_IsChar;
12994 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE_ABLE);
12995 AdvWaitEEPCmd(iop_base);
12998 * Write EEPROM from word 0 to word 20.
13000 for (addr = ADV_EEP_DVC_CFG_BEGIN;
13001 addr < ADV_EEP_DVC_CFG_END; addr++, wbuf++) {
13004 if (*charfields++) {
13005 word = cpu_to_le16(*wbuf);
13009 chksum += *wbuf; /* Checksum is calculated from word values. */
13010 AdvWriteWordRegister(iop_base, IOPW_EE_DATA, word);
13011 AdvWriteWordRegister(iop_base, IOPW_EE_CMD,
13012 ASC_EEP_CMD_WRITE | addr);
13013 AdvWaitEEPCmd(iop_base);
13014 mdelay(ADV_EEP_DELAY_MS);
13018 * Write EEPROM checksum at word 21.
13020 AdvWriteWordRegister(iop_base, IOPW_EE_DATA, chksum);
13021 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE | addr);
13022 AdvWaitEEPCmd(iop_base);
13027 * Write EEPROM OEM name at words 22 to 29.
13029 for (addr = ADV_EEP_DVC_CTL_BEGIN;
13030 addr < ADV_EEP_MAX_WORD_ADDR; addr++, wbuf++) {
13033 if (*charfields++) {
13034 word = cpu_to_le16(*wbuf);
13038 AdvWriteWordRegister(iop_base, IOPW_EE_DATA, word);
13039 AdvWriteWordRegister(iop_base, IOPW_EE_CMD,
13040 ASC_EEP_CMD_WRITE | addr);
13041 AdvWaitEEPCmd(iop_base);
13043 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE_DISABLE);
13044 AdvWaitEEPCmd(iop_base);
13048 * Read EEPROM configuration into the specified buffer.
13050 * Return a checksum based on the EEPROM configuration read.
13052 static ushort __devinit
13053 AdvGet3550EEPConfig(AdvPortAddr iop_base, ADVEEP_3550_CONFIG *cfg_buf)
13055 ushort wval, chksum;
13058 ushort *charfields;
13060 charfields = (ushort *)&ADVEEP_3550_Config_Field_IsChar;
13061 wbuf = (ushort *)cfg_buf;
13064 for (eep_addr = ADV_EEP_DVC_CFG_BEGIN;
13065 eep_addr < ADV_EEP_DVC_CFG_END; eep_addr++, wbuf++) {
13066 wval = AdvReadEEPWord(iop_base, eep_addr);
13067 chksum += wval; /* Checksum is calculated from word values. */
13068 if (*charfields++) {
13069 *wbuf = le16_to_cpu(wval);
13074 /* Read checksum word. */
13075 *wbuf = AdvReadEEPWord(iop_base, eep_addr);
13079 /* Read rest of EEPROM not covered by the checksum. */
13080 for (eep_addr = ADV_EEP_DVC_CTL_BEGIN;
13081 eep_addr < ADV_EEP_MAX_WORD_ADDR; eep_addr++, wbuf++) {
13082 *wbuf = AdvReadEEPWord(iop_base, eep_addr);
13083 if (*charfields++) {
13084 *wbuf = le16_to_cpu(*wbuf);
13091 * Read EEPROM configuration into the specified buffer.
13093 * Return a checksum based on the EEPROM configuration read.
13095 static ushort __devinit
13096 AdvGet38C0800EEPConfig(AdvPortAddr iop_base, ADVEEP_38C0800_CONFIG *cfg_buf)
13098 ushort wval, chksum;
13101 ushort *charfields;
13103 charfields = (ushort *)&ADVEEP_38C0800_Config_Field_IsChar;
13104 wbuf = (ushort *)cfg_buf;
13107 for (eep_addr = ADV_EEP_DVC_CFG_BEGIN;
13108 eep_addr < ADV_EEP_DVC_CFG_END; eep_addr++, wbuf++) {
13109 wval = AdvReadEEPWord(iop_base, eep_addr);
13110 chksum += wval; /* Checksum is calculated from word values. */
13111 if (*charfields++) {
13112 *wbuf = le16_to_cpu(wval);
13117 /* Read checksum word. */
13118 *wbuf = AdvReadEEPWord(iop_base, eep_addr);
13122 /* Read rest of EEPROM not covered by the checksum. */
13123 for (eep_addr = ADV_EEP_DVC_CTL_BEGIN;
13124 eep_addr < ADV_EEP_MAX_WORD_ADDR; eep_addr++, wbuf++) {
13125 *wbuf = AdvReadEEPWord(iop_base, eep_addr);
13126 if (*charfields++) {
13127 *wbuf = le16_to_cpu(*wbuf);
13134 * Read EEPROM configuration into the specified buffer.
13136 * Return a checksum based on the EEPROM configuration read.
13138 static ushort __devinit
13139 AdvGet38C1600EEPConfig(AdvPortAddr iop_base, ADVEEP_38C1600_CONFIG *cfg_buf)
13141 ushort wval, chksum;
13144 ushort *charfields;
13146 charfields = (ushort *)&ADVEEP_38C1600_Config_Field_IsChar;
13147 wbuf = (ushort *)cfg_buf;
13150 for (eep_addr = ADV_EEP_DVC_CFG_BEGIN;
13151 eep_addr < ADV_EEP_DVC_CFG_END; eep_addr++, wbuf++) {
13152 wval = AdvReadEEPWord(iop_base, eep_addr);
13153 chksum += wval; /* Checksum is calculated from word values. */
13154 if (*charfields++) {
13155 *wbuf = le16_to_cpu(wval);
13160 /* Read checksum word. */
13161 *wbuf = AdvReadEEPWord(iop_base, eep_addr);
13165 /* Read rest of EEPROM not covered by the checksum. */
13166 for (eep_addr = ADV_EEP_DVC_CTL_BEGIN;
13167 eep_addr < ADV_EEP_MAX_WORD_ADDR; eep_addr++, wbuf++) {
13168 *wbuf = AdvReadEEPWord(iop_base, eep_addr);
13169 if (*charfields++) {
13170 *wbuf = le16_to_cpu(*wbuf);
13177 * Read the board's EEPROM configuration. Set fields in ADV_DVC_VAR and
13178 * ADV_DVC_CFG based on the EEPROM settings. The chip is stopped while
13179 * all of this is done.
13181 * On failure set the ADV_DVC_VAR field 'err_code' and return ADV_ERROR.
13183 * For a non-fatal error return a warning code. If there are no warnings
13184 * then 0 is returned.
13186 * Note: Chip is stopped on entry.
13188 static int __devinit AdvInitFrom3550EEP(ADV_DVC_VAR *asc_dvc)
13190 AdvPortAddr iop_base;
13192 ADVEEP_3550_CONFIG eep_config;
13194 iop_base = asc_dvc->iop_base;
13199 * Read the board's EEPROM configuration.
13201 * Set default values if a bad checksum is found.
13203 if (AdvGet3550EEPConfig(iop_base, &eep_config) != eep_config.check_sum) {
13204 warn_code |= ASC_WARN_EEPROM_CHKSUM;
13207 * Set EEPROM default values.
13209 memcpy(&eep_config, &Default_3550_EEPROM_Config,
13210 sizeof(ADVEEP_3550_CONFIG));
13213 * Assume the 6 byte board serial number that was read from
13214 * EEPROM is correct even if the EEPROM checksum failed.
13216 eep_config.serial_number_word3 =
13217 AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 1);
13219 eep_config.serial_number_word2 =
13220 AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 2);
13222 eep_config.serial_number_word1 =
13223 AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 3);
13225 AdvSet3550EEPConfig(iop_base, &eep_config);
13228 * Set ASC_DVC_VAR and ASC_DVC_CFG variables from the
13229 * EEPROM configuration that was read.
13231 * This is the mapping of EEPROM fields to Adv Library fields.
13233 asc_dvc->wdtr_able = eep_config.wdtr_able;
13234 asc_dvc->sdtr_able = eep_config.sdtr_able;
13235 asc_dvc->ultra_able = eep_config.ultra_able;
13236 asc_dvc->tagqng_able = eep_config.tagqng_able;
13237 asc_dvc->cfg->disc_enable = eep_config.disc_enable;
13238 asc_dvc->max_host_qng = eep_config.max_host_qng;
13239 asc_dvc->max_dvc_qng = eep_config.max_dvc_qng;
13240 asc_dvc->chip_scsi_id = (eep_config.adapter_scsi_id & ADV_MAX_TID);
13241 asc_dvc->start_motor = eep_config.start_motor;
13242 asc_dvc->scsi_reset_wait = eep_config.scsi_reset_delay;
13243 asc_dvc->bios_ctrl = eep_config.bios_ctrl;
13244 asc_dvc->no_scam = eep_config.scam_tolerant;
13245 asc_dvc->cfg->serial1 = eep_config.serial_number_word1;
13246 asc_dvc->cfg->serial2 = eep_config.serial_number_word2;
13247 asc_dvc->cfg->serial3 = eep_config.serial_number_word3;
13250 * Set the host maximum queuing (max. 253, min. 16) and the per device
13251 * maximum queuing (max. 63, min. 4).
13253 if (eep_config.max_host_qng > ASC_DEF_MAX_HOST_QNG) {
13254 eep_config.max_host_qng = ASC_DEF_MAX_HOST_QNG;
13255 } else if (eep_config.max_host_qng < ASC_DEF_MIN_HOST_QNG) {
13256 /* If the value is zero, assume it is uninitialized. */
13257 if (eep_config.max_host_qng == 0) {
13258 eep_config.max_host_qng = ASC_DEF_MAX_HOST_QNG;
13260 eep_config.max_host_qng = ASC_DEF_MIN_HOST_QNG;
13264 if (eep_config.max_dvc_qng > ASC_DEF_MAX_DVC_QNG) {
13265 eep_config.max_dvc_qng = ASC_DEF_MAX_DVC_QNG;
13266 } else if (eep_config.max_dvc_qng < ASC_DEF_MIN_DVC_QNG) {
13267 /* If the value is zero, assume it is uninitialized. */
13268 if (eep_config.max_dvc_qng == 0) {
13269 eep_config.max_dvc_qng = ASC_DEF_MAX_DVC_QNG;
13271 eep_config.max_dvc_qng = ASC_DEF_MIN_DVC_QNG;
13276 * If 'max_dvc_qng' is greater than 'max_host_qng', then
13277 * set 'max_dvc_qng' to 'max_host_qng'.
13279 if (eep_config.max_dvc_qng > eep_config.max_host_qng) {
13280 eep_config.max_dvc_qng = eep_config.max_host_qng;
13284 * Set ADV_DVC_VAR 'max_host_qng' and ADV_DVC_VAR 'max_dvc_qng'
13285 * values based on possibly adjusted EEPROM values.
13287 asc_dvc->max_host_qng = eep_config.max_host_qng;
13288 asc_dvc->max_dvc_qng = eep_config.max_dvc_qng;
13291 * If the EEPROM 'termination' field is set to automatic (0), then set
13292 * the ADV_DVC_CFG 'termination' field to automatic also.
13294 * If the termination is specified with a non-zero 'termination'
13295 * value check that a legal value is set and set the ADV_DVC_CFG
13296 * 'termination' field appropriately.
13298 if (eep_config.termination == 0) {
13299 asc_dvc->cfg->termination = 0; /* auto termination */
13301 /* Enable manual control with low off / high off. */
13302 if (eep_config.termination == 1) {
13303 asc_dvc->cfg->termination = TERM_CTL_SEL;
13305 /* Enable manual control with low off / high on. */
13306 } else if (eep_config.termination == 2) {
13307 asc_dvc->cfg->termination = TERM_CTL_SEL | TERM_CTL_H;
13309 /* Enable manual control with low on / high on. */
13310 } else if (eep_config.termination == 3) {
13311 asc_dvc->cfg->termination =
13312 TERM_CTL_SEL | TERM_CTL_H | TERM_CTL_L;
13315 * The EEPROM 'termination' field contains a bad value. Use
13316 * automatic termination instead.
13318 asc_dvc->cfg->termination = 0;
13319 warn_code |= ASC_WARN_EEPROM_TERMINATION;
13327 * Read the board's EEPROM configuration. Set fields in ADV_DVC_VAR and
13328 * ADV_DVC_CFG based on the EEPROM settings. The chip is stopped while
13329 * all of this is done.
13331 * On failure set the ADV_DVC_VAR field 'err_code' and return ADV_ERROR.
13333 * For a non-fatal error return a warning code. If there are no warnings
13334 * then 0 is returned.
13336 * Note: Chip is stopped on entry.
13338 static int __devinit AdvInitFrom38C0800EEP(ADV_DVC_VAR *asc_dvc)
13340 AdvPortAddr iop_base;
13342 ADVEEP_38C0800_CONFIG eep_config;
13343 uchar tid, termination;
13344 ushort sdtr_speed = 0;
13346 iop_base = asc_dvc->iop_base;
13351 * Read the board's EEPROM configuration.
13353 * Set default values if a bad checksum is found.
13355 if (AdvGet38C0800EEPConfig(iop_base, &eep_config) !=
13356 eep_config.check_sum) {
13357 warn_code |= ASC_WARN_EEPROM_CHKSUM;
13360 * Set EEPROM default values.
13362 memcpy(&eep_config, &Default_38C0800_EEPROM_Config,
13363 sizeof(ADVEEP_38C0800_CONFIG));
13366 * Assume the 6 byte board serial number that was read from
13367 * EEPROM is correct even if the EEPROM checksum failed.
13369 eep_config.serial_number_word3 =
13370 AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 1);
13372 eep_config.serial_number_word2 =
13373 AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 2);
13375 eep_config.serial_number_word1 =
13376 AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 3);
13378 AdvSet38C0800EEPConfig(iop_base, &eep_config);
13381 * Set ADV_DVC_VAR and ADV_DVC_CFG variables from the
13382 * EEPROM configuration that was read.
13384 * This is the mapping of EEPROM fields to Adv Library fields.
13386 asc_dvc->wdtr_able = eep_config.wdtr_able;
13387 asc_dvc->sdtr_speed1 = eep_config.sdtr_speed1;
13388 asc_dvc->sdtr_speed2 = eep_config.sdtr_speed2;
13389 asc_dvc->sdtr_speed3 = eep_config.sdtr_speed3;
13390 asc_dvc->sdtr_speed4 = eep_config.sdtr_speed4;
13391 asc_dvc->tagqng_able = eep_config.tagqng_able;
13392 asc_dvc->cfg->disc_enable = eep_config.disc_enable;
13393 asc_dvc->max_host_qng = eep_config.max_host_qng;
13394 asc_dvc->max_dvc_qng = eep_config.max_dvc_qng;
13395 asc_dvc->chip_scsi_id = (eep_config.adapter_scsi_id & ADV_MAX_TID);
13396 asc_dvc->start_motor = eep_config.start_motor;
13397 asc_dvc->scsi_reset_wait = eep_config.scsi_reset_delay;
13398 asc_dvc->bios_ctrl = eep_config.bios_ctrl;
13399 asc_dvc->no_scam = eep_config.scam_tolerant;
13400 asc_dvc->cfg->serial1 = eep_config.serial_number_word1;
13401 asc_dvc->cfg->serial2 = eep_config.serial_number_word2;
13402 asc_dvc->cfg->serial3 = eep_config.serial_number_word3;
13405 * For every Target ID if any of its 'sdtr_speed[1234]' bits
13406 * are set, then set an 'sdtr_able' bit for it.
13408 asc_dvc->sdtr_able = 0;
13409 for (tid = 0; tid <= ADV_MAX_TID; tid++) {
13411 sdtr_speed = asc_dvc->sdtr_speed1;
13412 } else if (tid == 4) {
13413 sdtr_speed = asc_dvc->sdtr_speed2;
13414 } else if (tid == 8) {
13415 sdtr_speed = asc_dvc->sdtr_speed3;
13416 } else if (tid == 12) {
13417 sdtr_speed = asc_dvc->sdtr_speed4;
13419 if (sdtr_speed & ADV_MAX_TID) {
13420 asc_dvc->sdtr_able |= (1 << tid);
13426 * Set the host maximum queuing (max. 253, min. 16) and the per device
13427 * maximum queuing (max. 63, min. 4).
13429 if (eep_config.max_host_qng > ASC_DEF_MAX_HOST_QNG) {
13430 eep_config.max_host_qng = ASC_DEF_MAX_HOST_QNG;
13431 } else if (eep_config.max_host_qng < ASC_DEF_MIN_HOST_QNG) {
13432 /* If the value is zero, assume it is uninitialized. */
13433 if (eep_config.max_host_qng == 0) {
13434 eep_config.max_host_qng = ASC_DEF_MAX_HOST_QNG;
13436 eep_config.max_host_qng = ASC_DEF_MIN_HOST_QNG;
13440 if (eep_config.max_dvc_qng > ASC_DEF_MAX_DVC_QNG) {
13441 eep_config.max_dvc_qng = ASC_DEF_MAX_DVC_QNG;
13442 } else if (eep_config.max_dvc_qng < ASC_DEF_MIN_DVC_QNG) {
13443 /* If the value is zero, assume it is uninitialized. */
13444 if (eep_config.max_dvc_qng == 0) {
13445 eep_config.max_dvc_qng = ASC_DEF_MAX_DVC_QNG;
13447 eep_config.max_dvc_qng = ASC_DEF_MIN_DVC_QNG;
13452 * If 'max_dvc_qng' is greater than 'max_host_qng', then
13453 * set 'max_dvc_qng' to 'max_host_qng'.
13455 if (eep_config.max_dvc_qng > eep_config.max_host_qng) {
13456 eep_config.max_dvc_qng = eep_config.max_host_qng;
13460 * Set ADV_DVC_VAR 'max_host_qng' and ADV_DVC_VAR 'max_dvc_qng'
13461 * values based on possibly adjusted EEPROM values.
13463 asc_dvc->max_host_qng = eep_config.max_host_qng;
13464 asc_dvc->max_dvc_qng = eep_config.max_dvc_qng;
13467 * If the EEPROM 'termination' field is set to automatic (0), then set
13468 * the ADV_DVC_CFG 'termination' field to automatic also.
13470 * If the termination is specified with a non-zero 'termination'
13471 * value check that a legal value is set and set the ADV_DVC_CFG
13472 * 'termination' field appropriately.
13474 if (eep_config.termination_se == 0) {
13475 termination = 0; /* auto termination for SE */
13477 /* Enable manual control with low off / high off. */
13478 if (eep_config.termination_se == 1) {
13481 /* Enable manual control with low off / high on. */
13482 } else if (eep_config.termination_se == 2) {
13483 termination = TERM_SE_HI;
13485 /* Enable manual control with low on / high on. */
13486 } else if (eep_config.termination_se == 3) {
13487 termination = TERM_SE;
13490 * The EEPROM 'termination_se' field contains a bad value.
13491 * Use automatic termination instead.
13494 warn_code |= ASC_WARN_EEPROM_TERMINATION;
13498 if (eep_config.termination_lvd == 0) {
13499 asc_dvc->cfg->termination = termination; /* auto termination for LVD */
13501 /* Enable manual control with low off / high off. */
13502 if (eep_config.termination_lvd == 1) {
13503 asc_dvc->cfg->termination = termination;
13505 /* Enable manual control with low off / high on. */
13506 } else if (eep_config.termination_lvd == 2) {
13507 asc_dvc->cfg->termination = termination | TERM_LVD_HI;
13509 /* Enable manual control with low on / high on. */
13510 } else if (eep_config.termination_lvd == 3) {
13511 asc_dvc->cfg->termination = termination | TERM_LVD;
13514 * The EEPROM 'termination_lvd' field contains a bad value.
13515 * Use automatic termination instead.
13517 asc_dvc->cfg->termination = termination;
13518 warn_code |= ASC_WARN_EEPROM_TERMINATION;
13526 * Read the board's EEPROM configuration. Set fields in ASC_DVC_VAR and
13527 * ASC_DVC_CFG based on the EEPROM settings. The chip is stopped while
13528 * all of this is done.
13530 * On failure set the ASC_DVC_VAR field 'err_code' and return ADV_ERROR.
13532 * For a non-fatal error return a warning code. If there are no warnings
13533 * then 0 is returned.
13535 * Note: Chip is stopped on entry.
13537 static int __devinit AdvInitFrom38C1600EEP(ADV_DVC_VAR *asc_dvc)
13539 AdvPortAddr iop_base;
13541 ADVEEP_38C1600_CONFIG eep_config;
13542 uchar tid, termination;
13543 ushort sdtr_speed = 0;
13545 iop_base = asc_dvc->iop_base;
13550 * Read the board's EEPROM configuration.
13552 * Set default values if a bad checksum is found.
13554 if (AdvGet38C1600EEPConfig(iop_base, &eep_config) !=
13555 eep_config.check_sum) {
13556 struct pci_dev *pdev = adv_dvc_to_pdev(asc_dvc);
13557 warn_code |= ASC_WARN_EEPROM_CHKSUM;
13560 * Set EEPROM default values.
13562 memcpy(&eep_config, &Default_38C1600_EEPROM_Config,
13563 sizeof(ADVEEP_38C1600_CONFIG));
13565 if (PCI_FUNC(pdev->devfn) != 0) {
13568 * Disable Bit 14 (BIOS_ENABLE) to fix SPARC Ultra 60
13569 * and old Mac system booting problem. The Expansion
13570 * ROM must be disabled in Function 1 for these systems
13572 eep_config.cfg_lsw &= ~ADV_EEPROM_BIOS_ENABLE;
13574 * Clear the INTAB (bit 11) if the GPIO 0 input
13575 * indicates the Function 1 interrupt line is wired
13578 * Set/Clear Bit 11 (INTAB) from the GPIO bit 0 input:
13579 * 1 - Function 1 interrupt line wired to INT A.
13580 * 0 - Function 1 interrupt line wired to INT B.
13582 * Note: Function 0 is always wired to INTA.
13583 * Put all 5 GPIO bits in input mode and then read
13584 * their input values.
13586 AdvWriteByteRegister(iop_base, IOPB_GPIO_CNTL, 0);
13587 ints = AdvReadByteRegister(iop_base, IOPB_GPIO_DATA);
13588 if ((ints & 0x01) == 0)
13589 eep_config.cfg_lsw &= ~ADV_EEPROM_INTAB;
13593 * Assume the 6 byte board serial number that was read from
13594 * EEPROM is correct even if the EEPROM checksum failed.
13596 eep_config.serial_number_word3 =
13597 AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 1);
13598 eep_config.serial_number_word2 =
13599 AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 2);
13600 eep_config.serial_number_word1 =
13601 AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 3);
13603 AdvSet38C1600EEPConfig(iop_base, &eep_config);
13607 * Set ASC_DVC_VAR and ASC_DVC_CFG variables from the
13608 * EEPROM configuration that was read.
13610 * This is the mapping of EEPROM fields to Adv Library fields.
13612 asc_dvc->wdtr_able = eep_config.wdtr_able;
13613 asc_dvc->sdtr_speed1 = eep_config.sdtr_speed1;
13614 asc_dvc->sdtr_speed2 = eep_config.sdtr_speed2;
13615 asc_dvc->sdtr_speed3 = eep_config.sdtr_speed3;
13616 asc_dvc->sdtr_speed4 = eep_config.sdtr_speed4;
13617 asc_dvc->ppr_able = 0;
13618 asc_dvc->tagqng_able = eep_config.tagqng_able;
13619 asc_dvc->cfg->disc_enable = eep_config.disc_enable;
13620 asc_dvc->max_host_qng = eep_config.max_host_qng;
13621 asc_dvc->max_dvc_qng = eep_config.max_dvc_qng;
13622 asc_dvc->chip_scsi_id = (eep_config.adapter_scsi_id & ASC_MAX_TID);
13623 asc_dvc->start_motor = eep_config.start_motor;
13624 asc_dvc->scsi_reset_wait = eep_config.scsi_reset_delay;
13625 asc_dvc->bios_ctrl = eep_config.bios_ctrl;
13626 asc_dvc->no_scam = eep_config.scam_tolerant;
13629 * For every Target ID if any of its 'sdtr_speed[1234]' bits
13630 * are set, then set an 'sdtr_able' bit for it.
13632 asc_dvc->sdtr_able = 0;
13633 for (tid = 0; tid <= ASC_MAX_TID; tid++) {
13635 sdtr_speed = asc_dvc->sdtr_speed1;
13636 } else if (tid == 4) {
13637 sdtr_speed = asc_dvc->sdtr_speed2;
13638 } else if (tid == 8) {
13639 sdtr_speed = asc_dvc->sdtr_speed3;
13640 } else if (tid == 12) {
13641 sdtr_speed = asc_dvc->sdtr_speed4;
13643 if (sdtr_speed & ASC_MAX_TID) {
13644 asc_dvc->sdtr_able |= (1 << tid);
13650 * Set the host maximum queuing (max. 253, min. 16) and the per device
13651 * maximum queuing (max. 63, min. 4).
13653 if (eep_config.max_host_qng > ASC_DEF_MAX_HOST_QNG) {
13654 eep_config.max_host_qng = ASC_DEF_MAX_HOST_QNG;
13655 } else if (eep_config.max_host_qng < ASC_DEF_MIN_HOST_QNG) {
13656 /* If the value is zero, assume it is uninitialized. */
13657 if (eep_config.max_host_qng == 0) {
13658 eep_config.max_host_qng = ASC_DEF_MAX_HOST_QNG;
13660 eep_config.max_host_qng = ASC_DEF_MIN_HOST_QNG;
13664 if (eep_config.max_dvc_qng > ASC_DEF_MAX_DVC_QNG) {
13665 eep_config.max_dvc_qng = ASC_DEF_MAX_DVC_QNG;
13666 } else if (eep_config.max_dvc_qng < ASC_DEF_MIN_DVC_QNG) {
13667 /* If the value is zero, assume it is uninitialized. */
13668 if (eep_config.max_dvc_qng == 0) {
13669 eep_config.max_dvc_qng = ASC_DEF_MAX_DVC_QNG;
13671 eep_config.max_dvc_qng = ASC_DEF_MIN_DVC_QNG;
13676 * If 'max_dvc_qng' is greater than 'max_host_qng', then
13677 * set 'max_dvc_qng' to 'max_host_qng'.
13679 if (eep_config.max_dvc_qng > eep_config.max_host_qng) {
13680 eep_config.max_dvc_qng = eep_config.max_host_qng;
13684 * Set ASC_DVC_VAR 'max_host_qng' and ASC_DVC_VAR 'max_dvc_qng'
13685 * values based on possibly adjusted EEPROM values.
13687 asc_dvc->max_host_qng = eep_config.max_host_qng;
13688 asc_dvc->max_dvc_qng = eep_config.max_dvc_qng;
13691 * If the EEPROM 'termination' field is set to automatic (0), then set
13692 * the ASC_DVC_CFG 'termination' field to automatic also.
13694 * If the termination is specified with a non-zero 'termination'
13695 * value check that a legal value is set and set the ASC_DVC_CFG
13696 * 'termination' field appropriately.
13698 if (eep_config.termination_se == 0) {
13699 termination = 0; /* auto termination for SE */
13701 /* Enable manual control with low off / high off. */
13702 if (eep_config.termination_se == 1) {
13705 /* Enable manual control with low off / high on. */
13706 } else if (eep_config.termination_se == 2) {
13707 termination = TERM_SE_HI;
13709 /* Enable manual control with low on / high on. */
13710 } else if (eep_config.termination_se == 3) {
13711 termination = TERM_SE;
13714 * The EEPROM 'termination_se' field contains a bad value.
13715 * Use automatic termination instead.
13718 warn_code |= ASC_WARN_EEPROM_TERMINATION;
13722 if (eep_config.termination_lvd == 0) {
13723 asc_dvc->cfg->termination = termination; /* auto termination for LVD */
13725 /* Enable manual control with low off / high off. */
13726 if (eep_config.termination_lvd == 1) {
13727 asc_dvc->cfg->termination = termination;
13729 /* Enable manual control with low off / high on. */
13730 } else if (eep_config.termination_lvd == 2) {
13731 asc_dvc->cfg->termination = termination | TERM_LVD_HI;
13733 /* Enable manual control with low on / high on. */
13734 } else if (eep_config.termination_lvd == 3) {
13735 asc_dvc->cfg->termination = termination | TERM_LVD;
13738 * The EEPROM 'termination_lvd' field contains a bad value.
13739 * Use automatic termination instead.
13741 asc_dvc->cfg->termination = termination;
13742 warn_code |= ASC_WARN_EEPROM_TERMINATION;
13750 * Initialize the ADV_DVC_VAR structure.
13752 * On failure set the ADV_DVC_VAR field 'err_code' and return ADV_ERROR.
13754 * For a non-fatal error return a warning code. If there are no warnings
13755 * then 0 is returned.
13757 static int __devinit
13758 AdvInitGetConfig(struct pci_dev *pdev, asc_board_t *boardp)
13760 ADV_DVC_VAR *asc_dvc = &boardp->dvc_var.adv_dvc_var;
13761 unsigned short warn_code = 0;
13762 AdvPortAddr iop_base = asc_dvc->iop_base;
13766 asc_dvc->err_code = 0;
13769 * Save the state of the PCI Configuration Command Register
13770 * "Parity Error Response Control" Bit. If the bit is clear (0),
13771 * in AdvInitAsc3550/38C0800Driver() tell the microcode to ignore
13772 * DMA parity errors.
13774 asc_dvc->cfg->control_flag = 0;
13775 pci_read_config_word(pdev, PCI_COMMAND, &cmd);
13776 if ((cmd & PCI_COMMAND_PARITY) == 0)
13777 asc_dvc->cfg->control_flag |= CONTROL_FLAG_IGNORE_PERR;
13779 asc_dvc->cfg->lib_version = (ADV_LIB_VERSION_MAJOR << 8) |
13780 ADV_LIB_VERSION_MINOR;
13781 asc_dvc->cfg->chip_version =
13782 AdvGetChipVersion(iop_base, asc_dvc->bus_type);
13784 ASC_DBG2(1, "AdvInitGetConfig: iopb_chip_id_1: 0x%x 0x%x\n",
13785 (ushort)AdvReadByteRegister(iop_base, IOPB_CHIP_ID_1),
13786 (ushort)ADV_CHIP_ID_BYTE);
13788 ASC_DBG2(1, "AdvInitGetConfig: iopw_chip_id_0: 0x%x 0x%x\n",
13789 (ushort)AdvReadWordRegister(iop_base, IOPW_CHIP_ID_0),
13790 (ushort)ADV_CHIP_ID_WORD);
13793 * Reset the chip to start and allow register writes.
13795 if (AdvFindSignature(iop_base) == 0) {
13796 asc_dvc->err_code = ASC_IERR_BAD_SIGNATURE;
13800 * The caller must set 'chip_type' to a valid setting.
13802 if (asc_dvc->chip_type != ADV_CHIP_ASC3550 &&
13803 asc_dvc->chip_type != ADV_CHIP_ASC38C0800 &&
13804 asc_dvc->chip_type != ADV_CHIP_ASC38C1600) {
13805 asc_dvc->err_code |= ASC_IERR_BAD_CHIPTYPE;
13812 AdvWriteWordRegister(iop_base, IOPW_CTRL_REG,
13813 ADV_CTRL_REG_CMD_RESET);
13815 AdvWriteWordRegister(iop_base, IOPW_CTRL_REG,
13816 ADV_CTRL_REG_CMD_WR_IO_REG);
13818 if (asc_dvc->chip_type == ADV_CHIP_ASC38C1600) {
13819 status = AdvInitFrom38C1600EEP(asc_dvc);
13820 } else if (asc_dvc->chip_type == ADV_CHIP_ASC38C0800) {
13821 status = AdvInitFrom38C0800EEP(asc_dvc);
13823 status = AdvInitFrom3550EEP(asc_dvc);
13825 warn_code |= status;
13828 if (warn_code != 0) {
13829 ASC_PRINT2("AdvInitGetConfig: board %d: warning: 0x%x\n",
13830 boardp->id, warn_code);
13833 if (asc_dvc->err_code) {
13834 ASC_PRINT2("AdvInitGetConfig: board %d error: err_code 0x%x\n",
13835 boardp->id, asc_dvc->err_code);
13838 return asc_dvc->err_code;
13842 static struct scsi_host_template advansys_template = {
13843 .proc_name = DRV_NAME,
13844 #ifdef CONFIG_PROC_FS
13845 .proc_info = advansys_proc_info,
13848 .info = advansys_info,
13849 .queuecommand = advansys_queuecommand,
13850 .eh_bus_reset_handler = advansys_reset,
13851 .bios_param = advansys_biosparam,
13852 .slave_configure = advansys_slave_configure,
13854 * Because the driver may control an ISA adapter 'unchecked_isa_dma'
13855 * must be set. The flag will be cleared in advansys_board_found
13856 * for non-ISA adapters.
13858 .unchecked_isa_dma = 1,
13860 * All adapters controlled by this driver are capable of large
13861 * scatter-gather lists. According to the mid-level SCSI documentation
13862 * this obviates any performance gain provided by setting
13863 * 'use_clustering'. But empirically while CPU utilization is increased
13864 * by enabling clustering, I/O throughput increases as well.
13866 .use_clustering = ENABLE_CLUSTERING,
13869 static int __devinit
13870 advansys_wide_init_chip(asc_board_t *boardp, ADV_DVC_VAR *adv_dvc_varp)
13873 adv_req_t *reqp = NULL;
13876 int warn_code, err_code;
13879 * Allocate buffer carrier structures. The total size
13880 * is about 4 KB, so allocate all at once.
13882 boardp->carrp = kmalloc(ADV_CARRIER_BUFSIZE, GFP_KERNEL);
13883 ASC_DBG1(1, "advansys_wide_init_chip: carrp 0x%p\n", boardp->carrp);
13885 if (!boardp->carrp)
13886 goto kmalloc_failed;
13889 * Allocate up to 'max_host_qng' request structures for the Wide
13890 * board. The total size is about 16 KB, so allocate all at once.
13891 * If the allocation fails decrement and try again.
13893 for (req_cnt = adv_dvc_varp->max_host_qng; req_cnt > 0; req_cnt--) {
13894 reqp = kmalloc(sizeof(adv_req_t) * req_cnt, GFP_KERNEL);
13896 ASC_DBG3(1, "advansys_wide_init_chip: reqp 0x%p, req_cnt %d, "
13897 "bytes %lu\n", reqp, req_cnt,
13898 (ulong)sizeof(adv_req_t) * req_cnt);
13905 goto kmalloc_failed;
13907 boardp->orig_reqp = reqp;
13910 * Allocate up to ADV_TOT_SG_BLOCK request structures for
13911 * the Wide board. Each structure is about 136 bytes.
13913 boardp->adv_sgblkp = NULL;
13914 for (sg_cnt = 0; sg_cnt < ADV_TOT_SG_BLOCK; sg_cnt++) {
13915 sgp = kmalloc(sizeof(adv_sgblk_t), GFP_KERNEL);
13920 sgp->next_sgblkp = boardp->adv_sgblkp;
13921 boardp->adv_sgblkp = sgp;
13925 ASC_DBG3(1, "advansys_wide_init_chip: sg_cnt %d * %u = %u bytes\n",
13926 sg_cnt, sizeof(adv_sgblk_t),
13927 (unsigned)(sizeof(adv_sgblk_t) * sg_cnt));
13929 if (!boardp->adv_sgblkp)
13930 goto kmalloc_failed;
13932 adv_dvc_varp->carrier_buf = boardp->carrp;
13935 * Point 'adv_reqp' to the request structures and
13936 * link them together.
13939 reqp[req_cnt].next_reqp = NULL;
13940 for (; req_cnt > 0; req_cnt--) {
13941 reqp[req_cnt - 1].next_reqp = &reqp[req_cnt];
13943 boardp->adv_reqp = &reqp[0];
13945 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
13946 ASC_DBG(2, "advansys_wide_init_chip: AdvInitAsc3550Driver()\n");
13947 warn_code = AdvInitAsc3550Driver(adv_dvc_varp);
13948 } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
13949 ASC_DBG(2, "advansys_wide_init_chip: AdvInitAsc38C0800Driver()"
13951 warn_code = AdvInitAsc38C0800Driver(adv_dvc_varp);
13953 ASC_DBG(2, "advansys_wide_init_chip: AdvInitAsc38C1600Driver()"
13955 warn_code = AdvInitAsc38C1600Driver(adv_dvc_varp);
13957 err_code = adv_dvc_varp->err_code;
13959 if (warn_code || err_code) {
13960 ASC_PRINT3("advansys_wide_init_chip: board %d error: warn 0x%x,"
13961 " error 0x%x\n", boardp->id, warn_code, err_code);
13967 ASC_PRINT1("advansys_wide_init_chip: board %d error: kmalloc() "
13968 "failed\n", boardp->id);
13969 err_code = ADV_ERROR;
13974 static void advansys_wide_free_mem(asc_board_t *boardp)
13976 kfree(boardp->carrp);
13977 boardp->carrp = NULL;
13978 kfree(boardp->orig_reqp);
13979 boardp->orig_reqp = boardp->adv_reqp = NULL;
13980 while (boardp->adv_sgblkp) {
13981 adv_sgblk_t *sgp = boardp->adv_sgblkp;
13982 boardp->adv_sgblkp = sgp->next_sgblkp;
13987 static struct Scsi_Host *__devinit
13988 advansys_board_found(int iop, struct device *dev, int bus_type)
13990 struct Scsi_Host *shost;
13991 struct pci_dev *pdev = bus_type == ASC_IS_PCI ? to_pci_dev(dev) : NULL;
13992 asc_board_t *boardp;
13993 ASC_DVC_VAR *asc_dvc_varp = NULL;
13994 ADV_DVC_VAR *adv_dvc_varp = NULL;
13996 int warn_code, err_code;
14000 * Register the adapter, get its configuration, and
14003 ASC_DBG(2, "advansys_board_found: scsi_host_alloc()\n");
14004 shost = scsi_host_alloc(&advansys_template, sizeof(asc_board_t));
14008 /* Initialize private per board data */
14009 boardp = ASC_BOARDP(shost);
14010 memset(boardp, 0, sizeof(asc_board_t));
14011 boardp->id = asc_board_count++;
14012 spin_lock_init(&boardp->lock);
14016 * Handle both narrow and wide boards.
14018 * If a Wide board was detected, set the board structure
14019 * wide board flag. Set-up the board structure based on
14023 if (bus_type == ASC_IS_PCI &&
14024 (pdev->device == PCI_DEVICE_ID_ASP_ABP940UW ||
14025 pdev->device == PCI_DEVICE_ID_38C0800_REV1 ||
14026 pdev->device == PCI_DEVICE_ID_38C1600_REV1)) {
14027 boardp->flags |= ASC_IS_WIDE_BOARD;
14029 #endif /* CONFIG_PCI */
14031 if (ASC_NARROW_BOARD(boardp)) {
14032 ASC_DBG(1, "advansys_board_found: narrow board\n");
14033 asc_dvc_varp = &boardp->dvc_var.asc_dvc_var;
14034 asc_dvc_varp->bus_type = bus_type;
14035 asc_dvc_varp->drv_ptr = boardp;
14036 asc_dvc_varp->cfg = &boardp->dvc_cfg.asc_dvc_cfg;
14037 asc_dvc_varp->cfg->overrun_buf = &overrun_buf[0];
14038 asc_dvc_varp->iop_base = iop;
14041 ASC_DBG(1, "advansys_board_found: wide board\n");
14042 adv_dvc_varp = &boardp->dvc_var.adv_dvc_var;
14043 adv_dvc_varp->drv_ptr = boardp;
14044 adv_dvc_varp->cfg = &boardp->dvc_cfg.adv_dvc_cfg;
14045 if (pdev->device == PCI_DEVICE_ID_ASP_ABP940UW) {
14046 ASC_DBG(1, "advansys_board_found: ASC-3550\n");
14047 adv_dvc_varp->chip_type = ADV_CHIP_ASC3550;
14048 } else if (pdev->device == PCI_DEVICE_ID_38C0800_REV1) {
14049 ASC_DBG(1, "advansys_board_found: ASC-38C0800\n");
14050 adv_dvc_varp->chip_type = ADV_CHIP_ASC38C0800;
14052 ASC_DBG(1, "advansys_board_found: ASC-38C1600\n");
14053 adv_dvc_varp->chip_type = ADV_CHIP_ASC38C1600;
14056 boardp->asc_n_io_port = pci_resource_len(pdev, 1);
14057 boardp->ioremap_addr = ioremap(pci_resource_start(pdev, 1),
14058 boardp->asc_n_io_port);
14059 if (!boardp->ioremap_addr) {
14061 ("advansys_board_found: board %d: ioremap(%x, %d) returned NULL\n",
14062 boardp->id, pci_resource_start(pdev, 1),
14063 boardp->asc_n_io_port);
14066 adv_dvc_varp->iop_base = (AdvPortAddr)boardp->ioremap_addr
14067 ASC_DBG1(1, "advansys_board_found: iop_base: 0x%lx\n",
14068 adv_dvc_varp->iop_base);
14071 * Even though it isn't used to access wide boards, other
14072 * than for the debug line below, save I/O Port address so
14073 * that it can be reported.
14075 boardp->ioport = iop;
14077 ASC_DBG2(1, "advansys_board_found: iopb_chip_id_1 0x%x, "
14078 "iopw_chip_id_0 0x%x\n", (ushort)inp(iop + 1),
14079 (ushort)inpw(iop));
14080 #endif /* CONFIG_PCI */
14083 #ifdef CONFIG_PROC_FS
14085 * Allocate buffer for printing information from
14086 * /proc/scsi/advansys/[0...].
14088 boardp->prtbuf = kmalloc(ASC_PRTBUF_SIZE, GFP_KERNEL);
14089 if (!boardp->prtbuf) {
14090 ASC_PRINT2("advansys_board_found: board %d: kmalloc(%d) "
14091 "returned NULL\n", boardp->id, ASC_PRTBUF_SIZE);
14094 #endif /* CONFIG_PROC_FS */
14096 if (ASC_NARROW_BOARD(boardp)) {
14098 * Set the board bus type and PCI IRQ before
14099 * calling AscInitGetConfig().
14101 switch (asc_dvc_varp->bus_type) {
14104 shost->unchecked_isa_dma = TRUE;
14108 shost->unchecked_isa_dma = FALSE;
14112 shost->unchecked_isa_dma = FALSE;
14113 share_irq = IRQF_SHARED;
14115 #endif /* CONFIG_ISA */
14118 shost->irq = asc_dvc_varp->irq_no = pdev->irq;
14119 shost->unchecked_isa_dma = FALSE;
14120 share_irq = IRQF_SHARED;
14122 #endif /* CONFIG_PCI */
14125 ("advansys_board_found: board %d: unknown adapter type: %d\n",
14126 boardp->id, asc_dvc_varp->bus_type);
14127 shost->unchecked_isa_dma = TRUE;
14133 * NOTE: AscInitGetConfig() may change the board's
14134 * bus_type value. The bus_type value should no
14135 * longer be used. If the bus_type field must be
14136 * referenced only use the bit-wise AND operator "&".
14138 ASC_DBG(2, "advansys_board_found: AscInitGetConfig()\n");
14139 err_code = AscInitGetConfig(boardp);
14143 * For Wide boards set PCI information before calling
14144 * AdvInitGetConfig().
14146 shost->irq = adv_dvc_varp->irq_no = pdev->irq;
14147 shost->unchecked_isa_dma = FALSE;
14148 share_irq = IRQF_SHARED;
14149 ASC_DBG(2, "advansys_board_found: AdvInitGetConfig()\n");
14151 err_code = AdvInitGetConfig(pdev, boardp);
14152 #endif /* CONFIG_PCI */
14156 goto err_free_proc;
14159 * Save the EEPROM configuration so that it can be displayed
14160 * from /proc/scsi/advansys/[0...].
14162 if (ASC_NARROW_BOARD(boardp)) {
14167 * Set the adapter's target id bit in the 'init_tidmask' field.
14169 boardp->init_tidmask |=
14170 ADV_TID_TO_TIDMASK(asc_dvc_varp->cfg->chip_scsi_id);
14173 * Save EEPROM settings for the board.
14175 ep = &boardp->eep_config.asc_eep;
14177 ep->init_sdtr = asc_dvc_varp->cfg->sdtr_enable;
14178 ep->disc_enable = asc_dvc_varp->cfg->disc_enable;
14179 ep->use_cmd_qng = asc_dvc_varp->cfg->cmd_qng_enabled;
14180 ASC_EEP_SET_DMA_SPD(ep, asc_dvc_varp->cfg->isa_dma_speed);
14181 ep->start_motor = asc_dvc_varp->start_motor;
14182 ep->cntl = asc_dvc_varp->dvc_cntl;
14183 ep->no_scam = asc_dvc_varp->no_scam;
14184 ep->max_total_qng = asc_dvc_varp->max_total_qng;
14185 ASC_EEP_SET_CHIP_ID(ep, asc_dvc_varp->cfg->chip_scsi_id);
14186 /* 'max_tag_qng' is set to the same value for every device. */
14187 ep->max_tag_qng = asc_dvc_varp->cfg->max_tag_qng[0];
14188 ep->adapter_info[0] = asc_dvc_varp->cfg->adapter_info[0];
14189 ep->adapter_info[1] = asc_dvc_varp->cfg->adapter_info[1];
14190 ep->adapter_info[2] = asc_dvc_varp->cfg->adapter_info[2];
14191 ep->adapter_info[3] = asc_dvc_varp->cfg->adapter_info[3];
14192 ep->adapter_info[4] = asc_dvc_varp->cfg->adapter_info[4];
14193 ep->adapter_info[5] = asc_dvc_varp->cfg->adapter_info[5];
14196 * Modify board configuration.
14198 ASC_DBG(2, "advansys_board_found: AscInitSetConfig()\n");
14199 err_code = AscInitSetConfig(pdev, boardp);
14201 goto err_free_proc;
14204 * Finish initializing the 'Scsi_Host' structure.
14206 /* AscInitSetConfig() will set the IRQ for non-PCI boards. */
14207 if ((asc_dvc_varp->bus_type & ASC_IS_PCI) == 0) {
14208 shost->irq = asc_dvc_varp->irq_no;
14211 ADVEEP_3550_CONFIG *ep_3550;
14212 ADVEEP_38C0800_CONFIG *ep_38C0800;
14213 ADVEEP_38C1600_CONFIG *ep_38C1600;
14216 * Save Wide EEP Configuration Information.
14218 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
14219 ep_3550 = &boardp->eep_config.adv_3550_eep;
14221 ep_3550->adapter_scsi_id = adv_dvc_varp->chip_scsi_id;
14222 ep_3550->max_host_qng = adv_dvc_varp->max_host_qng;
14223 ep_3550->max_dvc_qng = adv_dvc_varp->max_dvc_qng;
14224 ep_3550->termination = adv_dvc_varp->cfg->termination;
14225 ep_3550->disc_enable = adv_dvc_varp->cfg->disc_enable;
14226 ep_3550->bios_ctrl = adv_dvc_varp->bios_ctrl;
14227 ep_3550->wdtr_able = adv_dvc_varp->wdtr_able;
14228 ep_3550->sdtr_able = adv_dvc_varp->sdtr_able;
14229 ep_3550->ultra_able = adv_dvc_varp->ultra_able;
14230 ep_3550->tagqng_able = adv_dvc_varp->tagqng_able;
14231 ep_3550->start_motor = adv_dvc_varp->start_motor;
14232 ep_3550->scsi_reset_delay =
14233 adv_dvc_varp->scsi_reset_wait;
14234 ep_3550->serial_number_word1 =
14235 adv_dvc_varp->cfg->serial1;
14236 ep_3550->serial_number_word2 =
14237 adv_dvc_varp->cfg->serial2;
14238 ep_3550->serial_number_word3 =
14239 adv_dvc_varp->cfg->serial3;
14240 } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
14241 ep_38C0800 = &boardp->eep_config.adv_38C0800_eep;
14243 ep_38C0800->adapter_scsi_id =
14244 adv_dvc_varp->chip_scsi_id;
14245 ep_38C0800->max_host_qng = adv_dvc_varp->max_host_qng;
14246 ep_38C0800->max_dvc_qng = adv_dvc_varp->max_dvc_qng;
14247 ep_38C0800->termination_lvd =
14248 adv_dvc_varp->cfg->termination;
14249 ep_38C0800->disc_enable =
14250 adv_dvc_varp->cfg->disc_enable;
14251 ep_38C0800->bios_ctrl = adv_dvc_varp->bios_ctrl;
14252 ep_38C0800->wdtr_able = adv_dvc_varp->wdtr_able;
14253 ep_38C0800->tagqng_able = adv_dvc_varp->tagqng_able;
14254 ep_38C0800->sdtr_speed1 = adv_dvc_varp->sdtr_speed1;
14255 ep_38C0800->sdtr_speed2 = adv_dvc_varp->sdtr_speed2;
14256 ep_38C0800->sdtr_speed3 = adv_dvc_varp->sdtr_speed3;
14257 ep_38C0800->sdtr_speed4 = adv_dvc_varp->sdtr_speed4;
14258 ep_38C0800->tagqng_able = adv_dvc_varp->tagqng_able;
14259 ep_38C0800->start_motor = adv_dvc_varp->start_motor;
14260 ep_38C0800->scsi_reset_delay =
14261 adv_dvc_varp->scsi_reset_wait;
14262 ep_38C0800->serial_number_word1 =
14263 adv_dvc_varp->cfg->serial1;
14264 ep_38C0800->serial_number_word2 =
14265 adv_dvc_varp->cfg->serial2;
14266 ep_38C0800->serial_number_word3 =
14267 adv_dvc_varp->cfg->serial3;
14269 ep_38C1600 = &boardp->eep_config.adv_38C1600_eep;
14271 ep_38C1600->adapter_scsi_id =
14272 adv_dvc_varp->chip_scsi_id;
14273 ep_38C1600->max_host_qng = adv_dvc_varp->max_host_qng;
14274 ep_38C1600->max_dvc_qng = adv_dvc_varp->max_dvc_qng;
14275 ep_38C1600->termination_lvd =
14276 adv_dvc_varp->cfg->termination;
14277 ep_38C1600->disc_enable =
14278 adv_dvc_varp->cfg->disc_enable;
14279 ep_38C1600->bios_ctrl = adv_dvc_varp->bios_ctrl;
14280 ep_38C1600->wdtr_able = adv_dvc_varp->wdtr_able;
14281 ep_38C1600->tagqng_able = adv_dvc_varp->tagqng_able;
14282 ep_38C1600->sdtr_speed1 = adv_dvc_varp->sdtr_speed1;
14283 ep_38C1600->sdtr_speed2 = adv_dvc_varp->sdtr_speed2;
14284 ep_38C1600->sdtr_speed3 = adv_dvc_varp->sdtr_speed3;
14285 ep_38C1600->sdtr_speed4 = adv_dvc_varp->sdtr_speed4;
14286 ep_38C1600->tagqng_able = adv_dvc_varp->tagqng_able;
14287 ep_38C1600->start_motor = adv_dvc_varp->start_motor;
14288 ep_38C1600->scsi_reset_delay =
14289 adv_dvc_varp->scsi_reset_wait;
14290 ep_38C1600->serial_number_word1 =
14291 adv_dvc_varp->cfg->serial1;
14292 ep_38C1600->serial_number_word2 =
14293 adv_dvc_varp->cfg->serial2;
14294 ep_38C1600->serial_number_word3 =
14295 adv_dvc_varp->cfg->serial3;
14299 * Set the adapter's target id bit in the 'init_tidmask' field.
14301 boardp->init_tidmask |=
14302 ADV_TID_TO_TIDMASK(adv_dvc_varp->chip_scsi_id);
14306 * Channels are numbered beginning with 0. For AdvanSys one host
14307 * structure supports one channel. Multi-channel boards have a
14308 * separate host structure for each channel.
14310 shost->max_channel = 0;
14311 if (ASC_NARROW_BOARD(boardp)) {
14312 shost->max_id = ASC_MAX_TID + 1;
14313 shost->max_lun = ASC_MAX_LUN + 1;
14314 shost->max_cmd_len = ASC_MAX_CDB_LEN;
14316 shost->io_port = asc_dvc_varp->iop_base;
14317 boardp->asc_n_io_port = ASC_IOADR_GAP;
14318 shost->this_id = asc_dvc_varp->cfg->chip_scsi_id;
14320 /* Set maximum number of queues the adapter can handle. */
14321 shost->can_queue = asc_dvc_varp->max_total_qng;
14323 shost->max_id = ADV_MAX_TID + 1;
14324 shost->max_lun = ADV_MAX_LUN + 1;
14325 shost->max_cmd_len = ADV_MAX_CDB_LEN;
14328 * Save the I/O Port address and length even though
14329 * I/O ports are not used to access Wide boards.
14330 * Instead the Wide boards are accessed with
14331 * PCI Memory Mapped I/O.
14333 shost->io_port = iop;
14335 shost->this_id = adv_dvc_varp->chip_scsi_id;
14337 /* Set maximum number of queues the adapter can handle. */
14338 shost->can_queue = adv_dvc_varp->max_host_qng;
14342 * Following v1.3.89, 'cmd_per_lun' is no longer needed
14343 * and should be set to zero.
14345 * But because of a bug introduced in v1.3.89 if the driver is
14346 * compiled as a module and 'cmd_per_lun' is zero, the Mid-Level
14347 * SCSI function 'allocate_device' will panic. To allow the driver
14348 * to work as a module in these kernels set 'cmd_per_lun' to 1.
14350 * Note: This is wrong. cmd_per_lun should be set to the depth
14351 * you want on untagged devices always.
14354 shost->cmd_per_lun = 1;
14356 shost->cmd_per_lun = 0;
14360 * Set the maximum number of scatter-gather elements the
14361 * adapter can handle.
14363 if (ASC_NARROW_BOARD(boardp)) {
14365 * Allow two commands with 'sg_tablesize' scatter-gather
14366 * elements to be executed simultaneously. This value is
14367 * the theoretical hardware limit. It may be decreased
14370 shost->sg_tablesize =
14371 (((asc_dvc_varp->max_total_qng - 2) / 2) *
14372 ASC_SG_LIST_PER_Q) + 1;
14374 shost->sg_tablesize = ADV_MAX_SG_LIST;
14378 * The value of 'sg_tablesize' can not exceed the SCSI
14379 * mid-level driver definition of SG_ALL. SG_ALL also
14380 * must not be exceeded, because it is used to define the
14381 * size of the scatter-gather table in 'struct asc_sg_head'.
14383 if (shost->sg_tablesize > SG_ALL) {
14384 shost->sg_tablesize = SG_ALL;
14387 ASC_DBG1(1, "advansys_board_found: sg_tablesize: %d\n", shost->sg_tablesize);
14389 /* BIOS start address. */
14390 if (ASC_NARROW_BOARD(boardp)) {
14391 shost->base = AscGetChipBiosAddress(asc_dvc_varp->iop_base,
14392 asc_dvc_varp->bus_type);
14395 * Fill-in BIOS board variables. The Wide BIOS saves
14396 * information in LRAM that is used by the driver.
14398 AdvReadWordLram(adv_dvc_varp->iop_base,
14399 BIOS_SIGNATURE, boardp->bios_signature);
14400 AdvReadWordLram(adv_dvc_varp->iop_base,
14401 BIOS_VERSION, boardp->bios_version);
14402 AdvReadWordLram(adv_dvc_varp->iop_base,
14403 BIOS_CODESEG, boardp->bios_codeseg);
14404 AdvReadWordLram(adv_dvc_varp->iop_base,
14405 BIOS_CODELEN, boardp->bios_codelen);
14408 "advansys_board_found: bios_signature 0x%x, bios_version 0x%x\n",
14409 boardp->bios_signature, boardp->bios_version);
14412 "advansys_board_found: bios_codeseg 0x%x, bios_codelen 0x%x\n",
14413 boardp->bios_codeseg, boardp->bios_codelen);
14416 * If the BIOS saved a valid signature, then fill in
14417 * the BIOS code segment base address.
14419 if (boardp->bios_signature == 0x55AA) {
14421 * Convert x86 realmode code segment to a linear
14422 * address by shifting left 4.
14424 shost->base = ((ulong)boardp->bios_codeseg << 4);
14431 * Register Board Resources - I/O Port, DMA, IRQ
14434 /* Register DMA Channel for Narrow boards. */
14435 shost->dma_channel = NO_ISA_DMA; /* Default to no ISA DMA. */
14437 if (ASC_NARROW_BOARD(boardp)) {
14438 /* Register DMA channel for ISA bus. */
14439 if (asc_dvc_varp->bus_type & ASC_IS_ISA) {
14440 shost->dma_channel = asc_dvc_varp->cfg->isa_dma_channel;
14441 ret = request_dma(shost->dma_channel, DRV_NAME);
14444 ("advansys_board_found: board %d: request_dma() %d failed %d\n",
14445 boardp->id, shost->dma_channel, ret);
14446 goto err_free_proc;
14448 AscEnableIsaDma(shost->dma_channel);
14451 #endif /* CONFIG_ISA */
14453 /* Register IRQ Number. */
14454 ASC_DBG1(2, "advansys_board_found: request_irq() %d\n", shost->irq);
14456 ret = request_irq(shost->irq, advansys_interrupt, share_irq,
14460 if (ret == -EBUSY) {
14462 ("advansys_board_found: board %d: request_irq(): IRQ 0x%x already in use.\n",
14463 boardp->id, shost->irq);
14464 } else if (ret == -EINVAL) {
14466 ("advansys_board_found: board %d: request_irq(): IRQ 0x%x not valid.\n",
14467 boardp->id, shost->irq);
14470 ("advansys_board_found: board %d: request_irq(): IRQ 0x%x failed with %d\n",
14471 boardp->id, shost->irq, ret);
14477 * Initialize board RISC chip and enable interrupts.
14479 if (ASC_NARROW_BOARD(boardp)) {
14480 ASC_DBG(2, "advansys_board_found: AscInitAsc1000Driver()\n");
14481 warn_code = AscInitAsc1000Driver(asc_dvc_varp);
14482 err_code = asc_dvc_varp->err_code;
14484 if (warn_code || err_code) {
14486 ("advansys_board_found: board %d error: init_state 0x%x, warn 0x%x, error 0x%x\n",
14488 asc_dvc_varp->init_state, warn_code, err_code);
14491 err_code = advansys_wide_init_chip(boardp, adv_dvc_varp);
14495 goto err_free_wide_mem;
14497 ASC_DBG_PRT_SCSI_HOST(2, shost);
14499 ret = scsi_add_host(shost, dev);
14501 goto err_free_wide_mem;
14503 scsi_scan_host(shost);
14507 advansys_wide_free_mem(boardp);
14508 free_irq(shost->irq, shost);
14510 if (shost->dma_channel != NO_ISA_DMA)
14511 free_dma(shost->dma_channel);
14513 kfree(boardp->prtbuf);
14515 if (boardp->ioremap_addr)
14516 iounmap(boardp->ioremap_addr);
14518 scsi_host_put(shost);
14523 * advansys_release()
14525 * Release resources allocated for a single AdvanSys adapter.
14527 static int advansys_release(struct Scsi_Host *shost)
14529 asc_board_t *boardp;
14531 ASC_DBG(1, "advansys_release: begin\n");
14532 scsi_remove_host(shost);
14533 boardp = ASC_BOARDP(shost);
14534 free_irq(shost->irq, shost);
14535 if (shost->dma_channel != NO_ISA_DMA) {
14536 ASC_DBG(1, "advansys_release: free_dma()\n");
14537 free_dma(shost->dma_channel);
14539 if (ASC_WIDE_BOARD(boardp)) {
14540 iounmap(boardp->ioremap_addr);
14541 advansys_wide_free_mem(boardp);
14543 kfree(boardp->prtbuf);
14544 scsi_host_put(shost);
14545 ASC_DBG(1, "advansys_release: end\n");
14549 #define ASC_IOADR_TABLE_MAX_IX 11
14551 static PortAddr _asc_def_iop_base[ASC_IOADR_TABLE_MAX_IX] __devinitdata = {
14552 0x100, 0x0110, 0x120, 0x0130, 0x140, 0x0150, 0x0190,
14553 0x0210, 0x0230, 0x0250, 0x0330
14556 static int __devinit advansys_isa_probe(struct device *dev, unsigned int id)
14558 PortAddr iop_base = _asc_def_iop_base[id];
14559 struct Scsi_Host *shost;
14561 if (!request_region(iop_base, ASC_IOADR_GAP, DRV_NAME)) {
14562 ASC_DBG1(1, "advansys_isa_match: I/O port 0x%x busy\n",
14566 ASC_DBG1(1, "advansys_isa_match: probing I/O port 0x%x\n", iop_base);
14567 if (!AscFindSignature(iop_base))
14569 if (!(AscGetChipVersion(iop_base, ASC_IS_ISA) & ASC_CHIP_VER_ISA_BIT))
14572 shost = advansys_board_found(iop_base, dev, ASC_IS_ISA);
14576 dev_set_drvdata(dev, shost);
14580 release_region(iop_base, ASC_IOADR_GAP);
14584 static int __devexit advansys_isa_remove(struct device *dev, unsigned int id)
14586 int ioport = _asc_def_iop_base[id];
14587 advansys_release(dev_get_drvdata(dev));
14588 release_region(ioport, ASC_IOADR_GAP);
14592 static struct isa_driver advansys_isa_driver = {
14593 .probe = advansys_isa_probe,
14594 .remove = __devexit_p(advansys_isa_remove),
14596 .owner = THIS_MODULE,
14601 static int __devinit advansys_vlb_probe(struct device *dev, unsigned int id)
14603 PortAddr iop_base = _asc_def_iop_base[id];
14604 struct Scsi_Host *shost;
14606 if (!request_region(iop_base, ASC_IOADR_GAP, DRV_NAME)) {
14607 ASC_DBG1(1, "advansys_vlb_match: I/O port 0x%x busy\n",
14611 ASC_DBG1(1, "advansys_vlb_match: probing I/O port 0x%x\n", iop_base);
14612 if (!AscFindSignature(iop_base))
14615 * I don't think this condition can actually happen, but the old
14616 * driver did it, and the chances of finding a VLB setup in 2007
14617 * to do testing with is slight to none.
14619 if (AscGetChipVersion(iop_base, ASC_IS_VL) > ASC_CHIP_MAX_VER_VL)
14622 shost = advansys_board_found(iop_base, dev, ASC_IS_VL);
14626 dev_set_drvdata(dev, shost);
14630 release_region(iop_base, ASC_IOADR_GAP);
14634 static struct isa_driver advansys_vlb_driver = {
14635 .probe = advansys_vlb_probe,
14636 .remove = __devexit_p(advansys_isa_remove),
14638 .owner = THIS_MODULE,
14639 .name = "advansys_vlb",
14643 static struct eisa_device_id advansys_eisa_table[] __devinitdata = {
14649 MODULE_DEVICE_TABLE(eisa, advansys_eisa_table);
14652 * EISA is a little more tricky than PCI; each EISA device may have two
14653 * channels, and this driver is written to make each channel its own Scsi_Host
14655 struct eisa_scsi_data {
14656 struct Scsi_Host *host[2];
14659 static int __devinit advansys_eisa_probe(struct device *dev)
14663 struct eisa_device *edev = to_eisa_device(dev);
14664 struct eisa_scsi_data *data;
14667 data = kzalloc(sizeof(*data), GFP_KERNEL);
14670 ioport = edev->base_addr + 0xc30;
14673 for (i = 0; i < 2; i++, ioport += 0x20) {
14674 if (!request_region(ioport, ASC_IOADR_GAP, DRV_NAME)) {
14675 printk(KERN_WARNING "Region %x-%x busy\n", ioport,
14676 ioport + ASC_IOADR_GAP - 1);
14679 if (!AscFindSignature(ioport)) {
14680 release_region(ioport, ASC_IOADR_GAP);
14685 * I don't know why we need to do this for EISA chips, but
14686 * not for any others. It looks to be equivalent to
14687 * AscGetChipCfgMsw, but I may have overlooked something,
14688 * so I'm not converting it until I get an EISA board to
14692 data->host[i] = advansys_board_found(ioport, dev, ASC_IS_EISA);
14693 if (data->host[i]) {
14696 release_region(ioport, ASC_IOADR_GAP);
14703 dev_set_drvdata(dev, data);
14710 static __devexit int advansys_eisa_remove(struct device *dev)
14713 struct eisa_scsi_data *data = dev_get_drvdata(dev);
14715 for (i = 0; i < 2; i++) {
14717 struct Scsi_Host *shost = data->host[i];
14720 ioport = shost->io_port;
14721 advansys_release(shost);
14722 release_region(ioport, ASC_IOADR_GAP);
14729 static struct eisa_driver advansys_eisa_driver = {
14730 .id_table = advansys_eisa_table,
14733 .probe = advansys_eisa_probe,
14734 .remove = __devexit_p(advansys_eisa_remove),
14738 /* PCI Devices supported by this driver */
14739 static struct pci_device_id advansys_pci_tbl[] __devinitdata = {
14740 {PCI_VENDOR_ID_ASP, PCI_DEVICE_ID_ASP_1200A,
14741 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
14742 {PCI_VENDOR_ID_ASP, PCI_DEVICE_ID_ASP_ABP940,
14743 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
14744 {PCI_VENDOR_ID_ASP, PCI_DEVICE_ID_ASP_ABP940U,
14745 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
14746 {PCI_VENDOR_ID_ASP, PCI_DEVICE_ID_ASP_ABP940UW,
14747 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
14748 {PCI_VENDOR_ID_ASP, PCI_DEVICE_ID_38C0800_REV1,
14749 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
14750 {PCI_VENDOR_ID_ASP, PCI_DEVICE_ID_38C1600_REV1,
14751 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
14755 MODULE_DEVICE_TABLE(pci, advansys_pci_tbl);
14757 static void __devinit advansys_set_latency(struct pci_dev *pdev)
14759 if ((pdev->device == PCI_DEVICE_ID_ASP_1200A) ||
14760 (pdev->device == PCI_DEVICE_ID_ASP_ABP940)) {
14761 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0);
14764 pci_read_config_byte(pdev, PCI_LATENCY_TIMER, &latency);
14765 if (latency < 0x20)
14766 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0x20);
14770 static int __devinit
14771 advansys_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
14774 struct Scsi_Host *shost;
14776 err = pci_enable_device(pdev);
14779 err = pci_request_regions(pdev, DRV_NAME);
14781 goto disable_device;
14782 pci_set_master(pdev);
14783 advansys_set_latency(pdev);
14785 if (pci_resource_len(pdev, 0) == 0)
14788 ioport = pci_resource_start(pdev, 0);
14789 shost = advansys_board_found(ioport, &pdev->dev, ASC_IS_PCI);
14794 pci_set_drvdata(pdev, shost);
14799 pci_release_regions(pdev);
14801 pci_disable_device(pdev);
14806 static void __devexit advansys_pci_remove(struct pci_dev *pdev)
14808 advansys_release(pci_get_drvdata(pdev));
14809 pci_release_regions(pdev);
14810 pci_disable_device(pdev);
14813 static struct pci_driver advansys_pci_driver = {
14815 .id_table = advansys_pci_tbl,
14816 .probe = advansys_pci_probe,
14817 .remove = __devexit_p(advansys_pci_remove),
14820 static int __init advansys_init(void)
14824 error = isa_register_driver(&advansys_isa_driver,
14825 ASC_IOADR_TABLE_MAX_IX);
14829 error = isa_register_driver(&advansys_vlb_driver,
14830 ASC_IOADR_TABLE_MAX_IX);
14832 goto unregister_isa;
14834 error = eisa_driver_register(&advansys_eisa_driver);
14836 goto unregister_vlb;
14838 error = pci_register_driver(&advansys_pci_driver);
14840 goto unregister_eisa;
14845 eisa_driver_unregister(&advansys_eisa_driver);
14847 isa_unregister_driver(&advansys_vlb_driver);
14849 isa_unregister_driver(&advansys_isa_driver);
14854 static void __exit advansys_exit(void)
14856 pci_unregister_driver(&advansys_pci_driver);
14857 eisa_driver_unregister(&advansys_eisa_driver);
14858 isa_unregister_driver(&advansys_vlb_driver);
14859 isa_unregister_driver(&advansys_isa_driver);
14862 module_init(advansys_init);
14863 module_exit(advansys_exit);
14865 MODULE_LICENSE("GPL");