1 #define ASC_VERSION "3.4" /* AdvanSys Driver Version */
4 * advansys.c - Linux Host Driver for AdvanSys SCSI Adapters
6 * Copyright (c) 1995-2000 Advanced System Products, Inc.
7 * Copyright (c) 2000-2001 ConnectCom Solutions, Inc.
8 * Copyright (c) 2007 Matthew Wilcox <matthew@wil.cx>
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
18 * As of March 8, 2000 Advanced System Products, Inc. (AdvanSys)
19 * changed its name to ConnectCom Solutions, Inc.
20 * On June 18, 2001 Initio Corp. acquired ConnectCom's SCSI assets
25 Documentation for the AdvanSys Driver
27 A. Linux Kernels Supported by this Driver
28 B. Adapters Supported by this Driver
29 C. Linux source files modified by AdvanSys Driver
31 E. Driver Compile Time Options and Debugging
33 G. Tests to run before releasing new driver
35 I. Known Problems/Fix List
36 J. Credits (Chronological Order)
38 A. Linux Kernels Supported by this Driver
40 This driver has been tested in the following Linux kernels: v2.2.18
41 v2.4.0. The driver is supported on v2.2 and v2.4 kernels and on x86,
42 alpha, and PowerPC platforms.
44 B. Adapters Supported by this Driver
46 AdvanSys (Advanced System Products, Inc.) manufactures the following
47 RISC-based, Bus-Mastering, Fast (10 Mhz) and Ultra (20 Mhz) Narrow
48 (8-bit transfer) SCSI Host Adapters for the ISA, EISA, VL, and PCI
49 buses and RISC-based, Bus-Mastering, Ultra (20 Mhz) Wide (16-bit
50 transfer) SCSI Host Adapters for the PCI bus.
52 The CDB counts below indicate the number of SCSI CDB (Command
53 Descriptor Block) requests that can be stored in the RISC chip
54 cache and board LRAM. A CDB is a single SCSI command. The driver
55 detect routine will display the number of CDBs available for each
56 adapter detected. The number of CDBs used by the driver can be
57 lowered in the BIOS by changing the 'Host Queue Size' adapter setting.
60 ABP-480 - Bus-Master CardBus (16 CDB) (2.4 kernel and greater)
62 Connectivity Products:
63 ABP510/5150 - Bus-Master ISA (240 CDB)
64 ABP5140 - Bus-Master ISA PnP (16 CDB)
65 ABP5142 - Bus-Master ISA PnP with floppy (16 CDB)
66 ABP902/3902 - Bus-Master PCI (16 CDB)
67 ABP3905 - Bus-Master PCI (16 CDB)
68 ABP915 - Bus-Master PCI (16 CDB)
69 ABP920 - Bus-Master PCI (16 CDB)
70 ABP3922 - Bus-Master PCI (16 CDB)
71 ABP3925 - Bus-Master PCI (16 CDB)
72 ABP930 - Bus-Master PCI (16 CDB)
73 ABP930U - Bus-Master PCI Ultra (16 CDB)
74 ABP930UA - Bus-Master PCI Ultra (16 CDB)
75 ABP960 - Bus-Master PCI MAC/PC (16 CDB)
76 ABP960U - Bus-Master PCI MAC/PC Ultra (16 CDB)
78 Single Channel Products:
79 ABP542 - Bus-Master ISA with floppy (240 CDB)
80 ABP742 - Bus-Master EISA (240 CDB)
81 ABP842 - Bus-Master VL (240 CDB)
82 ABP940 - Bus-Master PCI (240 CDB)
83 ABP940U - Bus-Master PCI Ultra (240 CDB)
84 ABP940UA/3940UA - Bus-Master PCI Ultra (240 CDB)
85 ABP970 - Bus-Master PCI MAC/PC (240 CDB)
86 ABP970U - Bus-Master PCI MAC/PC Ultra (240 CDB)
87 ABP3960UA - Bus-Master PCI MAC/PC Ultra (240 CDB)
88 ABP940UW/3940UW - Bus-Master PCI Ultra-Wide (253 CDB)
89 ABP970UW - Bus-Master PCI MAC/PC Ultra-Wide (253 CDB)
90 ABP3940U2W - Bus-Master PCI LVD/Ultra2-Wide (253 CDB)
92 Multi-Channel Products:
93 ABP752 - Dual Channel Bus-Master EISA (240 CDB Per Channel)
94 ABP852 - Dual Channel Bus-Master VL (240 CDB Per Channel)
95 ABP950 - Dual Channel Bus-Master PCI (240 CDB Per Channel)
96 ABP950UW - Dual Channel Bus-Master PCI Ultra-Wide (253 CDB Per Channel)
97 ABP980 - Four Channel Bus-Master PCI (240 CDB Per Channel)
98 ABP980U - Four Channel Bus-Master PCI Ultra (240 CDB Per Channel)
99 ABP980UA/3980UA - Four Channel Bus-Master PCI Ultra (16 CDB Per Chan.)
100 ABP3950U2W - Bus-Master PCI LVD/Ultra2-Wide and Ultra-Wide (253 CDB)
101 ABP3950U3W - Bus-Master PCI Dual LVD2/Ultra3-Wide (253 CDB)
103 C. Linux source files modified by AdvanSys Driver
105 This section for historical purposes documents the changes
106 originally made to the Linux kernel source to add the advansys
107 driver. As Linux has changed some of these files have also
110 1. linux/arch/i386/config.in:
112 bool 'AdvanSys SCSI support' CONFIG_SCSI_ADVANSYS y
114 2. linux/drivers/scsi/hosts.c:
116 #ifdef CONFIG_SCSI_ADVANSYS
117 #include "advansys.h"
120 and after "static struct scsi_host_template builtin_scsi_hosts[] =":
122 #ifdef CONFIG_SCSI_ADVANSYS
126 3. linux/drivers/scsi/Makefile:
128 ifdef CONFIG_SCSI_ADVANSYS
129 SCSI_SRCS := $(SCSI_SRCS) advansys.c
130 SCSI_OBJS := $(SCSI_OBJS) advansys.o
132 SCSI_MODULE_OBJS := $(SCSI_MODULE_OBJS) advansys.o
135 4. linux/init/main.c:
137 extern void advansys_setup(char *str, int *ints);
139 and add the following lines to the bootsetups[] array.
141 #ifdef CONFIG_SCSI_ADVANSYS
142 { "advansys=", advansys_setup },
147 1. Use tab stops set to 4 for the source files. For vi use 'se tabstops=4'.
149 2. This driver should be maintained in multiple files. But to make
150 it easier to include with Linux and to follow Linux conventions,
151 the whole driver is maintained in the source files advansys.h and
152 advansys.c. In this file logical sections of the driver begin with
153 a comment that contains '---'. The following are the logical sections
157 --- Linux Include File
160 --- Asc Library Constants and Macros
161 --- Adv Library Constants and Macros
162 --- Driver Constants and Macros
163 --- Driver Structures
165 --- Driver Function Prototypes
166 --- Linux 'struct scsi_host_template' and advansys_setup() Functions
167 --- Loadable Driver Support
168 --- Miscellaneous Driver Functions
169 --- Functions Required by the Asc Library
170 --- Functions Required by the Adv Library
171 --- Tracing and Debugging Functions
172 --- Asc Library Functions
173 --- Adv Library Functions
175 3. The string 'XXX' is used to flag code that needs to be re-written
176 or that contains a problem that needs to be addressed.
178 4. I have stripped comments from and reformatted the source for the
179 Asc Library and Adv Library to reduce the size of this file. This
180 source can be found under the following headings. The Asc Library
181 is used to support Narrow Boards. The Adv Library is used to
184 --- Asc Library Constants and Macros
185 --- Adv Library Constants and Macros
186 --- Asc Library Functions
187 --- Adv Library Functions
189 E. Driver Compile Time Options and Debugging
191 In this source file the following constants can be defined. They are
192 defined in the source below. Both of these options are enabled by
195 1. ADVANSYS_ASSERT - Enable driver assertions (Def: Enabled)
197 Enabling this option adds assertion logic statements to the
198 driver. If an assertion fails a message will be displayed to
199 the console, but the system will continue to operate. Any
200 assertions encountered should be reported to the person
201 responsible for the driver. Assertion statements may proactively
202 detect problems with the driver and facilitate fixing these
203 problems. Enabling assertions will add a small overhead to the
204 execution of the driver.
206 2. ADVANSYS_DEBUG - Enable driver debugging (Def: Disabled)
208 Enabling this option adds tracing functions to the driver and
209 the ability to set a driver tracing level at boot time. This
210 option will also export symbols not required outside the driver to
211 the kernel name space. This option is very useful for debugging
212 the driver, but it will add to the size of the driver execution
213 image and add overhead to the execution of the driver.
215 The amount of debugging output can be controlled with the global
216 variable 'asc_dbglvl'. The higher the number the more output. By
217 default the debug level is 0.
219 If the driver is loaded at boot time and the LILO Driver Option
220 is included in the system, the debug level can be changed by
221 specifying a 5th (ASC_NUM_IOPORT_PROBE + 1) I/O Port. The
222 first three hex digits of the pseudo I/O Port must be set to
223 'deb' and the fourth hex digit specifies the debug level: 0 - F.
224 The following command line will look for an adapter at 0x330
225 and set the debug level to 2.
227 linux advansys=0x330,0,0,0,0xdeb2
229 If the driver is built as a loadable module this variable can be
230 defined when the driver is loaded. The following insmod command
231 will set the debug level to one.
233 insmod advansys.o asc_dbglvl=1
235 Debugging Message Levels:
237 1: High-Level Tracing
240 To enable debug output to console, please make sure that:
242 a. System and kernel logging is enabled (syslogd, klogd running).
243 b. Kernel messages are routed to console output. Check
244 /etc/syslog.conf for an entry similar to this:
248 c. klogd is started with the appropriate -c parameter
251 This will cause printk() messages to be be displayed on the
252 current console. Refer to the klogd(8) and syslogd(8) man pages
255 Alternatively you can enable printk() to console with this
256 program. However, this is not the 'official' way to do this.
257 Debug output is logged in /var/log/messages.
261 syscall(103, 7, 0, 0);
264 Increasing LOG_BUF_LEN in kernel/printk.c to something like
265 40960 allows more debug messages to be buffered in the kernel
266 and written to the console or log file.
268 3. ADVANSYS_STATS - Enable statistics (Def: Enabled >= v1.3.0)
270 Enabling this option adds statistics collection and display
271 through /proc to the driver. The information is useful for
272 monitoring driver and device performance. It will add to the
273 size of the driver execution image and add minor overhead to
274 the execution of the driver.
276 Statistics are maintained on a per adapter basis. Driver entry
277 point call counts and transfer size counts are maintained.
278 Statistics are only available for kernels greater than or equal
279 to v1.3.0 with the CONFIG_PROC_FS (/proc) file system configured.
281 AdvanSys SCSI adapter files have the following path name format:
283 /proc/scsi/advansys/[0-(ASC_NUM_BOARD_SUPPORTED-1)]
285 This information can be displayed with cat. For example:
287 cat /proc/scsi/advansys/0
289 When ADVANSYS_STATS is not defined the AdvanSys /proc files only
290 contain adapter and device configuration information.
292 F. Driver LILO Option
294 If init/main.c is modified as described in the 'Directions for Adding
295 the AdvanSys Driver to Linux' section (B.4.) above, the driver will
296 recognize the 'advansys' LILO command line and /etc/lilo.conf option.
297 This option can be used to either disable I/O port scanning or to limit
298 scanning to 1 - 4 I/O ports. Regardless of the option setting EISA and
299 PCI boards will still be searched for and detected. This option only
300 affects searching for ISA and VL boards.
303 1. Eliminate I/O port scanning:
304 boot: linux advansys=
306 boot: linux advansys=0x0
307 2. Limit I/O port scanning to one I/O port:
308 boot: linux advansys=0x110
309 3. Limit I/O port scanning to four I/O ports:
310 boot: linux advansys=0x110,0x210,0x230,0x330
312 For a loadable module the same effect can be achieved by setting
313 the 'asc_iopflag' variable and 'asc_ioport' array when loading
316 insmod advansys.o asc_iopflag=1 asc_ioport=0x110,0x330
318 If ADVANSYS_DEBUG is defined a 5th (ASC_NUM_IOPORT_PROBE + 1)
319 I/O Port may be added to specify the driver debug level. Refer to
320 the 'Driver Compile Time Options and Debugging' section above for
323 G. Tests to run before releasing new driver
325 1. In the supported kernels verify there are no warning or compile
326 errors when the kernel is built as both a driver and as a module
327 and with the following options:
329 ADVANSYS_DEBUG - enabled and disabled
330 CONFIG_SMP - enabled and disabled
331 CONFIG_PROC_FS - enabled and disabled
333 2. Run tests on an x86, alpha, and PowerPC with at least one narrow
334 card and one wide card attached to a hard disk and CD-ROM drive:
335 fdisk, mkfs, fsck, bonnie, copy/compare test from the
336 CD-ROM to the hard drive.
344 1. Prevent advansys_detect() from being called twice.
345 2. Add LILO 0xdeb[0-f] option to set 'asc_dbglvl'.
348 1. Prevent re-entrancy in the interrupt handler which
349 resulted in the driver hanging Linux.
350 2. Fix problem that prevented ABP-940 cards from being
351 recognized on some PCI motherboards.
352 3. Add support for the ABP-5140 PnP ISA card.
353 4. Fix check condition return status.
354 5. Add conditionally compiled code for Linux v1.3.X.
357 1. Fix problem in advansys_biosparam() that resulted in the
358 wrong drive geometry being returned for drives > 1GB with
359 extended translation enabled.
360 2. Add additional tracing during device initialization.
361 3. Change code that only applies to ISA PnP adapter.
362 4. Eliminate 'make dep' warning.
363 5. Try to fix problem with handling resets by increasing their
367 1. Change definitions to eliminate conflicts with other subsystems.
368 2. Add versioning code for the shared interrupt changes.
369 3. Eliminate problem in asc_rmqueue() with iterating after removing
371 4. Remove reset request loop problem from the "Known Problems or
372 Issues" section. This problem was isolated and fixed in the
373 mid-level SCSI driver.
376 1. Add support for ABP-940U (PCI Ultra) adapter.
377 2. Add support for IRQ sharing by setting the IRQF_SHARED flag for
378 request_irq and supplying a dev_id pointer to both request_irq()
380 3. In AscSearchIOPortAddr11() restore a call to check_region() which
381 should be used before I/O port probing.
382 4. Fix bug in asc_prt_hex() which resulted in the displaying
384 5. Incorporate miscellaneous Asc Library bug fixes and new microcode.
385 6. Change driver versioning to be specific to each Linux sub-level.
386 7. Change statistics gathering to be per adapter instead of global
388 8. Add more information and statistics to the adapter /proc file:
389 /proc/scsi/advansys[0...].
390 9. Remove 'cmd_per_lun' from the "Known Problems or Issues" list.
391 This problem has been addressed with the SCSI mid-level changes
392 made in v1.3.89. The advansys_select_queue_depths() function
393 was added for the v1.3.89 changes.
396 1. Incorporate miscellaneous Asc Library bug fixes and new microcode.
399 1. Enable clustering and optimize the setting of the maximum number
400 of scatter gather elements for any particular board. Clustering
401 increases CPU utilization, but results in a relatively larger
402 increase in I/O throughput.
403 2. Improve the performance of the request queuing functions by
404 adding a last pointer to the queue structure.
405 3. Correct problems with reset and abort request handling that
406 could have hung or crashed Linux.
407 4. Add more information to the adapter /proc file:
408 /proc/scsi/advansys[0...].
409 5. Remove the request timeout issue form the driver issues list.
410 6. Miscellaneous documentation additions and changes.
413 1. Make changes to handle the new v2.1.0 kernel memory mapping
414 in which a kernel virtual address may not be equivalent to its
415 bus or DMA memory address.
416 2. Change abort and reset request handling to make it yet even
418 3. Try to mitigate request starvation by sending ordered requests
419 to heavily loaded, tag queuing enabled devices.
420 4. Maintain statistics on request response time.
421 5. Add request response time statistics and other information to
422 the adapter /proc file: /proc/scsi/advansys[0...].
425 1. Add conditionally compiled code (ASC_QUEUE_FLOW_CONTROL) to
426 make use of mid-level SCSI driver device queue depth flow
427 control mechanism. This will eliminate aborts caused by a
428 device being unable to keep up with requests and eliminate
429 repeat busy or QUEUE FULL status returned by a device.
430 2. Incorporate miscellaneous Asc Library bug fixes.
431 3. To allow the driver to work in kernels with broken module
432 support set 'cmd_per_lun' if the driver is compiled as a
433 module. This change affects kernels v1.3.89 to present.
434 4. Remove PCI BIOS address from the driver banner. The PCI BIOS
435 is relocated by the motherboard BIOS and its new address can
436 not be determined by the driver.
437 5. Add mid-level SCSI queue depth information to the adapter
438 /proc file: /proc/scsi/advansys[0...].
441 1. Change allocation of global structures used for device
442 initialization to guarantee they are in DMA-able memory.
443 Previously when the driver was loaded as a module these
444 structures might not have been in DMA-able memory, causing
445 device initialization to fail.
448 1. In advansys_reset(), if the request is a synchronous reset
449 request, even if the request serial number has changed, then
450 complete the request.
451 2. Add Asc Library bug fixes including new microcode.
452 3. Clear inquiry buffer before using it.
453 4. Correct ifdef typo.
456 1. Add Asc Library bug fixes including new microcode.
457 2. Add synchronous data transfer rate information to the
458 adapter /proc file: /proc/scsi/advansys[0...].
459 3. Change ADVANSYS_DEBUG to be disabled by default. This
460 will reduce the size of the driver image, eliminate execution
461 overhead, and remove unneeded symbols from the kernel symbol
462 space that were previously added by the driver.
463 4. Add new compile-time option ADVANSYS_ASSERT for assertion
464 code that used to be defined within ADVANSYS_DEBUG. This
465 option is enabled by default.
468 1. Change version number to 2.8 to synchronize the Linux driver
469 version numbering with other AdvanSys drivers.
470 2. Reformat source files without tabs to present the same view
471 of the file to everyone regardless of the editor tab setting
473 3. Add Asc Library bug fixes.
476 1. Change version number to 3.1 to indicate that support for
477 Ultra-Wide adapters (ABP-940UW) is included in this release.
478 2. Add Asc Library (Narrow Board) bug fixes.
479 3. Report an underrun condition with the host status byte set
480 to DID_UNDERRUN. Currently DID_UNDERRUN is defined to 0 which
481 causes the underrun condition to be ignored. When Linux defines
482 its own DID_UNDERRUN the constant defined in this file can be
484 4. Add patch to AscWaitTixISRDone().
485 5. Add support for up to 16 different AdvanSys host adapter SCSI
486 channels in one system. This allows four cards with four channels
487 to be used in one system.
490 1. Handle that PCI register base addresses are not always page
491 aligned even though ioremap() requires that the address argument
495 1. Update latest BIOS version checked for from the /proc file.
496 2. Don't set microcode SDTR variable at initialization. Instead
497 wait until device capabilities have been detected from an Inquiry
501 1. Improve performance when the driver is compiled as module by
502 allowing up to 64 scatter-gather elements instead of 8.
505 1. Set time delay in AscWaitTixISRDone() to 1000 ms.
506 2. Include SMP locking changes.
507 3. For v2.1.93 and newer kernels use CONFIG_PCI and new PCI BIOS
509 4. Update board serial number printing.
510 5. Try allocating an IRQ both with and without the IRQF_DISABLED
511 flag set to allow IRQ sharing with drivers that do not set
512 the IRQF_DISABLED flag. Also display a more descriptive error
513 message if request_irq() fails.
514 6. Update to latest Asc and Adv Libraries.
517 1. Update Adv Library to 4.16 which includes support for
518 the ASC38C0800 (Ultra2/LVD) IC.
521 1. Correct PCI compile time option for v2.1.93 and greater
522 kernels, advansys_info() string, and debug compile time
524 2. Correct DvcSleepMilliSecond() for v2.1.0 and greater
525 kernels. This caused an LVD detection/BIST problem problem
527 3. Sort PCI cards by PCI Bus, Slot, Function ascending order
528 to be consistent with the BIOS.
529 4. Update to Asc Library S121 and Adv Library 5.2.
532 1. Correct PCI card detection bug introduced in 3.2B that
533 prevented PCI cards from being detected in kernels older
537 1. Correct /proc device synchronous speed information display.
538 Also when re-negotiation is pending for a target device
539 note this condition with an * and footnote.
540 2. Correct initialization problem with Ultra-Wide cards that
541 have a pre-3.2 BIOS. A microcode variable changed locations
542 in 3.2 and greater BIOSes which caused WDTR to be attempted
543 erroneously with drives that don't support WDTR.
546 1. Fix compile error caused by v2.3.13 PCI structure change.
547 2. Remove field from ASCEEP_CONFIG that resulted in an EEPROM
548 checksum error for ISA cards.
549 3. Remove ASC_QUEUE_FLOW_CONTROL conditional code. The mid-level
550 SCSI changes that it depended on were never included in Linux.
553 1. Handle new initial function code added in v2.3.16 for all
557 1. Fix PCI board detection in v2.3.13 and greater kernels.
558 2. Fix comiple errors in v2.3.X with debugging enabled.
561 1. Add 64-bit address, long support for Alpha and UltraSPARC.
562 The driver has been verified to work on an Alpha system.
563 2. Add partial byte order handling support for Power PC and
564 other big-endian platforms. This support has not yet been
565 completed or verified.
566 3. For wide boards replace block zeroing of request and
567 scatter-gather structures with individual field initialization
568 to improve performance.
569 4. Correct and clarify ROM BIOS version detection.
572 1. Update to Adv Library 5.4.
573 2. Add v2.3.19 underrun reporting to asc_isr_callback() and
574 adv_isr_callback(). Remove DID_UNDERRUN constant and other
575 no longer needed code that previously documented the lack
576 of underrun handling.
579 1. Eliminate compile errors for v2.0 and earlier kernels.
582 1. Correct debug compile error in asc_prt_adv_scsi_req_q().
583 2. Update Adv Library to 5.5.
584 3. Add ifdef handling for /proc changes added in v2.3.28.
585 4. Increase Wide board scatter-gather list maximum length to
586 255 when the driver is compiled into the kernel.
589 1. Fix bug in adv_get_sglist() that caused an assertion failure
590 at line 7475. The reqp->sgblkp pointer must be initialized
591 to NULL in adv_get_sglist().
594 1. Really fix bug in adv_get_sglist().
595 2. Incorporate v2.3.29 changes into driver.
598 1. Add CONFIG_ISA ifdef code.
599 2. Include advansys_interrupts_enabled name change patch.
600 3. For >= v2.3.28 use new SCSI error handling with new function
601 advansys_eh_bus_reset(). Don't include an abort function
602 because of base library limitations.
603 4. For >= v2.3.28 use per board lock instead of io_request_lock.
604 5. For >= v2.3.28 eliminate advansys_command() and
605 advansys_command_done().
606 6. Add some changes for PowerPC (Big Endian) support, but it isn't
608 7. Fix "nonexistent resource free" problem that occurred on a module
609 unload for boards with an I/O space >= 255. The 'n_io_port' field
610 is only one byte and can not be used to hold an ioport length more
614 1. Update to Adv Library 5.8.
615 2. For wide cards add support for CDBs up to 16 bytes.
616 3. Eliminate warnings when CONFIG_PROC_FS is not defined.
619 1. Support for PowerPC (Big Endian) wide cards. Narrow cards
621 2. Change bitfields to shift and mask access for endian
625 1. Update for latest 2.4 kernel.
626 2. Test ABP-480 CardBus support in 2.4 kernel - works!
627 3. Update to Asc Library S123.
628 4. Update to Adv Library 5.12.
631 1. Update for latest 2.4 kernel.
632 2. Create patches for 2.2 and 2.4 kernels.
635 1. Now that 2.4 is released remove ifdef code for kernel versions
636 less than 2.2. The driver is now only supported in kernels 2.2,
638 2. Add code to release and acquire the io_request_lock in
639 the driver entrypoint functions: advansys_detect and
640 advansys_queuecommand. In kernel 2.4 the SCSI mid-level driver
641 still holds the io_request_lock on entry to SCSI low-level drivers.
642 This was supposed to be removed before 2.4 was released but never
643 happened. When the mid-level SCSI driver is changed all references
644 to the io_request_lock should be removed from the driver.
645 3. Simplify error handling by removing advansys_abort(),
646 AscAbortSRB(), AscResetDevice(). SCSI bus reset requests are
647 now handled by resetting the SCSI bus and fully re-initializing
648 the chip. This simple method of error recovery has proven to work
649 most reliably after attempts at different methods. Also now only
650 support the "new" error handling method and remove the obsolete
651 error handling interface.
652 4. Fix debug build errors.
655 1. Merge with ConnectCom version from Andy Kellner which
656 updates Adv Library to 5.14.
657 2. Make PowerPC (Big Endian) work for narrow cards and
658 fix problems writing EEPROM for wide cards.
659 3. Remove interrupts_enabled assertion function.
662 1. Return an error from narrow boards if passed a 16 byte
663 CDB. The wide board can already handle 16 byte CDBs.
666 1. hacks for lk 2.5 series (D. Gilbert)
669 1. change select_queue_depths to slave_configure
670 2. make cmd_per_lun be sane again
673 1. continuing cleanup for lk 2.6 series
674 2. Fix problem in lk 2.6.7-bk2 that broke PCI wide cards
675 3. Fix problem that oopsed ISA cards
677 I. Known Problems/Fix List (XXX)
679 1. Need to add memory mapping workaround. Test the memory mapping.
680 If it doesn't work revert to I/O port access. Can a test be done
682 2. Handle an interrupt not working. Keep an interrupt counter in
683 the interrupt handler. In the timeout function if the interrupt
684 has not occurred then print a message and run in polled mode.
685 3. Allow bus type scanning order to be changed.
686 4. Need to add support for target mode commands, cf. CAM XPT.
688 J. Credits (Chronological Order)
690 Bob Frey <bfrey@turbolinux.com.cn> wrote the AdvanSys SCSI driver
691 and maintained it up to 3.3F. He continues to answer questions
692 and help maintain the driver.
694 Nathan Hartwell <mage@cdc3.cdc.net> provided the directions and
695 basis for the Linux v1.3.X changes which were included in the
698 Thomas E Zerucha <zerucha@shell.portal.com> pointed out a bug
699 in advansys_biosparam() which was fixed in the 1.3 release.
701 Erik Ratcliffe <erik@caldera.com> has done testing of the
702 AdvanSys driver in the Caldera releases.
704 Rik van Riel <H.H.vanRiel@fys.ruu.nl> provided a patch to
705 AscWaitTixISRDone() which he found necessary to make the
706 driver work with a SCSI-1 disk.
708 Mark Moran <mmoran@mmoran.com> has helped test Ultra-Wide
709 support in the 3.1A driver.
711 Doug Gilbert <dgilbert@interlog.com> has made changes and
712 suggestions to improve the driver and done a lot of testing.
714 Ken Mort <ken@mort.net> reported a DEBUG compile bug fixed
717 Tom Rini <trini@kernel.crashing.org> provided the CONFIG_ISA
718 patch and helped with PowerPC wide and narrow board support.
720 Philip Blundell <philb@gnu.org> provided an
721 advansys_interrupts_enabled patch.
723 Dave Jones <dave@denial.force9.co.uk> reported the compiler
724 warnings generated when CONFIG_PROC_FS was not defined in
727 Jerry Quinn <jlquinn@us.ibm.com> fixed PowerPC support (endian
728 problems) for wide cards.
730 Bryan Henderson <bryanh@giraffe-data.com> helped debug narrow
733 Manuel Veloso <veloso@pobox.com> worked hard on PowerPC narrow
734 board support and fixed a bug in AscGetEEPConfig().
736 Arnaldo Carvalho de Melo <acme@conectiva.com.br> made
737 save_flags/restore_flags changes.
739 Andy Kellner <AKellner@connectcom.net> continues the Advansys SCSI
740 driver development for ConnectCom (Version > 3.3F).
742 K. ConnectCom (AdvanSys) Contact Information
744 Mail: ConnectCom Solutions, Inc.
747 Operator/Sales: 1-408-383-9400
749 Tech Support: 1-408-467-2930
750 Tech Support E-Mail: linux@connectcom.net
751 FTP Site: ftp.connectcom.net (login: anonymous)
752 Web Site: http://www.connectcom.net
757 * --- Linux Include Files
760 #include <linux/module.h>
761 #include <linux/string.h>
762 #include <linux/kernel.h>
763 #include <linux/types.h>
764 #include <linux/ioport.h>
765 #include <linux/interrupt.h>
766 #include <linux/delay.h>
767 #include <linux/slab.h>
768 #include <linux/mm.h>
769 #include <linux/proc_fs.h>
770 #include <linux/init.h>
771 #include <linux/blkdev.h>
772 #include <linux/pci.h>
773 #include <linux/spinlock.h>
774 #include <linux/dma-mapping.h>
777 #include <asm/system.h>
780 #include <scsi/scsi_cmnd.h>
781 #include <scsi/scsi_device.h>
782 #include <scsi/scsi_tcq.h>
783 #include <scsi/scsi.h>
784 #include <scsi/scsi_host.h>
786 /* FIXME: (by jejb@steeleye.com) This warning is present for two
789 * 1) This driver badly needs converting to the correct driver model
792 * 2) Although all of the necessary command mapping places have the
793 * appropriate dma_map.. APIs, the driver still processes its internal
794 * queue using bus_to_virt() and virt_to_bus() which are illegal under
795 * the API. The entire queue processing structure will need to be
796 * altered to fix this.
798 #warning this driver is still not properly converted to the DMA API
804 /* Enable driver assertions. */
805 #define ADVANSYS_ASSERT
807 /* Enable driver /proc statistics. */
808 #define ADVANSYS_STATS
810 /* Enable driver tracing. */
811 /* #define ADVANSYS_DEBUG */
814 * --- Asc Library Constants and Macros
817 #define ASC_LIB_VERSION_MAJOR 1
818 #define ASC_LIB_VERSION_MINOR 24
819 #define ASC_LIB_SERIAL_NUMBER 123
822 * Portable Data Types
824 * Any instance where a 32-bit long or pointer type is assumed
825 * for precision or HW defined structures, the following define
826 * types must be used. In Linux the char, short, and int types
827 * are all consistent at 8, 16, and 32 bits respectively. Pointers
828 * and long types are 64 bits on Alpha and UltraSPARC.
830 #define ASC_PADDR __u32 /* Physical/Bus address data type. */
831 #define ASC_VADDR __u32 /* Virtual address data type. */
832 #define ASC_DCNT __u32 /* Unsigned Data count type. */
833 #define ASC_SDCNT __s32 /* Signed Data count type. */
836 * These macros are used to convert a virtual address to a
837 * 32-bit value. This currently can be used on Linux Alpha
838 * which uses 64-bit virtual address but a 32-bit bus address.
839 * This is likely to break in the future, but doing this now
840 * will give us time to change the HW and FW to handle 64-bit
843 #define ASC_VADDR_TO_U32 virt_to_bus
844 #define ASC_U32_TO_VADDR bus_to_virt
846 typedef unsigned char uchar;
857 #define UW_ERR (uint)(0xFFFF)
858 #define isodd_word(val) ((((uint)val) & (uint)0x0001) != 0)
859 #define AscPCIConfigVendorIDRegister 0x0000
860 #define AscPCIConfigDeviceIDRegister 0x0002
861 #define AscPCIConfigCommandRegister 0x0004
862 #define AscPCIConfigStatusRegister 0x0006
863 #define AscPCIConfigRevisionIDRegister 0x0008
864 #define AscPCIConfigCacheSize 0x000C
865 #define AscPCIConfigLatencyTimer 0x000D
866 #define AscPCIIOBaseRegister 0x0010
867 #define AscPCICmdRegBits_IOMemBusMaster 0x0007
868 #define ASC_PCI_ID2BUS(id) ((id) & 0xFF)
869 #define ASC_PCI_ID2DEV(id) (((id) >> 11) & 0x1F)
870 #define ASC_PCI_ID2FUNC(id) (((id) >> 8) & 0x7)
871 #define ASC_PCI_MKID(bus, dev, func) ((((dev) & 0x1F) << 11) | (((func) & 0x7) << 8) | ((bus) & 0xFF))
872 #define ASC_PCI_REVISION_3150 0x02
873 #define ASC_PCI_REVISION_3050 0x03
875 #define ASC_DVCLIB_CALL_DONE (1)
876 #define ASC_DVCLIB_CALL_FAILED (0)
877 #define ASC_DVCLIB_CALL_ERROR (-1)
879 #define PCI_VENDOR_ID_ASP 0x10cd
880 #define PCI_DEVICE_ID_ASP_1200A 0x1100
881 #define PCI_DEVICE_ID_ASP_ABP940 0x1200
882 #define PCI_DEVICE_ID_ASP_ABP940U 0x1300
883 #define PCI_DEVICE_ID_ASP_ABP940UW 0x2300
884 #define PCI_DEVICE_ID_38C0800_REV1 0x2500
885 #define PCI_DEVICE_ID_38C1600_REV1 0x2700
888 * Enable CC_VERY_LONG_SG_LIST to support up to 64K element SG lists.
889 * The SRB structure will have to be changed and the ASC_SRB2SCSIQ()
890 * macro re-defined to be able to obtain a ASC_SCSI_Q pointer from the
893 #define CC_VERY_LONG_SG_LIST 0
894 #define ASC_SRB2SCSIQ(srb_ptr) (srb_ptr)
896 #define PortAddr unsigned short /* port address size */
897 #define inp(port) inb(port)
898 #define outp(port, byte) outb((byte), (port))
900 #define inpw(port) inw(port)
901 #define outpw(port, word) outw((word), (port))
903 #define ASC_MAX_SG_QUEUE 7
904 #define ASC_MAX_SG_LIST 255
906 #define ASC_CS_TYPE unsigned short
908 #define ASC_IS_ISA (0x0001)
909 #define ASC_IS_ISAPNP (0x0081)
910 #define ASC_IS_EISA (0x0002)
911 #define ASC_IS_PCI (0x0004)
912 #define ASC_IS_PCI_ULTRA (0x0104)
913 #define ASC_IS_PCMCIA (0x0008)
914 #define ASC_IS_MCA (0x0020)
915 #define ASC_IS_VL (0x0040)
916 #define ASC_ISA_PNP_PORT_ADDR (0x279)
917 #define ASC_ISA_PNP_PORT_WRITE (ASC_ISA_PNP_PORT_ADDR+0x800)
918 #define ASC_IS_WIDESCSI_16 (0x0100)
919 #define ASC_IS_WIDESCSI_32 (0x0200)
920 #define ASC_IS_BIG_ENDIAN (0x8000)
921 #define ASC_CHIP_MIN_VER_VL (0x01)
922 #define ASC_CHIP_MAX_VER_VL (0x07)
923 #define ASC_CHIP_MIN_VER_PCI (0x09)
924 #define ASC_CHIP_MAX_VER_PCI (0x0F)
925 #define ASC_CHIP_VER_PCI_BIT (0x08)
926 #define ASC_CHIP_MIN_VER_ISA (0x11)
927 #define ASC_CHIP_MIN_VER_ISA_PNP (0x21)
928 #define ASC_CHIP_MAX_VER_ISA (0x27)
929 #define ASC_CHIP_VER_ISA_BIT (0x30)
930 #define ASC_CHIP_VER_ISAPNP_BIT (0x20)
931 #define ASC_CHIP_VER_ASYN_BUG (0x21)
932 #define ASC_CHIP_VER_PCI 0x08
933 #define ASC_CHIP_VER_PCI_ULTRA_3150 (ASC_CHIP_VER_PCI | 0x02)
934 #define ASC_CHIP_VER_PCI_ULTRA_3050 (ASC_CHIP_VER_PCI | 0x03)
935 #define ASC_CHIP_MIN_VER_EISA (0x41)
936 #define ASC_CHIP_MAX_VER_EISA (0x47)
937 #define ASC_CHIP_VER_EISA_BIT (0x40)
938 #define ASC_CHIP_LATEST_VER_EISA ((ASC_CHIP_MIN_VER_EISA - 1) + 3)
939 #define ASC_MAX_LIB_SUPPORTED_ISA_CHIP_VER 0x21
940 #define ASC_MAX_LIB_SUPPORTED_PCI_CHIP_VER 0x0A
941 #define ASC_MAX_VL_DMA_ADDR (0x07FFFFFFL)
942 #define ASC_MAX_VL_DMA_COUNT (0x07FFFFFFL)
943 #define ASC_MAX_PCI_DMA_ADDR (0xFFFFFFFFL)
944 #define ASC_MAX_PCI_DMA_COUNT (0xFFFFFFFFL)
945 #define ASC_MAX_ISA_DMA_ADDR (0x00FFFFFFL)
946 #define ASC_MAX_ISA_DMA_COUNT (0x00FFFFFFL)
947 #define ASC_MAX_EISA_DMA_ADDR (0x07FFFFFFL)
948 #define ASC_MAX_EISA_DMA_COUNT (0x07FFFFFFL)
950 #define ASC_SCSI_ID_BITS 3
951 #define ASC_SCSI_TIX_TYPE uchar
952 #define ASC_ALL_DEVICE_BIT_SET 0xFF
953 #define ASC_SCSI_BIT_ID_TYPE uchar
954 #define ASC_MAX_TID 7
955 #define ASC_MAX_LUN 7
956 #define ASC_SCSI_WIDTH_BIT_SET 0xFF
957 #define ASC_MAX_SENSE_LEN 32
958 #define ASC_MIN_SENSE_LEN 14
959 #define ASC_MAX_CDB_LEN 12
960 #define ASC_SCSI_RESET_HOLD_TIME_US 60
962 #define ADV_INQ_CLOCKING_ST_ONLY 0x0
963 #define ADV_INQ_CLOCKING_DT_ONLY 0x1
964 #define ADV_INQ_CLOCKING_ST_AND_DT 0x3
967 * Inquiry SPC-2 SPI Byte 1 EVPD (Enable Vital Product Data)
968 * and CmdDt (Command Support Data) field bit definitions.
970 #define ADV_INQ_RTN_VPD_AND_CMDDT 0x3
971 #define ADV_INQ_RTN_CMDDT_FOR_OP_CODE 0x2
972 #define ADV_INQ_RTN_VPD_FOR_PG_CODE 0x1
973 #define ADV_INQ_RTN_STD_INQUIRY_DATA 0x0
975 #define ASC_SCSIDIR_NOCHK 0x00
976 #define ASC_SCSIDIR_T2H 0x08
977 #define ASC_SCSIDIR_H2T 0x10
978 #define ASC_SCSIDIR_NODATA 0x18
979 #define SCSI_ASC_NOMEDIA 0x3A
980 #define ASC_SRB_HOST(x) ((uchar)((uchar)(x) >> 4))
981 #define ASC_SRB_TID(x) ((uchar)((uchar)(x) & (uchar)0x0F))
982 #define ASC_SRB_LUN(x) ((uchar)((uint)(x) >> 13))
983 #define PUT_CDB1(x) ((uchar)((uint)(x) >> 8))
984 #define MS_CMD_DONE 0x00
985 #define MS_EXTEND 0x01
986 #define MS_SDTR_LEN 0x03
987 #define MS_SDTR_CODE 0x01
988 #define MS_WDTR_LEN 0x02
989 #define MS_WDTR_CODE 0x03
990 #define MS_MDP_LEN 0x05
991 #define MS_MDP_CODE 0x00
994 * Inquiry data structure and bitfield macros
996 * Only quantities of more than 1 bit are shifted, since the others are
997 * just tested for true or false. C bitfields aren't portable between big
998 * and little-endian platforms so they are not used.
1001 #define ASC_INQ_DVC_TYPE(inq) ((inq)->periph & 0x1f)
1002 #define ASC_INQ_QUALIFIER(inq) (((inq)->periph & 0xe0) >> 5)
1003 #define ASC_INQ_DVC_TYPE_MOD(inq) ((inq)->devtype & 0x7f)
1004 #define ASC_INQ_REMOVABLE(inq) ((inq)->devtype & 0x80)
1005 #define ASC_INQ_ANSI_VER(inq) ((inq)->ver & 0x07)
1006 #define ASC_INQ_ECMA_VER(inq) (((inq)->ver & 0x38) >> 3)
1007 #define ASC_INQ_ISO_VER(inq) (((inq)->ver & 0xc0) >> 6)
1008 #define ASC_INQ_RESPONSE_FMT(inq) ((inq)->byte3 & 0x0f)
1009 #define ASC_INQ_TERM_IO(inq) ((inq)->byte3 & 0x40)
1010 #define ASC_INQ_ASYNC_NOTIF(inq) ((inq)->byte3 & 0x80)
1011 #define ASC_INQ_SOFT_RESET(inq) ((inq)->flags & 0x01)
1012 #define ASC_INQ_CMD_QUEUE(inq) ((inq)->flags & 0x02)
1013 #define ASC_INQ_LINK_CMD(inq) ((inq)->flags & 0x08)
1014 #define ASC_INQ_SYNC(inq) ((inq)->flags & 0x10)
1015 #define ASC_INQ_WIDE16(inq) ((inq)->flags & 0x20)
1016 #define ASC_INQ_WIDE32(inq) ((inq)->flags & 0x40)
1017 #define ASC_INQ_REL_ADDR(inq) ((inq)->flags & 0x80)
1018 #define ASC_INQ_INFO_UNIT(inq) ((inq)->info & 0x01)
1019 #define ASC_INQ_QUICK_ARB(inq) ((inq)->info & 0x02)
1020 #define ASC_INQ_CLOCKING(inq) (((inq)->info & 0x0c) >> 2)
1032 uchar product_id[16];
1033 uchar product_rev_level[4];
1036 #define ASC_SG_LIST_PER_Q 7
1037 #define QS_FREE 0x00
1038 #define QS_READY 0x01
1039 #define QS_DISC1 0x02
1040 #define QS_DISC2 0x04
1041 #define QS_BUSY 0x08
1042 #define QS_ABORTED 0x40
1043 #define QS_DONE 0x80
1044 #define QC_NO_CALLBACK 0x01
1045 #define QC_SG_SWAP_QUEUE 0x02
1046 #define QC_SG_HEAD 0x04
1047 #define QC_DATA_IN 0x08
1048 #define QC_DATA_OUT 0x10
1049 #define QC_URGENT 0x20
1050 #define QC_MSG_OUT 0x40
1051 #define QC_REQ_SENSE 0x80
1052 #define QCSG_SG_XFER_LIST 0x02
1053 #define QCSG_SG_XFER_MORE 0x04
1054 #define QCSG_SG_XFER_END 0x08
1055 #define QD_IN_PROGRESS 0x00
1056 #define QD_NO_ERROR 0x01
1057 #define QD_ABORTED_BY_HOST 0x02
1058 #define QD_WITH_ERROR 0x04
1059 #define QD_INVALID_REQUEST 0x80
1060 #define QD_INVALID_HOST_NUM 0x81
1061 #define QD_INVALID_DEVICE 0x82
1062 #define QD_ERR_INTERNAL 0xFF
1063 #define QHSTA_NO_ERROR 0x00
1064 #define QHSTA_M_SEL_TIMEOUT 0x11
1065 #define QHSTA_M_DATA_OVER_RUN 0x12
1066 #define QHSTA_M_DATA_UNDER_RUN 0x12
1067 #define QHSTA_M_UNEXPECTED_BUS_FREE 0x13
1068 #define QHSTA_M_BAD_BUS_PHASE_SEQ 0x14
1069 #define QHSTA_D_QDONE_SG_LIST_CORRUPTED 0x21
1070 #define QHSTA_D_ASC_DVC_ERROR_CODE_SET 0x22
1071 #define QHSTA_D_HOST_ABORT_FAILED 0x23
1072 #define QHSTA_D_EXE_SCSI_Q_FAILED 0x24
1073 #define QHSTA_D_EXE_SCSI_Q_BUSY_TIMEOUT 0x25
1074 #define QHSTA_D_ASPI_NO_BUF_POOL 0x26
1075 #define QHSTA_M_WTM_TIMEOUT 0x41
1076 #define QHSTA_M_BAD_CMPL_STATUS_IN 0x42
1077 #define QHSTA_M_NO_AUTO_REQ_SENSE 0x43
1078 #define QHSTA_M_AUTO_REQ_SENSE_FAIL 0x44
1079 #define QHSTA_M_TARGET_STATUS_BUSY 0x45
1080 #define QHSTA_M_BAD_TAG_CODE 0x46
1081 #define QHSTA_M_BAD_QUEUE_FULL_OR_BUSY 0x47
1082 #define QHSTA_M_HUNG_REQ_SCSI_BUS_RESET 0x48
1083 #define QHSTA_D_LRAM_CMP_ERROR 0x81
1084 #define QHSTA_M_MICRO_CODE_ERROR_HALT 0xA1
1085 #define ASC_FLAG_SCSIQ_REQ 0x01
1086 #define ASC_FLAG_BIOS_SCSIQ_REQ 0x02
1087 #define ASC_FLAG_BIOS_ASYNC_IO 0x04
1088 #define ASC_FLAG_SRB_LINEAR_ADDR 0x08
1089 #define ASC_FLAG_WIN16 0x10
1090 #define ASC_FLAG_WIN32 0x20
1091 #define ASC_FLAG_ISA_OVER_16MB 0x40
1092 #define ASC_FLAG_DOS_VM_CALLBACK 0x80
1093 #define ASC_TAG_FLAG_EXTRA_BYTES 0x10
1094 #define ASC_TAG_FLAG_DISABLE_DISCONNECT 0x04
1095 #define ASC_TAG_FLAG_DISABLE_ASYN_USE_SYN_FIX 0x08
1096 #define ASC_TAG_FLAG_DISABLE_CHK_COND_INT_HOST 0x40
1097 #define ASC_SCSIQ_CPY_BEG 4
1098 #define ASC_SCSIQ_SGHD_CPY_BEG 2
1099 #define ASC_SCSIQ_B_FWD 0
1100 #define ASC_SCSIQ_B_BWD 1
1101 #define ASC_SCSIQ_B_STATUS 2
1102 #define ASC_SCSIQ_B_QNO 3
1103 #define ASC_SCSIQ_B_CNTL 4
1104 #define ASC_SCSIQ_B_SG_QUEUE_CNT 5
1105 #define ASC_SCSIQ_D_DATA_ADDR 8
1106 #define ASC_SCSIQ_D_DATA_CNT 12
1107 #define ASC_SCSIQ_B_SENSE_LEN 20
1108 #define ASC_SCSIQ_DONE_INFO_BEG 22
1109 #define ASC_SCSIQ_D_SRBPTR 22
1110 #define ASC_SCSIQ_B_TARGET_IX 26
1111 #define ASC_SCSIQ_B_CDB_LEN 28
1112 #define ASC_SCSIQ_B_TAG_CODE 29
1113 #define ASC_SCSIQ_W_VM_ID 30
1114 #define ASC_SCSIQ_DONE_STATUS 32
1115 #define ASC_SCSIQ_HOST_STATUS 33
1116 #define ASC_SCSIQ_SCSI_STATUS 34
1117 #define ASC_SCSIQ_CDB_BEG 36
1118 #define ASC_SCSIQ_DW_REMAIN_XFER_ADDR 56
1119 #define ASC_SCSIQ_DW_REMAIN_XFER_CNT 60
1120 #define ASC_SCSIQ_B_FIRST_SG_WK_QP 48
1121 #define ASC_SCSIQ_B_SG_WK_QP 49
1122 #define ASC_SCSIQ_B_SG_WK_IX 50
1123 #define ASC_SCSIQ_W_ALT_DC1 52
1124 #define ASC_SCSIQ_B_LIST_CNT 6
1125 #define ASC_SCSIQ_B_CUR_LIST_CNT 7
1126 #define ASC_SGQ_B_SG_CNTL 4
1127 #define ASC_SGQ_B_SG_HEAD_QP 5
1128 #define ASC_SGQ_B_SG_LIST_CNT 6
1129 #define ASC_SGQ_B_SG_CUR_LIST_CNT 7
1130 #define ASC_SGQ_LIST_BEG 8
1131 #define ASC_DEF_SCSI1_QNG 4
1132 #define ASC_MAX_SCSI1_QNG 4
1133 #define ASC_DEF_SCSI2_QNG 16
1134 #define ASC_MAX_SCSI2_QNG 32
1135 #define ASC_TAG_CODE_MASK 0x23
1136 #define ASC_STOP_REQ_RISC_STOP 0x01
1137 #define ASC_STOP_ACK_RISC_STOP 0x03
1138 #define ASC_STOP_CLEAN_UP_BUSY_Q 0x10
1139 #define ASC_STOP_CLEAN_UP_DISC_Q 0x20
1140 #define ASC_STOP_HOST_REQ_RISC_HALT 0x40
1141 #define ASC_TIDLUN_TO_IX(tid, lun) (ASC_SCSI_TIX_TYPE)((tid) + ((lun)<<ASC_SCSI_ID_BITS))
1142 #define ASC_TID_TO_TARGET_ID(tid) (ASC_SCSI_BIT_ID_TYPE)(0x01 << (tid))
1143 #define ASC_TIX_TO_TARGET_ID(tix) (0x01 << ((tix) & ASC_MAX_TID))
1144 #define ASC_TIX_TO_TID(tix) ((tix) & ASC_MAX_TID)
1145 #define ASC_TID_TO_TIX(tid) ((tid) & ASC_MAX_TID)
1146 #define ASC_TIX_TO_LUN(tix) (((tix) >> ASC_SCSI_ID_BITS) & ASC_MAX_LUN)
1147 #define ASC_QNO_TO_QADDR(q_no) ((ASC_QADR_BEG)+((int)(q_no) << 6))
1149 typedef struct asc_scsiq_1 {
1156 ASC_PADDR data_addr;
1158 ASC_PADDR sense_addr;
1163 typedef struct asc_scsiq_2 {
1172 typedef struct asc_scsiq_3 {
1179 typedef struct asc_scsiq_4 {
1180 uchar cdb[ASC_MAX_CDB_LEN];
1181 uchar y_first_sg_list_qp;
1182 uchar y_working_sg_qp;
1183 uchar y_working_sg_ix;
1186 ushort x_reconnect_rtn;
1187 ASC_PADDR x_saved_data_addr;
1188 ASC_DCNT x_saved_data_cnt;
1191 typedef struct asc_q_done_info {
1200 ASC_DCNT remain_bytes;
1203 typedef struct asc_sg_list {
1208 typedef struct asc_sg_head {
1211 ushort entry_to_copy;
1213 ASC_SG_LIST sg_list[ASC_MAX_SG_LIST];
1216 #define ASC_MIN_SG_LIST 2
1218 typedef struct asc_min_sg_head {
1221 ushort entry_to_copy;
1223 ASC_SG_LIST sg_list[ASC_MIN_SG_LIST];
1226 #define QCX_SORT (0x0001)
1227 #define QCX_COALEASE (0x0002)
1229 typedef struct asc_scsi_q {
1233 ASC_SG_HEAD *sg_head;
1234 ushort remain_sg_entry_cnt;
1235 ushort next_sg_index;
1238 typedef struct asc_scsi_req_q {
1242 ASC_SG_HEAD *sg_head;
1245 uchar cdb[ASC_MAX_CDB_LEN];
1246 uchar sense[ASC_MIN_SENSE_LEN];
1249 typedef struct asc_scsi_bios_req_q {
1253 ASC_SG_HEAD *sg_head;
1256 uchar cdb[ASC_MAX_CDB_LEN];
1257 uchar sense[ASC_MIN_SENSE_LEN];
1258 } ASC_SCSI_BIOS_REQ_Q;
1260 typedef struct asc_risc_q {
1269 typedef struct asc_sg_list_q {
1275 uchar sg_cur_list_cnt;
1278 typedef struct asc_risc_sg_list_q {
1282 ASC_SG_LIST sg_list[7];
1283 } ASC_RISC_SG_LIST_Q;
1285 #define ASC_EXE_SCSI_IO_MAX_IDLE_LOOP 0x1000000UL
1286 #define ASC_EXE_SCSI_IO_MAX_WAIT_LOOP 1024
1287 #define ASCQ_ERR_NO_ERROR 0
1288 #define ASCQ_ERR_IO_NOT_FOUND 1
1289 #define ASCQ_ERR_LOCAL_MEM 2
1290 #define ASCQ_ERR_CHKSUM 3
1291 #define ASCQ_ERR_START_CHIP 4
1292 #define ASCQ_ERR_INT_TARGET_ID 5
1293 #define ASCQ_ERR_INT_LOCAL_MEM 6
1294 #define ASCQ_ERR_HALT_RISC 7
1295 #define ASCQ_ERR_GET_ASPI_ENTRY 8
1296 #define ASCQ_ERR_CLOSE_ASPI 9
1297 #define ASCQ_ERR_HOST_INQUIRY 0x0A
1298 #define ASCQ_ERR_SAVED_SRB_BAD 0x0B
1299 #define ASCQ_ERR_QCNTL_SG_LIST 0x0C
1300 #define ASCQ_ERR_Q_STATUS 0x0D
1301 #define ASCQ_ERR_WR_SCSIQ 0x0E
1302 #define ASCQ_ERR_PC_ADDR 0x0F
1303 #define ASCQ_ERR_SYN_OFFSET 0x10
1304 #define ASCQ_ERR_SYN_XFER_TIME 0x11
1305 #define ASCQ_ERR_LOCK_DMA 0x12
1306 #define ASCQ_ERR_UNLOCK_DMA 0x13
1307 #define ASCQ_ERR_VDS_CHK_INSTALL 0x14
1308 #define ASCQ_ERR_MICRO_CODE_HALT 0x15
1309 #define ASCQ_ERR_SET_LRAM_ADDR 0x16
1310 #define ASCQ_ERR_CUR_QNG 0x17
1311 #define ASCQ_ERR_SG_Q_LINKS 0x18
1312 #define ASCQ_ERR_SCSIQ_PTR 0x19
1313 #define ASCQ_ERR_ISR_RE_ENTRY 0x1A
1314 #define ASCQ_ERR_CRITICAL_RE_ENTRY 0x1B
1315 #define ASCQ_ERR_ISR_ON_CRITICAL 0x1C
1316 #define ASCQ_ERR_SG_LIST_ODD_ADDRESS 0x1D
1317 #define ASCQ_ERR_XFER_ADDRESS_TOO_BIG 0x1E
1318 #define ASCQ_ERR_SCSIQ_NULL_PTR 0x1F
1319 #define ASCQ_ERR_SCSIQ_BAD_NEXT_PTR 0x20
1320 #define ASCQ_ERR_GET_NUM_OF_FREE_Q 0x21
1321 #define ASCQ_ERR_SEND_SCSI_Q 0x22
1322 #define ASCQ_ERR_HOST_REQ_RISC_HALT 0x23
1323 #define ASCQ_ERR_RESET_SDTR 0x24
1326 * Warning code values are set in ASC_DVC_VAR 'warn_code'.
1328 #define ASC_WARN_NO_ERROR 0x0000
1329 #define ASC_WARN_IO_PORT_ROTATE 0x0001
1330 #define ASC_WARN_EEPROM_CHKSUM 0x0002
1331 #define ASC_WARN_IRQ_MODIFIED 0x0004
1332 #define ASC_WARN_AUTO_CONFIG 0x0008
1333 #define ASC_WARN_CMD_QNG_CONFLICT 0x0010
1334 #define ASC_WARN_EEPROM_RECOVER 0x0020
1335 #define ASC_WARN_CFG_MSW_RECOVER 0x0040
1336 #define ASC_WARN_SET_PCI_CONFIG_SPACE 0x0080
1339 * Error code values are set in ASC_DVC_VAR 'err_code'.
1341 #define ASC_IERR_WRITE_EEPROM 0x0001
1342 #define ASC_IERR_MCODE_CHKSUM 0x0002
1343 #define ASC_IERR_SET_PC_ADDR 0x0004
1344 #define ASC_IERR_START_STOP_CHIP 0x0008
1345 #define ASC_IERR_IRQ_NO 0x0010
1346 #define ASC_IERR_SET_IRQ_NO 0x0020
1347 #define ASC_IERR_CHIP_VERSION 0x0040
1348 #define ASC_IERR_SET_SCSI_ID 0x0080
1349 #define ASC_IERR_GET_PHY_ADDR 0x0100
1350 #define ASC_IERR_BAD_SIGNATURE 0x0200
1351 #define ASC_IERR_NO_BUS_TYPE 0x0400
1352 #define ASC_IERR_SCAM 0x0800
1353 #define ASC_IERR_SET_SDTR 0x1000
1354 #define ASC_IERR_RW_LRAM 0x8000
1356 #define ASC_DEF_IRQ_NO 10
1357 #define ASC_MAX_IRQ_NO 15
1358 #define ASC_MIN_IRQ_NO 10
1359 #define ASC_MIN_REMAIN_Q (0x02)
1360 #define ASC_DEF_MAX_TOTAL_QNG (0xF0)
1361 #define ASC_MIN_TAG_Q_PER_DVC (0x04)
1362 #define ASC_DEF_TAG_Q_PER_DVC (0x04)
1363 #define ASC_MIN_FREE_Q ASC_MIN_REMAIN_Q
1364 #define ASC_MIN_TOTAL_QNG ((ASC_MAX_SG_QUEUE)+(ASC_MIN_FREE_Q))
1365 #define ASC_MAX_TOTAL_QNG 240
1366 #define ASC_MAX_PCI_ULTRA_INRAM_TOTAL_QNG 16
1367 #define ASC_MAX_PCI_ULTRA_INRAM_TAG_QNG 8
1368 #define ASC_MAX_PCI_INRAM_TOTAL_QNG 20
1369 #define ASC_MAX_INRAM_TAG_QNG 16
1370 #define ASC_IOADR_TABLE_MAX_IX 11
1371 #define ASC_IOADR_GAP 0x10
1372 #define ASC_SEARCH_IOP_GAP 0x10
1373 #define ASC_MIN_IOP_ADDR (PortAddr)0x0100
1374 #define ASC_MAX_IOP_ADDR (PortAddr)0x3F0
1375 #define ASC_IOADR_1 (PortAddr)0x0110
1376 #define ASC_IOADR_2 (PortAddr)0x0130
1377 #define ASC_IOADR_3 (PortAddr)0x0150
1378 #define ASC_IOADR_4 (PortAddr)0x0190
1379 #define ASC_IOADR_5 (PortAddr)0x0210
1380 #define ASC_IOADR_6 (PortAddr)0x0230
1381 #define ASC_IOADR_7 (PortAddr)0x0250
1382 #define ASC_IOADR_8 (PortAddr)0x0330
1383 #define ASC_IOADR_DEF ASC_IOADR_8
1384 #define ASC_LIB_SCSIQ_WK_SP 256
1385 #define ASC_MAX_SYN_XFER_NO 16
1386 #define ASC_SYN_MAX_OFFSET 0x0F
1387 #define ASC_DEF_SDTR_OFFSET 0x0F
1388 #define ASC_DEF_SDTR_INDEX 0x00
1389 #define ASC_SDTR_ULTRA_PCI_10MB_INDEX 0x02
1390 #define SYN_XFER_NS_0 25
1391 #define SYN_XFER_NS_1 30
1392 #define SYN_XFER_NS_2 35
1393 #define SYN_XFER_NS_3 40
1394 #define SYN_XFER_NS_4 50
1395 #define SYN_XFER_NS_5 60
1396 #define SYN_XFER_NS_6 70
1397 #define SYN_XFER_NS_7 85
1398 #define SYN_ULTRA_XFER_NS_0 12
1399 #define SYN_ULTRA_XFER_NS_1 19
1400 #define SYN_ULTRA_XFER_NS_2 25
1401 #define SYN_ULTRA_XFER_NS_3 32
1402 #define SYN_ULTRA_XFER_NS_4 38
1403 #define SYN_ULTRA_XFER_NS_5 44
1404 #define SYN_ULTRA_XFER_NS_6 50
1405 #define SYN_ULTRA_XFER_NS_7 57
1406 #define SYN_ULTRA_XFER_NS_8 63
1407 #define SYN_ULTRA_XFER_NS_9 69
1408 #define SYN_ULTRA_XFER_NS_10 75
1409 #define SYN_ULTRA_XFER_NS_11 82
1410 #define SYN_ULTRA_XFER_NS_12 88
1411 #define SYN_ULTRA_XFER_NS_13 94
1412 #define SYN_ULTRA_XFER_NS_14 100
1413 #define SYN_ULTRA_XFER_NS_15 107
1415 typedef struct ext_msg {
1421 uchar sdtr_xfer_period;
1422 uchar sdtr_req_ack_offset;
1437 #define xfer_period u_ext_msg.sdtr.sdtr_xfer_period
1438 #define req_ack_offset u_ext_msg.sdtr.sdtr_req_ack_offset
1439 #define wdtr_width u_ext_msg.wdtr.wdtr_width
1440 #define mdp_b3 u_ext_msg.mdp_b3
1441 #define mdp_b2 u_ext_msg.mdp_b2
1442 #define mdp_b1 u_ext_msg.mdp_b1
1443 #define mdp_b0 u_ext_msg.mdp_b0
1445 typedef struct asc_dvc_cfg {
1446 ASC_SCSI_BIT_ID_TYPE can_tagged_qng;
1447 ASC_SCSI_BIT_ID_TYPE cmd_qng_enabled;
1448 ASC_SCSI_BIT_ID_TYPE disc_enable;
1449 ASC_SCSI_BIT_ID_TYPE sdtr_enable;
1451 uchar isa_dma_speed;
1452 uchar isa_dma_channel;
1454 ushort lib_serial_no;
1457 ushort mcode_version;
1458 uchar max_tag_qng[ASC_MAX_TID + 1];
1460 uchar sdtr_period_offset[ASC_MAX_TID + 1];
1461 ushort pci_slot_info;
1462 uchar adapter_info[6];
1466 #define ASC_DEF_DVC_CNTL 0xFFFF
1467 #define ASC_DEF_CHIP_SCSI_ID 7
1468 #define ASC_DEF_ISA_DMA_SPEED 4
1469 #define ASC_INIT_STATE_NULL 0x0000
1470 #define ASC_INIT_STATE_BEG_GET_CFG 0x0001
1471 #define ASC_INIT_STATE_END_GET_CFG 0x0002
1472 #define ASC_INIT_STATE_BEG_SET_CFG 0x0004
1473 #define ASC_INIT_STATE_END_SET_CFG 0x0008
1474 #define ASC_INIT_STATE_BEG_LOAD_MC 0x0010
1475 #define ASC_INIT_STATE_END_LOAD_MC 0x0020
1476 #define ASC_INIT_STATE_BEG_INQUIRY 0x0040
1477 #define ASC_INIT_STATE_END_INQUIRY 0x0080
1478 #define ASC_INIT_RESET_SCSI_DONE 0x0100
1479 #define ASC_INIT_STATE_WITHOUT_EEP 0x8000
1480 #define ASC_BUG_FIX_IF_NOT_DWB 0x0001
1481 #define ASC_BUG_FIX_ASYN_USE_SYN 0x0002
1482 #define ASYN_SDTR_DATA_FIX_PCI_REV_AB 0x41
1483 #define ASC_MIN_TAGGED_CMD 7
1484 #define ASC_MAX_SCSI_RESET_WAIT 30
1486 struct asc_dvc_var; /* Forward Declaration. */
1488 typedef void (*ASC_ISR_CALLBACK) (struct asc_dvc_var *, ASC_QDONE_INFO *);
1489 typedef int (*ASC_EXE_CALLBACK) (struct asc_dvc_var *, ASC_SCSI_Q *);
1491 typedef struct asc_dvc_var {
1495 ushort bug_fix_cntl;
1497 ASC_ISR_CALLBACK isr_callback;
1498 ASC_EXE_CALLBACK exe_callback;
1499 ASC_SCSI_BIT_ID_TYPE init_sdtr;
1500 ASC_SCSI_BIT_ID_TYPE sdtr_done;
1501 ASC_SCSI_BIT_ID_TYPE use_tagged_qng;
1502 ASC_SCSI_BIT_ID_TYPE unit_not_ready;
1503 ASC_SCSI_BIT_ID_TYPE queue_full_or_busy;
1504 ASC_SCSI_BIT_ID_TYPE start_motor;
1505 uchar scsi_reset_wait;
1508 uchar max_total_qng;
1509 uchar cur_total_qng;
1510 uchar in_critical_cnt;
1512 uchar last_q_shortage;
1514 uchar cur_dvc_qng[ASC_MAX_TID + 1];
1515 uchar max_dvc_qng[ASC_MAX_TID + 1];
1516 ASC_SCSI_Q *scsiq_busy_head[ASC_MAX_TID + 1];
1517 ASC_SCSI_Q *scsiq_busy_tail[ASC_MAX_TID + 1];
1518 uchar sdtr_period_tbl[ASC_MAX_SYN_XFER_NO];
1520 ASC_SCSI_BIT_ID_TYPE pci_fix_asyn_xfer_always;
1523 uchar dos_int13_table[ASC_MAX_TID + 1];
1524 ASC_DCNT max_dma_count;
1525 ASC_SCSI_BIT_ID_TYPE no_scam;
1526 ASC_SCSI_BIT_ID_TYPE pci_fix_asyn_xfer;
1527 uchar max_sdtr_index;
1528 uchar host_init_sdtr_index;
1529 struct asc_board *drv_ptr;
1533 typedef struct asc_dvc_inq_info {
1534 uchar type[ASC_MAX_TID + 1][ASC_MAX_LUN + 1];
1537 typedef struct asc_cap_info {
1542 typedef struct asc_cap_info_array {
1543 ASC_CAP_INFO cap_info[ASC_MAX_TID + 1][ASC_MAX_LUN + 1];
1544 } ASC_CAP_INFO_ARRAY;
1546 #define ASC_MCNTL_NO_SEL_TIMEOUT (ushort)0x0001
1547 #define ASC_MCNTL_NULL_TARGET (ushort)0x0002
1548 #define ASC_CNTL_INITIATOR (ushort)0x0001
1549 #define ASC_CNTL_BIOS_GT_1GB (ushort)0x0002
1550 #define ASC_CNTL_BIOS_GT_2_DISK (ushort)0x0004
1551 #define ASC_CNTL_BIOS_REMOVABLE (ushort)0x0008
1552 #define ASC_CNTL_NO_SCAM (ushort)0x0010
1553 #define ASC_CNTL_INT_MULTI_Q (ushort)0x0080
1554 #define ASC_CNTL_NO_LUN_SUPPORT (ushort)0x0040
1555 #define ASC_CNTL_NO_VERIFY_COPY (ushort)0x0100
1556 #define ASC_CNTL_RESET_SCSI (ushort)0x0200
1557 #define ASC_CNTL_INIT_INQUIRY (ushort)0x0400
1558 #define ASC_CNTL_INIT_VERBOSE (ushort)0x0800
1559 #define ASC_CNTL_SCSI_PARITY (ushort)0x1000
1560 #define ASC_CNTL_BURST_MODE (ushort)0x2000
1561 #define ASC_CNTL_SDTR_ENABLE_ULTRA (ushort)0x4000
1562 #define ASC_EEP_DVC_CFG_BEG_VL 2
1563 #define ASC_EEP_MAX_DVC_ADDR_VL 15
1564 #define ASC_EEP_DVC_CFG_BEG 32
1565 #define ASC_EEP_MAX_DVC_ADDR 45
1566 #define ASC_EEP_DEFINED_WORDS 10
1567 #define ASC_EEP_MAX_ADDR 63
1568 #define ASC_EEP_RES_WORDS 0
1569 #define ASC_EEP_MAX_RETRY 20
1570 #define ASC_MAX_INIT_BUSY_RETRY 8
1571 #define ASC_EEP_ISA_PNP_WSIZE 16
1574 * These macros keep the chip SCSI id and ISA DMA speed
1575 * bitfields in board order. C bitfields aren't portable
1576 * between big and little-endian platforms so they are
1580 #define ASC_EEP_GET_CHIP_ID(cfg) ((cfg)->id_speed & 0x0f)
1581 #define ASC_EEP_GET_DMA_SPD(cfg) (((cfg)->id_speed & 0xf0) >> 4)
1582 #define ASC_EEP_SET_CHIP_ID(cfg, sid) \
1583 ((cfg)->id_speed = ((cfg)->id_speed & 0xf0) | ((sid) & ASC_MAX_TID))
1584 #define ASC_EEP_SET_DMA_SPD(cfg, spd) \
1585 ((cfg)->id_speed = ((cfg)->id_speed & 0x0f) | ((spd) & 0x0f) << 4)
1587 typedef struct asceep_config {
1594 uchar max_total_qng;
1597 uchar power_up_wait;
1599 uchar id_speed; /* low order 4 bits is chip scsi id */
1600 /* high order 4 bits is isa dma speed */
1601 uchar dos_int13_table[ASC_MAX_TID + 1];
1602 uchar adapter_info[6];
1607 #define ASC_PCI_CFG_LSW_SCSI_PARITY 0x0800
1608 #define ASC_PCI_CFG_LSW_BURST_MODE 0x0080
1609 #define ASC_PCI_CFG_LSW_INTR_ABLE 0x0020
1611 #define ASC_EEP_CMD_READ 0x80
1612 #define ASC_EEP_CMD_WRITE 0x40
1613 #define ASC_EEP_CMD_WRITE_ABLE 0x30
1614 #define ASC_EEP_CMD_WRITE_DISABLE 0x00
1615 #define ASC_OVERRUN_BSIZE 0x00000048UL
1616 #define ASC_CTRL_BREAK_ONCE 0x0001
1617 #define ASC_CTRL_BREAK_STAY_IDLE 0x0002
1618 #define ASCV_MSGOUT_BEG 0x0000
1619 #define ASCV_MSGOUT_SDTR_PERIOD (ASCV_MSGOUT_BEG+3)
1620 #define ASCV_MSGOUT_SDTR_OFFSET (ASCV_MSGOUT_BEG+4)
1621 #define ASCV_BREAK_SAVED_CODE (ushort)0x0006
1622 #define ASCV_MSGIN_BEG (ASCV_MSGOUT_BEG+8)
1623 #define ASCV_MSGIN_SDTR_PERIOD (ASCV_MSGIN_BEG+3)
1624 #define ASCV_MSGIN_SDTR_OFFSET (ASCV_MSGIN_BEG+4)
1625 #define ASCV_SDTR_DATA_BEG (ASCV_MSGIN_BEG+8)
1626 #define ASCV_SDTR_DONE_BEG (ASCV_SDTR_DATA_BEG+8)
1627 #define ASCV_MAX_DVC_QNG_BEG (ushort)0x0020
1628 #define ASCV_BREAK_ADDR (ushort)0x0028
1629 #define ASCV_BREAK_NOTIFY_COUNT (ushort)0x002A
1630 #define ASCV_BREAK_CONTROL (ushort)0x002C
1631 #define ASCV_BREAK_HIT_COUNT (ushort)0x002E
1633 #define ASCV_ASCDVC_ERR_CODE_W (ushort)0x0030
1634 #define ASCV_MCODE_CHKSUM_W (ushort)0x0032
1635 #define ASCV_MCODE_SIZE_W (ushort)0x0034
1636 #define ASCV_STOP_CODE_B (ushort)0x0036
1637 #define ASCV_DVC_ERR_CODE_B (ushort)0x0037
1638 #define ASCV_OVERRUN_PADDR_D (ushort)0x0038
1639 #define ASCV_OVERRUN_BSIZE_D (ushort)0x003C
1640 #define ASCV_HALTCODE_W (ushort)0x0040
1641 #define ASCV_CHKSUM_W (ushort)0x0042
1642 #define ASCV_MC_DATE_W (ushort)0x0044
1643 #define ASCV_MC_VER_W (ushort)0x0046
1644 #define ASCV_NEXTRDY_B (ushort)0x0048
1645 #define ASCV_DONENEXT_B (ushort)0x0049
1646 #define ASCV_USE_TAGGED_QNG_B (ushort)0x004A
1647 #define ASCV_SCSIBUSY_B (ushort)0x004B
1648 #define ASCV_Q_DONE_IN_PROGRESS_B (ushort)0x004C
1649 #define ASCV_CURCDB_B (ushort)0x004D
1650 #define ASCV_RCLUN_B (ushort)0x004E
1651 #define ASCV_BUSY_QHEAD_B (ushort)0x004F
1652 #define ASCV_DISC1_QHEAD_B (ushort)0x0050
1653 #define ASCV_DISC_ENABLE_B (ushort)0x0052
1654 #define ASCV_CAN_TAGGED_QNG_B (ushort)0x0053
1655 #define ASCV_HOSTSCSI_ID_B (ushort)0x0055
1656 #define ASCV_MCODE_CNTL_B (ushort)0x0056
1657 #define ASCV_NULL_TARGET_B (ushort)0x0057
1658 #define ASCV_FREE_Q_HEAD_W (ushort)0x0058
1659 #define ASCV_DONE_Q_TAIL_W (ushort)0x005A
1660 #define ASCV_FREE_Q_HEAD_B (ushort)(ASCV_FREE_Q_HEAD_W+1)
1661 #define ASCV_DONE_Q_TAIL_B (ushort)(ASCV_DONE_Q_TAIL_W+1)
1662 #define ASCV_HOST_FLAG_B (ushort)0x005D
1663 #define ASCV_TOTAL_READY_Q_B (ushort)0x0064
1664 #define ASCV_VER_SERIAL_B (ushort)0x0065
1665 #define ASCV_HALTCODE_SAVED_W (ushort)0x0066
1666 #define ASCV_WTM_FLAG_B (ushort)0x0068
1667 #define ASCV_RISC_FLAG_B (ushort)0x006A
1668 #define ASCV_REQ_SG_LIST_QP (ushort)0x006B
1669 #define ASC_HOST_FLAG_IN_ISR 0x01
1670 #define ASC_HOST_FLAG_ACK_INT 0x02
1671 #define ASC_RISC_FLAG_GEN_INT 0x01
1672 #define ASC_RISC_FLAG_REQ_SG_LIST 0x02
1673 #define IOP_CTRL (0x0F)
1674 #define IOP_STATUS (0x0E)
1675 #define IOP_INT_ACK IOP_STATUS
1676 #define IOP_REG_IFC (0x0D)
1677 #define IOP_SYN_OFFSET (0x0B)
1678 #define IOP_EXTRA_CONTROL (0x0D)
1679 #define IOP_REG_PC (0x0C)
1680 #define IOP_RAM_ADDR (0x0A)
1681 #define IOP_RAM_DATA (0x08)
1682 #define IOP_EEP_DATA (0x06)
1683 #define IOP_EEP_CMD (0x07)
1684 #define IOP_VERSION (0x03)
1685 #define IOP_CONFIG_HIGH (0x04)
1686 #define IOP_CONFIG_LOW (0x02)
1687 #define IOP_SIG_BYTE (0x01)
1688 #define IOP_SIG_WORD (0x00)
1689 #define IOP_REG_DC1 (0x0E)
1690 #define IOP_REG_DC0 (0x0C)
1691 #define IOP_REG_SB (0x0B)
1692 #define IOP_REG_DA1 (0x0A)
1693 #define IOP_REG_DA0 (0x08)
1694 #define IOP_REG_SC (0x09)
1695 #define IOP_DMA_SPEED (0x07)
1696 #define IOP_REG_FLAG (0x07)
1697 #define IOP_FIFO_H (0x06)
1698 #define IOP_FIFO_L (0x04)
1699 #define IOP_REG_ID (0x05)
1700 #define IOP_REG_QP (0x03)
1701 #define IOP_REG_IH (0x02)
1702 #define IOP_REG_IX (0x01)
1703 #define IOP_REG_AX (0x00)
1704 #define IFC_REG_LOCK (0x00)
1705 #define IFC_REG_UNLOCK (0x09)
1706 #define IFC_WR_EN_FILTER (0x10)
1707 #define IFC_RD_NO_EEPROM (0x10)
1708 #define IFC_SLEW_RATE (0x20)
1709 #define IFC_ACT_NEG (0x40)
1710 #define IFC_INP_FILTER (0x80)
1711 #define IFC_INIT_DEFAULT (IFC_ACT_NEG | IFC_REG_UNLOCK)
1712 #define SC_SEL (uchar)(0x80)
1713 #define SC_BSY (uchar)(0x40)
1714 #define SC_ACK (uchar)(0x20)
1715 #define SC_REQ (uchar)(0x10)
1716 #define SC_ATN (uchar)(0x08)
1717 #define SC_IO (uchar)(0x04)
1718 #define SC_CD (uchar)(0x02)
1719 #define SC_MSG (uchar)(0x01)
1720 #define SEC_SCSI_CTL (uchar)(0x80)
1721 #define SEC_ACTIVE_NEGATE (uchar)(0x40)
1722 #define SEC_SLEW_RATE (uchar)(0x20)
1723 #define SEC_ENABLE_FILTER (uchar)(0x10)
1724 #define ASC_HALT_EXTMSG_IN (ushort)0x8000
1725 #define ASC_HALT_CHK_CONDITION (ushort)0x8100
1726 #define ASC_HALT_SS_QUEUE_FULL (ushort)0x8200
1727 #define ASC_HALT_DISABLE_ASYN_USE_SYN_FIX (ushort)0x8300
1728 #define ASC_HALT_ENABLE_ASYN_USE_SYN_FIX (ushort)0x8400
1729 #define ASC_HALT_SDTR_REJECTED (ushort)0x4000
1730 #define ASC_HALT_HOST_COPY_SG_LIST_TO_RISC ( ushort )0x2000
1731 #define ASC_MAX_QNO 0xF8
1732 #define ASC_DATA_SEC_BEG (ushort)0x0080
1733 #define ASC_DATA_SEC_END (ushort)0x0080
1734 #define ASC_CODE_SEC_BEG (ushort)0x0080
1735 #define ASC_CODE_SEC_END (ushort)0x0080
1736 #define ASC_QADR_BEG (0x4000)
1737 #define ASC_QADR_USED (ushort)(ASC_MAX_QNO * 64)
1738 #define ASC_QADR_END (ushort)0x7FFF
1739 #define ASC_QLAST_ADR (ushort)0x7FC0
1740 #define ASC_QBLK_SIZE 0x40
1741 #define ASC_BIOS_DATA_QBEG 0xF8
1742 #define ASC_MIN_ACTIVE_QNO 0x01
1743 #define ASC_QLINK_END 0xFF
1744 #define ASC_EEPROM_WORDS 0x10
1745 #define ASC_MAX_MGS_LEN 0x10
1746 #define ASC_BIOS_ADDR_DEF 0xDC00
1747 #define ASC_BIOS_SIZE 0x3800
1748 #define ASC_BIOS_RAM_OFF 0x3800
1749 #define ASC_BIOS_RAM_SIZE 0x800
1750 #define ASC_BIOS_MIN_ADDR 0xC000
1751 #define ASC_BIOS_MAX_ADDR 0xEC00
1752 #define ASC_BIOS_BANK_SIZE 0x0400
1753 #define ASC_MCODE_START_ADDR 0x0080
1754 #define ASC_CFG0_HOST_INT_ON 0x0020
1755 #define ASC_CFG0_BIOS_ON 0x0040
1756 #define ASC_CFG0_VERA_BURST_ON 0x0080
1757 #define ASC_CFG0_SCSI_PARITY_ON 0x0800
1758 #define ASC_CFG1_SCSI_TARGET_ON 0x0080
1759 #define ASC_CFG1_LRAM_8BITS_ON 0x0800
1760 #define ASC_CFG_MSW_CLR_MASK 0x3080
1761 #define CSW_TEST1 (ASC_CS_TYPE)0x8000
1762 #define CSW_AUTO_CONFIG (ASC_CS_TYPE)0x4000
1763 #define CSW_RESERVED1 (ASC_CS_TYPE)0x2000
1764 #define CSW_IRQ_WRITTEN (ASC_CS_TYPE)0x1000
1765 #define CSW_33MHZ_SELECTED (ASC_CS_TYPE)0x0800
1766 #define CSW_TEST2 (ASC_CS_TYPE)0x0400
1767 #define CSW_TEST3 (ASC_CS_TYPE)0x0200
1768 #define CSW_RESERVED2 (ASC_CS_TYPE)0x0100
1769 #define CSW_DMA_DONE (ASC_CS_TYPE)0x0080
1770 #define CSW_FIFO_RDY (ASC_CS_TYPE)0x0040
1771 #define CSW_EEP_READ_DONE (ASC_CS_TYPE)0x0020
1772 #define CSW_HALTED (ASC_CS_TYPE)0x0010
1773 #define CSW_SCSI_RESET_ACTIVE (ASC_CS_TYPE)0x0008
1774 #define CSW_PARITY_ERR (ASC_CS_TYPE)0x0004
1775 #define CSW_SCSI_RESET_LATCH (ASC_CS_TYPE)0x0002
1776 #define CSW_INT_PENDING (ASC_CS_TYPE)0x0001
1777 #define CIW_CLR_SCSI_RESET_INT (ASC_CS_TYPE)0x1000
1778 #define CIW_INT_ACK (ASC_CS_TYPE)0x0100
1779 #define CIW_TEST1 (ASC_CS_TYPE)0x0200
1780 #define CIW_TEST2 (ASC_CS_TYPE)0x0400
1781 #define CIW_SEL_33MHZ (ASC_CS_TYPE)0x0800
1782 #define CIW_IRQ_ACT (ASC_CS_TYPE)0x1000
1783 #define CC_CHIP_RESET (uchar)0x80
1784 #define CC_SCSI_RESET (uchar)0x40
1785 #define CC_HALT (uchar)0x20
1786 #define CC_SINGLE_STEP (uchar)0x10
1787 #define CC_DMA_ABLE (uchar)0x08
1788 #define CC_TEST (uchar)0x04
1789 #define CC_BANK_ONE (uchar)0x02
1790 #define CC_DIAG (uchar)0x01
1791 #define ASC_1000_ID0W 0x04C1
1792 #define ASC_1000_ID0W_FIX 0x00C1
1793 #define ASC_1000_ID1B 0x25
1794 #define ASC_EISA_BIG_IOP_GAP (0x1C30-0x0C50)
1795 #define ASC_EISA_SMALL_IOP_GAP (0x0020)
1796 #define ASC_EISA_MIN_IOP_ADDR (0x0C30)
1797 #define ASC_EISA_MAX_IOP_ADDR (0xFC50)
1798 #define ASC_EISA_REV_IOP_MASK (0x0C83)
1799 #define ASC_EISA_PID_IOP_MASK (0x0C80)
1800 #define ASC_EISA_CFG_IOP_MASK (0x0C86)
1801 #define ASC_GET_EISA_SLOT(iop) (PortAddr)((iop) & 0xF000)
1802 #define ASC_EISA_ID_740 0x01745004UL
1803 #define ASC_EISA_ID_750 0x01755004UL
1804 #define INS_HALTINT (ushort)0x6281
1805 #define INS_HALT (ushort)0x6280
1806 #define INS_SINT (ushort)0x6200
1807 #define INS_RFLAG_WTM (ushort)0x7380
1808 #define ASC_MC_SAVE_CODE_WSIZE 0x500
1809 #define ASC_MC_SAVE_DATA_WSIZE 0x40
1811 typedef struct asc_mc_saved {
1812 ushort data[ASC_MC_SAVE_DATA_WSIZE];
1813 ushort code[ASC_MC_SAVE_CODE_WSIZE];
1816 #define AscGetQDoneInProgress(port) AscReadLramByte((port), ASCV_Q_DONE_IN_PROGRESS_B)
1817 #define AscPutQDoneInProgress(port, val) AscWriteLramByte((port), ASCV_Q_DONE_IN_PROGRESS_B, val)
1818 #define AscGetVarFreeQHead(port) AscReadLramWord((port), ASCV_FREE_Q_HEAD_W)
1819 #define AscGetVarDoneQTail(port) AscReadLramWord((port), ASCV_DONE_Q_TAIL_W)
1820 #define AscPutVarFreeQHead(port, val) AscWriteLramWord((port), ASCV_FREE_Q_HEAD_W, val)
1821 #define AscPutVarDoneQTail(port, val) AscWriteLramWord((port), ASCV_DONE_Q_TAIL_W, val)
1822 #define AscGetRiscVarFreeQHead(port) AscReadLramByte((port), ASCV_NEXTRDY_B)
1823 #define AscGetRiscVarDoneQTail(port) AscReadLramByte((port), ASCV_DONENEXT_B)
1824 #define AscPutRiscVarFreeQHead(port, val) AscWriteLramByte((port), ASCV_NEXTRDY_B, val)
1825 #define AscPutRiscVarDoneQTail(port, val) AscWriteLramByte((port), ASCV_DONENEXT_B, val)
1826 #define AscPutMCodeSDTRDoneAtID(port, id, data) AscWriteLramByte((port), (ushort)((ushort)ASCV_SDTR_DONE_BEG+(ushort)id), (data));
1827 #define AscGetMCodeSDTRDoneAtID(port, id) AscReadLramByte((port), (ushort)((ushort)ASCV_SDTR_DONE_BEG+(ushort)id));
1828 #define AscPutMCodeInitSDTRAtID(port, id, data) AscWriteLramByte((port), (ushort)((ushort)ASCV_SDTR_DATA_BEG+(ushort)id), data);
1829 #define AscGetMCodeInitSDTRAtID(port, id) AscReadLramByte((port), (ushort)((ushort)ASCV_SDTR_DATA_BEG+(ushort)id));
1830 #define AscSynIndexToPeriod(index) (uchar)(asc_dvc->sdtr_period_tbl[ (index) ])
1831 #define AscGetChipSignatureByte(port) (uchar)inp((port)+IOP_SIG_BYTE)
1832 #define AscGetChipSignatureWord(port) (ushort)inpw((port)+IOP_SIG_WORD)
1833 #define AscGetChipVerNo(port) (uchar)inp((port)+IOP_VERSION)
1834 #define AscGetChipCfgLsw(port) (ushort)inpw((port)+IOP_CONFIG_LOW)
1835 #define AscGetChipCfgMsw(port) (ushort)inpw((port)+IOP_CONFIG_HIGH)
1836 #define AscSetChipCfgLsw(port, data) outpw((port)+IOP_CONFIG_LOW, data)
1837 #define AscSetChipCfgMsw(port, data) outpw((port)+IOP_CONFIG_HIGH, data)
1838 #define AscGetChipEEPCmd(port) (uchar)inp((port)+IOP_EEP_CMD)
1839 #define AscSetChipEEPCmd(port, data) outp((port)+IOP_EEP_CMD, data)
1840 #define AscGetChipEEPData(port) (ushort)inpw((port)+IOP_EEP_DATA)
1841 #define AscSetChipEEPData(port, data) outpw((port)+IOP_EEP_DATA, data)
1842 #define AscGetChipLramAddr(port) (ushort)inpw((PortAddr)((port)+IOP_RAM_ADDR))
1843 #define AscSetChipLramAddr(port, addr) outpw((PortAddr)((port)+IOP_RAM_ADDR), addr)
1844 #define AscGetChipLramData(port) (ushort)inpw((port)+IOP_RAM_DATA)
1845 #define AscSetChipLramData(port, data) outpw((port)+IOP_RAM_DATA, data)
1846 #define AscGetChipIFC(port) (uchar)inp((port)+IOP_REG_IFC)
1847 #define AscSetChipIFC(port, data) outp((port)+IOP_REG_IFC, data)
1848 #define AscGetChipStatus(port) (ASC_CS_TYPE)inpw((port)+IOP_STATUS)
1849 #define AscSetChipStatus(port, cs_val) outpw((port)+IOP_STATUS, cs_val)
1850 #define AscGetChipControl(port) (uchar)inp((port)+IOP_CTRL)
1851 #define AscSetChipControl(port, cc_val) outp((port)+IOP_CTRL, cc_val)
1852 #define AscGetChipSyn(port) (uchar)inp((port)+IOP_SYN_OFFSET)
1853 #define AscSetChipSyn(port, data) outp((port)+IOP_SYN_OFFSET, data)
1854 #define AscSetPCAddr(port, data) outpw((port)+IOP_REG_PC, data)
1855 #define AscGetPCAddr(port) (ushort)inpw((port)+IOP_REG_PC)
1856 #define AscIsIntPending(port) (AscGetChipStatus(port) & (CSW_INT_PENDING | CSW_SCSI_RESET_LATCH))
1857 #define AscGetChipScsiID(port) ((AscGetChipCfgLsw(port) >> 8) & ASC_MAX_TID)
1858 #define AscGetExtraControl(port) (uchar)inp((port)+IOP_EXTRA_CONTROL)
1859 #define AscSetExtraControl(port, data) outp((port)+IOP_EXTRA_CONTROL, data)
1860 #define AscReadChipAX(port) (ushort)inpw((port)+IOP_REG_AX)
1861 #define AscWriteChipAX(port, data) outpw((port)+IOP_REG_AX, data)
1862 #define AscReadChipIX(port) (uchar)inp((port)+IOP_REG_IX)
1863 #define AscWriteChipIX(port, data) outp((port)+IOP_REG_IX, data)
1864 #define AscReadChipIH(port) (ushort)inpw((port)+IOP_REG_IH)
1865 #define AscWriteChipIH(port, data) outpw((port)+IOP_REG_IH, data)
1866 #define AscReadChipQP(port) (uchar)inp((port)+IOP_REG_QP)
1867 #define AscWriteChipQP(port, data) outp((port)+IOP_REG_QP, data)
1868 #define AscReadChipFIFO_L(port) (ushort)inpw((port)+IOP_REG_FIFO_L)
1869 #define AscWriteChipFIFO_L(port, data) outpw((port)+IOP_REG_FIFO_L, data)
1870 #define AscReadChipFIFO_H(port) (ushort)inpw((port)+IOP_REG_FIFO_H)
1871 #define AscWriteChipFIFO_H(port, data) outpw((port)+IOP_REG_FIFO_H, data)
1872 #define AscReadChipDmaSpeed(port) (uchar)inp((port)+IOP_DMA_SPEED)
1873 #define AscWriteChipDmaSpeed(port, data) outp((port)+IOP_DMA_SPEED, data)
1874 #define AscReadChipDA0(port) (ushort)inpw((port)+IOP_REG_DA0)
1875 #define AscWriteChipDA0(port) outpw((port)+IOP_REG_DA0, data)
1876 #define AscReadChipDA1(port) (ushort)inpw((port)+IOP_REG_DA1)
1877 #define AscWriteChipDA1(port) outpw((port)+IOP_REG_DA1, data)
1878 #define AscReadChipDC0(port) (ushort)inpw((port)+IOP_REG_DC0)
1879 #define AscWriteChipDC0(port) outpw((port)+IOP_REG_DC0, data)
1880 #define AscReadChipDC1(port) (ushort)inpw((port)+IOP_REG_DC1)
1881 #define AscWriteChipDC1(port) outpw((port)+IOP_REG_DC1, data)
1882 #define AscReadChipDvcID(port) (uchar)inp((port)+IOP_REG_ID)
1883 #define AscWriteChipDvcID(port, data) outp((port)+IOP_REG_ID, data)
1885 static int AscWriteEEPCmdReg(PortAddr iop_base, uchar cmd_reg);
1886 static int AscWriteEEPDataReg(PortAddr iop_base, ushort data_reg);
1887 static void AscWaitEEPRead(void);
1888 static void AscWaitEEPWrite(void);
1889 static ushort AscReadEEPWord(PortAddr, uchar);
1890 static ushort AscWriteEEPWord(PortAddr, uchar, ushort);
1891 static ushort AscGetEEPConfig(PortAddr, ASCEEP_CONFIG *, ushort);
1892 static int AscSetEEPConfigOnce(PortAddr, ASCEEP_CONFIG *, ushort);
1893 static int AscSetEEPConfig(PortAddr, ASCEEP_CONFIG *, ushort);
1894 static int AscStartChip(PortAddr);
1895 static int AscStopChip(PortAddr);
1896 static void AscSetChipIH(PortAddr, ushort);
1897 static int AscIsChipHalted(PortAddr);
1898 static void AscAckInterrupt(PortAddr);
1899 static void AscDisableInterrupt(PortAddr);
1900 static void AscEnableInterrupt(PortAddr);
1901 static void AscSetBank(PortAddr, uchar);
1902 static int AscResetChipAndScsiBus(ASC_DVC_VAR *);
1904 static ushort AscGetIsaDmaChannel(PortAddr);
1905 static ushort AscSetIsaDmaChannel(PortAddr, ushort);
1906 static uchar AscSetIsaDmaSpeed(PortAddr, uchar);
1907 static uchar AscGetIsaDmaSpeed(PortAddr);
1908 #endif /* CONFIG_ISA */
1909 static uchar AscReadLramByte(PortAddr, ushort);
1910 static ushort AscReadLramWord(PortAddr, ushort);
1911 #if CC_VERY_LONG_SG_LIST
1912 static ASC_DCNT AscReadLramDWord(PortAddr, ushort);
1913 #endif /* CC_VERY_LONG_SG_LIST */
1914 static void AscWriteLramWord(PortAddr, ushort, ushort);
1915 static void AscWriteLramByte(PortAddr, ushort, uchar);
1916 static ASC_DCNT AscMemSumLramWord(PortAddr, ushort, int);
1917 static void AscMemWordSetLram(PortAddr, ushort, ushort, int);
1918 static void AscMemWordCopyPtrToLram(PortAddr, ushort, uchar *, int);
1919 static void AscMemDWordCopyPtrToLram(PortAddr, ushort, uchar *, int);
1920 static void AscMemWordCopyPtrFromLram(PortAddr, ushort, uchar *, int);
1921 static ushort AscInitAscDvcVar(ASC_DVC_VAR *);
1922 static ushort AscInitFromEEP(ASC_DVC_VAR *);
1923 static ushort AscInitFromAscDvcVar(ASC_DVC_VAR *);
1924 static ushort AscInitMicroCodeVar(ASC_DVC_VAR *);
1925 static int AscTestExternalLram(ASC_DVC_VAR *);
1926 static uchar AscMsgOutSDTR(ASC_DVC_VAR *, uchar, uchar);
1927 static uchar AscCalSDTRData(ASC_DVC_VAR *, uchar, uchar);
1928 static void AscSetChipSDTR(PortAddr, uchar, uchar);
1929 static uchar AscGetSynPeriodIndex(ASC_DVC_VAR *, uchar);
1930 static uchar AscAllocFreeQueue(PortAddr, uchar);
1931 static uchar AscAllocMultipleFreeQueue(PortAddr, uchar, uchar);
1932 static int AscHostReqRiscHalt(PortAddr);
1933 static int AscStopQueueExe(PortAddr);
1934 static int AscSendScsiQueue(ASC_DVC_VAR *,
1935 ASC_SCSI_Q *scsiq, uchar n_q_required);
1936 static int AscPutReadyQueue(ASC_DVC_VAR *, ASC_SCSI_Q *, uchar);
1937 static int AscPutReadySgListQueue(ASC_DVC_VAR *, ASC_SCSI_Q *, uchar);
1938 static int AscSetChipSynRegAtID(PortAddr, uchar, uchar);
1939 static int AscSetRunChipSynRegAtID(PortAddr, uchar, uchar);
1940 static ushort AscInitLram(ASC_DVC_VAR *);
1941 static ushort AscInitQLinkVar(ASC_DVC_VAR *);
1942 static int AscSetLibErrorCode(ASC_DVC_VAR *, ushort);
1943 static int AscIsrChipHalted(ASC_DVC_VAR *);
1944 static uchar _AscCopyLramScsiDoneQ(PortAddr, ushort,
1945 ASC_QDONE_INFO *, ASC_DCNT);
1946 static int AscIsrQDone(ASC_DVC_VAR *);
1947 static int AscCompareString(uchar *, uchar *, int);
1949 static ushort AscGetEisaChipCfg(PortAddr);
1950 static ASC_DCNT AscGetEisaProductID(PortAddr);
1951 static PortAddr AscSearchIOPortAddrEISA(PortAddr);
1952 static PortAddr AscSearchIOPortAddr11(PortAddr);
1953 static PortAddr AscSearchIOPortAddr(PortAddr, ushort);
1954 static void AscSetISAPNPWaitForKey(void);
1955 #endif /* CONFIG_ISA */
1956 static uchar AscGetChipScsiCtrl(PortAddr);
1957 static uchar AscSetChipScsiID(PortAddr, uchar);
1958 static uchar AscGetChipVersion(PortAddr, ushort);
1959 static ushort AscGetChipBusType(PortAddr);
1960 static ASC_DCNT AscLoadMicroCode(PortAddr, ushort, uchar *, ushort);
1961 static int AscFindSignature(PortAddr);
1962 static void AscToggleIRQAct(PortAddr);
1963 static uchar AscGetChipIRQ(PortAddr, ushort);
1964 static uchar AscSetChipIRQ(PortAddr, uchar, ushort);
1965 static ushort AscGetChipBiosAddress(PortAddr, ushort);
1966 static inline ulong DvcEnterCritical(void);
1967 static inline void DvcLeaveCritical(ulong);
1969 static uchar DvcReadPCIConfigByte(ASC_DVC_VAR *, ushort);
1970 static void DvcWritePCIConfigByte(ASC_DVC_VAR *, ushort, uchar);
1971 #endif /* CONFIG_PCI */
1972 static ushort AscGetChipBiosAddress(PortAddr, ushort);
1973 static void DvcSleepMilliSecond(ASC_DCNT);
1974 static void DvcDelayNanoSecond(ASC_DVC_VAR *, ASC_DCNT);
1975 static void DvcPutScsiQ(PortAddr, ushort, uchar *, int);
1976 static void DvcGetQinfo(PortAddr, ushort, uchar *, int);
1977 static ushort AscInitGetConfig(ASC_DVC_VAR *);
1978 static ushort AscInitSetConfig(ASC_DVC_VAR *);
1979 static ushort AscInitAsc1000Driver(ASC_DVC_VAR *);
1980 static void AscAsyncFix(ASC_DVC_VAR *, uchar, ASC_SCSI_INQUIRY *);
1981 static int AscTagQueuingSafe(ASC_SCSI_INQUIRY *);
1982 static void AscInquiryHandling(ASC_DVC_VAR *, uchar, ASC_SCSI_INQUIRY *);
1983 static int AscExeScsiQueue(ASC_DVC_VAR *, ASC_SCSI_Q *);
1984 static int AscISR(ASC_DVC_VAR *);
1985 static uint AscGetNumOfFreeQueue(ASC_DVC_VAR *, uchar, uchar);
1986 static int AscSgListToQueue(int);
1988 static void AscEnableIsaDma(uchar);
1989 #endif /* CONFIG_ISA */
1990 static ASC_DCNT AscGetMaxDmaCount(ushort);
1991 static const char *advansys_info(struct Scsi_Host *shost);
1994 * --- Adv Library Constants and Macros
1997 #define ADV_LIB_VERSION_MAJOR 5
1998 #define ADV_LIB_VERSION_MINOR 14
2001 * Define Adv Library required special types.
2005 * Portable Data Types
2007 * Any instance where a 32-bit long or pointer type is assumed
2008 * for precision or HW defined structures, the following define
2009 * types must be used. In Linux the char, short, and int types
2010 * are all consistent at 8, 16, and 32 bits respectively. Pointers
2011 * and long types are 64 bits on Alpha and UltraSPARC.
2013 #define ADV_PADDR __u32 /* Physical address data type. */
2014 #define ADV_VADDR __u32 /* Virtual address data type. */
2015 #define ADV_DCNT __u32 /* Unsigned Data count type. */
2016 #define ADV_SDCNT __s32 /* Signed Data count type. */
2019 * These macros are used to convert a virtual address to a
2020 * 32-bit value. This currently can be used on Linux Alpha
2021 * which uses 64-bit virtual address but a 32-bit bus address.
2022 * This is likely to break in the future, but doing this now
2023 * will give us time to change the HW and FW to handle 64-bit
2026 #define ADV_VADDR_TO_U32 virt_to_bus
2027 #define ADV_U32_TO_VADDR bus_to_virt
2029 #define AdvPortAddr void __iomem * /* Virtual memory address size */
2032 * Define Adv Library required memory access macros.
2034 #define ADV_MEM_READB(addr) readb(addr)
2035 #define ADV_MEM_READW(addr) readw(addr)
2036 #define ADV_MEM_WRITEB(addr, byte) writeb(byte, addr)
2037 #define ADV_MEM_WRITEW(addr, word) writew(word, addr)
2038 #define ADV_MEM_WRITEDW(addr, dword) writel(dword, addr)
2040 #define ADV_CARRIER_COUNT (ASC_DEF_MAX_HOST_QNG + 15)
2043 * For wide boards a CDB length maximum of 16 bytes
2046 #define ADV_MAX_CDB_LEN 16
2049 * Define total number of simultaneous maximum element scatter-gather
2050 * request blocks per wide adapter. ASC_DEF_MAX_HOST_QNG (253) is the
2051 * maximum number of outstanding commands per wide host adapter. Each
2052 * command uses one or more ADV_SG_BLOCK each with 15 scatter-gather
2053 * elements. Allow each command to have at least one ADV_SG_BLOCK structure.
2054 * This allows about 15 commands to have the maximum 17 ADV_SG_BLOCK
2055 * structures or 255 scatter-gather elements.
2058 #define ADV_TOT_SG_BLOCK ASC_DEF_MAX_HOST_QNG
2061 * Define Adv Library required maximum number of scatter-gather
2062 * elements per request.
2064 #define ADV_MAX_SG_LIST 255
2066 /* Number of SG blocks needed. */
2067 #define ADV_NUM_SG_BLOCK \
2068 ((ADV_MAX_SG_LIST + (NO_OF_SG_PER_BLOCK - 1))/NO_OF_SG_PER_BLOCK)
2070 /* Total contiguous memory needed for SG blocks. */
2071 #define ADV_SG_TOTAL_MEM_SIZE \
2072 (sizeof(ADV_SG_BLOCK) * ADV_NUM_SG_BLOCK)
2074 #define ADV_PAGE_SIZE PAGE_SIZE
2076 #define ADV_NUM_PAGE_CROSSING \
2077 ((ADV_SG_TOTAL_MEM_SIZE + (ADV_PAGE_SIZE - 1))/ADV_PAGE_SIZE)
2079 #define ADV_EEP_DVC_CFG_BEGIN (0x00)
2080 #define ADV_EEP_DVC_CFG_END (0x15)
2081 #define ADV_EEP_DVC_CTL_BEGIN (0x16) /* location of OEM name */
2082 #define ADV_EEP_MAX_WORD_ADDR (0x1E)
2084 #define ADV_EEP_DELAY_MS 100
2086 #define ADV_EEPROM_BIG_ENDIAN 0x8000 /* EEPROM Bit 15 */
2087 #define ADV_EEPROM_BIOS_ENABLE 0x4000 /* EEPROM Bit 14 */
2089 * For the ASC3550 Bit 13 is Termination Polarity control bit.
2090 * For later ICs Bit 13 controls whether the CIS (Card Information
2091 * Service Section) is loaded from EEPROM.
2093 #define ADV_EEPROM_TERM_POL 0x2000 /* EEPROM Bit 13 */
2094 #define ADV_EEPROM_CIS_LD 0x2000 /* EEPROM Bit 13 */
2098 * If EEPROM Bit 11 is 0 for Function 0, then Function 0 will specify
2099 * INT A in the PCI Configuration Space Int Pin field. If it is 1, then
2100 * Function 0 will specify INT B.
2102 * If EEPROM Bit 11 is 0 for Function 1, then Function 1 will specify
2103 * INT B in the PCI Configuration Space Int Pin field. If it is 1, then
2104 * Function 1 will specify INT A.
2106 #define ADV_EEPROM_INTAB 0x0800 /* EEPROM Bit 11 */
2108 typedef struct adveep_3550_config {
2109 /* Word Offset, Description */
2111 ushort cfg_lsw; /* 00 power up initialization */
2112 /* bit 13 set - Term Polarity Control */
2113 /* bit 14 set - BIOS Enable */
2114 /* bit 15 set - Big Endian Mode */
2115 ushort cfg_msw; /* 01 unused */
2116 ushort disc_enable; /* 02 disconnect enable */
2117 ushort wdtr_able; /* 03 Wide DTR able */
2118 ushort sdtr_able; /* 04 Synchronous DTR able */
2119 ushort start_motor; /* 05 send start up motor */
2120 ushort tagqng_able; /* 06 tag queuing able */
2121 ushort bios_scan; /* 07 BIOS device control */
2122 ushort scam_tolerant; /* 08 no scam */
2124 uchar adapter_scsi_id; /* 09 Host Adapter ID */
2125 uchar bios_boot_delay; /* power up wait */
2127 uchar scsi_reset_delay; /* 10 reset delay */
2128 uchar bios_id_lun; /* first boot device scsi id & lun */
2129 /* high nibble is lun */
2130 /* low nibble is scsi id */
2132 uchar termination; /* 11 0 - automatic */
2133 /* 1 - low off / high off */
2134 /* 2 - low off / high on */
2135 /* 3 - low on / high on */
2136 /* There is no low on / high off */
2138 uchar reserved1; /* reserved byte (not used) */
2140 ushort bios_ctrl; /* 12 BIOS control bits */
2141 /* bit 0 BIOS don't act as initiator. */
2142 /* bit 1 BIOS > 1 GB support */
2143 /* bit 2 BIOS > 2 Disk Support */
2144 /* bit 3 BIOS don't support removables */
2145 /* bit 4 BIOS support bootable CD */
2146 /* bit 5 BIOS scan enabled */
2147 /* bit 6 BIOS support multiple LUNs */
2148 /* bit 7 BIOS display of message */
2149 /* bit 8 SCAM disabled */
2150 /* bit 9 Reset SCSI bus during init. */
2152 /* bit 11 No verbose initialization. */
2153 /* bit 12 SCSI parity enabled */
2157 ushort ultra_able; /* 13 ULTRA speed able */
2158 ushort reserved2; /* 14 reserved */
2159 uchar max_host_qng; /* 15 maximum host queuing */
2160 uchar max_dvc_qng; /* maximum per device queuing */
2161 ushort dvc_cntl; /* 16 control bit for driver */
2162 ushort bug_fix; /* 17 control bit for bug fix */
2163 ushort serial_number_word1; /* 18 Board serial number word 1 */
2164 ushort serial_number_word2; /* 19 Board serial number word 2 */
2165 ushort serial_number_word3; /* 20 Board serial number word 3 */
2166 ushort check_sum; /* 21 EEP check sum */
2167 uchar oem_name[16]; /* 22 OEM name */
2168 ushort dvc_err_code; /* 30 last device driver error code */
2169 ushort adv_err_code; /* 31 last uc and Adv Lib error code */
2170 ushort adv_err_addr; /* 32 last uc error address */
2171 ushort saved_dvc_err_code; /* 33 saved last dev. driver error code */
2172 ushort saved_adv_err_code; /* 34 saved last uc and Adv Lib error code */
2173 ushort saved_adv_err_addr; /* 35 saved last uc error address */
2174 ushort num_of_err; /* 36 number of error */
2175 } ADVEEP_3550_CONFIG;
2177 typedef struct adveep_38C0800_config {
2178 /* Word Offset, Description */
2180 ushort cfg_lsw; /* 00 power up initialization */
2181 /* bit 13 set - Load CIS */
2182 /* bit 14 set - BIOS Enable */
2183 /* bit 15 set - Big Endian Mode */
2184 ushort cfg_msw; /* 01 unused */
2185 ushort disc_enable; /* 02 disconnect enable */
2186 ushort wdtr_able; /* 03 Wide DTR able */
2187 ushort sdtr_speed1; /* 04 SDTR Speed TID 0-3 */
2188 ushort start_motor; /* 05 send start up motor */
2189 ushort tagqng_able; /* 06 tag queuing able */
2190 ushort bios_scan; /* 07 BIOS device control */
2191 ushort scam_tolerant; /* 08 no scam */
2193 uchar adapter_scsi_id; /* 09 Host Adapter ID */
2194 uchar bios_boot_delay; /* power up wait */
2196 uchar scsi_reset_delay; /* 10 reset delay */
2197 uchar bios_id_lun; /* first boot device scsi id & lun */
2198 /* high nibble is lun */
2199 /* low nibble is scsi id */
2201 uchar termination_se; /* 11 0 - automatic */
2202 /* 1 - low off / high off */
2203 /* 2 - low off / high on */
2204 /* 3 - low on / high on */
2205 /* There is no low on / high off */
2207 uchar termination_lvd; /* 11 0 - automatic */
2208 /* 1 - low off / high off */
2209 /* 2 - low off / high on */
2210 /* 3 - low on / high on */
2211 /* There is no low on / high off */
2213 ushort bios_ctrl; /* 12 BIOS control bits */
2214 /* bit 0 BIOS don't act as initiator. */
2215 /* bit 1 BIOS > 1 GB support */
2216 /* bit 2 BIOS > 2 Disk Support */
2217 /* bit 3 BIOS don't support removables */
2218 /* bit 4 BIOS support bootable CD */
2219 /* bit 5 BIOS scan enabled */
2220 /* bit 6 BIOS support multiple LUNs */
2221 /* bit 7 BIOS display of message */
2222 /* bit 8 SCAM disabled */
2223 /* bit 9 Reset SCSI bus during init. */
2225 /* bit 11 No verbose initialization. */
2226 /* bit 12 SCSI parity enabled */
2230 ushort sdtr_speed2; /* 13 SDTR speed TID 4-7 */
2231 ushort sdtr_speed3; /* 14 SDTR speed TID 8-11 */
2232 uchar max_host_qng; /* 15 maximum host queueing */
2233 uchar max_dvc_qng; /* maximum per device queuing */
2234 ushort dvc_cntl; /* 16 control bit for driver */
2235 ushort sdtr_speed4; /* 17 SDTR speed 4 TID 12-15 */
2236 ushort serial_number_word1; /* 18 Board serial number word 1 */
2237 ushort serial_number_word2; /* 19 Board serial number word 2 */
2238 ushort serial_number_word3; /* 20 Board serial number word 3 */
2239 ushort check_sum; /* 21 EEP check sum */
2240 uchar oem_name[16]; /* 22 OEM name */
2241 ushort dvc_err_code; /* 30 last device driver error code */
2242 ushort adv_err_code; /* 31 last uc and Adv Lib error code */
2243 ushort adv_err_addr; /* 32 last uc error address */
2244 ushort saved_dvc_err_code; /* 33 saved last dev. driver error code */
2245 ushort saved_adv_err_code; /* 34 saved last uc and Adv Lib error code */
2246 ushort saved_adv_err_addr; /* 35 saved last uc error address */
2247 ushort reserved36; /* 36 reserved */
2248 ushort reserved37; /* 37 reserved */
2249 ushort reserved38; /* 38 reserved */
2250 ushort reserved39; /* 39 reserved */
2251 ushort reserved40; /* 40 reserved */
2252 ushort reserved41; /* 41 reserved */
2253 ushort reserved42; /* 42 reserved */
2254 ushort reserved43; /* 43 reserved */
2255 ushort reserved44; /* 44 reserved */
2256 ushort reserved45; /* 45 reserved */
2257 ushort reserved46; /* 46 reserved */
2258 ushort reserved47; /* 47 reserved */
2259 ushort reserved48; /* 48 reserved */
2260 ushort reserved49; /* 49 reserved */
2261 ushort reserved50; /* 50 reserved */
2262 ushort reserved51; /* 51 reserved */
2263 ushort reserved52; /* 52 reserved */
2264 ushort reserved53; /* 53 reserved */
2265 ushort reserved54; /* 54 reserved */
2266 ushort reserved55; /* 55 reserved */
2267 ushort cisptr_lsw; /* 56 CIS PTR LSW */
2268 ushort cisprt_msw; /* 57 CIS PTR MSW */
2269 ushort subsysvid; /* 58 SubSystem Vendor ID */
2270 ushort subsysid; /* 59 SubSystem ID */
2271 ushort reserved60; /* 60 reserved */
2272 ushort reserved61; /* 61 reserved */
2273 ushort reserved62; /* 62 reserved */
2274 ushort reserved63; /* 63 reserved */
2275 } ADVEEP_38C0800_CONFIG;
2277 typedef struct adveep_38C1600_config {
2278 /* Word Offset, Description */
2280 ushort cfg_lsw; /* 00 power up initialization */
2281 /* bit 11 set - Func. 0 INTB, Func. 1 INTA */
2282 /* clear - Func. 0 INTA, Func. 1 INTB */
2283 /* bit 13 set - Load CIS */
2284 /* bit 14 set - BIOS Enable */
2285 /* bit 15 set - Big Endian Mode */
2286 ushort cfg_msw; /* 01 unused */
2287 ushort disc_enable; /* 02 disconnect enable */
2288 ushort wdtr_able; /* 03 Wide DTR able */
2289 ushort sdtr_speed1; /* 04 SDTR Speed TID 0-3 */
2290 ushort start_motor; /* 05 send start up motor */
2291 ushort tagqng_able; /* 06 tag queuing able */
2292 ushort bios_scan; /* 07 BIOS device control */
2293 ushort scam_tolerant; /* 08 no scam */
2295 uchar adapter_scsi_id; /* 09 Host Adapter ID */
2296 uchar bios_boot_delay; /* power up wait */
2298 uchar scsi_reset_delay; /* 10 reset delay */
2299 uchar bios_id_lun; /* first boot device scsi id & lun */
2300 /* high nibble is lun */
2301 /* low nibble is scsi id */
2303 uchar termination_se; /* 11 0 - automatic */
2304 /* 1 - low off / high off */
2305 /* 2 - low off / high on */
2306 /* 3 - low on / high on */
2307 /* There is no low on / high off */
2309 uchar termination_lvd; /* 11 0 - automatic */
2310 /* 1 - low off / high off */
2311 /* 2 - low off / high on */
2312 /* 3 - low on / high on */
2313 /* There is no low on / high off */
2315 ushort bios_ctrl; /* 12 BIOS control bits */
2316 /* bit 0 BIOS don't act as initiator. */
2317 /* bit 1 BIOS > 1 GB support */
2318 /* bit 2 BIOS > 2 Disk Support */
2319 /* bit 3 BIOS don't support removables */
2320 /* bit 4 BIOS support bootable CD */
2321 /* bit 5 BIOS scan enabled */
2322 /* bit 6 BIOS support multiple LUNs */
2323 /* bit 7 BIOS display of message */
2324 /* bit 8 SCAM disabled */
2325 /* bit 9 Reset SCSI bus during init. */
2326 /* bit 10 Basic Integrity Checking disabled */
2327 /* bit 11 No verbose initialization. */
2328 /* bit 12 SCSI parity enabled */
2329 /* bit 13 AIPP (Asyn. Info. Ph. Prot.) dis. */
2332 ushort sdtr_speed2; /* 13 SDTR speed TID 4-7 */
2333 ushort sdtr_speed3; /* 14 SDTR speed TID 8-11 */
2334 uchar max_host_qng; /* 15 maximum host queueing */
2335 uchar max_dvc_qng; /* maximum per device queuing */
2336 ushort dvc_cntl; /* 16 control bit for driver */
2337 ushort sdtr_speed4; /* 17 SDTR speed 4 TID 12-15 */
2338 ushort serial_number_word1; /* 18 Board serial number word 1 */
2339 ushort serial_number_word2; /* 19 Board serial number word 2 */
2340 ushort serial_number_word3; /* 20 Board serial number word 3 */
2341 ushort check_sum; /* 21 EEP check sum */
2342 uchar oem_name[16]; /* 22 OEM name */
2343 ushort dvc_err_code; /* 30 last device driver error code */
2344 ushort adv_err_code; /* 31 last uc and Adv Lib error code */
2345 ushort adv_err_addr; /* 32 last uc error address */
2346 ushort saved_dvc_err_code; /* 33 saved last dev. driver error code */
2347 ushort saved_adv_err_code; /* 34 saved last uc and Adv Lib error code */
2348 ushort saved_adv_err_addr; /* 35 saved last uc error address */
2349 ushort reserved36; /* 36 reserved */
2350 ushort reserved37; /* 37 reserved */
2351 ushort reserved38; /* 38 reserved */
2352 ushort reserved39; /* 39 reserved */
2353 ushort reserved40; /* 40 reserved */
2354 ushort reserved41; /* 41 reserved */
2355 ushort reserved42; /* 42 reserved */
2356 ushort reserved43; /* 43 reserved */
2357 ushort reserved44; /* 44 reserved */
2358 ushort reserved45; /* 45 reserved */
2359 ushort reserved46; /* 46 reserved */
2360 ushort reserved47; /* 47 reserved */
2361 ushort reserved48; /* 48 reserved */
2362 ushort reserved49; /* 49 reserved */
2363 ushort reserved50; /* 50 reserved */
2364 ushort reserved51; /* 51 reserved */
2365 ushort reserved52; /* 52 reserved */
2366 ushort reserved53; /* 53 reserved */
2367 ushort reserved54; /* 54 reserved */
2368 ushort reserved55; /* 55 reserved */
2369 ushort cisptr_lsw; /* 56 CIS PTR LSW */
2370 ushort cisprt_msw; /* 57 CIS PTR MSW */
2371 ushort subsysvid; /* 58 SubSystem Vendor ID */
2372 ushort subsysid; /* 59 SubSystem ID */
2373 ushort reserved60; /* 60 reserved */
2374 ushort reserved61; /* 61 reserved */
2375 ushort reserved62; /* 62 reserved */
2376 ushort reserved63; /* 63 reserved */
2377 } ADVEEP_38C1600_CONFIG;
2382 #define ASC_EEP_CMD_DONE 0x0200
2383 #define ASC_EEP_CMD_DONE_ERR 0x0001
2386 #define EEP_CFG_WORD_BIG_ENDIAN 0x8000
2389 #define BIOS_CTRL_BIOS 0x0001
2390 #define BIOS_CTRL_EXTENDED_XLAT 0x0002
2391 #define BIOS_CTRL_GT_2_DISK 0x0004
2392 #define BIOS_CTRL_BIOS_REMOVABLE 0x0008
2393 #define BIOS_CTRL_BOOTABLE_CD 0x0010
2394 #define BIOS_CTRL_MULTIPLE_LUN 0x0040
2395 #define BIOS_CTRL_DISPLAY_MSG 0x0080
2396 #define BIOS_CTRL_NO_SCAM 0x0100
2397 #define BIOS_CTRL_RESET_SCSI_BUS 0x0200
2398 #define BIOS_CTRL_INIT_VERBOSE 0x0800
2399 #define BIOS_CTRL_SCSI_PARITY 0x1000
2400 #define BIOS_CTRL_AIPP_DIS 0x2000
2402 #define ADV_3550_MEMSIZE 0x2000 /* 8 KB Internal Memory */
2403 #define ADV_3550_IOLEN 0x40 /* I/O Port Range in bytes */
2405 #define ADV_38C0800_MEMSIZE 0x4000 /* 16 KB Internal Memory */
2406 #define ADV_38C0800_IOLEN 0x100 /* I/O Port Range in bytes */
2409 * XXX - Since ASC38C1600 Rev.3 has a local RAM failure issue, there is
2410 * a special 16K Adv Library and Microcode version. After the issue is
2411 * resolved, should restore 32K support.
2413 * #define ADV_38C1600_MEMSIZE 0x8000L * 32 KB Internal Memory *
2415 #define ADV_38C1600_MEMSIZE 0x4000 /* 16 KB Internal Memory */
2416 #define ADV_38C1600_IOLEN 0x100 /* I/O Port Range 256 bytes */
2417 #define ADV_38C1600_MEMLEN 0x1000 /* Memory Range 4KB bytes */
2420 * Byte I/O register address from base of 'iop_base'.
2422 #define IOPB_INTR_STATUS_REG 0x00
2423 #define IOPB_CHIP_ID_1 0x01
2424 #define IOPB_INTR_ENABLES 0x02
2425 #define IOPB_CHIP_TYPE_REV 0x03
2426 #define IOPB_RES_ADDR_4 0x04
2427 #define IOPB_RES_ADDR_5 0x05
2428 #define IOPB_RAM_DATA 0x06
2429 #define IOPB_RES_ADDR_7 0x07
2430 #define IOPB_FLAG_REG 0x08
2431 #define IOPB_RES_ADDR_9 0x09
2432 #define IOPB_RISC_CSR 0x0A
2433 #define IOPB_RES_ADDR_B 0x0B
2434 #define IOPB_RES_ADDR_C 0x0C
2435 #define IOPB_RES_ADDR_D 0x0D
2436 #define IOPB_SOFT_OVER_WR 0x0E
2437 #define IOPB_RES_ADDR_F 0x0F
2438 #define IOPB_MEM_CFG 0x10
2439 #define IOPB_RES_ADDR_11 0x11
2440 #define IOPB_GPIO_DATA 0x12
2441 #define IOPB_RES_ADDR_13 0x13
2442 #define IOPB_FLASH_PAGE 0x14
2443 #define IOPB_RES_ADDR_15 0x15
2444 #define IOPB_GPIO_CNTL 0x16
2445 #define IOPB_RES_ADDR_17 0x17
2446 #define IOPB_FLASH_DATA 0x18
2447 #define IOPB_RES_ADDR_19 0x19
2448 #define IOPB_RES_ADDR_1A 0x1A
2449 #define IOPB_RES_ADDR_1B 0x1B
2450 #define IOPB_RES_ADDR_1C 0x1C
2451 #define IOPB_RES_ADDR_1D 0x1D
2452 #define IOPB_RES_ADDR_1E 0x1E
2453 #define IOPB_RES_ADDR_1F 0x1F
2454 #define IOPB_DMA_CFG0 0x20
2455 #define IOPB_DMA_CFG1 0x21
2456 #define IOPB_TICKLE 0x22
2457 #define IOPB_DMA_REG_WR 0x23
2458 #define IOPB_SDMA_STATUS 0x24
2459 #define IOPB_SCSI_BYTE_CNT 0x25
2460 #define IOPB_HOST_BYTE_CNT 0x26
2461 #define IOPB_BYTE_LEFT_TO_XFER 0x27
2462 #define IOPB_BYTE_TO_XFER_0 0x28
2463 #define IOPB_BYTE_TO_XFER_1 0x29
2464 #define IOPB_BYTE_TO_XFER_2 0x2A
2465 #define IOPB_BYTE_TO_XFER_3 0x2B
2466 #define IOPB_ACC_GRP 0x2C
2467 #define IOPB_RES_ADDR_2D 0x2D
2468 #define IOPB_DEV_ID 0x2E
2469 #define IOPB_RES_ADDR_2F 0x2F
2470 #define IOPB_SCSI_DATA 0x30
2471 #define IOPB_RES_ADDR_31 0x31
2472 #define IOPB_RES_ADDR_32 0x32
2473 #define IOPB_SCSI_DATA_HSHK 0x33
2474 #define IOPB_SCSI_CTRL 0x34
2475 #define IOPB_RES_ADDR_35 0x35
2476 #define IOPB_RES_ADDR_36 0x36
2477 #define IOPB_RES_ADDR_37 0x37
2478 #define IOPB_RAM_BIST 0x38
2479 #define IOPB_PLL_TEST 0x39
2480 #define IOPB_PCI_INT_CFG 0x3A
2481 #define IOPB_RES_ADDR_3B 0x3B
2482 #define IOPB_RFIFO_CNT 0x3C
2483 #define IOPB_RES_ADDR_3D 0x3D
2484 #define IOPB_RES_ADDR_3E 0x3E
2485 #define IOPB_RES_ADDR_3F 0x3F
2488 * Word I/O register address from base of 'iop_base'.
2490 #define IOPW_CHIP_ID_0 0x00 /* CID0 */
2491 #define IOPW_CTRL_REG 0x02 /* CC */
2492 #define IOPW_RAM_ADDR 0x04 /* LA */
2493 #define IOPW_RAM_DATA 0x06 /* LD */
2494 #define IOPW_RES_ADDR_08 0x08
2495 #define IOPW_RISC_CSR 0x0A /* CSR */
2496 #define IOPW_SCSI_CFG0 0x0C /* CFG0 */
2497 #define IOPW_SCSI_CFG1 0x0E /* CFG1 */
2498 #define IOPW_RES_ADDR_10 0x10
2499 #define IOPW_SEL_MASK 0x12 /* SM */
2500 #define IOPW_RES_ADDR_14 0x14
2501 #define IOPW_FLASH_ADDR 0x16 /* FA */
2502 #define IOPW_RES_ADDR_18 0x18
2503 #define IOPW_EE_CMD 0x1A /* EC */
2504 #define IOPW_EE_DATA 0x1C /* ED */
2505 #define IOPW_SFIFO_CNT 0x1E /* SFC */
2506 #define IOPW_RES_ADDR_20 0x20
2507 #define IOPW_Q_BASE 0x22 /* QB */
2508 #define IOPW_QP 0x24 /* QP */
2509 #define IOPW_IX 0x26 /* IX */
2510 #define IOPW_SP 0x28 /* SP */
2511 #define IOPW_PC 0x2A /* PC */
2512 #define IOPW_RES_ADDR_2C 0x2C
2513 #define IOPW_RES_ADDR_2E 0x2E
2514 #define IOPW_SCSI_DATA 0x30 /* SD */
2515 #define IOPW_SCSI_DATA_HSHK 0x32 /* SDH */
2516 #define IOPW_SCSI_CTRL 0x34 /* SC */
2517 #define IOPW_HSHK_CFG 0x36 /* HCFG */
2518 #define IOPW_SXFR_STATUS 0x36 /* SXS */
2519 #define IOPW_SXFR_CNTL 0x38 /* SXL */
2520 #define IOPW_SXFR_CNTH 0x3A /* SXH */
2521 #define IOPW_RES_ADDR_3C 0x3C
2522 #define IOPW_RFIFO_DATA 0x3E /* RFD */
2525 * Doubleword I/O register address from base of 'iop_base'.
2527 #define IOPDW_RES_ADDR_0 0x00
2528 #define IOPDW_RAM_DATA 0x04
2529 #define IOPDW_RES_ADDR_8 0x08
2530 #define IOPDW_RES_ADDR_C 0x0C
2531 #define IOPDW_RES_ADDR_10 0x10
2532 #define IOPDW_COMMA 0x14
2533 #define IOPDW_COMMB 0x18
2534 #define IOPDW_RES_ADDR_1C 0x1C
2535 #define IOPDW_SDMA_ADDR0 0x20
2536 #define IOPDW_SDMA_ADDR1 0x24
2537 #define IOPDW_SDMA_COUNT 0x28
2538 #define IOPDW_SDMA_ERROR 0x2C
2539 #define IOPDW_RDMA_ADDR0 0x30
2540 #define IOPDW_RDMA_ADDR1 0x34
2541 #define IOPDW_RDMA_COUNT 0x38
2542 #define IOPDW_RDMA_ERROR 0x3C
2544 #define ADV_CHIP_ID_BYTE 0x25
2545 #define ADV_CHIP_ID_WORD 0x04C1
2547 #define ADV_SC_SCSI_BUS_RESET 0x2000
2549 #define ADV_INTR_ENABLE_HOST_INTR 0x01
2550 #define ADV_INTR_ENABLE_SEL_INTR 0x02
2551 #define ADV_INTR_ENABLE_DPR_INTR 0x04
2552 #define ADV_INTR_ENABLE_RTA_INTR 0x08
2553 #define ADV_INTR_ENABLE_RMA_INTR 0x10
2554 #define ADV_INTR_ENABLE_RST_INTR 0x20
2555 #define ADV_INTR_ENABLE_DPE_INTR 0x40
2556 #define ADV_INTR_ENABLE_GLOBAL_INTR 0x80
2558 #define ADV_INTR_STATUS_INTRA 0x01
2559 #define ADV_INTR_STATUS_INTRB 0x02
2560 #define ADV_INTR_STATUS_INTRC 0x04
2562 #define ADV_RISC_CSR_STOP (0x0000)
2563 #define ADV_RISC_TEST_COND (0x2000)
2564 #define ADV_RISC_CSR_RUN (0x4000)
2565 #define ADV_RISC_CSR_SINGLE_STEP (0x8000)
2567 #define ADV_CTRL_REG_HOST_INTR 0x0100
2568 #define ADV_CTRL_REG_SEL_INTR 0x0200
2569 #define ADV_CTRL_REG_DPR_INTR 0x0400
2570 #define ADV_CTRL_REG_RTA_INTR 0x0800
2571 #define ADV_CTRL_REG_RMA_INTR 0x1000
2572 #define ADV_CTRL_REG_RES_BIT14 0x2000
2573 #define ADV_CTRL_REG_DPE_INTR 0x4000
2574 #define ADV_CTRL_REG_POWER_DONE 0x8000
2575 #define ADV_CTRL_REG_ANY_INTR 0xFF00
2577 #define ADV_CTRL_REG_CMD_RESET 0x00C6
2578 #define ADV_CTRL_REG_CMD_WR_IO_REG 0x00C5
2579 #define ADV_CTRL_REG_CMD_RD_IO_REG 0x00C4
2580 #define ADV_CTRL_REG_CMD_WR_PCI_CFG_SPACE 0x00C3
2581 #define ADV_CTRL_REG_CMD_RD_PCI_CFG_SPACE 0x00C2
2583 #define ADV_TICKLE_NOP 0x00
2584 #define ADV_TICKLE_A 0x01
2585 #define ADV_TICKLE_B 0x02
2586 #define ADV_TICKLE_C 0x03
2588 #define ADV_SCSI_CTRL_RSTOUT 0x2000
2590 #define AdvIsIntPending(port) \
2591 (AdvReadWordRegister(port, IOPW_CTRL_REG) & ADV_CTRL_REG_HOST_INTR)
2594 * SCSI_CFG0 Register bit definitions
2596 #define TIMER_MODEAB 0xC000 /* Watchdog, Second, and Select. Timer Ctrl. */
2597 #define PARITY_EN 0x2000 /* Enable SCSI Parity Error detection */
2598 #define EVEN_PARITY 0x1000 /* Select Even Parity */
2599 #define WD_LONG 0x0800 /* Watchdog Interval, 1: 57 min, 0: 13 sec */
2600 #define QUEUE_128 0x0400 /* Queue Size, 1: 128 byte, 0: 64 byte */
2601 #define PRIM_MODE 0x0100 /* Primitive SCSI mode */
2602 #define SCAM_EN 0x0080 /* Enable SCAM selection */
2603 #define SEL_TMO_LONG 0x0040 /* Sel/Resel Timeout, 1: 400 ms, 0: 1.6 ms */
2604 #define CFRM_ID 0x0020 /* SCAM id sel. confirm., 1: fast, 0: 6.4 ms */
2605 #define OUR_ID_EN 0x0010 /* Enable OUR_ID bits */
2606 #define OUR_ID 0x000F /* SCSI ID */
2609 * SCSI_CFG1 Register bit definitions
2611 #define BIG_ENDIAN 0x8000 /* Enable Big Endian Mode MIO:15, EEP:15 */
2612 #define TERM_POL 0x2000 /* Terminator Polarity Ctrl. MIO:13, EEP:13 */
2613 #define SLEW_RATE 0x1000 /* SCSI output buffer slew rate */
2614 #define FILTER_SEL 0x0C00 /* Filter Period Selection */
2615 #define FLTR_DISABLE 0x0000 /* Input Filtering Disabled */
2616 #define FLTR_11_TO_20NS 0x0800 /* Input Filtering 11ns to 20ns */
2617 #define FLTR_21_TO_39NS 0x0C00 /* Input Filtering 21ns to 39ns */
2618 #define ACTIVE_DBL 0x0200 /* Disable Active Negation */
2619 #define DIFF_MODE 0x0100 /* SCSI differential Mode (Read-Only) */
2620 #define DIFF_SENSE 0x0080 /* 1: No SE cables, 0: SE cable (Read-Only) */
2621 #define TERM_CTL_SEL 0x0040 /* Enable TERM_CTL_H and TERM_CTL_L */
2622 #define TERM_CTL 0x0030 /* External SCSI Termination Bits */
2623 #define TERM_CTL_H 0x0020 /* Enable External SCSI Upper Termination */
2624 #define TERM_CTL_L 0x0010 /* Enable External SCSI Lower Termination */
2625 #define CABLE_DETECT 0x000F /* External SCSI Cable Connection Status */
2628 * Addendum for ASC-38C0800 Chip
2630 * The ASC-38C1600 Chip uses the same definitions except that the
2631 * bus mode override bits [12:10] have been moved to byte register
2632 * offset 0xE (IOPB_SOFT_OVER_WR) bits [12:10]. The [12:10] bits in
2633 * SCSI_CFG1 are read-only and always available. Bit 14 (DIS_TERM_DRV)
2634 * is not needed. The [12:10] bits in IOPB_SOFT_OVER_WR are write-only.
2635 * Also each ASC-38C1600 function or channel uses only cable bits [5:4]
2636 * and [1:0]. Bits [14], [7:6], [3:2] are unused.
2638 #define DIS_TERM_DRV 0x4000 /* 1: Read c_det[3:0], 0: cannot read */
2639 #define HVD_LVD_SE 0x1C00 /* Device Detect Bits */
2640 #define HVD 0x1000 /* HVD Device Detect */
2641 #define LVD 0x0800 /* LVD Device Detect */
2642 #define SE 0x0400 /* SE Device Detect */
2643 #define TERM_LVD 0x00C0 /* LVD Termination Bits */
2644 #define TERM_LVD_HI 0x0080 /* Enable LVD Upper Termination */
2645 #define TERM_LVD_LO 0x0040 /* Enable LVD Lower Termination */
2646 #define TERM_SE 0x0030 /* SE Termination Bits */
2647 #define TERM_SE_HI 0x0020 /* Enable SE Upper Termination */
2648 #define TERM_SE_LO 0x0010 /* Enable SE Lower Termination */
2649 #define C_DET_LVD 0x000C /* LVD Cable Detect Bits */
2650 #define C_DET3 0x0008 /* Cable Detect for LVD External Wide */
2651 #define C_DET2 0x0004 /* Cable Detect for LVD Internal Wide */
2652 #define C_DET_SE 0x0003 /* SE Cable Detect Bits */
2653 #define C_DET1 0x0002 /* Cable Detect for SE Internal Wide */
2654 #define C_DET0 0x0001 /* Cable Detect for SE Internal Narrow */
2656 #define CABLE_ILLEGAL_A 0x7
2657 /* x 0 0 0 | on on | Illegal (all 3 connectors are used) */
2659 #define CABLE_ILLEGAL_B 0xB
2660 /* 0 x 0 0 | on on | Illegal (all 3 connectors are used) */
2663 * MEM_CFG Register bit definitions
2665 #define BIOS_EN 0x40 /* BIOS Enable MIO:14,EEP:14 */
2666 #define FAST_EE_CLK 0x20 /* Diagnostic Bit */
2667 #define RAM_SZ 0x1C /* Specify size of RAM to RISC */
2668 #define RAM_SZ_2KB 0x00 /* 2 KB */
2669 #define RAM_SZ_4KB 0x04 /* 4 KB */
2670 #define RAM_SZ_8KB 0x08 /* 8 KB */
2671 #define RAM_SZ_16KB 0x0C /* 16 KB */
2672 #define RAM_SZ_32KB 0x10 /* 32 KB */
2673 #define RAM_SZ_64KB 0x14 /* 64 KB */
2676 * DMA_CFG0 Register bit definitions
2678 * This register is only accessible to the host.
2680 #define BC_THRESH_ENB 0x80 /* PCI DMA Start Conditions */
2681 #define FIFO_THRESH 0x70 /* PCI DMA FIFO Threshold */
2682 #define FIFO_THRESH_16B 0x00 /* 16 bytes */
2683 #define FIFO_THRESH_32B 0x20 /* 32 bytes */
2684 #define FIFO_THRESH_48B 0x30 /* 48 bytes */
2685 #define FIFO_THRESH_64B 0x40 /* 64 bytes */
2686 #define FIFO_THRESH_80B 0x50 /* 80 bytes (default) */
2687 #define FIFO_THRESH_96B 0x60 /* 96 bytes */
2688 #define FIFO_THRESH_112B 0x70 /* 112 bytes */
2689 #define START_CTL 0x0C /* DMA start conditions */
2690 #define START_CTL_TH 0x00 /* Wait threshold level (default) */
2691 #define START_CTL_ID 0x04 /* Wait SDMA/SBUS idle */
2692 #define START_CTL_THID 0x08 /* Wait threshold and SDMA/SBUS idle */
2693 #define START_CTL_EMFU 0x0C /* Wait SDMA FIFO empty/full */
2694 #define READ_CMD 0x03 /* Memory Read Method */
2695 #define READ_CMD_MR 0x00 /* Memory Read */
2696 #define READ_CMD_MRL 0x02 /* Memory Read Long */
2697 #define READ_CMD_MRM 0x03 /* Memory Read Multiple (default) */
2700 * ASC-38C0800 RAM BIST Register bit definitions
2702 #define RAM_TEST_MODE 0x80
2703 #define PRE_TEST_MODE 0x40
2704 #define NORMAL_MODE 0x00
2705 #define RAM_TEST_DONE 0x10
2706 #define RAM_TEST_STATUS 0x0F
2707 #define RAM_TEST_HOST_ERROR 0x08
2708 #define RAM_TEST_INTRAM_ERROR 0x04
2709 #define RAM_TEST_RISC_ERROR 0x02
2710 #define RAM_TEST_SCSI_ERROR 0x01
2711 #define RAM_TEST_SUCCESS 0x00
2712 #define PRE_TEST_VALUE 0x05
2713 #define NORMAL_VALUE 0x00
2716 * ASC38C1600 Definitions
2718 * IOPB_PCI_INT_CFG Bit Field Definitions
2721 #define INTAB_LD 0x80 /* Value loaded from EEPROM Bit 11. */
2724 * Bit 1 can be set to change the interrupt for the Function to operate in
2725 * Totem Pole mode. By default Bit 1 is 0 and the interrupt operates in
2726 * Open Drain mode. Both functions of the ASC38C1600 must be set to the same
2727 * mode, otherwise the operating mode is undefined.
2729 #define TOTEMPOLE 0x02
2732 * Bit 0 can be used to change the Int Pin for the Function. The value is
2733 * 0 by default for both Functions with Function 0 using INT A and Function
2734 * B using INT B. For Function 0 if set, INT B is used. For Function 1 if set,
2737 * EEPROM Word 0 Bit 11 for each Function may change the initial Int Pin
2738 * value specified in the PCI Configuration Space.
2745 * Adv Library Status Definitions
2749 #define ADV_NOERROR 1
2750 #define ADV_SUCCESS 1
2752 #define ADV_ERROR (-1)
2755 * ADV_DVC_VAR 'warn_code' values
2757 #define ASC_WARN_BUSRESET_ERROR 0x0001 /* SCSI Bus Reset error */
2758 #define ASC_WARN_EEPROM_CHKSUM 0x0002 /* EEP check sum error */
2759 #define ASC_WARN_EEPROM_TERMINATION 0x0004 /* EEP termination bad field */
2760 #define ASC_WARN_SET_PCI_CONFIG_SPACE 0x0080 /* PCI config space set error */
2761 #define ASC_WARN_ERROR 0xFFFF /* ADV_ERROR return */
2763 #define ADV_MAX_TID 15 /* max. target identifier */
2764 #define ADV_MAX_LUN 7 /* max. logical unit number */
2767 * Error code values are set in ADV_DVC_VAR 'err_code'.
2769 #define ASC_IERR_WRITE_EEPROM 0x0001 /* write EEPROM error */
2770 #define ASC_IERR_MCODE_CHKSUM 0x0002 /* micro code check sum error */
2771 #define ASC_IERR_NO_CARRIER 0x0004 /* No more carrier memory. */
2772 #define ASC_IERR_START_STOP_CHIP 0x0008 /* start/stop chip failed */
2773 #define ASC_IERR_CHIP_VERSION 0x0040 /* wrong chip version */
2774 #define ASC_IERR_SET_SCSI_ID 0x0080 /* set SCSI ID failed */
2775 #define ASC_IERR_HVD_DEVICE 0x0100 /* HVD attached to LVD connector. */
2776 #define ASC_IERR_BAD_SIGNATURE 0x0200 /* signature not found */
2777 #define ASC_IERR_ILLEGAL_CONNECTION 0x0400 /* Illegal cable connection */
2778 #define ASC_IERR_SINGLE_END_DEVICE 0x0800 /* Single-end used w/differential */
2779 #define ASC_IERR_REVERSED_CABLE 0x1000 /* Narrow flat cable reversed */
2780 #define ASC_IERR_BIST_PRE_TEST 0x2000 /* BIST pre-test error */
2781 #define ASC_IERR_BIST_RAM_TEST 0x4000 /* BIST RAM test error */
2782 #define ASC_IERR_BAD_CHIPTYPE 0x8000 /* Invalid 'chip_type' setting. */
2785 * Fixed locations of microcode operating variables.
2787 #define ASC_MC_CODE_BEGIN_ADDR 0x0028 /* microcode start address */
2788 #define ASC_MC_CODE_END_ADDR 0x002A /* microcode end address */
2789 #define ASC_MC_CODE_CHK_SUM 0x002C /* microcode code checksum */
2790 #define ASC_MC_VERSION_DATE 0x0038 /* microcode version */
2791 #define ASC_MC_VERSION_NUM 0x003A /* microcode number */
2792 #define ASC_MC_BIOSMEM 0x0040 /* BIOS RISC Memory Start */
2793 #define ASC_MC_BIOSLEN 0x0050 /* BIOS RISC Memory Length */
2794 #define ASC_MC_BIOS_SIGNATURE 0x0058 /* BIOS Signature 0x55AA */
2795 #define ASC_MC_BIOS_VERSION 0x005A /* BIOS Version (2 bytes) */
2796 #define ASC_MC_SDTR_SPEED1 0x0090 /* SDTR Speed for TID 0-3 */
2797 #define ASC_MC_SDTR_SPEED2 0x0092 /* SDTR Speed for TID 4-7 */
2798 #define ASC_MC_SDTR_SPEED3 0x0094 /* SDTR Speed for TID 8-11 */
2799 #define ASC_MC_SDTR_SPEED4 0x0096 /* SDTR Speed for TID 12-15 */
2800 #define ASC_MC_CHIP_TYPE 0x009A
2801 #define ASC_MC_INTRB_CODE 0x009B
2802 #define ASC_MC_WDTR_ABLE 0x009C
2803 #define ASC_MC_SDTR_ABLE 0x009E
2804 #define ASC_MC_TAGQNG_ABLE 0x00A0
2805 #define ASC_MC_DISC_ENABLE 0x00A2
2806 #define ASC_MC_IDLE_CMD_STATUS 0x00A4
2807 #define ASC_MC_IDLE_CMD 0x00A6
2808 #define ASC_MC_IDLE_CMD_PARAMETER 0x00A8
2809 #define ASC_MC_DEFAULT_SCSI_CFG0 0x00AC
2810 #define ASC_MC_DEFAULT_SCSI_CFG1 0x00AE
2811 #define ASC_MC_DEFAULT_MEM_CFG 0x00B0
2812 #define ASC_MC_DEFAULT_SEL_MASK 0x00B2
2813 #define ASC_MC_SDTR_DONE 0x00B6
2814 #define ASC_MC_NUMBER_OF_QUEUED_CMD 0x00C0
2815 #define ASC_MC_NUMBER_OF_MAX_CMD 0x00D0
2816 #define ASC_MC_DEVICE_HSHK_CFG_TABLE 0x0100
2817 #define ASC_MC_CONTROL_FLAG 0x0122 /* Microcode control flag. */
2818 #define ASC_MC_WDTR_DONE 0x0124
2819 #define ASC_MC_CAM_MODE_MASK 0x015E /* CAM mode TID bitmask. */
2820 #define ASC_MC_ICQ 0x0160
2821 #define ASC_MC_IRQ 0x0164
2822 #define ASC_MC_PPR_ABLE 0x017A
2825 * BIOS LRAM variable absolute offsets.
2827 #define BIOS_CODESEG 0x54
2828 #define BIOS_CODELEN 0x56
2829 #define BIOS_SIGNATURE 0x58
2830 #define BIOS_VERSION 0x5A
2833 * Microcode Control Flags
2835 * Flags set by the Adv Library in RISC variable 'control_flag' (0x122)
2836 * and handled by the microcode.
2838 #define CONTROL_FLAG_IGNORE_PERR 0x0001 /* Ignore DMA Parity Errors */
2839 #define CONTROL_FLAG_ENABLE_AIPP 0x0002 /* Enabled AIPP checking. */
2842 * ASC_MC_DEVICE_HSHK_CFG_TABLE microcode table or HSHK_CFG register format
2844 #define HSHK_CFG_WIDE_XFR 0x8000
2845 #define HSHK_CFG_RATE 0x0F00
2846 #define HSHK_CFG_OFFSET 0x001F
2848 #define ASC_DEF_MAX_HOST_QNG 0xFD /* Max. number of host commands (253) */
2849 #define ASC_DEF_MIN_HOST_QNG 0x10 /* Min. number of host commands (16) */
2850 #define ASC_DEF_MAX_DVC_QNG 0x3F /* Max. number commands per device (63) */
2851 #define ASC_DEF_MIN_DVC_QNG 0x04 /* Min. number commands per device (4) */
2853 #define ASC_QC_DATA_CHECK 0x01 /* Require ASC_QC_DATA_OUT set or clear. */
2854 #define ASC_QC_DATA_OUT 0x02 /* Data out DMA transfer. */
2855 #define ASC_QC_START_MOTOR 0x04 /* Send auto-start motor before request. */
2856 #define ASC_QC_NO_OVERRUN 0x08 /* Don't report overrun. */
2857 #define ASC_QC_FREEZE_TIDQ 0x10 /* Freeze TID queue after request. XXX TBD */
2859 #define ASC_QSC_NO_DISC 0x01 /* Don't allow disconnect for request. */
2860 #define ASC_QSC_NO_TAGMSG 0x02 /* Don't allow tag queuing for request. */
2861 #define ASC_QSC_NO_SYNC 0x04 /* Don't use Synch. transfer on request. */
2862 #define ASC_QSC_NO_WIDE 0x08 /* Don't use Wide transfer on request. */
2863 #define ASC_QSC_REDO_DTR 0x10 /* Renegotiate WDTR/SDTR before request. */
2865 * Note: If a Tag Message is to be sent and neither ASC_QSC_HEAD_TAG or
2866 * ASC_QSC_ORDERED_TAG is set, then a Simple Tag Message (0x20) is used.
2868 #define ASC_QSC_HEAD_TAG 0x40 /* Use Head Tag Message (0x21). */
2869 #define ASC_QSC_ORDERED_TAG 0x80 /* Use Ordered Tag Message (0x22). */
2872 * All fields here are accessed by the board microcode and need to be
2875 typedef struct adv_carr_t {
2876 ADV_VADDR carr_va; /* Carrier Virtual Address */
2877 ADV_PADDR carr_pa; /* Carrier Physical Address */
2878 ADV_VADDR areq_vpa; /* ASC_SCSI_REQ_Q Virtual or Physical Address */
2880 * next_vpa [31:4] Carrier Virtual or Physical Next Pointer
2882 * next_vpa [3:1] Reserved Bits
2883 * next_vpa [0] Done Flag set in Response Queue.
2889 * Mask used to eliminate low 4 bits of carrier 'next_vpa' field.
2891 #define ASC_NEXT_VPA_MASK 0xFFFFFFF0
2893 #define ASC_RQ_DONE 0x00000001
2894 #define ASC_RQ_GOOD 0x00000002
2895 #define ASC_CQ_STOPPER 0x00000000
2897 #define ASC_GET_CARRP(carrp) ((carrp) & ASC_NEXT_VPA_MASK)
2899 #define ADV_CARRIER_NUM_PAGE_CROSSING \
2900 (((ADV_CARRIER_COUNT * sizeof(ADV_CARR_T)) + \
2901 (ADV_PAGE_SIZE - 1))/ADV_PAGE_SIZE)
2903 #define ADV_CARRIER_BUFSIZE \
2904 ((ADV_CARRIER_COUNT + ADV_CARRIER_NUM_PAGE_CROSSING) * sizeof(ADV_CARR_T))
2907 * ASC_SCSI_REQ_Q 'a_flag' definitions
2909 * The Adv Library should limit use to the lower nibble (4 bits) of
2910 * a_flag. Drivers are free to use the upper nibble (4 bits) of a_flag.
2912 #define ADV_POLL_REQUEST 0x01 /* poll for request completion */
2913 #define ADV_SCSIQ_DONE 0x02 /* request done */
2914 #define ADV_DONT_RETRY 0x08 /* don't do retry */
2916 #define ADV_CHIP_ASC3550 0x01 /* Ultra-Wide IC */
2917 #define ADV_CHIP_ASC38C0800 0x02 /* Ultra2-Wide/LVD IC */
2918 #define ADV_CHIP_ASC38C1600 0x03 /* Ultra3-Wide/LVD2 IC */
2921 * Adapter temporary configuration structure
2923 * This structure can be discarded after initialization. Don't add
2924 * fields here needed after initialization.
2926 * Field naming convention:
2928 * *_enable indicates the field enables or disables a feature. The
2929 * value of the field is never reset.
2931 typedef struct adv_dvc_cfg {
2932 ushort disc_enable; /* enable disconnection */
2933 uchar chip_version; /* chip version */
2934 uchar termination; /* Term. Ctrl. bits 6-5 of SCSI_CFG1 register */
2935 ushort lib_version; /* Adv Library version number */
2936 ushort control_flag; /* Microcode Control Flag */
2937 ushort mcode_date; /* Microcode date */
2938 ushort mcode_version; /* Microcode version */
2939 ushort pci_slot_info; /* high byte device/function number */
2940 /* bits 7-3 device num., bits 2-0 function num. */
2941 /* low byte bus num. */
2942 ushort serial1; /* EEPROM serial number word 1 */
2943 ushort serial2; /* EEPROM serial number word 2 */
2944 ushort serial3; /* EEPROM serial number word 3 */
2945 struct device *dev; /* pointer to the pci dev structure for this board */
2949 struct adv_scsi_req_q;
2951 typedef void (*ADV_ISR_CALLBACK)
2952 (struct adv_dvc_var *, struct adv_scsi_req_q *);
2954 typedef void (*ADV_ASYNC_CALLBACK)
2955 (struct adv_dvc_var *, uchar);
2958 * Adapter operation variable structure.
2960 * One structure is required per host adapter.
2962 * Field naming convention:
2964 * *_able indicates both whether a feature should be enabled or disabled
2965 * and whether a device isi capable of the feature. At initialization
2966 * this field may be set, but later if a device is found to be incapable
2967 * of the feature, the field is cleared.
2969 typedef struct adv_dvc_var {
2970 AdvPortAddr iop_base; /* I/O port address */
2971 ushort err_code; /* fatal error code */
2972 ushort bios_ctrl; /* BIOS control word, EEPROM word 12 */
2973 ADV_ISR_CALLBACK isr_callback;
2974 ADV_ASYNC_CALLBACK async_callback;
2975 ushort wdtr_able; /* try WDTR for a device */
2976 ushort sdtr_able; /* try SDTR for a device */
2977 ushort ultra_able; /* try SDTR Ultra speed for a device */
2978 ushort sdtr_speed1; /* EEPROM SDTR Speed for TID 0-3 */
2979 ushort sdtr_speed2; /* EEPROM SDTR Speed for TID 4-7 */
2980 ushort sdtr_speed3; /* EEPROM SDTR Speed for TID 8-11 */
2981 ushort sdtr_speed4; /* EEPROM SDTR Speed for TID 12-15 */
2982 ushort tagqng_able; /* try tagged queuing with a device */
2983 ushort ppr_able; /* PPR message capable per TID bitmask. */
2984 uchar max_dvc_qng; /* maximum number of tagged commands per device */
2985 ushort start_motor; /* start motor command allowed */
2986 uchar scsi_reset_wait; /* delay in seconds after scsi bus reset */
2987 uchar chip_no; /* should be assigned by caller */
2988 uchar max_host_qng; /* maximum number of Q'ed command allowed */
2989 uchar irq_no; /* IRQ number */
2990 ushort no_scam; /* scam_tolerant of EEPROM */
2991 struct asc_board *drv_ptr; /* driver pointer to private structure */
2992 uchar chip_scsi_id; /* chip SCSI target ID */
2994 uchar bist_err_code;
2995 ADV_CARR_T *carrier_buf;
2996 ADV_CARR_T *carr_freelist; /* Carrier free list. */
2997 ADV_CARR_T *icq_sp; /* Initiator command queue stopper pointer. */
2998 ADV_CARR_T *irq_sp; /* Initiator response queue stopper pointer. */
2999 ushort carr_pending_cnt; /* Count of pending carriers. */
3001 * Note: The following fields will not be used after initialization. The
3002 * driver may discard the buffer after initialization is done.
3004 ADV_DVC_CFG *cfg; /* temporary configuration structure */
3007 #define NO_OF_SG_PER_BLOCK 15
3009 typedef struct asc_sg_block {
3013 uchar sg_cnt; /* Valid entries in block. */
3014 ADV_PADDR sg_ptr; /* Pointer to next sg block. */
3016 ADV_PADDR sg_addr; /* SG element address. */
3017 ADV_DCNT sg_count; /* SG element count. */
3018 } sg_list[NO_OF_SG_PER_BLOCK];
3022 * ADV_SCSI_REQ_Q - microcode request structure
3024 * All fields in this structure up to byte 60 are used by the microcode.
3025 * The microcode makes assumptions about the size and ordering of fields
3026 * in this structure. Do not change the structure definition here without
3027 * coordinating the change with the microcode.
3029 * All fields accessed by microcode must be maintained in little_endian
3032 typedef struct adv_scsi_req_q {
3033 uchar cntl; /* Ucode flags and state (ASC_MC_QC_*). */
3035 uchar target_id; /* Device target identifier. */
3036 uchar target_lun; /* Device target logical unit number. */
3037 ADV_PADDR data_addr; /* Data buffer physical address. */
3038 ADV_DCNT data_cnt; /* Data count. Ucode sets to residual. */
3039 ADV_PADDR sense_addr;
3043 uchar cdb_len; /* SCSI CDB length. Must <= 16 bytes. */
3045 uchar done_status; /* Completion status. */
3046 uchar scsi_status; /* SCSI status byte. */
3047 uchar host_status; /* Ucode host status. */
3048 uchar sg_working_ix;
3049 uchar cdb[12]; /* SCSI CDB bytes 0-11. */
3050 ADV_PADDR sg_real_addr; /* SG list physical address. */
3051 ADV_PADDR scsiq_rptr;
3052 uchar cdb16[4]; /* SCSI CDB bytes 12-15. */
3053 ADV_VADDR scsiq_ptr;
3056 * End of microcode structure - 60 bytes. The rest of the structure
3057 * is used by the Adv Library and ignored by the microcode.
3060 ADV_SG_BLOCK *sg_list_ptr; /* SG list virtual address. */
3061 char *vdata_addr; /* Data buffer virtual address. */
3063 uchar pad[2]; /* Pad out to a word boundary. */
3067 * Microcode idle loop commands
3069 #define IDLE_CMD_COMPLETED 0
3070 #define IDLE_CMD_STOP_CHIP 0x0001
3071 #define IDLE_CMD_STOP_CHIP_SEND_INT 0x0002
3072 #define IDLE_CMD_SEND_INT 0x0004
3073 #define IDLE_CMD_ABORT 0x0008
3074 #define IDLE_CMD_DEVICE_RESET 0x0010
3075 #define IDLE_CMD_SCSI_RESET_START 0x0020 /* Assert SCSI Bus Reset */
3076 #define IDLE_CMD_SCSI_RESET_END 0x0040 /* Deassert SCSI Bus Reset */
3077 #define IDLE_CMD_SCSIREQ 0x0080
3079 #define IDLE_CMD_STATUS_SUCCESS 0x0001
3080 #define IDLE_CMD_STATUS_FAILURE 0x0002
3083 * AdvSendIdleCmd() flag definitions.
3085 #define ADV_NOWAIT 0x01
3088 * Wait loop time out values.
3090 #define SCSI_WAIT_10_SEC 10UL /* 10 seconds */
3091 #define SCSI_WAIT_100_MSEC 100UL /* 100 milliseconds */
3092 #define SCSI_US_PER_MSEC 1000 /* microseconds per millisecond */
3093 #define SCSI_MS_PER_SEC 1000UL /* milliseconds per second */
3094 #define SCSI_MAX_RETRY 10 /* retry count */
3096 #define ADV_ASYNC_RDMA_FAILURE 0x01 /* Fatal RDMA failure. */
3097 #define ADV_ASYNC_SCSI_BUS_RESET_DET 0x02 /* Detected SCSI Bus Reset. */
3098 #define ADV_ASYNC_CARRIER_READY_FAILURE 0x03 /* Carrier Ready failure. */
3099 #define ADV_RDMA_IN_CARR_AND_Q_INVALID 0x04 /* RDMAed-in data invalid. */
3101 #define ADV_HOST_SCSI_BUS_RESET 0x80 /* Host Initiated SCSI Bus Reset. */
3104 * Device drivers must define the following functions.
3106 static inline ulong DvcEnterCritical(void);
3107 static inline void DvcLeaveCritical(ulong);
3108 static void DvcSleepMilliSecond(ADV_DCNT);
3109 static uchar DvcAdvReadPCIConfigByte(ADV_DVC_VAR *, ushort);
3110 static void DvcAdvWritePCIConfigByte(ADV_DVC_VAR *, ushort, uchar);
3111 static ADV_PADDR DvcGetPhyAddr(ADV_DVC_VAR *, ADV_SCSI_REQ_Q *,
3112 uchar *, ASC_SDCNT *, int);
3113 static void DvcDelayMicroSecond(ADV_DVC_VAR *, ushort);
3116 * Adv Library functions available to drivers.
3118 static int AdvExeScsiQueue(ADV_DVC_VAR *, ADV_SCSI_REQ_Q *);
3119 static int AdvISR(ADV_DVC_VAR *);
3120 static int AdvInitGetConfig(ADV_DVC_VAR *);
3121 static int AdvInitAsc3550Driver(ADV_DVC_VAR *);
3122 static int AdvInitAsc38C0800Driver(ADV_DVC_VAR *);
3123 static int AdvInitAsc38C1600Driver(ADV_DVC_VAR *);
3124 static int AdvResetChipAndSB(ADV_DVC_VAR *);
3125 static int AdvResetSB(ADV_DVC_VAR *asc_dvc);
3128 * Internal Adv Library functions.
3130 static int AdvSendIdleCmd(ADV_DVC_VAR *, ushort, ADV_DCNT);
3131 static void AdvInquiryHandling(ADV_DVC_VAR *, ADV_SCSI_REQ_Q *);
3132 static int AdvInitFrom3550EEP(ADV_DVC_VAR *);
3133 static int AdvInitFrom38C0800EEP(ADV_DVC_VAR *);
3134 static int AdvInitFrom38C1600EEP(ADV_DVC_VAR *);
3135 static ushort AdvGet3550EEPConfig(AdvPortAddr, ADVEEP_3550_CONFIG *);
3136 static void AdvSet3550EEPConfig(AdvPortAddr, ADVEEP_3550_CONFIG *);
3137 static ushort AdvGet38C0800EEPConfig(AdvPortAddr, ADVEEP_38C0800_CONFIG *);
3138 static void AdvSet38C0800EEPConfig(AdvPortAddr, ADVEEP_38C0800_CONFIG *);
3139 static ushort AdvGet38C1600EEPConfig(AdvPortAddr, ADVEEP_38C1600_CONFIG *);
3140 static void AdvSet38C1600EEPConfig(AdvPortAddr, ADVEEP_38C1600_CONFIG *);
3141 static void AdvWaitEEPCmd(AdvPortAddr);
3142 static ushort AdvReadEEPWord(AdvPortAddr, int);
3145 * PCI Bus Definitions
3147 #define AscPCICmdRegBits_BusMastering 0x0007
3148 #define AscPCICmdRegBits_ParErrRespCtrl 0x0040
3150 /* Read byte from a register. */
3151 #define AdvReadByteRegister(iop_base, reg_off) \
3152 (ADV_MEM_READB((iop_base) + (reg_off)))
3154 /* Write byte to a register. */
3155 #define AdvWriteByteRegister(iop_base, reg_off, byte) \
3156 (ADV_MEM_WRITEB((iop_base) + (reg_off), (byte)))
3158 /* Read word (2 bytes) from a register. */
3159 #define AdvReadWordRegister(iop_base, reg_off) \
3160 (ADV_MEM_READW((iop_base) + (reg_off)))
3162 /* Write word (2 bytes) to a register. */
3163 #define AdvWriteWordRegister(iop_base, reg_off, word) \
3164 (ADV_MEM_WRITEW((iop_base) + (reg_off), (word)))
3166 /* Write dword (4 bytes) to a register. */
3167 #define AdvWriteDWordRegister(iop_base, reg_off, dword) \
3168 (ADV_MEM_WRITEDW((iop_base) + (reg_off), (dword)))
3170 /* Read byte from LRAM. */
3171 #define AdvReadByteLram(iop_base, addr, byte) \
3173 ADV_MEM_WRITEW((iop_base) + IOPW_RAM_ADDR, (addr)); \
3174 (byte) = ADV_MEM_READB((iop_base) + IOPB_RAM_DATA); \
3177 /* Write byte to LRAM. */
3178 #define AdvWriteByteLram(iop_base, addr, byte) \
3179 (ADV_MEM_WRITEW((iop_base) + IOPW_RAM_ADDR, (addr)), \
3180 ADV_MEM_WRITEB((iop_base) + IOPB_RAM_DATA, (byte)))
3182 /* Read word (2 bytes) from LRAM. */
3183 #define AdvReadWordLram(iop_base, addr, word) \
3185 ADV_MEM_WRITEW((iop_base) + IOPW_RAM_ADDR, (addr)); \
3186 (word) = (ADV_MEM_READW((iop_base) + IOPW_RAM_DATA)); \
3189 /* Write word (2 bytes) to LRAM. */
3190 #define AdvWriteWordLram(iop_base, addr, word) \
3191 (ADV_MEM_WRITEW((iop_base) + IOPW_RAM_ADDR, (addr)), \
3192 ADV_MEM_WRITEW((iop_base) + IOPW_RAM_DATA, (word)))
3194 /* Write little-endian double word (4 bytes) to LRAM */
3195 /* Because of unspecified C language ordering don't use auto-increment. */
3196 #define AdvWriteDWordLramNoSwap(iop_base, addr, dword) \
3197 ((ADV_MEM_WRITEW((iop_base) + IOPW_RAM_ADDR, (addr)), \
3198 ADV_MEM_WRITEW((iop_base) + IOPW_RAM_DATA, \
3199 cpu_to_le16((ushort) ((dword) & 0xFFFF)))), \
3200 (ADV_MEM_WRITEW((iop_base) + IOPW_RAM_ADDR, (addr) + 2), \
3201 ADV_MEM_WRITEW((iop_base) + IOPW_RAM_DATA, \
3202 cpu_to_le16((ushort) ((dword >> 16) & 0xFFFF)))))
3204 /* Read word (2 bytes) from LRAM assuming that the address is already set. */
3205 #define AdvReadWordAutoIncLram(iop_base) \
3206 (ADV_MEM_READW((iop_base) + IOPW_RAM_DATA))
3208 /* Write word (2 bytes) to LRAM assuming that the address is already set. */
3209 #define AdvWriteWordAutoIncLram(iop_base, word) \
3210 (ADV_MEM_WRITEW((iop_base) + IOPW_RAM_DATA, (word)))
3213 * Define macro to check for Condor signature.
3215 * Evaluate to ADV_TRUE if a Condor chip is found the specified port
3216 * address 'iop_base'. Otherwise evalue to ADV_FALSE.
3218 #define AdvFindSignature(iop_base) \
3219 (((AdvReadByteRegister((iop_base), IOPB_CHIP_ID_1) == \
3220 ADV_CHIP_ID_BYTE) && \
3221 (AdvReadWordRegister((iop_base), IOPW_CHIP_ID_0) == \
3222 ADV_CHIP_ID_WORD)) ? ADV_TRUE : ADV_FALSE)
3225 * Define macro to Return the version number of the chip at 'iop_base'.
3227 * The second parameter 'bus_type' is currently unused.
3229 #define AdvGetChipVersion(iop_base, bus_type) \
3230 AdvReadByteRegister((iop_base), IOPB_CHIP_TYPE_REV)
3233 * Abort an SRB in the chip's RISC Memory. The 'srb_ptr' argument must
3234 * match the ASC_SCSI_REQ_Q 'srb_ptr' field.
3236 * If the request has not yet been sent to the device it will simply be
3237 * aborted from RISC memory. If the request is disconnected it will be
3238 * aborted on reselection by sending an Abort Message to the target ID.
3241 * ADV_TRUE(1) - Queue was successfully aborted.
3242 * ADV_FALSE(0) - Queue was not found on the active queue list.
3244 #define AdvAbortQueue(asc_dvc, scsiq) \
3245 AdvSendIdleCmd((asc_dvc), (ushort) IDLE_CMD_ABORT, \
3249 * Send a Bus Device Reset Message to the specified target ID.
3251 * All outstanding commands will be purged if sending the
3252 * Bus Device Reset Message is successful.
3255 * ADV_TRUE(1) - All requests on the target are purged.
3256 * ADV_FALSE(0) - Couldn't issue Bus Device Reset Message; Requests
3259 #define AdvResetDevice(asc_dvc, target_id) \
3260 AdvSendIdleCmd((asc_dvc), (ushort) IDLE_CMD_DEVICE_RESET, \
3261 (ADV_DCNT) (target_id))
3264 * SCSI Wide Type definition.
3266 #define ADV_SCSI_BIT_ID_TYPE ushort
3269 * AdvInitScsiTarget() 'cntl_flag' options.
3271 #define ADV_SCAN_LUN 0x01
3272 #define ADV_CAPINFO_NOLUN 0x02
3275 * Convert target id to target id bit mask.
3277 #define ADV_TID_TO_TIDMASK(tid) (0x01 << ((tid) & ADV_MAX_TID))
3280 * ASC_SCSI_REQ_Q 'done_status' and 'host_status' return values.
3283 #define QD_NO_STATUS 0x00 /* Request not completed yet. */
3284 #define QD_NO_ERROR 0x01
3285 #define QD_ABORTED_BY_HOST 0x02
3286 #define QD_WITH_ERROR 0x04
3288 #define QHSTA_NO_ERROR 0x00
3289 #define QHSTA_M_SEL_TIMEOUT 0x11
3290 #define QHSTA_M_DATA_OVER_RUN 0x12
3291 #define QHSTA_M_UNEXPECTED_BUS_FREE 0x13
3292 #define QHSTA_M_QUEUE_ABORTED 0x15
3293 #define QHSTA_M_SXFR_SDMA_ERR 0x16 /* SXFR_STATUS SCSI DMA Error */
3294 #define QHSTA_M_SXFR_SXFR_PERR 0x17 /* SXFR_STATUS SCSI Bus Parity Error */
3295 #define QHSTA_M_RDMA_PERR 0x18 /* RISC PCI DMA parity error */
3296 #define QHSTA_M_SXFR_OFF_UFLW 0x19 /* SXFR_STATUS Offset Underflow */
3297 #define QHSTA_M_SXFR_OFF_OFLW 0x20 /* SXFR_STATUS Offset Overflow */
3298 #define QHSTA_M_SXFR_WD_TMO 0x21 /* SXFR_STATUS Watchdog Timeout */
3299 #define QHSTA_M_SXFR_DESELECTED 0x22 /* SXFR_STATUS Deselected */
3300 /* Note: QHSTA_M_SXFR_XFR_OFLW is identical to QHSTA_M_DATA_OVER_RUN. */
3301 #define QHSTA_M_SXFR_XFR_OFLW 0x12 /* SXFR_STATUS Transfer Overflow */
3302 #define QHSTA_M_SXFR_XFR_PH_ERR 0x24 /* SXFR_STATUS Transfer Phase Error */
3303 #define QHSTA_M_SXFR_UNKNOWN_ERROR 0x25 /* SXFR_STATUS Unknown Error */
3304 #define QHSTA_M_SCSI_BUS_RESET 0x30 /* Request aborted from SBR */
3305 #define QHSTA_M_SCSI_BUS_RESET_UNSOL 0x31 /* Request aborted from unsol. SBR */
3306 #define QHSTA_M_BUS_DEVICE_RESET 0x32 /* Request aborted from BDR */
3307 #define QHSTA_M_DIRECTION_ERR 0x35 /* Data Phase mismatch */
3308 #define QHSTA_M_DIRECTION_ERR_HUNG 0x36 /* Data Phase mismatch and bus hang */
3309 #define QHSTA_M_WTM_TIMEOUT 0x41
3310 #define QHSTA_M_BAD_CMPL_STATUS_IN 0x42
3311 #define QHSTA_M_NO_AUTO_REQ_SENSE 0x43
3312 #define QHSTA_M_AUTO_REQ_SENSE_FAIL 0x44
3313 #define QHSTA_M_INVALID_DEVICE 0x45 /* Bad target ID */
3314 #define QHSTA_M_FROZEN_TIDQ 0x46 /* TID Queue frozen. */
3315 #define QHSTA_M_SGBACKUP_ERROR 0x47 /* Scatter-Gather backup error */
3318 * Default EEPROM Configuration structure defined in a_init.c.
3320 static ADVEEP_3550_CONFIG Default_3550_EEPROM_Config;
3321 static ADVEEP_38C0800_CONFIG Default_38C0800_EEPROM_Config;
3322 static ADVEEP_38C1600_CONFIG Default_38C1600_EEPROM_Config;
3325 * DvcGetPhyAddr() flag arguments
3327 #define ADV_IS_SCSIQ_FLAG 0x01 /* 'addr' is ASC_SCSI_REQ_Q pointer */
3328 #define ADV_ASCGETSGLIST_VADDR 0x02 /* 'addr' is AscGetSGList() virtual addr */
3329 #define ADV_IS_SENSE_FLAG 0x04 /* 'addr' is sense virtual pointer */
3330 #define ADV_IS_DATA_FLAG 0x08 /* 'addr' is data virtual pointer */
3331 #define ADV_IS_SGLIST_FLAG 0x10 /* 'addr' is sglist virtual pointer */
3332 #define ADV_IS_CARRIER_FLAG 0x20 /* 'addr' is ADV_CARR_T pointer */
3334 /* Return the address that is aligned at the next doubleword >= to 'addr'. */
3335 #define ADV_8BALIGN(addr) (((ulong) (addr) + 0x7) & ~0x7)
3336 #define ADV_16BALIGN(addr) (((ulong) (addr) + 0xF) & ~0xF)
3337 #define ADV_32BALIGN(addr) (((ulong) (addr) + 0x1F) & ~0x1F)
3340 * Total contiguous memory needed for driver SG blocks.
3342 * ADV_MAX_SG_LIST must be defined by a driver. It is the maximum
3343 * number of scatter-gather elements the driver supports in a
3347 #define ADV_SG_LIST_MAX_BYTE_SIZE \
3348 (sizeof(ADV_SG_BLOCK) * \
3349 ((ADV_MAX_SG_LIST + (NO_OF_SG_PER_BLOCK - 1))/NO_OF_SG_PER_BLOCK))
3352 * Inquiry data structure and bitfield macros
3354 * Using bitfields to access the subchar data isn't portable across
3355 * endianness, so instead mask and shift. Only quantities of more
3356 * than 1 bit are shifted, since the others are just tested for true
3360 #define ADV_INQ_DVC_TYPE(inq) ((inq)->periph & 0x1f)
3361 #define ADV_INQ_QUALIFIER(inq) (((inq)->periph & 0xe0) >> 5)
3362 #define ADV_INQ_DVC_TYPE_MOD(inq) ((inq)->devtype & 0x7f)
3363 #define ADV_INQ_REMOVABLE(inq) ((inq)->devtype & 0x80)
3364 #define ADV_INQ_ANSI_VER(inq) ((inq)->ver & 0x07)
3365 #define ADV_INQ_ECMA_VER(inq) (((inq)->ver & 0x38) >> 3)
3366 #define ADV_INQ_ISO_VER(inq) (((inq)->ver & 0xc0) >> 6)
3367 #define ADV_INQ_RESPONSE_FMT(inq) ((inq)->byte3 & 0x0f)
3368 #define ADV_INQ_TERM_IO(inq) ((inq)->byte3 & 0x40)
3369 #define ADV_INQ_ASYNC_NOTIF(inq) ((inq)->byte3 & 0x80)
3370 #define ADV_INQ_SOFT_RESET(inq) ((inq)->flags & 0x01)
3371 #define ADV_INQ_CMD_QUEUE(inq) ((inq)->flags & 0x02)
3372 #define ADV_INQ_LINK_CMD(inq) ((inq)->flags & 0x08)
3373 #define ADV_INQ_SYNC(inq) ((inq)->flags & 0x10)
3374 #define ADV_INQ_WIDE16(inq) ((inq)->flags & 0x20)
3375 #define ADV_INQ_WIDE32(inq) ((inq)->flags & 0x40)
3376 #define ADV_INQ_REL_ADDR(inq) ((inq)->flags & 0x80)
3377 #define ADV_INQ_INFO_UNIT(inq) ((inq)->info & 0x01)
3378 #define ADV_INQ_QUICK_ARB(inq) ((inq)->info & 0x02)
3379 #define ADV_INQ_CLOCKING(inq) (((inq)->info & 0x0c) >> 2)
3382 uchar periph; /* peripheral device type [0:4] */
3383 /* peripheral qualifier [5:7] */
3384 uchar devtype; /* device type modifier (for SCSI I) [0:6] */
3385 /* RMB - removable medium bit [7] */
3386 uchar ver; /* ANSI approved version [0:2] */
3387 /* ECMA version [3:5] */
3388 /* ISO version [6:7] */
3389 uchar byte3; /* response data format [0:3] */
3394 /* reserved [4:5] */
3395 /* terminate I/O process bit (see 5.6.22) [6] */
3396 /* asynch. event notification (processor) [7] */
3397 uchar add_len; /* additional length */
3398 uchar res1; /* reserved */
3399 uchar res2; /* reserved */
3400 uchar flags; /* soft reset implemented [0] */
3401 /* command queuing [1] */
3403 /* linked command for this logical unit [3] */
3404 /* synchronous data transfer [4] */
3405 /* wide bus 16 bit data transfer [5] */
3406 /* wide bus 32 bit data transfer [6] */
3407 /* relative addressing mode [7] */
3408 uchar vendor_id[8]; /* vendor identification */
3409 uchar product_id[16]; /* product identification */
3410 uchar product_rev_level[4]; /* product revision level */
3411 uchar vendor_specific[20]; /* vendor specific */
3412 uchar info; /* information unit supported [0] */
3413 /* quick arbitrate supported [1] */
3414 /* clocking field [2:3] */
3415 /* reserved [4:7] */
3416 uchar res3; /* reserved */
3417 } ADV_SCSI_INQUIRY; /* 58 bytes */
3420 * --- Driver Constants and Macros
3423 #define ASC_NUM_BOARD_SUPPORTED 16
3424 #define ASC_NUM_IOPORT_PROBE 4
3425 #define ASC_NUM_BUS 4
3427 /* Reference Scsi_Host hostdata */
3428 #define ASC_BOARDP(host) ((asc_board_t *) &((host)->hostdata))
3430 /* asc_board_t flags */
3431 #define ASC_HOST_IN_RESET 0x01
3432 #define ASC_IS_WIDE_BOARD 0x04 /* AdvanSys Wide Board */
3433 #define ASC_SELECT_QUEUE_DEPTHS 0x08
3435 #define ASC_NARROW_BOARD(boardp) (((boardp)->flags & ASC_IS_WIDE_BOARD) == 0)
3436 #define ASC_WIDE_BOARD(boardp) ((boardp)->flags & ASC_IS_WIDE_BOARD)
3438 #define NO_ISA_DMA 0xff /* No ISA DMA Channel Used */
3440 #define ASC_INFO_SIZE 128 /* advansys_info() line size */
3442 #ifdef CONFIG_PROC_FS
3443 /* /proc/scsi/advansys/[0...] related definitions */
3444 #define ASC_PRTBUF_SIZE 2048
3445 #define ASC_PRTLINE_SIZE 160
3447 #define ASC_PRT_NEXT() \
3451 if (leftlen == 0) { \
3456 #endif /* CONFIG_PROC_FS */
3458 /* Asc Library return codes */
3461 #define ASC_NOERROR 1
3463 #define ASC_ERROR (-1)
3465 /* struct scsi_cmnd function return codes */
3466 #define STATUS_BYTE(byte) (byte)
3467 #define MSG_BYTE(byte) ((byte) << 8)
3468 #define HOST_BYTE(byte) ((byte) << 16)
3469 #define DRIVER_BYTE(byte) ((byte) << 24)
3472 * The following definitions and macros are OS independent interfaces to
3473 * the queue functions:
3474 * REQ - SCSI request structure
3475 * REQP - pointer to SCSI request structure
3476 * REQPTID(reqp) - reqp's target id
3477 * REQPNEXT(reqp) - reqp's next pointer
3478 * REQPNEXTP(reqp) - pointer to reqp's next pointer
3479 * REQPTIME(reqp) - reqp's time stamp value
3480 * REQTIMESTAMP() - system time stamp value
3482 typedef struct scsi_cmnd REQ, *REQP;
3483 #define REQPNEXT(reqp) ((REQP) ((reqp)->host_scribble))
3484 #define REQPNEXTP(reqp) ((REQP *) &((reqp)->host_scribble))
3485 #define REQPTID(reqp) ((reqp)->device->id)
3486 #define REQPTIME(reqp) ((reqp)->SCp.this_residual)
3487 #define REQTIMESTAMP() (jiffies)
3489 #define REQTIMESTAT(function, ascq, reqp, tid) \
3492 * If the request time stamp is less than the system time stamp, then \
3493 * maybe the system time stamp wrapped. Set the request time to zero.\
3495 if (REQPTIME(reqp) <= REQTIMESTAMP()) { \
3496 REQPTIME(reqp) = REQTIMESTAMP() - REQPTIME(reqp); \
3498 /* Indicate an error occurred with the assertion. */ \
3499 ASC_ASSERT(REQPTIME(reqp) <= REQTIMESTAMP()); \
3500 REQPTIME(reqp) = 0; \
3502 /* Handle first minimum time case without external initialization. */ \
3503 if (((ascq)->q_tot_cnt[tid] == 1) || \
3504 (REQPTIME(reqp) < (ascq)->q_min_tim[tid])) { \
3505 (ascq)->q_min_tim[tid] = REQPTIME(reqp); \
3506 ASC_DBG3(1, "%s: new q_min_tim[%d] %u\n", \
3507 (function), (tid), (ascq)->q_min_tim[tid]); \
3509 if (REQPTIME(reqp) > (ascq)->q_max_tim[tid]) { \
3510 (ascq)->q_max_tim[tid] = REQPTIME(reqp); \
3511 ASC_DBG3(1, "%s: new q_max_tim[%d] %u\n", \
3512 (function), tid, (ascq)->q_max_tim[tid]); \
3514 (ascq)->q_tot_tim[tid] += REQPTIME(reqp); \
3515 /* Reset the time stamp field. */ \
3516 REQPTIME(reqp) = 0; \
3519 /* asc_enqueue() flags */
3523 /* asc_dequeue_list() argument */
3524 #define ASC_TID_ALL (-1)
3526 /* Return non-zero, if the queue is empty. */
3527 #define ASC_QUEUE_EMPTY(ascq) ((ascq)->q_tidmask == 0)
3529 #define PCI_MAX_SLOT 0x1F
3530 #define PCI_MAX_BUS 0xFF
3531 #define PCI_IOADDRESS_MASK 0xFFFE
3532 #define ASC_PCI_DEVICE_ID_CNT 6 /* PCI Device ID count. */
3534 #ifndef ADVANSYS_STATS
3535 #define ASC_STATS(shost, counter)
3536 #define ASC_STATS_ADD(shost, counter, count)
3537 #else /* ADVANSYS_STATS */
3538 #define ASC_STATS(shost, counter) \
3539 (ASC_BOARDP(shost)->asc_stats.counter++)
3541 #define ASC_STATS_ADD(shost, counter, count) \
3542 (ASC_BOARDP(shost)->asc_stats.counter += (count))
3543 #endif /* ADVANSYS_STATS */
3545 #define ASC_CEILING(val, unit) (((val) + ((unit) - 1))/(unit))
3547 /* If the result wraps when calculating tenths, return 0. */
3548 #define ASC_TENTHS(num, den) \
3549 (((10 * ((num)/(den))) > (((num) * 10)/(den))) ? \
3550 0 : ((((num) * 10)/(den)) - (10 * ((num)/(den)))))
3553 * Display a message to the console.
3555 #define ASC_PRINT(s) \
3557 printk("advansys: "); \
3561 #define ASC_PRINT1(s, a1) \
3563 printk("advansys: "); \
3564 printk((s), (a1)); \
3567 #define ASC_PRINT2(s, a1, a2) \
3569 printk("advansys: "); \
3570 printk((s), (a1), (a2)); \
3573 #define ASC_PRINT3(s, a1, a2, a3) \
3575 printk("advansys: "); \
3576 printk((s), (a1), (a2), (a3)); \
3579 #define ASC_PRINT4(s, a1, a2, a3, a4) \
3581 printk("advansys: "); \
3582 printk((s), (a1), (a2), (a3), (a4)); \
3585 #ifndef ADVANSYS_DEBUG
3587 #define ASC_DBG(lvl, s)
3588 #define ASC_DBG1(lvl, s, a1)
3589 #define ASC_DBG2(lvl, s, a1, a2)
3590 #define ASC_DBG3(lvl, s, a1, a2, a3)
3591 #define ASC_DBG4(lvl, s, a1, a2, a3, a4)
3592 #define ASC_DBG_PRT_SCSI_HOST(lvl, s)
3593 #define ASC_DBG_PRT_SCSI_CMND(lvl, s)
3594 #define ASC_DBG_PRT_ASC_SCSI_Q(lvl, scsiqp)
3595 #define ASC_DBG_PRT_ADV_SCSI_REQ_Q(lvl, scsiqp)
3596 #define ASC_DBG_PRT_ASC_QDONE_INFO(lvl, qdone)
3597 #define ADV_DBG_PRT_ADV_SCSI_REQ_Q(lvl, scsiqp)
3598 #define ASC_DBG_PRT_HEX(lvl, name, start, length)
3599 #define ASC_DBG_PRT_CDB(lvl, cdb, len)
3600 #define ASC_DBG_PRT_SENSE(lvl, sense, len)
3601 #define ASC_DBG_PRT_INQUIRY(lvl, inq, len)
3603 #else /* ADVANSYS_DEBUG */
3606 * Debugging Message Levels:
3608 * 1: High-Level Tracing
3609 * 2-N: Verbose Tracing
3612 #define ASC_DBG(lvl, s) \
3614 if (asc_dbglvl >= (lvl)) { \
3619 #define ASC_DBG1(lvl, s, a1) \
3621 if (asc_dbglvl >= (lvl)) { \
3622 printk((s), (a1)); \
3626 #define ASC_DBG2(lvl, s, a1, a2) \
3628 if (asc_dbglvl >= (lvl)) { \
3629 printk((s), (a1), (a2)); \
3633 #define ASC_DBG3(lvl, s, a1, a2, a3) \
3635 if (asc_dbglvl >= (lvl)) { \
3636 printk((s), (a1), (a2), (a3)); \
3640 #define ASC_DBG4(lvl, s, a1, a2, a3, a4) \
3642 if (asc_dbglvl >= (lvl)) { \
3643 printk((s), (a1), (a2), (a3), (a4)); \
3647 #define ASC_DBG_PRT_SCSI_HOST(lvl, s) \
3649 if (asc_dbglvl >= (lvl)) { \
3650 asc_prt_scsi_host(s); \
3654 #define ASC_DBG_PRT_SCSI_CMND(lvl, s) \
3656 if (asc_dbglvl >= (lvl)) { \
3657 asc_prt_scsi_cmnd(s); \
3661 #define ASC_DBG_PRT_ASC_SCSI_Q(lvl, scsiqp) \
3663 if (asc_dbglvl >= (lvl)) { \
3664 asc_prt_asc_scsi_q(scsiqp); \
3668 #define ASC_DBG_PRT_ASC_QDONE_INFO(lvl, qdone) \
3670 if (asc_dbglvl >= (lvl)) { \
3671 asc_prt_asc_qdone_info(qdone); \
3675 #define ASC_DBG_PRT_ADV_SCSI_REQ_Q(lvl, scsiqp) \
3677 if (asc_dbglvl >= (lvl)) { \
3678 asc_prt_adv_scsi_req_q(scsiqp); \
3682 #define ASC_DBG_PRT_HEX(lvl, name, start, length) \
3684 if (asc_dbglvl >= (lvl)) { \
3685 asc_prt_hex((name), (start), (length)); \
3689 #define ASC_DBG_PRT_CDB(lvl, cdb, len) \
3690 ASC_DBG_PRT_HEX((lvl), "CDB", (uchar *) (cdb), (len));
3692 #define ASC_DBG_PRT_SENSE(lvl, sense, len) \
3693 ASC_DBG_PRT_HEX((lvl), "SENSE", (uchar *) (sense), (len));
3695 #define ASC_DBG_PRT_INQUIRY(lvl, inq, len) \
3696 ASC_DBG_PRT_HEX((lvl), "INQUIRY", (uchar *) (inq), (len));
3697 #endif /* ADVANSYS_DEBUG */
3699 #ifndef ADVANSYS_ASSERT
3700 #define ASC_ASSERT(a)
3701 #else /* ADVANSYS_ASSERT */
3703 #define ASC_ASSERT(a) \
3706 printk("ASC_ASSERT() Failure: file %s, line %d\n", \
3707 __FILE__, __LINE__); \
3711 #endif /* ADVANSYS_ASSERT */
3714 * --- Driver Structures
3717 #ifdef ADVANSYS_STATS
3719 /* Per board statistics structure */
3721 /* Driver Entrypoint Statistics */
3722 ADV_DCNT queuecommand; /* # calls to advansys_queuecommand() */
3723 ADV_DCNT reset; /* # calls to advansys_eh_bus_reset() */
3724 ADV_DCNT biosparam; /* # calls to advansys_biosparam() */
3725 ADV_DCNT interrupt; /* # advansys_interrupt() calls */
3726 ADV_DCNT callback; /* # calls to asc/adv_isr_callback() */
3727 ADV_DCNT done; /* # calls to request's scsi_done function */
3728 ADV_DCNT build_error; /* # asc/adv_build_req() ASC_ERROR returns. */
3729 ADV_DCNT adv_build_noreq; /* # adv_build_req() adv_req_t alloc. fail. */
3730 ADV_DCNT adv_build_nosg; /* # adv_build_req() adv_sgblk_t alloc. fail. */
3731 /* AscExeScsiQueue()/AdvExeScsiQueue() Statistics */
3732 ADV_DCNT exe_noerror; /* # ASC_NOERROR returns. */
3733 ADV_DCNT exe_busy; /* # ASC_BUSY returns. */
3734 ADV_DCNT exe_error; /* # ASC_ERROR returns. */
3735 ADV_DCNT exe_unknown; /* # unknown returns. */
3736 /* Data Transfer Statistics */
3737 ADV_DCNT cont_cnt; /* # non-scatter-gather I/O requests received */
3738 ADV_DCNT cont_xfer; /* # contiguous transfer 512-bytes */
3739 ADV_DCNT sg_cnt; /* # scatter-gather I/O requests received */
3740 ADV_DCNT sg_elem; /* # scatter-gather elements */
3741 ADV_DCNT sg_xfer; /* # scatter-gather transfer 512-bytes */
3743 #endif /* ADVANSYS_STATS */
3746 * Request queuing structure
3748 typedef struct asc_queue {
3749 ADV_SCSI_BIT_ID_TYPE q_tidmask; /* queue mask */
3750 REQP q_first[ADV_MAX_TID + 1]; /* first queued request */
3751 REQP q_last[ADV_MAX_TID + 1]; /* last queued request */
3752 #ifdef ADVANSYS_STATS
3753 short q_cur_cnt[ADV_MAX_TID + 1]; /* current queue count */
3754 short q_max_cnt[ADV_MAX_TID + 1]; /* maximum queue count */
3755 ADV_DCNT q_tot_cnt[ADV_MAX_TID + 1]; /* total enqueue count */
3756 ADV_DCNT q_tot_tim[ADV_MAX_TID + 1]; /* total time queued */
3757 ushort q_max_tim[ADV_MAX_TID + 1]; /* maximum time queued */
3758 ushort q_min_tim[ADV_MAX_TID + 1]; /* minimum time queued */
3759 #endif /* ADVANSYS_STATS */
3763 * Adv Library Request Structures
3765 * The following two structures are used to process Wide Board requests.
3767 * The ADV_SCSI_REQ_Q structure in adv_req_t is passed to the Adv Library
3768 * and microcode with the ADV_SCSI_REQ_Q field 'srb_ptr' pointing to the
3769 * adv_req_t. The adv_req_t structure 'cmndp' field in turn points to the
3770 * Mid-Level SCSI request structure.
3772 * Zero or more ADV_SG_BLOCK are used with each ADV_SCSI_REQ_Q. Each
3773 * ADV_SG_BLOCK structure holds 15 scatter-gather elements. Under Linux
3774 * up to 255 scatter-gather elements may be used per request or
3777 * Both structures must be 32 byte aligned.
3779 typedef struct adv_sgblk {
3780 ADV_SG_BLOCK sg_block; /* Sgblock structure. */
3781 uchar align[32]; /* Sgblock structure padding. */
3782 struct adv_sgblk *next_sgblkp; /* Next scatter-gather structure. */
3785 typedef struct adv_req {
3786 ADV_SCSI_REQ_Q scsi_req_q; /* Adv Library request structure. */
3787 uchar align[32]; /* Request structure padding. */
3788 struct scsi_cmnd *cmndp; /* Mid-Level SCSI command pointer. */
3789 adv_sgblk_t *sgblkp; /* Adv Library scatter-gather pointer. */
3790 struct adv_req *next_reqp; /* Next Request Structure. */
3794 * Structure allocated for each board.
3796 * This structure is allocated by scsi_register() at the end
3797 * of the 'Scsi_Host' structure starting at the 'hostdata'
3798 * field. It is guaranteed to be allocated from DMA-able memory.
3800 typedef struct asc_board {
3801 int id; /* Board Id */
3802 uint flags; /* Board flags */
3804 ASC_DVC_VAR asc_dvc_var; /* Narrow board */
3805 ADV_DVC_VAR adv_dvc_var; /* Wide board */
3808 ASC_DVC_CFG asc_dvc_cfg; /* Narrow board */
3809 ADV_DVC_CFG adv_dvc_cfg; /* Wide board */
3811 ushort asc_n_io_port; /* Number I/O ports. */
3812 asc_queue_t active; /* Active command queue */
3813 asc_queue_t waiting; /* Waiting command queue */
3814 asc_queue_t done; /* Done command queue */
3815 ADV_SCSI_BIT_ID_TYPE init_tidmask; /* Target init./valid mask */
3816 struct scsi_device *device[ADV_MAX_TID + 1]; /* Mid-Level Scsi Device */
3817 ushort reqcnt[ADV_MAX_TID + 1]; /* Starvation request count */
3818 ADV_SCSI_BIT_ID_TYPE queue_full; /* Queue full mask */
3819 ushort queue_full_cnt[ADV_MAX_TID + 1]; /* Queue full count */
3821 ASCEEP_CONFIG asc_eep; /* Narrow EEPROM config. */
3822 ADVEEP_3550_CONFIG adv_3550_eep; /* 3550 EEPROM config. */
3823 ADVEEP_38C0800_CONFIG adv_38C0800_eep; /* 38C0800 EEPROM config. */
3824 ADVEEP_38C1600_CONFIG adv_38C1600_eep; /* 38C1600 EEPROM config. */
3826 ulong last_reset; /* Saved last reset time */
3827 spinlock_t lock; /* Board spinlock */
3828 #ifdef CONFIG_PROC_FS
3829 /* /proc/scsi/advansys/[0...] */
3830 char *prtbuf; /* /proc print buffer */
3831 #endif /* CONFIG_PROC_FS */
3832 #ifdef ADVANSYS_STATS
3833 struct asc_stats asc_stats; /* Board statistics */
3834 #endif /* ADVANSYS_STATS */
3836 * The following fields are used only for Narrow Boards.
3838 /* The following three structures must be in DMA-able memory. */
3839 ASC_SCSI_REQ_Q scsireqq;
3840 ASC_CAP_INFO cap_info;
3841 ASC_SCSI_INQUIRY inquiry;
3842 uchar sdtr_data[ASC_MAX_TID + 1]; /* SDTR information */
3844 * The following fields are used only for Wide Boards.
3846 void __iomem *ioremap_addr; /* I/O Memory remap address. */
3847 ushort ioport; /* I/O Port address. */
3848 ADV_CARR_T *orig_carrp; /* ADV_CARR_T memory block. */
3849 adv_req_t *orig_reqp; /* adv_req_t memory block. */
3850 adv_req_t *adv_reqp; /* Request structures. */
3851 adv_sgblk_t *adv_sgblkp; /* Scatter-gather structures. */
3852 ushort bios_signature; /* BIOS Signature. */
3853 ushort bios_version; /* BIOS Version. */
3854 ushort bios_codeseg; /* BIOS Code Segment. */
3855 ushort bios_codelen; /* BIOS Code Segment Length. */
3859 * PCI configuration structures
3861 typedef struct _PCI_DATA_ {
3869 typedef struct _PCI_DEVICE_ {
3883 typedef struct _PCI_CONFIG_SPACE_ {
3894 ADV_PADDR baseAddress[6];
3896 ADV_PADDR optionRomAddr;
3897 ushort reserved2[4];
3908 /* Note: All driver global data should be initialized. */
3910 /* Number of boards detected in system. */
3911 static int asc_board_count = 0;
3912 static struct Scsi_Host *asc_host[ASC_NUM_BOARD_SUPPORTED] = { NULL };
3914 /* Overrun buffer used by all narrow boards. */
3915 static uchar overrun_buf[ASC_OVERRUN_BSIZE] = { 0 };
3918 * Global structures required to issue a command.
3920 static ASC_SCSI_Q asc_scsi_q = { {0} };
3921 static ASC_SG_HEAD asc_sg_head = { 0 };
3923 /* List of supported bus types. */
3924 static ushort asc_bus[ASC_NUM_BUS] __initdata = {
3931 static int asc_iopflag = ASC_FALSE;
3932 static int asc_ioport[ASC_NUM_IOPORT_PROBE] = { 0, 0, 0, 0 };
3934 #ifdef ADVANSYS_DEBUG
3935 static char *asc_bus_name[ASC_NUM_BUS] = {
3942 static int asc_dbglvl = 3;
3943 #endif /* ADVANSYS_DEBUG */
3945 /* Declaration for Asc Library internal data referenced by driver. */
3946 static PortAddr _asc_def_iop_base[];
3949 * --- Driver Function Prototypes
3951 * advansys.h contains function prototypes for functions global to Linux.
3954 static irqreturn_t advansys_interrupt(int, void *);
3955 static int advansys_slave_configure(struct scsi_device *);
3956 static void asc_scsi_done_list(struct scsi_cmnd *);
3957 static int asc_execute_scsi_cmnd(struct scsi_cmnd *);
3958 static int asc_build_req(asc_board_t *, struct scsi_cmnd *);
3959 static int adv_build_req(asc_board_t *, struct scsi_cmnd *, ADV_SCSI_REQ_Q **);
3960 static int adv_get_sglist(asc_board_t *, adv_req_t *, struct scsi_cmnd *, int);
3961 static void asc_isr_callback(ASC_DVC_VAR *, ASC_QDONE_INFO *);
3962 static void adv_isr_callback(ADV_DVC_VAR *, ADV_SCSI_REQ_Q *);
3963 static void adv_async_callback(ADV_DVC_VAR *, uchar);
3964 static void asc_enqueue(asc_queue_t *, REQP, int);
3965 static REQP asc_dequeue(asc_queue_t *, int);
3966 static REQP asc_dequeue_list(asc_queue_t *, REQP *, int);
3967 static int asc_rmqueue(asc_queue_t *, REQP);
3968 static void asc_execute_queue(asc_queue_t *);
3969 #ifdef CONFIG_PROC_FS
3970 static int asc_proc_copy(off_t, off_t, char *, int, char *, int);
3971 static int asc_prt_board_devices(struct Scsi_Host *, char *, int);
3972 static int asc_prt_adv_bios(struct Scsi_Host *, char *, int);
3973 static int asc_get_eeprom_string(ushort *serialnum, uchar *cp);
3974 static int asc_prt_asc_board_eeprom(struct Scsi_Host *, char *, int);
3975 static int asc_prt_adv_board_eeprom(struct Scsi_Host *, char *, int);
3976 static int asc_prt_driver_conf(struct Scsi_Host *, char *, int);
3977 static int asc_prt_asc_board_info(struct Scsi_Host *, char *, int);
3978 static int asc_prt_adv_board_info(struct Scsi_Host *, char *, int);
3979 static int asc_prt_line(char *, int, char *fmt, ...);
3980 #endif /* CONFIG_PROC_FS */
3982 /* Declaration for Asc Library internal functions referenced by driver. */
3983 static int AscFindSignature(PortAddr);
3984 static ushort AscGetEEPConfig(PortAddr, ASCEEP_CONFIG *, ushort);
3986 /* Statistics function prototypes. */
3987 #ifdef ADVANSYS_STATS
3988 #ifdef CONFIG_PROC_FS
3989 static int asc_prt_board_stats(struct Scsi_Host *, char *, int);
3990 static int asc_prt_target_stats(struct Scsi_Host *, int, char *, int);
3991 #endif /* CONFIG_PROC_FS */
3992 #endif /* ADVANSYS_STATS */
3994 /* Debug function prototypes. */
3995 #ifdef ADVANSYS_DEBUG
3996 static void asc_prt_scsi_host(struct Scsi_Host *);
3997 static void asc_prt_scsi_cmnd(struct scsi_cmnd *);
3998 static void asc_prt_asc_dvc_cfg(ASC_DVC_CFG *);
3999 static void asc_prt_asc_dvc_var(ASC_DVC_VAR *);
4000 static void asc_prt_asc_scsi_q(ASC_SCSI_Q *);
4001 static void asc_prt_asc_qdone_info(ASC_QDONE_INFO *);
4002 static void asc_prt_adv_dvc_cfg(ADV_DVC_CFG *);
4003 static void asc_prt_adv_dvc_var(ADV_DVC_VAR *);
4004 static void asc_prt_adv_scsi_req_q(ADV_SCSI_REQ_Q *);
4005 static void asc_prt_adv_sgblock(int, ADV_SG_BLOCK *);
4006 static void asc_prt_hex(char *f, uchar *, int);
4007 #endif /* ADVANSYS_DEBUG */
4009 #ifdef CONFIG_PROC_FS
4011 * advansys_proc_info() - /proc/scsi/advansys/[0-(ASC_NUM_BOARD_SUPPORTED-1)]
4013 * *buffer: I/O buffer
4014 * **start: if inout == FALSE pointer into buffer where user read should start
4015 * offset: current offset into a /proc/scsi/advansys/[0...] file
4016 * length: length of buffer
4017 * hostno: Scsi_Host host_no
4018 * inout: TRUE - user is writing; FALSE - user is reading
4020 * Return the number of bytes read from or written to a
4021 * /proc/scsi/advansys/[0...] file.
4023 * Note: This function uses the per board buffer 'prtbuf' which is
4024 * allocated when the board is initialized in advansys_detect(). The
4025 * buffer is ASC_PRTBUF_SIZE bytes. The function asc_proc_copy() is
4026 * used to write to the buffer. The way asc_proc_copy() is written
4027 * if 'prtbuf' is too small it will not be overwritten. Instead the
4028 * user just won't get all the available statistics.
4031 advansys_proc_info(struct Scsi_Host *shost, char *buffer, char **start,
4032 off_t offset, int length, int inout)
4034 asc_board_t *boardp;
4042 #ifdef ADVANSYS_STATS
4044 #endif /* ADVANSYS_STATS */
4046 ASC_DBG(1, "advansys_proc_info: begin\n");
4049 * User write not supported.
4051 if (inout == TRUE) {
4056 * User read of /proc/scsi/advansys/[0...] file.
4059 boardp = ASC_BOARDP(shost);
4061 /* Copy read data starting at the beginning of the buffer. */
4069 * Get board configuration information.
4071 * advansys_info() returns the board string from its own static buffer.
4073 cp = (char *)advansys_info(shost);
4076 /* Copy board information. */
4077 cnt = asc_proc_copy(advoffset, offset, curbuf, leftlen, cp, cplen);
4081 ASC_DBG1(1, "advansys_proc_info: totcnt %d\n", totcnt);
4088 * Display Wide Board BIOS Information.
4090 if (ASC_WIDE_BOARD(boardp)) {
4091 cp = boardp->prtbuf;
4092 cplen = asc_prt_adv_bios(shost, cp, ASC_PRTBUF_SIZE);
4093 ASC_ASSERT(cplen < ASC_PRTBUF_SIZE);
4095 asc_proc_copy(advoffset, offset, curbuf, leftlen, cp,
4100 ASC_DBG1(1, "advansys_proc_info: totcnt %d\n", totcnt);
4108 * Display driver information for each device attached to the board.
4110 cp = boardp->prtbuf;
4111 cplen = asc_prt_board_devices(shost, cp, ASC_PRTBUF_SIZE);
4112 ASC_ASSERT(cplen < ASC_PRTBUF_SIZE);
4113 cnt = asc_proc_copy(advoffset, offset, curbuf, leftlen, cp, cplen);
4117 ASC_DBG1(1, "advansys_proc_info: totcnt %d\n", totcnt);
4124 * Display EEPROM configuration for the board.
4126 cp = boardp->prtbuf;
4127 if (ASC_NARROW_BOARD(boardp)) {
4128 cplen = asc_prt_asc_board_eeprom(shost, cp, ASC_PRTBUF_SIZE);
4130 cplen = asc_prt_adv_board_eeprom(shost, cp, ASC_PRTBUF_SIZE);
4132 ASC_ASSERT(cplen < ASC_PRTBUF_SIZE);
4133 cnt = asc_proc_copy(advoffset, offset, curbuf, leftlen, cp, cplen);
4137 ASC_DBG1(1, "advansys_proc_info: totcnt %d\n", totcnt);
4144 * Display driver configuration and information for the board.
4146 cp = boardp->prtbuf;
4147 cplen = asc_prt_driver_conf(shost, cp, ASC_PRTBUF_SIZE);
4148 ASC_ASSERT(cplen < ASC_PRTBUF_SIZE);
4149 cnt = asc_proc_copy(advoffset, offset, curbuf, leftlen, cp, cplen);
4153 ASC_DBG1(1, "advansys_proc_info: totcnt %d\n", totcnt);
4159 #ifdef ADVANSYS_STATS
4161 * Display driver statistics for the board.
4163 cp = boardp->prtbuf;
4164 cplen = asc_prt_board_stats(shost, cp, ASC_PRTBUF_SIZE);
4165 ASC_ASSERT(cplen <= ASC_PRTBUF_SIZE);
4166 cnt = asc_proc_copy(advoffset, offset, curbuf, leftlen, cp, cplen);
4170 ASC_DBG1(1, "advansys_proc_info: totcnt %d\n", totcnt);
4177 * Display driver statistics for each target.
4179 for (tgt_id = 0; tgt_id <= ADV_MAX_TID; tgt_id++) {
4180 cp = boardp->prtbuf;
4181 cplen = asc_prt_target_stats(shost, tgt_id, cp,
4183 ASC_ASSERT(cplen <= ASC_PRTBUF_SIZE);
4185 asc_proc_copy(advoffset, offset, curbuf, leftlen, cp,
4190 ASC_DBG1(1, "advansys_proc_info: totcnt %d\n", totcnt);
4196 #endif /* ADVANSYS_STATS */
4199 * Display Asc Library dynamic configuration information
4202 cp = boardp->prtbuf;
4203 if (ASC_NARROW_BOARD(boardp)) {
4204 cplen = asc_prt_asc_board_info(shost, cp, ASC_PRTBUF_SIZE);
4206 cplen = asc_prt_adv_board_info(shost, cp, ASC_PRTBUF_SIZE);
4208 ASC_ASSERT(cplen < ASC_PRTBUF_SIZE);
4209 cnt = asc_proc_copy(advoffset, offset, curbuf, leftlen, cp, cplen);
4213 ASC_DBG1(1, "advansys_proc_info: totcnt %d\n", totcnt);
4219 ASC_DBG1(1, "advansys_proc_info: totcnt %d\n", totcnt);
4223 #endif /* CONFIG_PROC_FS */
4228 * Return suitable for printing on the console with the argument
4229 * adapter's configuration information.
4231 * Note: The information line should not exceed ASC_INFO_SIZE bytes,
4232 * otherwise the static 'info' array will be overrun.
4234 static const char *advansys_info(struct Scsi_Host *shost)
4236 static char info[ASC_INFO_SIZE];
4237 asc_board_t *boardp;
4238 ASC_DVC_VAR *asc_dvc_varp;
4239 ADV_DVC_VAR *adv_dvc_varp;
4242 char *widename = NULL;
4244 boardp = ASC_BOARDP(shost);
4245 if (ASC_NARROW_BOARD(boardp)) {
4246 asc_dvc_varp = &boardp->dvc_var.asc_dvc_var;
4247 ASC_DBG(1, "advansys_info: begin\n");
4248 if (asc_dvc_varp->bus_type & ASC_IS_ISA) {
4249 if ((asc_dvc_varp->bus_type & ASC_IS_ISAPNP) ==
4251 busname = "ISA PnP";
4255 /* Don't reference 'shost->n_io_port'; It may be truncated. */
4257 "AdvanSys SCSI %s: %s: IO 0x%lX-0x%lX, IRQ 0x%X, DMA 0x%X",
4258 ASC_VERSION, busname,
4259 (ulong)shost->io_port,
4260 (ulong)shost->io_port + boardp->asc_n_io_port -
4261 1, shost->irq, shost->dma_channel);
4263 if (asc_dvc_varp->bus_type & ASC_IS_VL) {
4265 } else if (asc_dvc_varp->bus_type & ASC_IS_EISA) {
4267 } else if (asc_dvc_varp->bus_type & ASC_IS_PCI) {
4268 if ((asc_dvc_varp->bus_type & ASC_IS_PCI_ULTRA)
4269 == ASC_IS_PCI_ULTRA) {
4270 busname = "PCI Ultra";
4277 ("advansys_info: board %d: unknown bus type %d\n",
4278 boardp->id, asc_dvc_varp->bus_type);
4280 /* Don't reference 'shost->n_io_port'; It may be truncated. */
4282 "AdvanSys SCSI %s: %s: IO 0x%lX-0x%lX, IRQ 0x%X",
4283 ASC_VERSION, busname,
4284 (ulong)shost->io_port,
4285 (ulong)shost->io_port + boardp->asc_n_io_port -
4290 * Wide Adapter Information
4292 * Memory-mapped I/O is used instead of I/O space to access
4293 * the adapter, but display the I/O Port range. The Memory
4294 * I/O address is displayed through the driver /proc file.
4296 adv_dvc_varp = &boardp->dvc_var.adv_dvc_var;
4297 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
4298 iolen = ADV_3550_IOLEN;
4299 widename = "Ultra-Wide";
4300 } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
4301 iolen = ADV_38C0800_IOLEN;
4302 widename = "Ultra2-Wide";
4304 iolen = ADV_38C1600_IOLEN;
4305 widename = "Ultra3-Wide";
4308 "AdvanSys SCSI %s: PCI %s: PCIMEM 0x%lX-0x%lX, IRQ 0x%X",
4309 ASC_VERSION, widename, (ulong)adv_dvc_varp->iop_base,
4310 (ulong)adv_dvc_varp->iop_base + iolen - 1, shost->irq);
4312 ASC_ASSERT(strlen(info) < ASC_INFO_SIZE);
4313 ASC_DBG(1, "advansys_info: end\n");
4318 * advansys_queuecommand() - interrupt-driven I/O entrypoint.
4320 * This function always returns 0. Command return status is saved
4321 * in the 'scp' result field.
4324 advansys_queuecommand(struct scsi_cmnd *scp, void (*done) (struct scsi_cmnd *))
4326 struct Scsi_Host *shost;
4327 asc_board_t *boardp;
4329 struct scsi_cmnd *done_scp;
4331 shost = scp->device->host;
4332 boardp = ASC_BOARDP(shost);
4333 ASC_STATS(shost, queuecommand);
4335 /* host_lock taken by mid-level prior to call but need to protect */
4336 /* against own ISR */
4337 spin_lock_irqsave(&boardp->lock, flags);
4340 * Block new commands while handling a reset or abort request.
4342 if (boardp->flags & ASC_HOST_IN_RESET) {
4344 "advansys_queuecommand: scp 0x%lx blocked for reset request\n",
4346 scp->result = HOST_BYTE(DID_RESET);
4349 * Add blocked requests to the board's 'done' queue. The queued
4350 * requests will be completed at the end of the abort or reset
4353 asc_enqueue(&boardp->done, scp, ASC_BACK);
4354 spin_unlock_irqrestore(&boardp->lock, flags);
4359 * Attempt to execute any waiting commands for the board.
4361 if (!ASC_QUEUE_EMPTY(&boardp->waiting)) {
4363 "advansys_queuecommand: before asc_execute_queue() waiting\n");
4364 asc_execute_queue(&boardp->waiting);
4368 * Save the function pointer to Linux mid-level 'done' function
4369 * and attempt to execute the command.
4371 * If ASC_NOERROR is returned the request has been added to the
4372 * board's 'active' queue and will be completed by the interrupt
4375 * If ASC_BUSY is returned add the request to the board's per
4376 * target waiting list. This is the first time the request has
4377 * been tried. Add it to the back of the waiting list. It will be
4380 * If an error occurred, the request will have been placed on the
4381 * board's 'done' queue and must be completed before returning.
4383 scp->scsi_done = done;
4384 switch (asc_execute_scsi_cmnd(scp)) {
4388 asc_enqueue(&boardp->waiting, scp, ASC_BACK);
4392 done_scp = asc_dequeue_list(&boardp->done, NULL, ASC_TID_ALL);
4393 /* Interrupts could be enabled here. */
4394 asc_scsi_done_list(done_scp);
4397 spin_unlock_irqrestore(&boardp->lock, flags);
4405 * Reset the bus associated with the command 'scp'.
4407 * This function runs its own thread. Interrupts must be blocked but
4408 * sleeping is allowed and no locking other than for host structures is
4409 * required. Returns SUCCESS or FAILED.
4411 static int advansys_reset(struct scsi_cmnd *scp)
4413 struct Scsi_Host *shost;
4414 asc_board_t *boardp;
4415 ASC_DVC_VAR *asc_dvc_varp;
4416 ADV_DVC_VAR *adv_dvc_varp;
4418 struct scsi_cmnd *done_scp = NULL, *last_scp = NULL;
4419 struct scsi_cmnd *tscp, *new_last_scp;
4423 ASC_DBG1(1, "advansys_reset: 0x%lx\n", (ulong)scp);
4425 #ifdef ADVANSYS_STATS
4426 if (scp->device->host != NULL) {
4427 ASC_STATS(scp->device->host, reset);
4429 #endif /* ADVANSYS_STATS */
4431 if ((shost = scp->device->host) == NULL) {
4432 scp->result = HOST_BYTE(DID_ERROR);
4436 boardp = ASC_BOARDP(shost);
4438 ASC_PRINT1("advansys_reset: board %d: SCSI bus reset started...\n",
4441 * Check for re-entrancy.
4443 spin_lock_irqsave(&boardp->lock, flags);
4444 if (boardp->flags & ASC_HOST_IN_RESET) {
4445 spin_unlock_irqrestore(&boardp->lock, flags);
4448 boardp->flags |= ASC_HOST_IN_RESET;
4449 spin_unlock_irqrestore(&boardp->lock, flags);
4451 if (ASC_NARROW_BOARD(boardp)) {
4455 asc_dvc_varp = &boardp->dvc_var.asc_dvc_var;
4458 * Reset the chip and SCSI bus.
4460 ASC_DBG(1, "advansys_reset: before AscInitAsc1000Driver()\n");
4461 status = AscInitAsc1000Driver(asc_dvc_varp);
4463 /* Refer to ASC_IERR_* defintions for meaning of 'err_code'. */
4464 if (asc_dvc_varp->err_code) {
4466 ("advansys_reset: board %d: SCSI bus reset error: 0x%x\n",
4467 boardp->id, asc_dvc_varp->err_code);
4469 } else if (status) {
4471 ("advansys_reset: board %d: SCSI bus reset warning: 0x%x\n",
4472 boardp->id, status);
4475 ("advansys_reset: board %d: SCSI bus reset successful.\n",
4479 ASC_DBG(1, "advansys_reset: after AscInitAsc1000Driver()\n");
4480 spin_lock_irqsave(&boardp->lock, flags);
4486 * If the suggest reset bus flags are set, then reset the bus.
4487 * Otherwise only reset the device.
4489 adv_dvc_varp = &boardp->dvc_var.adv_dvc_var;
4492 * Reset the target's SCSI bus.
4494 ASC_DBG(1, "advansys_reset: before AdvResetChipAndSB()\n");
4495 switch (AdvResetChipAndSB(adv_dvc_varp)) {
4498 ("advansys_reset: board %d: SCSI bus reset successful.\n",
4504 ("advansys_reset: board %d: SCSI bus reset error.\n",
4509 spin_lock_irqsave(&boardp->lock, flags);
4510 (void)AdvISR(adv_dvc_varp);
4512 /* Board lock is held. */
4515 * Dequeue all board 'done' requests. A pointer to the last request
4516 * is returned in 'last_scp'.
4518 done_scp = asc_dequeue_list(&boardp->done, &last_scp, ASC_TID_ALL);
4521 * Dequeue all board 'active' requests for all devices and set
4522 * the request status to DID_RESET. A pointer to the last request
4523 * is returned in 'last_scp'.
4525 if (done_scp == NULL) {
4527 asc_dequeue_list(&boardp->active, &last_scp, ASC_TID_ALL);
4528 for (tscp = done_scp; tscp; tscp = REQPNEXT(tscp)) {
4529 tscp->result = HOST_BYTE(DID_RESET);
4532 /* Append to 'done_scp' at the end with 'last_scp'. */
4533 ASC_ASSERT(last_scp != NULL);
4534 last_scp->host_scribble =
4535 (unsigned char *)asc_dequeue_list(&boardp->active,
4538 if (new_last_scp != NULL) {
4539 ASC_ASSERT(REQPNEXT(last_scp) != NULL);
4540 for (tscp = REQPNEXT(last_scp); tscp;
4541 tscp = REQPNEXT(tscp)) {
4542 tscp->result = HOST_BYTE(DID_RESET);
4544 last_scp = new_last_scp;
4549 * Dequeue all 'waiting' requests and set the request status
4552 if (done_scp == NULL) {
4554 asc_dequeue_list(&boardp->waiting, &last_scp, ASC_TID_ALL);
4555 for (tscp = done_scp; tscp; tscp = REQPNEXT(tscp)) {
4556 tscp->result = HOST_BYTE(DID_RESET);
4559 /* Append to 'done_scp' at the end with 'last_scp'. */
4560 ASC_ASSERT(last_scp != NULL);
4561 last_scp->host_scribble =
4562 (unsigned char *)asc_dequeue_list(&boardp->waiting,
4565 if (new_last_scp != NULL) {
4566 ASC_ASSERT(REQPNEXT(last_scp) != NULL);
4567 for (tscp = REQPNEXT(last_scp); tscp;
4568 tscp = REQPNEXT(tscp)) {
4569 tscp->result = HOST_BYTE(DID_RESET);
4571 last_scp = new_last_scp;
4575 /* Save the time of the most recently completed reset. */
4576 boardp->last_reset = jiffies;
4578 /* Clear reset flag. */
4579 boardp->flags &= ~ASC_HOST_IN_RESET;
4580 spin_unlock_irqrestore(&boardp->lock, flags);
4583 * Complete all the 'done_scp' requests.
4585 if (done_scp != NULL) {
4586 asc_scsi_done_list(done_scp);
4589 ASC_DBG1(1, "advansys_reset: ret %d\n", ret);
4595 * advansys_biosparam()
4597 * Translate disk drive geometry if the "BIOS greater than 1 GB"
4598 * support is enabled for a drive.
4600 * ip (information pointer) is an int array with the following definition:
4606 advansys_biosparam(struct scsi_device *sdev, struct block_device *bdev,
4607 sector_t capacity, int ip[])
4609 asc_board_t *boardp;
4611 ASC_DBG(1, "advansys_biosparam: begin\n");
4612 ASC_STATS(sdev->host, biosparam);
4613 boardp = ASC_BOARDP(sdev->host);
4614 if (ASC_NARROW_BOARD(boardp)) {
4615 if ((boardp->dvc_var.asc_dvc_var.dvc_cntl &
4616 ASC_CNTL_BIOS_GT_1GB) && capacity > 0x200000) {
4624 if ((boardp->dvc_var.adv_dvc_var.bios_ctrl &
4625 BIOS_CTRL_EXTENDED_XLAT) && capacity > 0x200000) {
4633 ip[2] = (unsigned long)capacity / (ip[0] * ip[1]);
4634 ASC_DBG(1, "advansys_biosparam: end\n");
4638 static int __init advansys_detect(struct scsi_host_template *tpnt);
4639 static int advansys_release(struct Scsi_Host *shp);
4641 static struct scsi_host_template driver_template = {
4642 .proc_name = "advansys",
4643 #ifdef CONFIG_PROC_FS
4644 .proc_info = advansys_proc_info,
4647 .detect = advansys_detect,
4648 .release = advansys_release,
4649 .info = advansys_info,
4650 .queuecommand = advansys_queuecommand,
4651 .eh_bus_reset_handler = advansys_reset,
4652 .bios_param = advansys_biosparam,
4653 .slave_configure = advansys_slave_configure,
4655 * Because the driver may control an ISA adapter 'unchecked_isa_dma'
4656 * must be set. The flag will be cleared in advansys_detect for non-ISA
4657 * adapters. Refer to the comment in scsi_module.c for more information.
4659 .unchecked_isa_dma = 1,
4661 * All adapters controlled by this driver are capable of large
4662 * scatter-gather lists. According to the mid-level SCSI documentation
4663 * this obviates any performance gain provided by setting
4664 * 'use_clustering'. But empirically while CPU utilization is increased
4665 * by enabling clustering, I/O throughput increases as well.
4667 .use_clustering = ENABLE_CLUSTERING,
4670 #include "scsi_module.c"
4673 * --- Miscellaneous Driver Functions
4677 * First-level interrupt handler.
4679 * 'dev_id' is a pointer to the interrupting adapter's asc_board_t. Because
4680 * all boards are currently checked for interrupts on each interrupt, 'dev_id'
4681 * is not referenced. 'dev_id' could be used to identify an interrupt passed
4682 * to the AdvanSys driver which is for a device sharing an interrupt with
4683 * an AdvanSys adapter.
4685 static irqreturn_t advansys_interrupt(int irq, void *dev_id)
4689 asc_board_t *boardp;
4690 struct scsi_cmnd *done_scp = NULL, *last_scp = NULL;
4691 struct scsi_cmnd *new_last_scp;
4692 struct Scsi_Host *shost;
4694 ASC_DBG(1, "advansys_interrupt: begin\n");
4697 * Check for interrupts on all boards.
4698 * AscISR() will call asc_isr_callback().
4700 for (i = 0; i < asc_board_count; i++) {
4701 shost = asc_host[i];
4702 boardp = ASC_BOARDP(shost);
4703 ASC_DBG2(2, "advansys_interrupt: i %d, boardp 0x%lx\n",
4705 spin_lock_irqsave(&boardp->lock, flags);
4706 if (ASC_NARROW_BOARD(boardp)) {
4710 if (AscIsIntPending(shost->io_port)) {
4711 ASC_STATS(shost, interrupt);
4713 "advansys_interrupt: before AscISR()\n");
4714 AscISR(&boardp->dvc_var.asc_dvc_var);
4720 ASC_DBG(1, "advansys_interrupt: before AdvISR()\n");
4721 if (AdvISR(&boardp->dvc_var.adv_dvc_var)) {
4722 ASC_STATS(shost, interrupt);
4727 * Start waiting requests and create a list of completed requests.
4729 * If a reset request is being performed for the board, the reset
4730 * handler will complete pending requests after it has completed.
4732 if ((boardp->flags & ASC_HOST_IN_RESET) == 0) {
4734 "advansys_interrupt: done_scp 0x%lx, last_scp 0x%lx\n",
4735 (ulong)done_scp, (ulong)last_scp);
4737 /* Start any waiting commands for the board. */
4738 if (!ASC_QUEUE_EMPTY(&boardp->waiting)) {
4740 "advansys_interrupt: before asc_execute_queue()\n");
4741 asc_execute_queue(&boardp->waiting);
4745 * Add to the list of requests that must be completed.
4747 * 'done_scp' will always be NULL on the first iteration
4748 * of this loop. 'last_scp' is set at the same time as
4751 if (done_scp == NULL) {
4753 asc_dequeue_list(&boardp->done, &last_scp,
4756 ASC_ASSERT(last_scp != NULL);
4757 last_scp->host_scribble =
4758 (unsigned char *)asc_dequeue_list(&boardp->
4762 if (new_last_scp != NULL) {
4763 ASC_ASSERT(REQPNEXT(last_scp) != NULL);
4764 last_scp = new_last_scp;
4768 spin_unlock_irqrestore(&boardp->lock, flags);
4772 * If interrupts were enabled on entry, then they
4773 * are now enabled here.
4775 * Complete all requests on the done list.
4778 asc_scsi_done_list(done_scp);
4780 ASC_DBG(1, "advansys_interrupt: end\n");
4785 * Set the number of commands to queue per device for the
4786 * specified host adapter.
4788 static int advansys_slave_configure(struct scsi_device *device)
4790 asc_board_t *boardp;
4792 boardp = ASC_BOARDP(device->host);
4793 boardp->flags |= ASC_SELECT_QUEUE_DEPTHS;
4795 * Save a pointer to the device and set its initial/maximum
4796 * queue depth. Only save the pointer for a lun0 dev though.
4798 if (device->lun == 0)
4799 boardp->device[device->id] = device;
4800 if (device->tagged_supported) {
4801 if (ASC_NARROW_BOARD(boardp)) {
4802 scsi_adjust_queue_depth(device, MSG_ORDERED_TAG,
4803 boardp->dvc_var.asc_dvc_var.
4804 max_dvc_qng[device->id]);
4806 scsi_adjust_queue_depth(device, MSG_ORDERED_TAG,
4807 boardp->dvc_var.adv_dvc_var.
4811 scsi_adjust_queue_depth(device, 0, device->host->cmd_per_lun);
4814 "advansys_slave_configure: device 0x%lx, boardp 0x%lx, id %d, depth %d\n",
4815 (ulong)device, (ulong)boardp, device->id, device->queue_depth);
4820 * Complete all requests on the singly linked list pointed
4823 * Interrupts can be enabled on entry.
4825 static void asc_scsi_done_list(struct scsi_cmnd *scp)
4827 struct scsi_cmnd *tscp;
4829 ASC_DBG(2, "asc_scsi_done_list: begin\n");
4830 while (scp != NULL) {
4831 asc_board_t *boardp;
4834 ASC_DBG1(3, "asc_scsi_done_list: scp 0x%lx\n", (ulong)scp);
4835 tscp = REQPNEXT(scp);
4836 scp->host_scribble = NULL;
4838 boardp = ASC_BOARDP(scp->device->host);
4840 if (ASC_NARROW_BOARD(boardp))
4841 dev = boardp->dvc_cfg.asc_dvc_cfg.dev;
4843 dev = boardp->dvc_cfg.adv_dvc_cfg.dev;
4847 (struct scatterlist *)scp->request_buffer,
4848 scp->use_sg, scp->sc_data_direction);
4849 else if (scp->request_bufflen)
4850 dma_unmap_single(dev, scp->SCp.dma_handle,
4851 scp->request_bufflen,
4852 scp->sc_data_direction);
4854 ASC_STATS(scp->device->host, done);
4855 ASC_ASSERT(scp->scsi_done != NULL);
4857 scp->scsi_done(scp);
4861 ASC_DBG(2, "asc_scsi_done_list: done\n");
4866 * Execute a single 'Scsi_Cmnd'.
4868 * The function 'done' is called when the request has been completed.
4872 * host - board controlling device
4873 * device - device to send command
4874 * target - target of device
4875 * lun - lun of device
4876 * cmd_len - length of SCSI CDB
4877 * cmnd - buffer for SCSI 8, 10, or 12 byte CDB
4878 * use_sg - if non-zero indicates scatter-gather request with use_sg elements
4880 * if (use_sg == 0) {
4881 * request_buffer - buffer address for request
4882 * request_bufflen - length of request buffer
4884 * request_buffer - pointer to scatterlist structure
4887 * sense_buffer - sense command buffer
4889 * result (4 bytes of an int):
4891 * 0 SCSI Status Byte Code
4892 * 1 SCSI One Byte Message Code
4894 * 3 Mid-Level Error Code
4896 * host driver fields:
4897 * SCp - Scsi_Pointer used for command processing status
4898 * scsi_done - used to save caller's done function
4899 * host_scribble - used for pointer to another struct scsi_cmnd
4901 * If this function returns ASC_NOERROR the request has been enqueued
4902 * on the board's 'active' queue and will be completed from the
4903 * interrupt handler.
4905 * If this function returns ASC_NOERROR the request has been enqueued
4906 * on the board's 'done' queue and must be completed by the caller.
4908 * If ASC_BUSY is returned the request will be enqueued by the
4909 * caller on the target's waiting queue and re-tried later.
4911 static int asc_execute_scsi_cmnd(struct scsi_cmnd *scp)
4913 asc_board_t *boardp;
4914 ASC_DVC_VAR *asc_dvc_varp;
4915 ADV_DVC_VAR *adv_dvc_varp;
4916 ADV_SCSI_REQ_Q *adv_scsiqp;
4917 struct scsi_device *device;
4920 ASC_DBG2(1, "asc_execute_scsi_cmnd: scp 0x%lx, done 0x%lx\n",
4921 (ulong)scp, (ulong)scp->scsi_done);
4923 boardp = ASC_BOARDP(scp->device->host);
4924 device = boardp->device[scp->device->id];
4926 if (ASC_NARROW_BOARD(boardp)) {
4928 * Build and execute Narrow Board request.
4931 asc_dvc_varp = &boardp->dvc_var.asc_dvc_var;
4934 * Build Asc Library request structure using the
4935 * global structures 'asc_scsi_req' and 'asc_sg_head'.
4937 * If an error is returned, then the request has been
4938 * queued on the board done queue. It will be completed
4941 * asc_build_req() can not return ASC_BUSY.
4943 if (asc_build_req(boardp, scp) == ASC_ERROR) {
4944 ASC_STATS(scp->device->host, build_error);
4949 * Execute the command. If there is no error, add the command
4950 * to the active queue.
4952 switch (ret = AscExeScsiQueue(asc_dvc_varp, &asc_scsi_q)) {
4954 ASC_STATS(scp->device->host, exe_noerror);
4956 * Increment monotonically increasing per device successful
4957 * request counter. Wrapping doesn't matter.
4959 boardp->reqcnt[scp->device->id]++;
4960 asc_enqueue(&boardp->active, scp, ASC_BACK);
4962 "asc_execute_scsi_cmnd: AscExeScsiQueue(), ASC_NOERROR\n");
4966 * Caller will enqueue request on the target's waiting queue
4969 ASC_STATS(scp->device->host, exe_busy);
4973 ("asc_execute_scsi_cmnd: board %d: AscExeScsiQueue() ASC_ERROR, err_code 0x%x\n",
4974 boardp->id, asc_dvc_varp->err_code);
4975 ASC_STATS(scp->device->host, exe_error);
4976 scp->result = HOST_BYTE(DID_ERROR);
4977 asc_enqueue(&boardp->done, scp, ASC_BACK);
4981 ("asc_execute_scsi_cmnd: board %d: AscExeScsiQueue() unknown, err_code 0x%x\n",
4982 boardp->id, asc_dvc_varp->err_code);
4983 ASC_STATS(scp->device->host, exe_unknown);
4984 scp->result = HOST_BYTE(DID_ERROR);
4985 asc_enqueue(&boardp->done, scp, ASC_BACK);
4990 * Build and execute Wide Board request.
4992 adv_dvc_varp = &boardp->dvc_var.adv_dvc_var;
4995 * Build and get a pointer to an Adv Library request structure.
4997 * If the request is successfully built then send it below,
4998 * otherwise return with an error.
5000 switch (adv_build_req(boardp, scp, &adv_scsiqp)) {
5003 "asc_execute_scsi_cmnd: adv_build_req ASC_NOERROR\n");
5007 "asc_execute_scsi_cmnd: adv_build_req ASC_BUSY\n");
5009 * If busy is returned the request has not been enqueued.
5010 * It will be enqueued by the caller on the target's waiting
5011 * queue and retried later.
5013 * The asc_stats fields 'adv_build_noreq' and 'adv_build_nosg'
5014 * count wide board busy conditions. They are updated in
5015 * adv_build_req and adv_get_sglist, respectively.
5020 * If an error is returned, then the request has been
5021 * queued on the board done queue. It will be completed
5026 "asc_execute_scsi_cmnd: adv_build_req ASC_ERROR\n");
5027 ASC_STATS(scp->device->host, build_error);
5032 * Execute the command. If there is no error, add the command
5033 * to the active queue.
5035 switch (ret = AdvExeScsiQueue(adv_dvc_varp, adv_scsiqp)) {
5037 ASC_STATS(scp->device->host, exe_noerror);
5039 * Increment monotonically increasing per device successful
5040 * request counter. Wrapping doesn't matter.
5042 boardp->reqcnt[scp->device->id]++;
5043 asc_enqueue(&boardp->active, scp, ASC_BACK);
5045 "asc_execute_scsi_cmnd: AdvExeScsiQueue(), ASC_NOERROR\n");
5049 * Caller will enqueue request on the target's waiting queue
5052 ASC_STATS(scp->device->host, exe_busy);
5056 ("asc_execute_scsi_cmnd: board %d: AdvExeScsiQueue() ASC_ERROR, err_code 0x%x\n",
5057 boardp->id, adv_dvc_varp->err_code);
5058 ASC_STATS(scp->device->host, exe_error);
5059 scp->result = HOST_BYTE(DID_ERROR);
5060 asc_enqueue(&boardp->done, scp, ASC_BACK);
5064 ("asc_execute_scsi_cmnd: board %d: AdvExeScsiQueue() unknown, err_code 0x%x\n",
5065 boardp->id, adv_dvc_varp->err_code);
5066 ASC_STATS(scp->device->host, exe_unknown);
5067 scp->result = HOST_BYTE(DID_ERROR);
5068 asc_enqueue(&boardp->done, scp, ASC_BACK);
5073 ASC_DBG(1, "asc_execute_scsi_cmnd: end\n");
5078 * Build a request structure for the Asc Library (Narrow Board).
5080 * The global structures 'asc_scsi_q' and 'asc_sg_head' are
5081 * used to build the request.
5083 * If an error occurs, then queue the request on the board done
5084 * queue and return ASC_ERROR.
5086 static int asc_build_req(asc_board_t *boardp, struct scsi_cmnd *scp)
5088 struct device *dev = boardp->dvc_cfg.asc_dvc_cfg.dev;
5091 * Mutually exclusive access is required to 'asc_scsi_q' and
5092 * 'asc_sg_head' until after the request is started.
5094 memset(&asc_scsi_q, 0, sizeof(ASC_SCSI_Q));
5097 * Point the ASC_SCSI_Q to the 'struct scsi_cmnd'.
5099 asc_scsi_q.q2.srb_ptr = ASC_VADDR_TO_U32(scp);
5102 * Build the ASC_SCSI_Q request.
5104 * For narrow boards a CDB length maximum of 12 bytes
5107 if (scp->cmd_len > ASC_MAX_CDB_LEN) {
5109 ("asc_build_req: board %d: cmd_len %d > ASC_MAX_CDB_LEN %d\n",
5110 boardp->id, scp->cmd_len, ASC_MAX_CDB_LEN);
5111 scp->result = HOST_BYTE(DID_ERROR);
5112 asc_enqueue(&boardp->done, scp, ASC_BACK);
5115 asc_scsi_q.cdbptr = &scp->cmnd[0];
5116 asc_scsi_q.q2.cdb_len = scp->cmd_len;
5117 asc_scsi_q.q1.target_id = ASC_TID_TO_TARGET_ID(scp->device->id);
5118 asc_scsi_q.q1.target_lun = scp->device->lun;
5119 asc_scsi_q.q2.target_ix =
5120 ASC_TIDLUN_TO_IX(scp->device->id, scp->device->lun);
5121 asc_scsi_q.q1.sense_addr =
5122 cpu_to_le32(virt_to_bus(&scp->sense_buffer[0]));
5123 asc_scsi_q.q1.sense_len = sizeof(scp->sense_buffer);
5126 * If there are any outstanding requests for the current target,
5127 * then every 255th request send an ORDERED request. This heuristic
5128 * tries to retain the benefit of request sorting while preventing
5129 * request starvation. 255 is the max number of tags or pending commands
5130 * a device may have outstanding.
5132 * The request count is incremented below for every successfully
5136 if ((boardp->dvc_var.asc_dvc_var.cur_dvc_qng[scp->device->id] > 0) &&
5137 (boardp->reqcnt[scp->device->id] % 255) == 0) {
5138 asc_scsi_q.q2.tag_code = MSG_ORDERED_TAG;
5140 asc_scsi_q.q2.tag_code = MSG_SIMPLE_TAG;
5144 * Build ASC_SCSI_Q for a contiguous buffer or a scatter-gather
5147 if (scp->use_sg == 0) {
5149 * CDB request of single contiguous buffer.
5151 ASC_STATS(scp->device->host, cont_cnt);
5152 scp->SCp.dma_handle = scp->request_bufflen ?
5153 dma_map_single(dev, scp->request_buffer,
5154 scp->request_bufflen,
5155 scp->sc_data_direction) : 0;
5156 asc_scsi_q.q1.data_addr = cpu_to_le32(scp->SCp.dma_handle);
5157 asc_scsi_q.q1.data_cnt = cpu_to_le32(scp->request_bufflen);
5158 ASC_STATS_ADD(scp->device->host, cont_xfer,
5159 ASC_CEILING(scp->request_bufflen, 512));
5160 asc_scsi_q.q1.sg_queue_cnt = 0;
5161 asc_scsi_q.sg_head = NULL;
5164 * CDB scatter-gather request list.
5168 struct scatterlist *slp;
5170 slp = (struct scatterlist *)scp->request_buffer;
5172 dma_map_sg(dev, slp, scp->use_sg, scp->sc_data_direction);
5174 if (use_sg > scp->device->host->sg_tablesize) {
5176 ("asc_build_req: board %d: use_sg %d > sg_tablesize %d\n",
5178 scp->device->host->sg_tablesize);
5179 dma_unmap_sg(dev, slp, scp->use_sg,
5180 scp->sc_data_direction);
5181 scp->result = HOST_BYTE(DID_ERROR);
5182 asc_enqueue(&boardp->done, scp, ASC_BACK);
5186 ASC_STATS(scp->device->host, sg_cnt);
5189 * Use global ASC_SG_HEAD structure and set the ASC_SCSI_Q
5190 * structure to point to it.
5192 memset(&asc_sg_head, 0, sizeof(ASC_SG_HEAD));
5194 asc_scsi_q.q1.cntl |= QC_SG_HEAD;
5195 asc_scsi_q.sg_head = &asc_sg_head;
5196 asc_scsi_q.q1.data_cnt = 0;
5197 asc_scsi_q.q1.data_addr = 0;
5198 /* This is a byte value, otherwise it would need to be swapped. */
5199 asc_sg_head.entry_cnt = asc_scsi_q.q1.sg_queue_cnt = use_sg;
5200 ASC_STATS_ADD(scp->device->host, sg_elem,
5201 asc_sg_head.entry_cnt);
5204 * Convert scatter-gather list into ASC_SG_HEAD list.
5206 for (sgcnt = 0; sgcnt < use_sg; sgcnt++, slp++) {
5207 asc_sg_head.sg_list[sgcnt].addr =
5208 cpu_to_le32(sg_dma_address(slp));
5209 asc_sg_head.sg_list[sgcnt].bytes =
5210 cpu_to_le32(sg_dma_len(slp));
5211 ASC_STATS_ADD(scp->device->host, sg_xfer,
5212 ASC_CEILING(sg_dma_len(slp), 512));
5216 ASC_DBG_PRT_ASC_SCSI_Q(2, &asc_scsi_q);
5217 ASC_DBG_PRT_CDB(1, scp->cmnd, scp->cmd_len);
5223 * Build a request structure for the Adv Library (Wide Board).
5225 * If an adv_req_t can not be allocated to issue the request,
5226 * then return ASC_BUSY. If an error occurs, then return ASC_ERROR.
5228 * Multi-byte fields in the ASC_SCSI_REQ_Q that are used by the
5229 * microcode for DMA addresses or math operations are byte swapped
5230 * to little-endian order.
5233 adv_build_req(asc_board_t *boardp, struct scsi_cmnd *scp,
5234 ADV_SCSI_REQ_Q **adv_scsiqpp)
5237 ADV_SCSI_REQ_Q *scsiqp;
5240 struct device *dev = boardp->dvc_cfg.adv_dvc_cfg.dev;
5243 * Allocate an adv_req_t structure from the board to execute
5246 if (boardp->adv_reqp == NULL) {
5247 ASC_DBG(1, "adv_build_req: no free adv_req_t\n");
5248 ASC_STATS(scp->device->host, adv_build_noreq);
5251 reqp = boardp->adv_reqp;
5252 boardp->adv_reqp = reqp->next_reqp;
5253 reqp->next_reqp = NULL;
5257 * Get 32-byte aligned ADV_SCSI_REQ_Q and ADV_SG_BLOCK pointers.
5259 scsiqp = (ADV_SCSI_REQ_Q *)ADV_32BALIGN(&reqp->scsi_req_q);
5262 * Initialize the structure.
5264 scsiqp->cntl = scsiqp->scsi_cntl = scsiqp->done_status = 0;
5267 * Set the ADV_SCSI_REQ_Q 'srb_ptr' to point to the adv_req_t structure.
5269 scsiqp->srb_ptr = ASC_VADDR_TO_U32(reqp);
5272 * Set the adv_req_t 'cmndp' to point to the struct scsi_cmnd structure.
5277 * Build the ADV_SCSI_REQ_Q request.
5281 * Set CDB length and copy it to the request structure.
5282 * For wide boards a CDB length maximum of 16 bytes
5285 if (scp->cmd_len > ADV_MAX_CDB_LEN) {
5287 ("adv_build_req: board %d: cmd_len %d > ADV_MAX_CDB_LEN %d\n",
5288 boardp->id, scp->cmd_len, ADV_MAX_CDB_LEN);
5289 scp->result = HOST_BYTE(DID_ERROR);
5290 asc_enqueue(&boardp->done, scp, ASC_BACK);
5293 scsiqp->cdb_len = scp->cmd_len;
5294 /* Copy first 12 CDB bytes to cdb[]. */
5295 for (i = 0; i < scp->cmd_len && i < 12; i++) {
5296 scsiqp->cdb[i] = scp->cmnd[i];
5298 /* Copy last 4 CDB bytes, if present, to cdb16[]. */
5299 for (; i < scp->cmd_len; i++) {
5300 scsiqp->cdb16[i - 12] = scp->cmnd[i];
5303 scsiqp->target_id = scp->device->id;
5304 scsiqp->target_lun = scp->device->lun;
5306 scsiqp->sense_addr = cpu_to_le32(virt_to_bus(&scp->sense_buffer[0]));
5307 scsiqp->sense_len = sizeof(scp->sense_buffer);
5310 * Build ADV_SCSI_REQ_Q for a contiguous buffer or a scatter-gather
5314 scsiqp->data_cnt = cpu_to_le32(scp->request_bufflen);
5315 scsiqp->vdata_addr = scp->request_buffer;
5316 scsiqp->data_addr = cpu_to_le32(virt_to_bus(scp->request_buffer));
5318 if (scp->use_sg == 0) {
5320 * CDB request of single contiguous buffer.
5322 reqp->sgblkp = NULL;
5323 scsiqp->data_cnt = cpu_to_le32(scp->request_bufflen);
5324 if (scp->request_bufflen) {
5325 scsiqp->vdata_addr = scp->request_buffer;
5326 scp->SCp.dma_handle =
5327 dma_map_single(dev, scp->request_buffer,
5328 scp->request_bufflen,
5329 scp->sc_data_direction);
5331 scsiqp->vdata_addr = NULL;
5332 scp->SCp.dma_handle = 0;
5334 scsiqp->data_addr = cpu_to_le32(scp->SCp.dma_handle);
5335 scsiqp->sg_list_ptr = NULL;
5336 scsiqp->sg_real_addr = 0;
5337 ASC_STATS(scp->device->host, cont_cnt);
5338 ASC_STATS_ADD(scp->device->host, cont_xfer,
5339 ASC_CEILING(scp->request_bufflen, 512));
5342 * CDB scatter-gather request list.
5344 struct scatterlist *slp;
5347 slp = (struct scatterlist *)scp->request_buffer;
5349 dma_map_sg(dev, slp, scp->use_sg, scp->sc_data_direction);
5351 if (use_sg > ADV_MAX_SG_LIST) {
5353 ("adv_build_req: board %d: use_sg %d > ADV_MAX_SG_LIST %d\n",
5355 scp->device->host->sg_tablesize);
5356 dma_unmap_sg(dev, slp, scp->use_sg,
5357 scp->sc_data_direction);
5358 scp->result = HOST_BYTE(DID_ERROR);
5359 asc_enqueue(&boardp->done, scp, ASC_BACK);
5362 * Free the 'adv_req_t' structure by adding it back to the
5365 reqp->next_reqp = boardp->adv_reqp;
5366 boardp->adv_reqp = reqp;
5372 adv_get_sglist(boardp, reqp, scp,
5373 use_sg)) != ADV_SUCCESS) {
5375 * Free the adv_req_t structure by adding it back to the
5378 reqp->next_reqp = boardp->adv_reqp;
5379 boardp->adv_reqp = reqp;
5384 ASC_STATS(scp->device->host, sg_cnt);
5385 ASC_STATS_ADD(scp->device->host, sg_elem, use_sg);
5388 ASC_DBG_PRT_ADV_SCSI_REQ_Q(2, scsiqp);
5389 ASC_DBG_PRT_CDB(1, scp->cmnd, scp->cmd_len);
5391 *adv_scsiqpp = scsiqp;
5397 * Build scatter-gather list for Adv Library (Wide Board).
5399 * Additional ADV_SG_BLOCK structures will need to be allocated
5400 * if the total number of scatter-gather elements exceeds
5401 * NO_OF_SG_PER_BLOCK (15). The ADV_SG_BLOCK structures are
5402 * assumed to be physically contiguous.
5405 * ADV_SUCCESS(1) - SG List successfully created
5406 * ADV_ERROR(-1) - SG List creation failed
5409 adv_get_sglist(asc_board_t *boardp, adv_req_t *reqp, struct scsi_cmnd *scp,
5412 adv_sgblk_t *sgblkp;
5413 ADV_SCSI_REQ_Q *scsiqp;
5414 struct scatterlist *slp;
5416 ADV_SG_BLOCK *sg_block, *prev_sg_block;
5417 ADV_PADDR sg_block_paddr;
5420 scsiqp = (ADV_SCSI_REQ_Q *)ADV_32BALIGN(&reqp->scsi_req_q);
5421 slp = (struct scatterlist *)scp->request_buffer;
5422 sg_elem_cnt = use_sg;
5423 prev_sg_block = NULL;
5424 reqp->sgblkp = NULL;
5428 * Allocate a 'adv_sgblk_t' structure from the board free
5429 * list. One 'adv_sgblk_t' structure holds NO_OF_SG_PER_BLOCK
5430 * (15) scatter-gather elements.
5432 if ((sgblkp = boardp->adv_sgblkp) == NULL) {
5433 ASC_DBG(1, "adv_get_sglist: no free adv_sgblk_t\n");
5434 ASC_STATS(scp->device->host, adv_build_nosg);
5437 * Allocation failed. Free 'adv_sgblk_t' structures already
5438 * allocated for the request.
5440 while ((sgblkp = reqp->sgblkp) != NULL) {
5441 /* Remove 'sgblkp' from the request list. */
5442 reqp->sgblkp = sgblkp->next_sgblkp;
5444 /* Add 'sgblkp' to the board free list. */
5445 sgblkp->next_sgblkp = boardp->adv_sgblkp;
5446 boardp->adv_sgblkp = sgblkp;
5450 /* Complete 'adv_sgblk_t' board allocation. */
5451 boardp->adv_sgblkp = sgblkp->next_sgblkp;
5452 sgblkp->next_sgblkp = NULL;
5455 * Get 8 byte aligned virtual and physical addresses for
5456 * the allocated ADV_SG_BLOCK structure.
5459 (ADV_SG_BLOCK *)ADV_8BALIGN(&sgblkp->sg_block);
5460 sg_block_paddr = virt_to_bus(sg_block);
5463 * Check if this is the first 'adv_sgblk_t' for the request.
5465 if (reqp->sgblkp == NULL) {
5466 /* Request's first scatter-gather block. */
5467 reqp->sgblkp = sgblkp;
5470 * Set ADV_SCSI_REQ_T ADV_SG_BLOCK virtual and physical
5473 scsiqp->sg_list_ptr = sg_block;
5474 scsiqp->sg_real_addr =
5475 cpu_to_le32(sg_block_paddr);
5477 /* Request's second or later scatter-gather block. */
5478 sgblkp->next_sgblkp = reqp->sgblkp;
5479 reqp->sgblkp = sgblkp;
5482 * Point the previous ADV_SG_BLOCK structure to
5483 * the newly allocated ADV_SG_BLOCK structure.
5485 ASC_ASSERT(prev_sg_block != NULL);
5486 prev_sg_block->sg_ptr =
5487 cpu_to_le32(sg_block_paddr);
5491 for (i = 0; i < NO_OF_SG_PER_BLOCK; i++) {
5492 sg_block->sg_list[i].sg_addr =
5493 cpu_to_le32(sg_dma_address(slp));
5494 sg_block->sg_list[i].sg_count =
5495 cpu_to_le32(sg_dma_len(slp));
5496 ASC_STATS_ADD(scp->device->host, sg_xfer,
5497 ASC_CEILING(sg_dma_len(slp), 512));
5499 if (--sg_elem_cnt == 0) { /* Last ADV_SG_BLOCK and scatter-gather entry. */
5500 sg_block->sg_cnt = i + 1;
5501 sg_block->sg_ptr = 0L; /* Last ADV_SG_BLOCK in list. */
5506 sg_block->sg_cnt = NO_OF_SG_PER_BLOCK;
5507 prev_sg_block = sg_block;
5514 * asc_isr_callback() - Second Level Interrupt Handler called by AscISR().
5516 * Interrupt callback function for the Narrow SCSI Asc Library.
5518 static void asc_isr_callback(ASC_DVC_VAR *asc_dvc_varp, ASC_QDONE_INFO *qdonep)
5520 asc_board_t *boardp;
5521 struct scsi_cmnd *scp;
5522 struct Scsi_Host *shost;
5525 ASC_DBG2(1, "asc_isr_callback: asc_dvc_varp 0x%lx, qdonep 0x%lx\n",
5526 (ulong)asc_dvc_varp, (ulong)qdonep);
5527 ASC_DBG_PRT_ASC_QDONE_INFO(2, qdonep);
5530 * Get the struct scsi_cmnd structure and Scsi_Host structure for the
5531 * command that has been completed.
5533 scp = (struct scsi_cmnd *)ASC_U32_TO_VADDR(qdonep->d2.srb_ptr);
5534 ASC_DBG1(1, "asc_isr_callback: scp 0x%lx\n", (ulong)scp);
5537 ASC_PRINT("asc_isr_callback: scp is NULL\n");
5540 ASC_DBG_PRT_CDB(2, scp->cmnd, scp->cmd_len);
5543 * If the request's host pointer is not valid, display a
5544 * message and return.
5546 shost = scp->device->host;
5547 for (i = 0; i < asc_board_count; i++) {
5548 if (asc_host[i] == shost) {
5552 if (i == asc_board_count) {
5554 ("asc_isr_callback: scp 0x%lx has bad host pointer, host 0x%lx\n",
5555 (ulong)scp, (ulong)shost);
5559 ASC_STATS(shost, callback);
5560 ASC_DBG1(1, "asc_isr_callback: shost 0x%lx\n", (ulong)shost);
5563 * If the request isn't found on the active queue, it may
5564 * have been removed to handle a reset request.
5565 * Display a message and return.
5567 boardp = ASC_BOARDP(shost);
5568 ASC_ASSERT(asc_dvc_varp == &boardp->dvc_var.asc_dvc_var);
5569 if (asc_rmqueue(&boardp->active, scp) == ASC_FALSE) {
5571 ("asc_isr_callback: board %d: scp 0x%lx not on active queue\n",
5572 boardp->id, (ulong)scp);
5577 * 'qdonep' contains the command's ending status.
5579 switch (qdonep->d3.done_stat) {
5581 ASC_DBG(2, "asc_isr_callback: QD_NO_ERROR\n");
5585 * If an INQUIRY command completed successfully, then call
5586 * the AscInquiryHandling() function to set-up the device.
5588 if (scp->cmnd[0] == INQUIRY && scp->device->lun == 0 &&
5589 (scp->request_bufflen - qdonep->remain_bytes) >= 8) {
5590 AscInquiryHandling(asc_dvc_varp, scp->device->id & 0x7,
5591 (ASC_SCSI_INQUIRY *)scp->
5596 * Check for an underrun condition.
5598 * If there was no error and an underrun condition, then
5599 * then return the number of underrun bytes.
5601 if (scp->request_bufflen != 0 && qdonep->remain_bytes != 0 &&
5602 qdonep->remain_bytes <= scp->request_bufflen) {
5604 "asc_isr_callback: underrun condition %u bytes\n",
5605 (unsigned)qdonep->remain_bytes);
5606 scp->resid = qdonep->remain_bytes;
5611 ASC_DBG(2, "asc_isr_callback: QD_WITH_ERROR\n");
5612 switch (qdonep->d3.host_stat) {
5613 case QHSTA_NO_ERROR:
5614 if (qdonep->d3.scsi_stat == SAM_STAT_CHECK_CONDITION) {
5616 "asc_isr_callback: SAM_STAT_CHECK_CONDITION\n");
5617 ASC_DBG_PRT_SENSE(2, scp->sense_buffer,
5618 sizeof(scp->sense_buffer));
5620 * Note: The 'status_byte()' macro used by target drivers
5621 * defined in scsi.h shifts the status byte returned by
5622 * host drivers right by 1 bit. This is why target drivers
5623 * also use right shifted status byte definitions. For
5624 * instance target drivers use CHECK_CONDITION, defined to
5625 * 0x1, instead of the SCSI defined check condition value
5626 * of 0x2. Host drivers are supposed to return the status
5627 * byte as it is defined by SCSI.
5629 scp->result = DRIVER_BYTE(DRIVER_SENSE) |
5630 STATUS_BYTE(qdonep->d3.scsi_stat);
5632 scp->result = STATUS_BYTE(qdonep->d3.scsi_stat);
5637 /* QHSTA error occurred */
5638 ASC_DBG1(1, "asc_isr_callback: host_stat 0x%x\n",
5639 qdonep->d3.host_stat);
5640 scp->result = HOST_BYTE(DID_BAD_TARGET);
5645 case QD_ABORTED_BY_HOST:
5646 ASC_DBG(1, "asc_isr_callback: QD_ABORTED_BY_HOST\n");
5648 HOST_BYTE(DID_ABORT) | MSG_BYTE(qdonep->d3.
5650 STATUS_BYTE(qdonep->d3.scsi_stat);
5654 ASC_DBG1(1, "asc_isr_callback: done_stat 0x%x\n",
5655 qdonep->d3.done_stat);
5657 HOST_BYTE(DID_ERROR) | MSG_BYTE(qdonep->d3.
5659 STATUS_BYTE(qdonep->d3.scsi_stat);
5664 * If the 'init_tidmask' bit isn't already set for the target and the
5665 * current request finished normally, then set the bit for the target
5666 * to indicate that a device is present.
5668 if ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(scp->device->id)) == 0 &&
5669 qdonep->d3.done_stat == QD_NO_ERROR &&
5670 qdonep->d3.host_stat == QHSTA_NO_ERROR) {
5671 boardp->init_tidmask |= ADV_TID_TO_TIDMASK(scp->device->id);
5675 * Because interrupts may be enabled by the 'struct scsi_cmnd' done
5676 * function, add the command to the end of the board's done queue.
5677 * The done function for the command will be called from
5678 * advansys_interrupt().
5680 asc_enqueue(&boardp->done, scp, ASC_BACK);
5686 * adv_isr_callback() - Second Level Interrupt Handler called by AdvISR().
5688 * Callback function for the Wide SCSI Adv Library.
5690 static void adv_isr_callback(ADV_DVC_VAR *adv_dvc_varp, ADV_SCSI_REQ_Q *scsiqp)
5692 asc_board_t *boardp;
5694 adv_sgblk_t *sgblkp;
5695 struct scsi_cmnd *scp;
5696 struct Scsi_Host *shost;
5700 ASC_DBG2(1, "adv_isr_callback: adv_dvc_varp 0x%lx, scsiqp 0x%lx\n",
5701 (ulong)adv_dvc_varp, (ulong)scsiqp);
5702 ASC_DBG_PRT_ADV_SCSI_REQ_Q(2, scsiqp);
5705 * Get the adv_req_t structure for the command that has been
5706 * completed. The adv_req_t structure actually contains the
5707 * completed ADV_SCSI_REQ_Q structure.
5709 reqp = (adv_req_t *)ADV_U32_TO_VADDR(scsiqp->srb_ptr);
5710 ASC_DBG1(1, "adv_isr_callback: reqp 0x%lx\n", (ulong)reqp);
5712 ASC_PRINT("adv_isr_callback: reqp is NULL\n");
5717 * Get the struct scsi_cmnd structure and Scsi_Host structure for the
5718 * command that has been completed.
5720 * Note: The adv_req_t request structure and adv_sgblk_t structure,
5721 * if any, are dropped, because a board structure pointer can not be
5725 ASC_DBG1(1, "adv_isr_callback: scp 0x%lx\n", (ulong)scp);
5728 ("adv_isr_callback: scp is NULL; adv_req_t dropped.\n");
5731 ASC_DBG_PRT_CDB(2, scp->cmnd, scp->cmd_len);
5734 * If the request's host pointer is not valid, display a message
5737 shost = scp->device->host;
5738 for (i = 0; i < asc_board_count; i++) {
5739 if (asc_host[i] == shost) {
5744 * Note: If the host structure is not found, the adv_req_t request
5745 * structure and adv_sgblk_t structure, if any, is dropped.
5747 if (i == asc_board_count) {
5749 ("adv_isr_callback: scp 0x%lx has bad host pointer, host 0x%lx\n",
5750 (ulong)scp, (ulong)shost);
5754 ASC_STATS(shost, callback);
5755 ASC_DBG1(1, "adv_isr_callback: shost 0x%lx\n", (ulong)shost);
5758 * If the request isn't found on the active queue, it may have been
5759 * removed to handle a reset request. Display a message and return.
5761 * Note: Because the structure may still be in use don't attempt
5762 * to free the adv_req_t and adv_sgblk_t, if any, structures.
5764 boardp = ASC_BOARDP(shost);
5765 ASC_ASSERT(adv_dvc_varp == &boardp->dvc_var.adv_dvc_var);
5766 if (asc_rmqueue(&boardp->active, scp) == ASC_FALSE) {
5768 ("adv_isr_callback: board %d: scp 0x%lx not on active queue\n",
5769 boardp->id, (ulong)scp);
5774 * 'done_status' contains the command's ending status.
5776 switch (scsiqp->done_status) {
5778 ASC_DBG(2, "adv_isr_callback: QD_NO_ERROR\n");
5782 * Check for an underrun condition.
5784 * If there was no error and an underrun condition, then
5785 * then return the number of underrun bytes.
5787 resid_cnt = le32_to_cpu(scsiqp->data_cnt);
5788 if (scp->request_bufflen != 0 && resid_cnt != 0 &&
5789 resid_cnt <= scp->request_bufflen) {
5791 "adv_isr_callback: underrun condition %lu bytes\n",
5793 scp->resid = resid_cnt;
5798 ASC_DBG(2, "adv_isr_callback: QD_WITH_ERROR\n");
5799 switch (scsiqp->host_status) {
5800 case QHSTA_NO_ERROR:
5801 if (scsiqp->scsi_status == SAM_STAT_CHECK_CONDITION) {
5803 "adv_isr_callback: SAM_STAT_CHECK_CONDITION\n");
5804 ASC_DBG_PRT_SENSE(2, scp->sense_buffer,
5805 sizeof(scp->sense_buffer));
5807 * Note: The 'status_byte()' macro used by target drivers
5808 * defined in scsi.h shifts the status byte returned by
5809 * host drivers right by 1 bit. This is why target drivers
5810 * also use right shifted status byte definitions. For
5811 * instance target drivers use CHECK_CONDITION, defined to
5812 * 0x1, instead of the SCSI defined check condition value
5813 * of 0x2. Host drivers are supposed to return the status
5814 * byte as it is defined by SCSI.
5816 scp->result = DRIVER_BYTE(DRIVER_SENSE) |
5817 STATUS_BYTE(scsiqp->scsi_status);
5819 scp->result = STATUS_BYTE(scsiqp->scsi_status);
5824 /* Some other QHSTA error occurred. */
5825 ASC_DBG1(1, "adv_isr_callback: host_status 0x%x\n",
5826 scsiqp->host_status);
5827 scp->result = HOST_BYTE(DID_BAD_TARGET);
5832 case QD_ABORTED_BY_HOST:
5833 ASC_DBG(1, "adv_isr_callback: QD_ABORTED_BY_HOST\n");
5835 HOST_BYTE(DID_ABORT) | STATUS_BYTE(scsiqp->scsi_status);
5839 ASC_DBG1(1, "adv_isr_callback: done_status 0x%x\n",
5840 scsiqp->done_status);
5842 HOST_BYTE(DID_ERROR) | STATUS_BYTE(scsiqp->scsi_status);
5847 * If the 'init_tidmask' bit isn't already set for the target and the
5848 * current request finished normally, then set the bit for the target
5849 * to indicate that a device is present.
5851 if ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(scp->device->id)) == 0 &&
5852 scsiqp->done_status == QD_NO_ERROR &&
5853 scsiqp->host_status == QHSTA_NO_ERROR) {
5854 boardp->init_tidmask |= ADV_TID_TO_TIDMASK(scp->device->id);
5858 * Because interrupts may be enabled by the 'struct scsi_cmnd' done
5859 * function, add the command to the end of the board's done queue.
5860 * The done function for the command will be called from
5861 * advansys_interrupt().
5863 asc_enqueue(&boardp->done, scp, ASC_BACK);
5866 * Free all 'adv_sgblk_t' structures allocated for the request.
5868 while ((sgblkp = reqp->sgblkp) != NULL) {
5869 /* Remove 'sgblkp' from the request list. */
5870 reqp->sgblkp = sgblkp->next_sgblkp;
5872 /* Add 'sgblkp' to the board free list. */
5873 sgblkp->next_sgblkp = boardp->adv_sgblkp;
5874 boardp->adv_sgblkp = sgblkp;
5878 * Free the adv_req_t structure used with the command by adding
5879 * it back to the board free list.
5881 reqp->next_reqp = boardp->adv_reqp;
5882 boardp->adv_reqp = reqp;
5884 ASC_DBG(1, "adv_isr_callback: done\n");
5890 * adv_async_callback() - Adv Library asynchronous event callback function.
5892 static void adv_async_callback(ADV_DVC_VAR *adv_dvc_varp, uchar code)
5895 case ADV_ASYNC_SCSI_BUS_RESET_DET:
5897 * The firmware detected a SCSI Bus reset.
5900 "adv_async_callback: ADV_ASYNC_SCSI_BUS_RESET_DET\n");
5903 case ADV_ASYNC_RDMA_FAILURE:
5905 * Handle RDMA failure by resetting the SCSI Bus and
5906 * possibly the chip if it is unresponsive. Log the error
5907 * with a unique code.
5909 ASC_DBG(0, "adv_async_callback: ADV_ASYNC_RDMA_FAILURE\n");
5910 AdvResetChipAndSB(adv_dvc_varp);
5913 case ADV_HOST_SCSI_BUS_RESET:
5915 * Host generated SCSI bus reset occurred.
5917 ASC_DBG(0, "adv_async_callback: ADV_HOST_SCSI_BUS_RESET\n");
5921 ASC_DBG1(0, "DvcAsyncCallBack: unknown code 0x%x\n", code);
5927 * Add a 'REQP' to the end of specified queue. Set 'tidmask'
5928 * to indicate a command is queued for the device.
5930 * 'flag' may be either ASC_FRONT or ASC_BACK.
5932 * 'REQPNEXT(reqp)' returns reqp's next pointer.
5934 static void asc_enqueue(asc_queue_t *ascq, REQP reqp, int flag)
5938 ASC_DBG3(3, "asc_enqueue: ascq 0x%lx, reqp 0x%lx, flag %d\n",
5939 (ulong)ascq, (ulong)reqp, flag);
5940 ASC_ASSERT(reqp != NULL);
5941 ASC_ASSERT(flag == ASC_FRONT || flag == ASC_BACK);
5942 tid = REQPTID(reqp);
5943 ASC_ASSERT(tid >= 0 && tid <= ADV_MAX_TID);
5944 if (flag == ASC_FRONT) {
5945 reqp->host_scribble = (unsigned char *)ascq->q_first[tid];
5946 ascq->q_first[tid] = reqp;
5947 /* If the queue was empty, set the last pointer. */
5948 if (ascq->q_last[tid] == NULL) {
5949 ascq->q_last[tid] = reqp;
5951 } else { /* ASC_BACK */
5952 if (ascq->q_last[tid] != NULL) {
5953 ascq->q_last[tid]->host_scribble =
5954 (unsigned char *)reqp;
5956 ascq->q_last[tid] = reqp;
5957 reqp->host_scribble = NULL;
5958 /* If the queue was empty, set the first pointer. */
5959 if (ascq->q_first[tid] == NULL) {
5960 ascq->q_first[tid] = reqp;
5963 /* The queue has at least one entry, set its bit. */
5964 ascq->q_tidmask |= ADV_TID_TO_TIDMASK(tid);
5965 #ifdef ADVANSYS_STATS
5966 /* Maintain request queue statistics. */
5967 ascq->q_tot_cnt[tid]++;
5968 ascq->q_cur_cnt[tid]++;
5969 if (ascq->q_cur_cnt[tid] > ascq->q_max_cnt[tid]) {
5970 ascq->q_max_cnt[tid] = ascq->q_cur_cnt[tid];
5971 ASC_DBG2(2, "asc_enqueue: new q_max_cnt[%d] %d\n",
5972 tid, ascq->q_max_cnt[tid]);
5974 REQPTIME(reqp) = REQTIMESTAMP();
5975 #endif /* ADVANSYS_STATS */
5976 ASC_DBG1(3, "asc_enqueue: reqp 0x%lx\n", (ulong)reqp);
5981 * Return first queued 'REQP' on the specified queue for
5982 * the specified target device. Clear the 'tidmask' bit for
5983 * the device if no more commands are left queued for it.
5985 * 'REQPNEXT(reqp)' returns reqp's next pointer.
5987 static REQP asc_dequeue(asc_queue_t *ascq, int tid)
5991 ASC_DBG2(3, "asc_dequeue: ascq 0x%lx, tid %d\n", (ulong)ascq, tid);
5992 ASC_ASSERT(tid >= 0 && tid <= ADV_MAX_TID);
5993 if ((reqp = ascq->q_first[tid]) != NULL) {
5994 ASC_ASSERT(ascq->q_tidmask & ADV_TID_TO_TIDMASK(tid));
5995 ascq->q_first[tid] = REQPNEXT(reqp);
5996 /* If the queue is empty, clear its bit and the last pointer. */
5997 if (ascq->q_first[tid] == NULL) {
5998 ascq->q_tidmask &= ~ADV_TID_TO_TIDMASK(tid);
5999 ASC_ASSERT(ascq->q_last[tid] == reqp);
6000 ascq->q_last[tid] = NULL;
6002 #ifdef ADVANSYS_STATS
6003 /* Maintain request queue statistics. */
6004 ascq->q_cur_cnt[tid]--;
6005 ASC_ASSERT(ascq->q_cur_cnt[tid] >= 0);
6006 REQTIMESTAT("asc_dequeue", ascq, reqp, tid);
6007 #endif /* ADVANSYS_STATS */
6009 ASC_DBG1(3, "asc_dequeue: reqp 0x%lx\n", (ulong)reqp);
6014 * Return a pointer to a singly linked list of all the requests queued
6015 * for 'tid' on the 'asc_queue_t' pointed to by 'ascq'.
6017 * If 'lastpp' is not NULL, '*lastpp' will be set to point to the
6018 * the last request returned in the singly linked list.
6020 * 'tid' should either be a valid target id or if it is ASC_TID_ALL,
6021 * then all queued requests are concatenated into one list and
6024 * Note: If 'lastpp' is used to append a new list to the end of
6025 * an old list, only change the old list last pointer if '*lastpp'
6026 * (or the function return value) is not NULL, i.e. use a temporary
6027 * variable for 'lastpp' and check its value after the function return
6028 * before assigning it to the list last pointer.
6030 * Unfortunately collecting queuing time statistics adds overhead to
6031 * the function that isn't inherent to the function's algorithm.
6033 static REQP asc_dequeue_list(asc_queue_t *ascq, REQP *lastpp, int tid)
6038 ASC_DBG2(3, "asc_dequeue_list: ascq 0x%lx, tid %d\n", (ulong)ascq, tid);
6039 ASC_ASSERT((tid == ASC_TID_ALL) || (tid >= 0 && tid <= ADV_MAX_TID));
6042 * If 'tid' is not ASC_TID_ALL, return requests only for
6043 * the specified 'tid'. If 'tid' is ASC_TID_ALL, return all
6044 * requests for all tids.
6046 if (tid != ASC_TID_ALL) {
6047 /* Return all requests for the specified 'tid'. */
6048 if ((ascq->q_tidmask & ADV_TID_TO_TIDMASK(tid)) == 0) {
6049 /* List is empty; Set first and last return pointers to NULL. */
6050 firstp = lastp = NULL;
6052 firstp = ascq->q_first[tid];
6053 lastp = ascq->q_last[tid];
6054 ascq->q_first[tid] = ascq->q_last[tid] = NULL;
6055 ascq->q_tidmask &= ~ADV_TID_TO_TIDMASK(tid);
6056 #ifdef ADVANSYS_STATS
6059 ascq->q_cur_cnt[tid] = 0;
6060 for (reqp = firstp; reqp; reqp = REQPNEXT(reqp)) {
6061 REQTIMESTAT("asc_dequeue_list", ascq,
6065 #endif /* ADVANSYS_STATS */
6068 /* Return all requests for all tids. */
6069 firstp = lastp = NULL;
6070 for (i = 0; i <= ADV_MAX_TID; i++) {
6071 if (ascq->q_tidmask & ADV_TID_TO_TIDMASK(i)) {
6072 if (firstp == NULL) {
6073 firstp = ascq->q_first[i];
6074 lastp = ascq->q_last[i];
6076 ASC_ASSERT(lastp != NULL);
6077 lastp->host_scribble =
6078 (unsigned char *)ascq->q_first[i];
6079 lastp = ascq->q_last[i];
6081 ascq->q_first[i] = ascq->q_last[i] = NULL;
6082 ascq->q_tidmask &= ~ADV_TID_TO_TIDMASK(i);
6083 #ifdef ADVANSYS_STATS
6084 ascq->q_cur_cnt[i] = 0;
6085 #endif /* ADVANSYS_STATS */
6088 #ifdef ADVANSYS_STATS
6091 for (reqp = firstp; reqp; reqp = REQPNEXT(reqp)) {
6092 REQTIMESTAT("asc_dequeue_list", ascq, reqp,
6096 #endif /* ADVANSYS_STATS */
6101 ASC_DBG1(3, "asc_dequeue_list: firstp 0x%lx\n", (ulong)firstp);
6106 * Remove the specified 'REQP' from the specified queue for
6107 * the specified target device. Clear the 'tidmask' bit for the
6108 * device if no more commands are left queued for it.
6110 * 'REQPNEXT(reqp)' returns reqp's the next pointer.
6112 * Return ASC_TRUE if the command was found and removed,
6113 * otherwise return ASC_FALSE.
6115 static int asc_rmqueue(asc_queue_t *ascq, REQP reqp)
6119 int ret = ASC_FALSE;
6121 ASC_DBG2(3, "asc_rmqueue: ascq 0x%lx, reqp 0x%lx\n",
6122 (ulong)ascq, (ulong)reqp);
6123 ASC_ASSERT(reqp != NULL);
6125 tid = REQPTID(reqp);
6126 ASC_ASSERT(tid >= 0 && tid <= ADV_MAX_TID);
6129 * Handle the common case of 'reqp' being the first
6130 * entry on the queue.
6132 if (reqp == ascq->q_first[tid]) {
6134 ascq->q_first[tid] = REQPNEXT(reqp);
6135 /* If the queue is now empty, clear its bit and the last pointer. */
6136 if (ascq->q_first[tid] == NULL) {
6137 ascq->q_tidmask &= ~ADV_TID_TO_TIDMASK(tid);
6138 ASC_ASSERT(ascq->q_last[tid] == reqp);
6139 ascq->q_last[tid] = NULL;
6141 } else if (ascq->q_first[tid] != NULL) {
6142 ASC_ASSERT(ascq->q_last[tid] != NULL);
6144 * Because the case of 'reqp' being the first entry has been
6145 * handled above and it is known the queue is not empty, if
6146 * 'reqp' is found on the queue it is guaranteed the queue will
6147 * not become empty and that 'q_first[tid]' will not be changed.
6149 * Set 'prevp' to the first entry, 'currp' to the second entry,
6150 * and search for 'reqp'.
6152 for (prevp = ascq->q_first[tid], currp = REQPNEXT(prevp);
6153 currp; prevp = currp, currp = REQPNEXT(currp)) {
6154 if (currp == reqp) {
6156 prevp->host_scribble =
6157 (unsigned char *)REQPNEXT(currp);
6158 reqp->host_scribble = NULL;
6159 if (ascq->q_last[tid] == reqp) {
6160 ascq->q_last[tid] = prevp;
6166 #ifdef ADVANSYS_STATS
6167 /* Maintain request queue statistics. */
6168 if (ret == ASC_TRUE) {
6169 ascq->q_cur_cnt[tid]--;
6170 REQTIMESTAT("asc_rmqueue", ascq, reqp, tid);
6172 ASC_ASSERT(ascq->q_cur_cnt[tid] >= 0);
6173 #endif /* ADVANSYS_STATS */
6174 ASC_DBG2(3, "asc_rmqueue: reqp 0x%lx, ret %d\n", (ulong)reqp, ret);
6179 * Execute as many queued requests as possible for the specified queue.
6181 * Calls asc_execute_scsi_cmnd() to execute a REQP/struct scsi_cmnd.
6183 static void asc_execute_queue(asc_queue_t *ascq)
6185 ADV_SCSI_BIT_ID_TYPE scan_tidmask;
6189 ASC_DBG1(1, "asc_execute_queue: ascq 0x%lx\n", (ulong)ascq);
6191 * Execute queued commands for devices attached to
6192 * the current board in round-robin fashion.
6194 scan_tidmask = ascq->q_tidmask;
6196 for (i = 0; i <= ADV_MAX_TID; i++) {
6197 if (scan_tidmask & ADV_TID_TO_TIDMASK(i)) {
6198 if ((reqp = asc_dequeue(ascq, i)) == NULL) {
6199 scan_tidmask &= ~ADV_TID_TO_TIDMASK(i);
6201 if (asc_execute_scsi_cmnd
6202 ((struct scsi_cmnd *)reqp)
6204 scan_tidmask &= ~ADV_TID_TO_TIDMASK(i);
6206 * The request returned ASC_BUSY. Enqueue at the front of
6207 * target's waiting list to maintain correct ordering.
6209 asc_enqueue(ascq, reqp, ASC_FRONT);
6213 } while (scan_tidmask);
6217 #ifdef CONFIG_PROC_FS
6219 * asc_prt_board_devices()
6221 * Print driver information for devices attached to the board.
6223 * Note: no single line should be greater than ASC_PRTLINE_SIZE,
6224 * cf. asc_prt_line().
6226 * Return the number of characters copied into 'cp'. No more than
6227 * 'cplen' characters will be copied to 'cp'.
6229 static int asc_prt_board_devices(struct Scsi_Host *shost, char *cp, int cplen)
6231 asc_board_t *boardp;
6238 boardp = ASC_BOARDP(shost);
6242 len = asc_prt_line(cp, leftlen,
6243 "\nDevice Information for AdvanSys SCSI Host %d:\n",
6247 if (ASC_NARROW_BOARD(boardp)) {
6248 chip_scsi_id = boardp->dvc_cfg.asc_dvc_cfg.chip_scsi_id;
6250 chip_scsi_id = boardp->dvc_var.adv_dvc_var.chip_scsi_id;
6253 len = asc_prt_line(cp, leftlen, "Target IDs Detected:");
6255 for (i = 0; i <= ADV_MAX_TID; i++) {
6256 if (boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) {
6257 len = asc_prt_line(cp, leftlen, " %X,", i);
6261 len = asc_prt_line(cp, leftlen, " (%X=Host Adapter)\n", chip_scsi_id);
6268 * Display Wide Board BIOS Information.
6270 static int asc_prt_adv_bios(struct Scsi_Host *shost, char *cp, int cplen)
6272 asc_board_t *boardp;
6276 ushort major, minor, letter;
6278 boardp = ASC_BOARDP(shost);
6282 len = asc_prt_line(cp, leftlen, "\nROM BIOS Version: ");
6286 * If the BIOS saved a valid signature, then fill in
6287 * the BIOS code segment base address.
6289 if (boardp->bios_signature != 0x55AA) {
6290 len = asc_prt_line(cp, leftlen, "Disabled or Pre-3.1\n");
6292 len = asc_prt_line(cp, leftlen,
6293 "BIOS either disabled or Pre-3.1. If it is pre-3.1, then a newer version\n");
6295 len = asc_prt_line(cp, leftlen,
6296 "can be found at the ConnectCom FTP site: ftp://ftp.connectcom.net/pub\n");
6299 major = (boardp->bios_version >> 12) & 0xF;
6300 minor = (boardp->bios_version >> 8) & 0xF;
6301 letter = (boardp->bios_version & 0xFF);
6303 len = asc_prt_line(cp, leftlen, "%d.%d%c\n",
6305 letter >= 26 ? '?' : letter + 'A');
6309 * Current available ROM BIOS release is 3.1I for UW
6310 * and 3.2I for U2W. This code doesn't differentiate
6311 * UW and U2W boards.
6313 if (major < 3 || (major <= 3 && minor < 1) ||
6314 (major <= 3 && minor <= 1 && letter < ('I' - 'A'))) {
6315 len = asc_prt_line(cp, leftlen,
6316 "Newer version of ROM BIOS is available at the ConnectCom FTP site:\n");
6318 len = asc_prt_line(cp, leftlen,
6319 "ftp://ftp.connectcom.net/pub\n");
6328 * Add serial number to information bar if signature AAh
6329 * is found in at bit 15-9 (7 bits) of word 1.
6331 * Serial Number consists fo 12 alpha-numeric digits.
6333 * 1 - Product type (A,B,C,D..) Word0: 15-13 (3 bits)
6334 * 2 - MFG Location (A,B,C,D..) Word0: 12-10 (3 bits)
6335 * 3-4 - Product ID (0-99) Word0: 9-0 (10 bits)
6336 * 5 - Product revision (A-J) Word0: " "
6338 * Signature Word1: 15-9 (7 bits)
6339 * 6 - Year (0-9) Word1: 8-6 (3 bits) & Word2: 15 (1 bit)
6340 * 7-8 - Week of the year (1-52) Word1: 5-0 (6 bits)
6342 * 9-12 - Serial Number (A001-Z999) Word2: 14-0 (15 bits)
6344 * Note 1: Only production cards will have a serial number.
6346 * Note 2: Signature is most significant 7 bits (0xFE).
6348 * Returns ASC_TRUE if serial number found, otherwise returns ASC_FALSE.
6350 static int asc_get_eeprom_string(ushort *serialnum, uchar *cp)
6354 if ((serialnum[1] & 0xFE00) != ((ushort)0xAA << 8)) {
6358 * First word - 6 digits.
6362 /* Product type - 1st digit. */
6363 if ((*cp = 'A' + ((w & 0xE000) >> 13)) == 'H') {
6364 /* Product type is P=Prototype */
6369 /* Manufacturing location - 2nd digit. */
6370 *cp++ = 'A' + ((w & 0x1C00) >> 10);
6372 /* Product ID - 3rd, 4th digits. */
6374 *cp++ = '0' + (num / 100);
6376 *cp++ = '0' + (num / 10);
6378 /* Product revision - 5th digit. */
6379 *cp++ = 'A' + (num % 10);
6389 * If bit 15 of third word is set, then the
6390 * last digit of the year is greater than 7.
6392 if (serialnum[2] & 0x8000) {
6393 *cp++ = '8' + ((w & 0x1C0) >> 6);
6395 *cp++ = '0' + ((w & 0x1C0) >> 6);
6398 /* Week of year - 7th, 8th digits. */
6400 *cp++ = '0' + num / 10;
6407 w = serialnum[2] & 0x7FFF;
6409 /* Serial number - 9th digit. */
6410 *cp++ = 'A' + (w / 1000);
6412 /* 10th, 11th, 12th digits. */
6414 *cp++ = '0' + num / 100;
6416 *cp++ = '0' + num / 10;
6420 *cp = '\0'; /* Null Terminate the string. */
6426 * asc_prt_asc_board_eeprom()
6428 * Print board EEPROM configuration.
6430 * Note: no single line should be greater than ASC_PRTLINE_SIZE,
6431 * cf. asc_prt_line().
6433 * Return the number of characters copied into 'cp'. No more than
6434 * 'cplen' characters will be copied to 'cp'.
6436 static int asc_prt_asc_board_eeprom(struct Scsi_Host *shost, char *cp, int cplen)
6438 asc_board_t *boardp;
6439 ASC_DVC_VAR *asc_dvc_varp;
6446 int isa_dma_speed[] = { 10, 8, 7, 6, 5, 4, 3, 2 };
6447 #endif /* CONFIG_ISA */
6448 uchar serialstr[13];
6450 boardp = ASC_BOARDP(shost);
6451 asc_dvc_varp = &boardp->dvc_var.asc_dvc_var;
6452 ep = &boardp->eep_config.asc_eep;
6457 len = asc_prt_line(cp, leftlen,
6458 "\nEEPROM Settings for AdvanSys SCSI Host %d:\n",
6462 if (asc_get_eeprom_string((ushort *)&ep->adapter_info[0], serialstr)
6465 asc_prt_line(cp, leftlen, " Serial Number: %s\n",
6469 if (ep->adapter_info[5] == 0xBB) {
6470 len = asc_prt_line(cp, leftlen,
6471 " Default Settings Used for EEPROM-less Adapter.\n");
6474 len = asc_prt_line(cp, leftlen,
6475 " Serial Number Signature Not Present.\n");
6480 len = asc_prt_line(cp, leftlen,
6481 " Host SCSI ID: %u, Host Queue Size: %u, Device Queue Size: %u\n",
6482 ASC_EEP_GET_CHIP_ID(ep), ep->max_total_qng,
6486 len = asc_prt_line(cp, leftlen,
6487 " cntl 0x%x, no_scam 0x%x\n", ep->cntl, ep->no_scam);
6490 len = asc_prt_line(cp, leftlen, " Target ID: ");
6492 for (i = 0; i <= ASC_MAX_TID; i++) {
6493 len = asc_prt_line(cp, leftlen, " %d", i);
6496 len = asc_prt_line(cp, leftlen, "\n");
6499 len = asc_prt_line(cp, leftlen, " Disconnects: ");
6501 for (i = 0; i <= ASC_MAX_TID; i++) {
6502 len = asc_prt_line(cp, leftlen, " %c",
6504 disc_enable & ADV_TID_TO_TIDMASK(i)) ? 'Y' :
6508 len = asc_prt_line(cp, leftlen, "\n");
6511 len = asc_prt_line(cp, leftlen, " Command Queuing: ");
6513 for (i = 0; i <= ASC_MAX_TID; i++) {
6514 len = asc_prt_line(cp, leftlen, " %c",
6516 use_cmd_qng & ADV_TID_TO_TIDMASK(i)) ? 'Y' :
6520 len = asc_prt_line(cp, leftlen, "\n");
6523 len = asc_prt_line(cp, leftlen, " Start Motor: ");
6525 for (i = 0; i <= ASC_MAX_TID; i++) {
6526 len = asc_prt_line(cp, leftlen, " %c",
6528 start_motor & ADV_TID_TO_TIDMASK(i)) ? 'Y' :
6532 len = asc_prt_line(cp, leftlen, "\n");
6535 len = asc_prt_line(cp, leftlen, " Synchronous Transfer:");
6537 for (i = 0; i <= ASC_MAX_TID; i++) {
6538 len = asc_prt_line(cp, leftlen, " %c",
6540 init_sdtr & ADV_TID_TO_TIDMASK(i)) ? 'Y' :
6544 len = asc_prt_line(cp, leftlen, "\n");
6548 if (asc_dvc_varp->bus_type & ASC_IS_ISA) {
6549 len = asc_prt_line(cp, leftlen,
6550 " Host ISA DMA speed: %d MB/S\n",
6551 isa_dma_speed[ASC_EEP_GET_DMA_SPD(ep)]);
6554 #endif /* CONFIG_ISA */
6560 * asc_prt_adv_board_eeprom()
6562 * Print board EEPROM configuration.
6564 * Note: no single line should be greater than ASC_PRTLINE_SIZE,
6565 * cf. asc_prt_line().
6567 * Return the number of characters copied into 'cp'. No more than
6568 * 'cplen' characters will be copied to 'cp'.
6570 static int asc_prt_adv_board_eeprom(struct Scsi_Host *shost, char *cp, int cplen)
6572 asc_board_t *boardp;
6573 ADV_DVC_VAR *adv_dvc_varp;
6579 uchar serialstr[13];
6580 ADVEEP_3550_CONFIG *ep_3550 = NULL;
6581 ADVEEP_38C0800_CONFIG *ep_38C0800 = NULL;
6582 ADVEEP_38C1600_CONFIG *ep_38C1600 = NULL;
6585 ushort sdtr_speed = 0;
6587 boardp = ASC_BOARDP(shost);
6588 adv_dvc_varp = &boardp->dvc_var.adv_dvc_var;
6589 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
6590 ep_3550 = &boardp->eep_config.adv_3550_eep;
6591 } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
6592 ep_38C0800 = &boardp->eep_config.adv_38C0800_eep;
6594 ep_38C1600 = &boardp->eep_config.adv_38C1600_eep;
6600 len = asc_prt_line(cp, leftlen,
6601 "\nEEPROM Settings for AdvanSys SCSI Host %d:\n",
6605 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
6606 wordp = &ep_3550->serial_number_word1;
6607 } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
6608 wordp = &ep_38C0800->serial_number_word1;
6610 wordp = &ep_38C1600->serial_number_word1;
6613 if (asc_get_eeprom_string(wordp, serialstr) == ASC_TRUE) {
6615 asc_prt_line(cp, leftlen, " Serial Number: %s\n",
6619 len = asc_prt_line(cp, leftlen,
6620 " Serial Number Signature Not Present.\n");
6624 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
6625 len = asc_prt_line(cp, leftlen,
6626 " Host SCSI ID: %u, Host Queue Size: %u, Device Queue Size: %u\n",
6627 ep_3550->adapter_scsi_id,
6628 ep_3550->max_host_qng, ep_3550->max_dvc_qng);
6630 } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
6631 len = asc_prt_line(cp, leftlen,
6632 " Host SCSI ID: %u, Host Queue Size: %u, Device Queue Size: %u\n",
6633 ep_38C0800->adapter_scsi_id,
6634 ep_38C0800->max_host_qng,
6635 ep_38C0800->max_dvc_qng);
6638 len = asc_prt_line(cp, leftlen,
6639 " Host SCSI ID: %u, Host Queue Size: %u, Device Queue Size: %u\n",
6640 ep_38C1600->adapter_scsi_id,
6641 ep_38C1600->max_host_qng,
6642 ep_38C1600->max_dvc_qng);
6645 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
6646 word = ep_3550->termination;
6647 } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
6648 word = ep_38C0800->termination_lvd;
6650 word = ep_38C1600->termination_lvd;
6654 termstr = "Low Off/High Off";
6657 termstr = "Low Off/High On";
6660 termstr = "Low On/High On";
6664 termstr = "Automatic";
6668 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
6669 len = asc_prt_line(cp, leftlen,
6670 " termination: %u (%s), bios_ctrl: 0x%x\n",
6671 ep_3550->termination, termstr,
6672 ep_3550->bios_ctrl);
6674 } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
6675 len = asc_prt_line(cp, leftlen,
6676 " termination: %u (%s), bios_ctrl: 0x%x\n",
6677 ep_38C0800->termination_lvd, termstr,
6678 ep_38C0800->bios_ctrl);
6681 len = asc_prt_line(cp, leftlen,
6682 " termination: %u (%s), bios_ctrl: 0x%x\n",
6683 ep_38C1600->termination_lvd, termstr,
6684 ep_38C1600->bios_ctrl);
6688 len = asc_prt_line(cp, leftlen, " Target ID: ");
6690 for (i = 0; i <= ADV_MAX_TID; i++) {
6691 len = asc_prt_line(cp, leftlen, " %X", i);
6694 len = asc_prt_line(cp, leftlen, "\n");
6697 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
6698 word = ep_3550->disc_enable;
6699 } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
6700 word = ep_38C0800->disc_enable;
6702 word = ep_38C1600->disc_enable;
6704 len = asc_prt_line(cp, leftlen, " Disconnects: ");
6706 for (i = 0; i <= ADV_MAX_TID; i++) {
6707 len = asc_prt_line(cp, leftlen, " %c",
6708 (word & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
6711 len = asc_prt_line(cp, leftlen, "\n");
6714 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
6715 word = ep_3550->tagqng_able;
6716 } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
6717 word = ep_38C0800->tagqng_able;
6719 word = ep_38C1600->tagqng_able;
6721 len = asc_prt_line(cp, leftlen, " Command Queuing: ");
6723 for (i = 0; i <= ADV_MAX_TID; i++) {
6724 len = asc_prt_line(cp, leftlen, " %c",
6725 (word & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
6728 len = asc_prt_line(cp, leftlen, "\n");
6731 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
6732 word = ep_3550->start_motor;
6733 } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
6734 word = ep_38C0800->start_motor;
6736 word = ep_38C1600->start_motor;
6738 len = asc_prt_line(cp, leftlen, " Start Motor: ");
6740 for (i = 0; i <= ADV_MAX_TID; i++) {
6741 len = asc_prt_line(cp, leftlen, " %c",
6742 (word & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
6745 len = asc_prt_line(cp, leftlen, "\n");
6748 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
6749 len = asc_prt_line(cp, leftlen, " Synchronous Transfer:");
6751 for (i = 0; i <= ADV_MAX_TID; i++) {
6752 len = asc_prt_line(cp, leftlen, " %c",
6754 sdtr_able & ADV_TID_TO_TIDMASK(i)) ?
6758 len = asc_prt_line(cp, leftlen, "\n");
6762 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
6763 len = asc_prt_line(cp, leftlen, " Ultra Transfer: ");
6765 for (i = 0; i <= ADV_MAX_TID; i++) {
6766 len = asc_prt_line(cp, leftlen, " %c",
6768 ultra_able & ADV_TID_TO_TIDMASK(i))
6772 len = asc_prt_line(cp, leftlen, "\n");
6776 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
6777 word = ep_3550->wdtr_able;
6778 } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
6779 word = ep_38C0800->wdtr_able;
6781 word = ep_38C1600->wdtr_able;
6783 len = asc_prt_line(cp, leftlen, " Wide Transfer: ");
6785 for (i = 0; i <= ADV_MAX_TID; i++) {
6786 len = asc_prt_line(cp, leftlen, " %c",
6787 (word & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
6790 len = asc_prt_line(cp, leftlen, "\n");
6793 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800 ||
6794 adv_dvc_varp->chip_type == ADV_CHIP_ASC38C1600) {
6795 len = asc_prt_line(cp, leftlen,
6796 " Synchronous Transfer Speed (Mhz):\n ");
6798 for (i = 0; i <= ADV_MAX_TID; i++) {
6802 sdtr_speed = adv_dvc_varp->sdtr_speed1;
6803 } else if (i == 4) {
6804 sdtr_speed = adv_dvc_varp->sdtr_speed2;
6805 } else if (i == 8) {
6806 sdtr_speed = adv_dvc_varp->sdtr_speed3;
6807 } else if (i == 12) {
6808 sdtr_speed = adv_dvc_varp->sdtr_speed4;
6810 switch (sdtr_speed & ADV_MAX_TID) {
6833 len = asc_prt_line(cp, leftlen, "%X:%s ", i, speed_str);
6836 len = asc_prt_line(cp, leftlen, "\n ");
6841 len = asc_prt_line(cp, leftlen, "\n");
6849 * asc_prt_driver_conf()
6851 * Note: no single line should be greater than ASC_PRTLINE_SIZE,
6852 * cf. asc_prt_line().
6854 * Return the number of characters copied into 'cp'. No more than
6855 * 'cplen' characters will be copied to 'cp'.
6857 static int asc_prt_driver_conf(struct Scsi_Host *shost, char *cp, int cplen)
6859 asc_board_t *boardp;
6865 boardp = ASC_BOARDP(shost);
6870 len = asc_prt_line(cp, leftlen,
6871 "\nLinux Driver Configuration and Information for AdvanSys SCSI Host %d:\n",
6875 len = asc_prt_line(cp, leftlen,
6876 " host_busy %u, last_reset %u, max_id %u, max_lun %u, max_channel %u\n",
6877 shost->host_busy, shost->last_reset, shost->max_id,
6878 shost->max_lun, shost->max_channel);
6881 len = asc_prt_line(cp, leftlen,
6882 " unique_id %d, can_queue %d, this_id %d, sg_tablesize %u, cmd_per_lun %u\n",
6883 shost->unique_id, shost->can_queue, shost->this_id,
6884 shost->sg_tablesize, shost->cmd_per_lun);
6887 len = asc_prt_line(cp, leftlen,
6888 " unchecked_isa_dma %d, use_clustering %d\n",
6889 shost->unchecked_isa_dma, shost->use_clustering);
6892 len = asc_prt_line(cp, leftlen,
6893 " flags 0x%x, last_reset 0x%x, jiffies 0x%x, asc_n_io_port 0x%x\n",
6894 boardp->flags, boardp->last_reset, jiffies,
6895 boardp->asc_n_io_port);
6898 /* 'shost->n_io_port' may be truncated because it is only one byte. */
6899 len = asc_prt_line(cp, leftlen,
6900 " io_port 0x%x, n_io_port 0x%x\n",
6901 shost->io_port, shost->n_io_port);
6904 if (ASC_NARROW_BOARD(boardp)) {
6905 chip_scsi_id = boardp->dvc_cfg.asc_dvc_cfg.chip_scsi_id;
6907 chip_scsi_id = boardp->dvc_var.adv_dvc_var.chip_scsi_id;
6914 * asc_prt_asc_board_info()
6916 * Print dynamic board configuration information.
6918 * Note: no single line should be greater than ASC_PRTLINE_SIZE,
6919 * cf. asc_prt_line().
6921 * Return the number of characters copied into 'cp'. No more than
6922 * 'cplen' characters will be copied to 'cp'.
6924 static int asc_prt_asc_board_info(struct Scsi_Host *shost, char *cp, int cplen)
6926 asc_board_t *boardp;
6934 int renegotiate = 0;
6936 boardp = ASC_BOARDP(shost);
6937 v = &boardp->dvc_var.asc_dvc_var;
6938 c = &boardp->dvc_cfg.asc_dvc_cfg;
6939 chip_scsi_id = c->chip_scsi_id;
6944 len = asc_prt_line(cp, leftlen,
6945 "\nAsc Library Configuration and Statistics for AdvanSys SCSI Host %d:\n",
6949 len = asc_prt_line(cp, leftlen,
6950 " chip_version %u, lib_version 0x%x, lib_serial_no %u, mcode_date 0x%x\n",
6951 c->chip_version, c->lib_version, c->lib_serial_no,
6955 len = asc_prt_line(cp, leftlen,
6956 " mcode_version 0x%x, err_code %u\n",
6957 c->mcode_version, v->err_code);
6960 /* Current number of commands waiting for the host. */
6961 len = asc_prt_line(cp, leftlen,
6962 " Total Command Pending: %d\n", v->cur_total_qng);
6965 len = asc_prt_line(cp, leftlen, " Command Queuing:");
6967 for (i = 0; i <= ASC_MAX_TID; i++) {
6968 if ((chip_scsi_id == i) ||
6969 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
6972 len = asc_prt_line(cp, leftlen, " %X:%c",
6975 use_tagged_qng & ADV_TID_TO_TIDMASK(i)) ?
6979 len = asc_prt_line(cp, leftlen, "\n");
6982 /* Current number of commands waiting for a device. */
6983 len = asc_prt_line(cp, leftlen, " Command Queue Pending:");
6985 for (i = 0; i <= ASC_MAX_TID; i++) {
6986 if ((chip_scsi_id == i) ||
6987 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
6990 len = asc_prt_line(cp, leftlen, " %X:%u", i, v->cur_dvc_qng[i]);
6993 len = asc_prt_line(cp, leftlen, "\n");
6996 /* Current limit on number of commands that can be sent to a device. */
6997 len = asc_prt_line(cp, leftlen, " Command Queue Limit:");
6999 for (i = 0; i <= ASC_MAX_TID; i++) {
7000 if ((chip_scsi_id == i) ||
7001 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
7004 len = asc_prt_line(cp, leftlen, " %X:%u", i, v->max_dvc_qng[i]);
7007 len = asc_prt_line(cp, leftlen, "\n");
7010 /* Indicate whether the device has returned queue full status. */
7011 len = asc_prt_line(cp, leftlen, " Command Queue Full:");
7013 for (i = 0; i <= ASC_MAX_TID; i++) {
7014 if ((chip_scsi_id == i) ||
7015 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
7018 if (boardp->queue_full & ADV_TID_TO_TIDMASK(i)) {
7019 len = asc_prt_line(cp, leftlen, " %X:Y-%d",
7020 i, boardp->queue_full_cnt[i]);
7022 len = asc_prt_line(cp, leftlen, " %X:N", i);
7026 len = asc_prt_line(cp, leftlen, "\n");
7029 len = asc_prt_line(cp, leftlen, " Synchronous Transfer:");
7031 for (i = 0; i <= ASC_MAX_TID; i++) {
7032 if ((chip_scsi_id == i) ||
7033 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
7036 len = asc_prt_line(cp, leftlen, " %X:%c",
7039 sdtr_done & ADV_TID_TO_TIDMASK(i)) ? 'Y' :
7043 len = asc_prt_line(cp, leftlen, "\n");
7046 for (i = 0; i <= ASC_MAX_TID; i++) {
7047 uchar syn_period_ix;
7049 if ((chip_scsi_id == i) ||
7050 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0) ||
7051 ((v->init_sdtr & ADV_TID_TO_TIDMASK(i)) == 0)) {
7055 len = asc_prt_line(cp, leftlen, " %X:", i);
7058 if ((boardp->sdtr_data[i] & ASC_SYN_MAX_OFFSET) == 0) {
7059 len = asc_prt_line(cp, leftlen, " Asynchronous");
7063 (boardp->sdtr_data[i] >> 4) & (v->max_sdtr_index -
7066 len = asc_prt_line(cp, leftlen,
7067 " Transfer Period Factor: %d (%d.%d Mhz),",
7068 v->sdtr_period_tbl[syn_period_ix],
7070 v->sdtr_period_tbl[syn_period_ix],
7077 len = asc_prt_line(cp, leftlen, " REQ/ACK Offset: %d",
7079 sdtr_data[i] & ASC_SYN_MAX_OFFSET);
7083 if ((v->sdtr_done & ADV_TID_TO_TIDMASK(i)) == 0) {
7084 len = asc_prt_line(cp, leftlen, "*\n");
7087 len = asc_prt_line(cp, leftlen, "\n");
7093 len = asc_prt_line(cp, leftlen,
7094 " * = Re-negotiation pending before next command.\n");
7102 * asc_prt_adv_board_info()
7104 * Print dynamic board configuration information.
7106 * Note: no single line should be greater than ASC_PRTLINE_SIZE,
7107 * cf. asc_prt_line().
7109 * Return the number of characters copied into 'cp'. No more than
7110 * 'cplen' characters will be copied to 'cp'.
7112 static int asc_prt_adv_board_info(struct Scsi_Host *shost, char *cp, int cplen)
7114 asc_board_t *boardp;
7121 AdvPortAddr iop_base;
7122 ushort chip_scsi_id;
7126 ushort sdtr_able, wdtr_able;
7127 ushort wdtr_done, sdtr_done;
7129 int renegotiate = 0;
7131 boardp = ASC_BOARDP(shost);
7132 v = &boardp->dvc_var.adv_dvc_var;
7133 c = &boardp->dvc_cfg.adv_dvc_cfg;
7134 iop_base = v->iop_base;
7135 chip_scsi_id = v->chip_scsi_id;
7140 len = asc_prt_line(cp, leftlen,
7141 "\nAdv Library Configuration and Statistics for AdvanSys SCSI Host %d:\n",
7145 len = asc_prt_line(cp, leftlen,
7146 " iop_base 0x%lx, cable_detect: %X, err_code %u\n",
7148 AdvReadWordRegister(iop_base,
7149 IOPW_SCSI_CFG1) & CABLE_DETECT,
7153 len = asc_prt_line(cp, leftlen,
7154 " chip_version %u, lib_version 0x%x, mcode_date 0x%x, mcode_version 0x%x\n",
7155 c->chip_version, c->lib_version, c->mcode_date,
7159 AdvReadWordLram(iop_base, ASC_MC_TAGQNG_ABLE, tagqng_able);
7160 len = asc_prt_line(cp, leftlen, " Queuing Enabled:");
7162 for (i = 0; i <= ADV_MAX_TID; i++) {
7163 if ((chip_scsi_id == i) ||
7164 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
7168 len = asc_prt_line(cp, leftlen, " %X:%c",
7170 (tagqng_able & ADV_TID_TO_TIDMASK(i)) ? 'Y' :
7174 len = asc_prt_line(cp, leftlen, "\n");
7177 len = asc_prt_line(cp, leftlen, " Queue Limit:");
7179 for (i = 0; i <= ADV_MAX_TID; i++) {
7180 if ((chip_scsi_id == i) ||
7181 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
7185 AdvReadByteLram(iop_base, ASC_MC_NUMBER_OF_MAX_CMD + i,
7188 len = asc_prt_line(cp, leftlen, " %X:%d", i, lrambyte);
7191 len = asc_prt_line(cp, leftlen, "\n");
7194 len = asc_prt_line(cp, leftlen, " Command Pending:");
7196 for (i = 0; i <= ADV_MAX_TID; i++) {
7197 if ((chip_scsi_id == i) ||
7198 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
7202 AdvReadByteLram(iop_base, ASC_MC_NUMBER_OF_QUEUED_CMD + i,
7205 len = asc_prt_line(cp, leftlen, " %X:%d", i, lrambyte);
7208 len = asc_prt_line(cp, leftlen, "\n");
7211 AdvReadWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able);
7212 len = asc_prt_line(cp, leftlen, " Wide Enabled:");
7214 for (i = 0; i <= ADV_MAX_TID; i++) {
7215 if ((chip_scsi_id == i) ||
7216 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
7220 len = asc_prt_line(cp, leftlen, " %X:%c",
7222 (wdtr_able & ADV_TID_TO_TIDMASK(i)) ? 'Y' :
7226 len = asc_prt_line(cp, leftlen, "\n");
7229 AdvReadWordLram(iop_base, ASC_MC_WDTR_DONE, wdtr_done);
7230 len = asc_prt_line(cp, leftlen, " Transfer Bit Width:");
7232 for (i = 0; i <= ADV_MAX_TID; i++) {
7233 if ((chip_scsi_id == i) ||
7234 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
7238 AdvReadWordLram(iop_base,
7239 ASC_MC_DEVICE_HSHK_CFG_TABLE + (2 * i),
7242 len = asc_prt_line(cp, leftlen, " %X:%d",
7243 i, (lramword & 0x8000) ? 16 : 8);
7246 if ((wdtr_able & ADV_TID_TO_TIDMASK(i)) &&
7247 (wdtr_done & ADV_TID_TO_TIDMASK(i)) == 0) {
7248 len = asc_prt_line(cp, leftlen, "*");
7253 len = asc_prt_line(cp, leftlen, "\n");
7256 AdvReadWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
7257 len = asc_prt_line(cp, leftlen, " Synchronous Enabled:");
7259 for (i = 0; i <= ADV_MAX_TID; i++) {
7260 if ((chip_scsi_id == i) ||
7261 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
7265 len = asc_prt_line(cp, leftlen, " %X:%c",
7267 (sdtr_able & ADV_TID_TO_TIDMASK(i)) ? 'Y' :
7271 len = asc_prt_line(cp, leftlen, "\n");
7274 AdvReadWordLram(iop_base, ASC_MC_SDTR_DONE, sdtr_done);
7275 for (i = 0; i <= ADV_MAX_TID; i++) {
7277 AdvReadWordLram(iop_base,
7278 ASC_MC_DEVICE_HSHK_CFG_TABLE + (2 * i),
7280 lramword &= ~0x8000;
7282 if ((chip_scsi_id == i) ||
7283 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0) ||
7284 ((sdtr_able & ADV_TID_TO_TIDMASK(i)) == 0)) {
7288 len = asc_prt_line(cp, leftlen, " %X:", i);
7291 if ((lramword & 0x1F) == 0) { /* Check for REQ/ACK Offset 0. */
7292 len = asc_prt_line(cp, leftlen, " Asynchronous");
7296 asc_prt_line(cp, leftlen,
7297 " Transfer Period Factor: ");
7300 if ((lramword & 0x1F00) == 0x1100) { /* 80 Mhz */
7302 asc_prt_line(cp, leftlen, "9 (80.0 Mhz),");
7304 } else if ((lramword & 0x1F00) == 0x1000) { /* 40 Mhz */
7306 asc_prt_line(cp, leftlen, "10 (40.0 Mhz),");
7308 } else { /* 20 Mhz or below. */
7310 period = (((lramword >> 8) * 25) + 50) / 4;
7312 if (period == 0) { /* Should never happen. */
7314 asc_prt_line(cp, leftlen,
7318 len = asc_prt_line(cp, leftlen,
7320 period, 250 / period,
7327 len = asc_prt_line(cp, leftlen, " REQ/ACK Offset: %d",
7332 if ((sdtr_done & ADV_TID_TO_TIDMASK(i)) == 0) {
7333 len = asc_prt_line(cp, leftlen, "*\n");
7336 len = asc_prt_line(cp, leftlen, "\n");
7342 len = asc_prt_line(cp, leftlen,
7343 " * = Re-negotiation pending before next command.\n");
7353 * Copy proc information to a read buffer taking into account the current
7354 * read offset in the file and the remaining space in the read buffer.
7357 asc_proc_copy(off_t advoffset, off_t offset, char *curbuf, int leftlen,
7358 char *cp, int cplen)
7362 ASC_DBG3(2, "asc_proc_copy: offset %d, advoffset %d, cplen %d\n",
7363 (unsigned)offset, (unsigned)advoffset, cplen);
7364 if (offset <= advoffset) {
7365 /* Read offset below current offset, copy everything. */
7366 cnt = min(cplen, leftlen);
7367 ASC_DBG3(2, "asc_proc_copy: curbuf 0x%lx, cp 0x%lx, cnt %d\n",
7368 (ulong)curbuf, (ulong)cp, cnt);
7369 memcpy(curbuf, cp, cnt);
7370 } else if (offset < advoffset + cplen) {
7371 /* Read offset within current range, partial copy. */
7372 cnt = (advoffset + cplen) - offset;
7373 cp = (cp + cplen) - cnt;
7374 cnt = min(cnt, leftlen);
7375 ASC_DBG3(2, "asc_proc_copy: curbuf 0x%lx, cp 0x%lx, cnt %d\n",
7376 (ulong)curbuf, (ulong)cp, cnt);
7377 memcpy(curbuf, cp, cnt);
7385 * If 'cp' is NULL print to the console, otherwise print to a buffer.
7387 * Return 0 if printing to the console, otherwise return the number of
7388 * bytes written to the buffer.
7390 * Note: If any single line is greater than ASC_PRTLINE_SIZE bytes the stack
7391 * will be corrupted. 's[]' is defined to be ASC_PRTLINE_SIZE bytes.
7393 static int asc_prt_line(char *buf, int buflen, char *fmt, ...)
7397 char s[ASC_PRTLINE_SIZE];
7399 va_start(args, fmt);
7400 ret = vsprintf(s, fmt, args);
7401 ASC_ASSERT(ret < ASC_PRTLINE_SIZE);
7406 ret = min(buflen, ret);
7407 memcpy(buf, s, ret);
7412 #endif /* CONFIG_PROC_FS */
7415 * --- Functions Required by the Asc Library
7419 * Delay for 'n' milliseconds. Don't use the 'jiffies'
7420 * global variable which is incremented once every 5 ms
7421 * from a timer interrupt, because this function may be
7422 * called when interrupts are disabled.
7424 static void DvcSleepMilliSecond(ADV_DCNT n)
7426 ASC_DBG1(4, "DvcSleepMilliSecond: %lu\n", (ulong)n);
7431 * Currently and inline noop but leave as a placeholder.
7432 * Leave DvcEnterCritical() as a noop placeholder.
7434 static inline ulong DvcEnterCritical(void)
7440 * Critical sections are all protected by the board spinlock.
7441 * Leave DvcLeaveCritical() as a noop placeholder.
7443 static inline void DvcLeaveCritical(ulong flags)
7450 * DvcPutScsiQ(PortAddr iop_base, ushort s_addr, uchar *outbuf, int words)
7452 * Calling/Exit State:
7456 * Output an ASC_SCSI_Q structure to the chip
7459 DvcPutScsiQ(PortAddr iop_base, ushort s_addr, uchar *outbuf, int words)
7463 ASC_DBG_PRT_HEX(2, "DvcPutScsiQ", outbuf, 2 * words);
7464 AscSetChipLramAddr(iop_base, s_addr);
7465 for (i = 0; i < 2 * words; i += 2) {
7466 if (i == 4 || i == 20) {
7469 outpw(iop_base + IOP_RAM_DATA,
7470 ((ushort)outbuf[i + 1] << 8) | outbuf[i]);
7476 * DvcGetQinfo(PortAddr iop_base, ushort s_addr, uchar *inbuf, int words)
7478 * Calling/Exit State:
7482 * Input an ASC_QDONE_INFO structure from the chip
7485 DvcGetQinfo(PortAddr iop_base, ushort s_addr, uchar *inbuf, int words)
7490 AscSetChipLramAddr(iop_base, s_addr);
7491 for (i = 0; i < 2 * words; i += 2) {
7495 word = inpw(iop_base + IOP_RAM_DATA);
7496 inbuf[i] = word & 0xff;
7497 inbuf[i + 1] = (word >> 8) & 0xff;
7499 ASC_DBG_PRT_HEX(2, "DvcGetQinfo", inbuf, 2 * words);
7503 * Read a PCI configuration byte.
7505 static uchar __init DvcReadPCIConfigByte(ASC_DVC_VAR *asc_dvc, ushort offset)
7509 pci_read_config_byte(to_pci_dev(asc_dvc->cfg->dev), offset, &byte_data);
7511 #else /* !defined(CONFIG_PCI) */
7513 #endif /* !defined(CONFIG_PCI) */
7517 * Write a PCI configuration byte.
7520 DvcWritePCIConfigByte(ASC_DVC_VAR *asc_dvc, ushort offset, uchar byte_data)
7523 pci_write_config_byte(to_pci_dev(asc_dvc->cfg->dev), offset, byte_data);
7524 #endif /* CONFIG_PCI */
7528 * Return the BIOS address of the adapter at the specified
7529 * I/O port and with the specified bus type.
7531 static ushort __init AscGetChipBiosAddress(PortAddr iop_base, ushort bus_type)
7537 * The PCI BIOS is re-located by the motherboard BIOS. Because
7538 * of this the driver can not determine where a PCI BIOS is
7539 * loaded and executes.
7541 if (bus_type & ASC_IS_PCI) {
7545 if ((bus_type & ASC_IS_EISA) != 0) {
7546 cfg_lsw = AscGetEisaChipCfg(iop_base);
7548 bios_addr = (ushort)(ASC_BIOS_MIN_ADDR +
7549 (cfg_lsw * ASC_BIOS_BANK_SIZE));
7552 #endif /* CONFIG_ISA */
7554 cfg_lsw = AscGetChipCfgLsw(iop_base);
7557 * ISA PnP uses the top bit as the 32K BIOS flag
7559 if (bus_type == ASC_IS_ISAPNP) {
7563 bios_addr = (ushort)(((cfg_lsw >> 12) * ASC_BIOS_BANK_SIZE) +
7569 * --- Functions Required by the Adv Library
7575 * Return the physical address of 'vaddr' and set '*lenp' to the
7576 * number of physically contiguous bytes that follow 'vaddr'.
7577 * 'flag' indicates the type of structure whose physical address
7578 * is being translated.
7580 * Note: Because Linux currently doesn't page the kernel and all
7581 * kernel buffers are physically contiguous, leave '*lenp' unchanged.
7584 DvcGetPhyAddr(ADV_DVC_VAR *asc_dvc, ADV_SCSI_REQ_Q *scsiq,
7585 uchar *vaddr, ADV_SDCNT *lenp, int flag)
7589 paddr = virt_to_bus(vaddr);
7592 "DvcGetPhyAddr: vaddr 0x%lx, lenp 0x%lx *lenp %lu, paddr 0x%lx\n",
7593 (ulong)vaddr, (ulong)lenp, (ulong)*((ulong *)lenp),
7600 * Read a PCI configuration byte.
7602 static uchar __init DvcAdvReadPCIConfigByte(ADV_DVC_VAR *asc_dvc, ushort offset)
7606 pci_read_config_byte(to_pci_dev(asc_dvc->cfg->dev), offset, &byte_data);
7608 #else /* CONFIG_PCI */
7610 #endif /* CONFIG_PCI */
7614 * Write a PCI configuration byte.
7617 DvcAdvWritePCIConfigByte(ADV_DVC_VAR *asc_dvc, ushort offset, uchar byte_data)
7620 pci_write_config_byte(to_pci_dev(asc_dvc->cfg->dev), offset, byte_data);
7621 #else /* CONFIG_PCI */
7623 #endif /* CONFIG_PCI */
7627 * --- Tracing and Debugging Functions
7630 #ifdef ADVANSYS_STATS
7631 #ifdef CONFIG_PROC_FS
7633 * asc_prt_board_stats()
7635 * Note: no single line should be greater than ASC_PRTLINE_SIZE,
7636 * cf. asc_prt_line().
7638 * Return the number of characters copied into 'cp'. No more than
7639 * 'cplen' characters will be copied to 'cp'.
7641 static int asc_prt_board_stats(struct Scsi_Host *shost, char *cp, int cplen)
7646 struct asc_stats *s;
7647 asc_board_t *boardp;
7652 boardp = ASC_BOARDP(shost);
7653 s = &boardp->asc_stats;
7655 len = asc_prt_line(cp, leftlen,
7656 "\nLinux Driver Statistics for AdvanSys SCSI Host %d:\n",
7660 len = asc_prt_line(cp, leftlen,
7661 " queuecommand %lu, reset %lu, biosparam %lu, interrupt %lu\n",
7662 s->queuecommand, s->reset, s->biosparam,
7666 len = asc_prt_line(cp, leftlen,
7667 " callback %lu, done %lu, build_error %lu, build_noreq %lu, build_nosg %lu\n",
7668 s->callback, s->done, s->build_error,
7669 s->adv_build_noreq, s->adv_build_nosg);
7672 len = asc_prt_line(cp, leftlen,
7673 " exe_noerror %lu, exe_busy %lu, exe_error %lu, exe_unknown %lu\n",
7674 s->exe_noerror, s->exe_busy, s->exe_error,
7679 * Display data transfer statistics.
7681 if (s->cont_cnt > 0) {
7682 len = asc_prt_line(cp, leftlen, " cont_cnt %lu, ", s->cont_cnt);
7685 len = asc_prt_line(cp, leftlen, "cont_xfer %lu.%01lu kb ",
7687 ASC_TENTHS(s->cont_xfer, 2));
7690 /* Contiguous transfer average size */
7691 len = asc_prt_line(cp, leftlen, "avg_xfer %lu.%01lu kb\n",
7692 (s->cont_xfer / 2) / s->cont_cnt,
7693 ASC_TENTHS((s->cont_xfer / 2), s->cont_cnt));
7697 if (s->sg_cnt > 0) {
7699 len = asc_prt_line(cp, leftlen, " sg_cnt %lu, sg_elem %lu, ",
7700 s->sg_cnt, s->sg_elem);
7703 len = asc_prt_line(cp, leftlen, "sg_xfer %lu.%01lu kb\n",
7704 s->sg_xfer / 2, ASC_TENTHS(s->sg_xfer, 2));
7707 /* Scatter gather transfer statistics */
7708 len = asc_prt_line(cp, leftlen, " avg_num_elem %lu.%01lu, ",
7709 s->sg_elem / s->sg_cnt,
7710 ASC_TENTHS(s->sg_elem, s->sg_cnt));
7713 len = asc_prt_line(cp, leftlen, "avg_elem_size %lu.%01lu kb, ",
7714 (s->sg_xfer / 2) / s->sg_elem,
7715 ASC_TENTHS((s->sg_xfer / 2), s->sg_elem));
7718 len = asc_prt_line(cp, leftlen, "avg_xfer_size %lu.%01lu kb\n",
7719 (s->sg_xfer / 2) / s->sg_cnt,
7720 ASC_TENTHS((s->sg_xfer / 2), s->sg_cnt));
7725 * Display request queuing statistics.
7727 len = asc_prt_line(cp, leftlen,
7728 " Active and Waiting Request Queues (Time Unit: %d HZ):\n",
7736 * asc_prt_target_stats()
7738 * Note: no single line should be greater than ASC_PRTLINE_SIZE,
7739 * cf. asc_prt_line().
7741 * This is separated from asc_prt_board_stats because a full set
7742 * of targets will overflow ASC_PRTBUF_SIZE.
7744 * Return the number of characters copied into 'cp'. No more than
7745 * 'cplen' characters will be copied to 'cp'.
7748 asc_prt_target_stats(struct Scsi_Host *shost, int tgt_id, char *cp, int cplen)
7753 struct asc_stats *s;
7754 ushort chip_scsi_id;
7755 asc_board_t *boardp;
7756 asc_queue_t *active;
7757 asc_queue_t *waiting;
7762 boardp = ASC_BOARDP(shost);
7763 s = &boardp->asc_stats;
7765 active = &ASC_BOARDP(shost)->active;
7766 waiting = &ASC_BOARDP(shost)->waiting;
7768 if (ASC_NARROW_BOARD(boardp)) {
7769 chip_scsi_id = boardp->dvc_cfg.asc_dvc_cfg.chip_scsi_id;
7771 chip_scsi_id = boardp->dvc_var.adv_dvc_var.chip_scsi_id;
7774 if ((chip_scsi_id == tgt_id) ||
7775 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(tgt_id)) == 0)) {
7780 if (active->q_tot_cnt[tgt_id] > 0
7781 || waiting->q_tot_cnt[tgt_id] > 0) {
7782 len = asc_prt_line(cp, leftlen, " target %d\n", tgt_id);
7785 len = asc_prt_line(cp, leftlen,
7786 " active: cnt [cur %d, max %d, tot %u], time [min %d, max %d, avg %lu.%01lu]\n",
7787 active->q_cur_cnt[tgt_id],
7788 active->q_max_cnt[tgt_id],
7789 active->q_tot_cnt[tgt_id],
7790 active->q_min_tim[tgt_id],
7791 active->q_max_tim[tgt_id],
7792 (active->q_tot_cnt[tgt_id] ==
7797 (active->q_tot_cnt[tgt_id] ==
7798 0) ? 0 : ASC_TENTHS(active->
7806 len = asc_prt_line(cp, leftlen,
7807 " waiting: cnt [cur %d, max %d, tot %u], time [min %u, max %u, avg %lu.%01lu]\n",
7808 waiting->q_cur_cnt[tgt_id],
7809 waiting->q_max_cnt[tgt_id],
7810 waiting->q_tot_cnt[tgt_id],
7811 waiting->q_min_tim[tgt_id],
7812 waiting->q_max_tim[tgt_id],
7813 (waiting->q_tot_cnt[tgt_id] ==
7818 (waiting->q_tot_cnt[tgt_id] ==
7819 0) ? 0 : ASC_TENTHS(waiting->
7831 #endif /* CONFIG_PROC_FS */
7832 #endif /* ADVANSYS_STATS */
7834 #ifdef ADVANSYS_DEBUG
7836 * asc_prt_scsi_host()
7838 static void asc_prt_scsi_host(struct Scsi_Host *s)
7840 asc_board_t *boardp;
7842 boardp = ASC_BOARDP(s);
7844 printk("Scsi_Host at addr 0x%lx\n", (ulong)s);
7845 printk(" host_busy %u, host_no %d, last_reset %d,\n",
7846 s->host_busy, s->host_no, (unsigned)s->last_reset);
7848 printk(" base 0x%lx, io_port 0x%lx, n_io_port %u, irq 0x%x,\n",
7849 (ulong)s->base, (ulong)s->io_port, s->n_io_port, s->irq);
7851 printk(" dma_channel %d, this_id %d, can_queue %d,\n",
7852 s->dma_channel, s->this_id, s->can_queue);
7854 printk(" cmd_per_lun %d, sg_tablesize %d, unchecked_isa_dma %d\n",
7855 s->cmd_per_lun, s->sg_tablesize, s->unchecked_isa_dma);
7857 if (ASC_NARROW_BOARD(boardp)) {
7858 asc_prt_asc_dvc_var(&ASC_BOARDP(s)->dvc_var.asc_dvc_var);
7859 asc_prt_asc_dvc_cfg(&ASC_BOARDP(s)->dvc_cfg.asc_dvc_cfg);
7861 asc_prt_adv_dvc_var(&ASC_BOARDP(s)->dvc_var.adv_dvc_var);
7862 asc_prt_adv_dvc_cfg(&ASC_BOARDP(s)->dvc_cfg.adv_dvc_cfg);
7867 * asc_prt_scsi_cmnd()
7869 static void asc_prt_scsi_cmnd(struct scsi_cmnd *s)
7871 printk("struct scsi_cmnd at addr 0x%lx\n", (ulong)s);
7873 printk(" host 0x%lx, device 0x%lx, target %u, lun %u, channel %u,\n",
7874 (ulong)s->device->host, (ulong)s->device, s->device->id,
7875 s->device->lun, s->device->channel);
7877 asc_prt_hex(" CDB", s->cmnd, s->cmd_len);
7879 printk("sc_data_direction %u, resid %d\n",
7880 s->sc_data_direction, s->resid);
7882 printk(" use_sg %u, sglist_len %u\n", s->use_sg, s->sglist_len);
7884 printk(" serial_number 0x%x, retries %d, allowed %d\n",
7885 (unsigned)s->serial_number, s->retries, s->allowed);
7887 printk(" timeout_per_command %d\n", s->timeout_per_command);
7890 (" scsi_done 0x%lx, done 0x%lx, host_scribble 0x%lx, result 0x%x\n",
7891 (ulong)s->scsi_done, (ulong)s->done, (ulong)s->host_scribble,
7894 printk(" tag %u, pid %u\n", (unsigned)s->tag, (unsigned)s->pid);
7898 * asc_prt_asc_dvc_var()
7900 static void asc_prt_asc_dvc_var(ASC_DVC_VAR *h)
7902 printk("ASC_DVC_VAR at addr 0x%lx\n", (ulong)h);
7905 (" iop_base 0x%x, err_code 0x%x, dvc_cntl 0x%x, bug_fix_cntl %d,\n",
7906 h->iop_base, h->err_code, h->dvc_cntl, h->bug_fix_cntl);
7909 (" bus_type %d, isr_callback 0x%lx, exe_callback 0x%lx, init_sdtr 0x%x,\n",
7910 h->bus_type, (ulong)h->isr_callback, (ulong)h->exe_callback,
7911 (unsigned)h->init_sdtr);
7914 (" sdtr_done 0x%x, use_tagged_qng 0x%x, unit_not_ready 0x%x, chip_no 0x%x,\n",
7915 (unsigned)h->sdtr_done, (unsigned)h->use_tagged_qng,
7916 (unsigned)h->unit_not_ready, (unsigned)h->chip_no);
7919 (" queue_full_or_busy 0x%x, start_motor 0x%x, scsi_reset_wait %u,\n",
7920 (unsigned)h->queue_full_or_busy, (unsigned)h->start_motor,
7921 (unsigned)h->scsi_reset_wait);
7924 (" is_in_int %u, max_total_qng %u, cur_total_qng %u, in_critical_cnt %u,\n",
7925 (unsigned)h->is_in_int, (unsigned)h->max_total_qng,
7926 (unsigned)h->cur_total_qng, (unsigned)h->in_critical_cnt);
7929 (" last_q_shortage %u, init_state 0x%x, no_scam 0x%x, pci_fix_asyn_xfer 0x%x,\n",
7930 (unsigned)h->last_q_shortage, (unsigned)h->init_state,
7931 (unsigned)h->no_scam, (unsigned)h->pci_fix_asyn_xfer);
7933 printk(" cfg 0x%lx, irq_no 0x%x\n", (ulong)h->cfg, (unsigned)h->irq_no);
7937 * asc_prt_asc_dvc_cfg()
7939 static void asc_prt_asc_dvc_cfg(ASC_DVC_CFG *h)
7941 printk("ASC_DVC_CFG at addr 0x%lx\n", (ulong)h);
7943 printk(" can_tagged_qng 0x%x, cmd_qng_enabled 0x%x,\n",
7944 h->can_tagged_qng, h->cmd_qng_enabled);
7945 printk(" disc_enable 0x%x, sdtr_enable 0x%x,\n",
7946 h->disc_enable, h->sdtr_enable);
7949 (" chip_scsi_id %d, isa_dma_speed %d, isa_dma_channel %d, chip_version %d,\n",
7950 h->chip_scsi_id, h->isa_dma_speed, h->isa_dma_channel,
7954 (" pci_device_id %d, lib_serial_no %u, lib_version %u, mcode_date 0x%x,\n",
7955 to_pci_dev(h->dev)->device, h->lib_serial_no, h->lib_version,
7958 printk(" mcode_version %d, overrun_buf 0x%lx\n",
7959 h->mcode_version, (ulong)h->overrun_buf);
7963 * asc_prt_asc_scsi_q()
7965 static void asc_prt_asc_scsi_q(ASC_SCSI_Q *q)
7970 printk("ASC_SCSI_Q at addr 0x%lx\n", (ulong)q);
7973 (" target_ix 0x%x, target_lun %u, srb_ptr 0x%lx, tag_code 0x%x,\n",
7974 q->q2.target_ix, q->q1.target_lun, (ulong)q->q2.srb_ptr,
7978 (" data_addr 0x%lx, data_cnt %lu, sense_addr 0x%lx, sense_len %u,\n",
7979 (ulong)le32_to_cpu(q->q1.data_addr),
7980 (ulong)le32_to_cpu(q->q1.data_cnt),
7981 (ulong)le32_to_cpu(q->q1.sense_addr), q->q1.sense_len);
7983 printk(" cdbptr 0x%lx, cdb_len %u, sg_head 0x%lx, sg_queue_cnt %u\n",
7984 (ulong)q->cdbptr, q->q2.cdb_len,
7985 (ulong)q->sg_head, q->q1.sg_queue_cnt);
7989 printk("ASC_SG_HEAD at addr 0x%lx\n", (ulong)sgp);
7990 printk(" entry_cnt %u, queue_cnt %u\n", sgp->entry_cnt,
7992 for (i = 0; i < sgp->entry_cnt; i++) {
7993 printk(" [%u]: addr 0x%lx, bytes %lu\n",
7994 i, (ulong)le32_to_cpu(sgp->sg_list[i].addr),
7995 (ulong)le32_to_cpu(sgp->sg_list[i].bytes));
8002 * asc_prt_asc_qdone_info()
8004 static void asc_prt_asc_qdone_info(ASC_QDONE_INFO *q)
8006 printk("ASC_QDONE_INFO at addr 0x%lx\n", (ulong)q);
8007 printk(" srb_ptr 0x%lx, target_ix %u, cdb_len %u, tag_code %u,\n",
8008 (ulong)q->d2.srb_ptr, q->d2.target_ix, q->d2.cdb_len,
8011 (" done_stat 0x%x, host_stat 0x%x, scsi_stat 0x%x, scsi_msg 0x%x\n",
8012 q->d3.done_stat, q->d3.host_stat, q->d3.scsi_stat, q->d3.scsi_msg);
8016 * asc_prt_adv_dvc_var()
8018 * Display an ADV_DVC_VAR structure.
8020 static void asc_prt_adv_dvc_var(ADV_DVC_VAR *h)
8022 printk(" ADV_DVC_VAR at addr 0x%lx\n", (ulong)h);
8024 printk(" iop_base 0x%lx, err_code 0x%x, ultra_able 0x%x\n",
8025 (ulong)h->iop_base, h->err_code, (unsigned)h->ultra_able);
8027 printk(" isr_callback 0x%lx, sdtr_able 0x%x, wdtr_able 0x%x\n",
8028 (ulong)h->isr_callback, (unsigned)h->sdtr_able,
8029 (unsigned)h->wdtr_able);
8031 printk(" start_motor 0x%x, scsi_reset_wait 0x%x, irq_no 0x%x,\n",
8032 (unsigned)h->start_motor,
8033 (unsigned)h->scsi_reset_wait, (unsigned)h->irq_no);
8035 printk(" max_host_qng %u, max_dvc_qng %u, carr_freelist 0x%lxn\n",
8036 (unsigned)h->max_host_qng, (unsigned)h->max_dvc_qng,
8037 (ulong)h->carr_freelist);
8039 printk(" icq_sp 0x%lx, irq_sp 0x%lx\n",
8040 (ulong)h->icq_sp, (ulong)h->irq_sp);
8042 printk(" no_scam 0x%x, tagqng_able 0x%x\n",
8043 (unsigned)h->no_scam, (unsigned)h->tagqng_able);
8045 printk(" chip_scsi_id 0x%x, cfg 0x%lx\n",
8046 (unsigned)h->chip_scsi_id, (ulong)h->cfg);
8050 * asc_prt_adv_dvc_cfg()
8052 * Display an ADV_DVC_CFG structure.
8054 static void asc_prt_adv_dvc_cfg(ADV_DVC_CFG *h)
8056 printk(" ADV_DVC_CFG at addr 0x%lx\n", (ulong)h);
8058 printk(" disc_enable 0x%x, termination 0x%x\n",
8059 h->disc_enable, h->termination);
8061 printk(" chip_version 0x%x, mcode_date 0x%x\n",
8062 h->chip_version, h->mcode_date);
8064 printk(" mcode_version 0x%x, pci_device_id 0x%x, lib_version %u\n",
8065 h->mcode_version, to_pci_dev(h->dev)->device, h->lib_version);
8067 printk(" control_flag 0x%x, pci_slot_info 0x%x\n",
8068 h->control_flag, h->pci_slot_info);
8072 * asc_prt_adv_scsi_req_q()
8074 * Display an ADV_SCSI_REQ_Q structure.
8076 static void asc_prt_adv_scsi_req_q(ADV_SCSI_REQ_Q *q)
8079 struct asc_sg_block *sg_ptr;
8081 printk("ADV_SCSI_REQ_Q at addr 0x%lx\n", (ulong)q);
8083 printk(" target_id %u, target_lun %u, srb_ptr 0x%lx, a_flag 0x%x\n",
8084 q->target_id, q->target_lun, (ulong)q->srb_ptr, q->a_flag);
8086 printk(" cntl 0x%x, data_addr 0x%lx, vdata_addr 0x%lx\n",
8087 q->cntl, (ulong)le32_to_cpu(q->data_addr), (ulong)q->vdata_addr);
8089 printk(" data_cnt %lu, sense_addr 0x%lx, sense_len %u,\n",
8090 (ulong)le32_to_cpu(q->data_cnt),
8091 (ulong)le32_to_cpu(q->sense_addr), q->sense_len);
8094 (" cdb_len %u, done_status 0x%x, host_status 0x%x, scsi_status 0x%x\n",
8095 q->cdb_len, q->done_status, q->host_status, q->scsi_status);
8097 printk(" sg_working_ix 0x%x, target_cmd %u\n",
8098 q->sg_working_ix, q->target_cmd);
8100 printk(" scsiq_rptr 0x%lx, sg_real_addr 0x%lx, sg_list_ptr 0x%lx\n",
8101 (ulong)le32_to_cpu(q->scsiq_rptr),
8102 (ulong)le32_to_cpu(q->sg_real_addr), (ulong)q->sg_list_ptr);
8104 /* Display the request's ADV_SG_BLOCK structures. */
8105 if (q->sg_list_ptr != NULL) {
8109 * 'sg_ptr' is a physical address. Convert it to a virtual
8110 * address by indexing 'sg_blk_cnt' into the virtual address
8111 * array 'sg_list_ptr'.
8113 * XXX - Assumes all SG physical blocks are virtually contiguous.
8116 &(((ADV_SG_BLOCK *)(q->sg_list_ptr))[sg_blk_cnt]);
8117 asc_prt_adv_sgblock(sg_blk_cnt, sg_ptr);
8118 if (sg_ptr->sg_ptr == 0) {
8127 * asc_prt_adv_sgblock()
8129 * Display an ADV_SG_BLOCK structure.
8131 static void asc_prt_adv_sgblock(int sgblockno, ADV_SG_BLOCK *b)
8135 printk(" ASC_SG_BLOCK at addr 0x%lx (sgblockno %d)\n",
8136 (ulong)b, sgblockno);
8137 printk(" sg_cnt %u, sg_ptr 0x%lx\n",
8138 b->sg_cnt, (ulong)le32_to_cpu(b->sg_ptr));
8139 ASC_ASSERT(b->sg_cnt <= NO_OF_SG_PER_BLOCK);
8140 if (b->sg_ptr != 0) {
8141 ASC_ASSERT(b->sg_cnt == NO_OF_SG_PER_BLOCK);
8143 for (i = 0; i < b->sg_cnt; i++) {
8144 printk(" [%u]: sg_addr 0x%lx, sg_count 0x%lx\n",
8145 i, (ulong)b->sg_list[i].sg_addr,
8146 (ulong)b->sg_list[i].sg_count);
8153 * Print hexadecimal output in 4 byte groupings 32 bytes
8154 * or 8 double-words per line.
8156 static void asc_prt_hex(char *f, uchar *s, int l)
8163 printk("%s: (%d bytes)\n", f, l);
8165 for (i = 0; i < l; i += 32) {
8167 /* Display a maximum of 8 double-words per line. */
8168 if ((k = (l - i) / 4) >= 8) {
8175 for (j = 0; j < k; j++) {
8176 printk(" %2.2X%2.2X%2.2X%2.2X",
8177 (unsigned)s[i + (j * 4)],
8178 (unsigned)s[i + (j * 4) + 1],
8179 (unsigned)s[i + (j * 4) + 2],
8180 (unsigned)s[i + (j * 4) + 3]);
8188 printk(" %2.2X", (unsigned)s[i + (j * 4)]);
8191 printk(" %2.2X%2.2X",
8192 (unsigned)s[i + (j * 4)],
8193 (unsigned)s[i + (j * 4) + 1]);
8196 printk(" %2.2X%2.2X%2.2X",
8197 (unsigned)s[i + (j * 4) + 1],
8198 (unsigned)s[i + (j * 4) + 2],
8199 (unsigned)s[i + (j * 4) + 3]);
8206 #endif /* ADVANSYS_DEBUG */
8209 * --- Asc Library Functions
8212 static ushort __init AscGetEisaChipCfg(PortAddr iop_base)
8214 PortAddr eisa_cfg_iop;
8216 eisa_cfg_iop = (PortAddr) ASC_GET_EISA_SLOT(iop_base) |
8217 (PortAddr) (ASC_EISA_CFG_IOP_MASK);
8218 return (inpw(eisa_cfg_iop));
8221 static uchar __init AscSetChipScsiID(PortAddr iop_base, uchar new_host_id)
8225 if (AscGetChipScsiID(iop_base) == new_host_id) {
8226 return (new_host_id);
8228 cfg_lsw = AscGetChipCfgLsw(iop_base);
8230 cfg_lsw |= (ushort)((new_host_id & ASC_MAX_TID) << 8);
8231 AscSetChipCfgLsw(iop_base, cfg_lsw);
8232 return (AscGetChipScsiID(iop_base));
8235 static uchar __init AscGetChipScsiCtrl(PortAddr iop_base)
8239 AscSetBank(iop_base, 1);
8240 sc = inp(iop_base + IOP_REG_SC);
8241 AscSetBank(iop_base, 0);
8245 static uchar __init AscGetChipVersion(PortAddr iop_base, ushort bus_type)
8247 if ((bus_type & ASC_IS_EISA) != 0) {
8250 eisa_iop = (PortAddr) ASC_GET_EISA_SLOT(iop_base) |
8251 (PortAddr) ASC_EISA_REV_IOP_MASK;
8252 revision = inp(eisa_iop);
8253 return ((uchar)((ASC_CHIP_MIN_VER_EISA - 1) + revision));
8255 return (AscGetChipVerNo(iop_base));
8258 static ushort __init AscGetChipBusType(PortAddr iop_base)
8262 chip_ver = AscGetChipVerNo(iop_base);
8263 if ((chip_ver >= ASC_CHIP_MIN_VER_VL)
8264 && (chip_ver <= ASC_CHIP_MAX_VER_VL)
8266 if (((iop_base & 0x0C30) == 0x0C30)
8267 || ((iop_base & 0x0C50) == 0x0C50)
8269 return (ASC_IS_EISA);
8273 if ((chip_ver >= ASC_CHIP_MIN_VER_ISA) &&
8274 (chip_ver <= ASC_CHIP_MAX_VER_ISA)) {
8275 if (chip_ver >= ASC_CHIP_MIN_VER_ISA_PNP) {
8276 return (ASC_IS_ISAPNP);
8278 return (ASC_IS_ISA);
8279 } else if ((chip_ver >= ASC_CHIP_MIN_VER_PCI) &&
8280 (chip_ver <= ASC_CHIP_MAX_VER_PCI)) {
8281 return (ASC_IS_PCI);
8287 AscLoadMicroCode(PortAddr iop_base,
8288 ushort s_addr, uchar *mcode_buf, ushort mcode_size)
8291 ushort mcode_word_size;
8292 ushort mcode_chksum;
8294 /* Write the microcode buffer starting at LRAM address 0. */
8295 mcode_word_size = (ushort)(mcode_size >> 1);
8296 AscMemWordSetLram(iop_base, s_addr, 0, mcode_word_size);
8297 AscMemWordCopyPtrToLram(iop_base, s_addr, mcode_buf, mcode_word_size);
8299 chksum = AscMemSumLramWord(iop_base, s_addr, mcode_word_size);
8300 ASC_DBG1(1, "AscLoadMicroCode: chksum 0x%lx\n", (ulong)chksum);
8301 mcode_chksum = (ushort)AscMemSumLramWord(iop_base,
8302 (ushort)ASC_CODE_SEC_BEG,
8303 (ushort)((mcode_size -
8307 ASC_DBG1(1, "AscLoadMicroCode: mcode_chksum 0x%lx\n",
8308 (ulong)mcode_chksum);
8309 AscWriteLramWord(iop_base, ASCV_MCODE_CHKSUM_W, mcode_chksum);
8310 AscWriteLramWord(iop_base, ASCV_MCODE_SIZE_W, mcode_size);
8314 static int AscFindSignature(PortAddr iop_base)
8318 ASC_DBG2(1, "AscFindSignature: AscGetChipSignatureByte(0x%x) 0x%x\n",
8319 iop_base, AscGetChipSignatureByte(iop_base));
8320 if (AscGetChipSignatureByte(iop_base) == (uchar)ASC_1000_ID1B) {
8322 "AscFindSignature: AscGetChipSignatureWord(0x%x) 0x%x\n",
8323 iop_base, AscGetChipSignatureWord(iop_base));
8324 sig_word = AscGetChipSignatureWord(iop_base);
8325 if ((sig_word == (ushort)ASC_1000_ID0W) ||
8326 (sig_word == (ushort)ASC_1000_ID0W_FIX)) {
8333 static PortAddr _asc_def_iop_base[ASC_IOADR_TABLE_MAX_IX] __initdata = {
8334 0x100, ASC_IOADR_1, 0x120, ASC_IOADR_2, 0x140, ASC_IOADR_3, ASC_IOADR_4,
8335 ASC_IOADR_5, ASC_IOADR_6, ASC_IOADR_7, ASC_IOADR_8
8339 static uchar _isa_pnp_inited __initdata = 0;
8341 static PortAddr __init AscSearchIOPortAddr(PortAddr iop_beg, ushort bus_type)
8343 if (bus_type & ASC_IS_VL) {
8344 while ((iop_beg = AscSearchIOPortAddr11(iop_beg)) != 0) {
8345 if (AscGetChipVersion(iop_beg, bus_type) <=
8346 ASC_CHIP_MAX_VER_VL) {
8352 if (bus_type & ASC_IS_ISA) {
8353 if (_isa_pnp_inited == 0) {
8354 AscSetISAPNPWaitForKey();
8357 while ((iop_beg = AscSearchIOPortAddr11(iop_beg)) != 0) {
8358 if ((AscGetChipVersion(iop_beg, bus_type) &
8359 ASC_CHIP_VER_ISA_BIT) != 0) {
8365 if (bus_type & ASC_IS_EISA) {
8366 if ((iop_beg = AscSearchIOPortAddrEISA(iop_beg)) != 0) {
8374 static PortAddr __init AscSearchIOPortAddr11(PortAddr s_addr)
8379 for (i = 0; i < ASC_IOADR_TABLE_MAX_IX; i++) {
8380 if (_asc_def_iop_base[i] > s_addr) {
8384 for (; i < ASC_IOADR_TABLE_MAX_IX; i++) {
8385 iop_base = _asc_def_iop_base[i];
8386 if (!request_region(iop_base, ASC_IOADR_GAP, "advansys")) {
8388 "AscSearchIOPortAddr11: check_region() failed I/O port 0x%x\n",
8392 ASC_DBG1(1, "AscSearchIOPortAddr11: probing I/O port 0x%x\n",
8394 release_region(iop_base, ASC_IOADR_GAP);
8395 if (AscFindSignature(iop_base)) {
8402 static void __init AscSetISAPNPWaitForKey(void)
8404 outp(ASC_ISA_PNP_PORT_ADDR, 0x02);
8405 outp(ASC_ISA_PNP_PORT_WRITE, 0x02);
8408 #endif /* CONFIG_ISA */
8410 static void __init AscToggleIRQAct(PortAddr iop_base)
8412 AscSetChipStatus(iop_base, CIW_IRQ_ACT);
8413 AscSetChipStatus(iop_base, 0);
8417 static uchar __init AscGetChipIRQ(PortAddr iop_base, ushort bus_type)
8422 if ((bus_type & ASC_IS_EISA) != 0) {
8423 cfg_lsw = AscGetEisaChipCfg(iop_base);
8424 chip_irq = (uchar)(((cfg_lsw >> 8) & 0x07) + 10);
8425 if ((chip_irq == 13) || (chip_irq > 15)) {
8430 if ((bus_type & ASC_IS_VL) != 0) {
8431 cfg_lsw = AscGetChipCfgLsw(iop_base);
8432 chip_irq = (uchar)(((cfg_lsw >> 2) & 0x07));
8433 if ((chip_irq == 0) || (chip_irq == 4) || (chip_irq == 7)) {
8436 return ((uchar)(chip_irq + (ASC_MIN_IRQ_NO - 1)));
8438 cfg_lsw = AscGetChipCfgLsw(iop_base);
8439 chip_irq = (uchar)(((cfg_lsw >> 2) & 0x03));
8441 chip_irq += (uchar)2;
8442 return ((uchar)(chip_irq + ASC_MIN_IRQ_NO));
8446 AscSetChipIRQ(PortAddr iop_base, uchar irq_no, ushort bus_type)
8450 if ((bus_type & ASC_IS_VL) != 0) {
8452 if ((irq_no < ASC_MIN_IRQ_NO)
8453 || (irq_no > ASC_MAX_IRQ_NO)) {
8456 irq_no -= (uchar)((ASC_MIN_IRQ_NO - 1));
8459 cfg_lsw = (ushort)(AscGetChipCfgLsw(iop_base) & 0xFFE3);
8460 cfg_lsw |= (ushort)0x0010;
8461 AscSetChipCfgLsw(iop_base, cfg_lsw);
8462 AscToggleIRQAct(iop_base);
8463 cfg_lsw = (ushort)(AscGetChipCfgLsw(iop_base) & 0xFFE0);
8464 cfg_lsw |= (ushort)((irq_no & 0x07) << 2);
8465 AscSetChipCfgLsw(iop_base, cfg_lsw);
8466 AscToggleIRQAct(iop_base);
8467 return (AscGetChipIRQ(iop_base, bus_type));
8469 if ((bus_type & (ASC_IS_ISA)) != 0) {
8472 irq_no -= (uchar)ASC_MIN_IRQ_NO;
8473 cfg_lsw = (ushort)(AscGetChipCfgLsw(iop_base) & 0xFFF3);
8474 cfg_lsw |= (ushort)((irq_no & 0x03) << 2);
8475 AscSetChipCfgLsw(iop_base, cfg_lsw);
8476 return (AscGetChipIRQ(iop_base, bus_type));
8482 static void __init AscEnableIsaDma(uchar dma_channel)
8484 if (dma_channel < 4) {
8485 outp(0x000B, (ushort)(0xC0 | dma_channel));
8486 outp(0x000A, dma_channel);
8487 } else if (dma_channel < 8) {
8488 outp(0x00D6, (ushort)(0xC0 | (dma_channel - 4)));
8489 outp(0x00D4, (ushort)(dma_channel - 4));
8493 #endif /* CONFIG_ISA */
8495 static int AscIsrChipHalted(ASC_DVC_VAR *asc_dvc)
8501 ushort int_halt_code;
8502 ASC_SCSI_BIT_ID_TYPE scsi_busy;
8503 ASC_SCSI_BIT_ID_TYPE target_id;
8510 uchar q_cntl, tid_no;
8514 asc_board_t *boardp;
8516 ASC_ASSERT(asc_dvc->drv_ptr != NULL);
8517 boardp = asc_dvc->drv_ptr;
8519 iop_base = asc_dvc->iop_base;
8520 int_halt_code = AscReadLramWord(iop_base, ASCV_HALTCODE_W);
8522 halt_qp = AscReadLramByte(iop_base, ASCV_CURCDB_B);
8523 halt_q_addr = ASC_QNO_TO_QADDR(halt_qp);
8524 target_ix = AscReadLramByte(iop_base,
8525 (ushort)(halt_q_addr +
8526 (ushort)ASC_SCSIQ_B_TARGET_IX));
8528 AscReadLramByte(iop_base,
8529 (ushort)(halt_q_addr + (ushort)ASC_SCSIQ_B_CNTL));
8530 tid_no = ASC_TIX_TO_TID(target_ix);
8531 target_id = (uchar)ASC_TID_TO_TARGET_ID(tid_no);
8532 if (asc_dvc->pci_fix_asyn_xfer & target_id) {
8533 asyn_sdtr = ASYN_SDTR_DATA_FIX_PCI_REV_AB;
8537 if (int_halt_code == ASC_HALT_DISABLE_ASYN_USE_SYN_FIX) {
8538 if (asc_dvc->pci_fix_asyn_xfer & target_id) {
8539 AscSetChipSDTR(iop_base, 0, tid_no);
8540 boardp->sdtr_data[tid_no] = 0;
8542 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
8544 } else if (int_halt_code == ASC_HALT_ENABLE_ASYN_USE_SYN_FIX) {
8545 if (asc_dvc->pci_fix_asyn_xfer & target_id) {
8546 AscSetChipSDTR(iop_base, asyn_sdtr, tid_no);
8547 boardp->sdtr_data[tid_no] = asyn_sdtr;
8549 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
8551 } else if (int_halt_code == ASC_HALT_EXTMSG_IN) {
8553 AscMemWordCopyPtrFromLram(iop_base,
8556 sizeof(EXT_MSG) >> 1);
8558 if (ext_msg.msg_type == MS_EXTEND &&
8559 ext_msg.msg_req == MS_SDTR_CODE &&
8560 ext_msg.msg_len == MS_SDTR_LEN) {
8562 if ((ext_msg.req_ack_offset > ASC_SYN_MAX_OFFSET)) {
8564 sdtr_accept = FALSE;
8565 ext_msg.req_ack_offset = ASC_SYN_MAX_OFFSET;
8567 if ((ext_msg.xfer_period <
8568 asc_dvc->sdtr_period_tbl[asc_dvc->
8569 host_init_sdtr_index])
8570 || (ext_msg.xfer_period >
8571 asc_dvc->sdtr_period_tbl[asc_dvc->
8573 sdtr_accept = FALSE;
8574 ext_msg.xfer_period =
8575 asc_dvc->sdtr_period_tbl[asc_dvc->
8576 host_init_sdtr_index];
8580 AscCalSDTRData(asc_dvc, ext_msg.xfer_period,
8581 ext_msg.req_ack_offset);
8582 if ((sdtr_data == 0xFF)) {
8584 q_cntl |= QC_MSG_OUT;
8585 asc_dvc->init_sdtr &= ~target_id;
8586 asc_dvc->sdtr_done &= ~target_id;
8587 AscSetChipSDTR(iop_base, asyn_sdtr,
8589 boardp->sdtr_data[tid_no] = asyn_sdtr;
8592 if (ext_msg.req_ack_offset == 0) {
8594 q_cntl &= ~QC_MSG_OUT;
8595 asc_dvc->init_sdtr &= ~target_id;
8596 asc_dvc->sdtr_done &= ~target_id;
8597 AscSetChipSDTR(iop_base, asyn_sdtr, tid_no);
8599 if (sdtr_accept && (q_cntl & QC_MSG_OUT)) {
8601 q_cntl &= ~QC_MSG_OUT;
8602 asc_dvc->sdtr_done |= target_id;
8603 asc_dvc->init_sdtr |= target_id;
8604 asc_dvc->pci_fix_asyn_xfer &=
8607 AscCalSDTRData(asc_dvc,
8608 ext_msg.xfer_period,
8611 AscSetChipSDTR(iop_base, sdtr_data,
8613 boardp->sdtr_data[tid_no] = sdtr_data;
8616 q_cntl |= QC_MSG_OUT;
8617 AscMsgOutSDTR(asc_dvc,
8618 ext_msg.xfer_period,
8619 ext_msg.req_ack_offset);
8620 asc_dvc->pci_fix_asyn_xfer &=
8623 AscCalSDTRData(asc_dvc,
8624 ext_msg.xfer_period,
8627 AscSetChipSDTR(iop_base, sdtr_data,
8629 boardp->sdtr_data[tid_no] = sdtr_data;
8630 asc_dvc->sdtr_done |= target_id;
8631 asc_dvc->init_sdtr |= target_id;
8635 AscWriteLramByte(iop_base,
8636 (ushort)(halt_q_addr +
8637 (ushort)ASC_SCSIQ_B_CNTL),
8639 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
8641 } else if (ext_msg.msg_type == MS_EXTEND &&
8642 ext_msg.msg_req == MS_WDTR_CODE &&
8643 ext_msg.msg_len == MS_WDTR_LEN) {
8645 ext_msg.wdtr_width = 0;
8646 AscMemWordCopyPtrToLram(iop_base,
8649 sizeof(EXT_MSG) >> 1);
8650 q_cntl |= QC_MSG_OUT;
8651 AscWriteLramByte(iop_base,
8652 (ushort)(halt_q_addr +
8653 (ushort)ASC_SCSIQ_B_CNTL),
8655 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
8659 ext_msg.msg_type = MESSAGE_REJECT;
8660 AscMemWordCopyPtrToLram(iop_base,
8663 sizeof(EXT_MSG) >> 1);
8664 q_cntl |= QC_MSG_OUT;
8665 AscWriteLramByte(iop_base,
8666 (ushort)(halt_q_addr +
8667 (ushort)ASC_SCSIQ_B_CNTL),
8669 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
8672 } else if (int_halt_code == ASC_HALT_CHK_CONDITION) {
8674 q_cntl |= QC_REQ_SENSE;
8676 if ((asc_dvc->init_sdtr & target_id) != 0) {
8678 asc_dvc->sdtr_done &= ~target_id;
8680 sdtr_data = AscGetMCodeInitSDTRAtID(iop_base, tid_no);
8681 q_cntl |= QC_MSG_OUT;
8682 AscMsgOutSDTR(asc_dvc,
8684 sdtr_period_tbl[(sdtr_data >> 4) &
8688 (uchar)(sdtr_data & (uchar)
8689 ASC_SYN_MAX_OFFSET));
8692 AscWriteLramByte(iop_base,
8693 (ushort)(halt_q_addr +
8694 (ushort)ASC_SCSIQ_B_CNTL), q_cntl);
8696 tag_code = AscReadLramByte(iop_base,
8697 (ushort)(halt_q_addr + (ushort)
8698 ASC_SCSIQ_B_TAG_CODE));
8700 if ((asc_dvc->pci_fix_asyn_xfer & target_id)
8701 && !(asc_dvc->pci_fix_asyn_xfer_always & target_id)
8704 tag_code |= (ASC_TAG_FLAG_DISABLE_DISCONNECT
8705 | ASC_TAG_FLAG_DISABLE_ASYN_USE_SYN_FIX);
8708 AscWriteLramByte(iop_base,
8709 (ushort)(halt_q_addr +
8710 (ushort)ASC_SCSIQ_B_TAG_CODE),
8713 q_status = AscReadLramByte(iop_base,
8714 (ushort)(halt_q_addr + (ushort)
8715 ASC_SCSIQ_B_STATUS));
8716 q_status |= (QS_READY | QS_BUSY);
8717 AscWriteLramByte(iop_base,
8718 (ushort)(halt_q_addr +
8719 (ushort)ASC_SCSIQ_B_STATUS),
8722 scsi_busy = AscReadLramByte(iop_base, (ushort)ASCV_SCSIBUSY_B);
8723 scsi_busy &= ~target_id;
8724 AscWriteLramByte(iop_base, (ushort)ASCV_SCSIBUSY_B, scsi_busy);
8726 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
8728 } else if (int_halt_code == ASC_HALT_SDTR_REJECTED) {
8730 AscMemWordCopyPtrFromLram(iop_base,
8733 sizeof(EXT_MSG) >> 1);
8735 if ((out_msg.msg_type == MS_EXTEND) &&
8736 (out_msg.msg_len == MS_SDTR_LEN) &&
8737 (out_msg.msg_req == MS_SDTR_CODE)) {
8739 asc_dvc->init_sdtr &= ~target_id;
8740 asc_dvc->sdtr_done &= ~target_id;
8741 AscSetChipSDTR(iop_base, asyn_sdtr, tid_no);
8742 boardp->sdtr_data[tid_no] = asyn_sdtr;
8744 q_cntl &= ~QC_MSG_OUT;
8745 AscWriteLramByte(iop_base,
8746 (ushort)(halt_q_addr +
8747 (ushort)ASC_SCSIQ_B_CNTL), q_cntl);
8748 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
8750 } else if (int_halt_code == ASC_HALT_SS_QUEUE_FULL) {
8752 scsi_status = AscReadLramByte(iop_base,
8753 (ushort)((ushort)halt_q_addr +
8755 ASC_SCSIQ_SCSI_STATUS));
8757 AscReadLramByte(iop_base,
8758 (ushort)((ushort)ASC_QADR_BEG +
8759 (ushort)target_ix));
8760 if ((cur_dvc_qng > 0) && (asc_dvc->cur_dvc_qng[tid_no] > 0)) {
8762 scsi_busy = AscReadLramByte(iop_base,
8763 (ushort)ASCV_SCSIBUSY_B);
8764 scsi_busy |= target_id;
8765 AscWriteLramByte(iop_base,
8766 (ushort)ASCV_SCSIBUSY_B, scsi_busy);
8767 asc_dvc->queue_full_or_busy |= target_id;
8769 if (scsi_status == SAM_STAT_TASK_SET_FULL) {
8770 if (cur_dvc_qng > ASC_MIN_TAGGED_CMD) {
8772 asc_dvc->max_dvc_qng[tid_no] =
8775 AscWriteLramByte(iop_base,
8777 ASCV_MAX_DVC_QNG_BEG
8783 * Set the device queue depth to the number of
8784 * active requests when the QUEUE FULL condition
8787 boardp->queue_full |= target_id;
8788 boardp->queue_full_cnt[tid_no] =
8793 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
8796 #if CC_VERY_LONG_SG_LIST
8797 else if (int_halt_code == ASC_HALT_HOST_COPY_SG_LIST_TO_RISC) {
8801 uchar first_sg_wk_q_no;
8802 ASC_SCSI_Q *scsiq; /* Ptr to driver request. */
8803 ASC_SG_HEAD *sg_head; /* Ptr to driver SG request. */
8804 ASC_SG_LIST_Q scsi_sg_q; /* Structure written to queue. */
8805 ushort sg_list_dwords;
8806 ushort sg_entry_cnt;
8810 q_no = AscReadLramByte(iop_base, (ushort)ASCV_REQ_SG_LIST_QP);
8811 if (q_no == ASC_QLINK_END) {
8815 q_addr = ASC_QNO_TO_QADDR(q_no);
8818 * Convert the request's SRB pointer to a host ASC_SCSI_REQ
8819 * structure pointer using a macro provided by the driver.
8820 * The ASC_SCSI_REQ pointer provides a pointer to the
8821 * host ASC_SG_HEAD structure.
8823 /* Read request's SRB pointer. */
8824 scsiq = (ASC_SCSI_Q *)
8825 ASC_SRB2SCSIQ(ASC_U32_TO_VADDR(AscReadLramDWord(iop_base,
8828 ASC_SCSIQ_D_SRBPTR))));
8831 * Get request's first and working SG queue.
8833 sg_wk_q_no = AscReadLramByte(iop_base,
8835 ASC_SCSIQ_B_SG_WK_QP));
8837 first_sg_wk_q_no = AscReadLramByte(iop_base,
8839 ASC_SCSIQ_B_FIRST_SG_WK_QP));
8842 * Reset request's working SG queue back to the
8845 AscWriteLramByte(iop_base,
8847 (ushort)ASC_SCSIQ_B_SG_WK_QP),
8850 sg_head = scsiq->sg_head;
8853 * Set sg_entry_cnt to the number of SG elements
8854 * that will be completed on this interrupt.
8856 * Note: The allocated SG queues contain ASC_MAX_SG_LIST - 1
8857 * SG elements. The data_cnt and data_addr fields which
8858 * add 1 to the SG element capacity are not used when
8859 * restarting SG handling after a halt.
8861 if (scsiq->remain_sg_entry_cnt > (ASC_MAX_SG_LIST - 1)) {
8862 sg_entry_cnt = ASC_MAX_SG_LIST - 1;
8865 * Keep track of remaining number of SG elements that will
8866 * need to be handled on the next interrupt.
8868 scsiq->remain_sg_entry_cnt -= (ASC_MAX_SG_LIST - 1);
8870 sg_entry_cnt = scsiq->remain_sg_entry_cnt;
8871 scsiq->remain_sg_entry_cnt = 0;
8875 * Copy SG elements into the list of allocated SG queues.
8877 * Last index completed is saved in scsiq->next_sg_index.
8879 next_qp = first_sg_wk_q_no;
8880 q_addr = ASC_QNO_TO_QADDR(next_qp);
8881 scsi_sg_q.sg_head_qp = q_no;
8882 scsi_sg_q.cntl = QCSG_SG_XFER_LIST;
8883 for (i = 0; i < sg_head->queue_cnt; i++) {
8884 scsi_sg_q.seq_no = i + 1;
8885 if (sg_entry_cnt > ASC_SG_LIST_PER_Q) {
8886 sg_list_dwords = (uchar)(ASC_SG_LIST_PER_Q * 2);
8887 sg_entry_cnt -= ASC_SG_LIST_PER_Q;
8889 * After very first SG queue RISC FW uses next
8890 * SG queue first element then checks sg_list_cnt
8891 * against zero and then decrements, so set
8892 * sg_list_cnt 1 less than number of SG elements
8895 scsi_sg_q.sg_list_cnt = ASC_SG_LIST_PER_Q - 1;
8896 scsi_sg_q.sg_cur_list_cnt =
8897 ASC_SG_LIST_PER_Q - 1;
8900 * This is the last SG queue in the list of
8901 * allocated SG queues. If there are more
8902 * SG elements than will fit in the allocated
8903 * queues, then set the QCSG_SG_XFER_MORE flag.
8905 if (scsiq->remain_sg_entry_cnt != 0) {
8906 scsi_sg_q.cntl |= QCSG_SG_XFER_MORE;
8908 scsi_sg_q.cntl |= QCSG_SG_XFER_END;
8910 /* equals sg_entry_cnt * 2 */
8911 sg_list_dwords = sg_entry_cnt << 1;
8912 scsi_sg_q.sg_list_cnt = sg_entry_cnt - 1;
8913 scsi_sg_q.sg_cur_list_cnt = sg_entry_cnt - 1;
8917 scsi_sg_q.q_no = next_qp;
8918 AscMemWordCopyPtrToLram(iop_base,
8919 q_addr + ASC_SCSIQ_SGHD_CPY_BEG,
8920 (uchar *)&scsi_sg_q,
8921 sizeof(ASC_SG_LIST_Q) >> 1);
8923 AscMemDWordCopyPtrToLram(iop_base,
8924 q_addr + ASC_SGQ_LIST_BEG,
8926 sg_list[scsiq->next_sg_index],
8929 scsiq->next_sg_index += ASC_SG_LIST_PER_Q;
8932 * If the just completed SG queue contained the
8933 * last SG element, then no more SG queues need
8936 if (scsi_sg_q.cntl & QCSG_SG_XFER_END) {
8940 next_qp = AscReadLramByte(iop_base,
8943 q_addr = ASC_QNO_TO_QADDR(next_qp);
8947 * Clear the halt condition so the RISC will be restarted
8950 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
8953 #endif /* CC_VERY_LONG_SG_LIST */
8958 _AscCopyLramScsiDoneQ(PortAddr iop_base,
8960 ASC_QDONE_INFO *scsiq, ASC_DCNT max_dma_count)
8965 DvcGetQinfo(iop_base,
8966 q_addr + ASC_SCSIQ_DONE_INFO_BEG,
8968 (sizeof(ASC_SCSIQ_2) + sizeof(ASC_SCSIQ_3)) / 2);
8970 _val = AscReadLramWord(iop_base,
8971 (ushort)(q_addr + (ushort)ASC_SCSIQ_B_STATUS));
8972 scsiq->q_status = (uchar)_val;
8973 scsiq->q_no = (uchar)(_val >> 8);
8974 _val = AscReadLramWord(iop_base,
8975 (ushort)(q_addr + (ushort)ASC_SCSIQ_B_CNTL));
8976 scsiq->cntl = (uchar)_val;
8977 sg_queue_cnt = (uchar)(_val >> 8);
8978 _val = AscReadLramWord(iop_base,
8980 (ushort)ASC_SCSIQ_B_SENSE_LEN));
8981 scsiq->sense_len = (uchar)_val;
8982 scsiq->extra_bytes = (uchar)(_val >> 8);
8985 * Read high word of remain bytes from alternate location.
8987 scsiq->remain_bytes = (((ADV_DCNT)AscReadLramWord(iop_base,
8990 ASC_SCSIQ_W_ALT_DC1)))
8993 * Read low word of remain bytes from original location.
8995 scsiq->remain_bytes += AscReadLramWord(iop_base,
8996 (ushort)(q_addr + (ushort)
8997 ASC_SCSIQ_DW_REMAIN_XFER_CNT));
8999 scsiq->remain_bytes &= max_dma_count;
9000 return (sg_queue_cnt);
9003 static int AscIsrQDone(ASC_DVC_VAR *asc_dvc)
9012 ASC_SCSI_BIT_ID_TYPE scsi_busy;
9013 ASC_SCSI_BIT_ID_TYPE target_id;
9017 uchar cur_target_qng;
9018 ASC_QDONE_INFO scsiq_buf;
9019 ASC_QDONE_INFO *scsiq;
9021 ASC_ISR_CALLBACK asc_isr_callback;
9023 iop_base = asc_dvc->iop_base;
9024 asc_isr_callback = asc_dvc->isr_callback;
9026 scsiq = (ASC_QDONE_INFO *)&scsiq_buf;
9027 done_q_tail = (uchar)AscGetVarDoneQTail(iop_base);
9028 q_addr = ASC_QNO_TO_QADDR(done_q_tail);
9029 next_qp = AscReadLramByte(iop_base,
9030 (ushort)(q_addr + (ushort)ASC_SCSIQ_B_FWD));
9031 if (next_qp != ASC_QLINK_END) {
9032 AscPutVarDoneQTail(iop_base, next_qp);
9033 q_addr = ASC_QNO_TO_QADDR(next_qp);
9034 sg_queue_cnt = _AscCopyLramScsiDoneQ(iop_base, q_addr, scsiq,
9035 asc_dvc->max_dma_count);
9036 AscWriteLramByte(iop_base,
9038 (ushort)ASC_SCSIQ_B_STATUS),
9040 q_status & (uchar)~(QS_READY |
9042 tid_no = ASC_TIX_TO_TID(scsiq->d2.target_ix);
9043 target_id = ASC_TIX_TO_TARGET_ID(scsiq->d2.target_ix);
9044 if ((scsiq->cntl & QC_SG_HEAD) != 0) {
9046 sg_list_qp = next_qp;
9047 for (q_cnt = 0; q_cnt < sg_queue_cnt; q_cnt++) {
9048 sg_list_qp = AscReadLramByte(iop_base,
9052 sg_q_addr = ASC_QNO_TO_QADDR(sg_list_qp);
9053 if (sg_list_qp == ASC_QLINK_END) {
9054 AscSetLibErrorCode(asc_dvc,
9055 ASCQ_ERR_SG_Q_LINKS);
9056 scsiq->d3.done_stat = QD_WITH_ERROR;
9057 scsiq->d3.host_stat =
9058 QHSTA_D_QDONE_SG_LIST_CORRUPTED;
9059 goto FATAL_ERR_QDONE;
9061 AscWriteLramByte(iop_base,
9062 (ushort)(sg_q_addr + (ushort)
9063 ASC_SCSIQ_B_STATUS),
9066 n_q_used = sg_queue_cnt + 1;
9067 AscPutVarDoneQTail(iop_base, sg_list_qp);
9069 if (asc_dvc->queue_full_or_busy & target_id) {
9070 cur_target_qng = AscReadLramByte(iop_base,
9076 if (cur_target_qng < asc_dvc->max_dvc_qng[tid_no]) {
9077 scsi_busy = AscReadLramByte(iop_base, (ushort)
9079 scsi_busy &= ~target_id;
9080 AscWriteLramByte(iop_base,
9081 (ushort)ASCV_SCSIBUSY_B,
9083 asc_dvc->queue_full_or_busy &= ~target_id;
9086 if (asc_dvc->cur_total_qng >= n_q_used) {
9087 asc_dvc->cur_total_qng -= n_q_used;
9088 if (asc_dvc->cur_dvc_qng[tid_no] != 0) {
9089 asc_dvc->cur_dvc_qng[tid_no]--;
9092 AscSetLibErrorCode(asc_dvc, ASCQ_ERR_CUR_QNG);
9093 scsiq->d3.done_stat = QD_WITH_ERROR;
9094 goto FATAL_ERR_QDONE;
9096 if ((scsiq->d2.srb_ptr == 0UL) ||
9097 ((scsiq->q_status & QS_ABORTED) != 0)) {
9099 } else if (scsiq->q_status == QS_DONE) {
9100 false_overrun = FALSE;
9101 if (scsiq->extra_bytes != 0) {
9102 scsiq->remain_bytes +=
9103 (ADV_DCNT)scsiq->extra_bytes;
9105 if (scsiq->d3.done_stat == QD_WITH_ERROR) {
9106 if (scsiq->d3.host_stat ==
9107 QHSTA_M_DATA_OVER_RUN) {
9109 cntl & (QC_DATA_IN | QC_DATA_OUT))
9111 scsiq->d3.done_stat =
9113 scsiq->d3.host_stat =
9115 } else if (false_overrun) {
9116 scsiq->d3.done_stat =
9118 scsiq->d3.host_stat =
9121 } else if (scsiq->d3.host_stat ==
9122 QHSTA_M_HUNG_REQ_SCSI_BUS_RESET) {
9123 AscStopChip(iop_base);
9124 AscSetChipControl(iop_base,
9125 (uchar)(CC_SCSI_RESET
9127 DvcDelayNanoSecond(asc_dvc, 60000);
9128 AscSetChipControl(iop_base, CC_HALT);
9129 AscSetChipStatus(iop_base,
9130 CIW_CLR_SCSI_RESET_INT);
9131 AscSetChipStatus(iop_base, 0);
9132 AscSetChipControl(iop_base, 0);
9135 if ((scsiq->cntl & QC_NO_CALLBACK) == 0) {
9136 (*asc_isr_callback) (asc_dvc, scsiq);
9138 if ((AscReadLramByte(iop_base,
9139 (ushort)(q_addr + (ushort)
9142 asc_dvc->unit_not_ready &= ~target_id;
9143 if (scsiq->d3.done_stat != QD_NO_ERROR) {
9144 asc_dvc->start_motor &=
9151 AscSetLibErrorCode(asc_dvc, ASCQ_ERR_Q_STATUS);
9153 if ((scsiq->cntl & QC_NO_CALLBACK) == 0) {
9154 (*asc_isr_callback) (asc_dvc, scsiq);
9162 static int AscISR(ASC_DVC_VAR *asc_dvc)
9164 ASC_CS_TYPE chipstat;
9166 ushort saved_ram_addr;
9168 uchar saved_ctrl_reg;
9173 iop_base = asc_dvc->iop_base;
9174 int_pending = FALSE;
9176 if (AscIsIntPending(iop_base) == 0) {
9180 if (((asc_dvc->init_state & ASC_INIT_STATE_END_LOAD_MC) == 0)
9181 || (asc_dvc->isr_callback == 0)
9185 if (asc_dvc->in_critical_cnt != 0) {
9186 AscSetLibErrorCode(asc_dvc, ASCQ_ERR_ISR_ON_CRITICAL);
9189 if (asc_dvc->is_in_int) {
9190 AscSetLibErrorCode(asc_dvc, ASCQ_ERR_ISR_RE_ENTRY);
9193 asc_dvc->is_in_int = TRUE;
9194 ctrl_reg = AscGetChipControl(iop_base);
9195 saved_ctrl_reg = ctrl_reg & (~(CC_SCSI_RESET | CC_CHIP_RESET |
9196 CC_SINGLE_STEP | CC_DIAG | CC_TEST));
9197 chipstat = AscGetChipStatus(iop_base);
9198 if (chipstat & CSW_SCSI_RESET_LATCH) {
9199 if (!(asc_dvc->bus_type & (ASC_IS_VL | ASC_IS_EISA))) {
9202 asc_dvc->sdtr_done = 0;
9203 saved_ctrl_reg &= (uchar)(~CC_HALT);
9204 while ((AscGetChipStatus(iop_base) &
9205 CSW_SCSI_RESET_ACTIVE) && (i-- > 0)) {
9206 DvcSleepMilliSecond(100);
9208 AscSetChipControl(iop_base, (CC_CHIP_RESET | CC_HALT));
9209 AscSetChipControl(iop_base, CC_HALT);
9210 AscSetChipStatus(iop_base, CIW_CLR_SCSI_RESET_INT);
9211 AscSetChipStatus(iop_base, 0);
9212 chipstat = AscGetChipStatus(iop_base);
9215 saved_ram_addr = AscGetChipLramAddr(iop_base);
9216 host_flag = AscReadLramByte(iop_base,
9218 (uchar)(~ASC_HOST_FLAG_IN_ISR);
9219 AscWriteLramByte(iop_base, ASCV_HOST_FLAG_B,
9220 (uchar)(host_flag | (uchar)ASC_HOST_FLAG_IN_ISR));
9221 if ((chipstat & CSW_INT_PENDING)
9224 AscAckInterrupt(iop_base);
9226 if ((chipstat & CSW_HALTED) && (ctrl_reg & CC_SINGLE_STEP)) {
9227 if (AscIsrChipHalted(asc_dvc) == ERR) {
9228 goto ISR_REPORT_QDONE_FATAL_ERROR;
9230 saved_ctrl_reg &= (uchar)(~CC_HALT);
9233 ISR_REPORT_QDONE_FATAL_ERROR:
9234 if ((asc_dvc->dvc_cntl & ASC_CNTL_INT_MULTI_Q) != 0) {
9236 AscIsrQDone(asc_dvc)) & 0x01) != 0) {
9241 AscIsrQDone(asc_dvc)) == 1) {
9244 } while (status == 0x11);
9246 if ((status & 0x80) != 0)
9250 AscWriteLramByte(iop_base, ASCV_HOST_FLAG_B, host_flag);
9251 AscSetChipLramAddr(iop_base, saved_ram_addr);
9252 AscSetChipControl(iop_base, saved_ctrl_reg);
9253 asc_dvc->is_in_int = FALSE;
9254 return (int_pending);
9257 /* Microcode buffer is kept after initialization for error recovery. */
9258 static uchar _asc_mcode_buf[] = {
9259 0x01, 0x03, 0x01, 0x19, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
9260 0x00, 0x00, 0x00, 0x00,
9261 0x0F, 0x0F, 0x0F, 0x0F, 0x0F, 0x0F, 0x0F, 0x0F, 0x00, 0x00, 0x00, 0x00,
9262 0x00, 0x00, 0x00, 0x00,
9263 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
9264 0x00, 0x00, 0x00, 0x00,
9265 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
9266 0x00, 0x00, 0x00, 0x00,
9267 0x00, 0x00, 0x00, 0x00, 0xC3, 0x12, 0x0D, 0x05, 0x01, 0x00, 0x00, 0x00,
9268 0x00, 0xFF, 0x00, 0x00,
9269 0x00, 0x00, 0x00, 0x00, 0xFF, 0x80, 0xFF, 0xFF, 0x01, 0x00, 0x00, 0x00,
9270 0x00, 0x00, 0x00, 0x00,
9271 0x00, 0x00, 0x00, 0x23, 0x00, 0x00, 0x00, 0x00, 0x00, 0x07, 0x00, 0xFF,
9272 0x00, 0x00, 0x00, 0x00,
9273 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE4, 0x88,
9274 0x00, 0x00, 0x00, 0x00,
9275 0x80, 0x73, 0x48, 0x04, 0x36, 0x00, 0x00, 0xA2, 0xC2, 0x00, 0x80, 0x73,
9276 0x03, 0x23, 0x36, 0x40,
9277 0xB6, 0x00, 0x36, 0x00, 0x05, 0xD6, 0x0C, 0xD2, 0x12, 0xDA, 0x00, 0xA2,
9278 0xC2, 0x00, 0x92, 0x80,
9279 0x1E, 0x98, 0x50, 0x00, 0xF5, 0x00, 0x48, 0x98, 0xDF, 0x23, 0x36, 0x60,
9280 0xB6, 0x00, 0x92, 0x80,
9281 0x4F, 0x00, 0xF5, 0x00, 0x48, 0x98, 0xEF, 0x23, 0x36, 0x60, 0xB6, 0x00,
9282 0x92, 0x80, 0x80, 0x62,
9283 0x92, 0x80, 0x00, 0x46, 0x15, 0xEE, 0x13, 0xEA, 0x02, 0x01, 0x09, 0xD8,
9284 0xCD, 0x04, 0x4D, 0x00,
9285 0x00, 0xA3, 0xD6, 0x00, 0xA6, 0x97, 0x7F, 0x23, 0x04, 0x61, 0x84, 0x01,
9286 0xE6, 0x84, 0xD2, 0xC1,
9287 0x80, 0x73, 0xCD, 0x04, 0x4D, 0x00, 0x00, 0xA3, 0xDA, 0x01, 0xA6, 0x97,
9288 0xC6, 0x81, 0xC2, 0x88,
9289 0x80, 0x73, 0x80, 0x77, 0x00, 0x01, 0x01, 0xA1, 0xFE, 0x00, 0x4F, 0x00,
9290 0x84, 0x97, 0x07, 0xA6,
9291 0x08, 0x01, 0x00, 0x33, 0x03, 0x00, 0xC2, 0x88, 0x03, 0x03, 0x01, 0xDE,
9292 0xC2, 0x88, 0xCE, 0x00,
9293 0x69, 0x60, 0xCE, 0x00, 0x02, 0x03, 0x4A, 0x60, 0x00, 0xA2, 0x78, 0x01,
9294 0x80, 0x63, 0x07, 0xA6,
9295 0x24, 0x01, 0x78, 0x81, 0x03, 0x03, 0x80, 0x63, 0xE2, 0x00, 0x07, 0xA6,
9296 0x34, 0x01, 0x00, 0x33,
9297 0x04, 0x00, 0xC2, 0x88, 0x03, 0x07, 0x02, 0x01, 0x04, 0xCA, 0x0D, 0x23,
9298 0x68, 0x98, 0x4D, 0x04,
9299 0x04, 0x85, 0x05, 0xD8, 0x0D, 0x23, 0x68, 0x98, 0xCD, 0x04, 0x15, 0x23,
9300 0xF8, 0x88, 0xFB, 0x23,
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9314 0xC2, 0x88, 0x06, 0x23,
9315 0x68, 0x98, 0xCD, 0x04, 0xE6, 0x84, 0x06, 0x01, 0x00, 0xA2, 0xD4, 0x01,
9316 0x57, 0x60, 0x00, 0xA0,
9317 0xDA, 0x01, 0xE6, 0x84, 0x80, 0x23, 0xA0, 0x01, 0xE6, 0x84, 0x80, 0x73,
9318 0x4B, 0x00, 0x06, 0x61,
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9320 0x4F, 0x00, 0x84, 0x97,
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9330 0x46, 0x82, 0xFE, 0x95,
9331 0x80, 0x67, 0x83, 0x03, 0x80, 0x63, 0xB6, 0x2D, 0x02, 0xA6, 0x6C, 0x02,
9332 0x07, 0xA6, 0x5A, 0x02,
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9339 0x03, 0x23, 0xA4, 0x01, 0x06, 0x23, 0x9C, 0x01, 0x24, 0x2B, 0x1C, 0x01,
9340 0x02, 0xA6, 0xAA, 0x02,
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9342 0x01, 0xA6, 0xB4, 0x02,
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9344 0x80, 0x63, 0x00, 0x43,
9345 0x00, 0xA0, 0x8C, 0x02, 0x4D, 0x04, 0x04, 0x01, 0x0B, 0xDC, 0xE7, 0x23,
9346 0x04, 0x61, 0x84, 0x01,
9347 0x10, 0x31, 0x12, 0x35, 0x14, 0x01, 0xEC, 0x00, 0x6C, 0x38, 0x00, 0x3F,
9348 0x00, 0x00, 0xEA, 0x82,
9349 0x18, 0x23, 0x04, 0x61, 0x18, 0xA0, 0xE2, 0x02, 0x04, 0x01, 0xA2, 0xC8,
9350 0x00, 0x33, 0x1F, 0x00,
9351 0xC2, 0x88, 0x08, 0x31, 0x0A, 0x35, 0x0C, 0x39, 0x0E, 0x3D, 0x7E, 0x98,
9352 0xB6, 0x2D, 0x01, 0xA6,
9353 0x14, 0x03, 0x00, 0xA6, 0x14, 0x03, 0x07, 0xA6, 0x0C, 0x03, 0x06, 0xA6,
9354 0x10, 0x03, 0x03, 0xA6,
9355 0x20, 0x04, 0x02, 0xA6, 0x6C, 0x02, 0x00, 0x33, 0x33, 0x00, 0xC2, 0x88,
9356 0x7C, 0x95, 0xEE, 0x82,
9357 0x60, 0x96, 0xEE, 0x82, 0x82, 0x98, 0x80, 0x42, 0x7E, 0x98, 0x64, 0xE4,
9358 0x04, 0x01, 0x2D, 0xC8,
9359 0x31, 0x05, 0x07, 0x01, 0x00, 0xA2, 0x54, 0x03, 0x00, 0x43, 0x87, 0x01,
9360 0x05, 0x05, 0x86, 0x98,
9361 0x7E, 0x98, 0x00, 0xA6, 0x16, 0x03, 0x07, 0xA6, 0x4C, 0x03, 0x03, 0xA6,
9362 0x3C, 0x04, 0x06, 0xA6,
9363 0x50, 0x03, 0x01, 0xA6, 0x16, 0x03, 0x00, 0x33, 0x25, 0x00, 0xC2, 0x88,
9364 0x7C, 0x95, 0x32, 0x83,
9365 0x60, 0x96, 0x32, 0x83, 0x04, 0x01, 0x10, 0xCE, 0x07, 0xC8, 0x05, 0x05,
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9368 0xFF, 0xA2, 0x7A, 0x03,
9369 0xB1, 0x01, 0x08, 0x23, 0xB2, 0x01, 0x2E, 0x83, 0x05, 0x05, 0x15, 0x01,
9370 0x00, 0xA2, 0x9A, 0x03,
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9372 0x01, 0xA6, 0x96, 0x03,
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9374 0xA4, 0x03, 0x00, 0xA6,
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9376 0x07, 0xA6, 0xB2, 0x03,
9377 0xD4, 0x83, 0x7C, 0x95, 0xA8, 0x83, 0x00, 0x33, 0x2F, 0x00, 0xC2, 0x88,
9378 0xA8, 0x98, 0x80, 0x42,
9379 0x00, 0xA6, 0xBC, 0x03, 0x07, 0xA6, 0xCA, 0x03, 0xD4, 0x83, 0x7C, 0x95,
9380 0xC0, 0x83, 0x00, 0x33,
9381 0x26, 0x00, 0xC2, 0x88, 0x38, 0x2B, 0x80, 0x32, 0x80, 0x36, 0x04, 0x23,
9382 0xA0, 0x01, 0x12, 0x23,
9383 0xA1, 0x01, 0x10, 0x84, 0x07, 0xF0, 0x06, 0xA4, 0xF4, 0x03, 0x80, 0x6B,
9384 0x80, 0x67, 0x05, 0x23,
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9386 0x06, 0xA6, 0x0A, 0x04,
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9388 0xF4, 0x83, 0x20, 0x84,
9389 0x07, 0xF0, 0x06, 0xA4, 0x20, 0x04, 0x80, 0x6B, 0x80, 0x67, 0x05, 0x23,
9390 0x83, 0x03, 0x80, 0x63,
9391 0xB6, 0x2D, 0x03, 0xA6, 0x3C, 0x04, 0x07, 0xA6, 0x34, 0x04, 0x06, 0xA6,
9392 0x38, 0x04, 0x00, 0x33,
9393 0x30, 0x00, 0xC2, 0x88, 0x7C, 0x95, 0x20, 0x84, 0x60, 0x96, 0x20, 0x84,
9394 0x1D, 0x01, 0x06, 0xCC,
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9398 0x80, 0x63, 0xA3, 0x01,
9399 0x07, 0xA4, 0x64, 0x04, 0x23, 0x01, 0x00, 0xA2, 0x86, 0x04, 0x0A, 0xA0,
9400 0x76, 0x04, 0xE0, 0x00,
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9402 0x00, 0x33, 0x1E, 0x00,
9403 0xC2, 0x88, 0x42, 0x23, 0xF8, 0x88, 0x00, 0x23, 0x22, 0xA3, 0xE6, 0x04,
9404 0x08, 0x23, 0x22, 0xA3,
9405 0xA2, 0x04, 0x28, 0x23, 0x22, 0xA3, 0xAE, 0x04, 0x02, 0x23, 0x22, 0xA3,
9406 0xC4, 0x04, 0x42, 0x23,
9407 0xF8, 0x88, 0x4A, 0x00, 0x06, 0x61, 0x00, 0xA0, 0xAE, 0x04, 0x45, 0x23,
9408 0xF8, 0x88, 0x04, 0x98,
9409 0x00, 0xA2, 0xC0, 0x04, 0xB4, 0x98, 0x00, 0x33, 0x00, 0x82, 0xC0, 0x20,
9410 0x81, 0x62, 0xE8, 0x81,
9411 0x47, 0x23, 0xF8, 0x88, 0x04, 0x01, 0x0B, 0xDE, 0x04, 0x98, 0xB4, 0x98,
9412 0x00, 0x33, 0x00, 0x81,
9413 0xC0, 0x20, 0x81, 0x62, 0x14, 0x01, 0x00, 0xA0, 0x00, 0x02, 0x43, 0x23,
9414 0xF8, 0x88, 0x04, 0x23,
9415 0xA0, 0x01, 0x44, 0x23, 0xA1, 0x01, 0x80, 0x73, 0x4D, 0x00, 0x03, 0xA3,
9416 0xF4, 0x04, 0x00, 0x33,
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9418 0x04, 0x23, 0xA0, 0x01,
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9420 0x00, 0xA3, 0x22, 0x05,
9421 0x00, 0x05, 0x76, 0x00, 0x06, 0x61, 0x00, 0xA2, 0x1C, 0x05, 0x0A, 0x85,
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9423 0x24, 0x85, 0x48, 0x04, 0x84, 0x80, 0x02, 0x01, 0x03, 0xDA, 0x80, 0x23,
9424 0x82, 0x01, 0x34, 0x85,
9425 0x02, 0x23, 0xA0, 0x01, 0x4A, 0x00, 0x06, 0x61, 0x00, 0xA2, 0x40, 0x05,
9426 0x1D, 0x01, 0x04, 0xD6,
9427 0xFF, 0x23, 0x86, 0x41, 0x4B, 0x60, 0xCB, 0x00, 0xFF, 0x23, 0x80, 0x01,
9428 0x49, 0x00, 0x81, 0x01,
9429 0x04, 0x01, 0x02, 0xC8, 0x30, 0x01, 0x80, 0x01, 0xF7, 0x04, 0x03, 0x01,
9430 0x49, 0x04, 0x80, 0x01,
9431 0xC9, 0x00, 0x00, 0x05, 0x00, 0x01, 0xFF, 0xA0, 0x60, 0x05, 0x77, 0x04,
9432 0x01, 0x23, 0xEA, 0x00,
9433 0x5D, 0x00, 0xFE, 0xC7, 0x00, 0x62, 0x00, 0x23, 0xEA, 0x00, 0x00, 0x63,
9434 0x07, 0xA4, 0xF8, 0x05,
9435 0x03, 0x03, 0x02, 0xA0, 0x8E, 0x05, 0xF4, 0x85, 0x00, 0x33, 0x2D, 0x00,
9436 0xC2, 0x88, 0x04, 0xA0,
9437 0xB8, 0x05, 0x80, 0x63, 0x00, 0x23, 0xDF, 0x00, 0x4A, 0x00, 0x06, 0x61,
9438 0x00, 0xA2, 0xA4, 0x05,
9439 0x1D, 0x01, 0x06, 0xD6, 0x02, 0x23, 0x02, 0x41, 0x82, 0x01, 0x50, 0x00,
9440 0x62, 0x97, 0x04, 0x85,
9441 0x04, 0x23, 0x02, 0x41, 0x82, 0x01, 0x04, 0x85, 0x08, 0xA0, 0xBE, 0x05,
9442 0xF4, 0x85, 0x03, 0xA0,
9443 0xC4, 0x05, 0xF4, 0x85, 0x01, 0xA0, 0xCE, 0x05, 0x88, 0x00, 0x80, 0x63,
9444 0xCC, 0x86, 0x07, 0xA0,
9445 0xEE, 0x05, 0x5F, 0x00, 0x00, 0x2B, 0xDF, 0x08, 0x00, 0xA2, 0xE6, 0x05,
9446 0x80, 0x67, 0x80, 0x63,
9447 0x01, 0xA2, 0x7A, 0x06, 0x7C, 0x85, 0x06, 0x23, 0x68, 0x98, 0x48, 0x23,
9448 0xF8, 0x88, 0x07, 0x23,
9449 0x80, 0x00, 0x06, 0x87, 0x80, 0x63, 0x7C, 0x85, 0x00, 0x23, 0xDF, 0x00,
9450 0x00, 0x63, 0x4A, 0x00,
9451 0x06, 0x61, 0x00, 0xA2, 0x36, 0x06, 0x1D, 0x01, 0x16, 0xD4, 0xC0, 0x23,
9452 0x07, 0x41, 0x83, 0x03,
9453 0x80, 0x63, 0x06, 0xA6, 0x1C, 0x06, 0x00, 0x33, 0x37, 0x00, 0xC2, 0x88,
9454 0x1D, 0x01, 0x01, 0xD6,
9455 0x20, 0x23, 0x63, 0x60, 0x83, 0x03, 0x80, 0x63, 0x02, 0x23, 0xDF, 0x00,
9456 0x07, 0xA6, 0x7C, 0x05,
9457 0xEF, 0x04, 0x6F, 0x00, 0x00, 0x63, 0x4B, 0x00, 0x06, 0x41, 0xCB, 0x00,
9458 0x52, 0x00, 0x06, 0x61,
9459 0x00, 0xA2, 0x4E, 0x06, 0x1D, 0x01, 0x03, 0xCA, 0xC0, 0x23, 0x07, 0x41,
9460 0x00, 0x63, 0x1D, 0x01,
9461 0x04, 0xCC, 0x00, 0x33, 0x00, 0x83, 0xC0, 0x20, 0x81, 0x62, 0x80, 0x23,
9462 0x07, 0x41, 0x00, 0x63,
9463 0x80, 0x67, 0x08, 0x23, 0x83, 0x03, 0x80, 0x63, 0x00, 0x63, 0x01, 0x23,
9464 0xDF, 0x00, 0x06, 0xA6,
9465 0x84, 0x06, 0x07, 0xA6, 0x7C, 0x05, 0x80, 0x67, 0x80, 0x63, 0x00, 0x33,
9466 0x00, 0x40, 0xC0, 0x20,
9467 0x81, 0x62, 0x00, 0x63, 0x00, 0x00, 0xFE, 0x95, 0x83, 0x03, 0x80, 0x63,
9468 0x06, 0xA6, 0x94, 0x06,
9469 0x07, 0xA6, 0x7C, 0x05, 0x00, 0x00, 0x01, 0xA0, 0x14, 0x07, 0x00, 0x2B,
9470 0x40, 0x0E, 0x80, 0x63,
9471 0x01, 0x00, 0x06, 0xA6, 0xAA, 0x06, 0x07, 0xA6, 0x7C, 0x05, 0x40, 0x0E,
9472 0x80, 0x63, 0x00, 0x43,
9473 0x00, 0xA0, 0xA2, 0x06, 0x06, 0xA6, 0xBC, 0x06, 0x07, 0xA6, 0x7C, 0x05,
9474 0x80, 0x67, 0x40, 0x0E,
9475 0x80, 0x63, 0x07, 0xA6, 0x7C, 0x05, 0x00, 0x23, 0xDF, 0x00, 0x00, 0x63,
9476 0x07, 0xA6, 0xD6, 0x06,
9477 0x00, 0x33, 0x2A, 0x00, 0xC2, 0x88, 0x03, 0x03, 0x80, 0x63, 0x89, 0x00,
9478 0x0A, 0x2B, 0x07, 0xA6,
9479 0xE8, 0x06, 0x00, 0x33, 0x29, 0x00, 0xC2, 0x88, 0x00, 0x43, 0x00, 0xA2,
9480 0xF4, 0x06, 0xC0, 0x0E,
9481 0x80, 0x63, 0xDE, 0x86, 0xC0, 0x0E, 0x00, 0x33, 0x00, 0x80, 0xC0, 0x20,
9482 0x81, 0x62, 0x04, 0x01,
9483 0x02, 0xDA, 0x80, 0x63, 0x7C, 0x85, 0x80, 0x7B, 0x80, 0x63, 0x06, 0xA6,
9484 0x8C, 0x06, 0x00, 0x33,
9485 0x2C, 0x00, 0xC2, 0x88, 0x0C, 0xA2, 0x2E, 0x07, 0xFE, 0x95, 0x83, 0x03,
9486 0x80, 0x63, 0x06, 0xA6,
9487 0x2C, 0x07, 0x07, 0xA6, 0x7C, 0x05, 0x00, 0x33, 0x3D, 0x00, 0xC2, 0x88,
9488 0x00, 0x00, 0x80, 0x67,
9489 0x83, 0x03, 0x80, 0x63, 0x0C, 0xA0, 0x44, 0x07, 0x07, 0xA6, 0x7C, 0x05,
9490 0xBF, 0x23, 0x04, 0x61,
9491 0x84, 0x01, 0xE6, 0x84, 0x00, 0x63, 0xF0, 0x04, 0x01, 0x01, 0xF1, 0x00,
9492 0x00, 0x01, 0xF2, 0x00,
9493 0x01, 0x05, 0x80, 0x01, 0x72, 0x04, 0x71, 0x00, 0x81, 0x01, 0x70, 0x04,
9494 0x80, 0x05, 0x81, 0x05,
9495 0x00, 0x63, 0xF0, 0x04, 0xF2, 0x00, 0x72, 0x04, 0x01, 0x01, 0xF1, 0x00,
9496 0x70, 0x00, 0x81, 0x01,
9497 0x70, 0x04, 0x71, 0x00, 0x81, 0x01, 0x72, 0x00, 0x80, 0x01, 0x71, 0x04,
9498 0x70, 0x00, 0x80, 0x01,
9499 0x70, 0x04, 0x00, 0x63, 0xF0, 0x04, 0xF2, 0x00, 0x72, 0x04, 0x00, 0x01,
9500 0xF1, 0x00, 0x70, 0x00,
9501 0x80, 0x01, 0x70, 0x04, 0x71, 0x00, 0x80, 0x01, 0x72, 0x00, 0x81, 0x01,
9502 0x71, 0x04, 0x70, 0x00,
9503 0x81, 0x01, 0x70, 0x04, 0x00, 0x63, 0x00, 0x23, 0xB3, 0x01, 0x83, 0x05,
9504 0xA3, 0x01, 0xA2, 0x01,
9505 0xA1, 0x01, 0x01, 0x23, 0xA0, 0x01, 0x00, 0x01, 0xC8, 0x00, 0x03, 0xA1,
9506 0xC4, 0x07, 0x00, 0x33,
9507 0x07, 0x00, 0xC2, 0x88, 0x80, 0x05, 0x81, 0x05, 0x04, 0x01, 0x11, 0xC8,
9508 0x48, 0x00, 0xB0, 0x01,
9509 0xB1, 0x01, 0x08, 0x23, 0xB2, 0x01, 0x05, 0x01, 0x48, 0x04, 0x00, 0x43,
9510 0x00, 0xA2, 0xE4, 0x07,
9511 0x00, 0x05, 0xDA, 0x87, 0x00, 0x01, 0xC8, 0x00, 0xFF, 0x23, 0x80, 0x01,
9512 0x05, 0x05, 0x00, 0x63,
9513 0xF7, 0x04, 0x1A, 0x09, 0xF6, 0x08, 0x6E, 0x04, 0x00, 0x02, 0x80, 0x43,
9514 0x76, 0x08, 0x80, 0x02,
9515 0x77, 0x04, 0x00, 0x63, 0xF7, 0x04, 0x1A, 0x09, 0xF6, 0x08, 0x6E, 0x04,
9516 0x00, 0x02, 0x00, 0xA0,
9517 0x14, 0x08, 0x16, 0x88, 0x00, 0x43, 0x76, 0x08, 0x80, 0x02, 0x77, 0x04,
9518 0x00, 0x63, 0xF3, 0x04,
9519 0x00, 0x23, 0xF4, 0x00, 0x74, 0x00, 0x80, 0x43, 0xF4, 0x00, 0xCF, 0x40,
9520 0x00, 0xA2, 0x44, 0x08,
9521 0x74, 0x04, 0x02, 0x01, 0xF7, 0xC9, 0xF6, 0xD9, 0x00, 0x01, 0x01, 0xA1,
9522 0x24, 0x08, 0x04, 0x98,
9523 0x26, 0x95, 0x24, 0x88, 0x73, 0x04, 0x00, 0x63, 0xF3, 0x04, 0x75, 0x04,
9524 0x5A, 0x88, 0x02, 0x01,
9525 0x04, 0xD8, 0x46, 0x97, 0x04, 0x98, 0x26, 0x95, 0x4A, 0x88, 0x75, 0x00,
9526 0x00, 0xA3, 0x64, 0x08,
9527 0x00, 0x05, 0x4E, 0x88, 0x73, 0x04, 0x00, 0x63, 0x80, 0x7B, 0x80, 0x63,
9528 0x06, 0xA6, 0x76, 0x08,
9529 0x00, 0x33, 0x3E, 0x00, 0xC2, 0x88, 0x80, 0x67, 0x83, 0x03, 0x80, 0x63,
9530 0x00, 0x63, 0x38, 0x2B,
9531 0x9C, 0x88, 0x38, 0x2B, 0x92, 0x88, 0x32, 0x09, 0x31, 0x05, 0x92, 0x98,
9532 0x05, 0x05, 0xB2, 0x09,
9533 0x00, 0x63, 0x00, 0x32, 0x00, 0x36, 0x00, 0x3A, 0x00, 0x3E, 0x00, 0x63,
9534 0x80, 0x32, 0x80, 0x36,
9535 0x80, 0x3A, 0x80, 0x3E, 0xB4, 0x3D, 0x00, 0x63, 0x38, 0x2B, 0x40, 0x32,
9536 0x40, 0x36, 0x40, 0x3A,
9537 0x40, 0x3E, 0x00, 0x63, 0x5A, 0x20, 0xC9, 0x40, 0x00, 0xA0, 0xB4, 0x08,
9538 0x5D, 0x00, 0xFE, 0xC3,
9539 0x00, 0x63, 0x80, 0x73, 0xE6, 0x20, 0x02, 0x23, 0xE8, 0x00, 0x82, 0x73,
9540 0xFF, 0xFD, 0x80, 0x73,
9541 0x13, 0x23, 0xF8, 0x88, 0x66, 0x20, 0xC0, 0x20, 0x04, 0x23, 0xA0, 0x01,
9542 0xA1, 0x23, 0xA1, 0x01,
9543 0x81, 0x62, 0xE2, 0x88, 0x80, 0x73, 0x80, 0x77, 0x68, 0x00, 0x00, 0xA2,
9544 0x80, 0x00, 0x03, 0xC2,
9545 0xF1, 0xC7, 0x41, 0x23, 0xF8, 0x88, 0x11, 0x23, 0xA1, 0x01, 0x04, 0x23,
9546 0xA0, 0x01, 0xE6, 0x84,
9549 static ushort _asc_mcode_size = sizeof(_asc_mcode_buf);
9550 static ADV_DCNT _asc_mcode_chksum = 0x012C453FUL;
9552 #define ASC_SYN_OFFSET_ONE_DISABLE_LIST 16
9553 static uchar _syn_offset_one_disable_cmd[ASC_SYN_OFFSET_ONE_DISABLE_LIST] = {
9572 static int AscExeScsiQueue(ASC_DVC_VAR *asc_dvc, ASC_SCSI_Q *scsiq)
9575 ulong last_int_level;
9578 int disable_syn_offset_one_fix;
9581 ASC_EXE_CALLBACK asc_exe_callback;
9582 ushort sg_entry_cnt = 0;
9583 ushort sg_entry_cnt_minus_one = 0;
9590 ASC_SG_HEAD *sg_head;
9593 iop_base = asc_dvc->iop_base;
9594 sg_head = scsiq->sg_head;
9595 asc_exe_callback = asc_dvc->exe_callback;
9596 if (asc_dvc->err_code != 0)
9598 if (scsiq == (ASC_SCSI_Q *)0L) {
9599 AscSetLibErrorCode(asc_dvc, ASCQ_ERR_SCSIQ_NULL_PTR);
9603 if ((scsiq->q2.tag_code & ASC_TAG_FLAG_EXTRA_BYTES) == 0) {
9604 scsiq->q1.extra_bytes = 0;
9607 target_ix = scsiq->q2.target_ix;
9608 tid_no = ASC_TIX_TO_TID(target_ix);
9610 if (scsiq->cdbptr[0] == REQUEST_SENSE) {
9611 if ((asc_dvc->init_sdtr & scsiq->q1.target_id) != 0) {
9612 asc_dvc->sdtr_done &= ~scsiq->q1.target_id;
9613 sdtr_data = AscGetMCodeInitSDTRAtID(iop_base, tid_no);
9614 AscMsgOutSDTR(asc_dvc,
9616 sdtr_period_tbl[(sdtr_data >> 4) &
9620 (uchar)(sdtr_data & (uchar)
9621 ASC_SYN_MAX_OFFSET));
9622 scsiq->q1.cntl |= (QC_MSG_OUT | QC_URGENT);
9625 last_int_level = DvcEnterCritical();
9626 if (asc_dvc->in_critical_cnt != 0) {
9627 DvcLeaveCritical(last_int_level);
9628 AscSetLibErrorCode(asc_dvc, ASCQ_ERR_CRITICAL_RE_ENTRY);
9631 asc_dvc->in_critical_cnt++;
9632 if ((scsiq->q1.cntl & QC_SG_HEAD) != 0) {
9633 if ((sg_entry_cnt = sg_head->entry_cnt) == 0) {
9634 asc_dvc->in_critical_cnt--;
9635 DvcLeaveCritical(last_int_level);
9638 #if !CC_VERY_LONG_SG_LIST
9639 if (sg_entry_cnt > ASC_MAX_SG_LIST) {
9640 asc_dvc->in_critical_cnt--;
9641 DvcLeaveCritical(last_int_level);
9644 #endif /* !CC_VERY_LONG_SG_LIST */
9645 if (sg_entry_cnt == 1) {
9646 scsiq->q1.data_addr =
9647 (ADV_PADDR)sg_head->sg_list[0].addr;
9648 scsiq->q1.data_cnt =
9649 (ADV_DCNT)sg_head->sg_list[0].bytes;
9650 scsiq->q1.cntl &= ~(QC_SG_HEAD | QC_SG_SWAP_QUEUE);
9652 sg_entry_cnt_minus_one = sg_entry_cnt - 1;
9654 scsi_cmd = scsiq->cdbptr[0];
9655 disable_syn_offset_one_fix = FALSE;
9656 if ((asc_dvc->pci_fix_asyn_xfer & scsiq->q1.target_id) &&
9657 !(asc_dvc->pci_fix_asyn_xfer_always & scsiq->q1.target_id)) {
9658 if (scsiq->q1.cntl & QC_SG_HEAD) {
9660 for (i = 0; i < sg_entry_cnt; i++) {
9662 (ADV_DCNT)le32_to_cpu(sg_head->sg_list[i].
9666 data_cnt = le32_to_cpu(scsiq->q1.data_cnt);
9668 if (data_cnt != 0UL) {
9669 if (data_cnt < 512UL) {
9670 disable_syn_offset_one_fix = TRUE;
9672 for (i = 0; i < ASC_SYN_OFFSET_ONE_DISABLE_LIST;
9675 _syn_offset_one_disable_cmd[i];
9676 if (disable_cmd == 0xFF) {
9679 if (scsi_cmd == disable_cmd) {
9680 disable_syn_offset_one_fix =
9688 if (disable_syn_offset_one_fix) {
9689 scsiq->q2.tag_code &= ~MSG_SIMPLE_TAG;
9690 scsiq->q2.tag_code |= (ASC_TAG_FLAG_DISABLE_ASYN_USE_SYN_FIX |
9691 ASC_TAG_FLAG_DISABLE_DISCONNECT);
9693 scsiq->q2.tag_code &= 0x27;
9695 if ((scsiq->q1.cntl & QC_SG_HEAD) != 0) {
9696 if (asc_dvc->bug_fix_cntl) {
9697 if (asc_dvc->bug_fix_cntl & ASC_BUG_FIX_IF_NOT_DWB) {
9698 if ((scsi_cmd == READ_6) ||
9699 (scsi_cmd == READ_10)) {
9701 (ADV_PADDR)le32_to_cpu(sg_head->
9703 [sg_entry_cnt_minus_one].
9705 (ADV_DCNT)le32_to_cpu(sg_head->
9707 [sg_entry_cnt_minus_one].
9710 (uchar)((ushort)addr & 0x0003);
9711 if ((extra_bytes != 0)
9715 ASC_TAG_FLAG_EXTRA_BYTES)
9717 scsiq->q2.tag_code |=
9718 ASC_TAG_FLAG_EXTRA_BYTES;
9719 scsiq->q1.extra_bytes =
9722 le32_to_cpu(sg_head->
9724 [sg_entry_cnt_minus_one].
9727 (ASC_DCNT) extra_bytes;
9730 [sg_entry_cnt_minus_one].
9732 cpu_to_le32(data_cnt);
9737 sg_head->entry_to_copy = sg_head->entry_cnt;
9738 #if CC_VERY_LONG_SG_LIST
9740 * Set the sg_entry_cnt to the maximum possible. The rest of
9741 * the SG elements will be copied when the RISC completes the
9742 * SG elements that fit and halts.
9744 if (sg_entry_cnt > ASC_MAX_SG_LIST) {
9745 sg_entry_cnt = ASC_MAX_SG_LIST;
9747 #endif /* CC_VERY_LONG_SG_LIST */
9748 n_q_required = AscSgListToQueue(sg_entry_cnt);
9749 if ((AscGetNumOfFreeQueue(asc_dvc, target_ix, n_q_required) >=
9750 (uint) n_q_required)
9751 || ((scsiq->q1.cntl & QC_URGENT) != 0)) {
9753 AscSendScsiQueue(asc_dvc, scsiq,
9754 n_q_required)) == 1) {
9755 asc_dvc->in_critical_cnt--;
9756 if (asc_exe_callback != 0) {
9757 (*asc_exe_callback) (asc_dvc, scsiq);
9759 DvcLeaveCritical(last_int_level);
9764 if (asc_dvc->bug_fix_cntl) {
9765 if (asc_dvc->bug_fix_cntl & ASC_BUG_FIX_IF_NOT_DWB) {
9766 if ((scsi_cmd == READ_6) ||
9767 (scsi_cmd == READ_10)) {
9769 le32_to_cpu(scsiq->q1.data_addr) +
9770 le32_to_cpu(scsiq->q1.data_cnt);
9772 (uchar)((ushort)addr & 0x0003);
9773 if ((extra_bytes != 0)
9777 ASC_TAG_FLAG_EXTRA_BYTES)
9780 le32_to_cpu(scsiq->q1.
9782 if (((ushort)data_cnt & 0x01FF)
9784 scsiq->q2.tag_code |=
9785 ASC_TAG_FLAG_EXTRA_BYTES;
9786 data_cnt -= (ASC_DCNT)
9788 scsiq->q1.data_cnt =
9791 scsiq->q1.extra_bytes =
9799 if ((AscGetNumOfFreeQueue(asc_dvc, target_ix, 1) >= 1) ||
9800 ((scsiq->q1.cntl & QC_URGENT) != 0)) {
9801 if ((sta = AscSendScsiQueue(asc_dvc, scsiq,
9802 n_q_required)) == 1) {
9803 asc_dvc->in_critical_cnt--;
9804 if (asc_exe_callback != 0) {
9805 (*asc_exe_callback) (asc_dvc, scsiq);
9807 DvcLeaveCritical(last_int_level);
9812 asc_dvc->in_critical_cnt--;
9813 DvcLeaveCritical(last_int_level);
9818 AscSendScsiQueue(ASC_DVC_VAR *asc_dvc, ASC_SCSI_Q *scsiq, uchar n_q_required)
9827 iop_base = asc_dvc->iop_base;
9828 target_ix = scsiq->q2.target_ix;
9829 tid_no = ASC_TIX_TO_TID(target_ix);
9831 free_q_head = (uchar)AscGetVarFreeQHead(iop_base);
9832 if (n_q_required > 1) {
9833 if ((next_qp = AscAllocMultipleFreeQueue(iop_base,
9834 free_q_head, (uchar)
9836 != (uchar)ASC_QLINK_END) {
9837 asc_dvc->last_q_shortage = 0;
9838 scsiq->sg_head->queue_cnt = n_q_required - 1;
9839 scsiq->q1.q_no = free_q_head;
9840 if ((sta = AscPutReadySgListQueue(asc_dvc, scsiq,
9841 free_q_head)) == 1) {
9842 AscPutVarFreeQHead(iop_base, next_qp);
9843 asc_dvc->cur_total_qng += (uchar)(n_q_required);
9844 asc_dvc->cur_dvc_qng[tid_no]++;
9848 } else if (n_q_required == 1) {
9849 if ((next_qp = AscAllocFreeQueue(iop_base,
9852 scsiq->q1.q_no = free_q_head;
9853 if ((sta = AscPutReadyQueue(asc_dvc, scsiq,
9854 free_q_head)) == 1) {
9855 AscPutVarFreeQHead(iop_base, next_qp);
9856 asc_dvc->cur_total_qng++;
9857 asc_dvc->cur_dvc_qng[tid_no]++;
9865 static int AscSgListToQueue(int sg_list)
9869 n_sg_list_qs = ((sg_list - 1) / ASC_SG_LIST_PER_Q);
9870 if (((sg_list - 1) % ASC_SG_LIST_PER_Q) != 0)
9872 return (n_sg_list_qs + 1);
9876 AscGetNumOfFreeQueue(ASC_DVC_VAR *asc_dvc, uchar target_ix, uchar n_qs)
9880 ASC_SCSI_BIT_ID_TYPE target_id;
9883 target_id = ASC_TIX_TO_TARGET_ID(target_ix);
9884 tid_no = ASC_TIX_TO_TID(target_ix);
9885 if ((asc_dvc->unit_not_ready & target_id) ||
9886 (asc_dvc->queue_full_or_busy & target_id)) {
9890 cur_used_qs = (uint) asc_dvc->cur_total_qng +
9891 (uint) asc_dvc->last_q_shortage + (uint) ASC_MIN_FREE_Q;
9893 cur_used_qs = (uint) asc_dvc->cur_total_qng +
9894 (uint) ASC_MIN_FREE_Q;
9896 if ((uint) (cur_used_qs + n_qs) <= (uint) asc_dvc->max_total_qng) {
9897 cur_free_qs = (uint) asc_dvc->max_total_qng - cur_used_qs;
9898 if (asc_dvc->cur_dvc_qng[tid_no] >=
9899 asc_dvc->max_dvc_qng[tid_no]) {
9902 return (cur_free_qs);
9905 if ((n_qs > asc_dvc->last_q_shortage)
9906 && (n_qs <= (asc_dvc->max_total_qng - ASC_MIN_FREE_Q))) {
9907 asc_dvc->last_q_shortage = n_qs;
9913 static int AscPutReadyQueue(ASC_DVC_VAR *asc_dvc, ASC_SCSI_Q *scsiq, uchar q_no)
9918 uchar syn_period_ix;
9922 iop_base = asc_dvc->iop_base;
9923 if (((asc_dvc->init_sdtr & scsiq->q1.target_id) != 0) &&
9924 ((asc_dvc->sdtr_done & scsiq->q1.target_id) == 0)) {
9925 tid_no = ASC_TIX_TO_TID(scsiq->q2.target_ix);
9926 sdtr_data = AscGetMCodeInitSDTRAtID(iop_base, tid_no);
9928 (sdtr_data >> 4) & (asc_dvc->max_sdtr_index - 1);
9929 syn_offset = sdtr_data & ASC_SYN_MAX_OFFSET;
9930 AscMsgOutSDTR(asc_dvc,
9931 asc_dvc->sdtr_period_tbl[syn_period_ix],
9933 scsiq->q1.cntl |= QC_MSG_OUT;
9935 q_addr = ASC_QNO_TO_QADDR(q_no);
9936 if ((scsiq->q1.target_id & asc_dvc->use_tagged_qng) == 0) {
9937 scsiq->q2.tag_code &= ~MSG_SIMPLE_TAG;
9939 scsiq->q1.status = QS_FREE;
9940 AscMemWordCopyPtrToLram(iop_base,
9941 q_addr + ASC_SCSIQ_CDB_BEG,
9942 (uchar *)scsiq->cdbptr, scsiq->q2.cdb_len >> 1);
9944 DvcPutScsiQ(iop_base,
9945 q_addr + ASC_SCSIQ_CPY_BEG,
9946 (uchar *)&scsiq->q1.cntl,
9947 ((sizeof(ASC_SCSIQ_1) + sizeof(ASC_SCSIQ_2)) / 2) - 1);
9948 AscWriteLramWord(iop_base,
9949 (ushort)(q_addr + (ushort)ASC_SCSIQ_B_STATUS),
9950 (ushort)(((ushort)scsiq->q1.
9951 q_no << 8) | (ushort)QS_READY));
9956 AscPutReadySgListQueue(ASC_DVC_VAR *asc_dvc, ASC_SCSI_Q *scsiq, uchar q_no)
9960 ASC_SG_HEAD *sg_head;
9961 ASC_SG_LIST_Q scsi_sg_q;
9962 ASC_DCNT saved_data_addr;
9963 ASC_DCNT saved_data_cnt;
9965 ushort sg_list_dwords;
9967 ushort sg_entry_cnt;
9971 iop_base = asc_dvc->iop_base;
9972 sg_head = scsiq->sg_head;
9973 saved_data_addr = scsiq->q1.data_addr;
9974 saved_data_cnt = scsiq->q1.data_cnt;
9975 scsiq->q1.data_addr = (ASC_PADDR) sg_head->sg_list[0].addr;
9976 scsiq->q1.data_cnt = (ASC_DCNT) sg_head->sg_list[0].bytes;
9977 #if CC_VERY_LONG_SG_LIST
9979 * If sg_head->entry_cnt is greater than ASC_MAX_SG_LIST
9980 * then not all SG elements will fit in the allocated queues.
9981 * The rest of the SG elements will be copied when the RISC
9982 * completes the SG elements that fit and halts.
9984 if (sg_head->entry_cnt > ASC_MAX_SG_LIST) {
9986 * Set sg_entry_cnt to be the number of SG elements that
9987 * will fit in the allocated SG queues. It is minus 1, because
9988 * the first SG element is handled above. ASC_MAX_SG_LIST is
9989 * already inflated by 1 to account for this. For example it
9990 * may be 50 which is 1 + 7 queues * 7 SG elements.
9992 sg_entry_cnt = ASC_MAX_SG_LIST - 1;
9995 * Keep track of remaining number of SG elements that will
9996 * need to be handled from a_isr.c.
9998 scsiq->remain_sg_entry_cnt =
9999 sg_head->entry_cnt - ASC_MAX_SG_LIST;
10001 #endif /* CC_VERY_LONG_SG_LIST */
10003 * Set sg_entry_cnt to be the number of SG elements that
10004 * will fit in the allocated SG queues. It is minus 1, because
10005 * the first SG element is handled above.
10007 sg_entry_cnt = sg_head->entry_cnt - 1;
10008 #if CC_VERY_LONG_SG_LIST
10010 #endif /* CC_VERY_LONG_SG_LIST */
10011 if (sg_entry_cnt != 0) {
10012 scsiq->q1.cntl |= QC_SG_HEAD;
10013 q_addr = ASC_QNO_TO_QADDR(q_no);
10015 scsiq->q1.sg_queue_cnt = sg_head->queue_cnt;
10016 scsi_sg_q.sg_head_qp = q_no;
10017 scsi_sg_q.cntl = QCSG_SG_XFER_LIST;
10018 for (i = 0; i < sg_head->queue_cnt; i++) {
10019 scsi_sg_q.seq_no = i + 1;
10020 if (sg_entry_cnt > ASC_SG_LIST_PER_Q) {
10021 sg_list_dwords = (uchar)(ASC_SG_LIST_PER_Q * 2);
10022 sg_entry_cnt -= ASC_SG_LIST_PER_Q;
10024 scsi_sg_q.sg_list_cnt =
10026 scsi_sg_q.sg_cur_list_cnt =
10029 scsi_sg_q.sg_list_cnt =
10030 ASC_SG_LIST_PER_Q - 1;
10031 scsi_sg_q.sg_cur_list_cnt =
10032 ASC_SG_LIST_PER_Q - 1;
10035 #if CC_VERY_LONG_SG_LIST
10037 * This is the last SG queue in the list of
10038 * allocated SG queues. If there are more
10039 * SG elements than will fit in the allocated
10040 * queues, then set the QCSG_SG_XFER_MORE flag.
10042 if (sg_head->entry_cnt > ASC_MAX_SG_LIST) {
10043 scsi_sg_q.cntl |= QCSG_SG_XFER_MORE;
10045 #endif /* CC_VERY_LONG_SG_LIST */
10046 scsi_sg_q.cntl |= QCSG_SG_XFER_END;
10047 #if CC_VERY_LONG_SG_LIST
10049 #endif /* CC_VERY_LONG_SG_LIST */
10050 sg_list_dwords = sg_entry_cnt << 1;
10052 scsi_sg_q.sg_list_cnt = sg_entry_cnt;
10053 scsi_sg_q.sg_cur_list_cnt =
10056 scsi_sg_q.sg_list_cnt =
10058 scsi_sg_q.sg_cur_list_cnt =
10063 next_qp = AscReadLramByte(iop_base,
10066 scsi_sg_q.q_no = next_qp;
10067 q_addr = ASC_QNO_TO_QADDR(next_qp);
10068 AscMemWordCopyPtrToLram(iop_base,
10069 q_addr + ASC_SCSIQ_SGHD_CPY_BEG,
10070 (uchar *)&scsi_sg_q,
10071 sizeof(ASC_SG_LIST_Q) >> 1);
10072 AscMemDWordCopyPtrToLram(iop_base,
10073 q_addr + ASC_SGQ_LIST_BEG,
10074 (uchar *)&sg_head->
10077 sg_index += ASC_SG_LIST_PER_Q;
10078 scsiq->next_sg_index = sg_index;
10081 scsiq->q1.cntl &= ~QC_SG_HEAD;
10083 sta = AscPutReadyQueue(asc_dvc, scsiq, q_no);
10084 scsiq->q1.data_addr = saved_data_addr;
10085 scsiq->q1.data_cnt = saved_data_cnt;
10090 AscSetRunChipSynRegAtID(PortAddr iop_base, uchar tid_no, uchar sdtr_data)
10094 if (AscHostReqRiscHalt(iop_base)) {
10095 sta = AscSetChipSynRegAtID(iop_base, tid_no, sdtr_data);
10096 AscStartChip(iop_base);
10102 static int AscSetChipSynRegAtID(PortAddr iop_base, uchar id, uchar sdtr_data)
10104 ASC_SCSI_BIT_ID_TYPE org_id;
10108 AscSetBank(iop_base, 1);
10109 org_id = AscReadChipDvcID(iop_base);
10110 for (i = 0; i <= ASC_MAX_TID; i++) {
10111 if (org_id == (0x01 << i))
10114 org_id = (ASC_SCSI_BIT_ID_TYPE) i;
10115 AscWriteChipDvcID(iop_base, id);
10116 if (AscReadChipDvcID(iop_base) == (0x01 << id)) {
10117 AscSetBank(iop_base, 0);
10118 AscSetChipSyn(iop_base, sdtr_data);
10119 if (AscGetChipSyn(iop_base) != sdtr_data) {
10125 AscSetBank(iop_base, 1);
10126 AscWriteChipDvcID(iop_base, org_id);
10127 AscSetBank(iop_base, 0);
10131 static ushort AscInitLram(ASC_DVC_VAR *asc_dvc)
10138 iop_base = asc_dvc->iop_base;
10140 AscMemWordSetLram(iop_base, ASC_QADR_BEG, 0,
10141 (ushort)(((int)(asc_dvc->max_total_qng + 2 + 1) *
10144 i = ASC_MIN_ACTIVE_QNO;
10145 s_addr = ASC_QADR_BEG + ASC_QBLK_SIZE;
10146 AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_FWD),
10148 AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_BWD),
10149 (uchar)(asc_dvc->max_total_qng));
10150 AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_QNO),
10153 s_addr += ASC_QBLK_SIZE;
10154 for (; i < asc_dvc->max_total_qng; i++, s_addr += ASC_QBLK_SIZE) {
10155 AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_FWD),
10157 AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_BWD),
10159 AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_QNO),
10162 AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_FWD),
10163 (uchar)ASC_QLINK_END);
10164 AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_BWD),
10165 (uchar)(asc_dvc->max_total_qng - 1));
10166 AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_QNO),
10167 (uchar)asc_dvc->max_total_qng);
10169 s_addr += ASC_QBLK_SIZE;
10170 for (; i <= (uchar)(asc_dvc->max_total_qng + 3);
10171 i++, s_addr += ASC_QBLK_SIZE) {
10172 AscWriteLramByte(iop_base,
10173 (ushort)(s_addr + (ushort)ASC_SCSIQ_B_FWD), i);
10174 AscWriteLramByte(iop_base,
10175 (ushort)(s_addr + (ushort)ASC_SCSIQ_B_BWD), i);
10176 AscWriteLramByte(iop_base,
10177 (ushort)(s_addr + (ushort)ASC_SCSIQ_B_QNO), i);
10179 return (warn_code);
10182 static ushort AscInitQLinkVar(ASC_DVC_VAR *asc_dvc)
10188 iop_base = asc_dvc->iop_base;
10189 AscPutRiscVarFreeQHead(iop_base, 1);
10190 AscPutRiscVarDoneQTail(iop_base, asc_dvc->max_total_qng);
10191 AscPutVarFreeQHead(iop_base, 1);
10192 AscPutVarDoneQTail(iop_base, asc_dvc->max_total_qng);
10193 AscWriteLramByte(iop_base, ASCV_BUSY_QHEAD_B,
10194 (uchar)((int)asc_dvc->max_total_qng + 1));
10195 AscWriteLramByte(iop_base, ASCV_DISC1_QHEAD_B,
10196 (uchar)((int)asc_dvc->max_total_qng + 2));
10197 AscWriteLramByte(iop_base, (ushort)ASCV_TOTAL_READY_Q_B,
10198 asc_dvc->max_total_qng);
10199 AscWriteLramWord(iop_base, ASCV_ASCDVC_ERR_CODE_W, 0);
10200 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
10201 AscWriteLramByte(iop_base, ASCV_STOP_CODE_B, 0);
10202 AscWriteLramByte(iop_base, ASCV_SCSIBUSY_B, 0);
10203 AscWriteLramByte(iop_base, ASCV_WTM_FLAG_B, 0);
10204 AscPutQDoneInProgress(iop_base, 0);
10205 lram_addr = ASC_QADR_BEG;
10206 for (i = 0; i < 32; i++, lram_addr += 2) {
10207 AscWriteLramWord(iop_base, lram_addr, 0);
10212 static int AscSetLibErrorCode(ASC_DVC_VAR *asc_dvc, ushort err_code)
10214 if (asc_dvc->err_code == 0) {
10215 asc_dvc->err_code = err_code;
10216 AscWriteLramWord(asc_dvc->iop_base, ASCV_ASCDVC_ERR_CODE_W,
10223 AscMsgOutSDTR(ASC_DVC_VAR *asc_dvc, uchar sdtr_period, uchar sdtr_offset)
10226 uchar sdtr_period_index;
10229 iop_base = asc_dvc->iop_base;
10230 sdtr_buf.msg_type = MS_EXTEND;
10231 sdtr_buf.msg_len = MS_SDTR_LEN;
10232 sdtr_buf.msg_req = MS_SDTR_CODE;
10233 sdtr_buf.xfer_period = sdtr_period;
10234 sdtr_offset &= ASC_SYN_MAX_OFFSET;
10235 sdtr_buf.req_ack_offset = sdtr_offset;
10236 if ((sdtr_period_index =
10237 AscGetSynPeriodIndex(asc_dvc, sdtr_period)) <=
10238 asc_dvc->max_sdtr_index) {
10239 AscMemWordCopyPtrToLram(iop_base,
10241 (uchar *)&sdtr_buf,
10242 sizeof(EXT_MSG) >> 1);
10243 return ((sdtr_period_index << 4) | sdtr_offset);
10246 sdtr_buf.req_ack_offset = 0;
10247 AscMemWordCopyPtrToLram(iop_base,
10249 (uchar *)&sdtr_buf,
10250 sizeof(EXT_MSG) >> 1);
10256 AscCalSDTRData(ASC_DVC_VAR *asc_dvc, uchar sdtr_period, uchar syn_offset)
10259 uchar sdtr_period_ix;
10261 sdtr_period_ix = AscGetSynPeriodIndex(asc_dvc, sdtr_period);
10262 if ((sdtr_period_ix > asc_dvc->max_sdtr_index)
10266 byte = (sdtr_period_ix << 4) | (syn_offset & ASC_SYN_MAX_OFFSET);
10270 static void AscSetChipSDTR(PortAddr iop_base, uchar sdtr_data, uchar tid_no)
10272 AscSetChipSynRegAtID(iop_base, tid_no, sdtr_data);
10273 AscPutMCodeSDTRDoneAtID(iop_base, tid_no, sdtr_data);
10277 static uchar AscGetSynPeriodIndex(ASC_DVC_VAR *asc_dvc, uchar syn_time)
10279 uchar *period_table;
10284 period_table = asc_dvc->sdtr_period_tbl;
10285 max_index = (int)asc_dvc->max_sdtr_index;
10286 min_index = (int)asc_dvc->host_init_sdtr_index;
10287 if ((syn_time <= period_table[max_index])) {
10288 for (i = min_index; i < (max_index - 1); i++) {
10289 if (syn_time <= period_table[i]) {
10293 return ((uchar)max_index);
10295 return ((uchar)(max_index + 1));
10299 static uchar AscAllocFreeQueue(PortAddr iop_base, uchar free_q_head)
10305 q_addr = ASC_QNO_TO_QADDR(free_q_head);
10306 q_status = (uchar)AscReadLramByte(iop_base,
10308 ASC_SCSIQ_B_STATUS));
10309 next_qp = AscReadLramByte(iop_base, (ushort)(q_addr + ASC_SCSIQ_B_FWD));
10310 if (((q_status & QS_READY) == 0) && (next_qp != ASC_QLINK_END)) {
10313 return (ASC_QLINK_END);
10317 AscAllocMultipleFreeQueue(PortAddr iop_base, uchar free_q_head, uchar n_free_q)
10321 for (i = 0; i < n_free_q; i++) {
10322 if ((free_q_head = AscAllocFreeQueue(iop_base, free_q_head))
10323 == ASC_QLINK_END) {
10324 return (ASC_QLINK_END);
10327 return (free_q_head);
10330 static int AscHostReqRiscHalt(PortAddr iop_base)
10334 uchar saved_stop_code;
10336 if (AscIsChipHalted(iop_base))
10338 saved_stop_code = AscReadLramByte(iop_base, ASCV_STOP_CODE_B);
10339 AscWriteLramByte(iop_base, ASCV_STOP_CODE_B,
10340 ASC_STOP_HOST_REQ_RISC_HALT | ASC_STOP_REQ_RISC_STOP);
10342 if (AscIsChipHalted(iop_base)) {
10346 DvcSleepMilliSecond(100);
10347 } while (count++ < 20);
10348 AscWriteLramByte(iop_base, ASCV_STOP_CODE_B, saved_stop_code);
10352 static int AscStopQueueExe(PortAddr iop_base)
10356 if (AscReadLramByte(iop_base, ASCV_STOP_CODE_B) == 0) {
10357 AscWriteLramByte(iop_base, ASCV_STOP_CODE_B,
10358 ASC_STOP_REQ_RISC_STOP);
10360 if (AscReadLramByte(iop_base, ASCV_STOP_CODE_B) &
10361 ASC_STOP_ACK_RISC_STOP) {
10364 DvcSleepMilliSecond(100);
10365 } while (count++ < 20);
10370 static void DvcDelayMicroSecond(ADV_DVC_VAR *asc_dvc, ushort micro_sec)
10375 static void DvcDelayNanoSecond(ASC_DVC_VAR *asc_dvc, ASC_DCNT nano_sec)
10377 udelay((nano_sec + 999) / 1000);
10381 static ASC_DCNT __init AscGetEisaProductID(PortAddr iop_base)
10384 ushort product_id_high, product_id_low;
10385 ASC_DCNT product_id;
10387 eisa_iop = ASC_GET_EISA_SLOT(iop_base) | ASC_EISA_PID_IOP_MASK;
10388 product_id_low = inpw(eisa_iop);
10389 product_id_high = inpw(eisa_iop + 2);
10390 product_id = ((ASC_DCNT) product_id_high << 16) |
10391 (ASC_DCNT) product_id_low;
10392 return (product_id);
10395 static PortAddr __init AscSearchIOPortAddrEISA(PortAddr iop_base)
10397 ASC_DCNT eisa_product_id;
10399 if (iop_base == 0) {
10400 iop_base = ASC_EISA_MIN_IOP_ADDR;
10402 if (iop_base == ASC_EISA_MAX_IOP_ADDR)
10404 if ((iop_base & 0x0050) == 0x0050) {
10405 iop_base += ASC_EISA_BIG_IOP_GAP;
10407 iop_base += ASC_EISA_SMALL_IOP_GAP;
10410 while (iop_base <= ASC_EISA_MAX_IOP_ADDR) {
10411 eisa_product_id = AscGetEisaProductID(iop_base);
10412 if ((eisa_product_id == ASC_EISA_ID_740) ||
10413 (eisa_product_id == ASC_EISA_ID_750)) {
10414 if (AscFindSignature(iop_base)) {
10415 inpw(iop_base + 4);
10419 if (iop_base == ASC_EISA_MAX_IOP_ADDR)
10421 if ((iop_base & 0x0050) == 0x0050) {
10422 iop_base += ASC_EISA_BIG_IOP_GAP;
10424 iop_base += ASC_EISA_SMALL_IOP_GAP;
10429 #endif /* CONFIG_ISA */
10431 static int AscStartChip(PortAddr iop_base)
10433 AscSetChipControl(iop_base, 0);
10434 if ((AscGetChipStatus(iop_base) & CSW_HALTED) != 0) {
10440 static int AscStopChip(PortAddr iop_base)
10445 AscGetChipControl(iop_base) &
10446 (~(CC_SINGLE_STEP | CC_TEST | CC_DIAG));
10447 AscSetChipControl(iop_base, (uchar)(cc_val | CC_HALT));
10448 AscSetChipIH(iop_base, INS_HALT);
10449 AscSetChipIH(iop_base, INS_RFLAG_WTM);
10450 if ((AscGetChipStatus(iop_base) & CSW_HALTED) == 0) {
10456 static int AscIsChipHalted(PortAddr iop_base)
10458 if ((AscGetChipStatus(iop_base) & CSW_HALTED) != 0) {
10459 if ((AscGetChipControl(iop_base) & CC_HALT) != 0) {
10466 static void AscSetChipIH(PortAddr iop_base, ushort ins_code)
10468 AscSetBank(iop_base, 1);
10469 AscWriteChipIH(iop_base, ins_code);
10470 AscSetBank(iop_base, 0);
10474 static void AscAckInterrupt(PortAddr iop_base)
10482 risc_flag = AscReadLramByte(iop_base, ASCV_RISC_FLAG_B);
10483 if (loop++ > 0x7FFF) {
10486 } while ((risc_flag & ASC_RISC_FLAG_GEN_INT) != 0);
10488 AscReadLramByte(iop_base,
10489 ASCV_HOST_FLAG_B) & (~ASC_HOST_FLAG_ACK_INT);
10490 AscWriteLramByte(iop_base, ASCV_HOST_FLAG_B,
10491 (uchar)(host_flag | ASC_HOST_FLAG_ACK_INT));
10492 AscSetChipStatus(iop_base, CIW_INT_ACK);
10494 while (AscGetChipStatus(iop_base) & CSW_INT_PENDING) {
10495 AscSetChipStatus(iop_base, CIW_INT_ACK);
10500 AscWriteLramByte(iop_base, ASCV_HOST_FLAG_B, host_flag);
10504 static void AscDisableInterrupt(PortAddr iop_base)
10508 cfg = AscGetChipCfgLsw(iop_base);
10509 AscSetChipCfgLsw(iop_base, cfg & (~ASC_CFG0_HOST_INT_ON));
10513 static void AscEnableInterrupt(PortAddr iop_base)
10517 cfg = AscGetChipCfgLsw(iop_base);
10518 AscSetChipCfgLsw(iop_base, cfg | ASC_CFG0_HOST_INT_ON);
10522 static void AscSetBank(PortAddr iop_base, uchar bank)
10526 val = AscGetChipControl(iop_base) &
10528 (CC_SINGLE_STEP | CC_TEST | CC_DIAG | CC_SCSI_RESET |
10531 val |= CC_BANK_ONE;
10532 } else if (bank == 2) {
10533 val |= CC_DIAG | CC_BANK_ONE;
10535 val &= ~CC_BANK_ONE;
10537 AscSetChipControl(iop_base, val);
10541 static int AscResetChipAndScsiBus(ASC_DVC_VAR *asc_dvc)
10546 iop_base = asc_dvc->iop_base;
10547 while ((AscGetChipStatus(iop_base) & CSW_SCSI_RESET_ACTIVE)
10549 DvcSleepMilliSecond(100);
10551 AscStopChip(iop_base);
10552 AscSetChipControl(iop_base, CC_CHIP_RESET | CC_SCSI_RESET | CC_HALT);
10553 DvcDelayNanoSecond(asc_dvc, 60000);
10554 AscSetChipIH(iop_base, INS_RFLAG_WTM);
10555 AscSetChipIH(iop_base, INS_HALT);
10556 AscSetChipControl(iop_base, CC_CHIP_RESET | CC_HALT);
10557 AscSetChipControl(iop_base, CC_HALT);
10558 DvcSleepMilliSecond(200);
10559 AscSetChipStatus(iop_base, CIW_CLR_SCSI_RESET_INT);
10560 AscSetChipStatus(iop_base, 0);
10561 return (AscIsChipHalted(iop_base));
10564 static ASC_DCNT __init AscGetMaxDmaCount(ushort bus_type)
10566 if (bus_type & ASC_IS_ISA)
10567 return (ASC_MAX_ISA_DMA_COUNT);
10568 else if (bus_type & (ASC_IS_EISA | ASC_IS_VL))
10569 return (ASC_MAX_VL_DMA_COUNT);
10570 return (ASC_MAX_PCI_DMA_COUNT);
10574 static ushort __init AscGetIsaDmaChannel(PortAddr iop_base)
10578 channel = AscGetChipCfgLsw(iop_base) & 0x0003;
10579 if (channel == 0x03)
10581 else if (channel == 0x00)
10583 return (channel + 4);
10586 static ushort __init AscSetIsaDmaChannel(PortAddr iop_base, ushort dma_channel)
10591 if ((dma_channel >= 5) && (dma_channel <= 7)) {
10592 if (dma_channel == 7)
10595 value = dma_channel - 4;
10596 cfg_lsw = AscGetChipCfgLsw(iop_base) & 0xFFFC;
10598 AscSetChipCfgLsw(iop_base, cfg_lsw);
10599 return (AscGetIsaDmaChannel(iop_base));
10604 static uchar __init AscSetIsaDmaSpeed(PortAddr iop_base, uchar speed_value)
10606 speed_value &= 0x07;
10607 AscSetBank(iop_base, 1);
10608 AscWriteChipDmaSpeed(iop_base, speed_value);
10609 AscSetBank(iop_base, 0);
10610 return (AscGetIsaDmaSpeed(iop_base));
10613 static uchar __init AscGetIsaDmaSpeed(PortAddr iop_base)
10617 AscSetBank(iop_base, 1);
10618 speed_value = AscReadChipDmaSpeed(iop_base);
10619 speed_value &= 0x07;
10620 AscSetBank(iop_base, 0);
10621 return (speed_value);
10623 #endif /* CONFIG_ISA */
10625 static ushort __init
10626 AscReadPCIConfigWord(ASC_DVC_VAR *asc_dvc, ushort pci_config_offset)
10630 lsb = DvcReadPCIConfigByte(asc_dvc, pci_config_offset);
10631 msb = DvcReadPCIConfigByte(asc_dvc, pci_config_offset + 1);
10632 return ((ushort)((msb << 8) | lsb));
10635 static ushort __init AscInitGetConfig(ASC_DVC_VAR *asc_dvc)
10639 ushort PCIDeviceID;
10640 ushort PCIVendorID;
10641 uchar PCIRevisionID;
10642 uchar prevCmdRegBits;
10645 iop_base = asc_dvc->iop_base;
10646 asc_dvc->init_state = ASC_INIT_STATE_BEG_GET_CFG;
10647 if (asc_dvc->err_code != 0) {
10650 if (asc_dvc->bus_type == ASC_IS_PCI) {
10651 PCIVendorID = AscReadPCIConfigWord(asc_dvc,
10652 AscPCIConfigVendorIDRegister);
10654 PCIDeviceID = AscReadPCIConfigWord(asc_dvc,
10655 AscPCIConfigDeviceIDRegister);
10657 PCIRevisionID = DvcReadPCIConfigByte(asc_dvc,
10658 AscPCIConfigRevisionIDRegister);
10660 if (PCIVendorID != PCI_VENDOR_ID_ASP) {
10661 warn_code |= ASC_WARN_SET_PCI_CONFIG_SPACE;
10663 prevCmdRegBits = DvcReadPCIConfigByte(asc_dvc,
10664 AscPCIConfigCommandRegister);
10666 if ((prevCmdRegBits & AscPCICmdRegBits_IOMemBusMaster) !=
10667 AscPCICmdRegBits_IOMemBusMaster) {
10668 DvcWritePCIConfigByte(asc_dvc,
10669 AscPCIConfigCommandRegister,
10671 AscPCICmdRegBits_IOMemBusMaster));
10673 if ((DvcReadPCIConfigByte(asc_dvc,
10674 AscPCIConfigCommandRegister)
10675 & AscPCICmdRegBits_IOMemBusMaster)
10676 != AscPCICmdRegBits_IOMemBusMaster) {
10677 warn_code |= ASC_WARN_SET_PCI_CONFIG_SPACE;
10680 if ((PCIDeviceID == PCI_DEVICE_ID_ASP_1200A) ||
10681 (PCIDeviceID == PCI_DEVICE_ID_ASP_ABP940)) {
10682 DvcWritePCIConfigByte(asc_dvc,
10683 AscPCIConfigLatencyTimer, 0x00);
10684 if (DvcReadPCIConfigByte
10685 (asc_dvc, AscPCIConfigLatencyTimer)
10687 warn_code |= ASC_WARN_SET_PCI_CONFIG_SPACE;
10689 } else if (PCIDeviceID == PCI_DEVICE_ID_ASP_ABP940U) {
10690 if (DvcReadPCIConfigByte(asc_dvc,
10691 AscPCIConfigLatencyTimer) <
10693 DvcWritePCIConfigByte(asc_dvc,
10694 AscPCIConfigLatencyTimer,
10697 if (DvcReadPCIConfigByte(asc_dvc,
10698 AscPCIConfigLatencyTimer)
10701 ASC_WARN_SET_PCI_CONFIG_SPACE;
10707 if (AscFindSignature(iop_base)) {
10708 warn_code |= AscInitAscDvcVar(asc_dvc);
10709 warn_code |= AscInitFromEEP(asc_dvc);
10710 asc_dvc->init_state |= ASC_INIT_STATE_END_GET_CFG;
10711 if (asc_dvc->scsi_reset_wait > ASC_MAX_SCSI_RESET_WAIT) {
10712 asc_dvc->scsi_reset_wait = ASC_MAX_SCSI_RESET_WAIT;
10715 asc_dvc->err_code = ASC_IERR_BAD_SIGNATURE;
10717 return (warn_code);
10720 static ushort __init AscInitSetConfig(ASC_DVC_VAR *asc_dvc)
10722 ushort warn_code = 0;
10724 asc_dvc->init_state |= ASC_INIT_STATE_BEG_SET_CFG;
10725 if (asc_dvc->err_code != 0)
10727 if (AscFindSignature(asc_dvc->iop_base)) {
10728 warn_code |= AscInitFromAscDvcVar(asc_dvc);
10729 asc_dvc->init_state |= ASC_INIT_STATE_END_SET_CFG;
10731 asc_dvc->err_code = ASC_IERR_BAD_SIGNATURE;
10733 return (warn_code);
10736 static ushort __init AscInitFromAscDvcVar(ASC_DVC_VAR *asc_dvc)
10741 ushort pci_device_id = 0;
10743 iop_base = asc_dvc->iop_base;
10745 if (asc_dvc->cfg->dev)
10746 pci_device_id = to_pci_dev(asc_dvc->cfg->dev)->device;
10749 cfg_msw = AscGetChipCfgMsw(iop_base);
10750 if ((cfg_msw & ASC_CFG_MSW_CLR_MASK) != 0) {
10751 cfg_msw &= (~(ASC_CFG_MSW_CLR_MASK));
10752 warn_code |= ASC_WARN_CFG_MSW_RECOVER;
10753 AscSetChipCfgMsw(iop_base, cfg_msw);
10755 if ((asc_dvc->cfg->cmd_qng_enabled & asc_dvc->cfg->disc_enable) !=
10756 asc_dvc->cfg->cmd_qng_enabled) {
10757 asc_dvc->cfg->disc_enable = asc_dvc->cfg->cmd_qng_enabled;
10758 warn_code |= ASC_WARN_CMD_QNG_CONFLICT;
10760 if (AscGetChipStatus(iop_base) & CSW_AUTO_CONFIG) {
10761 warn_code |= ASC_WARN_AUTO_CONFIG;
10763 if ((asc_dvc->bus_type & (ASC_IS_ISA | ASC_IS_VL)) != 0) {
10764 if (AscSetChipIRQ(iop_base, asc_dvc->irq_no, asc_dvc->bus_type)
10765 != asc_dvc->irq_no) {
10766 asc_dvc->err_code |= ASC_IERR_SET_IRQ_NO;
10769 if (asc_dvc->bus_type & ASC_IS_PCI) {
10771 AscSetChipCfgMsw(iop_base, cfg_msw);
10772 if ((asc_dvc->bus_type & ASC_IS_PCI_ULTRA) == ASC_IS_PCI_ULTRA) {
10774 if ((pci_device_id == PCI_DEVICE_ID_ASP_1200A) ||
10775 (pci_device_id == PCI_DEVICE_ID_ASP_ABP940)) {
10776 asc_dvc->bug_fix_cntl |= ASC_BUG_FIX_IF_NOT_DWB;
10777 asc_dvc->bug_fix_cntl |=
10778 ASC_BUG_FIX_ASYN_USE_SYN;
10781 } else if (asc_dvc->bus_type == ASC_IS_ISAPNP) {
10782 if (AscGetChipVersion(iop_base, asc_dvc->bus_type)
10783 == ASC_CHIP_VER_ASYN_BUG) {
10784 asc_dvc->bug_fix_cntl |= ASC_BUG_FIX_ASYN_USE_SYN;
10787 if (AscSetChipScsiID(iop_base, asc_dvc->cfg->chip_scsi_id) !=
10788 asc_dvc->cfg->chip_scsi_id) {
10789 asc_dvc->err_code |= ASC_IERR_SET_SCSI_ID;
10792 if (asc_dvc->bus_type & ASC_IS_ISA) {
10793 AscSetIsaDmaChannel(iop_base, asc_dvc->cfg->isa_dma_channel);
10794 AscSetIsaDmaSpeed(iop_base, asc_dvc->cfg->isa_dma_speed);
10796 #endif /* CONFIG_ISA */
10797 return (warn_code);
10800 static ushort AscInitAsc1000Driver(ASC_DVC_VAR *asc_dvc)
10805 iop_base = asc_dvc->iop_base;
10807 if ((asc_dvc->dvc_cntl & ASC_CNTL_RESET_SCSI) &&
10808 !(asc_dvc->init_state & ASC_INIT_RESET_SCSI_DONE)) {
10809 AscResetChipAndScsiBus(asc_dvc);
10810 DvcSleepMilliSecond((ASC_DCNT)
10811 ((ushort)asc_dvc->scsi_reset_wait * 1000));
10813 asc_dvc->init_state |= ASC_INIT_STATE_BEG_LOAD_MC;
10814 if (asc_dvc->err_code != 0)
10816 if (!AscFindSignature(asc_dvc->iop_base)) {
10817 asc_dvc->err_code = ASC_IERR_BAD_SIGNATURE;
10818 return (warn_code);
10820 AscDisableInterrupt(iop_base);
10821 warn_code |= AscInitLram(asc_dvc);
10822 if (asc_dvc->err_code != 0)
10824 ASC_DBG1(1, "AscInitAsc1000Driver: _asc_mcode_chksum 0x%lx\n",
10825 (ulong)_asc_mcode_chksum);
10826 if (AscLoadMicroCode(iop_base, 0, _asc_mcode_buf,
10827 _asc_mcode_size) != _asc_mcode_chksum) {
10828 asc_dvc->err_code |= ASC_IERR_MCODE_CHKSUM;
10829 return (warn_code);
10831 warn_code |= AscInitMicroCodeVar(asc_dvc);
10832 asc_dvc->init_state |= ASC_INIT_STATE_END_LOAD_MC;
10833 AscEnableInterrupt(iop_base);
10834 return (warn_code);
10837 static ushort __init AscInitAscDvcVar(ASC_DVC_VAR *asc_dvc)
10842 uchar chip_version;
10844 iop_base = asc_dvc->iop_base;
10846 asc_dvc->err_code = 0;
10847 if ((asc_dvc->bus_type &
10848 (ASC_IS_ISA | ASC_IS_PCI | ASC_IS_EISA | ASC_IS_VL)) == 0) {
10849 asc_dvc->err_code |= ASC_IERR_NO_BUS_TYPE;
10851 AscSetChipControl(iop_base, CC_HALT);
10852 AscSetChipStatus(iop_base, 0);
10853 asc_dvc->bug_fix_cntl = 0;
10854 asc_dvc->pci_fix_asyn_xfer = 0;
10855 asc_dvc->pci_fix_asyn_xfer_always = 0;
10856 /* asc_dvc->init_state initalized in AscInitGetConfig(). */
10857 asc_dvc->sdtr_done = 0;
10858 asc_dvc->cur_total_qng = 0;
10859 asc_dvc->is_in_int = 0;
10860 asc_dvc->in_critical_cnt = 0;
10861 asc_dvc->last_q_shortage = 0;
10862 asc_dvc->use_tagged_qng = 0;
10863 asc_dvc->no_scam = 0;
10864 asc_dvc->unit_not_ready = 0;
10865 asc_dvc->queue_full_or_busy = 0;
10866 asc_dvc->redo_scam = 0;
10868 asc_dvc->host_init_sdtr_index = 0;
10869 asc_dvc->cfg->can_tagged_qng = 0;
10870 asc_dvc->cfg->cmd_qng_enabled = 0;
10871 asc_dvc->dvc_cntl = ASC_DEF_DVC_CNTL;
10872 asc_dvc->init_sdtr = 0;
10873 asc_dvc->max_total_qng = ASC_DEF_MAX_TOTAL_QNG;
10874 asc_dvc->scsi_reset_wait = 3;
10875 asc_dvc->start_motor = ASC_SCSI_WIDTH_BIT_SET;
10876 asc_dvc->max_dma_count = AscGetMaxDmaCount(asc_dvc->bus_type);
10877 asc_dvc->cfg->sdtr_enable = ASC_SCSI_WIDTH_BIT_SET;
10878 asc_dvc->cfg->disc_enable = ASC_SCSI_WIDTH_BIT_SET;
10879 asc_dvc->cfg->chip_scsi_id = ASC_DEF_CHIP_SCSI_ID;
10880 asc_dvc->cfg->lib_serial_no = ASC_LIB_SERIAL_NUMBER;
10881 asc_dvc->cfg->lib_version = (ASC_LIB_VERSION_MAJOR << 8) |
10882 ASC_LIB_VERSION_MINOR;
10883 chip_version = AscGetChipVersion(iop_base, asc_dvc->bus_type);
10884 asc_dvc->cfg->chip_version = chip_version;
10885 asc_dvc->sdtr_period_tbl[0] = SYN_XFER_NS_0;
10886 asc_dvc->sdtr_period_tbl[1] = SYN_XFER_NS_1;
10887 asc_dvc->sdtr_period_tbl[2] = SYN_XFER_NS_2;
10888 asc_dvc->sdtr_period_tbl[3] = SYN_XFER_NS_3;
10889 asc_dvc->sdtr_period_tbl[4] = SYN_XFER_NS_4;
10890 asc_dvc->sdtr_period_tbl[5] = SYN_XFER_NS_5;
10891 asc_dvc->sdtr_period_tbl[6] = SYN_XFER_NS_6;
10892 asc_dvc->sdtr_period_tbl[7] = SYN_XFER_NS_7;
10893 asc_dvc->max_sdtr_index = 7;
10894 if ((asc_dvc->bus_type & ASC_IS_PCI) &&
10895 (chip_version >= ASC_CHIP_VER_PCI_ULTRA_3150)) {
10896 asc_dvc->bus_type = ASC_IS_PCI_ULTRA;
10897 asc_dvc->sdtr_period_tbl[0] = SYN_ULTRA_XFER_NS_0;
10898 asc_dvc->sdtr_period_tbl[1] = SYN_ULTRA_XFER_NS_1;
10899 asc_dvc->sdtr_period_tbl[2] = SYN_ULTRA_XFER_NS_2;
10900 asc_dvc->sdtr_period_tbl[3] = SYN_ULTRA_XFER_NS_3;
10901 asc_dvc->sdtr_period_tbl[4] = SYN_ULTRA_XFER_NS_4;
10902 asc_dvc->sdtr_period_tbl[5] = SYN_ULTRA_XFER_NS_5;
10903 asc_dvc->sdtr_period_tbl[6] = SYN_ULTRA_XFER_NS_6;
10904 asc_dvc->sdtr_period_tbl[7] = SYN_ULTRA_XFER_NS_7;
10905 asc_dvc->sdtr_period_tbl[8] = SYN_ULTRA_XFER_NS_8;
10906 asc_dvc->sdtr_period_tbl[9] = SYN_ULTRA_XFER_NS_9;
10907 asc_dvc->sdtr_period_tbl[10] = SYN_ULTRA_XFER_NS_10;
10908 asc_dvc->sdtr_period_tbl[11] = SYN_ULTRA_XFER_NS_11;
10909 asc_dvc->sdtr_period_tbl[12] = SYN_ULTRA_XFER_NS_12;
10910 asc_dvc->sdtr_period_tbl[13] = SYN_ULTRA_XFER_NS_13;
10911 asc_dvc->sdtr_period_tbl[14] = SYN_ULTRA_XFER_NS_14;
10912 asc_dvc->sdtr_period_tbl[15] = SYN_ULTRA_XFER_NS_15;
10913 asc_dvc->max_sdtr_index = 15;
10914 if (chip_version == ASC_CHIP_VER_PCI_ULTRA_3150) {
10915 AscSetExtraControl(iop_base,
10916 (SEC_ACTIVE_NEGATE | SEC_SLEW_RATE));
10917 } else if (chip_version >= ASC_CHIP_VER_PCI_ULTRA_3050) {
10918 AscSetExtraControl(iop_base,
10919 (SEC_ACTIVE_NEGATE |
10920 SEC_ENABLE_FILTER));
10923 if (asc_dvc->bus_type == ASC_IS_PCI) {
10924 AscSetExtraControl(iop_base,
10925 (SEC_ACTIVE_NEGATE | SEC_SLEW_RATE));
10928 asc_dvc->cfg->isa_dma_speed = ASC_DEF_ISA_DMA_SPEED;
10929 if (AscGetChipBusType(iop_base) == ASC_IS_ISAPNP) {
10930 AscSetChipIFC(iop_base, IFC_INIT_DEFAULT);
10931 asc_dvc->bus_type = ASC_IS_ISAPNP;
10934 if ((asc_dvc->bus_type & ASC_IS_ISA) != 0) {
10935 asc_dvc->cfg->isa_dma_channel =
10936 (uchar)AscGetIsaDmaChannel(iop_base);
10938 #endif /* CONFIG_ISA */
10939 for (i = 0; i <= ASC_MAX_TID; i++) {
10940 asc_dvc->cur_dvc_qng[i] = 0;
10941 asc_dvc->max_dvc_qng[i] = ASC_MAX_SCSI1_QNG;
10942 asc_dvc->scsiq_busy_head[i] = (ASC_SCSI_Q *)0L;
10943 asc_dvc->scsiq_busy_tail[i] = (ASC_SCSI_Q *)0L;
10944 asc_dvc->cfg->max_tag_qng[i] = ASC_MAX_INRAM_TAG_QNG;
10946 return (warn_code);
10949 static ushort __init AscInitFromEEP(ASC_DVC_VAR *asc_dvc)
10951 ASCEEP_CONFIG eep_config_buf;
10952 ASCEEP_CONFIG *eep_config;
10956 ushort cfg_msw, cfg_lsw;
10960 iop_base = asc_dvc->iop_base;
10962 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0x00FE);
10963 AscStopQueueExe(iop_base);
10964 if ((AscStopChip(iop_base) == FALSE) ||
10965 (AscGetChipScsiCtrl(iop_base) != 0)) {
10966 asc_dvc->init_state |= ASC_INIT_RESET_SCSI_DONE;
10967 AscResetChipAndScsiBus(asc_dvc);
10968 DvcSleepMilliSecond((ASC_DCNT)
10969 ((ushort)asc_dvc->scsi_reset_wait * 1000));
10971 if (AscIsChipHalted(iop_base) == FALSE) {
10972 asc_dvc->err_code |= ASC_IERR_START_STOP_CHIP;
10973 return (warn_code);
10975 AscSetPCAddr(iop_base, ASC_MCODE_START_ADDR);
10976 if (AscGetPCAddr(iop_base) != ASC_MCODE_START_ADDR) {
10977 asc_dvc->err_code |= ASC_IERR_SET_PC_ADDR;
10978 return (warn_code);
10980 eep_config = (ASCEEP_CONFIG *)&eep_config_buf;
10981 cfg_msw = AscGetChipCfgMsw(iop_base);
10982 cfg_lsw = AscGetChipCfgLsw(iop_base);
10983 if ((cfg_msw & ASC_CFG_MSW_CLR_MASK) != 0) {
10984 cfg_msw &= (~(ASC_CFG_MSW_CLR_MASK));
10985 warn_code |= ASC_WARN_CFG_MSW_RECOVER;
10986 AscSetChipCfgMsw(iop_base, cfg_msw);
10988 chksum = AscGetEEPConfig(iop_base, eep_config, asc_dvc->bus_type);
10989 ASC_DBG1(1, "AscInitFromEEP: chksum 0x%x\n", chksum);
10993 if (AscGetChipStatus(iop_base) & CSW_AUTO_CONFIG) {
10994 warn_code |= ASC_WARN_AUTO_CONFIG;
10995 if (asc_dvc->cfg->chip_version == 3) {
10996 if (eep_config->cfg_lsw != cfg_lsw) {
10997 warn_code |= ASC_WARN_EEPROM_RECOVER;
10998 eep_config->cfg_lsw =
10999 AscGetChipCfgLsw(iop_base);
11001 if (eep_config->cfg_msw != cfg_msw) {
11002 warn_code |= ASC_WARN_EEPROM_RECOVER;
11003 eep_config->cfg_msw =
11004 AscGetChipCfgMsw(iop_base);
11008 eep_config->cfg_msw &= ~ASC_CFG_MSW_CLR_MASK;
11009 eep_config->cfg_lsw |= ASC_CFG0_HOST_INT_ON;
11010 ASC_DBG1(1, "AscInitFromEEP: eep_config->chksum 0x%x\n",
11011 eep_config->chksum);
11012 if (chksum != eep_config->chksum) {
11013 if (AscGetChipVersion(iop_base, asc_dvc->bus_type) ==
11014 ASC_CHIP_VER_PCI_ULTRA_3050) {
11016 "AscInitFromEEP: chksum error ignored; EEPROM-less board\n");
11017 eep_config->init_sdtr = 0xFF;
11018 eep_config->disc_enable = 0xFF;
11019 eep_config->start_motor = 0xFF;
11020 eep_config->use_cmd_qng = 0;
11021 eep_config->max_total_qng = 0xF0;
11022 eep_config->max_tag_qng = 0x20;
11023 eep_config->cntl = 0xBFFF;
11024 ASC_EEP_SET_CHIP_ID(eep_config, 7);
11025 eep_config->no_scam = 0;
11026 eep_config->adapter_info[0] = 0;
11027 eep_config->adapter_info[1] = 0;
11028 eep_config->adapter_info[2] = 0;
11029 eep_config->adapter_info[3] = 0;
11030 eep_config->adapter_info[4] = 0;
11031 /* Indicate EEPROM-less board. */
11032 eep_config->adapter_info[5] = 0xBB;
11035 ("AscInitFromEEP: EEPROM checksum error; Will try to re-write EEPROM.\n");
11037 warn_code |= ASC_WARN_EEPROM_CHKSUM;
11040 asc_dvc->cfg->sdtr_enable = eep_config->init_sdtr;
11041 asc_dvc->cfg->disc_enable = eep_config->disc_enable;
11042 asc_dvc->cfg->cmd_qng_enabled = eep_config->use_cmd_qng;
11043 asc_dvc->cfg->isa_dma_speed = ASC_EEP_GET_DMA_SPD(eep_config);
11044 asc_dvc->start_motor = eep_config->start_motor;
11045 asc_dvc->dvc_cntl = eep_config->cntl;
11046 asc_dvc->no_scam = eep_config->no_scam;
11047 asc_dvc->cfg->adapter_info[0] = eep_config->adapter_info[0];
11048 asc_dvc->cfg->adapter_info[1] = eep_config->adapter_info[1];
11049 asc_dvc->cfg->adapter_info[2] = eep_config->adapter_info[2];
11050 asc_dvc->cfg->adapter_info[3] = eep_config->adapter_info[3];
11051 asc_dvc->cfg->adapter_info[4] = eep_config->adapter_info[4];
11052 asc_dvc->cfg->adapter_info[5] = eep_config->adapter_info[5];
11053 if (!AscTestExternalLram(asc_dvc)) {
11054 if (((asc_dvc->bus_type & ASC_IS_PCI_ULTRA) ==
11055 ASC_IS_PCI_ULTRA)) {
11056 eep_config->max_total_qng =
11057 ASC_MAX_PCI_ULTRA_INRAM_TOTAL_QNG;
11058 eep_config->max_tag_qng =
11059 ASC_MAX_PCI_ULTRA_INRAM_TAG_QNG;
11061 eep_config->cfg_msw |= 0x0800;
11063 AscSetChipCfgMsw(iop_base, cfg_msw);
11064 eep_config->max_total_qng = ASC_MAX_PCI_INRAM_TOTAL_QNG;
11065 eep_config->max_tag_qng = ASC_MAX_INRAM_TAG_QNG;
11069 if (eep_config->max_total_qng < ASC_MIN_TOTAL_QNG) {
11070 eep_config->max_total_qng = ASC_MIN_TOTAL_QNG;
11072 if (eep_config->max_total_qng > ASC_MAX_TOTAL_QNG) {
11073 eep_config->max_total_qng = ASC_MAX_TOTAL_QNG;
11075 if (eep_config->max_tag_qng > eep_config->max_total_qng) {
11076 eep_config->max_tag_qng = eep_config->max_total_qng;
11078 if (eep_config->max_tag_qng < ASC_MIN_TAG_Q_PER_DVC) {
11079 eep_config->max_tag_qng = ASC_MIN_TAG_Q_PER_DVC;
11081 asc_dvc->max_total_qng = eep_config->max_total_qng;
11082 if ((eep_config->use_cmd_qng & eep_config->disc_enable) !=
11083 eep_config->use_cmd_qng) {
11084 eep_config->disc_enable = eep_config->use_cmd_qng;
11085 warn_code |= ASC_WARN_CMD_QNG_CONFLICT;
11087 if (asc_dvc->bus_type & (ASC_IS_ISA | ASC_IS_VL | ASC_IS_EISA)) {
11088 asc_dvc->irq_no = AscGetChipIRQ(iop_base, asc_dvc->bus_type);
11090 ASC_EEP_SET_CHIP_ID(eep_config,
11091 ASC_EEP_GET_CHIP_ID(eep_config) & ASC_MAX_TID);
11092 asc_dvc->cfg->chip_scsi_id = ASC_EEP_GET_CHIP_ID(eep_config);
11093 if (((asc_dvc->bus_type & ASC_IS_PCI_ULTRA) == ASC_IS_PCI_ULTRA) &&
11094 !(asc_dvc->dvc_cntl & ASC_CNTL_SDTR_ENABLE_ULTRA)) {
11095 asc_dvc->host_init_sdtr_index = ASC_SDTR_ULTRA_PCI_10MB_INDEX;
11098 for (i = 0; i <= ASC_MAX_TID; i++) {
11099 asc_dvc->dos_int13_table[i] = eep_config->dos_int13_table[i];
11100 asc_dvc->cfg->max_tag_qng[i] = eep_config->max_tag_qng;
11101 asc_dvc->cfg->sdtr_period_offset[i] =
11102 (uchar)(ASC_DEF_SDTR_OFFSET |
11103 (asc_dvc->host_init_sdtr_index << 4));
11105 eep_config->cfg_msw = AscGetChipCfgMsw(iop_base);
11108 AscSetEEPConfig(iop_base, eep_config,
11109 asc_dvc->bus_type)) != 0) {
11111 ("AscInitFromEEP: Failed to re-write EEPROM with %d errors.\n",
11115 ("AscInitFromEEP: Successfully re-wrote EEPROM.\n");
11118 return (warn_code);
11121 static ushort AscInitMicroCodeVar(ASC_DVC_VAR *asc_dvc)
11126 ASC_PADDR phy_addr;
11129 iop_base = asc_dvc->iop_base;
11131 for (i = 0; i <= ASC_MAX_TID; i++) {
11132 AscPutMCodeInitSDTRAtID(iop_base, i,
11133 asc_dvc->cfg->sdtr_period_offset[i]
11137 AscInitQLinkVar(asc_dvc);
11138 AscWriteLramByte(iop_base, ASCV_DISC_ENABLE_B,
11139 asc_dvc->cfg->disc_enable);
11140 AscWriteLramByte(iop_base, ASCV_HOSTSCSI_ID_B,
11141 ASC_TID_TO_TARGET_ID(asc_dvc->cfg->chip_scsi_id));
11143 /* Align overrun buffer on an 8 byte boundary. */
11144 phy_addr = virt_to_bus(asc_dvc->cfg->overrun_buf);
11145 phy_addr = cpu_to_le32((phy_addr + 7) & ~0x7);
11146 AscMemDWordCopyPtrToLram(iop_base, ASCV_OVERRUN_PADDR_D,
11147 (uchar *)&phy_addr, 1);
11148 phy_size = cpu_to_le32(ASC_OVERRUN_BSIZE - 8);
11149 AscMemDWordCopyPtrToLram(iop_base, ASCV_OVERRUN_BSIZE_D,
11150 (uchar *)&phy_size, 1);
11152 asc_dvc->cfg->mcode_date =
11153 AscReadLramWord(iop_base, (ushort)ASCV_MC_DATE_W);
11154 asc_dvc->cfg->mcode_version =
11155 AscReadLramWord(iop_base, (ushort)ASCV_MC_VER_W);
11157 AscSetPCAddr(iop_base, ASC_MCODE_START_ADDR);
11158 if (AscGetPCAddr(iop_base) != ASC_MCODE_START_ADDR) {
11159 asc_dvc->err_code |= ASC_IERR_SET_PC_ADDR;
11160 return (warn_code);
11162 if (AscStartChip(iop_base) != 1) {
11163 asc_dvc->err_code |= ASC_IERR_START_STOP_CHIP;
11164 return (warn_code);
11167 return (warn_code);
11170 static int __init AscTestExternalLram(ASC_DVC_VAR *asc_dvc)
11177 iop_base = asc_dvc->iop_base;
11179 q_addr = ASC_QNO_TO_QADDR(241);
11180 saved_word = AscReadLramWord(iop_base, q_addr);
11181 AscSetChipLramAddr(iop_base, q_addr);
11182 AscSetChipLramData(iop_base, 0x55AA);
11183 DvcSleepMilliSecond(10);
11184 AscSetChipLramAddr(iop_base, q_addr);
11185 if (AscGetChipLramData(iop_base) == 0x55AA) {
11187 AscWriteLramWord(iop_base, q_addr, saved_word);
11192 static int __init AscWriteEEPCmdReg(PortAddr iop_base, uchar cmd_reg)
11199 AscSetChipEEPCmd(iop_base, cmd_reg);
11200 DvcSleepMilliSecond(1);
11201 read_back = AscGetChipEEPCmd(iop_base);
11202 if (read_back == cmd_reg) {
11205 if (retry++ > ASC_EEP_MAX_RETRY) {
11211 static int __init AscWriteEEPDataReg(PortAddr iop_base, ushort data_reg)
11218 AscSetChipEEPData(iop_base, data_reg);
11219 DvcSleepMilliSecond(1);
11220 read_back = AscGetChipEEPData(iop_base);
11221 if (read_back == data_reg) {
11224 if (retry++ > ASC_EEP_MAX_RETRY) {
11230 static void __init AscWaitEEPRead(void)
11232 DvcSleepMilliSecond(1);
11236 static void __init AscWaitEEPWrite(void)
11238 DvcSleepMilliSecond(20);
11242 static ushort __init AscReadEEPWord(PortAddr iop_base, uchar addr)
11247 AscWriteEEPCmdReg(iop_base, ASC_EEP_CMD_WRITE_DISABLE);
11249 cmd_reg = addr | ASC_EEP_CMD_READ;
11250 AscWriteEEPCmdReg(iop_base, cmd_reg);
11252 read_wval = AscGetChipEEPData(iop_base);
11254 return (read_wval);
11257 static ushort __init
11258 AscWriteEEPWord(PortAddr iop_base, uchar addr, ushort word_val)
11262 read_wval = AscReadEEPWord(iop_base, addr);
11263 if (read_wval != word_val) {
11264 AscWriteEEPCmdReg(iop_base, ASC_EEP_CMD_WRITE_ABLE);
11266 AscWriteEEPDataReg(iop_base, word_val);
11268 AscWriteEEPCmdReg(iop_base,
11269 (uchar)((uchar)ASC_EEP_CMD_WRITE | addr));
11271 AscWriteEEPCmdReg(iop_base, ASC_EEP_CMD_WRITE_DISABLE);
11273 return (AscReadEEPWord(iop_base, addr));
11275 return (read_wval);
11278 static ushort __init
11279 AscGetEEPConfig(PortAddr iop_base, ASCEEP_CONFIG *cfg_buf, ushort bus_type)
11286 int uchar_end_in_config = ASC_EEP_MAX_DVC_ADDR - 2;
11289 wbuf = (ushort *)cfg_buf;
11291 /* Read two config words; Byte-swapping done by AscReadEEPWord(). */
11292 for (s_addr = 0; s_addr < 2; s_addr++, wbuf++) {
11293 *wbuf = AscReadEEPWord(iop_base, (uchar)s_addr);
11296 if (bus_type & ASC_IS_VL) {
11297 cfg_beg = ASC_EEP_DVC_CFG_BEG_VL;
11298 cfg_end = ASC_EEP_MAX_DVC_ADDR_VL;
11300 cfg_beg = ASC_EEP_DVC_CFG_BEG;
11301 cfg_end = ASC_EEP_MAX_DVC_ADDR;
11303 for (s_addr = cfg_beg; s_addr <= (cfg_end - 1); s_addr++, wbuf++) {
11304 wval = AscReadEEPWord(iop_base, (uchar)s_addr);
11305 if (s_addr <= uchar_end_in_config) {
11307 * Swap all char fields - must unswap bytes already swapped
11308 * by AscReadEEPWord().
11310 *wbuf = le16_to_cpu(wval);
11312 /* Don't swap word field at the end - cntl field. */
11315 sum += wval; /* Checksum treats all EEPROM data as words. */
11318 * Read the checksum word which will be compared against 'sum'
11319 * by the caller. Word field already swapped.
11321 *wbuf = AscReadEEPWord(iop_base, (uchar)s_addr);
11326 AscSetEEPConfigOnce(PortAddr iop_base, ASCEEP_CONFIG *cfg_buf, ushort bus_type)
11335 int uchar_end_in_config = ASC_EEP_MAX_DVC_ADDR - 2;
11337 wbuf = (ushort *)cfg_buf;
11340 /* Write two config words; AscWriteEEPWord() will swap bytes. */
11341 for (s_addr = 0; s_addr < 2; s_addr++, wbuf++) {
11343 if (*wbuf != AscWriteEEPWord(iop_base, (uchar)s_addr, *wbuf)) {
11347 if (bus_type & ASC_IS_VL) {
11348 cfg_beg = ASC_EEP_DVC_CFG_BEG_VL;
11349 cfg_end = ASC_EEP_MAX_DVC_ADDR_VL;
11351 cfg_beg = ASC_EEP_DVC_CFG_BEG;
11352 cfg_end = ASC_EEP_MAX_DVC_ADDR;
11354 for (s_addr = cfg_beg; s_addr <= (cfg_end - 1); s_addr++, wbuf++) {
11355 if (s_addr <= uchar_end_in_config) {
11357 * This is a char field. Swap char fields before they are
11358 * swapped again by AscWriteEEPWord().
11360 word = cpu_to_le16(*wbuf);
11362 AscWriteEEPWord(iop_base, (uchar)s_addr, word)) {
11366 /* Don't swap word field at the end - cntl field. */
11368 AscWriteEEPWord(iop_base, (uchar)s_addr, *wbuf)) {
11372 sum += *wbuf; /* Checksum calculated from word values. */
11374 /* Write checksum word. It will be swapped by AscWriteEEPWord(). */
11376 if (sum != AscWriteEEPWord(iop_base, (uchar)s_addr, sum)) {
11380 /* Read EEPROM back again. */
11381 wbuf = (ushort *)cfg_buf;
11383 * Read two config words; Byte-swapping done by AscReadEEPWord().
11385 for (s_addr = 0; s_addr < 2; s_addr++, wbuf++) {
11386 if (*wbuf != AscReadEEPWord(iop_base, (uchar)s_addr)) {
11390 if (bus_type & ASC_IS_VL) {
11391 cfg_beg = ASC_EEP_DVC_CFG_BEG_VL;
11392 cfg_end = ASC_EEP_MAX_DVC_ADDR_VL;
11394 cfg_beg = ASC_EEP_DVC_CFG_BEG;
11395 cfg_end = ASC_EEP_MAX_DVC_ADDR;
11397 for (s_addr = cfg_beg; s_addr <= (cfg_end - 1); s_addr++, wbuf++) {
11398 if (s_addr <= uchar_end_in_config) {
11400 * Swap all char fields. Must unswap bytes already swapped
11401 * by AscReadEEPWord().
11404 le16_to_cpu(AscReadEEPWord
11405 (iop_base, (uchar)s_addr));
11407 /* Don't swap word field at the end - cntl field. */
11408 word = AscReadEEPWord(iop_base, (uchar)s_addr);
11410 if (*wbuf != word) {
11414 /* Read checksum; Byte swapping not needed. */
11415 if (AscReadEEPWord(iop_base, (uchar)s_addr) != sum) {
11422 AscSetEEPConfig(PortAddr iop_base, ASCEEP_CONFIG *cfg_buf, ushort bus_type)
11429 if ((n_error = AscSetEEPConfigOnce(iop_base, cfg_buf,
11433 if (++retry > ASC_EEP_MAX_RETRY) {
11441 AscAsyncFix(ASC_DVC_VAR *asc_dvc, uchar tid_no, ASC_SCSI_INQUIRY *inq)
11444 ASC_SCSI_BIT_ID_TYPE tid_bits;
11446 dvc_type = ASC_INQ_DVC_TYPE(inq);
11447 tid_bits = ASC_TIX_TO_TARGET_ID(tid_no);
11449 if (asc_dvc->bug_fix_cntl & ASC_BUG_FIX_ASYN_USE_SYN) {
11450 if (!(asc_dvc->init_sdtr & tid_bits)) {
11451 if ((dvc_type == TYPE_ROM) &&
11452 (AscCompareString((uchar *)inq->vendor_id,
11453 (uchar *)"HP ", 3) == 0)) {
11454 asc_dvc->pci_fix_asyn_xfer_always |= tid_bits;
11456 asc_dvc->pci_fix_asyn_xfer |= tid_bits;
11457 if ((dvc_type == TYPE_PROCESSOR) ||
11458 (dvc_type == TYPE_SCANNER) ||
11459 (dvc_type == TYPE_ROM) || (dvc_type == TYPE_TAPE)) {
11460 asc_dvc->pci_fix_asyn_xfer &= ~tid_bits;
11463 if (asc_dvc->pci_fix_asyn_xfer & tid_bits) {
11464 AscSetRunChipSynRegAtID(asc_dvc->iop_base,
11466 ASYN_SDTR_DATA_FIX_PCI_REV_AB);
11473 static int AscTagQueuingSafe(ASC_SCSI_INQUIRY *inq)
11475 if ((inq->add_len >= 32) &&
11476 (AscCompareString((uchar *)inq->vendor_id,
11477 (uchar *)"QUANTUM XP34301", 15) == 0) &&
11478 (AscCompareString((uchar *)inq->product_rev_level,
11479 (uchar *)"1071", 4) == 0)) {
11486 AscInquiryHandling(ASC_DVC_VAR *asc_dvc, uchar tid_no, ASC_SCSI_INQUIRY *inq)
11488 ASC_SCSI_BIT_ID_TYPE tid_bit = ASC_TIX_TO_TARGET_ID(tid_no);
11489 ASC_SCSI_BIT_ID_TYPE orig_init_sdtr, orig_use_tagged_qng;
11491 orig_init_sdtr = asc_dvc->init_sdtr;
11492 orig_use_tagged_qng = asc_dvc->use_tagged_qng;
11494 asc_dvc->init_sdtr &= ~tid_bit;
11495 asc_dvc->cfg->can_tagged_qng &= ~tid_bit;
11496 asc_dvc->use_tagged_qng &= ~tid_bit;
11498 if (ASC_INQ_RESPONSE_FMT(inq) >= 2 || ASC_INQ_ANSI_VER(inq) >= 2) {
11499 if ((asc_dvc->cfg->sdtr_enable & tid_bit) && ASC_INQ_SYNC(inq)) {
11500 asc_dvc->init_sdtr |= tid_bit;
11502 if ((asc_dvc->cfg->cmd_qng_enabled & tid_bit) &&
11503 ASC_INQ_CMD_QUEUE(inq)) {
11504 if (AscTagQueuingSafe(inq)) {
11505 asc_dvc->use_tagged_qng |= tid_bit;
11506 asc_dvc->cfg->can_tagged_qng |= tid_bit;
11510 if (orig_use_tagged_qng != asc_dvc->use_tagged_qng) {
11511 AscWriteLramByte(asc_dvc->iop_base, ASCV_DISC_ENABLE_B,
11512 asc_dvc->cfg->disc_enable);
11513 AscWriteLramByte(asc_dvc->iop_base, ASCV_USE_TAGGED_QNG_B,
11514 asc_dvc->use_tagged_qng);
11515 AscWriteLramByte(asc_dvc->iop_base, ASCV_CAN_TAGGED_QNG_B,
11516 asc_dvc->cfg->can_tagged_qng);
11518 asc_dvc->max_dvc_qng[tid_no] =
11519 asc_dvc->cfg->max_tag_qng[tid_no];
11520 AscWriteLramByte(asc_dvc->iop_base,
11521 (ushort)(ASCV_MAX_DVC_QNG_BEG + tid_no),
11522 asc_dvc->max_dvc_qng[tid_no]);
11524 if (orig_init_sdtr != asc_dvc->init_sdtr) {
11525 AscAsyncFix(asc_dvc, tid_no, inq);
11530 static int AscCompareString(uchar *str1, uchar *str2, int len)
11535 for (i = 0; i < len; i++) {
11536 diff = (int)(str1[i] - str2[i]);
11543 static uchar AscReadLramByte(PortAddr iop_base, ushort addr)
11548 if (isodd_word(addr)) {
11549 AscSetChipLramAddr(iop_base, addr - 1);
11550 word_data = AscGetChipLramData(iop_base);
11551 byte_data = (uchar)((word_data >> 8) & 0xFF);
11553 AscSetChipLramAddr(iop_base, addr);
11554 word_data = AscGetChipLramData(iop_base);
11555 byte_data = (uchar)(word_data & 0xFF);
11557 return (byte_data);
11560 static ushort AscReadLramWord(PortAddr iop_base, ushort addr)
11564 AscSetChipLramAddr(iop_base, addr);
11565 word_data = AscGetChipLramData(iop_base);
11566 return (word_data);
11569 #if CC_VERY_LONG_SG_LIST
11570 static ASC_DCNT AscReadLramDWord(PortAddr iop_base, ushort addr)
11572 ushort val_low, val_high;
11573 ASC_DCNT dword_data;
11575 AscSetChipLramAddr(iop_base, addr);
11576 val_low = AscGetChipLramData(iop_base);
11577 val_high = AscGetChipLramData(iop_base);
11578 dword_data = ((ASC_DCNT) val_high << 16) | (ASC_DCNT) val_low;
11579 return (dword_data);
11581 #endif /* CC_VERY_LONG_SG_LIST */
11583 static void AscWriteLramWord(PortAddr iop_base, ushort addr, ushort word_val)
11585 AscSetChipLramAddr(iop_base, addr);
11586 AscSetChipLramData(iop_base, word_val);
11590 static void AscWriteLramByte(PortAddr iop_base, ushort addr, uchar byte_val)
11594 if (isodd_word(addr)) {
11596 word_data = AscReadLramWord(iop_base, addr);
11597 word_data &= 0x00FF;
11598 word_data |= (((ushort)byte_val << 8) & 0xFF00);
11600 word_data = AscReadLramWord(iop_base, addr);
11601 word_data &= 0xFF00;
11602 word_data |= ((ushort)byte_val & 0x00FF);
11604 AscWriteLramWord(iop_base, addr, word_data);
11609 * Copy 2 bytes to LRAM.
11611 * The source data is assumed to be in little-endian order in memory
11612 * and is maintained in little-endian order when written to LRAM.
11615 AscMemWordCopyPtrToLram(PortAddr iop_base,
11616 ushort s_addr, uchar *s_buffer, int words)
11620 AscSetChipLramAddr(iop_base, s_addr);
11621 for (i = 0; i < 2 * words; i += 2) {
11623 * On a little-endian system the second argument below
11624 * produces a little-endian ushort which is written to
11625 * LRAM in little-endian order. On a big-endian system
11626 * the second argument produces a big-endian ushort which
11627 * is "transparently" byte-swapped by outpw() and written
11628 * in little-endian order to LRAM.
11630 outpw(iop_base + IOP_RAM_DATA,
11631 ((ushort)s_buffer[i + 1] << 8) | s_buffer[i]);
11637 * Copy 4 bytes to LRAM.
11639 * The source data is assumed to be in little-endian order in memory
11640 * and is maintained in little-endian order when writen to LRAM.
11643 AscMemDWordCopyPtrToLram(PortAddr iop_base,
11644 ushort s_addr, uchar *s_buffer, int dwords)
11648 AscSetChipLramAddr(iop_base, s_addr);
11649 for (i = 0; i < 4 * dwords; i += 4) {
11650 outpw(iop_base + IOP_RAM_DATA, ((ushort)s_buffer[i + 1] << 8) | s_buffer[i]); /* LSW */
11651 outpw(iop_base + IOP_RAM_DATA, ((ushort)s_buffer[i + 3] << 8) | s_buffer[i + 2]); /* MSW */
11657 * Copy 2 bytes from LRAM.
11659 * The source data is assumed to be in little-endian order in LRAM
11660 * and is maintained in little-endian order when written to memory.
11663 AscMemWordCopyPtrFromLram(PortAddr iop_base,
11664 ushort s_addr, uchar *d_buffer, int words)
11669 AscSetChipLramAddr(iop_base, s_addr);
11670 for (i = 0; i < 2 * words; i += 2) {
11671 word = inpw(iop_base + IOP_RAM_DATA);
11672 d_buffer[i] = word & 0xff;
11673 d_buffer[i + 1] = (word >> 8) & 0xff;
11678 static ASC_DCNT AscMemSumLramWord(PortAddr iop_base, ushort s_addr, int words)
11684 for (i = 0; i < words; i++, s_addr += 2) {
11685 sum += AscReadLramWord(iop_base, s_addr);
11691 AscMemWordSetLram(PortAddr iop_base, ushort s_addr, ushort set_wval, int words)
11695 AscSetChipLramAddr(iop_base, s_addr);
11696 for (i = 0; i < words; i++) {
11697 AscSetChipLramData(iop_base, set_wval);
11703 * --- Adv Library Functions
11708 /* Microcode buffer is kept after initialization for error recovery. */
11709 static unsigned char _adv_asc3550_buf[] = {
11710 0x00, 0x00, 0x00, 0xf2, 0x00, 0xf0, 0x00, 0x16, 0x18, 0xe4, 0x00, 0xfc,
11711 0x01, 0x00, 0x48, 0xe4,
11712 0xbe, 0x18, 0x18, 0x80, 0x03, 0xf6, 0x02, 0x00, 0x00, 0xfa, 0xff, 0xff,
11713 0x28, 0x0e, 0x9e, 0xe7,
11714 0xff, 0x00, 0x82, 0xe7, 0x00, 0xea, 0x00, 0xf6, 0x01, 0xe6, 0x09, 0xe7,
11715 0x55, 0xf0, 0x01, 0xf6,
11716 0x01, 0xfa, 0x08, 0x00, 0x03, 0x00, 0x04, 0x00, 0x18, 0xf4, 0x10, 0x00,
11717 0x00, 0xec, 0x85, 0xf0,
11718 0xbc, 0x00, 0xd5, 0xf0, 0x8e, 0x0c, 0x38, 0x54, 0x00, 0xe6, 0x1e, 0xf0,
11719 0x86, 0xf0, 0xb4, 0x00,
11720 0x98, 0x57, 0xd0, 0x01, 0x0c, 0x1c, 0x3e, 0x1c, 0x0c, 0x00, 0xbb, 0x00,
11721 0xaa, 0x18, 0x02, 0x80,
11722 0x32, 0xf0, 0x01, 0xfc, 0x88, 0x0c, 0xc6, 0x12, 0x02, 0x13, 0x18, 0x40,
11723 0x00, 0x57, 0x01, 0xea,
11724 0x3c, 0x00, 0x6c, 0x01, 0x6e, 0x01, 0x04, 0x12, 0x3e, 0x57, 0x00, 0x80,
11725 0x03, 0xe6, 0xb6, 0x00,
11726 0xc0, 0x00, 0x01, 0x01, 0x3e, 0x01, 0xda, 0x0f, 0x22, 0x10, 0x08, 0x12,
11727 0x02, 0x4a, 0xb9, 0x54,
11728 0x03, 0x58, 0x1b, 0x80, 0x30, 0xe4, 0x4b, 0xe4, 0x20, 0x00, 0x32, 0x00,
11729 0x3e, 0x00, 0x80, 0x00,
11730 0x24, 0x01, 0x3c, 0x01, 0x68, 0x01, 0x6a, 0x01, 0x70, 0x01, 0x72, 0x01,
11731 0x74, 0x01, 0x76, 0x01,
11732 0x78, 0x01, 0x62, 0x0a, 0x92, 0x0c, 0x2c, 0x10, 0x2e, 0x10, 0x06, 0x13,
11733 0x4c, 0x1c, 0xbb, 0x55,
11734 0x3c, 0x56, 0x04, 0x80, 0x4a, 0xe4, 0x02, 0xee, 0x5b, 0xf0, 0xb1, 0xf0,
11735 0x03, 0xf7, 0x06, 0xf7,
11736 0x03, 0xfc, 0x0f, 0x00, 0x40, 0x00, 0xbe, 0x00, 0x00, 0x01, 0xb0, 0x08,
11737 0x30, 0x13, 0x64, 0x15,
11738 0x32, 0x1c, 0x38, 0x1c, 0x4e, 0x1c, 0x10, 0x44, 0x02, 0x48, 0x00, 0x4c,
11739 0x04, 0xea, 0x5d, 0xf0,
11740 0x04, 0xf6, 0x02, 0xfc, 0x05, 0x00, 0x34, 0x00, 0x36, 0x00, 0x98, 0x00,
11741 0xcc, 0x00, 0x20, 0x01,
11742 0x4e, 0x01, 0x4e, 0x0b, 0x1e, 0x0e, 0x0c, 0x10, 0x0a, 0x12, 0x04, 0x13,
11743 0x40, 0x13, 0x30, 0x1c,
11744 0x00, 0x4e, 0xbd, 0x56, 0x06, 0x83, 0x00, 0xdc, 0x05, 0xf0, 0x09, 0xf0,
11745 0x59, 0xf0, 0xa7, 0xf0,
11746 0xb8, 0xf0, 0x0e, 0xf7, 0x06, 0x00, 0x19, 0x00, 0x33, 0x00, 0x9b, 0x00,
11747 0xa4, 0x00, 0xb5, 0x00,
11748 0xba, 0x00, 0xd0, 0x00, 0xe1, 0x00, 0xe7, 0x00, 0xde, 0x03, 0x56, 0x0a,
11749 0x14, 0x0e, 0x02, 0x10,
11750 0x04, 0x10, 0x0a, 0x10, 0x36, 0x10, 0x0a, 0x13, 0x12, 0x13, 0x52, 0x13,
11751 0x10, 0x15, 0x14, 0x15,
11752 0xac, 0x16, 0x20, 0x1c, 0x34, 0x1c, 0x36, 0x1c, 0x08, 0x44, 0x38, 0x44,
11753 0x91, 0x44, 0x0a, 0x45,
11754 0x48, 0x46, 0x01, 0x48, 0x68, 0x54, 0x83, 0x55, 0xb0, 0x57, 0x01, 0x58,
11755 0x83, 0x59, 0x05, 0xe6,
11756 0x0b, 0xf0, 0x0c, 0xf0, 0x5c, 0xf0, 0x4b, 0xf4, 0x04, 0xf8, 0x05, 0xf8,
11757 0x02, 0xfa, 0x03, 0xfa,
11758 0x04, 0xfc, 0x05, 0xfc, 0x07, 0x00, 0x0a, 0x00, 0x0d, 0x00, 0x1c, 0x00,
11759 0x9e, 0x00, 0xa8, 0x00,
11760 0xaa, 0x00, 0xb9, 0x00, 0xe0, 0x00, 0x22, 0x01, 0x26, 0x01, 0x79, 0x01,
11761 0x7a, 0x01, 0xc0, 0x01,
11762 0xc2, 0x01, 0x7c, 0x02, 0x5a, 0x03, 0xea, 0x04, 0xe8, 0x07, 0x68, 0x08,
11763 0x69, 0x08, 0xba, 0x08,
11764 0xe9, 0x09, 0x06, 0x0b, 0x3a, 0x0e, 0x00, 0x10, 0x1a, 0x10, 0xed, 0x10,
11765 0xf1, 0x10, 0x06, 0x12,
11766 0x0c, 0x13, 0x16, 0x13, 0x1e, 0x13, 0x82, 0x13, 0x42, 0x14, 0xd6, 0x14,
11767 0x8a, 0x15, 0xc6, 0x17,
11768 0xd2, 0x17, 0x6b, 0x18, 0x12, 0x1c, 0x46, 0x1c, 0x9c, 0x32, 0x00, 0x40,
11769 0x0e, 0x47, 0x48, 0x47,
11770 0x41, 0x48, 0x89, 0x48, 0x80, 0x4c, 0x00, 0x54, 0x44, 0x55, 0xe5, 0x55,
11771 0x14, 0x56, 0x77, 0x57,
11772 0xbf, 0x57, 0x40, 0x5c, 0x06, 0x80, 0x08, 0x90, 0x03, 0xa1, 0xfe, 0x9c,
11773 0xf0, 0x29, 0x02, 0xfe,
11774 0xb8, 0x0c, 0xff, 0x10, 0x00, 0x00, 0xd0, 0xfe, 0xcc, 0x18, 0x00, 0xcf,
11775 0xfe, 0x80, 0x01, 0xff,
11776 0x03, 0x00, 0x00, 0xfe, 0x93, 0x15, 0xfe, 0x0f, 0x05, 0xff, 0x38, 0x00,
11777 0x00, 0xfe, 0x57, 0x24,
11778 0x00, 0xfe, 0x48, 0x00, 0x4f, 0xff, 0x04, 0x00, 0x00, 0x10, 0xff, 0x09,
11779 0x00, 0x00, 0xff, 0x08,
11780 0x01, 0x01, 0xff, 0x08, 0xff, 0xff, 0xff, 0x27, 0x00, 0x00, 0xff, 0x10,
11781 0xff, 0xff, 0xff, 0x0f,
11782 0x00, 0x00, 0xfe, 0x78, 0x56, 0xfe, 0x34, 0x12, 0xff, 0x21, 0x00, 0x00,
11783 0xfe, 0x04, 0xf7, 0xcf,
11784 0x2a, 0x67, 0x0b, 0x01, 0xfe, 0xce, 0x0e, 0xfe, 0x04, 0xf7, 0xcf, 0x67,
11785 0x0b, 0x3c, 0x2a, 0xfe,
11786 0x3d, 0xf0, 0xfe, 0x02, 0x02, 0xfe, 0x20, 0xf0, 0x9c, 0xfe, 0x91, 0xf0,
11787 0xfe, 0xf0, 0x01, 0xfe,
11788 0x90, 0xf0, 0xfe, 0xf0, 0x01, 0xfe, 0x8f, 0xf0, 0x9c, 0x05, 0x51, 0x3b,
11789 0x02, 0xfe, 0xd4, 0x0c,
11790 0x01, 0xfe, 0x44, 0x0d, 0xfe, 0xdd, 0x12, 0xfe, 0xfc, 0x10, 0xfe, 0x28,
11791 0x1c, 0x05, 0xfe, 0xa6,
11792 0x00, 0xfe, 0xd3, 0x12, 0x47, 0x18, 0xfe, 0xa6, 0x00, 0xb5, 0xfe, 0x48,
11793 0xf0, 0xfe, 0x86, 0x02,
11794 0xfe, 0x49, 0xf0, 0xfe, 0xa0, 0x02, 0xfe, 0x4a, 0xf0, 0xfe, 0xbe, 0x02,
11795 0xfe, 0x46, 0xf0, 0xfe,
11796 0x50, 0x02, 0xfe, 0x47, 0xf0, 0xfe, 0x56, 0x02, 0xfe, 0x43, 0xf0, 0xfe,
11797 0x44, 0x02, 0xfe, 0x44,
11798 0xf0, 0xfe, 0x48, 0x02, 0xfe, 0x45, 0xf0, 0xfe, 0x4c, 0x02, 0x17, 0x0b,
11799 0xa0, 0x17, 0x06, 0x18,
11800 0x96, 0x02, 0x29, 0xfe, 0x00, 0x1c, 0xde, 0xfe, 0x02, 0x1c, 0xdd, 0xfe,
11801 0x1e, 0x1c, 0xfe, 0xe9,
11802 0x10, 0x01, 0xfe, 0x20, 0x17, 0xfe, 0xe7, 0x10, 0xfe, 0x06, 0xfc, 0xc7,
11803 0x0a, 0x6b, 0x01, 0x9e,
11804 0x02, 0x29, 0x14, 0x4d, 0x37, 0x97, 0x01, 0xfe, 0x64, 0x0f, 0x0a, 0x6b,
11805 0x01, 0x82, 0xfe, 0xbd,
11806 0x10, 0x0a, 0x6b, 0x01, 0x82, 0xfe, 0xad, 0x10, 0xfe, 0x16, 0x1c, 0xfe,
11807 0x58, 0x1c, 0x17, 0x06,
11808 0x18, 0x96, 0x2a, 0x25, 0x29, 0xfe, 0x3d, 0xf0, 0xfe, 0x02, 0x02, 0x21,
11809 0xfe, 0x94, 0x02, 0xfe,
11810 0x5a, 0x1c, 0xea, 0xfe, 0x14, 0x1c, 0x14, 0xfe, 0x30, 0x00, 0x37, 0x97,
11811 0x01, 0xfe, 0x54, 0x0f,
11812 0x17, 0x06, 0x18, 0x96, 0x02, 0xd0, 0x1e, 0x20, 0x07, 0x10, 0x34, 0xfe,
11813 0x69, 0x10, 0x17, 0x06,
11814 0x18, 0x96, 0xfe, 0x04, 0xec, 0x20, 0x46, 0x3d, 0x12, 0x20, 0xfe, 0x05,
11815 0xf6, 0xc7, 0x01, 0xfe,
11816 0x52, 0x16, 0x09, 0x4a, 0x4c, 0x35, 0x11, 0x2d, 0x3c, 0x8a, 0x01, 0xe6,
11817 0x02, 0x29, 0x0a, 0x40,
11818 0x01, 0x0e, 0x07, 0x00, 0x5d, 0x01, 0x6f, 0xfe, 0x18, 0x10, 0xfe, 0x41,
11819 0x58, 0x0a, 0x99, 0x01,
11820 0x0e, 0xfe, 0xc8, 0x54, 0x64, 0xfe, 0x0c, 0x03, 0x01, 0xe6, 0x02, 0x29,
11821 0x2a, 0x46, 0xfe, 0x02,
11822 0xe8, 0x27, 0xf8, 0xfe, 0x9e, 0x43, 0xf7, 0xfe, 0x27, 0xf0, 0xfe, 0xdc,
11823 0x01, 0xfe, 0x07, 0x4b,
11824 0xfe, 0x20, 0xf0, 0x9c, 0xfe, 0x40, 0x1c, 0x25, 0xd2, 0xfe, 0x26, 0xf0,
11825 0xfe, 0x56, 0x03, 0xfe,
11826 0xa0, 0xf0, 0xfe, 0x44, 0x03, 0xfe, 0x11, 0xf0, 0x9c, 0xfe, 0xef, 0x10,
11827 0xfe, 0x9f, 0xf0, 0xfe,
11828 0x64, 0x03, 0xeb, 0x0f, 0xfe, 0x11, 0x00, 0x02, 0x5a, 0x2a, 0xfe, 0x48,
11829 0x1c, 0xeb, 0x09, 0x04,
11830 0x1d, 0xfe, 0x18, 0x13, 0x23, 0x1e, 0x98, 0xac, 0x12, 0x98, 0x0a, 0x40,
11831 0x01, 0x0e, 0xac, 0x75,
11832 0x01, 0xfe, 0xbc, 0x15, 0x11, 0xca, 0x25, 0xd2, 0xfe, 0x01, 0xf0, 0xd2,
11833 0xfe, 0x82, 0xf0, 0xfe,
11834 0x92, 0x03, 0xec, 0x11, 0xfe, 0xe4, 0x00, 0x65, 0xfe, 0xa4, 0x03, 0x25,
11835 0x32, 0x1f, 0xfe, 0xb4,
11836 0x03, 0x01, 0x43, 0xfe, 0x06, 0xf0, 0xfe, 0xc4, 0x03, 0x8d, 0x81, 0xfe,
11837 0x0a, 0xf0, 0xfe, 0x7a,
11838 0x06, 0x02, 0x22, 0x05, 0x6b, 0x28, 0x16, 0xfe, 0xf6, 0x04, 0x14, 0x2c,
11839 0x01, 0x33, 0x8f, 0xfe,
11840 0x66, 0x02, 0x02, 0xd1, 0xeb, 0x2a, 0x67, 0x1a, 0xfe, 0x67, 0x1b, 0xf8,
11841 0xf7, 0xfe, 0x48, 0x1c,
11842 0x70, 0x01, 0x6e, 0x87, 0x0a, 0x40, 0x01, 0x0e, 0x07, 0x00, 0x16, 0xd3,
11843 0x0a, 0xca, 0x01, 0x0e,
11844 0x74, 0x60, 0x59, 0x76, 0x27, 0x05, 0x6b, 0x28, 0xfe, 0x10, 0x12, 0x14,
11845 0x2c, 0x01, 0x33, 0x8f,
11846 0xfe, 0x66, 0x02, 0x02, 0xd1, 0xbc, 0x7d, 0xbd, 0x7f, 0x25, 0x22, 0x65,
11847 0xfe, 0x3c, 0x04, 0x1f,
11848 0xfe, 0x38, 0x04, 0x68, 0xfe, 0xa0, 0x00, 0xfe, 0x9b, 0x57, 0xfe, 0x4e,
11849 0x12, 0x2b, 0xff, 0x02,
11850 0x00, 0x10, 0x01, 0x08, 0x1f, 0xfe, 0xe0, 0x04, 0x2b, 0x01, 0x08, 0x1f,
11851 0x22, 0x30, 0x2e, 0xd5,
11852 0xfe, 0x4c, 0x44, 0xfe, 0x4c, 0x12, 0x60, 0xfe, 0x44, 0x48, 0x13, 0x2c,
11853 0xfe, 0x4c, 0x54, 0x64,
11854 0xd3, 0x46, 0x76, 0x27, 0xfa, 0xef, 0xfe, 0x62, 0x13, 0x09, 0x04, 0x1d,
11855 0xfe, 0x2a, 0x13, 0x2f,
11856 0x07, 0x7e, 0xa5, 0xfe, 0x20, 0x10, 0x13, 0x2c, 0xfe, 0x4c, 0x54, 0x64,
11857 0xd3, 0xfa, 0xef, 0x86,
11858 0x09, 0x04, 0x1d, 0xfe, 0x08, 0x13, 0x2f, 0x07, 0x7e, 0x6e, 0x09, 0x04,
11859 0x1d, 0xfe, 0x1c, 0x12,
11860 0x14, 0x92, 0x09, 0x04, 0x06, 0x3b, 0x14, 0xc4, 0x01, 0x33, 0x8f, 0xfe,
11861 0x70, 0x0c, 0x02, 0x22,
11862 0x2b, 0x11, 0xfe, 0xe6, 0x00, 0xfe, 0x1c, 0x90, 0xf9, 0x03, 0x14, 0x92,
11863 0x01, 0x33, 0x02, 0x29,
11864 0xfe, 0x42, 0x5b, 0x67, 0x1a, 0xfe, 0x46, 0x59, 0xf8, 0xf7, 0xfe, 0x87,
11865 0x80, 0xfe, 0x31, 0xe4,
11866 0x4f, 0x09, 0x04, 0x0b, 0xfe, 0x78, 0x13, 0xfe, 0x20, 0x80, 0x07, 0x1a,
11867 0xfe, 0x70, 0x12, 0x49,
11868 0x04, 0x06, 0xfe, 0x60, 0x13, 0x05, 0xfe, 0xa2, 0x00, 0x28, 0x16, 0xfe,
11869 0x80, 0x05, 0xfe, 0x31,
11870 0xe4, 0x6a, 0x49, 0x04, 0x0b, 0xfe, 0x4a, 0x13, 0x05, 0xfe, 0xa0, 0x00,
11871 0x28, 0xfe, 0x42, 0x12,
11872 0x5e, 0x01, 0x08, 0x25, 0x32, 0xf1, 0x01, 0x08, 0x26, 0xfe, 0x98, 0x05,
11873 0x11, 0xfe, 0xe3, 0x00,
11874 0x23, 0x49, 0xfe, 0x4a, 0xf0, 0xfe, 0x6a, 0x05, 0xfe, 0x49, 0xf0, 0xfe,
11875 0x64, 0x05, 0x83, 0x24,
11876 0xfe, 0x21, 0x00, 0xa1, 0x24, 0xfe, 0x22, 0x00, 0xa0, 0x24, 0x4c, 0xfe,
11877 0x09, 0x48, 0x01, 0x08,
11878 0x26, 0xfe, 0x98, 0x05, 0xfe, 0xe2, 0x08, 0x49, 0x04, 0xc5, 0x3b, 0x01,
11879 0x86, 0x24, 0x06, 0x12,
11880 0xcc, 0x37, 0xfe, 0x27, 0x01, 0x09, 0x04, 0x1d, 0xfe, 0x22, 0x12, 0x47,
11881 0x01, 0xa7, 0x14, 0x92,
11882 0x09, 0x04, 0x06, 0x3b, 0x14, 0xc4, 0x01, 0x33, 0x8f, 0xfe, 0x70, 0x0c,
11883 0x02, 0x22, 0x05, 0xfe,
11884 0x9c, 0x00, 0x28, 0xfe, 0x3e, 0x12, 0x05, 0x50, 0x28, 0xfe, 0x36, 0x13,
11885 0x47, 0x01, 0xa7, 0x26,
11886 0xfe, 0x08, 0x06, 0x0a, 0x06, 0x49, 0x04, 0x19, 0xfe, 0x02, 0x12, 0x5f,
11887 0x01, 0xfe, 0xaa, 0x14,
11888 0x1f, 0xfe, 0xfe, 0x05, 0x11, 0x9a, 0x01, 0x43, 0x11, 0xfe, 0xe5, 0x00,
11889 0x05, 0x50, 0xb4, 0x0c,
11890 0x50, 0x05, 0xc6, 0x28, 0xfe, 0x62, 0x12, 0x05, 0x3f, 0x28, 0xfe, 0x5a,
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12320 0xfe, 0x4e, 0xe4, 0xc2, 0x64, 0xfe, 0x36, 0x18, 0x05, 0xfe, 0x92, 0x00,
12321 0xfe, 0x02, 0xe6, 0x1b,
12322 0xdc, 0xfe, 0x4e, 0xe4, 0xfe, 0x0b, 0x00, 0x64, 0xfe, 0x48, 0x18, 0x05,
12323 0xfe, 0x94, 0x00, 0xfe,
12324 0x02, 0xe6, 0x19, 0xfe, 0x08, 0x10, 0x05, 0xfe, 0x96, 0x00, 0xfe, 0x02,
12325 0xe6, 0x2c, 0xfe, 0x4e,
12326 0x45, 0xfe, 0x0c, 0x12, 0xaf, 0xff, 0x04, 0x68, 0x54, 0xde, 0x1c, 0x69,
12327 0x03, 0x07, 0x7a, 0xfe,
12328 0x5a, 0xf0, 0xfe, 0x74, 0x18, 0x24, 0xfe, 0x09, 0x00, 0xfe, 0x34, 0x10,
12329 0x07, 0x1b, 0xfe, 0x5a,
12330 0xf0, 0xfe, 0x82, 0x18, 0x24, 0xc3, 0xfe, 0x26, 0x10, 0x07, 0x1a, 0x5d,
12331 0x24, 0x2c, 0xdc, 0x07,
12332 0x0b, 0x5d, 0x24, 0x93, 0xfe, 0x0e, 0x10, 0x07, 0x06, 0x5d, 0x24, 0x4d,
12333 0x9f, 0xad, 0x03, 0x14,
12334 0xfe, 0x09, 0x00, 0x01, 0x33, 0xfe, 0x04, 0xfe, 0x7d, 0x05, 0x7f, 0xf9,
12335 0x03, 0x25, 0xfe, 0xca,
12336 0x18, 0xfe, 0x14, 0xf0, 0x08, 0x65, 0xfe, 0xc6, 0x18, 0x03, 0xff, 0x1a,
12340 static unsigned short _adv_asc3550_size = sizeof(_adv_asc3550_buf); /* 0x13AD */
12341 static ADV_DCNT _adv_asc3550_chksum = 0x04D52DDDUL; /* Expanded little-endian checksum. */
12343 /* Microcode buffer is kept after initialization for error recovery. */
12344 static unsigned char _adv_asc38C0800_buf[] = {
12345 0x00, 0x00, 0x00, 0xf2, 0x00, 0xf0, 0x00, 0xfc, 0x00, 0x16, 0x18, 0xe4,
12346 0x01, 0x00, 0x48, 0xe4,
12347 0x18, 0x80, 0x03, 0xf6, 0x02, 0x00, 0xce, 0x19, 0x00, 0xfa, 0xff, 0xff,
12348 0x1c, 0x0f, 0x00, 0xf6,
12349 0x9e, 0xe7, 0xff, 0x00, 0x82, 0xe7, 0x00, 0xea, 0x01, 0xfa, 0x01, 0xe6,
12350 0x09, 0xe7, 0x55, 0xf0,
12351 0x01, 0xf6, 0x03, 0x00, 0x04, 0x00, 0x10, 0x00, 0x1e, 0xf0, 0x85, 0xf0,
12352 0x18, 0xf4, 0x08, 0x00,
12353 0xbc, 0x00, 0x38, 0x54, 0x00, 0xec, 0xd5, 0xf0, 0x82, 0x0d, 0x00, 0xe6,
12354 0x86, 0xf0, 0xb1, 0xf0,
12355 0x98, 0x57, 0x01, 0xfc, 0xb4, 0x00, 0xd4, 0x01, 0x0c, 0x1c, 0x3e, 0x1c,
12356 0x3c, 0x00, 0xbb, 0x00,
12357 0x00, 0x10, 0xba, 0x19, 0x02, 0x80, 0x32, 0xf0, 0x7c, 0x0d, 0x02, 0x13,
12358 0xba, 0x13, 0x18, 0x40,
12359 0x00, 0x57, 0x01, 0xea, 0x02, 0xfc, 0x03, 0xfc, 0x3e, 0x00, 0x6c, 0x01,
12360 0x6e, 0x01, 0x74, 0x01,
12361 0x76, 0x01, 0xb9, 0x54, 0x3e, 0x57, 0x00, 0x80, 0x03, 0xe6, 0xb6, 0x00,
12362 0xc0, 0x00, 0x01, 0x01,
12363 0x3e, 0x01, 0x7a, 0x01, 0xca, 0x08, 0xce, 0x10, 0x16, 0x11, 0x04, 0x12,
12364 0x08, 0x12, 0x02, 0x4a,
12365 0xbb, 0x55, 0x3c, 0x56, 0x03, 0x58, 0x1b, 0x80, 0x30, 0xe4, 0x4b, 0xe4,
12366 0x5d, 0xf0, 0x02, 0xfa,
12367 0x20, 0x00, 0x32, 0x00, 0x40, 0x00, 0x80, 0x00, 0x24, 0x01, 0x3c, 0x01,
12368 0x68, 0x01, 0x6a, 0x01,
12369 0x70, 0x01, 0x72, 0x01, 0x78, 0x01, 0x7c, 0x01, 0x62, 0x0a, 0x86, 0x0d,
12370 0x06, 0x13, 0x4c, 0x1c,
12371 0x04, 0x80, 0x4a, 0xe4, 0x02, 0xee, 0x5b, 0xf0, 0x03, 0xf7, 0x0c, 0x00,
12372 0x0f, 0x00, 0x47, 0x00,
12373 0xbe, 0x00, 0x00, 0x01, 0x20, 0x11, 0x5c, 0x16, 0x32, 0x1c, 0x38, 0x1c,
12374 0x4e, 0x1c, 0x10, 0x44,
12375 0x00, 0x4c, 0x04, 0xea, 0x5c, 0xf0, 0xa7, 0xf0, 0x04, 0xf6, 0x03, 0xfa,
12376 0x05, 0x00, 0x34, 0x00,
12377 0x36, 0x00, 0x98, 0x00, 0xcc, 0x00, 0x20, 0x01, 0x4e, 0x01, 0x4a, 0x0b,
12378 0x42, 0x0c, 0x12, 0x0f,
12379 0x0c, 0x10, 0x22, 0x11, 0x0a, 0x12, 0x04, 0x13, 0x30, 0x1c, 0x02, 0x48,
12380 0x00, 0x4e, 0x42, 0x54,
12381 0x44, 0x55, 0xbd, 0x56, 0x06, 0x83, 0x00, 0xdc, 0x05, 0xf0, 0x09, 0xf0,
12382 0x59, 0xf0, 0xb8, 0xf0,
12383 0x4b, 0xf4, 0x06, 0xf7, 0x0e, 0xf7, 0x04, 0xfc, 0x05, 0xfc, 0x06, 0x00,
12384 0x19, 0x00, 0x33, 0x00,
12385 0x9b, 0x00, 0xa4, 0x00, 0xb5, 0x00, 0xba, 0x00, 0xd0, 0x00, 0xe1, 0x00,
12386 0xe7, 0x00, 0xe2, 0x03,
12387 0x08, 0x0f, 0x02, 0x10, 0x04, 0x10, 0x0a, 0x10, 0x0a, 0x13, 0x0c, 0x13,
12388 0x12, 0x13, 0x24, 0x14,
12389 0x34, 0x14, 0x04, 0x16, 0x08, 0x16, 0xa4, 0x17, 0x20, 0x1c, 0x34, 0x1c,
12390 0x36, 0x1c, 0x08, 0x44,
12391 0x38, 0x44, 0x91, 0x44, 0x0a, 0x45, 0x48, 0x46, 0x01, 0x48, 0x68, 0x54,
12392 0x3a, 0x55, 0x83, 0x55,
12393 0xe5, 0x55, 0xb0, 0x57, 0x01, 0x58, 0x83, 0x59, 0x05, 0xe6, 0x0b, 0xf0,
12394 0x0c, 0xf0, 0x04, 0xf8,
12395 0x05, 0xf8, 0x07, 0x00, 0x0a, 0x00, 0x1c, 0x00, 0x1e, 0x00, 0x9e, 0x00,
12396 0xa8, 0x00, 0xaa, 0x00,
12397 0xb9, 0x00, 0xe0, 0x00, 0x22, 0x01, 0x26, 0x01, 0x79, 0x01, 0x7e, 0x01,
12398 0xc4, 0x01, 0xc6, 0x01,
12399 0x80, 0x02, 0x5e, 0x03, 0xee, 0x04, 0x9a, 0x06, 0xf8, 0x07, 0x62, 0x08,
12400 0x68, 0x08, 0x69, 0x08,
12401 0xd6, 0x08, 0xe9, 0x09, 0xfa, 0x0b, 0x2e, 0x0f, 0x12, 0x10, 0x1a, 0x10,
12402 0xed, 0x10, 0xf1, 0x10,
12403 0x2a, 0x11, 0x06, 0x12, 0x0c, 0x12, 0x3e, 0x12, 0x10, 0x13, 0x16, 0x13,
12404 0x1e, 0x13, 0x46, 0x14,
12405 0x76, 0x14, 0x82, 0x14, 0x36, 0x15, 0xca, 0x15, 0x6b, 0x18, 0xbe, 0x18,
12406 0xca, 0x18, 0xe6, 0x19,
12407 0x12, 0x1c, 0x46, 0x1c, 0x9c, 0x32, 0x00, 0x40, 0x0e, 0x47, 0xfe, 0x9c,
12408 0xf0, 0x2b, 0x02, 0xfe,
12409 0xac, 0x0d, 0xff, 0x10, 0x00, 0x00, 0xd7, 0xfe, 0xe8, 0x19, 0x00, 0xd6,
12410 0xfe, 0x84, 0x01, 0xff,
12411 0x03, 0x00, 0x00, 0xfe, 0x93, 0x15, 0xfe, 0x0f, 0x05, 0xff, 0x38, 0x00,
12412 0x00, 0xfe, 0x57, 0x24,
12413 0x00, 0xfe, 0x4c, 0x00, 0x5b, 0xff, 0x04, 0x00, 0x00, 0x11, 0xff, 0x09,
12414 0x00, 0x00, 0xff, 0x08,
12415 0x01, 0x01, 0xff, 0x08, 0xff, 0xff, 0xff, 0x27, 0x00, 0x00, 0xff, 0x10,
12416 0xff, 0xff, 0xff, 0x11,
12417 0x00, 0x00, 0xfe, 0x78, 0x56, 0xfe, 0x34, 0x12, 0xff, 0x21, 0x00, 0x00,
12418 0xfe, 0x04, 0xf7, 0xd6,
12419 0x2c, 0x99, 0x0a, 0x01, 0xfe, 0xc2, 0x0f, 0xfe, 0x04, 0xf7, 0xd6, 0x99,
12420 0x0a, 0x42, 0x2c, 0xfe,
12421 0x3d, 0xf0, 0xfe, 0x06, 0x02, 0xfe, 0x20, 0xf0, 0xa7, 0xfe, 0x91, 0xf0,
12422 0xfe, 0xf4, 0x01, 0xfe,
12423 0x90, 0xf0, 0xfe, 0xf4, 0x01, 0xfe, 0x8f, 0xf0, 0xa7, 0x03, 0x5d, 0x4d,
12424 0x02, 0xfe, 0xc8, 0x0d,
12425 0x01, 0xfe, 0x38, 0x0e, 0xfe, 0xdd, 0x12, 0xfe, 0xfc, 0x10, 0xfe, 0x28,
12426 0x1c, 0x03, 0xfe, 0xa6,
12427 0x00, 0xfe, 0xd3, 0x12, 0x41, 0x14, 0xfe, 0xa6, 0x00, 0xc2, 0xfe, 0x48,
12428 0xf0, 0xfe, 0x8a, 0x02,
12429 0xfe, 0x49, 0xf0, 0xfe, 0xa4, 0x02, 0xfe, 0x4a, 0xf0, 0xfe, 0xc2, 0x02,
12430 0xfe, 0x46, 0xf0, 0xfe,
12431 0x54, 0x02, 0xfe, 0x47, 0xf0, 0xfe, 0x5a, 0x02, 0xfe, 0x43, 0xf0, 0xfe,
12432 0x48, 0x02, 0xfe, 0x44,
12433 0xf0, 0xfe, 0x4c, 0x02, 0xfe, 0x45, 0xf0, 0xfe, 0x50, 0x02, 0x18, 0x0a,
12434 0xaa, 0x18, 0x06, 0x14,
12435 0xa1, 0x02, 0x2b, 0xfe, 0x00, 0x1c, 0xe7, 0xfe, 0x02, 0x1c, 0xe6, 0xfe,
12436 0x1e, 0x1c, 0xfe, 0xe9,
12437 0x10, 0x01, 0xfe, 0x18, 0x18, 0xfe, 0xe7, 0x10, 0xfe, 0x06, 0xfc, 0xce,
12438 0x09, 0x70, 0x01, 0xa8,
12439 0x02, 0x2b, 0x15, 0x59, 0x39, 0xa2, 0x01, 0xfe, 0x58, 0x10, 0x09, 0x70,
12440 0x01, 0x87, 0xfe, 0xbd,
12441 0x10, 0x09, 0x70, 0x01, 0x87, 0xfe, 0xad, 0x10, 0xfe, 0x16, 0x1c, 0xfe,
12442 0x58, 0x1c, 0x18, 0x06,
12443 0x14, 0xa1, 0x2c, 0x1c, 0x2b, 0xfe, 0x3d, 0xf0, 0xfe, 0x06, 0x02, 0x23,
12444 0xfe, 0x98, 0x02, 0xfe,
12445 0x5a, 0x1c, 0xf8, 0xfe, 0x14, 0x1c, 0x15, 0xfe, 0x30, 0x00, 0x39, 0xa2,
12446 0x01, 0xfe, 0x48, 0x10,
12447 0x18, 0x06, 0x14, 0xa1, 0x02, 0xd7, 0x22, 0x20, 0x07, 0x11, 0x35, 0xfe,
12448 0x69, 0x10, 0x18, 0x06,
12449 0x14, 0xa1, 0xfe, 0x04, 0xec, 0x20, 0x4f, 0x43, 0x13, 0x20, 0xfe, 0x05,
12450 0xf6, 0xce, 0x01, 0xfe,
12451 0x4a, 0x17, 0x08, 0x54, 0x58, 0x37, 0x12, 0x2f, 0x42, 0x92, 0x01, 0xfe,
12452 0x82, 0x16, 0x02, 0x2b,
12453 0x09, 0x46, 0x01, 0x0e, 0x07, 0x00, 0x66, 0x01, 0x73, 0xfe, 0x18, 0x10,
12454 0xfe, 0x41, 0x58, 0x09,
12455 0xa4, 0x01, 0x0e, 0xfe, 0xc8, 0x54, 0x6b, 0xfe, 0x10, 0x03, 0x01, 0xfe,
12456 0x82, 0x16, 0x02, 0x2b,
12457 0x2c, 0x4f, 0xfe, 0x02, 0xe8, 0x2a, 0xfe, 0xbf, 0x57, 0xfe, 0x9e, 0x43,
12458 0xfe, 0x77, 0x57, 0xfe,
12459 0x27, 0xf0, 0xfe, 0xe0, 0x01, 0xfe, 0x07, 0x4b, 0xfe, 0x20, 0xf0, 0xa7,
12460 0xfe, 0x40, 0x1c, 0x1c,
12461 0xd9, 0xfe, 0x26, 0xf0, 0xfe, 0x5a, 0x03, 0xfe, 0xa0, 0xf0, 0xfe, 0x48,
12462 0x03, 0xfe, 0x11, 0xf0,
12463 0xa7, 0xfe, 0xef, 0x10, 0xfe, 0x9f, 0xf0, 0xfe, 0x68, 0x03, 0xf9, 0x10,
12464 0xfe, 0x11, 0x00, 0x02,
12465 0x65, 0x2c, 0xfe, 0x48, 0x1c, 0xf9, 0x08, 0x05, 0x1b, 0xfe, 0x18, 0x13,
12466 0x21, 0x22, 0xa3, 0xb7,
12467 0x13, 0xa3, 0x09, 0x46, 0x01, 0x0e, 0xb7, 0x78, 0x01, 0xfe, 0xb4, 0x16,
12468 0x12, 0xd1, 0x1c, 0xd9,
12469 0xfe, 0x01, 0xf0, 0xd9, 0xfe, 0x82, 0xf0, 0xfe, 0x96, 0x03, 0xfa, 0x12,
12470 0xfe, 0xe4, 0x00, 0x27,
12471 0xfe, 0xa8, 0x03, 0x1c, 0x34, 0x1d, 0xfe, 0xb8, 0x03, 0x01, 0x4b, 0xfe,
12472 0x06, 0xf0, 0xfe, 0xc8,
12473 0x03, 0x95, 0x86, 0xfe, 0x0a, 0xf0, 0xfe, 0x8a, 0x06, 0x02, 0x24, 0x03,
12474 0x70, 0x28, 0x17, 0xfe,
12475 0xfa, 0x04, 0x15, 0x6d, 0x01, 0x36, 0x7b, 0xfe, 0x6a, 0x02, 0x02, 0xd8,
12476 0xf9, 0x2c, 0x99, 0x19,
12477 0xfe, 0x67, 0x1b, 0xfe, 0xbf, 0x57, 0xfe, 0x77, 0x57, 0xfe, 0x48, 0x1c,
12478 0x74, 0x01, 0xaf, 0x8c,
12479 0x09, 0x46, 0x01, 0x0e, 0x07, 0x00, 0x17, 0xda, 0x09, 0xd1, 0x01, 0x0e,
12480 0x8d, 0x51, 0x64, 0x79,
12481 0x2a, 0x03, 0x70, 0x28, 0xfe, 0x10, 0x12, 0x15, 0x6d, 0x01, 0x36, 0x7b,
12482 0xfe, 0x6a, 0x02, 0x02,
12483 0xd8, 0xc7, 0x81, 0xc8, 0x83, 0x1c, 0x24, 0x27, 0xfe, 0x40, 0x04, 0x1d,
12484 0xfe, 0x3c, 0x04, 0x3b,
12485 0xfe, 0xa0, 0x00, 0xfe, 0x9b, 0x57, 0xfe, 0x4e, 0x12, 0x2d, 0xff, 0x02,
12486 0x00, 0x10, 0x01, 0x0b,
12487 0x1d, 0xfe, 0xe4, 0x04, 0x2d, 0x01, 0x0b, 0x1d, 0x24, 0x33, 0x31, 0xde,
12488 0xfe, 0x4c, 0x44, 0xfe,
12489 0x4c, 0x12, 0x51, 0xfe, 0x44, 0x48, 0x0f, 0x6f, 0xfe, 0x4c, 0x54, 0x6b,
12490 0xda, 0x4f, 0x79, 0x2a,
12491 0xfe, 0x06, 0x80, 0xfe, 0x48, 0x47, 0xfe, 0x62, 0x13, 0x08, 0x05, 0x1b,
12492 0xfe, 0x2a, 0x13, 0x32,
12493 0x07, 0x82, 0xfe, 0x52, 0x13, 0xfe, 0x20, 0x10, 0x0f, 0x6f, 0xfe, 0x4c,
12494 0x54, 0x6b, 0xda, 0xfe,
12495 0x06, 0x80, 0xfe, 0x48, 0x47, 0xfe, 0x40, 0x13, 0x08, 0x05, 0x1b, 0xfe,
12496 0x08, 0x13, 0x32, 0x07,
12497 0x82, 0xfe, 0x30, 0x13, 0x08, 0x05, 0x1b, 0xfe, 0x1c, 0x12, 0x15, 0x9d,
12498 0x08, 0x05, 0x06, 0x4d,
12499 0x15, 0xfe, 0x0d, 0x00, 0x01, 0x36, 0x7b, 0xfe, 0x64, 0x0d, 0x02, 0x24,
12500 0x2d, 0x12, 0xfe, 0xe6,
12501 0x00, 0xfe, 0x1c, 0x90, 0xfe, 0x40, 0x5c, 0x04, 0x15, 0x9d, 0x01, 0x36,
12502 0x02, 0x2b, 0xfe, 0x42,
12503 0x5b, 0x99, 0x19, 0xfe, 0x46, 0x59, 0xfe, 0xbf, 0x57, 0xfe, 0x77, 0x57,
12504 0xfe, 0x87, 0x80, 0xfe,
12505 0x31, 0xe4, 0x5b, 0x08, 0x05, 0x0a, 0xfe, 0x84, 0x13, 0xfe, 0x20, 0x80,
12506 0x07, 0x19, 0xfe, 0x7c,
12507 0x12, 0x53, 0x05, 0x06, 0xfe, 0x6c, 0x13, 0x03, 0xfe, 0xa2, 0x00, 0x28,
12508 0x17, 0xfe, 0x90, 0x05,
12509 0xfe, 0x31, 0xe4, 0x5a, 0x53, 0x05, 0x0a, 0xfe, 0x56, 0x13, 0x03, 0xfe,
12510 0xa0, 0x00, 0x28, 0xfe,
12511 0x4e, 0x12, 0x67, 0xff, 0x02, 0x00, 0x10, 0x27, 0xfe, 0x48, 0x05, 0x1c,
12512 0x34, 0xfe, 0x89, 0x48,
12513 0xff, 0x02, 0x00, 0x10, 0x27, 0xfe, 0x56, 0x05, 0x26, 0xfe, 0xa8, 0x05,
12514 0x12, 0xfe, 0xe3, 0x00,
12515 0x21, 0x53, 0xfe, 0x4a, 0xf0, 0xfe, 0x76, 0x05, 0xfe, 0x49, 0xf0, 0xfe,
12516 0x70, 0x05, 0x88, 0x25,
12517 0xfe, 0x21, 0x00, 0xab, 0x25, 0xfe, 0x22, 0x00, 0xaa, 0x25, 0x58, 0xfe,
12518 0x09, 0x48, 0xff, 0x02,
12519 0x00, 0x10, 0x27, 0xfe, 0x86, 0x05, 0x26, 0xfe, 0xa8, 0x05, 0xfe, 0xe2,
12520 0x08, 0x53, 0x05, 0xcb,
12521 0x4d, 0x01, 0xb0, 0x25, 0x06, 0x13, 0xd3, 0x39, 0xfe, 0x27, 0x01, 0x08,
12522 0x05, 0x1b, 0xfe, 0x22,
12523 0x12, 0x41, 0x01, 0xb2, 0x15, 0x9d, 0x08, 0x05, 0x06, 0x4d, 0x15, 0xfe,
12524 0x0d, 0x00, 0x01, 0x36,
12525 0x7b, 0xfe, 0x64, 0x0d, 0x02, 0x24, 0x03, 0xfe, 0x9c, 0x00, 0x28, 0xeb,
12526 0x03, 0x5c, 0x28, 0xfe,
12527 0x36, 0x13, 0x41, 0x01, 0xb2, 0x26, 0xfe, 0x18, 0x06, 0x09, 0x06, 0x53,
12528 0x05, 0x1f, 0xfe, 0x02,
12529 0x12, 0x50, 0x01, 0xfe, 0x9e, 0x15, 0x1d, 0xfe, 0x0e, 0x06, 0x12, 0xa5,
12530 0x01, 0x4b, 0x12, 0xfe,
12531 0xe5, 0x00, 0x03, 0x5c, 0xc1, 0x0c, 0x5c, 0x03, 0xcd, 0x28, 0xfe, 0x62,
12532 0x12, 0x03, 0x45, 0x28,
12533 0xfe, 0x5a, 0x13, 0x01, 0xfe, 0x0c, 0x19, 0x01, 0xfe, 0x76, 0x19, 0xfe,
12534 0x43, 0x48, 0xc4, 0xcc,
12535 0x0f, 0x71, 0xff, 0x02, 0x00, 0x57, 0x52, 0x93, 0x1e, 0x43, 0x8b, 0xc4,
12536 0x6e, 0x41, 0x01, 0xb2,
12537 0x26, 0xfe, 0x82, 0x06, 0x53, 0x05, 0x1a, 0xe9, 0x91, 0x09, 0x59, 0x01,
12538 0xfe, 0xcc, 0x15, 0x1d,
12539 0xfe, 0x78, 0x06, 0x12, 0xa5, 0x01, 0x4b, 0x12, 0xfe, 0xe5, 0x00, 0x03,
12540 0x45, 0xc1, 0x0c, 0x45,
12541 0x18, 0x06, 0x01, 0xb2, 0xfa, 0x76, 0x74, 0x01, 0xaf, 0x8c, 0x12, 0xfe,
12542 0xe2, 0x00, 0x27, 0xdb,
12543 0x1c, 0x34, 0xfe, 0x0a, 0xf0, 0xfe, 0xb6, 0x06, 0x94, 0xfe, 0x6c, 0x07,
12544 0xfe, 0x06, 0xf0, 0xfe,
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12943 0x97, 0xfe, 0x38, 0x17,
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12976 0x56, 0xfe, 0xd6, 0xf0, 0xfe, 0x1c, 0x18, 0x18, 0x0a, 0x04, 0xfe, 0x9c,
12977 0xe7, 0x0a, 0x10, 0xfe,
12978 0x15, 0x00, 0x64, 0x79, 0x2a, 0x01, 0xe3, 0x18, 0x06, 0x04, 0x42, 0x92,
12979 0x08, 0x54, 0x1b, 0x37,
12980 0x12, 0x2f, 0x01, 0x73, 0x18, 0x06, 0x04, 0xfe, 0x38, 0x90, 0xfe, 0xba,
12981 0x90, 0x3a, 0xce, 0x3b,
12982 0xcf, 0xfe, 0x48, 0x55, 0x35, 0xfe, 0xc9, 0x55, 0x04, 0x22, 0xa3, 0x77,
12983 0x13, 0xa3, 0x04, 0x09,
12984 0xa4, 0x01, 0x0e, 0xfe, 0x41, 0x48, 0x09, 0x46, 0x01, 0x0e, 0xfe, 0x49,
12985 0x44, 0x17, 0xfe, 0xe8,
12986 0x18, 0x77, 0x78, 0x04, 0x09, 0x48, 0x01, 0x0e, 0x07, 0x11, 0x4e, 0x09,
12987 0x5d, 0x01, 0xa8, 0x09,
12988 0x46, 0x01, 0x0e, 0x77, 0x78, 0x04, 0xfe, 0x4e, 0xe4, 0x19, 0x6b, 0xfe,
12989 0x1c, 0x19, 0x03, 0xfe,
12990 0x90, 0x00, 0xfe, 0x3a, 0x45, 0xfe, 0x2c, 0x10, 0xfe, 0x4e, 0xe4, 0xc9,
12991 0x6b, 0xfe, 0x2e, 0x19,
12992 0x03, 0xfe, 0x92, 0x00, 0xfe, 0x02, 0xe6, 0x1a, 0xe5, 0xfe, 0x4e, 0xe4,
12993 0xfe, 0x0b, 0x00, 0x6b,
12994 0xfe, 0x40, 0x19, 0x03, 0xfe, 0x94, 0x00, 0xfe, 0x02, 0xe6, 0x1f, 0xfe,
12995 0x08, 0x10, 0x03, 0xfe,
12996 0x96, 0x00, 0xfe, 0x02, 0xe6, 0x6d, 0xfe, 0x4e, 0x45, 0xea, 0xba, 0xff,
12997 0x04, 0x68, 0x54, 0xe7,
12998 0x1e, 0x6e, 0xfe, 0x08, 0x1c, 0xfe, 0x67, 0x19, 0xfe, 0x0a, 0x1c, 0xfe,
12999 0x1a, 0xf4, 0xfe, 0x00,
13000 0x04, 0xea, 0xfe, 0x48, 0xf4, 0x19, 0x7a, 0xfe, 0x74, 0x19, 0x0f, 0x19,
13001 0x04, 0x07, 0x7e, 0xfe,
13002 0x5a, 0xf0, 0xfe, 0x84, 0x19, 0x25, 0xfe, 0x09, 0x00, 0xfe, 0x34, 0x10,
13003 0x07, 0x1a, 0xfe, 0x5a,
13004 0xf0, 0xfe, 0x92, 0x19, 0x25, 0xca, 0xfe, 0x26, 0x10, 0x07, 0x19, 0x66,
13005 0x25, 0x6d, 0xe5, 0x07,
13006 0x0a, 0x66, 0x25, 0x9e, 0xfe, 0x0e, 0x10, 0x07, 0x06, 0x66, 0x25, 0x59,
13007 0xa9, 0xb8, 0x04, 0x15,
13008 0xfe, 0x09, 0x00, 0x01, 0x36, 0xfe, 0x04, 0xfe, 0x81, 0x03, 0x83, 0xfe,
13009 0x40, 0x5c, 0x04, 0x1c,
13010 0xf7, 0xfe, 0x14, 0xf0, 0x0b, 0x27, 0xfe, 0xd6, 0x19, 0x1c, 0xf7, 0x7b,
13011 0xf7, 0xfe, 0x82, 0xf0,
13012 0xfe, 0xda, 0x19, 0x04, 0xff, 0xcc, 0x00, 0x00,
13015 static unsigned short _adv_asc38C0800_size = sizeof(_adv_asc38C0800_buf); /* 0x14E1 */
13016 static ADV_DCNT _adv_asc38C0800_chksum = 0x050D3FD8UL; /* Expanded little-endian checksum. */
13018 /* Microcode buffer is kept after initialization for error recovery. */
13019 static unsigned char _adv_asc38C1600_buf[] = {
13020 0x00, 0x00, 0x00, 0xf2, 0x00, 0x16, 0x00, 0xfc, 0x00, 0x10, 0x00, 0xf0,
13021 0x18, 0xe4, 0x01, 0x00,
13022 0x04, 0x1e, 0x48, 0xe4, 0x03, 0xf6, 0xf7, 0x13, 0x2e, 0x1e, 0x02, 0x00,
13023 0x07, 0x17, 0xc0, 0x5f,
13024 0x00, 0xfa, 0xff, 0xff, 0x04, 0x00, 0x00, 0xf6, 0x09, 0xe7, 0x82, 0xe7,
13025 0x85, 0xf0, 0x86, 0xf0,
13026 0x4e, 0x10, 0x9e, 0xe7, 0xff, 0x00, 0x55, 0xf0, 0x01, 0xf6, 0x03, 0x00,
13027 0x98, 0x57, 0x01, 0xe6,
13028 0x00, 0xea, 0x00, 0xec, 0x01, 0xfa, 0x18, 0xf4, 0x08, 0x00, 0xf0, 0x1d,
13029 0x38, 0x54, 0x32, 0xf0,
13030 0x10, 0x00, 0xc2, 0x0e, 0x1e, 0xf0, 0xd5, 0xf0, 0xbc, 0x00, 0x4b, 0xe4,
13031 0x00, 0xe6, 0xb1, 0xf0,
13032 0xb4, 0x00, 0x02, 0x13, 0x3e, 0x1c, 0xc8, 0x47, 0x3e, 0x00, 0xd8, 0x01,
13033 0x06, 0x13, 0x0c, 0x1c,
13034 0x5e, 0x1e, 0x00, 0x57, 0xc8, 0x57, 0x01, 0xfc, 0xbc, 0x0e, 0xa2, 0x12,
13035 0xb9, 0x54, 0x00, 0x80,
13036 0x62, 0x0a, 0x5a, 0x12, 0xc8, 0x15, 0x3e, 0x1e, 0x18, 0x40, 0xbd, 0x56,
13037 0x03, 0xe6, 0x01, 0xea,
13038 0x5c, 0xf0, 0x0f, 0x00, 0x20, 0x00, 0x6c, 0x01, 0x6e, 0x01, 0x04, 0x12,
13039 0x04, 0x13, 0xbb, 0x55,
13040 0x3c, 0x56, 0x3e, 0x57, 0x03, 0x58, 0x4a, 0xe4, 0x40, 0x00, 0xb6, 0x00,
13041 0xbb, 0x00, 0xc0, 0x00,
13042 0x00, 0x01, 0x01, 0x01, 0x3e, 0x01, 0x58, 0x0a, 0x44, 0x10, 0x0a, 0x12,
13043 0x4c, 0x1c, 0x4e, 0x1c,
13044 0x02, 0x4a, 0x30, 0xe4, 0x05, 0xe6, 0x0c, 0x00, 0x3c, 0x00, 0x80, 0x00,
13045 0x24, 0x01, 0x3c, 0x01,
13046 0x68, 0x01, 0x6a, 0x01, 0x70, 0x01, 0x72, 0x01, 0x74, 0x01, 0x76, 0x01,
13047 0x78, 0x01, 0x7c, 0x01,
13048 0xc6, 0x0e, 0x0c, 0x10, 0xac, 0x12, 0xae, 0x12, 0x16, 0x1a, 0x32, 0x1c,
13049 0x6e, 0x1e, 0x02, 0x48,
13050 0x3a, 0x55, 0xc9, 0x57, 0x02, 0xee, 0x5b, 0xf0, 0x03, 0xf7, 0x06, 0xf7,
13051 0x03, 0xfc, 0x06, 0x00,
13052 0x1e, 0x00, 0xbe, 0x00, 0xe1, 0x00, 0x0c, 0x12, 0x18, 0x1a, 0x70, 0x1a,
13053 0x30, 0x1c, 0x38, 0x1c,
13054 0x10, 0x44, 0x00, 0x4c, 0xb0, 0x57, 0x40, 0x5c, 0x4d, 0xe4, 0x04, 0xea,
13055 0x5d, 0xf0, 0xa7, 0xf0,
13056 0x04, 0xf6, 0x02, 0xfc, 0x05, 0x00, 0x09, 0x00, 0x19, 0x00, 0x32, 0x00,
13057 0x33, 0x00, 0x34, 0x00,
13058 0x36, 0x00, 0x98, 0x00, 0x9e, 0x00, 0xcc, 0x00, 0x20, 0x01, 0x4e, 0x01,
13059 0x79, 0x01, 0x3c, 0x09,
13060 0x68, 0x0d, 0x02, 0x10, 0x04, 0x10, 0x3a, 0x10, 0x08, 0x12, 0x0a, 0x13,
13061 0x40, 0x16, 0x50, 0x16,
13062 0x00, 0x17, 0x4a, 0x19, 0x00, 0x4e, 0x00, 0x54, 0x01, 0x58, 0x00, 0xdc,
13063 0x05, 0xf0, 0x09, 0xf0,
13064 0x59, 0xf0, 0xb8, 0xf0, 0x48, 0xf4, 0x0e, 0xf7, 0x0a, 0x00, 0x9b, 0x00,
13065 0x9c, 0x00, 0xa4, 0x00,
13066 0xb5, 0x00, 0xba, 0x00, 0xd0, 0x00, 0xe7, 0x00, 0xf0, 0x03, 0x69, 0x08,
13067 0xe9, 0x09, 0x5c, 0x0c,
13068 0xb6, 0x12, 0xbc, 0x19, 0xd8, 0x1b, 0x20, 0x1c, 0x34, 0x1c, 0x36, 0x1c,
13069 0x42, 0x1d, 0x08, 0x44,
13070 0x38, 0x44, 0x91, 0x44, 0x0a, 0x45, 0x48, 0x46, 0x89, 0x48, 0x68, 0x54,
13071 0x83, 0x55, 0x83, 0x59,
13072 0x31, 0xe4, 0x02, 0xe6, 0x07, 0xf0, 0x08, 0xf0, 0x0b, 0xf0, 0x0c, 0xf0,
13073 0x4b, 0xf4, 0x04, 0xf8,
13074 0x05, 0xf8, 0x02, 0xfa, 0x03, 0xfa, 0x04, 0xfc, 0x05, 0xfc, 0x07, 0x00,
13075 0xa8, 0x00, 0xaa, 0x00,
13076 0xb9, 0x00, 0xe0, 0x00, 0xe5, 0x00, 0x22, 0x01, 0x26, 0x01, 0x60, 0x01,
13077 0x7a, 0x01, 0x82, 0x01,
13078 0xc8, 0x01, 0xca, 0x01, 0x86, 0x02, 0x6a, 0x03, 0x18, 0x05, 0xb2, 0x07,
13079 0x68, 0x08, 0x10, 0x0d,
13080 0x06, 0x10, 0x0a, 0x10, 0x0e, 0x10, 0x12, 0x10, 0x60, 0x10, 0xed, 0x10,
13081 0xf3, 0x10, 0x06, 0x12,
13082 0x10, 0x12, 0x1e, 0x12, 0x0c, 0x13, 0x0e, 0x13, 0x10, 0x13, 0xfe, 0x9c,
13083 0xf0, 0x35, 0x05, 0xfe,
13084 0xec, 0x0e, 0xff, 0x10, 0x00, 0x00, 0xe9, 0xfe, 0x34, 0x1f, 0x00, 0xe8,
13085 0xfe, 0x88, 0x01, 0xff,
13086 0x03, 0x00, 0x00, 0xfe, 0x93, 0x15, 0xfe, 0x0f, 0x05, 0xff, 0x38, 0x00,
13087 0x00, 0xfe, 0x57, 0x24,
13088 0x00, 0xfe, 0x4c, 0x00, 0x65, 0xff, 0x04, 0x00, 0x00, 0x1a, 0xff, 0x09,
13089 0x00, 0x00, 0xff, 0x08,
13090 0x01, 0x01, 0xff, 0x08, 0xff, 0xff, 0xff, 0x27, 0x00, 0x00, 0xff, 0x10,
13091 0xff, 0xff, 0xff, 0x13,
13092 0x00, 0x00, 0xfe, 0x78, 0x56, 0xfe, 0x34, 0x12, 0xff, 0x21, 0x00, 0x00,
13093 0xfe, 0x04, 0xf7, 0xe8,
13094 0x37, 0x7d, 0x0d, 0x01, 0xfe, 0x4a, 0x11, 0xfe, 0x04, 0xf7, 0xe8, 0x7d,
13095 0x0d, 0x51, 0x37, 0xfe,
13096 0x3d, 0xf0, 0xfe, 0x0c, 0x02, 0xfe, 0x20, 0xf0, 0xbc, 0xfe, 0x91, 0xf0,
13097 0xfe, 0xf8, 0x01, 0xfe,
13098 0x90, 0xf0, 0xfe, 0xf8, 0x01, 0xfe, 0x8f, 0xf0, 0xbc, 0x03, 0x67, 0x4d,
13099 0x05, 0xfe, 0x08, 0x0f,
13100 0x01, 0xfe, 0x78, 0x0f, 0xfe, 0xdd, 0x12, 0x05, 0xfe, 0x0e, 0x03, 0xfe,
13101 0x28, 0x1c, 0x03, 0xfe,
13102 0xa6, 0x00, 0xfe, 0xd1, 0x12, 0x3e, 0x22, 0xfe, 0xa6, 0x00, 0xac, 0xfe,
13103 0x48, 0xf0, 0xfe, 0x90,
13104 0x02, 0xfe, 0x49, 0xf0, 0xfe, 0xaa, 0x02, 0xfe, 0x4a, 0xf0, 0xfe, 0xc8,
13105 0x02, 0xfe, 0x46, 0xf0,
13106 0xfe, 0x5a, 0x02, 0xfe, 0x47, 0xf0, 0xfe, 0x60, 0x02, 0xfe, 0x43, 0xf0,
13107 0xfe, 0x4e, 0x02, 0xfe,
13108 0x44, 0xf0, 0xfe, 0x52, 0x02, 0xfe, 0x45, 0xf0, 0xfe, 0x56, 0x02, 0x1c,
13109 0x0d, 0xa2, 0x1c, 0x07,
13110 0x22, 0xb7, 0x05, 0x35, 0xfe, 0x00, 0x1c, 0xfe, 0xf1, 0x10, 0xfe, 0x02,
13111 0x1c, 0xf5, 0xfe, 0x1e,
13112 0x1c, 0xfe, 0xe9, 0x10, 0x01, 0x5f, 0xfe, 0xe7, 0x10, 0xfe, 0x06, 0xfc,
13113 0xde, 0x0a, 0x81, 0x01,
13114 0xa3, 0x05, 0x35, 0x1f, 0x95, 0x47, 0xb8, 0x01, 0xfe, 0xe4, 0x11, 0x0a,
13115 0x81, 0x01, 0x5c, 0xfe,
13116 0xbd, 0x10, 0x0a, 0x81, 0x01, 0x5c, 0xfe, 0xad, 0x10, 0xfe, 0x16, 0x1c,
13117 0xfe, 0x58, 0x1c, 0x1c,
13118 0x07, 0x22, 0xb7, 0x37, 0x2a, 0x35, 0xfe, 0x3d, 0xf0, 0xfe, 0x0c, 0x02,
13119 0x2b, 0xfe, 0x9e, 0x02,
13120 0xfe, 0x5a, 0x1c, 0xfe, 0x12, 0x1c, 0xfe, 0x14, 0x1c, 0x1f, 0xfe, 0x30,
13121 0x00, 0x47, 0xb8, 0x01,
13122 0xfe, 0xd4, 0x11, 0x1c, 0x07, 0x22, 0xb7, 0x05, 0xe9, 0x21, 0x2c, 0x09,
13123 0x1a, 0x31, 0xfe, 0x69,
13124 0x10, 0x1c, 0x07, 0x22, 0xb7, 0xfe, 0x04, 0xec, 0x2c, 0x60, 0x01, 0xfe,
13125 0x1e, 0x1e, 0x20, 0x2c,
13126 0xfe, 0x05, 0xf6, 0xde, 0x01, 0xfe, 0x62, 0x1b, 0x01, 0x0c, 0x61, 0x4a,
13127 0x44, 0x15, 0x56, 0x51,
13128 0x01, 0xfe, 0x9e, 0x1e, 0x01, 0xfe, 0x96, 0x1a, 0x05, 0x35, 0x0a, 0x57,
13129 0x01, 0x18, 0x09, 0x00,
13130 0x36, 0x01, 0x85, 0xfe, 0x18, 0x10, 0xfe, 0x41, 0x58, 0x0a, 0xba, 0x01,
13131 0x18, 0xfe, 0xc8, 0x54,
13132 0x7b, 0xfe, 0x1c, 0x03, 0x01, 0xfe, 0x96, 0x1a, 0x05, 0x35, 0x37, 0x60,
13133 0xfe, 0x02, 0xe8, 0x30,
13134 0xfe, 0xbf, 0x57, 0xfe, 0x9e, 0x43, 0xfe, 0x77, 0x57, 0xfe, 0x27, 0xf0,
13135 0xfe, 0xe4, 0x01, 0xfe,
13136 0x07, 0x4b, 0xfe, 0x20, 0xf0, 0xbc, 0xfe, 0x40, 0x1c, 0x2a, 0xeb, 0xfe,
13137 0x26, 0xf0, 0xfe, 0x66,
13138 0x03, 0xfe, 0xa0, 0xf0, 0xfe, 0x54, 0x03, 0xfe, 0x11, 0xf0, 0xbc, 0xfe,
13139 0xef, 0x10, 0xfe, 0x9f,
13140 0xf0, 0xfe, 0x74, 0x03, 0xfe, 0x46, 0x1c, 0x19, 0xfe, 0x11, 0x00, 0x05,
13141 0x70, 0x37, 0xfe, 0x48,
13142 0x1c, 0xfe, 0x46, 0x1c, 0x01, 0x0c, 0x06, 0x28, 0xfe, 0x18, 0x13, 0x26,
13143 0x21, 0xb9, 0xc7, 0x20,
13144 0xb9, 0x0a, 0x57, 0x01, 0x18, 0xc7, 0x89, 0x01, 0xfe, 0xc8, 0x1a, 0x15,
13145 0xe1, 0x2a, 0xeb, 0xfe,
13146 0x01, 0xf0, 0xeb, 0xfe, 0x82, 0xf0, 0xfe, 0xa4, 0x03, 0xfe, 0x9c, 0x32,
13147 0x15, 0xfe, 0xe4, 0x00,
13148 0x2f, 0xfe, 0xb6, 0x03, 0x2a, 0x3c, 0x16, 0xfe, 0xc6, 0x03, 0x01, 0x41,
13149 0xfe, 0x06, 0xf0, 0xfe,
13150 0xd6, 0x03, 0xaf, 0xa0, 0xfe, 0x0a, 0xf0, 0xfe, 0xa2, 0x07, 0x05, 0x29,
13151 0x03, 0x81, 0x1e, 0x1b,
13152 0xfe, 0x24, 0x05, 0x1f, 0x63, 0x01, 0x42, 0x8f, 0xfe, 0x70, 0x02, 0x05,
13153 0xea, 0xfe, 0x46, 0x1c,
13154 0x37, 0x7d, 0x1d, 0xfe, 0x67, 0x1b, 0xfe, 0xbf, 0x57, 0xfe, 0x77, 0x57,
13155 0xfe, 0x48, 0x1c, 0x75,
13156 0x01, 0xa6, 0x86, 0x0a, 0x57, 0x01, 0x18, 0x09, 0x00, 0x1b, 0xec, 0x0a,
13157 0xe1, 0x01, 0x18, 0x77,
13158 0x50, 0x40, 0x8d, 0x30, 0x03, 0x81, 0x1e, 0xf8, 0x1f, 0x63, 0x01, 0x42,
13159 0x8f, 0xfe, 0x70, 0x02,
13160 0x05, 0xea, 0xd7, 0x99, 0xd8, 0x9c, 0x2a, 0x29, 0x2f, 0xfe, 0x4e, 0x04,
13161 0x16, 0xfe, 0x4a, 0x04,
13162 0x7e, 0xfe, 0xa0, 0x00, 0xfe, 0x9b, 0x57, 0xfe, 0x54, 0x12, 0x32, 0xff,
13163 0x02, 0x00, 0x10, 0x01,
13164 0x08, 0x16, 0xfe, 0x02, 0x05, 0x32, 0x01, 0x08, 0x16, 0x29, 0x27, 0x25,
13165 0xee, 0xfe, 0x4c, 0x44,
13166 0xfe, 0x58, 0x12, 0x50, 0xfe, 0x44, 0x48, 0x13, 0x34, 0xfe, 0x4c, 0x54,
13167 0x7b, 0xec, 0x60, 0x8d,
13168 0x30, 0x01, 0xfe, 0x4e, 0x1e, 0xfe, 0x48, 0x47, 0xfe, 0x7c, 0x13, 0x01,
13169 0x0c, 0x06, 0x28, 0xfe,
13170 0x32, 0x13, 0x01, 0x43, 0x09, 0x9b, 0xfe, 0x68, 0x13, 0xfe, 0x26, 0x10,
13171 0x13, 0x34, 0xfe, 0x4c,
13172 0x54, 0x7b, 0xec, 0x01, 0xfe, 0x4e, 0x1e, 0xfe, 0x48, 0x47, 0xfe, 0x54,
13173 0x13, 0x01, 0x0c, 0x06,
13174 0x28, 0xa5, 0x01, 0x43, 0x09, 0x9b, 0xfe, 0x40, 0x13, 0x01, 0x0c, 0x06,
13175 0x28, 0xf9, 0x1f, 0x7f,
13176 0x01, 0x0c, 0x06, 0x07, 0x4d, 0x1f, 0xfe, 0x0d, 0x00, 0x01, 0x42, 0x8f,
13177 0xfe, 0xa4, 0x0e, 0x05,
13178 0x29, 0x32, 0x15, 0xfe, 0xe6, 0x00, 0x0f, 0xfe, 0x1c, 0x90, 0x04, 0xfe,
13179 0x9c, 0x93, 0x3a, 0x0b,
13180 0x0e, 0x8b, 0x02, 0x1f, 0x7f, 0x01, 0x42, 0x05, 0x35, 0xfe, 0x42, 0x5b,
13181 0x7d, 0x1d, 0xfe, 0x46,
13182 0x59, 0xfe, 0xbf, 0x57, 0xfe, 0x77, 0x57, 0x0f, 0xfe, 0x87, 0x80, 0x04,
13183 0xfe, 0x87, 0x83, 0xfe,
13184 0xc9, 0x47, 0x0b, 0x0e, 0xd0, 0x65, 0x01, 0x0c, 0x06, 0x0d, 0xfe, 0x98,
13185 0x13, 0x0f, 0xfe, 0x20,
13186 0x80, 0x04, 0xfe, 0xa0, 0x83, 0x33, 0x0b, 0x0e, 0x09, 0x1d, 0xfe, 0x84,
13187 0x12, 0x01, 0x38, 0x06,
13188 0x07, 0xfe, 0x70, 0x13, 0x03, 0xfe, 0xa2, 0x00, 0x1e, 0x1b, 0xfe, 0xda,
13189 0x05, 0xd0, 0x54, 0x01,
13190 0x38, 0x06, 0x0d, 0xfe, 0x58, 0x13, 0x03, 0xfe, 0xa0, 0x00, 0x1e, 0xfe,
13191 0x50, 0x12, 0x5e, 0xff,
13192 0x02, 0x00, 0x10, 0x2f, 0xfe, 0x90, 0x05, 0x2a, 0x3c, 0xcc, 0xff, 0x02,
13193 0x00, 0x10, 0x2f, 0xfe,
13194 0x9e, 0x05, 0x17, 0xfe, 0xf4, 0x05, 0x15, 0xfe, 0xe3, 0x00, 0x26, 0x01,
13195 0x38, 0xfe, 0x4a, 0xf0,
13196 0xfe, 0xc0, 0x05, 0xfe, 0x49, 0xf0, 0xfe, 0xba, 0x05, 0x71, 0x2e, 0xfe,
13197 0x21, 0x00, 0xf1, 0x2e,
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13626 0x01, 0xfe, 0x24, 0x16, 0x23, 0x3f, 0xfc, 0xa8, 0x8c, 0x49, 0x48, 0xfe,
13627 0xda, 0x17, 0x62, 0x49,
13628 0xfe, 0x1c, 0x10, 0xa8, 0x8c, 0x80, 0x48, 0xfe, 0xda, 0x17, 0x62, 0x80,
13629 0x71, 0x50, 0x26, 0xfe,
13630 0x4d, 0xf4, 0x00, 0xf7, 0x45, 0x13, 0x07, 0xfe, 0xb4, 0x56, 0xfe, 0xc3,
13631 0x58, 0x02, 0x50, 0x13,
13632 0x0d, 0x02, 0x50, 0x3e, 0x78, 0x4f, 0x45, 0x01, 0x08, 0x16, 0xa9, 0x27,
13633 0x25, 0xbe, 0xfe, 0x03,
13634 0xea, 0xfe, 0x7e, 0x01, 0x01, 0x08, 0x16, 0xa9, 0x27, 0x25, 0xfe, 0xe9,
13635 0x0a, 0x01, 0x08, 0x16,
13636 0xa9, 0x27, 0x25, 0xfe, 0xe9, 0x0a, 0xfe, 0x05, 0xea, 0xfe, 0x7f, 0x01,
13637 0x01, 0x08, 0x16, 0xa9,
13638 0x27, 0x25, 0xfe, 0x69, 0x09, 0xfe, 0x02, 0xea, 0xfe, 0x80, 0x01, 0x01,
13639 0x08, 0x16, 0xa9, 0x27,
13640 0x25, 0xfe, 0xe8, 0x08, 0x47, 0xfe, 0x81, 0x01, 0x03, 0xb6, 0x1e, 0x83,
13641 0x01, 0x38, 0x06, 0x24,
13642 0x31, 0xa2, 0x78, 0xf2, 0x53, 0x07, 0x36, 0xfe, 0x34, 0xf4, 0x3f, 0xa1,
13643 0x78, 0x03, 0x9a, 0x1e,
13644 0x83, 0x01, 0x38, 0x06, 0x12, 0x31, 0xf0, 0x4f, 0x45, 0xfe, 0x90, 0x10,
13645 0xfe, 0x40, 0x5a, 0x23,
13646 0x3f, 0xfb, 0x8c, 0x49, 0x48, 0xfe, 0xaa, 0x18, 0x62, 0x49, 0x71, 0x8c,
13647 0x80, 0x48, 0xfe, 0xaa,
13648 0x18, 0x62, 0x80, 0xfe, 0xb4, 0x56, 0xfe, 0x40, 0x5d, 0x01, 0xc6, 0x01,
13649 0xfe, 0xac, 0x1d, 0xfe,
13650 0x02, 0x17, 0xfe, 0xc8, 0x45, 0xfe, 0x5a, 0xf0, 0xfe, 0xc0, 0x18, 0xfe,
13651 0x43, 0x48, 0x2d, 0x93,
13652 0x36, 0xfe, 0x34, 0xf4, 0xfe, 0x00, 0x11, 0xfe, 0x40, 0x10, 0x2d, 0xb4,
13653 0x36, 0xfe, 0x34, 0xf4,
13654 0x04, 0xfe, 0x34, 0x10, 0x2d, 0xfe, 0x0b, 0x00, 0x36, 0x46, 0x63, 0xfe,
13655 0x28, 0x10, 0xfe, 0xc0,
13656 0x49, 0xff, 0x02, 0x00, 0x54, 0xb2, 0xfe, 0x90, 0x01, 0x48, 0xfe, 0xfa,
13657 0x18, 0x45, 0xfe, 0x1c,
13658 0xf4, 0x3f, 0xf3, 0xfe, 0x40, 0xf4, 0x96, 0xfe, 0x56, 0xf0, 0xfe, 0x0c,
13659 0x19, 0xfe, 0x04, 0xf4,
13660 0x58, 0xfe, 0x40, 0xf4, 0x94, 0xf6, 0x3e, 0x2d, 0x93, 0x4e, 0xd0, 0x0d,
13661 0x21, 0xfe, 0x7f, 0x01,
13662 0xfe, 0xc8, 0x46, 0xfe, 0x24, 0x13, 0x8c, 0x00, 0x5d, 0x26, 0x21, 0xfe,
13663 0x7e, 0x01, 0xfe, 0xc8,
13664 0x45, 0xfe, 0x14, 0x13, 0x21, 0xfe, 0x80, 0x01, 0xfe, 0x48, 0x45, 0xfa,
13665 0x21, 0xfe, 0x81, 0x01,
13666 0xfe, 0xc8, 0x44, 0x4e, 0x26, 0x02, 0x13, 0x07, 0x02, 0x78, 0x45, 0x50,
13667 0x13, 0x0d, 0x02, 0x14,
13668 0x07, 0x01, 0x08, 0x17, 0xfe, 0x82, 0x19, 0x14, 0x0d, 0x01, 0x08, 0x17,
13669 0xfe, 0x82, 0x19, 0x14,
13670 0x1d, 0x01, 0x08, 0x17, 0xfe, 0x82, 0x19, 0x5f, 0xfe, 0x89, 0x49, 0x01,
13671 0x08, 0x02, 0x14, 0x07,
13672 0x01, 0x08, 0x17, 0xc1, 0x14, 0x1d, 0x01, 0x08, 0x17, 0xc1, 0x14, 0x07,
13673 0x01, 0x08, 0x17, 0xc1,
13674 0xfe, 0x89, 0x49, 0x01, 0x08, 0x17, 0xc1, 0x5f, 0xfe, 0x89, 0x4a, 0x01,
13675 0x08, 0x02, 0x50, 0x02,
13676 0x14, 0x07, 0x01, 0x08, 0x17, 0x74, 0x14, 0x7f, 0x01, 0x08, 0x17, 0x74,
13677 0x14, 0x12, 0x01, 0x08,
13678 0x17, 0x74, 0xfe, 0x89, 0x49, 0x01, 0x08, 0x17, 0x74, 0x14, 0x00, 0x01,
13679 0x08, 0x17, 0x74, 0xfe,
13680 0x89, 0x4a, 0x01, 0x08, 0x17, 0x74, 0xfe, 0x09, 0x49, 0x01, 0x08, 0x17,
13681 0x74, 0x5f, 0xcc, 0x01,
13682 0x08, 0x02, 0x21, 0xe4, 0x09, 0x07, 0xfe, 0x4c, 0x13, 0xc8, 0x20, 0xe4,
13683 0xfe, 0x49, 0xf4, 0x00,
13684 0x4d, 0x5f, 0xa1, 0x5e, 0xfe, 0x01, 0xec, 0xfe, 0x27, 0x01, 0xcc, 0xff,
13685 0x02, 0x00, 0x10, 0x2f,
13686 0xfe, 0x3e, 0x1a, 0x01, 0x43, 0x09, 0xfe, 0xe3, 0x00, 0xfe, 0x22, 0x13,
13687 0x16, 0xfe, 0x64, 0x1a,
13688 0x26, 0x20, 0x9e, 0x01, 0x41, 0x21, 0x9e, 0x09, 0x07, 0x5d, 0x01, 0x0c,
13689 0x61, 0x07, 0x44, 0x02,
13690 0x0a, 0x5a, 0x01, 0x18, 0xfe, 0x00, 0x40, 0xaa, 0x09, 0x1a, 0xfe, 0x12,
13691 0x13, 0x0a, 0x9d, 0x01,
13692 0x18, 0xaa, 0x0a, 0x67, 0x01, 0xa3, 0x02, 0x0a, 0x9d, 0x01, 0x18, 0xaa,
13693 0xfe, 0x80, 0xe7, 0x1a,
13694 0x09, 0x1a, 0x5d, 0xfe, 0x45, 0x58, 0x01, 0xfe, 0xb2, 0x16, 0xaa, 0x02,
13695 0x0a, 0x5a, 0x01, 0x18,
13696 0xaa, 0x0a, 0x67, 0x01, 0xa3, 0x02, 0x0a, 0x5a, 0x01, 0x18, 0x01, 0xfe,
13697 0x7e, 0x1e, 0xfe, 0x80,
13698 0x4c, 0xfe, 0x49, 0xe4, 0x1a, 0xfe, 0x12, 0x13, 0x0a, 0x9d, 0x01, 0x18,
13699 0xfe, 0x80, 0x4c, 0x0a,
13700 0x67, 0x01, 0x5c, 0x02, 0x1c, 0x1a, 0x87, 0x7c, 0xe5, 0xfe, 0x18, 0xdf,
13701 0xfe, 0x19, 0xde, 0xfe,
13702 0x24, 0x1c, 0xfe, 0x1d, 0xf7, 0x28, 0xb1, 0xfe, 0x04, 0x1b, 0x01, 0xfe,
13703 0x2a, 0x1c, 0xfa, 0xb3,
13704 0x28, 0x7c, 0xfe, 0x2c, 0x01, 0xfe, 0x2f, 0x19, 0x02, 0xc9, 0x2b, 0xfe,
13705 0xf4, 0x1a, 0xfe, 0xfa,
13706 0x10, 0x1c, 0x1a, 0x87, 0x03, 0xfe, 0x64, 0x01, 0xfe, 0x00, 0xf4, 0x24,
13707 0xfe, 0x18, 0x58, 0x03,
13708 0xfe, 0x66, 0x01, 0xfe, 0x19, 0x58, 0xb3, 0x24, 0x01, 0xfe, 0x0e, 0x1f,
13709 0xfe, 0x30, 0xf4, 0x07,
13710 0xfe, 0x3c, 0x50, 0x7c, 0xfe, 0x38, 0x00, 0xfe, 0x0f, 0x79, 0xfe, 0x1c,
13711 0xf7, 0x24, 0xb1, 0xfe,
13712 0x50, 0x1b, 0xfe, 0xd4, 0x14, 0x31, 0x02, 0xc9, 0x2b, 0xfe, 0x26, 0x1b,
13713 0xfe, 0xba, 0x10, 0x1c,
13714 0x1a, 0x87, 0xfe, 0x83, 0x5a, 0xfe, 0x18, 0xdf, 0xfe, 0x19, 0xde, 0xfe,
13715 0x1d, 0xf7, 0x54, 0xb1,
13716 0xfe, 0x72, 0x1b, 0xfe, 0xb2, 0x14, 0xfc, 0xb3, 0x54, 0x7c, 0x12, 0xfe,
13717 0xaf, 0x19, 0xfe, 0x98,
13718 0xe7, 0x00, 0x02, 0xc9, 0x2b, 0xfe, 0x66, 0x1b, 0xfe, 0x8a, 0x10, 0x1c,
13719 0x1a, 0x87, 0x8b, 0x0f,
13720 0xfe, 0x30, 0x90, 0x04, 0xfe, 0xb0, 0x93, 0x3a, 0x0b, 0xfe, 0x18, 0x58,
13721 0xfe, 0x32, 0x90, 0x04,
13722 0xfe, 0xb2, 0x93, 0x3a, 0x0b, 0xfe, 0x19, 0x58, 0x0e, 0xa8, 0xb3, 0x4a,
13723 0x7c, 0x12, 0xfe, 0x0f,
13724 0x79, 0xfe, 0x1c, 0xf7, 0x4a, 0xb1, 0xfe, 0xc6, 0x1b, 0xfe, 0x5e, 0x14,
13725 0x31, 0x02, 0xc9, 0x2b,
13726 0xfe, 0x96, 0x1b, 0x5c, 0xfe, 0x02, 0xf6, 0x1a, 0x87, 0xfe, 0x18, 0xfe,
13727 0x6a, 0xfe, 0x19, 0xfe,
13728 0x6b, 0x01, 0xfe, 0x1e, 0x1f, 0xfe, 0x1d, 0xf7, 0x65, 0xb1, 0xfe, 0xee,
13729 0x1b, 0xfe, 0x36, 0x14,
13730 0xfe, 0x1c, 0x13, 0xb3, 0x65, 0x3e, 0xfe, 0x83, 0x58, 0xfe, 0xaf, 0x19,
13731 0xfe, 0x80, 0xe7, 0x1a,
13732 0xfe, 0x81, 0xe7, 0x1a, 0x15, 0xfe, 0xdd, 0x00, 0x7a, 0x30, 0x02, 0x7a,
13733 0x30, 0xfe, 0x12, 0x45,
13734 0x2b, 0xfe, 0xdc, 0x1b, 0x1f, 0x07, 0x47, 0xb5, 0xc3, 0x05, 0x35, 0xfe,
13735 0x39, 0xf0, 0x75, 0x26,
13736 0x02, 0xfe, 0x7e, 0x18, 0x23, 0x1d, 0x36, 0x13, 0x11, 0x02, 0x87, 0x03,
13737 0xe3, 0x23, 0x07, 0xfe,
13738 0xef, 0x12, 0xfe, 0xe1, 0x10, 0x90, 0x34, 0x60, 0xfe, 0x02, 0x80, 0x09,
13739 0x56, 0xfe, 0x3c, 0x13,
13740 0xfe, 0x82, 0x14, 0xfe, 0x42, 0x13, 0x51, 0xfe, 0x06, 0x83, 0x0a, 0x5a,
13741 0x01, 0x18, 0xcb, 0xfe,
13742 0x3e, 0x12, 0xfe, 0x41, 0x48, 0xfe, 0x45, 0x48, 0x01, 0xfe, 0xb2, 0x16,
13743 0xfe, 0x00, 0xcc, 0xcb,
13744 0xfe, 0xf3, 0x13, 0x3f, 0x89, 0x09, 0x1a, 0xa5, 0x0a, 0x9d, 0x01, 0x18,
13745 0xfe, 0x80, 0x4c, 0x01,
13746 0x85, 0xfe, 0x16, 0x10, 0x09, 0x9b, 0x4e, 0xfe, 0x40, 0x14, 0xfe, 0x24,
13747 0x12, 0xfe, 0x14, 0x56,
13748 0xfe, 0xd6, 0xf0, 0xfe, 0x52, 0x1c, 0x1c, 0x0d, 0x02, 0xfe, 0x9c, 0xe7,
13749 0x0d, 0x19, 0xfe, 0x15,
13750 0x00, 0x40, 0x8d, 0x30, 0x01, 0xf4, 0x1c, 0x07, 0x02, 0x51, 0xfe, 0x06,
13751 0x83, 0xfe, 0x18, 0x80,
13752 0x61, 0x28, 0x44, 0x15, 0x56, 0x01, 0x85, 0x1c, 0x07, 0x02, 0xfe, 0x38,
13753 0x90, 0xfe, 0xba, 0x90,
13754 0x91, 0xde, 0x7e, 0xdf, 0xfe, 0x48, 0x55, 0x31, 0xfe, 0xc9, 0x55, 0x02,
13755 0x21, 0xb9, 0x88, 0x20,
13756 0xb9, 0x02, 0x0a, 0xba, 0x01, 0x18, 0xfe, 0x41, 0x48, 0x0a, 0x57, 0x01,
13757 0x18, 0xfe, 0x49, 0x44,
13758 0x1b, 0xfe, 0x1e, 0x1d, 0x88, 0x89, 0x02, 0x0a, 0x5a, 0x01, 0x18, 0x09,
13759 0x1a, 0xa4, 0x0a, 0x67,
13760 0x01, 0xa3, 0x0a, 0x57, 0x01, 0x18, 0x88, 0x89, 0x02, 0xfe, 0x4e, 0xe4,
13761 0x1d, 0x7b, 0xfe, 0x52,
13762 0x1d, 0x03, 0xfe, 0x90, 0x00, 0xfe, 0x3a, 0x45, 0xfe, 0x2c, 0x10, 0xfe,
13763 0x4e, 0xe4, 0xdd, 0x7b,
13764 0xfe, 0x64, 0x1d, 0x03, 0xfe, 0x92, 0x00, 0xd1, 0x12, 0xfe, 0x1a, 0x10,
13765 0xfe, 0x4e, 0xe4, 0xfe,
13766 0x0b, 0x00, 0x7b, 0xfe, 0x76, 0x1d, 0x03, 0xfe, 0x94, 0x00, 0xd1, 0x24,
13767 0xfe, 0x08, 0x10, 0x03,
13768 0xfe, 0x96, 0x00, 0xd1, 0x63, 0xfe, 0x4e, 0x45, 0x83, 0xca, 0xff, 0x04,
13769 0x68, 0x54, 0xfe, 0xf1,
13770 0x10, 0x23, 0x49, 0xfe, 0x08, 0x1c, 0xfe, 0x67, 0x19, 0xfe, 0x0a, 0x1c,
13771 0xfe, 0x1a, 0xf4, 0xfe,
13772 0x00, 0x04, 0x83, 0xb2, 0x1d, 0x48, 0xfe, 0xaa, 0x1d, 0x13, 0x1d, 0x02,
13773 0x09, 0x92, 0xfe, 0x5a,
13774 0xf0, 0xfe, 0xba, 0x1d, 0x2e, 0x93, 0xfe, 0x34, 0x10, 0x09, 0x12, 0xfe,
13775 0x5a, 0xf0, 0xfe, 0xc8,
13776 0x1d, 0x2e, 0xb4, 0xfe, 0x26, 0x10, 0x09, 0x1d, 0x36, 0x2e, 0x63, 0xfe,
13777 0x1a, 0x10, 0x09, 0x0d,
13778 0x36, 0x2e, 0x94, 0xf2, 0x09, 0x07, 0x36, 0x2e, 0x95, 0xa1, 0xc8, 0x02,
13779 0x1f, 0x93, 0x01, 0x42,
13780 0xfe, 0x04, 0xfe, 0x99, 0x03, 0x9c, 0x8b, 0x02, 0x2a, 0xfe, 0x1c, 0x1e,
13781 0xfe, 0x14, 0xf0, 0x08,
13782 0x2f, 0xfe, 0x0c, 0x1e, 0x2a, 0xfe, 0x1c, 0x1e, 0x8f, 0xfe, 0x1c, 0x1e,
13783 0xfe, 0x82, 0xf0, 0xfe,
13784 0x10, 0x1e, 0x02, 0x0f, 0x3f, 0x04, 0xfe, 0x80, 0x83, 0x33, 0x0b, 0x0e,
13785 0x02, 0x0f, 0xfe, 0x18,
13786 0x80, 0x04, 0xfe, 0x98, 0x83, 0x33, 0x0b, 0x0e, 0x02, 0x0f, 0xfe, 0x02,
13787 0x80, 0x04, 0xfe, 0x82,
13788 0x83, 0x33, 0x0b, 0x0e, 0x02, 0x0f, 0xfe, 0x06, 0x80, 0x04, 0xfe, 0x86,
13789 0x83, 0x33, 0x0b, 0x0e,
13790 0x02, 0x0f, 0xfe, 0x1b, 0x80, 0x04, 0xfe, 0x9b, 0x83, 0x33, 0x0b, 0x0e,
13791 0x02, 0x0f, 0xfe, 0x04,
13792 0x80, 0x04, 0xfe, 0x84, 0x83, 0x33, 0x0b, 0x0e, 0x02, 0x0f, 0xfe, 0x80,
13793 0x80, 0x04, 0xfe, 0x80,
13794 0x83, 0xfe, 0xc9, 0x47, 0x0b, 0x0e, 0x02, 0x0f, 0xfe, 0x19, 0x81, 0x04,
13795 0xfe, 0x99, 0x83, 0xfe,
13796 0xca, 0x47, 0x0b, 0x0e, 0x02, 0x0f, 0xfe, 0x06, 0x83, 0x04, 0xfe, 0x86,
13797 0x83, 0xfe, 0xce, 0x47,
13798 0x0b, 0x0e, 0x02, 0x0f, 0xfe, 0x2c, 0x90, 0x04, 0xfe, 0xac, 0x93, 0x3a,
13799 0x0b, 0x0e, 0x02, 0x0f,
13800 0xfe, 0xae, 0x90, 0x04, 0xfe, 0xae, 0x93, 0x79, 0x0b, 0x0e, 0x02, 0x0f,
13801 0xfe, 0x08, 0x90, 0x04,
13802 0xfe, 0x88, 0x93, 0x3a, 0x0b, 0x0e, 0x02, 0x0f, 0xfe, 0x8a, 0x90, 0x04,
13803 0xfe, 0x8a, 0x93, 0x79,
13804 0x0b, 0x0e, 0x02, 0x0f, 0xfe, 0x0c, 0x90, 0x04, 0xfe, 0x8c, 0x93, 0x3a,
13805 0x0b, 0x0e, 0x02, 0x0f,
13806 0xfe, 0x8e, 0x90, 0x04, 0xfe, 0x8e, 0x93, 0x79, 0x0b, 0x0e, 0x02, 0x0f,
13807 0xfe, 0x3c, 0x90, 0x04,
13808 0xfe, 0xbc, 0x93, 0x3a, 0x0b, 0x0e, 0x02, 0x8b, 0x0f, 0xfe, 0x03, 0x80,
13809 0x04, 0xfe, 0x83, 0x83,
13810 0x33, 0x0b, 0x77, 0x0e, 0xa8, 0x02, 0xff, 0x66, 0x00, 0x00,
13813 static unsigned short _adv_asc38C1600_size = sizeof(_adv_asc38C1600_buf); /* 0x1673 */
13814 static ADV_DCNT _adv_asc38C1600_chksum = 0x0604EF77UL; /* Expanded little-endian checksum. */
13818 * EEPROM Configuration.
13820 * All drivers should use this structure to set the default EEPROM
13821 * configuration. The BIOS now uses this structure when it is built.
13822 * Additional structure information can be found in a_condor.h where
13823 * the structure is defined.
13825 * The *_Field_IsChar structs are needed to correct for endianness.
13826 * These values are read from the board 16 bits at a time directly
13827 * into the structs. Because some fields are char, the values will be
13828 * in the wrong order. The *_Field_IsChar tells when to flip the
13829 * bytes. Data read and written to PCI memory is automatically swapped
13830 * on big-endian platforms so char fields read as words are actually being
13831 * unswapped on big-endian platforms.
13833 static ADVEEP_3550_CONFIG Default_3550_EEPROM_Config __initdata = {
13834 ADV_EEPROM_BIOS_ENABLE, /* cfg_lsw */
13835 0x0000, /* cfg_msw */
13836 0xFFFF, /* disc_enable */
13837 0xFFFF, /* wdtr_able */
13838 0xFFFF, /* sdtr_able */
13839 0xFFFF, /* start_motor */
13840 0xFFFF, /* tagqng_able */
13841 0xFFFF, /* bios_scan */
13842 0, /* scam_tolerant */
13843 7, /* adapter_scsi_id */
13844 0, /* bios_boot_delay */
13845 3, /* scsi_reset_delay */
13846 0, /* bios_id_lun */
13847 0, /* termination */
13849 0xFFE7, /* bios_ctrl */
13850 0xFFFF, /* ultra_able */
13852 ASC_DEF_MAX_HOST_QNG, /* max_host_qng */
13853 ASC_DEF_MAX_DVC_QNG, /* max_dvc_qng */
13856 0, /* serial_number_word1 */
13857 0, /* serial_number_word2 */
13858 0, /* serial_number_word3 */
13860 {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
13861 , /* oem_name[16] */
13862 0, /* dvc_err_code */
13863 0, /* adv_err_code */
13864 0, /* adv_err_addr */
13865 0, /* saved_dvc_err_code */
13866 0, /* saved_adv_err_code */
13867 0, /* saved_adv_err_addr */
13871 static ADVEEP_3550_CONFIG ADVEEP_3550_Config_Field_IsChar __initdata = {
13874 0, /* -disc_enable */
13877 0, /* start_motor */
13878 0, /* tagqng_able */
13880 0, /* scam_tolerant */
13881 1, /* adapter_scsi_id */
13882 1, /* bios_boot_delay */
13883 1, /* scsi_reset_delay */
13884 1, /* bios_id_lun */
13885 1, /* termination */
13888 0, /* ultra_able */
13890 1, /* max_host_qng */
13891 1, /* max_dvc_qng */
13894 0, /* serial_number_word1 */
13895 0, /* serial_number_word2 */
13896 0, /* serial_number_word3 */
13898 {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1}
13899 , /* oem_name[16] */
13900 0, /* dvc_err_code */
13901 0, /* adv_err_code */
13902 0, /* adv_err_addr */
13903 0, /* saved_dvc_err_code */
13904 0, /* saved_adv_err_code */
13905 0, /* saved_adv_err_addr */
13909 static ADVEEP_38C0800_CONFIG Default_38C0800_EEPROM_Config __initdata = {
13910 ADV_EEPROM_BIOS_ENABLE, /* 00 cfg_lsw */
13911 0x0000, /* 01 cfg_msw */
13912 0xFFFF, /* 02 disc_enable */
13913 0xFFFF, /* 03 wdtr_able */
13914 0x4444, /* 04 sdtr_speed1 */
13915 0xFFFF, /* 05 start_motor */
13916 0xFFFF, /* 06 tagqng_able */
13917 0xFFFF, /* 07 bios_scan */
13918 0, /* 08 scam_tolerant */
13919 7, /* 09 adapter_scsi_id */
13920 0, /* bios_boot_delay */
13921 3, /* 10 scsi_reset_delay */
13922 0, /* bios_id_lun */
13923 0, /* 11 termination_se */
13924 0, /* termination_lvd */
13925 0xFFE7, /* 12 bios_ctrl */
13926 0x4444, /* 13 sdtr_speed2 */
13927 0x4444, /* 14 sdtr_speed3 */
13928 ASC_DEF_MAX_HOST_QNG, /* 15 max_host_qng */
13929 ASC_DEF_MAX_DVC_QNG, /* max_dvc_qng */
13930 0, /* 16 dvc_cntl */
13931 0x4444, /* 17 sdtr_speed4 */
13932 0, /* 18 serial_number_word1 */
13933 0, /* 19 serial_number_word2 */
13934 0, /* 20 serial_number_word3 */
13935 0, /* 21 check_sum */
13936 {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
13937 , /* 22-29 oem_name[16] */
13938 0, /* 30 dvc_err_code */
13939 0, /* 31 adv_err_code */
13940 0, /* 32 adv_err_addr */
13941 0, /* 33 saved_dvc_err_code */
13942 0, /* 34 saved_adv_err_code */
13943 0, /* 35 saved_adv_err_addr */
13944 0, /* 36 reserved */
13945 0, /* 37 reserved */
13946 0, /* 38 reserved */
13947 0, /* 39 reserved */
13948 0, /* 40 reserved */
13949 0, /* 41 reserved */
13950 0, /* 42 reserved */
13951 0, /* 43 reserved */
13952 0, /* 44 reserved */
13953 0, /* 45 reserved */
13954 0, /* 46 reserved */
13955 0, /* 47 reserved */
13956 0, /* 48 reserved */
13957 0, /* 49 reserved */
13958 0, /* 50 reserved */
13959 0, /* 51 reserved */
13960 0, /* 52 reserved */
13961 0, /* 53 reserved */
13962 0, /* 54 reserved */
13963 0, /* 55 reserved */
13964 0, /* 56 cisptr_lsw */
13965 0, /* 57 cisprt_msw */
13966 PCI_VENDOR_ID_ASP, /* 58 subsysvid */
13967 PCI_DEVICE_ID_38C0800_REV1, /* 59 subsysid */
13968 0, /* 60 reserved */
13969 0, /* 61 reserved */
13970 0, /* 62 reserved */
13971 0 /* 63 reserved */
13974 static ADVEEP_38C0800_CONFIG ADVEEP_38C0800_Config_Field_IsChar __initdata = {
13975 0, /* 00 cfg_lsw */
13976 0, /* 01 cfg_msw */
13977 0, /* 02 disc_enable */
13978 0, /* 03 wdtr_able */
13979 0, /* 04 sdtr_speed1 */
13980 0, /* 05 start_motor */
13981 0, /* 06 tagqng_able */
13982 0, /* 07 bios_scan */
13983 0, /* 08 scam_tolerant */
13984 1, /* 09 adapter_scsi_id */
13985 1, /* bios_boot_delay */
13986 1, /* 10 scsi_reset_delay */
13987 1, /* bios_id_lun */
13988 1, /* 11 termination_se */
13989 1, /* termination_lvd */
13990 0, /* 12 bios_ctrl */
13991 0, /* 13 sdtr_speed2 */
13992 0, /* 14 sdtr_speed3 */
13993 1, /* 15 max_host_qng */
13994 1, /* max_dvc_qng */
13995 0, /* 16 dvc_cntl */
13996 0, /* 17 sdtr_speed4 */
13997 0, /* 18 serial_number_word1 */
13998 0, /* 19 serial_number_word2 */
13999 0, /* 20 serial_number_word3 */
14000 0, /* 21 check_sum */
14001 {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1}
14002 , /* 22-29 oem_name[16] */
14003 0, /* 30 dvc_err_code */
14004 0, /* 31 adv_err_code */
14005 0, /* 32 adv_err_addr */
14006 0, /* 33 saved_dvc_err_code */
14007 0, /* 34 saved_adv_err_code */
14008 0, /* 35 saved_adv_err_addr */
14009 0, /* 36 reserved */
14010 0, /* 37 reserved */
14011 0, /* 38 reserved */
14012 0, /* 39 reserved */
14013 0, /* 40 reserved */
14014 0, /* 41 reserved */
14015 0, /* 42 reserved */
14016 0, /* 43 reserved */
14017 0, /* 44 reserved */
14018 0, /* 45 reserved */
14019 0, /* 46 reserved */
14020 0, /* 47 reserved */
14021 0, /* 48 reserved */
14022 0, /* 49 reserved */
14023 0, /* 50 reserved */
14024 0, /* 51 reserved */
14025 0, /* 52 reserved */
14026 0, /* 53 reserved */
14027 0, /* 54 reserved */
14028 0, /* 55 reserved */
14029 0, /* 56 cisptr_lsw */
14030 0, /* 57 cisprt_msw */
14031 0, /* 58 subsysvid */
14032 0, /* 59 subsysid */
14033 0, /* 60 reserved */
14034 0, /* 61 reserved */
14035 0, /* 62 reserved */
14036 0 /* 63 reserved */
14039 static ADVEEP_38C1600_CONFIG Default_38C1600_EEPROM_Config __initdata = {
14040 ADV_EEPROM_BIOS_ENABLE, /* 00 cfg_lsw */
14041 0x0000, /* 01 cfg_msw */
14042 0xFFFF, /* 02 disc_enable */
14043 0xFFFF, /* 03 wdtr_able */
14044 0x5555, /* 04 sdtr_speed1 */
14045 0xFFFF, /* 05 start_motor */
14046 0xFFFF, /* 06 tagqng_able */
14047 0xFFFF, /* 07 bios_scan */
14048 0, /* 08 scam_tolerant */
14049 7, /* 09 adapter_scsi_id */
14050 0, /* bios_boot_delay */
14051 3, /* 10 scsi_reset_delay */
14052 0, /* bios_id_lun */
14053 0, /* 11 termination_se */
14054 0, /* termination_lvd */
14055 0xFFE7, /* 12 bios_ctrl */
14056 0x5555, /* 13 sdtr_speed2 */
14057 0x5555, /* 14 sdtr_speed3 */
14058 ASC_DEF_MAX_HOST_QNG, /* 15 max_host_qng */
14059 ASC_DEF_MAX_DVC_QNG, /* max_dvc_qng */
14060 0, /* 16 dvc_cntl */
14061 0x5555, /* 17 sdtr_speed4 */
14062 0, /* 18 serial_number_word1 */
14063 0, /* 19 serial_number_word2 */
14064 0, /* 20 serial_number_word3 */
14065 0, /* 21 check_sum */
14066 {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
14067 , /* 22-29 oem_name[16] */
14068 0, /* 30 dvc_err_code */
14069 0, /* 31 adv_err_code */
14070 0, /* 32 adv_err_addr */
14071 0, /* 33 saved_dvc_err_code */
14072 0, /* 34 saved_adv_err_code */
14073 0, /* 35 saved_adv_err_addr */
14074 0, /* 36 reserved */
14075 0, /* 37 reserved */
14076 0, /* 38 reserved */
14077 0, /* 39 reserved */
14078 0, /* 40 reserved */
14079 0, /* 41 reserved */
14080 0, /* 42 reserved */
14081 0, /* 43 reserved */
14082 0, /* 44 reserved */
14083 0, /* 45 reserved */
14084 0, /* 46 reserved */
14085 0, /* 47 reserved */
14086 0, /* 48 reserved */
14087 0, /* 49 reserved */
14088 0, /* 50 reserved */
14089 0, /* 51 reserved */
14090 0, /* 52 reserved */
14091 0, /* 53 reserved */
14092 0, /* 54 reserved */
14093 0, /* 55 reserved */
14094 0, /* 56 cisptr_lsw */
14095 0, /* 57 cisprt_msw */
14096 PCI_VENDOR_ID_ASP, /* 58 subsysvid */
14097 PCI_DEVICE_ID_38C1600_REV1, /* 59 subsysid */
14098 0, /* 60 reserved */
14099 0, /* 61 reserved */
14100 0, /* 62 reserved */
14101 0 /* 63 reserved */
14104 static ADVEEP_38C1600_CONFIG ADVEEP_38C1600_Config_Field_IsChar __initdata = {
14105 0, /* 00 cfg_lsw */
14106 0, /* 01 cfg_msw */
14107 0, /* 02 disc_enable */
14108 0, /* 03 wdtr_able */
14109 0, /* 04 sdtr_speed1 */
14110 0, /* 05 start_motor */
14111 0, /* 06 tagqng_able */
14112 0, /* 07 bios_scan */
14113 0, /* 08 scam_tolerant */
14114 1, /* 09 adapter_scsi_id */
14115 1, /* bios_boot_delay */
14116 1, /* 10 scsi_reset_delay */
14117 1, /* bios_id_lun */
14118 1, /* 11 termination_se */
14119 1, /* termination_lvd */
14120 0, /* 12 bios_ctrl */
14121 0, /* 13 sdtr_speed2 */
14122 0, /* 14 sdtr_speed3 */
14123 1, /* 15 max_host_qng */
14124 1, /* max_dvc_qng */
14125 0, /* 16 dvc_cntl */
14126 0, /* 17 sdtr_speed4 */
14127 0, /* 18 serial_number_word1 */
14128 0, /* 19 serial_number_word2 */
14129 0, /* 20 serial_number_word3 */
14130 0, /* 21 check_sum */
14131 {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1}
14132 , /* 22-29 oem_name[16] */
14133 0, /* 30 dvc_err_code */
14134 0, /* 31 adv_err_code */
14135 0, /* 32 adv_err_addr */
14136 0, /* 33 saved_dvc_err_code */
14137 0, /* 34 saved_adv_err_code */
14138 0, /* 35 saved_adv_err_addr */
14139 0, /* 36 reserved */
14140 0, /* 37 reserved */
14141 0, /* 38 reserved */
14142 0, /* 39 reserved */
14143 0, /* 40 reserved */
14144 0, /* 41 reserved */
14145 0, /* 42 reserved */
14146 0, /* 43 reserved */
14147 0, /* 44 reserved */
14148 0, /* 45 reserved */
14149 0, /* 46 reserved */
14150 0, /* 47 reserved */
14151 0, /* 48 reserved */
14152 0, /* 49 reserved */
14153 0, /* 50 reserved */
14154 0, /* 51 reserved */
14155 0, /* 52 reserved */
14156 0, /* 53 reserved */
14157 0, /* 54 reserved */
14158 0, /* 55 reserved */
14159 0, /* 56 cisptr_lsw */
14160 0, /* 57 cisprt_msw */
14161 0, /* 58 subsysvid */
14162 0, /* 59 subsysid */
14163 0, /* 60 reserved */
14164 0, /* 61 reserved */
14165 0, /* 62 reserved */
14166 0 /* 63 reserved */
14170 * Initialize the ADV_DVC_VAR structure.
14172 * On failure set the ADV_DVC_VAR field 'err_code' and return ADV_ERROR.
14174 * For a non-fatal error return a warning code. If there are no warnings
14175 * then 0 is returned.
14177 static int __init AdvInitGetConfig(ADV_DVC_VAR *asc_dvc)
14180 AdvPortAddr iop_base;
14185 asc_dvc->err_code = 0;
14186 iop_base = asc_dvc->iop_base;
14189 * PCI Command Register
14191 * Note: AscPCICmdRegBits_BusMastering definition (0x0007) includes
14192 * I/O Space Control, Memory Space Control and Bus Master Control bits.
14195 if (((pci_cmd_reg = DvcAdvReadPCIConfigByte(asc_dvc,
14196 AscPCIConfigCommandRegister))
14197 & AscPCICmdRegBits_BusMastering)
14198 != AscPCICmdRegBits_BusMastering) {
14199 pci_cmd_reg |= AscPCICmdRegBits_BusMastering;
14201 DvcAdvWritePCIConfigByte(asc_dvc,
14202 AscPCIConfigCommandRegister,
14205 if (((DvcAdvReadPCIConfigByte
14206 (asc_dvc, AscPCIConfigCommandRegister))
14207 & AscPCICmdRegBits_BusMastering)
14208 != AscPCICmdRegBits_BusMastering) {
14209 warn_code |= ASC_WARN_SET_PCI_CONFIG_SPACE;
14214 * PCI Latency Timer
14216 * If the "latency timer" register is 0x20 or above, then we don't need
14217 * to change it. Otherwise, set it to 0x20 (i.e. set it to 0x20 if it
14218 * comes up less than 0x20).
14220 if (DvcAdvReadPCIConfigByte(asc_dvc, AscPCIConfigLatencyTimer) < 0x20) {
14221 DvcAdvWritePCIConfigByte(asc_dvc, AscPCIConfigLatencyTimer,
14223 if (DvcAdvReadPCIConfigByte(asc_dvc, AscPCIConfigLatencyTimer) <
14225 warn_code |= ASC_WARN_SET_PCI_CONFIG_SPACE;
14230 * Save the state of the PCI Configuration Command Register
14231 * "Parity Error Response Control" Bit. If the bit is clear (0),
14232 * in AdvInitAsc3550/38C0800Driver() tell the microcode to ignore
14233 * DMA parity errors.
14235 asc_dvc->cfg->control_flag = 0;
14236 if (((DvcAdvReadPCIConfigByte(asc_dvc, AscPCIConfigCommandRegister)
14237 & AscPCICmdRegBits_ParErrRespCtrl)) == 0) {
14238 asc_dvc->cfg->control_flag |= CONTROL_FLAG_IGNORE_PERR;
14241 asc_dvc->cfg->lib_version = (ADV_LIB_VERSION_MAJOR << 8) |
14242 ADV_LIB_VERSION_MINOR;
14243 asc_dvc->cfg->chip_version =
14244 AdvGetChipVersion(iop_base, asc_dvc->bus_type);
14246 ASC_DBG2(1, "AdvInitGetConfig: iopb_chip_id_1: 0x%x 0x%x\n",
14247 (ushort)AdvReadByteRegister(iop_base, IOPB_CHIP_ID_1),
14248 (ushort)ADV_CHIP_ID_BYTE);
14250 ASC_DBG2(1, "AdvInitGetConfig: iopw_chip_id_0: 0x%x 0x%x\n",
14251 (ushort)AdvReadWordRegister(iop_base, IOPW_CHIP_ID_0),
14252 (ushort)ADV_CHIP_ID_WORD);
14255 * Reset the chip to start and allow register writes.
14257 if (AdvFindSignature(iop_base) == 0) {
14258 asc_dvc->err_code = ASC_IERR_BAD_SIGNATURE;
14262 * The caller must set 'chip_type' to a valid setting.
14264 if (asc_dvc->chip_type != ADV_CHIP_ASC3550 &&
14265 asc_dvc->chip_type != ADV_CHIP_ASC38C0800 &&
14266 asc_dvc->chip_type != ADV_CHIP_ASC38C1600) {
14267 asc_dvc->err_code |= ASC_IERR_BAD_CHIPTYPE;
14274 AdvWriteWordRegister(iop_base, IOPW_CTRL_REG,
14275 ADV_CTRL_REG_CMD_RESET);
14276 DvcSleepMilliSecond(100);
14277 AdvWriteWordRegister(iop_base, IOPW_CTRL_REG,
14278 ADV_CTRL_REG_CMD_WR_IO_REG);
14280 if (asc_dvc->chip_type == ADV_CHIP_ASC38C1600) {
14282 AdvInitFrom38C1600EEP(asc_dvc)) == ADV_ERROR) {
14285 } else if (asc_dvc->chip_type == ADV_CHIP_ASC38C0800) {
14287 AdvInitFrom38C0800EEP(asc_dvc)) == ADV_ERROR) {
14291 if ((status = AdvInitFrom3550EEP(asc_dvc)) == ADV_ERROR) {
14295 warn_code |= status;
14302 * Initialize the ASC-3550.
14304 * On failure set the ADV_DVC_VAR field 'err_code' and return ADV_ERROR.
14306 * For a non-fatal error return a warning code. If there are no warnings
14307 * then 0 is returned.
14309 * Needed after initialization for error recovery.
14311 static int AdvInitAsc3550Driver(ADV_DVC_VAR *asc_dvc)
14313 AdvPortAddr iop_base;
14321 int adv_asc3550_expanded_size;
14323 ADV_DCNT contig_len;
14324 ADV_SDCNT buf_size;
14325 ADV_PADDR carr_paddr;
14329 ushort bios_mem[ASC_MC_BIOSLEN / 2]; /* BIOS RISC Memory 0x40-0x8F. */
14330 ushort wdtr_able = 0, sdtr_able, tagqng_able;
14331 uchar max_cmd[ADV_MAX_TID + 1];
14333 /* If there is already an error, don't continue. */
14334 if (asc_dvc->err_code != 0) {
14339 * The caller must set 'chip_type' to ADV_CHIP_ASC3550.
14341 if (asc_dvc->chip_type != ADV_CHIP_ASC3550) {
14342 asc_dvc->err_code |= ASC_IERR_BAD_CHIPTYPE;
14347 iop_base = asc_dvc->iop_base;
14350 * Save the RISC memory BIOS region before writing the microcode.
14351 * The BIOS may already be loaded and using its RISC LRAM region
14352 * so its region must be saved and restored.
14354 * Note: This code makes the assumption, which is currently true,
14355 * that a chip reset does not clear RISC LRAM.
14357 for (i = 0; i < ASC_MC_BIOSLEN / 2; i++) {
14358 AdvReadWordLram(iop_base, ASC_MC_BIOSMEM + (2 * i),
14363 * Save current per TID negotiated values.
14365 if (bios_mem[(ASC_MC_BIOS_SIGNATURE - ASC_MC_BIOSMEM) / 2] == 0x55AA) {
14366 ushort bios_version, major, minor;
14369 bios_mem[(ASC_MC_BIOS_VERSION - ASC_MC_BIOSMEM) / 2];
14370 major = (bios_version >> 12) & 0xF;
14371 minor = (bios_version >> 8) & 0xF;
14372 if (major < 3 || (major == 3 && minor == 1)) {
14373 /* BIOS 3.1 and earlier location of 'wdtr_able' variable. */
14374 AdvReadWordLram(iop_base, 0x120, wdtr_able);
14376 AdvReadWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able);
14379 AdvReadWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
14380 AdvReadWordLram(iop_base, ASC_MC_TAGQNG_ABLE, tagqng_able);
14381 for (tid = 0; tid <= ADV_MAX_TID; tid++) {
14382 AdvReadByteLram(iop_base, ASC_MC_NUMBER_OF_MAX_CMD + tid,
14387 * Load the Microcode
14389 * Write the microcode image to RISC memory starting at address 0.
14391 AdvWriteWordRegister(iop_base, IOPW_RAM_ADDR, 0);
14392 /* Assume the following compressed format of the microcode buffer:
14394 * 254 word (508 byte) table indexed by byte code followed
14395 * by the following byte codes:
14398 * 00: Emit word 0 in table.
14399 * 01: Emit word 1 in table.
14401 * FD: Emit word 253 in table.
14404 * FE WW WW: (3 byte code) Word to emit is the next word WW WW.
14405 * FF BB WW WW: (4 byte code) Emit BB count times next word WW WW.
14408 for (i = 253 * 2; i < _adv_asc3550_size; i++) {
14409 if (_adv_asc3550_buf[i] == 0xff) {
14410 for (j = 0; j < _adv_asc3550_buf[i + 1]; j++) {
14411 AdvWriteWordAutoIncLram(iop_base, (((ushort)
14420 } else if (_adv_asc3550_buf[i] == 0xfe) {
14421 AdvWriteWordAutoIncLram(iop_base, (((ushort)
14422 _adv_asc3550_buf[i +
14425 _adv_asc3550_buf[i +
14430 AdvWriteWordAutoIncLram(iop_base, (((ushort)
14431 _adv_asc3550_buf[(_adv_asc3550_buf[i] * 2) + 1] << 8) | _adv_asc3550_buf[_adv_asc3550_buf[i] * 2]));
14437 * Set 'word' for later use to clear the rest of memory and save
14438 * the expanded mcode size.
14441 adv_asc3550_expanded_size = word;
14444 * Clear the rest of ASC-3550 Internal RAM (8KB).
14446 for (; word < ADV_3550_MEMSIZE; word += 2) {
14447 AdvWriteWordAutoIncLram(iop_base, 0);
14451 * Verify the microcode checksum.
14454 AdvWriteWordRegister(iop_base, IOPW_RAM_ADDR, 0);
14456 for (word = 0; word < adv_asc3550_expanded_size; word += 2) {
14457 sum += AdvReadWordAutoIncLram(iop_base);
14460 if (sum != _adv_asc3550_chksum) {
14461 asc_dvc->err_code |= ASC_IERR_MCODE_CHKSUM;
14466 * Restore the RISC memory BIOS region.
14468 for (i = 0; i < ASC_MC_BIOSLEN / 2; i++) {
14469 AdvWriteWordLram(iop_base, ASC_MC_BIOSMEM + (2 * i),
14474 * Calculate and write the microcode code checksum to the microcode
14475 * code checksum location ASC_MC_CODE_CHK_SUM (0x2C).
14477 AdvReadWordLram(iop_base, ASC_MC_CODE_BEGIN_ADDR, begin_addr);
14478 AdvReadWordLram(iop_base, ASC_MC_CODE_END_ADDR, end_addr);
14480 AdvWriteWordRegister(iop_base, IOPW_RAM_ADDR, begin_addr);
14481 for (word = begin_addr; word < end_addr; word += 2) {
14482 code_sum += AdvReadWordAutoIncLram(iop_base);
14484 AdvWriteWordLram(iop_base, ASC_MC_CODE_CHK_SUM, code_sum);
14487 * Read and save microcode version and date.
14489 AdvReadWordLram(iop_base, ASC_MC_VERSION_DATE,
14490 asc_dvc->cfg->mcode_date);
14491 AdvReadWordLram(iop_base, ASC_MC_VERSION_NUM,
14492 asc_dvc->cfg->mcode_version);
14495 * Set the chip type to indicate the ASC3550.
14497 AdvWriteWordLram(iop_base, ASC_MC_CHIP_TYPE, ADV_CHIP_ASC3550);
14500 * If the PCI Configuration Command Register "Parity Error Response
14501 * Control" Bit was clear (0), then set the microcode variable
14502 * 'control_flag' CONTROL_FLAG_IGNORE_PERR flag to tell the microcode
14503 * to ignore DMA parity errors.
14505 if (asc_dvc->cfg->control_flag & CONTROL_FLAG_IGNORE_PERR) {
14506 AdvReadWordLram(iop_base, ASC_MC_CONTROL_FLAG, word);
14507 word |= CONTROL_FLAG_IGNORE_PERR;
14508 AdvWriteWordLram(iop_base, ASC_MC_CONTROL_FLAG, word);
14512 * For ASC-3550, setting the START_CTL_EMFU [3:2] bits sets a FIFO
14513 * threshold of 128 bytes. This register is only accessible to the host.
14515 AdvWriteByteRegister(iop_base, IOPB_DMA_CFG0,
14516 START_CTL_EMFU | READ_CMD_MRM);
14519 * Microcode operating variables for WDTR, SDTR, and command tag
14520 * queuing will be set in AdvInquiryHandling() based on what a
14521 * device reports it is capable of in Inquiry byte 7.
14523 * If SCSI Bus Resets have been disabled, then directly set
14524 * SDTR and WDTR from the EEPROM configuration. This will allow
14525 * the BIOS and warm boot to work without a SCSI bus hang on
14526 * the Inquiry caused by host and target mismatched DTR values.
14527 * Without the SCSI Bus Reset, before an Inquiry a device can't
14528 * be assumed to be in Asynchronous, Narrow mode.
14530 if ((asc_dvc->bios_ctrl & BIOS_CTRL_RESET_SCSI_BUS) == 0) {
14531 AdvWriteWordLram(iop_base, ASC_MC_WDTR_ABLE,
14532 asc_dvc->wdtr_able);
14533 AdvWriteWordLram(iop_base, ASC_MC_SDTR_ABLE,
14534 asc_dvc->sdtr_able);
14538 * Set microcode operating variables for SDTR_SPEED1, SDTR_SPEED2,
14539 * SDTR_SPEED3, and SDTR_SPEED4 based on the ULTRA EEPROM per TID
14540 * bitmask. These values determine the maximum SDTR speed negotiated
14543 * The SDTR per TID bitmask overrides the SDTR_SPEED1, SDTR_SPEED2,
14544 * SDTR_SPEED3, and SDTR_SPEED4 values so it is safe to set them
14545 * without determining here whether the device supports SDTR.
14547 * 4-bit speed SDTR speed name
14548 * =========== ===============
14549 * 0000b (0x0) SDTR disabled
14550 * 0001b (0x1) 5 Mhz
14551 * 0010b (0x2) 10 Mhz
14552 * 0011b (0x3) 20 Mhz (Ultra)
14553 * 0100b (0x4) 40 Mhz (LVD/Ultra2)
14554 * 0101b (0x5) 80 Mhz (LVD2/Ultra3)
14555 * 0110b (0x6) Undefined
14557 * 1111b (0xF) Undefined
14560 for (tid = 0; tid <= ADV_MAX_TID; tid++) {
14561 if (ADV_TID_TO_TIDMASK(tid) & asc_dvc->ultra_able) {
14562 /* Set Ultra speed for TID 'tid'. */
14563 word |= (0x3 << (4 * (tid % 4)));
14565 /* Set Fast speed for TID 'tid'. */
14566 word |= (0x2 << (4 * (tid % 4)));
14568 if (tid == 3) { /* Check if done with sdtr_speed1. */
14569 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED1, word);
14571 } else if (tid == 7) { /* Check if done with sdtr_speed2. */
14572 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED2, word);
14574 } else if (tid == 11) { /* Check if done with sdtr_speed3. */
14575 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED3, word);
14577 } else if (tid == 15) { /* Check if done with sdtr_speed4. */
14578 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED4, word);
14584 * Set microcode operating variable for the disconnect per TID bitmask.
14586 AdvWriteWordLram(iop_base, ASC_MC_DISC_ENABLE,
14587 asc_dvc->cfg->disc_enable);
14590 * Set SCSI_CFG0 Microcode Default Value.
14592 * The microcode will set the SCSI_CFG0 register using this value
14593 * after it is started below.
14595 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SCSI_CFG0,
14596 PARITY_EN | QUEUE_128 | SEL_TMO_LONG | OUR_ID_EN |
14597 asc_dvc->chip_scsi_id);
14600 * Determine SCSI_CFG1 Microcode Default Value.
14602 * The microcode will set the SCSI_CFG1 register using this value
14603 * after it is started below.
14606 /* Read current SCSI_CFG1 Register value. */
14607 scsi_cfg1 = AdvReadWordRegister(iop_base, IOPW_SCSI_CFG1);
14610 * If all three connectors are in use, return an error.
14612 if ((scsi_cfg1 & CABLE_ILLEGAL_A) == 0 ||
14613 (scsi_cfg1 & CABLE_ILLEGAL_B) == 0) {
14614 asc_dvc->err_code |= ASC_IERR_ILLEGAL_CONNECTION;
14619 * If the internal narrow cable is reversed all of the SCSI_CTRL
14620 * register signals will be set. Check for and return an error if
14621 * this condition is found.
14623 if ((AdvReadWordRegister(iop_base, IOPW_SCSI_CTRL) & 0x3F07) == 0x3F07) {
14624 asc_dvc->err_code |= ASC_IERR_REVERSED_CABLE;
14629 * If this is a differential board and a single-ended device
14630 * is attached to one of the connectors, return an error.
14632 if ((scsi_cfg1 & DIFF_MODE) && (scsi_cfg1 & DIFF_SENSE) == 0) {
14633 asc_dvc->err_code |= ASC_IERR_SINGLE_END_DEVICE;
14638 * If automatic termination control is enabled, then set the
14639 * termination value based on a table listed in a_condor.h.
14641 * If manual termination was specified with an EEPROM setting
14642 * then 'termination' was set-up in AdvInitFrom3550EEPROM() and
14643 * is ready to be 'ored' into SCSI_CFG1.
14645 if (asc_dvc->cfg->termination == 0) {
14647 * The software always controls termination by setting TERM_CTL_SEL.
14648 * If TERM_CTL_SEL were set to 0, the hardware would set termination.
14650 asc_dvc->cfg->termination |= TERM_CTL_SEL;
14652 switch (scsi_cfg1 & CABLE_DETECT) {
14653 /* TERM_CTL_H: on, TERM_CTL_L: on */
14660 asc_dvc->cfg->termination |= (TERM_CTL_H | TERM_CTL_L);
14663 /* TERM_CTL_H: on, TERM_CTL_L: off */
14669 asc_dvc->cfg->termination |= TERM_CTL_H;
14672 /* TERM_CTL_H: off, TERM_CTL_L: off */
14680 * Clear any set TERM_CTL_H and TERM_CTL_L bits.
14682 scsi_cfg1 &= ~TERM_CTL;
14685 * Invert the TERM_CTL_H and TERM_CTL_L bits and then
14686 * set 'scsi_cfg1'. The TERM_POL bit does not need to be
14687 * referenced, because the hardware internally inverts
14688 * the Termination High and Low bits if TERM_POL is set.
14690 scsi_cfg1 |= (TERM_CTL_SEL | (~asc_dvc->cfg->termination & TERM_CTL));
14693 * Set SCSI_CFG1 Microcode Default Value
14695 * Set filter value and possibly modified termination control
14696 * bits in the Microcode SCSI_CFG1 Register Value.
14698 * The microcode will set the SCSI_CFG1 register using this value
14699 * after it is started below.
14701 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SCSI_CFG1,
14702 FLTR_DISABLE | scsi_cfg1);
14705 * Set MEM_CFG Microcode Default Value
14707 * The microcode will set the MEM_CFG register using this value
14708 * after it is started below.
14710 * MEM_CFG may be accessed as a word or byte, but only bits 0-7
14713 * ASC-3550 has 8KB internal memory.
14715 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_MEM_CFG,
14716 BIOS_EN | RAM_SZ_8KB);
14719 * Set SEL_MASK Microcode Default Value
14721 * The microcode will set the SEL_MASK register using this value
14722 * after it is started below.
14724 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SEL_MASK,
14725 ADV_TID_TO_TIDMASK(asc_dvc->chip_scsi_id));
14728 * Build carrier freelist.
14730 * Driver must have already allocated memory and set 'carrier_buf'.
14732 ASC_ASSERT(asc_dvc->carrier_buf != NULL);
14734 carrp = (ADV_CARR_T *) ADV_16BALIGN(asc_dvc->carrier_buf);
14735 asc_dvc->carr_freelist = NULL;
14736 if (carrp == (ADV_CARR_T *) asc_dvc->carrier_buf) {
14737 buf_size = ADV_CARRIER_BUFSIZE;
14739 buf_size = ADV_CARRIER_BUFSIZE - sizeof(ADV_CARR_T);
14744 * Get physical address of the carrier 'carrp'.
14746 contig_len = sizeof(ADV_CARR_T);
14748 cpu_to_le32(DvcGetPhyAddr
14749 (asc_dvc, NULL, (uchar *)carrp,
14750 (ADV_SDCNT *)&contig_len,
14751 ADV_IS_CARRIER_FLAG));
14753 buf_size -= sizeof(ADV_CARR_T);
14756 * If the current carrier is not physically contiguous, then
14757 * maybe there was a page crossing. Try the next carrier aligned
14760 if (contig_len < sizeof(ADV_CARR_T)) {
14765 carrp->carr_pa = carr_paddr;
14766 carrp->carr_va = cpu_to_le32(ADV_VADDR_TO_U32(carrp));
14769 * Insert the carrier at the beginning of the freelist.
14772 cpu_to_le32(ADV_VADDR_TO_U32(asc_dvc->carr_freelist));
14773 asc_dvc->carr_freelist = carrp;
14777 while (buf_size > 0);
14780 * Set-up the Host->RISC Initiator Command Queue (ICQ).
14783 if ((asc_dvc->icq_sp = asc_dvc->carr_freelist) == NULL) {
14784 asc_dvc->err_code |= ASC_IERR_NO_CARRIER;
14787 asc_dvc->carr_freelist = (ADV_CARR_T *)
14788 ADV_U32_TO_VADDR(le32_to_cpu(asc_dvc->icq_sp->next_vpa));
14791 * The first command issued will be placed in the stopper carrier.
14793 asc_dvc->icq_sp->next_vpa = cpu_to_le32(ASC_CQ_STOPPER);
14796 * Set RISC ICQ physical address start value.
14798 AdvWriteDWordLramNoSwap(iop_base, ASC_MC_ICQ, asc_dvc->icq_sp->carr_pa);
14801 * Set-up the RISC->Host Initiator Response Queue (IRQ).
14803 if ((asc_dvc->irq_sp = asc_dvc->carr_freelist) == NULL) {
14804 asc_dvc->err_code |= ASC_IERR_NO_CARRIER;
14807 asc_dvc->carr_freelist = (ADV_CARR_T *)
14808 ADV_U32_TO_VADDR(le32_to_cpu(asc_dvc->irq_sp->next_vpa));
14811 * The first command completed by the RISC will be placed in
14814 * Note: Set 'next_vpa' to ASC_CQ_STOPPER. When the request is
14815 * completed the RISC will set the ASC_RQ_STOPPER bit.
14817 asc_dvc->irq_sp->next_vpa = cpu_to_le32(ASC_CQ_STOPPER);
14820 * Set RISC IRQ physical address start value.
14822 AdvWriteDWordLramNoSwap(iop_base, ASC_MC_IRQ, asc_dvc->irq_sp->carr_pa);
14823 asc_dvc->carr_pending_cnt = 0;
14825 AdvWriteByteRegister(iop_base, IOPB_INTR_ENABLES,
14826 (ADV_INTR_ENABLE_HOST_INTR |
14827 ADV_INTR_ENABLE_GLOBAL_INTR));
14829 AdvReadWordLram(iop_base, ASC_MC_CODE_BEGIN_ADDR, word);
14830 AdvWriteWordRegister(iop_base, IOPW_PC, word);
14832 /* finally, finally, gentlemen, start your engine */
14833 AdvWriteWordRegister(iop_base, IOPW_RISC_CSR, ADV_RISC_CSR_RUN);
14836 * Reset the SCSI Bus if the EEPROM indicates that SCSI Bus
14837 * Resets should be performed. The RISC has to be running
14838 * to issue a SCSI Bus Reset.
14840 if (asc_dvc->bios_ctrl & BIOS_CTRL_RESET_SCSI_BUS) {
14842 * If the BIOS Signature is present in memory, restore the
14843 * BIOS Handshake Configuration Table and do not perform
14844 * a SCSI Bus Reset.
14846 if (bios_mem[(ASC_MC_BIOS_SIGNATURE - ASC_MC_BIOSMEM) / 2] ==
14849 * Restore per TID negotiated values.
14851 AdvWriteWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able);
14852 AdvWriteWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
14853 AdvWriteWordLram(iop_base, ASC_MC_TAGQNG_ABLE,
14855 for (tid = 0; tid <= ADV_MAX_TID; tid++) {
14856 AdvWriteByteLram(iop_base,
14857 ASC_MC_NUMBER_OF_MAX_CMD + tid,
14861 if (AdvResetSB(asc_dvc) != ADV_TRUE) {
14862 warn_code = ASC_WARN_BUSRESET_ERROR;
14871 * Initialize the ASC-38C0800.
14873 * On failure set the ADV_DVC_VAR field 'err_code' and return ADV_ERROR.
14875 * For a non-fatal error return a warning code. If there are no warnings
14876 * then 0 is returned.
14878 * Needed after initialization for error recovery.
14880 static int AdvInitAsc38C0800Driver(ADV_DVC_VAR *asc_dvc)
14882 AdvPortAddr iop_base;
14890 int adv_asc38C0800_expanded_size;
14892 ADV_DCNT contig_len;
14893 ADV_SDCNT buf_size;
14894 ADV_PADDR carr_paddr;
14899 ushort bios_mem[ASC_MC_BIOSLEN / 2]; /* BIOS RISC Memory 0x40-0x8F. */
14900 ushort wdtr_able, sdtr_able, tagqng_able;
14901 uchar max_cmd[ADV_MAX_TID + 1];
14903 /* If there is already an error, don't continue. */
14904 if (asc_dvc->err_code != 0) {
14909 * The caller must set 'chip_type' to ADV_CHIP_ASC38C0800.
14911 if (asc_dvc->chip_type != ADV_CHIP_ASC38C0800) {
14912 asc_dvc->err_code = ASC_IERR_BAD_CHIPTYPE;
14917 iop_base = asc_dvc->iop_base;
14920 * Save the RISC memory BIOS region before writing the microcode.
14921 * The BIOS may already be loaded and using its RISC LRAM region
14922 * so its region must be saved and restored.
14924 * Note: This code makes the assumption, which is currently true,
14925 * that a chip reset does not clear RISC LRAM.
14927 for (i = 0; i < ASC_MC_BIOSLEN / 2; i++) {
14928 AdvReadWordLram(iop_base, ASC_MC_BIOSMEM + (2 * i),
14933 * Save current per TID negotiated values.
14935 AdvReadWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able);
14936 AdvReadWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
14937 AdvReadWordLram(iop_base, ASC_MC_TAGQNG_ABLE, tagqng_able);
14938 for (tid = 0; tid <= ADV_MAX_TID; tid++) {
14939 AdvReadByteLram(iop_base, ASC_MC_NUMBER_OF_MAX_CMD + tid,
14944 * RAM BIST (RAM Built-In Self Test)
14946 * Address : I/O base + offset 0x38h register (byte).
14947 * Function: Bit 7-6(RW) : RAM mode
14948 * Normal Mode : 0x00
14949 * Pre-test Mode : 0x40
14950 * RAM Test Mode : 0x80
14952 * Bit 4(RO) : Done bit
14953 * Bit 3-0(RO) : Status
14954 * Host Error : 0x08
14955 * Int_RAM Error : 0x04
14956 * RISC Error : 0x02
14957 * SCSI Error : 0x01
14960 * Note: RAM BIST code should be put right here, before loading the
14961 * microcode and after saving the RISC memory BIOS region.
14967 * Write PRE_TEST_MODE (0x40) to register and wait for 10 milliseconds.
14968 * If Done bit not set or low nibble not PRE_TEST_VALUE (0x05), return
14969 * an error. Reset to NORMAL_MODE (0x00) and do again. If cannot reset
14970 * to NORMAL_MODE, return an error too.
14972 for (i = 0; i < 2; i++) {
14973 AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, PRE_TEST_MODE);
14974 DvcSleepMilliSecond(10); /* Wait for 10ms before reading back. */
14975 byte = AdvReadByteRegister(iop_base, IOPB_RAM_BIST);
14976 if ((byte & RAM_TEST_DONE) == 0
14977 || (byte & 0x0F) != PRE_TEST_VALUE) {
14978 asc_dvc->err_code |= ASC_IERR_BIST_PRE_TEST;
14982 AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, NORMAL_MODE);
14983 DvcSleepMilliSecond(10); /* Wait for 10ms before reading back. */
14984 if (AdvReadByteRegister(iop_base, IOPB_RAM_BIST)
14986 asc_dvc->err_code |= ASC_IERR_BIST_PRE_TEST;
14992 * LRAM Test - It takes about 1.5 ms to run through the test.
14994 * Write RAM_TEST_MODE (0x80) to register and wait for 10 milliseconds.
14995 * If Done bit not set or Status not 0, save register byte, set the
14996 * err_code, and return an error.
14998 AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, RAM_TEST_MODE);
14999 DvcSleepMilliSecond(10); /* Wait for 10ms before checking status. */
15001 byte = AdvReadByteRegister(iop_base, IOPB_RAM_BIST);
15002 if ((byte & RAM_TEST_DONE) == 0 || (byte & RAM_TEST_STATUS) != 0) {
15003 /* Get here if Done bit not set or Status not 0. */
15004 asc_dvc->bist_err_code = byte; /* for BIOS display message */
15005 asc_dvc->err_code |= ASC_IERR_BIST_RAM_TEST;
15009 /* We need to reset back to normal mode after LRAM test passes. */
15010 AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, NORMAL_MODE);
15013 * Load the Microcode
15015 * Write the microcode image to RISC memory starting at address 0.
15018 AdvWriteWordRegister(iop_base, IOPW_RAM_ADDR, 0);
15020 /* Assume the following compressed format of the microcode buffer:
15022 * 254 word (508 byte) table indexed by byte code followed
15023 * by the following byte codes:
15026 * 00: Emit word 0 in table.
15027 * 01: Emit word 1 in table.
15029 * FD: Emit word 253 in table.
15032 * FE WW WW: (3 byte code) Word to emit is the next word WW WW.
15033 * FF BB WW WW: (4 byte code) Emit BB count times next word WW WW.
15036 for (i = 253 * 2; i < _adv_asc38C0800_size; i++) {
15037 if (_adv_asc38C0800_buf[i] == 0xff) {
15038 for (j = 0; j < _adv_asc38C0800_buf[i + 1]; j++) {
15039 AdvWriteWordAutoIncLram(iop_base, (((ushort)
15040 _adv_asc38C0800_buf
15043 _adv_asc38C0800_buf
15048 } else if (_adv_asc38C0800_buf[i] == 0xfe) {
15049 AdvWriteWordAutoIncLram(iop_base, (((ushort)
15050 _adv_asc38C0800_buf
15053 _adv_asc38C0800_buf[i
15059 AdvWriteWordAutoIncLram(iop_base, (((ushort)
15060 _adv_asc38C0800_buf[(_adv_asc38C0800_buf[i] * 2) + 1] << 8) | _adv_asc38C0800_buf[_adv_asc38C0800_buf[i] * 2]));
15066 * Set 'word' for later use to clear the rest of memory and save
15067 * the expanded mcode size.
15070 adv_asc38C0800_expanded_size = word;
15073 * Clear the rest of ASC-38C0800 Internal RAM (16KB).
15075 for (; word < ADV_38C0800_MEMSIZE; word += 2) {
15076 AdvWriteWordAutoIncLram(iop_base, 0);
15080 * Verify the microcode checksum.
15083 AdvWriteWordRegister(iop_base, IOPW_RAM_ADDR, 0);
15085 for (word = 0; word < adv_asc38C0800_expanded_size; word += 2) {
15086 sum += AdvReadWordAutoIncLram(iop_base);
15088 ASC_DBG2(1, "AdvInitAsc38C0800Driver: word %d, i %d\n", word, i);
15091 "AdvInitAsc38C0800Driver: sum 0x%lx, _adv_asc38C0800_chksum 0x%lx\n",
15092 (ulong)sum, (ulong)_adv_asc38C0800_chksum);
15094 if (sum != _adv_asc38C0800_chksum) {
15095 asc_dvc->err_code |= ASC_IERR_MCODE_CHKSUM;
15100 * Restore the RISC memory BIOS region.
15102 for (i = 0; i < ASC_MC_BIOSLEN / 2; i++) {
15103 AdvWriteWordLram(iop_base, ASC_MC_BIOSMEM + (2 * i),
15108 * Calculate and write the microcode code checksum to the microcode
15109 * code checksum location ASC_MC_CODE_CHK_SUM (0x2C).
15111 AdvReadWordLram(iop_base, ASC_MC_CODE_BEGIN_ADDR, begin_addr);
15112 AdvReadWordLram(iop_base, ASC_MC_CODE_END_ADDR, end_addr);
15114 AdvWriteWordRegister(iop_base, IOPW_RAM_ADDR, begin_addr);
15115 for (word = begin_addr; word < end_addr; word += 2) {
15116 code_sum += AdvReadWordAutoIncLram(iop_base);
15118 AdvWriteWordLram(iop_base, ASC_MC_CODE_CHK_SUM, code_sum);
15121 * Read microcode version and date.
15123 AdvReadWordLram(iop_base, ASC_MC_VERSION_DATE,
15124 asc_dvc->cfg->mcode_date);
15125 AdvReadWordLram(iop_base, ASC_MC_VERSION_NUM,
15126 asc_dvc->cfg->mcode_version);
15129 * Set the chip type to indicate the ASC38C0800.
15131 AdvWriteWordLram(iop_base, ASC_MC_CHIP_TYPE, ADV_CHIP_ASC38C0800);
15134 * Write 1 to bit 14 'DIS_TERM_DRV' in the SCSI_CFG1 register.
15135 * When DIS_TERM_DRV set to 1, C_DET[3:0] will reflect current
15136 * cable detection and then we are able to read C_DET[3:0].
15138 * Note: We will reset DIS_TERM_DRV to 0 in the 'Set SCSI_CFG1
15139 * Microcode Default Value' section below.
15141 scsi_cfg1 = AdvReadWordRegister(iop_base, IOPW_SCSI_CFG1);
15142 AdvWriteWordRegister(iop_base, IOPW_SCSI_CFG1,
15143 scsi_cfg1 | DIS_TERM_DRV);
15146 * If the PCI Configuration Command Register "Parity Error Response
15147 * Control" Bit was clear (0), then set the microcode variable
15148 * 'control_flag' CONTROL_FLAG_IGNORE_PERR flag to tell the microcode
15149 * to ignore DMA parity errors.
15151 if (asc_dvc->cfg->control_flag & CONTROL_FLAG_IGNORE_PERR) {
15152 AdvReadWordLram(iop_base, ASC_MC_CONTROL_FLAG, word);
15153 word |= CONTROL_FLAG_IGNORE_PERR;
15154 AdvWriteWordLram(iop_base, ASC_MC_CONTROL_FLAG, word);
15158 * For ASC-38C0800, set FIFO_THRESH_80B [6:4] bits and START_CTL_TH [3:2]
15159 * bits for the default FIFO threshold.
15161 * Note: ASC-38C0800 FIFO threshold has been changed to 256 bytes.
15163 * For DMA Errata #4 set the BC_THRESH_ENB bit.
15165 AdvWriteByteRegister(iop_base, IOPB_DMA_CFG0,
15166 BC_THRESH_ENB | FIFO_THRESH_80B | START_CTL_TH |
15170 * Microcode operating variables for WDTR, SDTR, and command tag
15171 * queuing will be set in AdvInquiryHandling() based on what a
15172 * device reports it is capable of in Inquiry byte 7.
15174 * If SCSI Bus Resets have been disabled, then directly set
15175 * SDTR and WDTR from the EEPROM configuration. This will allow
15176 * the BIOS and warm boot to work without a SCSI bus hang on
15177 * the Inquiry caused by host and target mismatched DTR values.
15178 * Without the SCSI Bus Reset, before an Inquiry a device can't
15179 * be assumed to be in Asynchronous, Narrow mode.
15181 if ((asc_dvc->bios_ctrl & BIOS_CTRL_RESET_SCSI_BUS) == 0) {
15182 AdvWriteWordLram(iop_base, ASC_MC_WDTR_ABLE,
15183 asc_dvc->wdtr_able);
15184 AdvWriteWordLram(iop_base, ASC_MC_SDTR_ABLE,
15185 asc_dvc->sdtr_able);
15189 * Set microcode operating variables for DISC and SDTR_SPEED1,
15190 * SDTR_SPEED2, SDTR_SPEED3, and SDTR_SPEED4 based on the EEPROM
15191 * configuration values.
15193 * The SDTR per TID bitmask overrides the SDTR_SPEED1, SDTR_SPEED2,
15194 * SDTR_SPEED3, and SDTR_SPEED4 values so it is safe to set them
15195 * without determining here whether the device supports SDTR.
15197 AdvWriteWordLram(iop_base, ASC_MC_DISC_ENABLE,
15198 asc_dvc->cfg->disc_enable);
15199 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED1, asc_dvc->sdtr_speed1);
15200 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED2, asc_dvc->sdtr_speed2);
15201 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED3, asc_dvc->sdtr_speed3);
15202 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED4, asc_dvc->sdtr_speed4);
15205 * Set SCSI_CFG0 Microcode Default Value.
15207 * The microcode will set the SCSI_CFG0 register using this value
15208 * after it is started below.
15210 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SCSI_CFG0,
15211 PARITY_EN | QUEUE_128 | SEL_TMO_LONG | OUR_ID_EN |
15212 asc_dvc->chip_scsi_id);
15215 * Determine SCSI_CFG1 Microcode Default Value.
15217 * The microcode will set the SCSI_CFG1 register using this value
15218 * after it is started below.
15221 /* Read current SCSI_CFG1 Register value. */
15222 scsi_cfg1 = AdvReadWordRegister(iop_base, IOPW_SCSI_CFG1);
15225 * If the internal narrow cable is reversed all of the SCSI_CTRL
15226 * register signals will be set. Check for and return an error if
15227 * this condition is found.
15229 if ((AdvReadWordRegister(iop_base, IOPW_SCSI_CTRL) & 0x3F07) == 0x3F07) {
15230 asc_dvc->err_code |= ASC_IERR_REVERSED_CABLE;
15235 * All kind of combinations of devices attached to one of four connectors
15236 * are acceptable except HVD device attached. For example, LVD device can
15237 * be attached to SE connector while SE device attached to LVD connector.
15238 * If LVD device attached to SE connector, it only runs up to Ultra speed.
15240 * If an HVD device is attached to one of LVD connectors, return an error.
15241 * However, there is no way to detect HVD device attached to SE connectors.
15243 if (scsi_cfg1 & HVD) {
15244 asc_dvc->err_code |= ASC_IERR_HVD_DEVICE;
15249 * If either SE or LVD automatic termination control is enabled, then
15250 * set the termination value based on a table listed in a_condor.h.
15252 * If manual termination was specified with an EEPROM setting then
15253 * 'termination' was set-up in AdvInitFrom38C0800EEPROM() and is ready to
15254 * be 'ored' into SCSI_CFG1.
15256 if ((asc_dvc->cfg->termination & TERM_SE) == 0) {
15257 /* SE automatic termination control is enabled. */
15258 switch (scsi_cfg1 & C_DET_SE) {
15259 /* TERM_SE_HI: on, TERM_SE_LO: on */
15263 asc_dvc->cfg->termination |= TERM_SE;
15266 /* TERM_SE_HI: on, TERM_SE_LO: off */
15268 asc_dvc->cfg->termination |= TERM_SE_HI;
15273 if ((asc_dvc->cfg->termination & TERM_LVD) == 0) {
15274 /* LVD automatic termination control is enabled. */
15275 switch (scsi_cfg1 & C_DET_LVD) {
15276 /* TERM_LVD_HI: on, TERM_LVD_LO: on */
15280 asc_dvc->cfg->termination |= TERM_LVD;
15283 /* TERM_LVD_HI: off, TERM_LVD_LO: off */
15290 * Clear any set TERM_SE and TERM_LVD bits.
15292 scsi_cfg1 &= (~TERM_SE & ~TERM_LVD);
15295 * Invert the TERM_SE and TERM_LVD bits and then set 'scsi_cfg1'.
15297 scsi_cfg1 |= (~asc_dvc->cfg->termination & 0xF0);
15300 * Clear BIG_ENDIAN, DIS_TERM_DRV, Terminator Polarity and HVD/LVD/SE bits
15301 * and set possibly modified termination control bits in the Microcode
15302 * SCSI_CFG1 Register Value.
15304 scsi_cfg1 &= (~BIG_ENDIAN & ~DIS_TERM_DRV & ~TERM_POL & ~HVD_LVD_SE);
15307 * Set SCSI_CFG1 Microcode Default Value
15309 * Set possibly modified termination control and reset DIS_TERM_DRV
15310 * bits in the Microcode SCSI_CFG1 Register Value.
15312 * The microcode will set the SCSI_CFG1 register using this value
15313 * after it is started below.
15315 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SCSI_CFG1, scsi_cfg1);
15318 * Set MEM_CFG Microcode Default Value
15320 * The microcode will set the MEM_CFG register using this value
15321 * after it is started below.
15323 * MEM_CFG may be accessed as a word or byte, but only bits 0-7
15326 * ASC-38C0800 has 16KB internal memory.
15328 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_MEM_CFG,
15329 BIOS_EN | RAM_SZ_16KB);
15332 * Set SEL_MASK Microcode Default Value
15334 * The microcode will set the SEL_MASK register using this value
15335 * after it is started below.
15337 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SEL_MASK,
15338 ADV_TID_TO_TIDMASK(asc_dvc->chip_scsi_id));
15341 * Build the carrier freelist.
15343 * Driver must have already allocated memory and set 'carrier_buf'.
15345 ASC_ASSERT(asc_dvc->carrier_buf != NULL);
15347 carrp = (ADV_CARR_T *) ADV_16BALIGN(asc_dvc->carrier_buf);
15348 asc_dvc->carr_freelist = NULL;
15349 if (carrp == (ADV_CARR_T *) asc_dvc->carrier_buf) {
15350 buf_size = ADV_CARRIER_BUFSIZE;
15352 buf_size = ADV_CARRIER_BUFSIZE - sizeof(ADV_CARR_T);
15357 * Get physical address for the carrier 'carrp'.
15359 contig_len = sizeof(ADV_CARR_T);
15361 cpu_to_le32(DvcGetPhyAddr
15362 (asc_dvc, NULL, (uchar *)carrp,
15363 (ADV_SDCNT *)&contig_len,
15364 ADV_IS_CARRIER_FLAG));
15366 buf_size -= sizeof(ADV_CARR_T);
15369 * If the current carrier is not physically contiguous, then
15370 * maybe there was a page crossing. Try the next carrier aligned
15373 if (contig_len < sizeof(ADV_CARR_T)) {
15378 carrp->carr_pa = carr_paddr;
15379 carrp->carr_va = cpu_to_le32(ADV_VADDR_TO_U32(carrp));
15382 * Insert the carrier at the beginning of the freelist.
15385 cpu_to_le32(ADV_VADDR_TO_U32(asc_dvc->carr_freelist));
15386 asc_dvc->carr_freelist = carrp;
15390 while (buf_size > 0);
15393 * Set-up the Host->RISC Initiator Command Queue (ICQ).
15396 if ((asc_dvc->icq_sp = asc_dvc->carr_freelist) == NULL) {
15397 asc_dvc->err_code |= ASC_IERR_NO_CARRIER;
15400 asc_dvc->carr_freelist = (ADV_CARR_T *)
15401 ADV_U32_TO_VADDR(le32_to_cpu(asc_dvc->icq_sp->next_vpa));
15404 * The first command issued will be placed in the stopper carrier.
15406 asc_dvc->icq_sp->next_vpa = cpu_to_le32(ASC_CQ_STOPPER);
15409 * Set RISC ICQ physical address start value.
15410 * carr_pa is LE, must be native before write
15412 AdvWriteDWordLramNoSwap(iop_base, ASC_MC_ICQ, asc_dvc->icq_sp->carr_pa);
15415 * Set-up the RISC->Host Initiator Response Queue (IRQ).
15417 if ((asc_dvc->irq_sp = asc_dvc->carr_freelist) == NULL) {
15418 asc_dvc->err_code |= ASC_IERR_NO_CARRIER;
15421 asc_dvc->carr_freelist = (ADV_CARR_T *)
15422 ADV_U32_TO_VADDR(le32_to_cpu(asc_dvc->irq_sp->next_vpa));
15425 * The first command completed by the RISC will be placed in
15428 * Note: Set 'next_vpa' to ASC_CQ_STOPPER. When the request is
15429 * completed the RISC will set the ASC_RQ_STOPPER bit.
15431 asc_dvc->irq_sp->next_vpa = cpu_to_le32(ASC_CQ_STOPPER);
15434 * Set RISC IRQ physical address start value.
15436 * carr_pa is LE, must be native before write *
15438 AdvWriteDWordLramNoSwap(iop_base, ASC_MC_IRQ, asc_dvc->irq_sp->carr_pa);
15439 asc_dvc->carr_pending_cnt = 0;
15441 AdvWriteByteRegister(iop_base, IOPB_INTR_ENABLES,
15442 (ADV_INTR_ENABLE_HOST_INTR |
15443 ADV_INTR_ENABLE_GLOBAL_INTR));
15445 AdvReadWordLram(iop_base, ASC_MC_CODE_BEGIN_ADDR, word);
15446 AdvWriteWordRegister(iop_base, IOPW_PC, word);
15448 /* finally, finally, gentlemen, start your engine */
15449 AdvWriteWordRegister(iop_base, IOPW_RISC_CSR, ADV_RISC_CSR_RUN);
15452 * Reset the SCSI Bus if the EEPROM indicates that SCSI Bus
15453 * Resets should be performed. The RISC has to be running
15454 * to issue a SCSI Bus Reset.
15456 if (asc_dvc->bios_ctrl & BIOS_CTRL_RESET_SCSI_BUS) {
15458 * If the BIOS Signature is present in memory, restore the
15459 * BIOS Handshake Configuration Table and do not perform
15460 * a SCSI Bus Reset.
15462 if (bios_mem[(ASC_MC_BIOS_SIGNATURE - ASC_MC_BIOSMEM) / 2] ==
15465 * Restore per TID negotiated values.
15467 AdvWriteWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able);
15468 AdvWriteWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
15469 AdvWriteWordLram(iop_base, ASC_MC_TAGQNG_ABLE,
15471 for (tid = 0; tid <= ADV_MAX_TID; tid++) {
15472 AdvWriteByteLram(iop_base,
15473 ASC_MC_NUMBER_OF_MAX_CMD + tid,
15477 if (AdvResetSB(asc_dvc) != ADV_TRUE) {
15478 warn_code = ASC_WARN_BUSRESET_ERROR;
15487 * Initialize the ASC-38C1600.
15489 * On failure set the ASC_DVC_VAR field 'err_code' and return ADV_ERROR.
15491 * For a non-fatal error return a warning code. If there are no warnings
15492 * then 0 is returned.
15494 * Needed after initialization for error recovery.
15496 static int AdvInitAsc38C1600Driver(ADV_DVC_VAR *asc_dvc)
15498 AdvPortAddr iop_base;
15506 int adv_asc38C1600_expanded_size;
15508 ADV_DCNT contig_len;
15509 ADV_SDCNT buf_size;
15510 ADV_PADDR carr_paddr;
15515 ushort bios_mem[ASC_MC_BIOSLEN / 2]; /* BIOS RISC Memory 0x40-0x8F. */
15516 ushort wdtr_able, sdtr_able, ppr_able, tagqng_able;
15517 uchar max_cmd[ASC_MAX_TID + 1];
15519 /* If there is already an error, don't continue. */
15520 if (asc_dvc->err_code != 0) {
15525 * The caller must set 'chip_type' to ADV_CHIP_ASC38C1600.
15527 if (asc_dvc->chip_type != ADV_CHIP_ASC38C1600) {
15528 asc_dvc->err_code = ASC_IERR_BAD_CHIPTYPE;
15533 iop_base = asc_dvc->iop_base;
15536 * Save the RISC memory BIOS region before writing the microcode.
15537 * The BIOS may already be loaded and using its RISC LRAM region
15538 * so its region must be saved and restored.
15540 * Note: This code makes the assumption, which is currently true,
15541 * that a chip reset does not clear RISC LRAM.
15543 for (i = 0; i < ASC_MC_BIOSLEN / 2; i++) {
15544 AdvReadWordLram(iop_base, ASC_MC_BIOSMEM + (2 * i),
15549 * Save current per TID negotiated values.
15551 AdvReadWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able);
15552 AdvReadWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
15553 AdvReadWordLram(iop_base, ASC_MC_PPR_ABLE, ppr_able);
15554 AdvReadWordLram(iop_base, ASC_MC_TAGQNG_ABLE, tagqng_able);
15555 for (tid = 0; tid <= ASC_MAX_TID; tid++) {
15556 AdvReadByteLram(iop_base, ASC_MC_NUMBER_OF_MAX_CMD + tid,
15561 * RAM BIST (Built-In Self Test)
15563 * Address : I/O base + offset 0x38h register (byte).
15564 * Function: Bit 7-6(RW) : RAM mode
15565 * Normal Mode : 0x00
15566 * Pre-test Mode : 0x40
15567 * RAM Test Mode : 0x80
15569 * Bit 4(RO) : Done bit
15570 * Bit 3-0(RO) : Status
15571 * Host Error : 0x08
15572 * Int_RAM Error : 0x04
15573 * RISC Error : 0x02
15574 * SCSI Error : 0x01
15577 * Note: RAM BIST code should be put right here, before loading the
15578 * microcode and after saving the RISC memory BIOS region.
15584 * Write PRE_TEST_MODE (0x40) to register and wait for 10 milliseconds.
15585 * If Done bit not set or low nibble not PRE_TEST_VALUE (0x05), return
15586 * an error. Reset to NORMAL_MODE (0x00) and do again. If cannot reset
15587 * to NORMAL_MODE, return an error too.
15589 for (i = 0; i < 2; i++) {
15590 AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, PRE_TEST_MODE);
15591 DvcSleepMilliSecond(10); /* Wait for 10ms before reading back. */
15592 byte = AdvReadByteRegister(iop_base, IOPB_RAM_BIST);
15593 if ((byte & RAM_TEST_DONE) == 0
15594 || (byte & 0x0F) != PRE_TEST_VALUE) {
15595 asc_dvc->err_code |= ASC_IERR_BIST_PRE_TEST;
15599 AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, NORMAL_MODE);
15600 DvcSleepMilliSecond(10); /* Wait for 10ms before reading back. */
15601 if (AdvReadByteRegister(iop_base, IOPB_RAM_BIST)
15603 asc_dvc->err_code |= ASC_IERR_BIST_PRE_TEST;
15609 * LRAM Test - It takes about 1.5 ms to run through the test.
15611 * Write RAM_TEST_MODE (0x80) to register and wait for 10 milliseconds.
15612 * If Done bit not set or Status not 0, save register byte, set the
15613 * err_code, and return an error.
15615 AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, RAM_TEST_MODE);
15616 DvcSleepMilliSecond(10); /* Wait for 10ms before checking status. */
15618 byte = AdvReadByteRegister(iop_base, IOPB_RAM_BIST);
15619 if ((byte & RAM_TEST_DONE) == 0 || (byte & RAM_TEST_STATUS) != 0) {
15620 /* Get here if Done bit not set or Status not 0. */
15621 asc_dvc->bist_err_code = byte; /* for BIOS display message */
15622 asc_dvc->err_code |= ASC_IERR_BIST_RAM_TEST;
15626 /* We need to reset back to normal mode after LRAM test passes. */
15627 AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, NORMAL_MODE);
15630 * Load the Microcode
15632 * Write the microcode image to RISC memory starting at address 0.
15635 AdvWriteWordRegister(iop_base, IOPW_RAM_ADDR, 0);
15638 * Assume the following compressed format of the microcode buffer:
15640 * 254 word (508 byte) table indexed by byte code followed
15641 * by the following byte codes:
15644 * 00: Emit word 0 in table.
15645 * 01: Emit word 1 in table.
15647 * FD: Emit word 253 in table.
15650 * FE WW WW: (3 byte code) Word to emit is the next word WW WW.
15651 * FF BB WW WW: (4 byte code) Emit BB count times next word WW WW.
15654 for (i = 253 * 2; i < _adv_asc38C1600_size; i++) {
15655 if (_adv_asc38C1600_buf[i] == 0xff) {
15656 for (j = 0; j < _adv_asc38C1600_buf[i + 1]; j++) {
15657 AdvWriteWordAutoIncLram(iop_base, (((ushort)
15658 _adv_asc38C1600_buf
15661 _adv_asc38C1600_buf
15666 } else if (_adv_asc38C1600_buf[i] == 0xfe) {
15667 AdvWriteWordAutoIncLram(iop_base, (((ushort)
15668 _adv_asc38C1600_buf
15671 _adv_asc38C1600_buf[i
15677 AdvWriteWordAutoIncLram(iop_base, (((ushort)
15678 _adv_asc38C1600_buf[(_adv_asc38C1600_buf[i] * 2) + 1] << 8) | _adv_asc38C1600_buf[_adv_asc38C1600_buf[i] * 2]));
15684 * Set 'word' for later use to clear the rest of memory and save
15685 * the expanded mcode size.
15688 adv_asc38C1600_expanded_size = word;
15691 * Clear the rest of ASC-38C1600 Internal RAM (32KB).
15693 for (; word < ADV_38C1600_MEMSIZE; word += 2) {
15694 AdvWriteWordAutoIncLram(iop_base, 0);
15698 * Verify the microcode checksum.
15701 AdvWriteWordRegister(iop_base, IOPW_RAM_ADDR, 0);
15703 for (word = 0; word < adv_asc38C1600_expanded_size; word += 2) {
15704 sum += AdvReadWordAutoIncLram(iop_base);
15707 if (sum != _adv_asc38C1600_chksum) {
15708 asc_dvc->err_code |= ASC_IERR_MCODE_CHKSUM;
15713 * Restore the RISC memory BIOS region.
15715 for (i = 0; i < ASC_MC_BIOSLEN / 2; i++) {
15716 AdvWriteWordLram(iop_base, ASC_MC_BIOSMEM + (2 * i),
15721 * Calculate and write the microcode code checksum to the microcode
15722 * code checksum location ASC_MC_CODE_CHK_SUM (0x2C).
15724 AdvReadWordLram(iop_base, ASC_MC_CODE_BEGIN_ADDR, begin_addr);
15725 AdvReadWordLram(iop_base, ASC_MC_CODE_END_ADDR, end_addr);
15727 AdvWriteWordRegister(iop_base, IOPW_RAM_ADDR, begin_addr);
15728 for (word = begin_addr; word < end_addr; word += 2) {
15729 code_sum += AdvReadWordAutoIncLram(iop_base);
15731 AdvWriteWordLram(iop_base, ASC_MC_CODE_CHK_SUM, code_sum);
15734 * Read microcode version and date.
15736 AdvReadWordLram(iop_base, ASC_MC_VERSION_DATE,
15737 asc_dvc->cfg->mcode_date);
15738 AdvReadWordLram(iop_base, ASC_MC_VERSION_NUM,
15739 asc_dvc->cfg->mcode_version);
15742 * Set the chip type to indicate the ASC38C1600.
15744 AdvWriteWordLram(iop_base, ASC_MC_CHIP_TYPE, ADV_CHIP_ASC38C1600);
15747 * Write 1 to bit 14 'DIS_TERM_DRV' in the SCSI_CFG1 register.
15748 * When DIS_TERM_DRV set to 1, C_DET[3:0] will reflect current
15749 * cable detection and then we are able to read C_DET[3:0].
15751 * Note: We will reset DIS_TERM_DRV to 0 in the 'Set SCSI_CFG1
15752 * Microcode Default Value' section below.
15754 scsi_cfg1 = AdvReadWordRegister(iop_base, IOPW_SCSI_CFG1);
15755 AdvWriteWordRegister(iop_base, IOPW_SCSI_CFG1,
15756 scsi_cfg1 | DIS_TERM_DRV);
15759 * If the PCI Configuration Command Register "Parity Error Response
15760 * Control" Bit was clear (0), then set the microcode variable
15761 * 'control_flag' CONTROL_FLAG_IGNORE_PERR flag to tell the microcode
15762 * to ignore DMA parity errors.
15764 if (asc_dvc->cfg->control_flag & CONTROL_FLAG_IGNORE_PERR) {
15765 AdvReadWordLram(iop_base, ASC_MC_CONTROL_FLAG, word);
15766 word |= CONTROL_FLAG_IGNORE_PERR;
15767 AdvWriteWordLram(iop_base, ASC_MC_CONTROL_FLAG, word);
15771 * If the BIOS control flag AIPP (Asynchronous Information
15772 * Phase Protection) disable bit is not set, then set the firmware
15773 * 'control_flag' CONTROL_FLAG_ENABLE_AIPP bit to enable
15774 * AIPP checking and encoding.
15776 if ((asc_dvc->bios_ctrl & BIOS_CTRL_AIPP_DIS) == 0) {
15777 AdvReadWordLram(iop_base, ASC_MC_CONTROL_FLAG, word);
15778 word |= CONTROL_FLAG_ENABLE_AIPP;
15779 AdvWriteWordLram(iop_base, ASC_MC_CONTROL_FLAG, word);
15783 * For ASC-38C1600 use DMA_CFG0 default values: FIFO_THRESH_80B [6:4],
15784 * and START_CTL_TH [3:2].
15786 AdvWriteByteRegister(iop_base, IOPB_DMA_CFG0,
15787 FIFO_THRESH_80B | START_CTL_TH | READ_CMD_MRM);
15790 * Microcode operating variables for WDTR, SDTR, and command tag
15791 * queuing will be set in AdvInquiryHandling() based on what a
15792 * device reports it is capable of in Inquiry byte 7.
15794 * If SCSI Bus Resets have been disabled, then directly set
15795 * SDTR and WDTR from the EEPROM configuration. This will allow
15796 * the BIOS and warm boot to work without a SCSI bus hang on
15797 * the Inquiry caused by host and target mismatched DTR values.
15798 * Without the SCSI Bus Reset, before an Inquiry a device can't
15799 * be assumed to be in Asynchronous, Narrow mode.
15801 if ((asc_dvc->bios_ctrl & BIOS_CTRL_RESET_SCSI_BUS) == 0) {
15802 AdvWriteWordLram(iop_base, ASC_MC_WDTR_ABLE,
15803 asc_dvc->wdtr_able);
15804 AdvWriteWordLram(iop_base, ASC_MC_SDTR_ABLE,
15805 asc_dvc->sdtr_able);
15809 * Set microcode operating variables for DISC and SDTR_SPEED1,
15810 * SDTR_SPEED2, SDTR_SPEED3, and SDTR_SPEED4 based on the EEPROM
15811 * configuration values.
15813 * The SDTR per TID bitmask overrides the SDTR_SPEED1, SDTR_SPEED2,
15814 * SDTR_SPEED3, and SDTR_SPEED4 values so it is safe to set them
15815 * without determining here whether the device supports SDTR.
15817 AdvWriteWordLram(iop_base, ASC_MC_DISC_ENABLE,
15818 asc_dvc->cfg->disc_enable);
15819 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED1, asc_dvc->sdtr_speed1);
15820 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED2, asc_dvc->sdtr_speed2);
15821 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED3, asc_dvc->sdtr_speed3);
15822 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED4, asc_dvc->sdtr_speed4);
15825 * Set SCSI_CFG0 Microcode Default Value.
15827 * The microcode will set the SCSI_CFG0 register using this value
15828 * after it is started below.
15830 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SCSI_CFG0,
15831 PARITY_EN | QUEUE_128 | SEL_TMO_LONG | OUR_ID_EN |
15832 asc_dvc->chip_scsi_id);
15835 * Calculate SCSI_CFG1 Microcode Default Value.
15837 * The microcode will set the SCSI_CFG1 register using this value
15838 * after it is started below.
15840 * Each ASC-38C1600 function has only two cable detect bits.
15841 * The bus mode override bits are in IOPB_SOFT_OVER_WR.
15843 scsi_cfg1 = AdvReadWordRegister(iop_base, IOPW_SCSI_CFG1);
15846 * If the cable is reversed all of the SCSI_CTRL register signals
15847 * will be set. Check for and return an error if this condition is
15850 if ((AdvReadWordRegister(iop_base, IOPW_SCSI_CTRL) & 0x3F07) == 0x3F07) {
15851 asc_dvc->err_code |= ASC_IERR_REVERSED_CABLE;
15856 * Each ASC-38C1600 function has two connectors. Only an HVD device
15857 * can not be connected to either connector. An LVD device or SE device
15858 * may be connected to either connecor. If an SE device is connected,
15859 * then at most Ultra speed (20 Mhz) can be used on both connectors.
15861 * If an HVD device is attached, return an error.
15863 if (scsi_cfg1 & HVD) {
15864 asc_dvc->err_code |= ASC_IERR_HVD_DEVICE;
15869 * Each function in the ASC-38C1600 uses only the SE cable detect and
15870 * termination because there are two connectors for each function. Each
15871 * function may use either LVD or SE mode. Corresponding the SE automatic
15872 * termination control EEPROM bits are used for each function. Each
15873 * function has its own EEPROM. If SE automatic control is enabled for
15874 * the function, then set the termination value based on a table listed
15877 * If manual termination is specified in the EEPROM for the function,
15878 * then 'termination' was set-up in AscInitFrom38C1600EEPROM() and is
15879 * ready to be 'ored' into SCSI_CFG1.
15881 if ((asc_dvc->cfg->termination & TERM_SE) == 0) {
15882 /* SE automatic termination control is enabled. */
15883 switch (scsi_cfg1 & C_DET_SE) {
15884 /* TERM_SE_HI: on, TERM_SE_LO: on */
15888 asc_dvc->cfg->termination |= TERM_SE;
15892 if (ASC_PCI_ID2FUNC(asc_dvc->cfg->pci_slot_info) == 0) {
15893 /* Function 0 - TERM_SE_HI: off, TERM_SE_LO: off */
15895 /* Function 1 - TERM_SE_HI: on, TERM_SE_LO: off */
15896 asc_dvc->cfg->termination |= TERM_SE_HI;
15903 * Clear any set TERM_SE bits.
15905 scsi_cfg1 &= ~TERM_SE;
15908 * Invert the TERM_SE bits and then set 'scsi_cfg1'.
15910 scsi_cfg1 |= (~asc_dvc->cfg->termination & TERM_SE);
15913 * Clear Big Endian and Terminator Polarity bits and set possibly
15914 * modified termination control bits in the Microcode SCSI_CFG1
15917 * Big Endian bit is not used even on big endian machines.
15919 scsi_cfg1 &= (~BIG_ENDIAN & ~DIS_TERM_DRV & ~TERM_POL);
15922 * Set SCSI_CFG1 Microcode Default Value
15924 * Set possibly modified termination control bits in the Microcode
15925 * SCSI_CFG1 Register Value.
15927 * The microcode will set the SCSI_CFG1 register using this value
15928 * after it is started below.
15930 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SCSI_CFG1, scsi_cfg1);
15933 * Set MEM_CFG Microcode Default Value
15935 * The microcode will set the MEM_CFG register using this value
15936 * after it is started below.
15938 * MEM_CFG may be accessed as a word or byte, but only bits 0-7
15941 * ASC-38C1600 has 32KB internal memory.
15943 * XXX - Since ASC38C1600 Rev.3 has a Local RAM failure issue, we come
15944 * out a special 16K Adv Library and Microcode version. After the issue
15945 * resolved, we should turn back to the 32K support. Both a_condor.h and
15946 * mcode.sas files also need to be updated.
15948 * AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_MEM_CFG,
15949 * BIOS_EN | RAM_SZ_32KB);
15951 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_MEM_CFG,
15952 BIOS_EN | RAM_SZ_16KB);
15955 * Set SEL_MASK Microcode Default Value
15957 * The microcode will set the SEL_MASK register using this value
15958 * after it is started below.
15960 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SEL_MASK,
15961 ADV_TID_TO_TIDMASK(asc_dvc->chip_scsi_id));
15964 * Build the carrier freelist.
15966 * Driver must have already allocated memory and set 'carrier_buf'.
15969 ASC_ASSERT(asc_dvc->carrier_buf != NULL);
15971 carrp = (ADV_CARR_T *) ADV_16BALIGN(asc_dvc->carrier_buf);
15972 asc_dvc->carr_freelist = NULL;
15973 if (carrp == (ADV_CARR_T *) asc_dvc->carrier_buf) {
15974 buf_size = ADV_CARRIER_BUFSIZE;
15976 buf_size = ADV_CARRIER_BUFSIZE - sizeof(ADV_CARR_T);
15981 * Get physical address for the carrier 'carrp'.
15983 contig_len = sizeof(ADV_CARR_T);
15985 cpu_to_le32(DvcGetPhyAddr
15986 (asc_dvc, NULL, (uchar *)carrp,
15987 (ADV_SDCNT *)&contig_len,
15988 ADV_IS_CARRIER_FLAG));
15990 buf_size -= sizeof(ADV_CARR_T);
15993 * If the current carrier is not physically contiguous, then
15994 * maybe there was a page crossing. Try the next carrier aligned
15997 if (contig_len < sizeof(ADV_CARR_T)) {
16002 carrp->carr_pa = carr_paddr;
16003 carrp->carr_va = cpu_to_le32(ADV_VADDR_TO_U32(carrp));
16006 * Insert the carrier at the beginning of the freelist.
16009 cpu_to_le32(ADV_VADDR_TO_U32(asc_dvc->carr_freelist));
16010 asc_dvc->carr_freelist = carrp;
16014 while (buf_size > 0);
16017 * Set-up the Host->RISC Initiator Command Queue (ICQ).
16019 if ((asc_dvc->icq_sp = asc_dvc->carr_freelist) == NULL) {
16020 asc_dvc->err_code |= ASC_IERR_NO_CARRIER;
16023 asc_dvc->carr_freelist = (ADV_CARR_T *)
16024 ADV_U32_TO_VADDR(le32_to_cpu(asc_dvc->icq_sp->next_vpa));
16027 * The first command issued will be placed in the stopper carrier.
16029 asc_dvc->icq_sp->next_vpa = cpu_to_le32(ASC_CQ_STOPPER);
16032 * Set RISC ICQ physical address start value. Initialize the
16033 * COMMA register to the same value otherwise the RISC will
16034 * prematurely detect a command is available.
16036 AdvWriteDWordLramNoSwap(iop_base, ASC_MC_ICQ, asc_dvc->icq_sp->carr_pa);
16037 AdvWriteDWordRegister(iop_base, IOPDW_COMMA,
16038 le32_to_cpu(asc_dvc->icq_sp->carr_pa));
16041 * Set-up the RISC->Host Initiator Response Queue (IRQ).
16043 if ((asc_dvc->irq_sp = asc_dvc->carr_freelist) == NULL) {
16044 asc_dvc->err_code |= ASC_IERR_NO_CARRIER;
16047 asc_dvc->carr_freelist = (ADV_CARR_T *)
16048 ADV_U32_TO_VADDR(le32_to_cpu(asc_dvc->irq_sp->next_vpa));
16051 * The first command completed by the RISC will be placed in
16054 * Note: Set 'next_vpa' to ASC_CQ_STOPPER. When the request is
16055 * completed the RISC will set the ASC_RQ_STOPPER bit.
16057 asc_dvc->irq_sp->next_vpa = cpu_to_le32(ASC_CQ_STOPPER);
16060 * Set RISC IRQ physical address start value.
16062 AdvWriteDWordLramNoSwap(iop_base, ASC_MC_IRQ, asc_dvc->irq_sp->carr_pa);
16063 asc_dvc->carr_pending_cnt = 0;
16065 AdvWriteByteRegister(iop_base, IOPB_INTR_ENABLES,
16066 (ADV_INTR_ENABLE_HOST_INTR |
16067 ADV_INTR_ENABLE_GLOBAL_INTR));
16068 AdvReadWordLram(iop_base, ASC_MC_CODE_BEGIN_ADDR, word);
16069 AdvWriteWordRegister(iop_base, IOPW_PC, word);
16071 /* finally, finally, gentlemen, start your engine */
16072 AdvWriteWordRegister(iop_base, IOPW_RISC_CSR, ADV_RISC_CSR_RUN);
16075 * Reset the SCSI Bus if the EEPROM indicates that SCSI Bus
16076 * Resets should be performed. The RISC has to be running
16077 * to issue a SCSI Bus Reset.
16079 if (asc_dvc->bios_ctrl & BIOS_CTRL_RESET_SCSI_BUS) {
16081 * If the BIOS Signature is present in memory, restore the
16082 * per TID microcode operating variables.
16084 if (bios_mem[(ASC_MC_BIOS_SIGNATURE - ASC_MC_BIOSMEM) / 2] ==
16087 * Restore per TID negotiated values.
16089 AdvWriteWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able);
16090 AdvWriteWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
16091 AdvWriteWordLram(iop_base, ASC_MC_PPR_ABLE, ppr_able);
16092 AdvWriteWordLram(iop_base, ASC_MC_TAGQNG_ABLE,
16094 for (tid = 0; tid <= ASC_MAX_TID; tid++) {
16095 AdvWriteByteLram(iop_base,
16096 ASC_MC_NUMBER_OF_MAX_CMD + tid,
16100 if (AdvResetSB(asc_dvc) != ADV_TRUE) {
16101 warn_code = ASC_WARN_BUSRESET_ERROR;
16110 * Read the board's EEPROM configuration. Set fields in ADV_DVC_VAR and
16111 * ADV_DVC_CFG based on the EEPROM settings. The chip is stopped while
16112 * all of this is done.
16114 * On failure set the ADV_DVC_VAR field 'err_code' and return ADV_ERROR.
16116 * For a non-fatal error return a warning code. If there are no warnings
16117 * then 0 is returned.
16119 * Note: Chip is stopped on entry.
16121 static int __init AdvInitFrom3550EEP(ADV_DVC_VAR *asc_dvc)
16123 AdvPortAddr iop_base;
16125 ADVEEP_3550_CONFIG eep_config;
16128 iop_base = asc_dvc->iop_base;
16133 * Read the board's EEPROM configuration.
16135 * Set default values if a bad checksum is found.
16137 if (AdvGet3550EEPConfig(iop_base, &eep_config) != eep_config.check_sum) {
16138 warn_code |= ASC_WARN_EEPROM_CHKSUM;
16141 * Set EEPROM default values.
16143 for (i = 0; i < sizeof(ADVEEP_3550_CONFIG); i++) {
16144 *((uchar *)&eep_config + i) =
16145 *((uchar *)&Default_3550_EEPROM_Config + i);
16149 * Assume the 6 byte board serial number that was read
16150 * from EEPROM is correct even if the EEPROM checksum
16153 eep_config.serial_number_word3 =
16154 AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 1);
16156 eep_config.serial_number_word2 =
16157 AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 2);
16159 eep_config.serial_number_word1 =
16160 AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 3);
16162 AdvSet3550EEPConfig(iop_base, &eep_config);
16165 * Set ASC_DVC_VAR and ASC_DVC_CFG variables from the
16166 * EEPROM configuration that was read.
16168 * This is the mapping of EEPROM fields to Adv Library fields.
16170 asc_dvc->wdtr_able = eep_config.wdtr_able;
16171 asc_dvc->sdtr_able = eep_config.sdtr_able;
16172 asc_dvc->ultra_able = eep_config.ultra_able;
16173 asc_dvc->tagqng_able = eep_config.tagqng_able;
16174 asc_dvc->cfg->disc_enable = eep_config.disc_enable;
16175 asc_dvc->max_host_qng = eep_config.max_host_qng;
16176 asc_dvc->max_dvc_qng = eep_config.max_dvc_qng;
16177 asc_dvc->chip_scsi_id = (eep_config.adapter_scsi_id & ADV_MAX_TID);
16178 asc_dvc->start_motor = eep_config.start_motor;
16179 asc_dvc->scsi_reset_wait = eep_config.scsi_reset_delay;
16180 asc_dvc->bios_ctrl = eep_config.bios_ctrl;
16181 asc_dvc->no_scam = eep_config.scam_tolerant;
16182 asc_dvc->cfg->serial1 = eep_config.serial_number_word1;
16183 asc_dvc->cfg->serial2 = eep_config.serial_number_word2;
16184 asc_dvc->cfg->serial3 = eep_config.serial_number_word3;
16187 * Set the host maximum queuing (max. 253, min. 16) and the per device
16188 * maximum queuing (max. 63, min. 4).
16190 if (eep_config.max_host_qng > ASC_DEF_MAX_HOST_QNG) {
16191 eep_config.max_host_qng = ASC_DEF_MAX_HOST_QNG;
16192 } else if (eep_config.max_host_qng < ASC_DEF_MIN_HOST_QNG) {
16193 /* If the value is zero, assume it is uninitialized. */
16194 if (eep_config.max_host_qng == 0) {
16195 eep_config.max_host_qng = ASC_DEF_MAX_HOST_QNG;
16197 eep_config.max_host_qng = ASC_DEF_MIN_HOST_QNG;
16201 if (eep_config.max_dvc_qng > ASC_DEF_MAX_DVC_QNG) {
16202 eep_config.max_dvc_qng = ASC_DEF_MAX_DVC_QNG;
16203 } else if (eep_config.max_dvc_qng < ASC_DEF_MIN_DVC_QNG) {
16204 /* If the value is zero, assume it is uninitialized. */
16205 if (eep_config.max_dvc_qng == 0) {
16206 eep_config.max_dvc_qng = ASC_DEF_MAX_DVC_QNG;
16208 eep_config.max_dvc_qng = ASC_DEF_MIN_DVC_QNG;
16213 * If 'max_dvc_qng' is greater than 'max_host_qng', then
16214 * set 'max_dvc_qng' to 'max_host_qng'.
16216 if (eep_config.max_dvc_qng > eep_config.max_host_qng) {
16217 eep_config.max_dvc_qng = eep_config.max_host_qng;
16221 * Set ADV_DVC_VAR 'max_host_qng' and ADV_DVC_VAR 'max_dvc_qng'
16222 * values based on possibly adjusted EEPROM values.
16224 asc_dvc->max_host_qng = eep_config.max_host_qng;
16225 asc_dvc->max_dvc_qng = eep_config.max_dvc_qng;
16228 * If the EEPROM 'termination' field is set to automatic (0), then set
16229 * the ADV_DVC_CFG 'termination' field to automatic also.
16231 * If the termination is specified with a non-zero 'termination'
16232 * value check that a legal value is set and set the ADV_DVC_CFG
16233 * 'termination' field appropriately.
16235 if (eep_config.termination == 0) {
16236 asc_dvc->cfg->termination = 0; /* auto termination */
16238 /* Enable manual control with low off / high off. */
16239 if (eep_config.termination == 1) {
16240 asc_dvc->cfg->termination = TERM_CTL_SEL;
16242 /* Enable manual control with low off / high on. */
16243 } else if (eep_config.termination == 2) {
16244 asc_dvc->cfg->termination = TERM_CTL_SEL | TERM_CTL_H;
16246 /* Enable manual control with low on / high on. */
16247 } else if (eep_config.termination == 3) {
16248 asc_dvc->cfg->termination =
16249 TERM_CTL_SEL | TERM_CTL_H | TERM_CTL_L;
16252 * The EEPROM 'termination' field contains a bad value. Use
16253 * automatic termination instead.
16255 asc_dvc->cfg->termination = 0;
16256 warn_code |= ASC_WARN_EEPROM_TERMINATION;
16264 * Read the board's EEPROM configuration. Set fields in ADV_DVC_VAR and
16265 * ADV_DVC_CFG based on the EEPROM settings. The chip is stopped while
16266 * all of this is done.
16268 * On failure set the ADV_DVC_VAR field 'err_code' and return ADV_ERROR.
16270 * For a non-fatal error return a warning code. If there are no warnings
16271 * then 0 is returned.
16273 * Note: Chip is stopped on entry.
16275 static int __init AdvInitFrom38C0800EEP(ADV_DVC_VAR *asc_dvc)
16277 AdvPortAddr iop_base;
16279 ADVEEP_38C0800_CONFIG eep_config;
16281 uchar tid, termination;
16282 ushort sdtr_speed = 0;
16284 iop_base = asc_dvc->iop_base;
16289 * Read the board's EEPROM configuration.
16291 * Set default values if a bad checksum is found.
16293 if (AdvGet38C0800EEPConfig(iop_base, &eep_config) !=
16294 eep_config.check_sum) {
16295 warn_code |= ASC_WARN_EEPROM_CHKSUM;
16298 * Set EEPROM default values.
16300 for (i = 0; i < sizeof(ADVEEP_38C0800_CONFIG); i++) {
16301 *((uchar *)&eep_config + i) =
16302 *((uchar *)&Default_38C0800_EEPROM_Config + i);
16306 * Assume the 6 byte board serial number that was read
16307 * from EEPROM is correct even if the EEPROM checksum
16310 eep_config.serial_number_word3 =
16311 AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 1);
16313 eep_config.serial_number_word2 =
16314 AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 2);
16316 eep_config.serial_number_word1 =
16317 AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 3);
16319 AdvSet38C0800EEPConfig(iop_base, &eep_config);
16322 * Set ADV_DVC_VAR and ADV_DVC_CFG variables from the
16323 * EEPROM configuration that was read.
16325 * This is the mapping of EEPROM fields to Adv Library fields.
16327 asc_dvc->wdtr_able = eep_config.wdtr_able;
16328 asc_dvc->sdtr_speed1 = eep_config.sdtr_speed1;
16329 asc_dvc->sdtr_speed2 = eep_config.sdtr_speed2;
16330 asc_dvc->sdtr_speed3 = eep_config.sdtr_speed3;
16331 asc_dvc->sdtr_speed4 = eep_config.sdtr_speed4;
16332 asc_dvc->tagqng_able = eep_config.tagqng_able;
16333 asc_dvc->cfg->disc_enable = eep_config.disc_enable;
16334 asc_dvc->max_host_qng = eep_config.max_host_qng;
16335 asc_dvc->max_dvc_qng = eep_config.max_dvc_qng;
16336 asc_dvc->chip_scsi_id = (eep_config.adapter_scsi_id & ADV_MAX_TID);
16337 asc_dvc->start_motor = eep_config.start_motor;
16338 asc_dvc->scsi_reset_wait = eep_config.scsi_reset_delay;
16339 asc_dvc->bios_ctrl = eep_config.bios_ctrl;
16340 asc_dvc->no_scam = eep_config.scam_tolerant;
16341 asc_dvc->cfg->serial1 = eep_config.serial_number_word1;
16342 asc_dvc->cfg->serial2 = eep_config.serial_number_word2;
16343 asc_dvc->cfg->serial3 = eep_config.serial_number_word3;
16346 * For every Target ID if any of its 'sdtr_speed[1234]' bits
16347 * are set, then set an 'sdtr_able' bit for it.
16349 asc_dvc->sdtr_able = 0;
16350 for (tid = 0; tid <= ADV_MAX_TID; tid++) {
16352 sdtr_speed = asc_dvc->sdtr_speed1;
16353 } else if (tid == 4) {
16354 sdtr_speed = asc_dvc->sdtr_speed2;
16355 } else if (tid == 8) {
16356 sdtr_speed = asc_dvc->sdtr_speed3;
16357 } else if (tid == 12) {
16358 sdtr_speed = asc_dvc->sdtr_speed4;
16360 if (sdtr_speed & ADV_MAX_TID) {
16361 asc_dvc->sdtr_able |= (1 << tid);
16367 * Set the host maximum queuing (max. 253, min. 16) and the per device
16368 * maximum queuing (max. 63, min. 4).
16370 if (eep_config.max_host_qng > ASC_DEF_MAX_HOST_QNG) {
16371 eep_config.max_host_qng = ASC_DEF_MAX_HOST_QNG;
16372 } else if (eep_config.max_host_qng < ASC_DEF_MIN_HOST_QNG) {
16373 /* If the value is zero, assume it is uninitialized. */
16374 if (eep_config.max_host_qng == 0) {
16375 eep_config.max_host_qng = ASC_DEF_MAX_HOST_QNG;
16377 eep_config.max_host_qng = ASC_DEF_MIN_HOST_QNG;
16381 if (eep_config.max_dvc_qng > ASC_DEF_MAX_DVC_QNG) {
16382 eep_config.max_dvc_qng = ASC_DEF_MAX_DVC_QNG;
16383 } else if (eep_config.max_dvc_qng < ASC_DEF_MIN_DVC_QNG) {
16384 /* If the value is zero, assume it is uninitialized. */
16385 if (eep_config.max_dvc_qng == 0) {
16386 eep_config.max_dvc_qng = ASC_DEF_MAX_DVC_QNG;
16388 eep_config.max_dvc_qng = ASC_DEF_MIN_DVC_QNG;
16393 * If 'max_dvc_qng' is greater than 'max_host_qng', then
16394 * set 'max_dvc_qng' to 'max_host_qng'.
16396 if (eep_config.max_dvc_qng > eep_config.max_host_qng) {
16397 eep_config.max_dvc_qng = eep_config.max_host_qng;
16401 * Set ADV_DVC_VAR 'max_host_qng' and ADV_DVC_VAR 'max_dvc_qng'
16402 * values based on possibly adjusted EEPROM values.
16404 asc_dvc->max_host_qng = eep_config.max_host_qng;
16405 asc_dvc->max_dvc_qng = eep_config.max_dvc_qng;
16408 * If the EEPROM 'termination' field is set to automatic (0), then set
16409 * the ADV_DVC_CFG 'termination' field to automatic also.
16411 * If the termination is specified with a non-zero 'termination'
16412 * value check that a legal value is set and set the ADV_DVC_CFG
16413 * 'termination' field appropriately.
16415 if (eep_config.termination_se == 0) {
16416 termination = 0; /* auto termination for SE */
16418 /* Enable manual control with low off / high off. */
16419 if (eep_config.termination_se == 1) {
16422 /* Enable manual control with low off / high on. */
16423 } else if (eep_config.termination_se == 2) {
16424 termination = TERM_SE_HI;
16426 /* Enable manual control with low on / high on. */
16427 } else if (eep_config.termination_se == 3) {
16428 termination = TERM_SE;
16431 * The EEPROM 'termination_se' field contains a bad value.
16432 * Use automatic termination instead.
16435 warn_code |= ASC_WARN_EEPROM_TERMINATION;
16439 if (eep_config.termination_lvd == 0) {
16440 asc_dvc->cfg->termination = termination; /* auto termination for LVD */
16442 /* Enable manual control with low off / high off. */
16443 if (eep_config.termination_lvd == 1) {
16444 asc_dvc->cfg->termination = termination;
16446 /* Enable manual control with low off / high on. */
16447 } else if (eep_config.termination_lvd == 2) {
16448 asc_dvc->cfg->termination = termination | TERM_LVD_HI;
16450 /* Enable manual control with low on / high on. */
16451 } else if (eep_config.termination_lvd == 3) {
16452 asc_dvc->cfg->termination = termination | TERM_LVD;
16455 * The EEPROM 'termination_lvd' field contains a bad value.
16456 * Use automatic termination instead.
16458 asc_dvc->cfg->termination = termination;
16459 warn_code |= ASC_WARN_EEPROM_TERMINATION;
16467 * Read the board's EEPROM configuration. Set fields in ASC_DVC_VAR and
16468 * ASC_DVC_CFG based on the EEPROM settings. The chip is stopped while
16469 * all of this is done.
16471 * On failure set the ASC_DVC_VAR field 'err_code' and return ADV_ERROR.
16473 * For a non-fatal error return a warning code. If there are no warnings
16474 * then 0 is returned.
16476 * Note: Chip is stopped on entry.
16478 static int __init AdvInitFrom38C1600EEP(ADV_DVC_VAR *asc_dvc)
16480 AdvPortAddr iop_base;
16482 ADVEEP_38C1600_CONFIG eep_config;
16484 uchar tid, termination;
16485 ushort sdtr_speed = 0;
16487 iop_base = asc_dvc->iop_base;
16492 * Read the board's EEPROM configuration.
16494 * Set default values if a bad checksum is found.
16496 if (AdvGet38C1600EEPConfig(iop_base, &eep_config) !=
16497 eep_config.check_sum) {
16498 warn_code |= ASC_WARN_EEPROM_CHKSUM;
16501 * Set EEPROM default values.
16503 for (i = 0; i < sizeof(ADVEEP_38C1600_CONFIG); i++) {
16505 && ASC_PCI_ID2FUNC(asc_dvc->cfg->pci_slot_info) !=
16508 * Set Function 1 EEPROM Word 0 MSB
16510 * Clear the BIOS_ENABLE (bit 14) and INTAB (bit 11)
16513 * Disable Bit 14 (BIOS_ENABLE) to fix SPARC Ultra 60 and
16514 * old Mac system booting problem. The Expansion ROM must
16515 * be disabled in Function 1 for these systems.
16518 *((uchar *)&eep_config + i) =
16520 ((uchar *)&Default_38C1600_EEPROM_Config
16524 (((ADV_EEPROM_BIOS_ENABLE |
16525 ADV_EEPROM_INTAB) >> 8) & 0xFF)));
16528 * Set the INTAB (bit 11) if the GPIO 0 input indicates
16529 * the Function 1 interrupt line is wired to INTA.
16531 * Set/Clear Bit 11 (INTAB) from the GPIO bit 0 input:
16532 * 1 - Function 1 interrupt line wired to INT A.
16533 * 0 - Function 1 interrupt line wired to INT B.
16535 * Note: Adapter boards always have Function 0 wired to INTA.
16536 * Put all 5 GPIO bits in input mode and then read
16537 * their input values.
16539 AdvWriteByteRegister(iop_base, IOPB_GPIO_CNTL,
16541 if (AdvReadByteRegister
16542 (iop_base, IOPB_GPIO_DATA) & 0x01) {
16543 /* Function 1 interrupt wired to INTA; Set EEPROM bit. */
16544 *((uchar *)&eep_config + i) |=
16545 ((ADV_EEPROM_INTAB >> 8) & 0xFF);
16548 *((uchar *)&eep_config + i) =
16549 *((uchar *)&Default_38C1600_EEPROM_Config
16555 * Assume the 6 byte board serial number that was read
16556 * from EEPROM is correct even if the EEPROM checksum
16559 eep_config.serial_number_word3 =
16560 AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 1);
16562 eep_config.serial_number_word2 =
16563 AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 2);
16565 eep_config.serial_number_word1 =
16566 AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 3);
16568 AdvSet38C1600EEPConfig(iop_base, &eep_config);
16572 * Set ASC_DVC_VAR and ASC_DVC_CFG variables from the
16573 * EEPROM configuration that was read.
16575 * This is the mapping of EEPROM fields to Adv Library fields.
16577 asc_dvc->wdtr_able = eep_config.wdtr_able;
16578 asc_dvc->sdtr_speed1 = eep_config.sdtr_speed1;
16579 asc_dvc->sdtr_speed2 = eep_config.sdtr_speed2;
16580 asc_dvc->sdtr_speed3 = eep_config.sdtr_speed3;
16581 asc_dvc->sdtr_speed4 = eep_config.sdtr_speed4;
16582 asc_dvc->ppr_able = 0;
16583 asc_dvc->tagqng_able = eep_config.tagqng_able;
16584 asc_dvc->cfg->disc_enable = eep_config.disc_enable;
16585 asc_dvc->max_host_qng = eep_config.max_host_qng;
16586 asc_dvc->max_dvc_qng = eep_config.max_dvc_qng;
16587 asc_dvc->chip_scsi_id = (eep_config.adapter_scsi_id & ASC_MAX_TID);
16588 asc_dvc->start_motor = eep_config.start_motor;
16589 asc_dvc->scsi_reset_wait = eep_config.scsi_reset_delay;
16590 asc_dvc->bios_ctrl = eep_config.bios_ctrl;
16591 asc_dvc->no_scam = eep_config.scam_tolerant;
16594 * For every Target ID if any of its 'sdtr_speed[1234]' bits
16595 * are set, then set an 'sdtr_able' bit for it.
16597 asc_dvc->sdtr_able = 0;
16598 for (tid = 0; tid <= ASC_MAX_TID; tid++) {
16600 sdtr_speed = asc_dvc->sdtr_speed1;
16601 } else if (tid == 4) {
16602 sdtr_speed = asc_dvc->sdtr_speed2;
16603 } else if (tid == 8) {
16604 sdtr_speed = asc_dvc->sdtr_speed3;
16605 } else if (tid == 12) {
16606 sdtr_speed = asc_dvc->sdtr_speed4;
16608 if (sdtr_speed & ASC_MAX_TID) {
16609 asc_dvc->sdtr_able |= (1 << tid);
16615 * Set the host maximum queuing (max. 253, min. 16) and the per device
16616 * maximum queuing (max. 63, min. 4).
16618 if (eep_config.max_host_qng > ASC_DEF_MAX_HOST_QNG) {
16619 eep_config.max_host_qng = ASC_DEF_MAX_HOST_QNG;
16620 } else if (eep_config.max_host_qng < ASC_DEF_MIN_HOST_QNG) {
16621 /* If the value is zero, assume it is uninitialized. */
16622 if (eep_config.max_host_qng == 0) {
16623 eep_config.max_host_qng = ASC_DEF_MAX_HOST_QNG;
16625 eep_config.max_host_qng = ASC_DEF_MIN_HOST_QNG;
16629 if (eep_config.max_dvc_qng > ASC_DEF_MAX_DVC_QNG) {
16630 eep_config.max_dvc_qng = ASC_DEF_MAX_DVC_QNG;
16631 } else if (eep_config.max_dvc_qng < ASC_DEF_MIN_DVC_QNG) {
16632 /* If the value is zero, assume it is uninitialized. */
16633 if (eep_config.max_dvc_qng == 0) {
16634 eep_config.max_dvc_qng = ASC_DEF_MAX_DVC_QNG;
16636 eep_config.max_dvc_qng = ASC_DEF_MIN_DVC_QNG;
16641 * If 'max_dvc_qng' is greater than 'max_host_qng', then
16642 * set 'max_dvc_qng' to 'max_host_qng'.
16644 if (eep_config.max_dvc_qng > eep_config.max_host_qng) {
16645 eep_config.max_dvc_qng = eep_config.max_host_qng;
16649 * Set ASC_DVC_VAR 'max_host_qng' and ASC_DVC_VAR 'max_dvc_qng'
16650 * values based on possibly adjusted EEPROM values.
16652 asc_dvc->max_host_qng = eep_config.max_host_qng;
16653 asc_dvc->max_dvc_qng = eep_config.max_dvc_qng;
16656 * If the EEPROM 'termination' field is set to automatic (0), then set
16657 * the ASC_DVC_CFG 'termination' field to automatic also.
16659 * If the termination is specified with a non-zero 'termination'
16660 * value check that a legal value is set and set the ASC_DVC_CFG
16661 * 'termination' field appropriately.
16663 if (eep_config.termination_se == 0) {
16664 termination = 0; /* auto termination for SE */
16666 /* Enable manual control with low off / high off. */
16667 if (eep_config.termination_se == 1) {
16670 /* Enable manual control with low off / high on. */
16671 } else if (eep_config.termination_se == 2) {
16672 termination = TERM_SE_HI;
16674 /* Enable manual control with low on / high on. */
16675 } else if (eep_config.termination_se == 3) {
16676 termination = TERM_SE;
16679 * The EEPROM 'termination_se' field contains a bad value.
16680 * Use automatic termination instead.
16683 warn_code |= ASC_WARN_EEPROM_TERMINATION;
16687 if (eep_config.termination_lvd == 0) {
16688 asc_dvc->cfg->termination = termination; /* auto termination for LVD */
16690 /* Enable manual control with low off / high off. */
16691 if (eep_config.termination_lvd == 1) {
16692 asc_dvc->cfg->termination = termination;
16694 /* Enable manual control with low off / high on. */
16695 } else if (eep_config.termination_lvd == 2) {
16696 asc_dvc->cfg->termination = termination | TERM_LVD_HI;
16698 /* Enable manual control with low on / high on. */
16699 } else if (eep_config.termination_lvd == 3) {
16700 asc_dvc->cfg->termination = termination | TERM_LVD;
16703 * The EEPROM 'termination_lvd' field contains a bad value.
16704 * Use automatic termination instead.
16706 asc_dvc->cfg->termination = termination;
16707 warn_code |= ASC_WARN_EEPROM_TERMINATION;
16715 * Read EEPROM configuration into the specified buffer.
16717 * Return a checksum based on the EEPROM configuration read.
16719 static ushort __init
16720 AdvGet3550EEPConfig(AdvPortAddr iop_base, ADVEEP_3550_CONFIG *cfg_buf)
16722 ushort wval, chksum;
16725 ushort *charfields;
16727 charfields = (ushort *)&ADVEEP_3550_Config_Field_IsChar;
16728 wbuf = (ushort *)cfg_buf;
16731 for (eep_addr = ADV_EEP_DVC_CFG_BEGIN;
16732 eep_addr < ADV_EEP_DVC_CFG_END; eep_addr++, wbuf++) {
16733 wval = AdvReadEEPWord(iop_base, eep_addr);
16734 chksum += wval; /* Checksum is calculated from word values. */
16735 if (*charfields++) {
16736 *wbuf = le16_to_cpu(wval);
16741 /* Read checksum word. */
16742 *wbuf = AdvReadEEPWord(iop_base, eep_addr);
16746 /* Read rest of EEPROM not covered by the checksum. */
16747 for (eep_addr = ADV_EEP_DVC_CTL_BEGIN;
16748 eep_addr < ADV_EEP_MAX_WORD_ADDR; eep_addr++, wbuf++) {
16749 *wbuf = AdvReadEEPWord(iop_base, eep_addr);
16750 if (*charfields++) {
16751 *wbuf = le16_to_cpu(*wbuf);
16758 * Read EEPROM configuration into the specified buffer.
16760 * Return a checksum based on the EEPROM configuration read.
16762 static ushort __init
16763 AdvGet38C0800EEPConfig(AdvPortAddr iop_base, ADVEEP_38C0800_CONFIG *cfg_buf)
16765 ushort wval, chksum;
16768 ushort *charfields;
16770 charfields = (ushort *)&ADVEEP_38C0800_Config_Field_IsChar;
16771 wbuf = (ushort *)cfg_buf;
16774 for (eep_addr = ADV_EEP_DVC_CFG_BEGIN;
16775 eep_addr < ADV_EEP_DVC_CFG_END; eep_addr++, wbuf++) {
16776 wval = AdvReadEEPWord(iop_base, eep_addr);
16777 chksum += wval; /* Checksum is calculated from word values. */
16778 if (*charfields++) {
16779 *wbuf = le16_to_cpu(wval);
16784 /* Read checksum word. */
16785 *wbuf = AdvReadEEPWord(iop_base, eep_addr);
16789 /* Read rest of EEPROM not covered by the checksum. */
16790 for (eep_addr = ADV_EEP_DVC_CTL_BEGIN;
16791 eep_addr < ADV_EEP_MAX_WORD_ADDR; eep_addr++, wbuf++) {
16792 *wbuf = AdvReadEEPWord(iop_base, eep_addr);
16793 if (*charfields++) {
16794 *wbuf = le16_to_cpu(*wbuf);
16801 * Read EEPROM configuration into the specified buffer.
16803 * Return a checksum based on the EEPROM configuration read.
16805 static ushort __init
16806 AdvGet38C1600EEPConfig(AdvPortAddr iop_base, ADVEEP_38C1600_CONFIG *cfg_buf)
16808 ushort wval, chksum;
16811 ushort *charfields;
16813 charfields = (ushort *)&ADVEEP_38C1600_Config_Field_IsChar;
16814 wbuf = (ushort *)cfg_buf;
16817 for (eep_addr = ADV_EEP_DVC_CFG_BEGIN;
16818 eep_addr < ADV_EEP_DVC_CFG_END; eep_addr++, wbuf++) {
16819 wval = AdvReadEEPWord(iop_base, eep_addr);
16820 chksum += wval; /* Checksum is calculated from word values. */
16821 if (*charfields++) {
16822 *wbuf = le16_to_cpu(wval);
16827 /* Read checksum word. */
16828 *wbuf = AdvReadEEPWord(iop_base, eep_addr);
16832 /* Read rest of EEPROM not covered by the checksum. */
16833 for (eep_addr = ADV_EEP_DVC_CTL_BEGIN;
16834 eep_addr < ADV_EEP_MAX_WORD_ADDR; eep_addr++, wbuf++) {
16835 *wbuf = AdvReadEEPWord(iop_base, eep_addr);
16836 if (*charfields++) {
16837 *wbuf = le16_to_cpu(*wbuf);
16844 * Read the EEPROM from specified location
16846 static ushort __init AdvReadEEPWord(AdvPortAddr iop_base, int eep_word_addr)
16848 AdvWriteWordRegister(iop_base, IOPW_EE_CMD,
16849 ASC_EEP_CMD_READ | eep_word_addr);
16850 AdvWaitEEPCmd(iop_base);
16851 return AdvReadWordRegister(iop_base, IOPW_EE_DATA);
16855 * Wait for EEPROM command to complete
16857 static void __init AdvWaitEEPCmd(AdvPortAddr iop_base)
16861 for (eep_delay_ms = 0; eep_delay_ms < ADV_EEP_DELAY_MS; eep_delay_ms++) {
16862 if (AdvReadWordRegister(iop_base, IOPW_EE_CMD) &
16863 ASC_EEP_CMD_DONE) {
16866 DvcSleepMilliSecond(1);
16868 if ((AdvReadWordRegister(iop_base, IOPW_EE_CMD) & ASC_EEP_CMD_DONE) ==
16876 * Write the EEPROM from 'cfg_buf'.
16879 AdvSet3550EEPConfig(AdvPortAddr iop_base, ADVEEP_3550_CONFIG *cfg_buf)
16882 ushort addr, chksum;
16883 ushort *charfields;
16885 wbuf = (ushort *)cfg_buf;
16886 charfields = (ushort *)&ADVEEP_3550_Config_Field_IsChar;
16889 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE_ABLE);
16890 AdvWaitEEPCmd(iop_base);
16893 * Write EEPROM from word 0 to word 20.
16895 for (addr = ADV_EEP_DVC_CFG_BEGIN;
16896 addr < ADV_EEP_DVC_CFG_END; addr++, wbuf++) {
16899 if (*charfields++) {
16900 word = cpu_to_le16(*wbuf);
16904 chksum += *wbuf; /* Checksum is calculated from word values. */
16905 AdvWriteWordRegister(iop_base, IOPW_EE_DATA, word);
16906 AdvWriteWordRegister(iop_base, IOPW_EE_CMD,
16907 ASC_EEP_CMD_WRITE | addr);
16908 AdvWaitEEPCmd(iop_base);
16909 DvcSleepMilliSecond(ADV_EEP_DELAY_MS);
16913 * Write EEPROM checksum at word 21.
16915 AdvWriteWordRegister(iop_base, IOPW_EE_DATA, chksum);
16916 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE | addr);
16917 AdvWaitEEPCmd(iop_base);
16922 * Write EEPROM OEM name at words 22 to 29.
16924 for (addr = ADV_EEP_DVC_CTL_BEGIN;
16925 addr < ADV_EEP_MAX_WORD_ADDR; addr++, wbuf++) {
16928 if (*charfields++) {
16929 word = cpu_to_le16(*wbuf);
16933 AdvWriteWordRegister(iop_base, IOPW_EE_DATA, word);
16934 AdvWriteWordRegister(iop_base, IOPW_EE_CMD,
16935 ASC_EEP_CMD_WRITE | addr);
16936 AdvWaitEEPCmd(iop_base);
16938 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE_DISABLE);
16939 AdvWaitEEPCmd(iop_base);
16944 * Write the EEPROM from 'cfg_buf'.
16947 AdvSet38C0800EEPConfig(AdvPortAddr iop_base, ADVEEP_38C0800_CONFIG *cfg_buf)
16950 ushort *charfields;
16951 ushort addr, chksum;
16953 wbuf = (ushort *)cfg_buf;
16954 charfields = (ushort *)&ADVEEP_38C0800_Config_Field_IsChar;
16957 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE_ABLE);
16958 AdvWaitEEPCmd(iop_base);
16961 * Write EEPROM from word 0 to word 20.
16963 for (addr = ADV_EEP_DVC_CFG_BEGIN;
16964 addr < ADV_EEP_DVC_CFG_END; addr++, wbuf++) {
16967 if (*charfields++) {
16968 word = cpu_to_le16(*wbuf);
16972 chksum += *wbuf; /* Checksum is calculated from word values. */
16973 AdvWriteWordRegister(iop_base, IOPW_EE_DATA, word);
16974 AdvWriteWordRegister(iop_base, IOPW_EE_CMD,
16975 ASC_EEP_CMD_WRITE | addr);
16976 AdvWaitEEPCmd(iop_base);
16977 DvcSleepMilliSecond(ADV_EEP_DELAY_MS);
16981 * Write EEPROM checksum at word 21.
16983 AdvWriteWordRegister(iop_base, IOPW_EE_DATA, chksum);
16984 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE | addr);
16985 AdvWaitEEPCmd(iop_base);
16990 * Write EEPROM OEM name at words 22 to 29.
16992 for (addr = ADV_EEP_DVC_CTL_BEGIN;
16993 addr < ADV_EEP_MAX_WORD_ADDR; addr++, wbuf++) {
16996 if (*charfields++) {
16997 word = cpu_to_le16(*wbuf);
17001 AdvWriteWordRegister(iop_base, IOPW_EE_DATA, word);
17002 AdvWriteWordRegister(iop_base, IOPW_EE_CMD,
17003 ASC_EEP_CMD_WRITE | addr);
17004 AdvWaitEEPCmd(iop_base);
17006 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE_DISABLE);
17007 AdvWaitEEPCmd(iop_base);
17012 * Write the EEPROM from 'cfg_buf'.
17015 AdvSet38C1600EEPConfig(AdvPortAddr iop_base, ADVEEP_38C1600_CONFIG *cfg_buf)
17018 ushort *charfields;
17019 ushort addr, chksum;
17021 wbuf = (ushort *)cfg_buf;
17022 charfields = (ushort *)&ADVEEP_38C1600_Config_Field_IsChar;
17025 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE_ABLE);
17026 AdvWaitEEPCmd(iop_base);
17029 * Write EEPROM from word 0 to word 20.
17031 for (addr = ADV_EEP_DVC_CFG_BEGIN;
17032 addr < ADV_EEP_DVC_CFG_END; addr++, wbuf++) {
17035 if (*charfields++) {
17036 word = cpu_to_le16(*wbuf);
17040 chksum += *wbuf; /* Checksum is calculated from word values. */
17041 AdvWriteWordRegister(iop_base, IOPW_EE_DATA, word);
17042 AdvWriteWordRegister(iop_base, IOPW_EE_CMD,
17043 ASC_EEP_CMD_WRITE | addr);
17044 AdvWaitEEPCmd(iop_base);
17045 DvcSleepMilliSecond(ADV_EEP_DELAY_MS);
17049 * Write EEPROM checksum at word 21.
17051 AdvWriteWordRegister(iop_base, IOPW_EE_DATA, chksum);
17052 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE | addr);
17053 AdvWaitEEPCmd(iop_base);
17058 * Write EEPROM OEM name at words 22 to 29.
17060 for (addr = ADV_EEP_DVC_CTL_BEGIN;
17061 addr < ADV_EEP_MAX_WORD_ADDR; addr++, wbuf++) {
17064 if (*charfields++) {
17065 word = cpu_to_le16(*wbuf);
17069 AdvWriteWordRegister(iop_base, IOPW_EE_DATA, word);
17070 AdvWriteWordRegister(iop_base, IOPW_EE_CMD,
17071 ASC_EEP_CMD_WRITE | addr);
17072 AdvWaitEEPCmd(iop_base);
17074 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE_DISABLE);
17075 AdvWaitEEPCmd(iop_base);
17081 * AdvExeScsiQueue() - Send a request to the RISC microcode program.
17083 * Allocate a carrier structure, point the carrier to the ADV_SCSI_REQ_Q,
17084 * add the carrier to the ICQ (Initiator Command Queue), and tickle the
17085 * RISC to notify it a new command is ready to be executed.
17087 * If 'done_status' is not set to QD_DO_RETRY, then 'error_retry' will be
17088 * set to SCSI_MAX_RETRY.
17090 * Multi-byte fields in the ASC_SCSI_REQ_Q that are used by the microcode
17091 * for DMA addresses or math operations are byte swapped to little-endian
17095 * ADV_SUCCESS(1) - The request was successfully queued.
17096 * ADV_BUSY(0) - Resource unavailable; Retry again after pending
17097 * request completes.
17098 * ADV_ERROR(-1) - Invalid ADV_SCSI_REQ_Q request structure
17101 static int AdvExeScsiQueue(ADV_DVC_VAR *asc_dvc, ADV_SCSI_REQ_Q *scsiq)
17103 ulong last_int_level;
17104 AdvPortAddr iop_base;
17106 ADV_PADDR req_paddr;
17107 ADV_CARR_T *new_carrp;
17109 ASC_ASSERT(scsiq != NULL); /* 'scsiq' should never be NULL. */
17112 * The ADV_SCSI_REQ_Q 'target_id' field should never exceed ADV_MAX_TID.
17114 if (scsiq->target_id > ADV_MAX_TID) {
17115 scsiq->host_status = QHSTA_M_INVALID_DEVICE;
17116 scsiq->done_status = QD_WITH_ERROR;
17120 iop_base = asc_dvc->iop_base;
17122 last_int_level = DvcEnterCritical();
17125 * Allocate a carrier ensuring at least one carrier always
17126 * remains on the freelist and initialize fields.
17128 if ((new_carrp = asc_dvc->carr_freelist) == NULL) {
17129 DvcLeaveCritical(last_int_level);
17132 asc_dvc->carr_freelist = (ADV_CARR_T *)
17133 ADV_U32_TO_VADDR(le32_to_cpu(new_carrp->next_vpa));
17134 asc_dvc->carr_pending_cnt++;
17137 * Set the carrier to be a stopper by setting 'next_vpa'
17138 * to the stopper value. The current stopper will be changed
17139 * below to point to the new stopper.
17141 new_carrp->next_vpa = cpu_to_le32(ASC_CQ_STOPPER);
17144 * Clear the ADV_SCSI_REQ_Q done flag.
17146 scsiq->a_flag &= ~ADV_SCSIQ_DONE;
17148 req_size = sizeof(ADV_SCSI_REQ_Q);
17149 req_paddr = DvcGetPhyAddr(asc_dvc, scsiq, (uchar *)scsiq,
17150 (ADV_SDCNT *)&req_size, ADV_IS_SCSIQ_FLAG);
17152 ASC_ASSERT(ADV_32BALIGN(req_paddr) == req_paddr);
17153 ASC_ASSERT(req_size >= sizeof(ADV_SCSI_REQ_Q));
17155 /* Wait for assertion before making little-endian */
17156 req_paddr = cpu_to_le32(req_paddr);
17158 /* Save virtual and physical address of ADV_SCSI_REQ_Q and carrier. */
17159 scsiq->scsiq_ptr = cpu_to_le32(ADV_VADDR_TO_U32(scsiq));
17160 scsiq->scsiq_rptr = req_paddr;
17162 scsiq->carr_va = cpu_to_le32(ADV_VADDR_TO_U32(asc_dvc->icq_sp));
17164 * Every ADV_CARR_T.carr_pa is byte swapped to little-endian
17165 * order during initialization.
17167 scsiq->carr_pa = asc_dvc->icq_sp->carr_pa;
17170 * Use the current stopper to send the ADV_SCSI_REQ_Q command to
17171 * the microcode. The newly allocated stopper will become the new
17174 asc_dvc->icq_sp->areq_vpa = req_paddr;
17177 * Set the 'next_vpa' pointer for the old stopper to be the
17178 * physical address of the new stopper. The RISC can only
17179 * follow physical addresses.
17181 asc_dvc->icq_sp->next_vpa = new_carrp->carr_pa;
17184 * Set the host adapter stopper pointer to point to the new carrier.
17186 asc_dvc->icq_sp = new_carrp;
17188 if (asc_dvc->chip_type == ADV_CHIP_ASC3550 ||
17189 asc_dvc->chip_type == ADV_CHIP_ASC38C0800) {
17191 * Tickle the RISC to tell it to read its Command Queue Head pointer.
17193 AdvWriteByteRegister(iop_base, IOPB_TICKLE, ADV_TICKLE_A);
17194 if (asc_dvc->chip_type == ADV_CHIP_ASC3550) {
17196 * Clear the tickle value. In the ASC-3550 the RISC flag
17197 * command 'clr_tickle_a' does not work unless the host
17198 * value is cleared.
17200 AdvWriteByteRegister(iop_base, IOPB_TICKLE,
17203 } else if (asc_dvc->chip_type == ADV_CHIP_ASC38C1600) {
17205 * Notify the RISC a carrier is ready by writing the physical
17206 * address of the new carrier stopper to the COMMA register.
17208 AdvWriteDWordRegister(iop_base, IOPDW_COMMA,
17209 le32_to_cpu(new_carrp->carr_pa));
17212 DvcLeaveCritical(last_int_level);
17214 return ADV_SUCCESS;
17218 * Reset SCSI Bus and purge all outstanding requests.
17221 * ADV_TRUE(1) - All requests are purged and SCSI Bus is reset.
17222 * ADV_FALSE(0) - Microcode command failed.
17223 * ADV_ERROR(-1) - Microcode command timed-out. Microcode or IC
17224 * may be hung which requires driver recovery.
17226 static int AdvResetSB(ADV_DVC_VAR *asc_dvc)
17231 * Send the SCSI Bus Reset idle start idle command which asserts
17232 * the SCSI Bus Reset signal.
17234 status = AdvSendIdleCmd(asc_dvc, (ushort)IDLE_CMD_SCSI_RESET_START, 0L);
17235 if (status != ADV_TRUE) {
17240 * Delay for the specified SCSI Bus Reset hold time.
17242 * The hold time delay is done on the host because the RISC has no
17243 * microsecond accurate timer.
17245 DvcDelayMicroSecond(asc_dvc, (ushort)ASC_SCSI_RESET_HOLD_TIME_US);
17248 * Send the SCSI Bus Reset end idle command which de-asserts
17249 * the SCSI Bus Reset signal and purges any pending requests.
17251 status = AdvSendIdleCmd(asc_dvc, (ushort)IDLE_CMD_SCSI_RESET_END, 0L);
17252 if (status != ADV_TRUE) {
17256 DvcSleepMilliSecond((ADV_DCNT)asc_dvc->scsi_reset_wait * 1000);
17262 * Reset chip and SCSI Bus.
17265 * ADV_TRUE(1) - Chip re-initialization and SCSI Bus Reset successful.
17266 * ADV_FALSE(0) - Chip re-initialization and SCSI Bus Reset failure.
17268 static int AdvResetChipAndSB(ADV_DVC_VAR *asc_dvc)
17271 ushort wdtr_able, sdtr_able, tagqng_able;
17272 ushort ppr_able = 0;
17273 uchar tid, max_cmd[ADV_MAX_TID + 1];
17274 AdvPortAddr iop_base;
17277 iop_base = asc_dvc->iop_base;
17280 * Save current per TID negotiated values.
17282 AdvReadWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able);
17283 AdvReadWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
17284 if (asc_dvc->chip_type == ADV_CHIP_ASC38C1600) {
17285 AdvReadWordLram(iop_base, ASC_MC_PPR_ABLE, ppr_able);
17287 AdvReadWordLram(iop_base, ASC_MC_TAGQNG_ABLE, tagqng_able);
17288 for (tid = 0; tid <= ADV_MAX_TID; tid++) {
17289 AdvReadByteLram(iop_base, ASC_MC_NUMBER_OF_MAX_CMD + tid,
17294 * Force the AdvInitAsc3550/38C0800Driver() function to
17295 * perform a SCSI Bus Reset by clearing the BIOS signature word.
17296 * The initialization functions assumes a SCSI Bus Reset is not
17297 * needed if the BIOS signature word is present.
17299 AdvReadWordLram(iop_base, ASC_MC_BIOS_SIGNATURE, bios_sig);
17300 AdvWriteWordLram(iop_base, ASC_MC_BIOS_SIGNATURE, 0);
17303 * Stop chip and reset it.
17305 AdvWriteWordRegister(iop_base, IOPW_RISC_CSR, ADV_RISC_CSR_STOP);
17306 AdvWriteWordRegister(iop_base, IOPW_CTRL_REG, ADV_CTRL_REG_CMD_RESET);
17307 DvcSleepMilliSecond(100);
17308 AdvWriteWordRegister(iop_base, IOPW_CTRL_REG,
17309 ADV_CTRL_REG_CMD_WR_IO_REG);
17312 * Reset Adv Library error code, if any, and try
17313 * re-initializing the chip.
17315 asc_dvc->err_code = 0;
17316 if (asc_dvc->chip_type == ADV_CHIP_ASC38C1600) {
17317 status = AdvInitAsc38C1600Driver(asc_dvc);
17318 } else if (asc_dvc->chip_type == ADV_CHIP_ASC38C0800) {
17319 status = AdvInitAsc38C0800Driver(asc_dvc);
17321 status = AdvInitAsc3550Driver(asc_dvc);
17324 /* Translate initialization return value to status value. */
17328 status = ADV_FALSE;
17332 * Restore the BIOS signature word.
17334 AdvWriteWordLram(iop_base, ASC_MC_BIOS_SIGNATURE, bios_sig);
17337 * Restore per TID negotiated values.
17339 AdvWriteWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able);
17340 AdvWriteWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
17341 if (asc_dvc->chip_type == ADV_CHIP_ASC38C1600) {
17342 AdvWriteWordLram(iop_base, ASC_MC_PPR_ABLE, ppr_able);
17344 AdvWriteWordLram(iop_base, ASC_MC_TAGQNG_ABLE, tagqng_able);
17345 for (tid = 0; tid <= ADV_MAX_TID; tid++) {
17346 AdvWriteByteLram(iop_base, ASC_MC_NUMBER_OF_MAX_CMD + tid,
17354 * Adv Library Interrupt Service Routine
17356 * This function is called by a driver's interrupt service routine.
17357 * The function disables and re-enables interrupts.
17359 * When a microcode idle command is completed, the ADV_DVC_VAR
17360 * 'idle_cmd_done' field is set to ADV_TRUE.
17362 * Note: AdvISR() can be called when interrupts are disabled or even
17363 * when there is no hardware interrupt condition present. It will
17364 * always check for completed idle commands and microcode requests.
17365 * This is an important feature that shouldn't be changed because it
17366 * allows commands to be completed from polling mode loops.
17369 * ADV_TRUE(1) - interrupt was pending
17370 * ADV_FALSE(0) - no interrupt was pending
17372 static int AdvISR(ADV_DVC_VAR *asc_dvc)
17374 AdvPortAddr iop_base;
17377 ADV_CARR_T *free_carrp;
17378 ADV_VADDR irq_next_vpa;
17380 ADV_SCSI_REQ_Q *scsiq;
17382 flags = DvcEnterCritical();
17384 iop_base = asc_dvc->iop_base;
17386 /* Reading the register clears the interrupt. */
17387 int_stat = AdvReadByteRegister(iop_base, IOPB_INTR_STATUS_REG);
17389 if ((int_stat & (ADV_INTR_STATUS_INTRA | ADV_INTR_STATUS_INTRB |
17390 ADV_INTR_STATUS_INTRC)) == 0) {
17391 DvcLeaveCritical(flags);
17396 * Notify the driver of an asynchronous microcode condition by
17397 * calling the ADV_DVC_VAR.async_callback function. The function
17398 * is passed the microcode ASC_MC_INTRB_CODE byte value.
17400 if (int_stat & ADV_INTR_STATUS_INTRB) {
17403 AdvReadByteLram(iop_base, ASC_MC_INTRB_CODE, intrb_code);
17405 if (asc_dvc->chip_type == ADV_CHIP_ASC3550 ||
17406 asc_dvc->chip_type == ADV_CHIP_ASC38C0800) {
17407 if (intrb_code == ADV_ASYNC_CARRIER_READY_FAILURE &&
17408 asc_dvc->carr_pending_cnt != 0) {
17409 AdvWriteByteRegister(iop_base, IOPB_TICKLE,
17411 if (asc_dvc->chip_type == ADV_CHIP_ASC3550) {
17412 AdvWriteByteRegister(iop_base,
17419 if (asc_dvc->async_callback != 0) {
17420 (*asc_dvc->async_callback) (asc_dvc, intrb_code);
17425 * Check if the IRQ stopper carrier contains a completed request.
17427 while (((irq_next_vpa =
17428 le32_to_cpu(asc_dvc->irq_sp->next_vpa)) & ASC_RQ_DONE) != 0) {
17430 * Get a pointer to the newly completed ADV_SCSI_REQ_Q structure.
17431 * The RISC will have set 'areq_vpa' to a virtual address.
17433 * The firmware will have copied the ASC_SCSI_REQ_Q.scsiq_ptr
17434 * field to the carrier ADV_CARR_T.areq_vpa field. The conversion
17435 * below complements the conversion of ASC_SCSI_REQ_Q.scsiq_ptr'
17436 * in AdvExeScsiQueue().
17438 scsiq = (ADV_SCSI_REQ_Q *)
17439 ADV_U32_TO_VADDR(le32_to_cpu(asc_dvc->irq_sp->areq_vpa));
17442 * Request finished with good status and the queue was not
17443 * DMAed to host memory by the firmware. Set all status fields
17444 * to indicate good status.
17446 if ((irq_next_vpa & ASC_RQ_GOOD) != 0) {
17447 scsiq->done_status = QD_NO_ERROR;
17448 scsiq->host_status = scsiq->scsi_status = 0;
17449 scsiq->data_cnt = 0L;
17453 * Advance the stopper pointer to the next carrier
17454 * ignoring the lower four bits. Free the previous
17457 free_carrp = asc_dvc->irq_sp;
17458 asc_dvc->irq_sp = (ADV_CARR_T *)
17459 ADV_U32_TO_VADDR(ASC_GET_CARRP(irq_next_vpa));
17461 free_carrp->next_vpa =
17462 cpu_to_le32(ADV_VADDR_TO_U32(asc_dvc->carr_freelist));
17463 asc_dvc->carr_freelist = free_carrp;
17464 asc_dvc->carr_pending_cnt--;
17466 ASC_ASSERT(scsiq != NULL);
17467 target_bit = ADV_TID_TO_TIDMASK(scsiq->target_id);
17470 * Clear request microcode control flag.
17475 * If the command that completed was a SCSI INQUIRY and
17476 * LUN 0 was sent the command, then process the INQUIRY
17477 * command information for the device.
17479 * Note: If data returned were either VPD or CmdDt data,
17480 * don't process the INQUIRY command information for
17481 * the device, otherwise may erroneously set *_able bits.
17483 if (scsiq->done_status == QD_NO_ERROR &&
17484 scsiq->cdb[0] == INQUIRY &&
17485 scsiq->target_lun == 0 &&
17486 (scsiq->cdb[1] & ADV_INQ_RTN_VPD_AND_CMDDT)
17487 == ADV_INQ_RTN_STD_INQUIRY_DATA) {
17488 AdvInquiryHandling(asc_dvc, scsiq);
17492 * Notify the driver of the completed request by passing
17493 * the ADV_SCSI_REQ_Q pointer to its callback function.
17495 scsiq->a_flag |= ADV_SCSIQ_DONE;
17496 (*asc_dvc->isr_callback) (asc_dvc, scsiq);
17498 * Note: After the driver callback function is called, 'scsiq'
17499 * can no longer be referenced.
17501 * Fall through and continue processing other completed
17506 * Disable interrupts again in case the driver inadvertently
17507 * enabled interrupts in its callback function.
17509 * The DvcEnterCritical() return value is ignored, because
17510 * the 'flags' saved when AdvISR() was first entered will be
17511 * used to restore the interrupt flag on exit.
17513 (void)DvcEnterCritical();
17515 DvcLeaveCritical(flags);
17520 * Send an idle command to the chip and wait for completion.
17522 * Command completion is polled for once per microsecond.
17524 * The function can be called from anywhere including an interrupt handler.
17525 * But the function is not re-entrant, so it uses the DvcEnter/LeaveCritical()
17526 * functions to prevent reentrancy.
17529 * ADV_TRUE - command completed successfully
17530 * ADV_FALSE - command failed
17531 * ADV_ERROR - command timed out
17534 AdvSendIdleCmd(ADV_DVC_VAR *asc_dvc,
17535 ushort idle_cmd, ADV_DCNT idle_cmd_parameter)
17537 ulong last_int_level;
17540 AdvPortAddr iop_base;
17542 last_int_level = DvcEnterCritical();
17544 iop_base = asc_dvc->iop_base;
17547 * Clear the idle command status which is set by the microcode
17548 * to a non-zero value to indicate when the command is completed.
17549 * The non-zero result is one of the IDLE_CMD_STATUS_* values
17550 * defined in a_advlib.h.
17552 AdvWriteWordLram(iop_base, ASC_MC_IDLE_CMD_STATUS, (ushort)0);
17555 * Write the idle command value after the idle command parameter
17556 * has been written to avoid a race condition. If the order is not
17557 * followed, the microcode may process the idle command before the
17558 * parameters have been written to LRAM.
17560 AdvWriteDWordLramNoSwap(iop_base, ASC_MC_IDLE_CMD_PARAMETER,
17561 cpu_to_le32(idle_cmd_parameter));
17562 AdvWriteWordLram(iop_base, ASC_MC_IDLE_CMD, idle_cmd);
17565 * Tickle the RISC to tell it to process the idle command.
17567 AdvWriteByteRegister(iop_base, IOPB_TICKLE, ADV_TICKLE_B);
17568 if (asc_dvc->chip_type == ADV_CHIP_ASC3550) {
17570 * Clear the tickle value. In the ASC-3550 the RISC flag
17571 * command 'clr_tickle_b' does not work unless the host
17572 * value is cleared.
17574 AdvWriteByteRegister(iop_base, IOPB_TICKLE, ADV_TICKLE_NOP);
17577 /* Wait for up to 100 millisecond for the idle command to timeout. */
17578 for (i = 0; i < SCSI_WAIT_100_MSEC; i++) {
17579 /* Poll once each microsecond for command completion. */
17580 for (j = 0; j < SCSI_US_PER_MSEC; j++) {
17581 AdvReadWordLram(iop_base, ASC_MC_IDLE_CMD_STATUS,
17584 DvcLeaveCritical(last_int_level);
17587 DvcDelayMicroSecond(asc_dvc, (ushort)1);
17591 ASC_ASSERT(0); /* The idle command should never timeout. */
17592 DvcLeaveCritical(last_int_level);
17597 * Inquiry Information Byte 7 Handling
17599 * Handle SCSI Inquiry Command information for a device by setting
17600 * microcode operating variables that affect WDTR, SDTR, and Tag
17603 static void AdvInquiryHandling(ADV_DVC_VAR *asc_dvc, ADV_SCSI_REQ_Q *scsiq)
17605 AdvPortAddr iop_base;
17607 ADV_SCSI_INQUIRY *inq;
17612 * AdvInquiryHandling() requires up to INQUIRY information Byte 7
17615 * If less than 8 bytes of INQUIRY information were requested or less
17616 * than 8 bytes were transferred, then return. cdb[4] is the request
17617 * length and the ADV_SCSI_REQ_Q 'data_cnt' field is set by the
17618 * microcode to the transfer residual count.
17621 if (scsiq->cdb[4] < 8 ||
17622 (scsiq->cdb[4] - le32_to_cpu(scsiq->data_cnt)) < 8) {
17626 iop_base = asc_dvc->iop_base;
17627 tid = scsiq->target_id;
17629 inq = (ADV_SCSI_INQUIRY *) scsiq->vdata_addr;
17632 * WDTR, SDTR, and Tag Queuing cannot be enabled for old devices.
17634 if (ADV_INQ_RESPONSE_FMT(inq) < 2 && ADV_INQ_ANSI_VER(inq) < 2) {
17638 * INQUIRY Byte 7 Handling
17640 * Use a device's INQUIRY byte 7 to determine whether it
17641 * supports WDTR, SDTR, and Tag Queuing. If the feature
17642 * is enabled in the EEPROM and the device supports the
17643 * feature, then enable it in the microcode.
17646 tidmask = ADV_TID_TO_TIDMASK(tid);
17651 * If the EEPROM enabled WDTR for the device and the device
17652 * supports wide bus (16 bit) transfers, then turn on the
17653 * device's 'wdtr_able' bit and write the new value to the
17656 if ((asc_dvc->wdtr_able & tidmask) && ADV_INQ_WIDE16(inq)) {
17657 AdvReadWordLram(iop_base, ASC_MC_WDTR_ABLE, cfg_word);
17658 if ((cfg_word & tidmask) == 0) {
17659 cfg_word |= tidmask;
17660 AdvWriteWordLram(iop_base, ASC_MC_WDTR_ABLE,
17664 * Clear the microcode "SDTR negotiation" and "WDTR
17665 * negotiation" done indicators for the target to cause
17666 * it to negotiate with the new setting set above.
17667 * WDTR when accepted causes the target to enter
17668 * asynchronous mode, so SDTR must be negotiated.
17670 AdvReadWordLram(iop_base, ASC_MC_SDTR_DONE,
17672 cfg_word &= ~tidmask;
17673 AdvWriteWordLram(iop_base, ASC_MC_SDTR_DONE,
17675 AdvReadWordLram(iop_base, ASC_MC_WDTR_DONE,
17677 cfg_word &= ~tidmask;
17678 AdvWriteWordLram(iop_base, ASC_MC_WDTR_DONE,
17684 * Synchronous Transfers
17686 * If the EEPROM enabled SDTR for the device and the device
17687 * supports synchronous transfers, then turn on the device's
17688 * 'sdtr_able' bit. Write the new value to the microcode.
17690 if ((asc_dvc->sdtr_able & tidmask) && ADV_INQ_SYNC(inq)) {
17691 AdvReadWordLram(iop_base, ASC_MC_SDTR_ABLE, cfg_word);
17692 if ((cfg_word & tidmask) == 0) {
17693 cfg_word |= tidmask;
17694 AdvWriteWordLram(iop_base, ASC_MC_SDTR_ABLE,
17698 * Clear the microcode "SDTR negotiation" done indicator
17699 * for the target to cause it to negotiate with the new
17700 * setting set above.
17702 AdvReadWordLram(iop_base, ASC_MC_SDTR_DONE,
17704 cfg_word &= ~tidmask;
17705 AdvWriteWordLram(iop_base, ASC_MC_SDTR_DONE,
17710 * If the Inquiry data included enough space for the SPI-3
17711 * Clocking field, then check if DT mode is supported.
17713 if (asc_dvc->chip_type == ADV_CHIP_ASC38C1600 &&
17714 (scsiq->cdb[4] >= 57 ||
17715 (scsiq->cdb[4] - le32_to_cpu(scsiq->data_cnt)) >= 57)) {
17717 * PPR (Parallel Protocol Request) Capable
17719 * If the device supports DT mode, then it must be PPR capable.
17720 * The PPR message will be used in place of the SDTR and WDTR
17721 * messages to negotiate synchronous speed and offset, transfer
17722 * width, and protocol options.
17724 if (ADV_INQ_CLOCKING(inq) & ADV_INQ_CLOCKING_DT_ONLY) {
17725 AdvReadWordLram(iop_base, ASC_MC_PPR_ABLE,
17726 asc_dvc->ppr_able);
17727 asc_dvc->ppr_able |= tidmask;
17728 AdvWriteWordLram(iop_base, ASC_MC_PPR_ABLE,
17729 asc_dvc->ppr_able);
17734 * If the EEPROM enabled Tag Queuing for the device and the
17735 * device supports Tag Queueing, then turn on the device's
17736 * 'tagqng_enable' bit in the microcode and set the microcode
17737 * maximum command count to the ADV_DVC_VAR 'max_dvc_qng'
17740 * Tag Queuing is disabled for the BIOS which runs in polled
17741 * mode and would see no benefit from Tag Queuing. Also by
17742 * disabling Tag Queuing in the BIOS devices with Tag Queuing
17743 * bugs will at least work with the BIOS.
17745 if ((asc_dvc->tagqng_able & tidmask) && ADV_INQ_CMD_QUEUE(inq)) {
17746 AdvReadWordLram(iop_base, ASC_MC_TAGQNG_ABLE, cfg_word);
17747 cfg_word |= tidmask;
17748 AdvWriteWordLram(iop_base, ASC_MC_TAGQNG_ABLE,
17751 AdvWriteByteLram(iop_base,
17752 ASC_MC_NUMBER_OF_MAX_CMD + tid,
17753 asc_dvc->max_dvc_qng);
17758 static struct Scsi_Host *__devinit
17759 advansys_board_found(int iop, struct device *dev, int bus_type)
17761 struct Scsi_Host *shost;
17762 struct pci_dev *pdev = bus_type == ASC_IS_PCI ? to_pci_dev(dev) : NULL;
17763 asc_board_t *boardp;
17764 ASC_DVC_VAR *asc_dvc_varp = NULL;
17765 ADV_DVC_VAR *adv_dvc_varp = NULL;
17766 adv_sgblk_t *sgp = NULL;
17767 int share_irq = FALSE;
17769 ADV_PADDR pci_memory_address;
17770 int warn_code, err_code;
17776 * Register the adapter, get its configuration, and
17779 ASC_DBG(2, "advansys_board_found: scsi_register()\n");
17780 shost = scsi_register(&driver_template, sizeof(asc_board_t));
17785 /* Save a pointer to the Scsi_Host of each board found. */
17786 asc_host[asc_board_count++] = shost;
17788 /* Initialize private per board data */
17789 boardp = ASC_BOARDP(shost);
17790 memset(boardp, 0, sizeof(asc_board_t));
17791 boardp->id = asc_board_count - 1;
17793 /* Initialize spinlock. */
17794 spin_lock_init(&boardp->lock);
17797 * Handle both narrow and wide boards.
17799 * If a Wide board was detected, set the board structure
17800 * wide board flag. Set-up the board structure based on
17804 if (bus_type == ASC_IS_PCI &&
17805 (pdev->device == PCI_DEVICE_ID_ASP_ABP940UW ||
17806 pdev->device == PCI_DEVICE_ID_38C0800_REV1 ||
17807 pdev->device == PCI_DEVICE_ID_38C1600_REV1)) {
17808 boardp->flags |= ASC_IS_WIDE_BOARD;
17810 #endif /* CONFIG_PCI */
17812 if (ASC_NARROW_BOARD(boardp)) {
17813 ASC_DBG(1, "advansys_board_found: narrow board\n");
17814 asc_dvc_varp = &boardp->dvc_var.asc_dvc_var;
17815 asc_dvc_varp->bus_type = bus_type;
17816 asc_dvc_varp->drv_ptr = boardp;
17817 asc_dvc_varp->cfg = &boardp->dvc_cfg.asc_dvc_cfg;
17818 asc_dvc_varp->cfg->overrun_buf = &overrun_buf[0];
17819 asc_dvc_varp->iop_base = iop;
17820 asc_dvc_varp->isr_callback = asc_isr_callback;
17822 ASC_DBG(1, "advansys_board_found: wide board\n");
17823 adv_dvc_varp = &boardp->dvc_var.adv_dvc_var;
17824 adv_dvc_varp->drv_ptr = boardp;
17825 adv_dvc_varp->cfg = &boardp->dvc_cfg.adv_dvc_cfg;
17826 adv_dvc_varp->isr_callback = adv_isr_callback;
17827 adv_dvc_varp->async_callback = adv_async_callback;
17829 if (pdev->device == PCI_DEVICE_ID_ASP_ABP940UW) {
17830 ASC_DBG(1, "advansys_board_found: ASC-3550\n");
17831 adv_dvc_varp->chip_type = ADV_CHIP_ASC3550;
17832 } else if (pdev->device == PCI_DEVICE_ID_38C0800_REV1) {
17833 ASC_DBG(1, "advansys_board_found: ASC-38C0800\n");
17834 adv_dvc_varp->chip_type = ADV_CHIP_ASC38C0800;
17836 ASC_DBG(1, "advansys_board_found: ASC-38C1600\n");
17837 adv_dvc_varp->chip_type = ADV_CHIP_ASC38C1600;
17839 #endif /* CONFIG_PCI */
17842 * Map the board's registers into virtual memory for
17843 * PCI slave access. Only memory accesses are used to
17844 * access the board's registers.
17846 * Note: The PCI register base address is not always
17847 * page aligned, but the address passed to ioremap()
17848 * must be page aligned. It is guaranteed that the
17849 * PCI register base address will not cross a page
17852 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
17853 iolen = ADV_3550_IOLEN;
17854 } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
17855 iolen = ADV_38C0800_IOLEN;
17857 iolen = ADV_38C1600_IOLEN;
17860 pci_memory_address = pci_resource_start(pdev, 1);
17862 "advansys_board_found: pci_memory_address: 0x%lx\n",
17863 (ulong)pci_memory_address);
17864 if ((boardp->ioremap_addr =
17865 ioremap(pci_memory_address & PAGE_MASK, PAGE_SIZE)) == 0) {
17867 ("advansys_board_found: board %d: ioremap(%x, %d) returned NULL\n",
17868 boardp->id, pci_memory_address, iolen);
17869 scsi_unregister(shost);
17874 "advansys_board_found: ioremap_addr: 0x%lx\n",
17875 (ulong)boardp->ioremap_addr);
17876 adv_dvc_varp->iop_base = (AdvPortAddr)
17877 (boardp->ioremap_addr +
17878 (pci_memory_address - (pci_memory_address & PAGE_MASK)));
17880 "advansys_board_found: iop_base: 0x%lx\n",
17881 adv_dvc_varp->iop_base);
17882 #endif /* CONFIG_PCI */
17885 * Even though it isn't used to access wide boards, other
17886 * than for the debug line below, save I/O Port address so
17887 * that it can be reported.
17889 boardp->ioport = iop;
17892 "advansys_board_found: iopb_chip_id_1 0x%x, iopw_chip_id_0 0x%x\n",
17893 (ushort)inp(iop + 1), (ushort)inpw(iop));
17896 #ifdef CONFIG_PROC_FS
17898 * Allocate buffer for printing information from
17899 * /proc/scsi/advansys/[0...].
17901 if ((boardp->prtbuf = kmalloc(ASC_PRTBUF_SIZE, GFP_ATOMIC)) == NULL) {
17903 ("advansys_board_found: board %d: kmalloc(%d, %d) returned NULL\n",
17904 boardp->id, ASC_PRTBUF_SIZE, GFP_ATOMIC);
17905 scsi_unregister(shost);
17909 #endif /* CONFIG_PROC_FS */
17911 if (ASC_NARROW_BOARD(boardp)) {
17912 asc_dvc_varp->cfg->dev = dev;
17914 * Set the board bus type and PCI IRQ before
17915 * calling AscInitGetConfig().
17917 switch (asc_dvc_varp->bus_type) {
17920 shost->unchecked_isa_dma = TRUE;
17924 shost->unchecked_isa_dma = FALSE;
17928 shost->unchecked_isa_dma = FALSE;
17931 #endif /* CONFIG_ISA */
17934 shost->irq = asc_dvc_varp->irq_no = pdev->irq;
17935 asc_dvc_varp->cfg->pci_slot_info =
17936 ASC_PCI_MKID(pdev->bus->number,
17937 PCI_SLOT(pdev->devfn),
17938 PCI_FUNC(pdev->devfn));
17939 shost->unchecked_isa_dma = FALSE;
17942 #endif /* CONFIG_PCI */
17945 ("advansys_board_found: board %d: unknown adapter type: %d\n",
17946 boardp->id, asc_dvc_varp->bus_type);
17947 shost->unchecked_isa_dma = TRUE;
17952 adv_dvc_varp->cfg->dev = dev;
17954 * For Wide boards set PCI information before calling
17955 * AdvInitGetConfig().
17958 shost->irq = adv_dvc_varp->irq_no = pdev->irq;
17959 adv_dvc_varp->cfg->pci_slot_info =
17960 ASC_PCI_MKID(pdev->bus->number,
17961 PCI_SLOT(pdev->devfn),
17962 PCI_FUNC(pdev->devfn));
17963 shost->unchecked_isa_dma = FALSE;
17965 #endif /* CONFIG_PCI */
17969 * Read the board configuration.
17971 if (ASC_NARROW_BOARD(boardp)) {
17973 * NOTE: AscInitGetConfig() may change the board's
17974 * bus_type value. The bus_type value should no
17975 * longer be used. If the bus_type field must be
17976 * referenced only use the bit-wise AND operator "&".
17978 ASC_DBG(2, "advansys_board_found: AscInitGetConfig()\n");
17979 switch (ret = AscInitGetConfig(asc_dvc_varp)) {
17980 case 0: /* No error */
17982 case ASC_WARN_IO_PORT_ROTATE:
17984 ("AscInitGetConfig: board %d: I/O port address modified\n",
17987 case ASC_WARN_AUTO_CONFIG:
17989 ("AscInitGetConfig: board %d: I/O port increment switch enabled\n",
17992 case ASC_WARN_EEPROM_CHKSUM:
17994 ("AscInitGetConfig: board %d: EEPROM checksum error\n",
17997 case ASC_WARN_IRQ_MODIFIED:
17999 ("AscInitGetConfig: board %d: IRQ modified\n",
18002 case ASC_WARN_CMD_QNG_CONFLICT:
18004 ("AscInitGetConfig: board %d: tag queuing enabled w/o disconnects\n",
18009 ("AscInitGetConfig: board %d: unknown warning: 0x%x\n",
18013 if ((err_code = asc_dvc_varp->err_code) != 0) {
18015 ("AscInitGetConfig: board %d error: init_state 0x%x, err_code 0x%x\n",
18017 asc_dvc_varp->init_state, asc_dvc_varp->err_code);
18020 ASC_DBG(2, "advansys_board_found: AdvInitGetConfig()\n");
18021 if ((ret = AdvInitGetConfig(adv_dvc_varp)) != 0) {
18023 ("AdvInitGetConfig: board %d: warning: 0x%x\n",
18026 if ((err_code = adv_dvc_varp->err_code) != 0) {
18028 ("AdvInitGetConfig: board %d error: err_code 0x%x\n",
18029 boardp->id, adv_dvc_varp->err_code);
18033 if (err_code != 0) {
18034 #ifdef CONFIG_PROC_FS
18035 kfree(boardp->prtbuf);
18036 #endif /* CONFIG_PROC_FS */
18037 scsi_unregister(shost);
18043 * Save the EEPROM configuration so that it can be displayed
18044 * from /proc/scsi/advansys/[0...].
18046 if (ASC_NARROW_BOARD(boardp)) {
18051 * Set the adapter's target id bit in the 'init_tidmask' field.
18053 boardp->init_tidmask |=
18054 ADV_TID_TO_TIDMASK(asc_dvc_varp->cfg->chip_scsi_id);
18057 * Save EEPROM settings for the board.
18059 ep = &boardp->eep_config.asc_eep;
18061 ep->init_sdtr = asc_dvc_varp->cfg->sdtr_enable;
18062 ep->disc_enable = asc_dvc_varp->cfg->disc_enable;
18063 ep->use_cmd_qng = asc_dvc_varp->cfg->cmd_qng_enabled;
18064 ASC_EEP_SET_DMA_SPD(ep, asc_dvc_varp->cfg->isa_dma_speed);
18065 ep->start_motor = asc_dvc_varp->start_motor;
18066 ep->cntl = asc_dvc_varp->dvc_cntl;
18067 ep->no_scam = asc_dvc_varp->no_scam;
18068 ep->max_total_qng = asc_dvc_varp->max_total_qng;
18069 ASC_EEP_SET_CHIP_ID(ep, asc_dvc_varp->cfg->chip_scsi_id);
18070 /* 'max_tag_qng' is set to the same value for every device. */
18071 ep->max_tag_qng = asc_dvc_varp->cfg->max_tag_qng[0];
18072 ep->adapter_info[0] = asc_dvc_varp->cfg->adapter_info[0];
18073 ep->adapter_info[1] = asc_dvc_varp->cfg->adapter_info[1];
18074 ep->adapter_info[2] = asc_dvc_varp->cfg->adapter_info[2];
18075 ep->adapter_info[3] = asc_dvc_varp->cfg->adapter_info[3];
18076 ep->adapter_info[4] = asc_dvc_varp->cfg->adapter_info[4];
18077 ep->adapter_info[5] = asc_dvc_varp->cfg->adapter_info[5];
18080 * Modify board configuration.
18082 ASC_DBG(2, "advansys_board_found: AscInitSetConfig()\n");
18083 switch (ret = AscInitSetConfig(asc_dvc_varp)) {
18084 case 0: /* No error. */
18086 case ASC_WARN_IO_PORT_ROTATE:
18088 ("AscInitSetConfig: board %d: I/O port address modified\n",
18091 case ASC_WARN_AUTO_CONFIG:
18093 ("AscInitSetConfig: board %d: I/O port increment switch enabled\n",
18096 case ASC_WARN_EEPROM_CHKSUM:
18098 ("AscInitSetConfig: board %d: EEPROM checksum error\n",
18101 case ASC_WARN_IRQ_MODIFIED:
18103 ("AscInitSetConfig: board %d: IRQ modified\n",
18106 case ASC_WARN_CMD_QNG_CONFLICT:
18108 ("AscInitSetConfig: board %d: tag queuing w/o disconnects\n",
18113 ("AscInitSetConfig: board %d: unknown warning: 0x%x\n",
18117 if (asc_dvc_varp->err_code != 0) {
18119 ("AscInitSetConfig: board %d error: init_state 0x%x, err_code 0x%x\n",
18121 asc_dvc_varp->init_state, asc_dvc_varp->err_code);
18122 #ifdef CONFIG_PROC_FS
18123 kfree(boardp->prtbuf);
18124 #endif /* CONFIG_PROC_FS */
18125 scsi_unregister(shost);
18131 * Finish initializing the 'Scsi_Host' structure.
18133 /* AscInitSetConfig() will set the IRQ for non-PCI boards. */
18134 if ((asc_dvc_varp->bus_type & ASC_IS_PCI) == 0) {
18135 shost->irq = asc_dvc_varp->irq_no;
18138 ADVEEP_3550_CONFIG *ep_3550;
18139 ADVEEP_38C0800_CONFIG *ep_38C0800;
18140 ADVEEP_38C1600_CONFIG *ep_38C1600;
18143 * Save Wide EEP Configuration Information.
18145 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
18146 ep_3550 = &boardp->eep_config.adv_3550_eep;
18148 ep_3550->adapter_scsi_id = adv_dvc_varp->chip_scsi_id;
18149 ep_3550->max_host_qng = adv_dvc_varp->max_host_qng;
18150 ep_3550->max_dvc_qng = adv_dvc_varp->max_dvc_qng;
18151 ep_3550->termination = adv_dvc_varp->cfg->termination;
18152 ep_3550->disc_enable = adv_dvc_varp->cfg->disc_enable;
18153 ep_3550->bios_ctrl = adv_dvc_varp->bios_ctrl;
18154 ep_3550->wdtr_able = adv_dvc_varp->wdtr_able;
18155 ep_3550->sdtr_able = adv_dvc_varp->sdtr_able;
18156 ep_3550->ultra_able = adv_dvc_varp->ultra_able;
18157 ep_3550->tagqng_able = adv_dvc_varp->tagqng_able;
18158 ep_3550->start_motor = adv_dvc_varp->start_motor;
18159 ep_3550->scsi_reset_delay =
18160 adv_dvc_varp->scsi_reset_wait;
18161 ep_3550->serial_number_word1 =
18162 adv_dvc_varp->cfg->serial1;
18163 ep_3550->serial_number_word2 =
18164 adv_dvc_varp->cfg->serial2;
18165 ep_3550->serial_number_word3 =
18166 adv_dvc_varp->cfg->serial3;
18167 } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
18168 ep_38C0800 = &boardp->eep_config.adv_38C0800_eep;
18170 ep_38C0800->adapter_scsi_id =
18171 adv_dvc_varp->chip_scsi_id;
18172 ep_38C0800->max_host_qng = adv_dvc_varp->max_host_qng;
18173 ep_38C0800->max_dvc_qng = adv_dvc_varp->max_dvc_qng;
18174 ep_38C0800->termination_lvd =
18175 adv_dvc_varp->cfg->termination;
18176 ep_38C0800->disc_enable =
18177 adv_dvc_varp->cfg->disc_enable;
18178 ep_38C0800->bios_ctrl = adv_dvc_varp->bios_ctrl;
18179 ep_38C0800->wdtr_able = adv_dvc_varp->wdtr_able;
18180 ep_38C0800->tagqng_able = adv_dvc_varp->tagqng_able;
18181 ep_38C0800->sdtr_speed1 = adv_dvc_varp->sdtr_speed1;
18182 ep_38C0800->sdtr_speed2 = adv_dvc_varp->sdtr_speed2;
18183 ep_38C0800->sdtr_speed3 = adv_dvc_varp->sdtr_speed3;
18184 ep_38C0800->sdtr_speed4 = adv_dvc_varp->sdtr_speed4;
18185 ep_38C0800->tagqng_able = adv_dvc_varp->tagqng_able;
18186 ep_38C0800->start_motor = adv_dvc_varp->start_motor;
18187 ep_38C0800->scsi_reset_delay =
18188 adv_dvc_varp->scsi_reset_wait;
18189 ep_38C0800->serial_number_word1 =
18190 adv_dvc_varp->cfg->serial1;
18191 ep_38C0800->serial_number_word2 =
18192 adv_dvc_varp->cfg->serial2;
18193 ep_38C0800->serial_number_word3 =
18194 adv_dvc_varp->cfg->serial3;
18196 ep_38C1600 = &boardp->eep_config.adv_38C1600_eep;
18198 ep_38C1600->adapter_scsi_id =
18199 adv_dvc_varp->chip_scsi_id;
18200 ep_38C1600->max_host_qng = adv_dvc_varp->max_host_qng;
18201 ep_38C1600->max_dvc_qng = adv_dvc_varp->max_dvc_qng;
18202 ep_38C1600->termination_lvd =
18203 adv_dvc_varp->cfg->termination;
18204 ep_38C1600->disc_enable =
18205 adv_dvc_varp->cfg->disc_enable;
18206 ep_38C1600->bios_ctrl = adv_dvc_varp->bios_ctrl;
18207 ep_38C1600->wdtr_able = adv_dvc_varp->wdtr_able;
18208 ep_38C1600->tagqng_able = adv_dvc_varp->tagqng_able;
18209 ep_38C1600->sdtr_speed1 = adv_dvc_varp->sdtr_speed1;
18210 ep_38C1600->sdtr_speed2 = adv_dvc_varp->sdtr_speed2;
18211 ep_38C1600->sdtr_speed3 = adv_dvc_varp->sdtr_speed3;
18212 ep_38C1600->sdtr_speed4 = adv_dvc_varp->sdtr_speed4;
18213 ep_38C1600->tagqng_able = adv_dvc_varp->tagqng_able;
18214 ep_38C1600->start_motor = adv_dvc_varp->start_motor;
18215 ep_38C1600->scsi_reset_delay =
18216 adv_dvc_varp->scsi_reset_wait;
18217 ep_38C1600->serial_number_word1 =
18218 adv_dvc_varp->cfg->serial1;
18219 ep_38C1600->serial_number_word2 =
18220 adv_dvc_varp->cfg->serial2;
18221 ep_38C1600->serial_number_word3 =
18222 adv_dvc_varp->cfg->serial3;
18226 * Set the adapter's target id bit in the 'init_tidmask' field.
18228 boardp->init_tidmask |=
18229 ADV_TID_TO_TIDMASK(adv_dvc_varp->chip_scsi_id);
18232 * Finish initializing the 'Scsi_Host' structure.
18234 shost->irq = adv_dvc_varp->irq_no;
18238 * Channels are numbered beginning with 0. For AdvanSys one host
18239 * structure supports one channel. Multi-channel boards have a
18240 * separate host structure for each channel.
18242 shost->max_channel = 0;
18243 if (ASC_NARROW_BOARD(boardp)) {
18244 shost->max_id = ASC_MAX_TID + 1;
18245 shost->max_lun = ASC_MAX_LUN + 1;
18247 shost->io_port = asc_dvc_varp->iop_base;
18248 boardp->asc_n_io_port = ASC_IOADR_GAP;
18249 shost->this_id = asc_dvc_varp->cfg->chip_scsi_id;
18251 /* Set maximum number of queues the adapter can handle. */
18252 shost->can_queue = asc_dvc_varp->max_total_qng;
18254 shost->max_id = ADV_MAX_TID + 1;
18255 shost->max_lun = ADV_MAX_LUN + 1;
18258 * Save the I/O Port address and length even though
18259 * I/O ports are not used to access Wide boards.
18260 * Instead the Wide boards are accessed with
18261 * PCI Memory Mapped I/O.
18263 shost->io_port = iop;
18264 boardp->asc_n_io_port = iolen;
18266 shost->this_id = adv_dvc_varp->chip_scsi_id;
18268 /* Set maximum number of queues the adapter can handle. */
18269 shost->can_queue = adv_dvc_varp->max_host_qng;
18273 * 'n_io_port' currently is one byte.
18275 * Set a value to 'n_io_port', but never referenced it because
18276 * it may be truncated.
18278 shost->n_io_port = boardp->asc_n_io_port <= 255 ?
18279 boardp->asc_n_io_port : 255;
18282 * Following v1.3.89, 'cmd_per_lun' is no longer needed
18283 * and should be set to zero.
18285 * But because of a bug introduced in v1.3.89 if the driver is
18286 * compiled as a module and 'cmd_per_lun' is zero, the Mid-Level
18287 * SCSI function 'allocate_device' will panic. To allow the driver
18288 * to work as a module in these kernels set 'cmd_per_lun' to 1.
18290 * Note: This is wrong. cmd_per_lun should be set to the depth
18291 * you want on untagged devices always.
18294 shost->cmd_per_lun = 1;
18296 shost->cmd_per_lun = 0;
18300 * Set the maximum number of scatter-gather elements the
18301 * adapter can handle.
18303 if (ASC_NARROW_BOARD(boardp)) {
18305 * Allow two commands with 'sg_tablesize' scatter-gather
18306 * elements to be executed simultaneously. This value is
18307 * the theoretical hardware limit. It may be decreased
18310 shost->sg_tablesize =
18311 (((asc_dvc_varp->max_total_qng - 2) / 2) *
18312 ASC_SG_LIST_PER_Q) + 1;
18314 shost->sg_tablesize = ADV_MAX_SG_LIST;
18318 * The value of 'sg_tablesize' can not exceed the SCSI
18319 * mid-level driver definition of SG_ALL. SG_ALL also
18320 * must not be exceeded, because it is used to define the
18321 * size of the scatter-gather table in 'struct asc_sg_head'.
18323 if (shost->sg_tablesize > SG_ALL) {
18324 shost->sg_tablesize = SG_ALL;
18327 ASC_DBG1(1, "advansys_board_found: sg_tablesize: %d\n", shost->sg_tablesize);
18329 /* BIOS start address. */
18330 if (ASC_NARROW_BOARD(boardp)) {
18331 shost->base = ((ulong)
18332 AscGetChipBiosAddress(asc_dvc_varp->
18334 asc_dvc_varp->bus_type));
18337 * Fill-in BIOS board variables. The Wide BIOS saves
18338 * information in LRAM that is used by the driver.
18340 AdvReadWordLram(adv_dvc_varp->iop_base,
18341 BIOS_SIGNATURE, boardp->bios_signature);
18342 AdvReadWordLram(adv_dvc_varp->iop_base,
18343 BIOS_VERSION, boardp->bios_version);
18344 AdvReadWordLram(adv_dvc_varp->iop_base,
18345 BIOS_CODESEG, boardp->bios_codeseg);
18346 AdvReadWordLram(adv_dvc_varp->iop_base,
18347 BIOS_CODELEN, boardp->bios_codelen);
18350 "advansys_board_found: bios_signature 0x%x, bios_version 0x%x\n",
18351 boardp->bios_signature, boardp->bios_version);
18354 "advansys_board_found: bios_codeseg 0x%x, bios_codelen 0x%x\n",
18355 boardp->bios_codeseg, boardp->bios_codelen);
18358 * If the BIOS saved a valid signature, then fill in
18359 * the BIOS code segment base address.
18361 if (boardp->bios_signature == 0x55AA) {
18363 * Convert x86 realmode code segment to a linear
18364 * address by shifting left 4.
18366 shost->base = ((ulong)boardp->bios_codeseg << 4);
18373 * Register Board Resources - I/O Port, DMA, IRQ
18377 * Register I/O port range.
18379 * For Wide boards the I/O ports are not used to access
18380 * the board, but request the region anyway.
18382 * 'shost->n_io_port' is not referenced, because it may be truncated.
18385 "advansys_board_found: request_region port 0x%lx, len 0x%x\n",
18386 (ulong)shost->io_port, boardp->asc_n_io_port);
18387 if (request_region(shost->io_port, boardp->asc_n_io_port,
18388 "advansys") == NULL) {
18390 ("advansys_board_found: board %d: request_region() failed, port 0x%lx, len 0x%x\n",
18391 boardp->id, (ulong)shost->io_port, boardp->asc_n_io_port);
18392 #ifdef CONFIG_PROC_FS
18393 kfree(boardp->prtbuf);
18394 #endif /* CONFIG_PROC_FS */
18395 scsi_unregister(shost);
18400 /* Register DMA Channel for Narrow boards. */
18401 shost->dma_channel = NO_ISA_DMA; /* Default to no ISA DMA. */
18403 if (ASC_NARROW_BOARD(boardp)) {
18404 /* Register DMA channel for ISA bus. */
18405 if (asc_dvc_varp->bus_type & ASC_IS_ISA) {
18406 shost->dma_channel = asc_dvc_varp->cfg->isa_dma_channel;
18408 request_dma(shost->dma_channel, "advansys")) != 0) {
18410 ("advansys_board_found: board %d: request_dma() %d failed %d\n",
18411 boardp->id, shost->dma_channel, ret);
18412 release_region(shost->io_port,
18413 boardp->asc_n_io_port);
18414 #ifdef CONFIG_PROC_FS
18415 kfree(boardp->prtbuf);
18416 #endif /* CONFIG_PROC_FS */
18417 scsi_unregister(shost);
18421 AscEnableIsaDma(shost->dma_channel);
18424 #endif /* CONFIG_ISA */
18426 /* Register IRQ Number. */
18427 ASC_DBG1(2, "advansys_board_found: request_irq() %d\n", shost->irq);
18429 * If request_irq() fails with the IRQF_DISABLED flag set,
18430 * then try again without the IRQF_DISABLED flag set. This
18431 * allows IRQ sharing to work even with other drivers that
18432 * do not set the IRQF_DISABLED flag.
18434 * If IRQF_DISABLED is not set, then interrupts are enabled
18435 * before the driver interrupt function is called.
18437 if (((ret = request_irq(shost->irq, advansys_interrupt,
18438 IRQF_DISABLED | (share_irq ==
18441 0), "advansys", boardp)) != 0)
18444 request_irq(shost->irq, advansys_interrupt,
18445 (share_irq == TRUE ? IRQF_SHARED : 0),
18446 "advansys", boardp)) != 0)) {
18447 if (ret == -EBUSY) {
18449 ("advansys_board_found: board %d: request_irq(): IRQ 0x%x already in use.\n",
18450 boardp->id, shost->irq);
18451 } else if (ret == -EINVAL) {
18453 ("advansys_board_found: board %d: request_irq(): IRQ 0x%x not valid.\n",
18454 boardp->id, shost->irq);
18457 ("advansys_board_found: board %d: request_irq(): IRQ 0x%x failed with %d\n",
18458 boardp->id, shost->irq, ret);
18460 release_region(shost->io_port, boardp->asc_n_io_port);
18461 iounmap(boardp->ioremap_addr);
18462 if (shost->dma_channel != NO_ISA_DMA) {
18463 free_dma(shost->dma_channel);
18465 #ifdef CONFIG_PROC_FS
18466 kfree(boardp->prtbuf);
18467 #endif /* CONFIG_PROC_FS */
18468 scsi_unregister(shost);
18474 * Initialize board RISC chip and enable interrupts.
18476 if (ASC_NARROW_BOARD(boardp)) {
18477 ASC_DBG(2, "advansys_board_found: AscInitAsc1000Driver()\n");
18478 warn_code = AscInitAsc1000Driver(asc_dvc_varp);
18479 err_code = asc_dvc_varp->err_code;
18481 if (warn_code || err_code) {
18483 ("advansys_board_found: board %d error: init_state 0x%x, warn 0x%x, error 0x%x\n",
18485 asc_dvc_varp->init_state, warn_code, err_code);
18490 adv_req_t *reqp = NULL;
18494 * Allocate buffer carrier structures. The total size
18495 * is about 4 KB, so allocate all at once.
18497 carrp = (ADV_CARR_T *) kmalloc(ADV_CARRIER_BUFSIZE, GFP_ATOMIC);
18498 ASC_DBG1(1, "advansys_board_found: carrp 0x%lx\n", (ulong)carrp);
18500 if (carrp == NULL) {
18501 goto kmalloc_error;
18505 * Allocate up to 'max_host_qng' request structures for
18506 * the Wide board. The total size is about 16 KB, so
18507 * allocate all at once. If the allocation fails decrement
18510 for (req_cnt = adv_dvc_varp->max_host_qng;
18511 req_cnt > 0; req_cnt--) {
18513 reqp = (adv_req_t *)
18514 kmalloc(sizeof(adv_req_t) * req_cnt, GFP_ATOMIC);
18517 "advansys_board_found: reqp 0x%lx, req_cnt %d, bytes %lu\n",
18518 (ulong)reqp, req_cnt,
18519 (ulong)sizeof(adv_req_t) * req_cnt);
18521 if (reqp != NULL) {
18525 if (reqp == NULL) {
18526 goto kmalloc_error;
18530 * Allocate up to ADV_TOT_SG_BLOCK request structures for
18531 * the Wide board. Each structure is about 136 bytes.
18533 boardp->adv_sgblkp = NULL;
18534 for (sg_cnt = 0; sg_cnt < ADV_TOT_SG_BLOCK; sg_cnt++) {
18536 sgp = (adv_sgblk_t *)
18537 kmalloc(sizeof(adv_sgblk_t), GFP_ATOMIC);
18543 sgp->next_sgblkp = boardp->adv_sgblkp;
18544 boardp->adv_sgblkp = sgp;
18548 "advansys_board_found: sg_cnt %d * %u = %u bytes\n",
18549 sg_cnt, sizeof(adv_sgblk_t),
18550 (unsigned)(sizeof(adv_sgblk_t) * sg_cnt));
18553 * If no request structures or scatter-gather structures could
18554 * be allocated, then return an error. Otherwise continue with
18558 if (carrp == NULL) {
18560 ("advansys_board_found: board %d error: failed to kmalloc() carrier buffer.\n",
18562 err_code = ADV_ERROR;
18563 } else if (reqp == NULL) {
18566 ("advansys_board_found: board %d error: failed to kmalloc() adv_req_t buffer.\n",
18568 err_code = ADV_ERROR;
18569 } else if (boardp->adv_sgblkp == NULL) {
18573 ("advansys_board_found: board %d error: failed to kmalloc() adv_sgblk_t buffers.\n",
18575 err_code = ADV_ERROR;
18578 /* Save carrier buffer pointer. */
18579 boardp->orig_carrp = carrp;
18582 * Save original pointer for kfree() in case the
18583 * driver is built as a module and can be unloaded.
18585 boardp->orig_reqp = reqp;
18587 adv_dvc_varp->carrier_buf = carrp;
18590 * Point 'adv_reqp' to the request structures and
18591 * link them together.
18594 reqp[req_cnt].next_reqp = NULL;
18595 for (; req_cnt > 0; req_cnt--) {
18596 reqp[req_cnt - 1].next_reqp = &reqp[req_cnt];
18598 boardp->adv_reqp = &reqp[0];
18600 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
18602 "advansys_board_found: AdvInitAsc3550Driver()\n");
18603 warn_code = AdvInitAsc3550Driver(adv_dvc_varp);
18604 } else if (adv_dvc_varp->chip_type ==
18605 ADV_CHIP_ASC38C0800) {
18607 "advansys_board_found: AdvInitAsc38C0800Driver()\n");
18609 AdvInitAsc38C0800Driver(adv_dvc_varp);
18612 "advansys_board_found: AdvInitAsc38C1600Driver()\n");
18614 AdvInitAsc38C1600Driver(adv_dvc_varp);
18616 err_code = adv_dvc_varp->err_code;
18618 if (warn_code || err_code) {
18620 ("advansys_board_found: board %d error: warn 0x%x, error 0x%x\n",
18621 boardp->id, warn_code, err_code);
18626 if (err_code != 0) {
18627 release_region(shost->io_port, boardp->asc_n_io_port);
18628 if (ASC_WIDE_BOARD(boardp)) {
18629 iounmap(boardp->ioremap_addr);
18630 kfree(boardp->orig_carrp);
18631 boardp->orig_carrp = NULL;
18632 if (boardp->orig_reqp) {
18633 kfree(boardp->orig_reqp);
18634 boardp->orig_reqp = boardp->adv_reqp = NULL;
18636 while ((sgp = boardp->adv_sgblkp) != NULL) {
18637 boardp->adv_sgblkp = sgp->next_sgblkp;
18641 if (shost->dma_channel != NO_ISA_DMA) {
18642 free_dma(shost->dma_channel);
18644 #ifdef CONFIG_PROC_FS
18645 kfree(boardp->prtbuf);
18646 #endif /* CONFIG_PROC_FS */
18647 free_irq(shost->irq, boardp);
18648 scsi_unregister(shost);
18652 ASC_DBG_PRT_SCSI_HOST(2, shost);
18658 * advansys_detect()
18660 * Detect function for AdvanSys adapters.
18662 * Argument is a pointer to the host driver's scsi_hosts entry.
18664 * Return number of adapters found.
18666 * Note: Because this function is called during system initialization
18667 * it must not call SCSI mid-level functions including scsi_malloc()
18670 static int __init advansys_detect(struct scsi_host_template *tpnt)
18672 static int detect_called = ASC_FALSE;
18676 struct device *dev = NULL;
18678 int pci_init_search = 0;
18679 struct pci_dev *pci_devicep[ASC_NUM_BOARD_SUPPORTED];
18680 int pci_card_cnt_max = 0;
18681 int pci_card_cnt = 0;
18682 struct pci_dev *pdev = NULL;
18683 int pci_device_id_cnt = 0;
18684 unsigned int pci_device_id[ASC_PCI_DEVICE_ID_CNT] = {
18685 PCI_DEVICE_ID_ASP_1200A,
18686 PCI_DEVICE_ID_ASP_ABP940,
18687 PCI_DEVICE_ID_ASP_ABP940U,
18688 PCI_DEVICE_ID_ASP_ABP940UW,
18689 PCI_DEVICE_ID_38C0800_REV1,
18690 PCI_DEVICE_ID_38C1600_REV1
18692 #endif /* CONFIG_PCI */
18694 if (detect_called == ASC_FALSE) {
18695 detect_called = ASC_TRUE;
18698 ("AdvanSys SCSI: advansys_detect() multiple calls ignored\n");
18702 ASC_DBG(1, "advansys_detect: begin\n");
18704 asc_board_count = 0;
18707 * If I/O port probing has been modified, then verify and
18708 * clean-up the 'asc_ioport' list.
18710 if (asc_iopflag == ASC_TRUE) {
18711 for (ioport = 0; ioport < ASC_NUM_IOPORT_PROBE; ioport++) {
18712 ASC_DBG2(1, "advansys_detect: asc_ioport[%d] 0x%x\n",
18713 ioport, asc_ioport[ioport]);
18714 if (asc_ioport[ioport] != 0) {
18715 for (iop = 0; iop < ASC_IOADR_TABLE_MAX_IX;
18717 if (_asc_def_iop_base[iop] ==
18718 asc_ioport[ioport]) {
18722 if (iop == ASC_IOADR_TABLE_MAX_IX) {
18724 ("AdvanSys SCSI: specified I/O Port 0x%X is invalid\n",
18725 asc_ioport[ioport]);
18726 asc_ioport[ioport] = 0;
18733 for (bus = 0; bus < ASC_NUM_BUS; bus++) {
18735 ASC_DBG2(1, "advansys_detect: bus search type %d (%s)\n",
18736 bus, asc_bus_name[bus]);
18739 while (asc_board_count < ASC_NUM_BOARD_SUPPORTED) {
18741 ASC_DBG1(2, "advansys_detect: asc_board_count %d\n",
18744 switch (asc_bus[bus]) {
18748 if (asc_iopflag == ASC_FALSE) {
18750 AscSearchIOPortAddr(iop,
18754 * ISA and VL I/O port scanning has either been
18755 * eliminated or limited to selected ports on
18756 * the LILO command line, /etc/lilo.conf, or
18757 * by setting variables when the module was loaded.
18760 "advansys_detect: I/O port scanning modified\n");
18763 for (; ioport < ASC_NUM_IOPORT_PROBE;
18766 asc_ioport[ioport]) != 0) {
18772 "advansys_detect: probing I/O port 0x%x...\n",
18774 if (!request_region
18775 (iop, ASC_IOADR_GAP,
18778 ("AdvanSys SCSI: specified I/O Port 0x%X is busy\n",
18780 /* Don't try this I/O port twice. */
18781 asc_ioport[ioport] = 0;
18782 goto ioport_try_again;
18783 } else if (AscFindSignature(iop)
18786 ("AdvanSys SCSI: specified I/O Port 0x%X has no adapter\n",
18788 /* Don't try this I/O port twice. */
18789 release_region(iop,
18791 asc_ioport[ioport] = 0;
18792 goto ioport_try_again;
18795 * If this isn't an ISA board, then it must be
18796 * a VL board. If currently looking an ISA
18797 * board is being looked for then try for
18798 * another ISA board in 'asc_ioport'.
18800 if (asc_bus[bus] ==
18806 ASC_CHIP_VER_ISA_BIT)
18809 * Don't clear 'asc_ioport[ioport]'. Try
18810 * this board again for VL. Increment
18811 * 'ioport' past this board.
18817 goto ioport_try_again;
18821 * This board appears good, don't try the I/O port
18822 * again by clearing its value. Increment 'ioport'
18823 * for the next iteration.
18825 asc_ioport[ioport++] = 0;
18828 #endif /* CONFIG_ISA */
18833 iop = AscSearchIOPortAddr(iop, asc_bus[bus]);
18834 #endif /* CONFIG_ISA */
18839 if (pci_init_search == 0) {
18842 pci_init_search = 1;
18844 /* Find all PCI cards. */
18845 while (pci_device_id_cnt <
18846 ASC_PCI_DEVICE_ID_CNT) {
18849 (PCI_VENDOR_ID_ASP,
18851 [pci_device_id_cnt],
18853 pci_device_id_cnt++;
18855 if (pci_enable_device
18858 [pci_card_cnt_max++]
18865 * Sort PCI cards in ascending order by PCI Bus, Slot,
18866 * and Device Number.
18868 for (i = 0; i < pci_card_cnt_max - 1;
18871 j < pci_card_cnt_max;
18873 if ((pci_devicep[j]->
18904 if (pci_card_cnt == pci_card_cnt_max) {
18907 pdev = pci_devicep[pci_card_cnt];
18910 "advansys_detect: devfn %d, bus number %d\n",
18912 pdev->bus->number);
18913 iop = pci_resource_start(pdev, 0);
18915 "advansys_detect: vendorID %X, deviceID %X\n",
18919 "advansys_detect: iop %X, irqLine %d\n",
18925 #endif /* CONFIG_PCI */
18930 ("advansys_detect: unknown bus type: %d\n",
18934 ASC_DBG1(1, "advansys_detect: iop 0x%x\n", iop);
18937 * Adapter not found, try next bus type.
18943 advansys_board_found(iop, dev, asc_bus[bus]);
18947 ASC_DBG1(1, "advansys_detect: done: asc_board_count %d\n",
18949 return asc_board_count;
18953 * advansys_release()
18955 * Release resources allocated for a single AdvanSys adapter.
18957 static int advansys_release(struct Scsi_Host *shost)
18959 asc_board_t *boardp;
18961 ASC_DBG(1, "advansys_release: begin\n");
18962 boardp = ASC_BOARDP(shost);
18963 free_irq(shost->irq, boardp);
18964 if (shost->dma_channel != NO_ISA_DMA) {
18965 ASC_DBG(1, "advansys_release: free_dma()\n");
18966 free_dma(shost->dma_channel);
18968 release_region(shost->io_port, boardp->asc_n_io_port);
18969 if (ASC_WIDE_BOARD(boardp)) {
18970 adv_sgblk_t *sgp = NULL;
18972 iounmap(boardp->ioremap_addr);
18973 kfree(boardp->orig_carrp);
18974 boardp->orig_carrp = NULL;
18975 if (boardp->orig_reqp) {
18976 kfree(boardp->orig_reqp);
18977 boardp->orig_reqp = boardp->adv_reqp = NULL;
18979 while ((sgp = boardp->adv_sgblkp) != NULL) {
18980 boardp->adv_sgblkp = sgp->next_sgblkp;
18984 #ifdef CONFIG_PROC_FS
18985 ASC_ASSERT(boardp->prtbuf != NULL);
18986 kfree(boardp->prtbuf);
18987 #endif /* CONFIG_PROC_FS */
18988 scsi_unregister(shost);
18989 ASC_DBG(1, "advansys_release: end\n");
18994 /* PCI Devices supported by this driver */
18995 static struct pci_device_id advansys_pci_tbl[] __devinitdata = {
18996 {PCI_VENDOR_ID_ASP, PCI_DEVICE_ID_ASP_1200A,
18997 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
18998 {PCI_VENDOR_ID_ASP, PCI_DEVICE_ID_ASP_ABP940,
18999 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
19000 {PCI_VENDOR_ID_ASP, PCI_DEVICE_ID_ASP_ABP940U,
19001 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
19002 {PCI_VENDOR_ID_ASP, PCI_DEVICE_ID_ASP_ABP940UW,
19003 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
19004 {PCI_VENDOR_ID_ASP, PCI_DEVICE_ID_38C0800_REV1,
19005 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
19006 {PCI_VENDOR_ID_ASP, PCI_DEVICE_ID_38C1600_REV1,
19007 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
19011 MODULE_DEVICE_TABLE(pci, advansys_pci_tbl);
19012 #endif /* CONFIG_PCI */
19014 MODULE_LICENSE("GPL");