1 #define DRV_NAME "advansys"
2 #define ASC_VERSION "3.4" /* AdvanSys Driver Version */
5 * advansys.c - Linux Host Driver for AdvanSys SCSI Adapters
7 * Copyright (c) 1995-2000 Advanced System Products, Inc.
8 * Copyright (c) 2000-2001 ConnectCom Solutions, Inc.
9 * Copyright (c) 2007 Matthew Wilcox <matthew@wil.cx>
10 * All Rights Reserved.
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2 of the License, or
15 * (at your option) any later version.
19 * As of March 8, 2000 Advanced System Products, Inc. (AdvanSys)
20 * changed its name to ConnectCom Solutions, Inc.
21 * On June 18, 2001 Initio Corp. acquired ConnectCom's SCSI assets
24 #include <linux/module.h>
25 #include <linux/string.h>
26 #include <linux/kernel.h>
27 #include <linux/types.h>
28 #include <linux/ioport.h>
29 #include <linux/interrupt.h>
30 #include <linux/delay.h>
31 #include <linux/slab.h>
33 #include <linux/proc_fs.h>
34 #include <linux/init.h>
35 #include <linux/blkdev.h>
36 #include <linux/isa.h>
37 #include <linux/eisa.h>
38 #include <linux/pci.h>
39 #include <linux/spinlock.h>
40 #include <linux/dma-mapping.h>
43 #include <asm/system.h>
46 #include <scsi/scsi_cmnd.h>
47 #include <scsi/scsi_device.h>
48 #include <scsi/scsi_tcq.h>
49 #include <scsi/scsi.h>
50 #include <scsi/scsi_host.h>
54 * 1. Although all of the necessary command mapping places have the
55 * appropriate dma_map.. APIs, the driver still processes its internal
56 * queue using bus_to_virt() and virt_to_bus() which are illegal under
57 * the API. The entire queue processing structure will need to be
58 * altered to fix this.
59 * 2. Need to add memory mapping workaround. Test the memory mapping.
60 * If it doesn't work revert to I/O port access. Can a test be done
62 * 3. Handle an interrupt not working. Keep an interrupt counter in
63 * the interrupt handler. In the timeout function if the interrupt
64 * has not occurred then print a message and run in polled mode.
65 * 4. Need to add support for target mode commands, cf. CAM XPT.
66 * 5. check DMA mapping functions for failure
67 * 6. Use scsi_transport_spi
68 * 7. advansys_info is not safe against multiple simultaneous callers
69 * 8. Add module_param to override ISA/VLB ioport array
71 #warning this driver is still not properly converted to the DMA API
73 /* Enable driver /proc statistics. */
74 #define ADVANSYS_STATS
76 /* Enable driver tracing. */
82 * Any instance where a 32-bit long or pointer type is assumed
83 * for precision or HW defined structures, the following define
84 * types must be used. In Linux the char, short, and int types
85 * are all consistent at 8, 16, and 32 bits respectively. Pointers
86 * and long types are 64 bits on Alpha and UltraSPARC.
88 #define ASC_PADDR __u32 /* Physical/Bus address data type. */
89 #define ASC_VADDR __u32 /* Virtual address data type. */
90 #define ASC_DCNT __u32 /* Unsigned Data count type. */
91 #define ASC_SDCNT __s32 /* Signed Data count type. */
94 * These macros are used to convert a virtual address to a
95 * 32-bit value. This currently can be used on Linux Alpha
96 * which uses 64-bit virtual address but a 32-bit bus address.
97 * This is likely to break in the future, but doing this now
98 * will give us time to change the HW and FW to handle 64-bit
101 #define ASC_VADDR_TO_U32 virt_to_bus
102 #define ASC_U32_TO_VADDR bus_to_virt
104 typedef unsigned char uchar;
114 #define UW_ERR (uint)(0xFFFF)
115 #define isodd_word(val) ((((uint)val) & (uint)0x0001) != 0)
117 #define PCI_VENDOR_ID_ASP 0x10cd
118 #define PCI_DEVICE_ID_ASP_1200A 0x1100
119 #define PCI_DEVICE_ID_ASP_ABP940 0x1200
120 #define PCI_DEVICE_ID_ASP_ABP940U 0x1300
121 #define PCI_DEVICE_ID_ASP_ABP940UW 0x2300
122 #define PCI_DEVICE_ID_38C0800_REV1 0x2500
123 #define PCI_DEVICE_ID_38C1600_REV1 0x2700
126 * Enable CC_VERY_LONG_SG_LIST to support up to 64K element SG lists.
127 * The SRB structure will have to be changed and the ASC_SRB2SCSIQ()
128 * macro re-defined to be able to obtain a ASC_SCSI_Q pointer from the
131 #define CC_VERY_LONG_SG_LIST 0
132 #define ASC_SRB2SCSIQ(srb_ptr) (srb_ptr)
134 #define PortAddr unsigned short /* port address size */
135 #define inp(port) inb(port)
136 #define outp(port, byte) outb((byte), (port))
138 #define inpw(port) inw(port)
139 #define outpw(port, word) outw((word), (port))
141 #define ASC_MAX_SG_QUEUE 7
142 #define ASC_MAX_SG_LIST 255
144 #define ASC_CS_TYPE unsigned short
146 #define ASC_IS_ISA (0x0001)
147 #define ASC_IS_ISAPNP (0x0081)
148 #define ASC_IS_EISA (0x0002)
149 #define ASC_IS_PCI (0x0004)
150 #define ASC_IS_PCI_ULTRA (0x0104)
151 #define ASC_IS_PCMCIA (0x0008)
152 #define ASC_IS_MCA (0x0020)
153 #define ASC_IS_VL (0x0040)
154 #define ASC_IS_WIDESCSI_16 (0x0100)
155 #define ASC_IS_WIDESCSI_32 (0x0200)
156 #define ASC_IS_BIG_ENDIAN (0x8000)
158 #define ASC_CHIP_MIN_VER_VL (0x01)
159 #define ASC_CHIP_MAX_VER_VL (0x07)
160 #define ASC_CHIP_MIN_VER_PCI (0x09)
161 #define ASC_CHIP_MAX_VER_PCI (0x0F)
162 #define ASC_CHIP_VER_PCI_BIT (0x08)
163 #define ASC_CHIP_MIN_VER_ISA (0x11)
164 #define ASC_CHIP_MIN_VER_ISA_PNP (0x21)
165 #define ASC_CHIP_MAX_VER_ISA (0x27)
166 #define ASC_CHIP_VER_ISA_BIT (0x30)
167 #define ASC_CHIP_VER_ISAPNP_BIT (0x20)
168 #define ASC_CHIP_VER_ASYN_BUG (0x21)
169 #define ASC_CHIP_VER_PCI 0x08
170 #define ASC_CHIP_VER_PCI_ULTRA_3150 (ASC_CHIP_VER_PCI | 0x02)
171 #define ASC_CHIP_VER_PCI_ULTRA_3050 (ASC_CHIP_VER_PCI | 0x03)
172 #define ASC_CHIP_MIN_VER_EISA (0x41)
173 #define ASC_CHIP_MAX_VER_EISA (0x47)
174 #define ASC_CHIP_VER_EISA_BIT (0x40)
175 #define ASC_CHIP_LATEST_VER_EISA ((ASC_CHIP_MIN_VER_EISA - 1) + 3)
176 #define ASC_MAX_VL_DMA_COUNT (0x07FFFFFFL)
177 #define ASC_MAX_PCI_DMA_COUNT (0xFFFFFFFFL)
178 #define ASC_MAX_ISA_DMA_COUNT (0x00FFFFFFL)
180 #define ASC_SCSI_ID_BITS 3
181 #define ASC_SCSI_TIX_TYPE uchar
182 #define ASC_ALL_DEVICE_BIT_SET 0xFF
183 #define ASC_SCSI_BIT_ID_TYPE uchar
184 #define ASC_MAX_TID 7
185 #define ASC_MAX_LUN 7
186 #define ASC_SCSI_WIDTH_BIT_SET 0xFF
187 #define ASC_MAX_SENSE_LEN 32
188 #define ASC_MIN_SENSE_LEN 14
189 #define ASC_SCSI_RESET_HOLD_TIME_US 60
192 * Narrow boards only support 12-byte commands, while wide boards
193 * extend to 16-byte commands.
195 #define ASC_MAX_CDB_LEN 12
196 #define ADV_MAX_CDB_LEN 16
198 #define MS_SDTR_LEN 0x03
199 #define MS_WDTR_LEN 0x02
201 #define ASC_SG_LIST_PER_Q 7
203 #define QS_READY 0x01
204 #define QS_DISC1 0x02
205 #define QS_DISC2 0x04
207 #define QS_ABORTED 0x40
209 #define QC_NO_CALLBACK 0x01
210 #define QC_SG_SWAP_QUEUE 0x02
211 #define QC_SG_HEAD 0x04
212 #define QC_DATA_IN 0x08
213 #define QC_DATA_OUT 0x10
214 #define QC_URGENT 0x20
215 #define QC_MSG_OUT 0x40
216 #define QC_REQ_SENSE 0x80
217 #define QCSG_SG_XFER_LIST 0x02
218 #define QCSG_SG_XFER_MORE 0x04
219 #define QCSG_SG_XFER_END 0x08
220 #define QD_IN_PROGRESS 0x00
221 #define QD_NO_ERROR 0x01
222 #define QD_ABORTED_BY_HOST 0x02
223 #define QD_WITH_ERROR 0x04
224 #define QD_INVALID_REQUEST 0x80
225 #define QD_INVALID_HOST_NUM 0x81
226 #define QD_INVALID_DEVICE 0x82
227 #define QD_ERR_INTERNAL 0xFF
228 #define QHSTA_NO_ERROR 0x00
229 #define QHSTA_M_SEL_TIMEOUT 0x11
230 #define QHSTA_M_DATA_OVER_RUN 0x12
231 #define QHSTA_M_DATA_UNDER_RUN 0x12
232 #define QHSTA_M_UNEXPECTED_BUS_FREE 0x13
233 #define QHSTA_M_BAD_BUS_PHASE_SEQ 0x14
234 #define QHSTA_D_QDONE_SG_LIST_CORRUPTED 0x21
235 #define QHSTA_D_ASC_DVC_ERROR_CODE_SET 0x22
236 #define QHSTA_D_HOST_ABORT_FAILED 0x23
237 #define QHSTA_D_EXE_SCSI_Q_FAILED 0x24
238 #define QHSTA_D_EXE_SCSI_Q_BUSY_TIMEOUT 0x25
239 #define QHSTA_D_ASPI_NO_BUF_POOL 0x26
240 #define QHSTA_M_WTM_TIMEOUT 0x41
241 #define QHSTA_M_BAD_CMPL_STATUS_IN 0x42
242 #define QHSTA_M_NO_AUTO_REQ_SENSE 0x43
243 #define QHSTA_M_AUTO_REQ_SENSE_FAIL 0x44
244 #define QHSTA_M_TARGET_STATUS_BUSY 0x45
245 #define QHSTA_M_BAD_TAG_CODE 0x46
246 #define QHSTA_M_BAD_QUEUE_FULL_OR_BUSY 0x47
247 #define QHSTA_M_HUNG_REQ_SCSI_BUS_RESET 0x48
248 #define QHSTA_D_LRAM_CMP_ERROR 0x81
249 #define QHSTA_M_MICRO_CODE_ERROR_HALT 0xA1
250 #define ASC_FLAG_SCSIQ_REQ 0x01
251 #define ASC_FLAG_BIOS_SCSIQ_REQ 0x02
252 #define ASC_FLAG_BIOS_ASYNC_IO 0x04
253 #define ASC_FLAG_SRB_LINEAR_ADDR 0x08
254 #define ASC_FLAG_WIN16 0x10
255 #define ASC_FLAG_WIN32 0x20
256 #define ASC_FLAG_ISA_OVER_16MB 0x40
257 #define ASC_FLAG_DOS_VM_CALLBACK 0x80
258 #define ASC_TAG_FLAG_EXTRA_BYTES 0x10
259 #define ASC_TAG_FLAG_DISABLE_DISCONNECT 0x04
260 #define ASC_TAG_FLAG_DISABLE_ASYN_USE_SYN_FIX 0x08
261 #define ASC_TAG_FLAG_DISABLE_CHK_COND_INT_HOST 0x40
262 #define ASC_SCSIQ_CPY_BEG 4
263 #define ASC_SCSIQ_SGHD_CPY_BEG 2
264 #define ASC_SCSIQ_B_FWD 0
265 #define ASC_SCSIQ_B_BWD 1
266 #define ASC_SCSIQ_B_STATUS 2
267 #define ASC_SCSIQ_B_QNO 3
268 #define ASC_SCSIQ_B_CNTL 4
269 #define ASC_SCSIQ_B_SG_QUEUE_CNT 5
270 #define ASC_SCSIQ_D_DATA_ADDR 8
271 #define ASC_SCSIQ_D_DATA_CNT 12
272 #define ASC_SCSIQ_B_SENSE_LEN 20
273 #define ASC_SCSIQ_DONE_INFO_BEG 22
274 #define ASC_SCSIQ_D_SRBPTR 22
275 #define ASC_SCSIQ_B_TARGET_IX 26
276 #define ASC_SCSIQ_B_CDB_LEN 28
277 #define ASC_SCSIQ_B_TAG_CODE 29
278 #define ASC_SCSIQ_W_VM_ID 30
279 #define ASC_SCSIQ_DONE_STATUS 32
280 #define ASC_SCSIQ_HOST_STATUS 33
281 #define ASC_SCSIQ_SCSI_STATUS 34
282 #define ASC_SCSIQ_CDB_BEG 36
283 #define ASC_SCSIQ_DW_REMAIN_XFER_ADDR 56
284 #define ASC_SCSIQ_DW_REMAIN_XFER_CNT 60
285 #define ASC_SCSIQ_B_FIRST_SG_WK_QP 48
286 #define ASC_SCSIQ_B_SG_WK_QP 49
287 #define ASC_SCSIQ_B_SG_WK_IX 50
288 #define ASC_SCSIQ_W_ALT_DC1 52
289 #define ASC_SCSIQ_B_LIST_CNT 6
290 #define ASC_SCSIQ_B_CUR_LIST_CNT 7
291 #define ASC_SGQ_B_SG_CNTL 4
292 #define ASC_SGQ_B_SG_HEAD_QP 5
293 #define ASC_SGQ_B_SG_LIST_CNT 6
294 #define ASC_SGQ_B_SG_CUR_LIST_CNT 7
295 #define ASC_SGQ_LIST_BEG 8
296 #define ASC_DEF_SCSI1_QNG 4
297 #define ASC_MAX_SCSI1_QNG 4
298 #define ASC_DEF_SCSI2_QNG 16
299 #define ASC_MAX_SCSI2_QNG 32
300 #define ASC_TAG_CODE_MASK 0x23
301 #define ASC_STOP_REQ_RISC_STOP 0x01
302 #define ASC_STOP_ACK_RISC_STOP 0x03
303 #define ASC_STOP_CLEAN_UP_BUSY_Q 0x10
304 #define ASC_STOP_CLEAN_UP_DISC_Q 0x20
305 #define ASC_STOP_HOST_REQ_RISC_HALT 0x40
306 #define ASC_TIDLUN_TO_IX(tid, lun) (ASC_SCSI_TIX_TYPE)((tid) + ((lun)<<ASC_SCSI_ID_BITS))
307 #define ASC_TID_TO_TARGET_ID(tid) (ASC_SCSI_BIT_ID_TYPE)(0x01 << (tid))
308 #define ASC_TIX_TO_TARGET_ID(tix) (0x01 << ((tix) & ASC_MAX_TID))
309 #define ASC_TIX_TO_TID(tix) ((tix) & ASC_MAX_TID)
310 #define ASC_TID_TO_TIX(tid) ((tid) & ASC_MAX_TID)
311 #define ASC_TIX_TO_LUN(tix) (((tix) >> ASC_SCSI_ID_BITS) & ASC_MAX_LUN)
312 #define ASC_QNO_TO_QADDR(q_no) ((ASC_QADR_BEG)+((int)(q_no) << 6))
314 typedef struct asc_scsiq_1 {
323 ASC_PADDR sense_addr;
328 typedef struct asc_scsiq_2 {
337 typedef struct asc_scsiq_3 {
344 typedef struct asc_scsiq_4 {
345 uchar cdb[ASC_MAX_CDB_LEN];
346 uchar y_first_sg_list_qp;
347 uchar y_working_sg_qp;
348 uchar y_working_sg_ix;
351 ushort x_reconnect_rtn;
352 ASC_PADDR x_saved_data_addr;
353 ASC_DCNT x_saved_data_cnt;
356 typedef struct asc_q_done_info {
365 ASC_DCNT remain_bytes;
368 typedef struct asc_sg_list {
373 typedef struct asc_sg_head {
376 ushort entry_to_copy;
378 ASC_SG_LIST sg_list[0];
381 typedef struct asc_scsi_q {
385 ASC_SG_HEAD *sg_head;
386 ushort remain_sg_entry_cnt;
387 ushort next_sg_index;
390 typedef struct asc_scsi_req_q {
394 ASC_SG_HEAD *sg_head;
397 uchar cdb[ASC_MAX_CDB_LEN];
398 uchar sense[ASC_MIN_SENSE_LEN];
401 typedef struct asc_scsi_bios_req_q {
405 ASC_SG_HEAD *sg_head;
408 uchar cdb[ASC_MAX_CDB_LEN];
409 uchar sense[ASC_MIN_SENSE_LEN];
410 } ASC_SCSI_BIOS_REQ_Q;
412 typedef struct asc_risc_q {
421 typedef struct asc_sg_list_q {
427 uchar sg_cur_list_cnt;
430 typedef struct asc_risc_sg_list_q {
434 ASC_SG_LIST sg_list[7];
435 } ASC_RISC_SG_LIST_Q;
437 #define ASCQ_ERR_Q_STATUS 0x0D
438 #define ASCQ_ERR_CUR_QNG 0x17
439 #define ASCQ_ERR_SG_Q_LINKS 0x18
440 #define ASCQ_ERR_ISR_RE_ENTRY 0x1A
441 #define ASCQ_ERR_CRITICAL_RE_ENTRY 0x1B
442 #define ASCQ_ERR_ISR_ON_CRITICAL 0x1C
445 * Warning code values are set in ASC_DVC_VAR 'warn_code'.
447 #define ASC_WARN_NO_ERROR 0x0000
448 #define ASC_WARN_IO_PORT_ROTATE 0x0001
449 #define ASC_WARN_EEPROM_CHKSUM 0x0002
450 #define ASC_WARN_IRQ_MODIFIED 0x0004
451 #define ASC_WARN_AUTO_CONFIG 0x0008
452 #define ASC_WARN_CMD_QNG_CONFLICT 0x0010
453 #define ASC_WARN_EEPROM_RECOVER 0x0020
454 #define ASC_WARN_CFG_MSW_RECOVER 0x0040
457 * Error code values are set in {ASC/ADV}_DVC_VAR 'err_code'.
459 #define ASC_IERR_NO_CARRIER 0x0001 /* No more carrier memory */
460 #define ASC_IERR_MCODE_CHKSUM 0x0002 /* micro code check sum error */
461 #define ASC_IERR_SET_PC_ADDR 0x0004
462 #define ASC_IERR_START_STOP_CHIP 0x0008 /* start/stop chip failed */
463 #define ASC_IERR_ILLEGAL_CONNECTION 0x0010 /* Illegal cable connection */
464 #define ASC_IERR_SINGLE_END_DEVICE 0x0020 /* SE device on DIFF bus */
465 #define ASC_IERR_REVERSED_CABLE 0x0040 /* Narrow flat cable reversed */
466 #define ASC_IERR_SET_SCSI_ID 0x0080 /* set SCSI ID failed */
467 #define ASC_IERR_HVD_DEVICE 0x0100 /* HVD device on LVD port */
468 #define ASC_IERR_BAD_SIGNATURE 0x0200 /* signature not found */
469 #define ASC_IERR_NO_BUS_TYPE 0x0400
470 #define ASC_IERR_BIST_PRE_TEST 0x0800 /* BIST pre-test error */
471 #define ASC_IERR_BIST_RAM_TEST 0x1000 /* BIST RAM test error */
472 #define ASC_IERR_BAD_CHIPTYPE 0x2000 /* Invalid chip_type setting */
474 #define ASC_DEF_MAX_TOTAL_QNG (0xF0)
475 #define ASC_MIN_TAG_Q_PER_DVC (0x04)
476 #define ASC_MIN_FREE_Q (0x02)
477 #define ASC_MIN_TOTAL_QNG ((ASC_MAX_SG_QUEUE)+(ASC_MIN_FREE_Q))
478 #define ASC_MAX_TOTAL_QNG 240
479 #define ASC_MAX_PCI_ULTRA_INRAM_TOTAL_QNG 16
480 #define ASC_MAX_PCI_ULTRA_INRAM_TAG_QNG 8
481 #define ASC_MAX_PCI_INRAM_TOTAL_QNG 20
482 #define ASC_MAX_INRAM_TAG_QNG 16
483 #define ASC_IOADR_GAP 0x10
484 #define ASC_SYN_MAX_OFFSET 0x0F
485 #define ASC_DEF_SDTR_OFFSET 0x0F
486 #define ASC_SDTR_ULTRA_PCI_10MB_INDEX 0x02
487 #define ASYN_SDTR_DATA_FIX_PCI_REV_AB 0x41
489 /* The narrow chip only supports a limited selection of transfer rates.
490 * These are encoded in the range 0..7 or 0..15 depending whether the chip
491 * is Ultra-capable or not. These tables let us convert from one to the other.
493 static const unsigned char asc_syn_xfer_period[8] = {
494 25, 30, 35, 40, 50, 60, 70, 85
497 static const unsigned char asc_syn_ultra_xfer_period[16] = {
498 12, 19, 25, 32, 38, 44, 50, 57, 63, 69, 75, 82, 88, 94, 100, 107
501 typedef struct ext_msg {
507 uchar sdtr_xfer_period;
508 uchar sdtr_req_ack_offset;
523 #define xfer_period u_ext_msg.sdtr.sdtr_xfer_period
524 #define req_ack_offset u_ext_msg.sdtr.sdtr_req_ack_offset
525 #define wdtr_width u_ext_msg.wdtr.wdtr_width
526 #define mdp_b3 u_ext_msg.mdp_b3
527 #define mdp_b2 u_ext_msg.mdp_b2
528 #define mdp_b1 u_ext_msg.mdp_b1
529 #define mdp_b0 u_ext_msg.mdp_b0
531 typedef struct asc_dvc_cfg {
532 ASC_SCSI_BIT_ID_TYPE can_tagged_qng;
533 ASC_SCSI_BIT_ID_TYPE cmd_qng_enabled;
534 ASC_SCSI_BIT_ID_TYPE disc_enable;
535 ASC_SCSI_BIT_ID_TYPE sdtr_enable;
538 uchar isa_dma_channel;
541 ushort mcode_version;
542 uchar max_tag_qng[ASC_MAX_TID + 1];
544 uchar sdtr_period_offset[ASC_MAX_TID + 1];
545 uchar adapter_info[6];
548 #define ASC_DEF_DVC_CNTL 0xFFFF
549 #define ASC_DEF_CHIP_SCSI_ID 7
550 #define ASC_DEF_ISA_DMA_SPEED 4
551 #define ASC_INIT_STATE_BEG_GET_CFG 0x0001
552 #define ASC_INIT_STATE_END_GET_CFG 0x0002
553 #define ASC_INIT_STATE_BEG_SET_CFG 0x0004
554 #define ASC_INIT_STATE_END_SET_CFG 0x0008
555 #define ASC_INIT_STATE_BEG_LOAD_MC 0x0010
556 #define ASC_INIT_STATE_END_LOAD_MC 0x0020
557 #define ASC_INIT_STATE_BEG_INQUIRY 0x0040
558 #define ASC_INIT_STATE_END_INQUIRY 0x0080
559 #define ASC_INIT_RESET_SCSI_DONE 0x0100
560 #define ASC_INIT_STATE_WITHOUT_EEP 0x8000
561 #define ASC_BUG_FIX_IF_NOT_DWB 0x0001
562 #define ASC_BUG_FIX_ASYN_USE_SYN 0x0002
563 #define ASC_MIN_TAGGED_CMD 7
564 #define ASC_MAX_SCSI_RESET_WAIT 30
566 struct asc_dvc_var; /* Forward Declaration. */
568 typedef struct asc_dvc_var {
574 ASC_SCSI_BIT_ID_TYPE init_sdtr;
575 ASC_SCSI_BIT_ID_TYPE sdtr_done;
576 ASC_SCSI_BIT_ID_TYPE use_tagged_qng;
577 ASC_SCSI_BIT_ID_TYPE unit_not_ready;
578 ASC_SCSI_BIT_ID_TYPE queue_full_or_busy;
579 ASC_SCSI_BIT_ID_TYPE start_motor;
580 uchar scsi_reset_wait;
585 uchar in_critical_cnt;
586 uchar last_q_shortage;
588 uchar cur_dvc_qng[ASC_MAX_TID + 1];
589 uchar max_dvc_qng[ASC_MAX_TID + 1];
590 ASC_SCSI_Q *scsiq_busy_head[ASC_MAX_TID + 1];
591 ASC_SCSI_Q *scsiq_busy_tail[ASC_MAX_TID + 1];
592 const uchar *sdtr_period_tbl;
594 ASC_SCSI_BIT_ID_TYPE pci_fix_asyn_xfer_always;
597 uchar dos_int13_table[ASC_MAX_TID + 1];
598 ASC_DCNT max_dma_count;
599 ASC_SCSI_BIT_ID_TYPE no_scam;
600 ASC_SCSI_BIT_ID_TYPE pci_fix_asyn_xfer;
601 uchar min_sdtr_index;
602 uchar max_sdtr_index;
603 struct asc_board *drv_ptr;
607 typedef struct asc_dvc_inq_info {
608 uchar type[ASC_MAX_TID + 1][ASC_MAX_LUN + 1];
611 typedef struct asc_cap_info {
616 typedef struct asc_cap_info_array {
617 ASC_CAP_INFO cap_info[ASC_MAX_TID + 1][ASC_MAX_LUN + 1];
618 } ASC_CAP_INFO_ARRAY;
620 #define ASC_MCNTL_NO_SEL_TIMEOUT (ushort)0x0001
621 #define ASC_MCNTL_NULL_TARGET (ushort)0x0002
622 #define ASC_CNTL_INITIATOR (ushort)0x0001
623 #define ASC_CNTL_BIOS_GT_1GB (ushort)0x0002
624 #define ASC_CNTL_BIOS_GT_2_DISK (ushort)0x0004
625 #define ASC_CNTL_BIOS_REMOVABLE (ushort)0x0008
626 #define ASC_CNTL_NO_SCAM (ushort)0x0010
627 #define ASC_CNTL_INT_MULTI_Q (ushort)0x0080
628 #define ASC_CNTL_NO_LUN_SUPPORT (ushort)0x0040
629 #define ASC_CNTL_NO_VERIFY_COPY (ushort)0x0100
630 #define ASC_CNTL_RESET_SCSI (ushort)0x0200
631 #define ASC_CNTL_INIT_INQUIRY (ushort)0x0400
632 #define ASC_CNTL_INIT_VERBOSE (ushort)0x0800
633 #define ASC_CNTL_SCSI_PARITY (ushort)0x1000
634 #define ASC_CNTL_BURST_MODE (ushort)0x2000
635 #define ASC_CNTL_SDTR_ENABLE_ULTRA (ushort)0x4000
636 #define ASC_EEP_DVC_CFG_BEG_VL 2
637 #define ASC_EEP_MAX_DVC_ADDR_VL 15
638 #define ASC_EEP_DVC_CFG_BEG 32
639 #define ASC_EEP_MAX_DVC_ADDR 45
640 #define ASC_EEP_MAX_RETRY 20
643 * These macros keep the chip SCSI id and ISA DMA speed
644 * bitfields in board order. C bitfields aren't portable
645 * between big and little-endian platforms so they are
649 #define ASC_EEP_GET_CHIP_ID(cfg) ((cfg)->id_speed & 0x0f)
650 #define ASC_EEP_GET_DMA_SPD(cfg) (((cfg)->id_speed & 0xf0) >> 4)
651 #define ASC_EEP_SET_CHIP_ID(cfg, sid) \
652 ((cfg)->id_speed = ((cfg)->id_speed & 0xf0) | ((sid) & ASC_MAX_TID))
653 #define ASC_EEP_SET_DMA_SPD(cfg, spd) \
654 ((cfg)->id_speed = ((cfg)->id_speed & 0x0f) | ((spd) & 0x0f) << 4)
656 typedef struct asceep_config {
668 uchar id_speed; /* low order 4 bits is chip scsi id */
669 /* high order 4 bits is isa dma speed */
670 uchar dos_int13_table[ASC_MAX_TID + 1];
671 uchar adapter_info[6];
676 #define ASC_EEP_CMD_READ 0x80
677 #define ASC_EEP_CMD_WRITE 0x40
678 #define ASC_EEP_CMD_WRITE_ABLE 0x30
679 #define ASC_EEP_CMD_WRITE_DISABLE 0x00
680 #define ASC_OVERRUN_BSIZE 0x00000048UL
681 #define ASCV_MSGOUT_BEG 0x0000
682 #define ASCV_MSGOUT_SDTR_PERIOD (ASCV_MSGOUT_BEG+3)
683 #define ASCV_MSGOUT_SDTR_OFFSET (ASCV_MSGOUT_BEG+4)
684 #define ASCV_BREAK_SAVED_CODE (ushort)0x0006
685 #define ASCV_MSGIN_BEG (ASCV_MSGOUT_BEG+8)
686 #define ASCV_MSGIN_SDTR_PERIOD (ASCV_MSGIN_BEG+3)
687 #define ASCV_MSGIN_SDTR_OFFSET (ASCV_MSGIN_BEG+4)
688 #define ASCV_SDTR_DATA_BEG (ASCV_MSGIN_BEG+8)
689 #define ASCV_SDTR_DONE_BEG (ASCV_SDTR_DATA_BEG+8)
690 #define ASCV_MAX_DVC_QNG_BEG (ushort)0x0020
691 #define ASCV_BREAK_ADDR (ushort)0x0028
692 #define ASCV_BREAK_NOTIFY_COUNT (ushort)0x002A
693 #define ASCV_BREAK_CONTROL (ushort)0x002C
694 #define ASCV_BREAK_HIT_COUNT (ushort)0x002E
696 #define ASCV_ASCDVC_ERR_CODE_W (ushort)0x0030
697 #define ASCV_MCODE_CHKSUM_W (ushort)0x0032
698 #define ASCV_MCODE_SIZE_W (ushort)0x0034
699 #define ASCV_STOP_CODE_B (ushort)0x0036
700 #define ASCV_DVC_ERR_CODE_B (ushort)0x0037
701 #define ASCV_OVERRUN_PADDR_D (ushort)0x0038
702 #define ASCV_OVERRUN_BSIZE_D (ushort)0x003C
703 #define ASCV_HALTCODE_W (ushort)0x0040
704 #define ASCV_CHKSUM_W (ushort)0x0042
705 #define ASCV_MC_DATE_W (ushort)0x0044
706 #define ASCV_MC_VER_W (ushort)0x0046
707 #define ASCV_NEXTRDY_B (ushort)0x0048
708 #define ASCV_DONENEXT_B (ushort)0x0049
709 #define ASCV_USE_TAGGED_QNG_B (ushort)0x004A
710 #define ASCV_SCSIBUSY_B (ushort)0x004B
711 #define ASCV_Q_DONE_IN_PROGRESS_B (ushort)0x004C
712 #define ASCV_CURCDB_B (ushort)0x004D
713 #define ASCV_RCLUN_B (ushort)0x004E
714 #define ASCV_BUSY_QHEAD_B (ushort)0x004F
715 #define ASCV_DISC1_QHEAD_B (ushort)0x0050
716 #define ASCV_DISC_ENABLE_B (ushort)0x0052
717 #define ASCV_CAN_TAGGED_QNG_B (ushort)0x0053
718 #define ASCV_HOSTSCSI_ID_B (ushort)0x0055
719 #define ASCV_MCODE_CNTL_B (ushort)0x0056
720 #define ASCV_NULL_TARGET_B (ushort)0x0057
721 #define ASCV_FREE_Q_HEAD_W (ushort)0x0058
722 #define ASCV_DONE_Q_TAIL_W (ushort)0x005A
723 #define ASCV_FREE_Q_HEAD_B (ushort)(ASCV_FREE_Q_HEAD_W+1)
724 #define ASCV_DONE_Q_TAIL_B (ushort)(ASCV_DONE_Q_TAIL_W+1)
725 #define ASCV_HOST_FLAG_B (ushort)0x005D
726 #define ASCV_TOTAL_READY_Q_B (ushort)0x0064
727 #define ASCV_VER_SERIAL_B (ushort)0x0065
728 #define ASCV_HALTCODE_SAVED_W (ushort)0x0066
729 #define ASCV_WTM_FLAG_B (ushort)0x0068
730 #define ASCV_RISC_FLAG_B (ushort)0x006A
731 #define ASCV_REQ_SG_LIST_QP (ushort)0x006B
732 #define ASC_HOST_FLAG_IN_ISR 0x01
733 #define ASC_HOST_FLAG_ACK_INT 0x02
734 #define ASC_RISC_FLAG_GEN_INT 0x01
735 #define ASC_RISC_FLAG_REQ_SG_LIST 0x02
736 #define IOP_CTRL (0x0F)
737 #define IOP_STATUS (0x0E)
738 #define IOP_INT_ACK IOP_STATUS
739 #define IOP_REG_IFC (0x0D)
740 #define IOP_SYN_OFFSET (0x0B)
741 #define IOP_EXTRA_CONTROL (0x0D)
742 #define IOP_REG_PC (0x0C)
743 #define IOP_RAM_ADDR (0x0A)
744 #define IOP_RAM_DATA (0x08)
745 #define IOP_EEP_DATA (0x06)
746 #define IOP_EEP_CMD (0x07)
747 #define IOP_VERSION (0x03)
748 #define IOP_CONFIG_HIGH (0x04)
749 #define IOP_CONFIG_LOW (0x02)
750 #define IOP_SIG_BYTE (0x01)
751 #define IOP_SIG_WORD (0x00)
752 #define IOP_REG_DC1 (0x0E)
753 #define IOP_REG_DC0 (0x0C)
754 #define IOP_REG_SB (0x0B)
755 #define IOP_REG_DA1 (0x0A)
756 #define IOP_REG_DA0 (0x08)
757 #define IOP_REG_SC (0x09)
758 #define IOP_DMA_SPEED (0x07)
759 #define IOP_REG_FLAG (0x07)
760 #define IOP_FIFO_H (0x06)
761 #define IOP_FIFO_L (0x04)
762 #define IOP_REG_ID (0x05)
763 #define IOP_REG_QP (0x03)
764 #define IOP_REG_IH (0x02)
765 #define IOP_REG_IX (0x01)
766 #define IOP_REG_AX (0x00)
767 #define IFC_REG_LOCK (0x00)
768 #define IFC_REG_UNLOCK (0x09)
769 #define IFC_WR_EN_FILTER (0x10)
770 #define IFC_RD_NO_EEPROM (0x10)
771 #define IFC_SLEW_RATE (0x20)
772 #define IFC_ACT_NEG (0x40)
773 #define IFC_INP_FILTER (0x80)
774 #define IFC_INIT_DEFAULT (IFC_ACT_NEG | IFC_REG_UNLOCK)
775 #define SC_SEL (uchar)(0x80)
776 #define SC_BSY (uchar)(0x40)
777 #define SC_ACK (uchar)(0x20)
778 #define SC_REQ (uchar)(0x10)
779 #define SC_ATN (uchar)(0x08)
780 #define SC_IO (uchar)(0x04)
781 #define SC_CD (uchar)(0x02)
782 #define SC_MSG (uchar)(0x01)
783 #define SEC_SCSI_CTL (uchar)(0x80)
784 #define SEC_ACTIVE_NEGATE (uchar)(0x40)
785 #define SEC_SLEW_RATE (uchar)(0x20)
786 #define SEC_ENABLE_FILTER (uchar)(0x10)
787 #define ASC_HALT_EXTMSG_IN (ushort)0x8000
788 #define ASC_HALT_CHK_CONDITION (ushort)0x8100
789 #define ASC_HALT_SS_QUEUE_FULL (ushort)0x8200
790 #define ASC_HALT_DISABLE_ASYN_USE_SYN_FIX (ushort)0x8300
791 #define ASC_HALT_ENABLE_ASYN_USE_SYN_FIX (ushort)0x8400
792 #define ASC_HALT_SDTR_REJECTED (ushort)0x4000
793 #define ASC_HALT_HOST_COPY_SG_LIST_TO_RISC ( ushort )0x2000
794 #define ASC_MAX_QNO 0xF8
795 #define ASC_DATA_SEC_BEG (ushort)0x0080
796 #define ASC_DATA_SEC_END (ushort)0x0080
797 #define ASC_CODE_SEC_BEG (ushort)0x0080
798 #define ASC_CODE_SEC_END (ushort)0x0080
799 #define ASC_QADR_BEG (0x4000)
800 #define ASC_QADR_USED (ushort)(ASC_MAX_QNO * 64)
801 #define ASC_QADR_END (ushort)0x7FFF
802 #define ASC_QLAST_ADR (ushort)0x7FC0
803 #define ASC_QBLK_SIZE 0x40
804 #define ASC_BIOS_DATA_QBEG 0xF8
805 #define ASC_MIN_ACTIVE_QNO 0x01
806 #define ASC_QLINK_END 0xFF
807 #define ASC_EEPROM_WORDS 0x10
808 #define ASC_MAX_MGS_LEN 0x10
809 #define ASC_BIOS_ADDR_DEF 0xDC00
810 #define ASC_BIOS_SIZE 0x3800
811 #define ASC_BIOS_RAM_OFF 0x3800
812 #define ASC_BIOS_RAM_SIZE 0x800
813 #define ASC_BIOS_MIN_ADDR 0xC000
814 #define ASC_BIOS_MAX_ADDR 0xEC00
815 #define ASC_BIOS_BANK_SIZE 0x0400
816 #define ASC_MCODE_START_ADDR 0x0080
817 #define ASC_CFG0_HOST_INT_ON 0x0020
818 #define ASC_CFG0_BIOS_ON 0x0040
819 #define ASC_CFG0_VERA_BURST_ON 0x0080
820 #define ASC_CFG0_SCSI_PARITY_ON 0x0800
821 #define ASC_CFG1_SCSI_TARGET_ON 0x0080
822 #define ASC_CFG1_LRAM_8BITS_ON 0x0800
823 #define ASC_CFG_MSW_CLR_MASK 0x3080
824 #define CSW_TEST1 (ASC_CS_TYPE)0x8000
825 #define CSW_AUTO_CONFIG (ASC_CS_TYPE)0x4000
826 #define CSW_RESERVED1 (ASC_CS_TYPE)0x2000
827 #define CSW_IRQ_WRITTEN (ASC_CS_TYPE)0x1000
828 #define CSW_33MHZ_SELECTED (ASC_CS_TYPE)0x0800
829 #define CSW_TEST2 (ASC_CS_TYPE)0x0400
830 #define CSW_TEST3 (ASC_CS_TYPE)0x0200
831 #define CSW_RESERVED2 (ASC_CS_TYPE)0x0100
832 #define CSW_DMA_DONE (ASC_CS_TYPE)0x0080
833 #define CSW_FIFO_RDY (ASC_CS_TYPE)0x0040
834 #define CSW_EEP_READ_DONE (ASC_CS_TYPE)0x0020
835 #define CSW_HALTED (ASC_CS_TYPE)0x0010
836 #define CSW_SCSI_RESET_ACTIVE (ASC_CS_TYPE)0x0008
837 #define CSW_PARITY_ERR (ASC_CS_TYPE)0x0004
838 #define CSW_SCSI_RESET_LATCH (ASC_CS_TYPE)0x0002
839 #define CSW_INT_PENDING (ASC_CS_TYPE)0x0001
840 #define CIW_CLR_SCSI_RESET_INT (ASC_CS_TYPE)0x1000
841 #define CIW_INT_ACK (ASC_CS_TYPE)0x0100
842 #define CIW_TEST1 (ASC_CS_TYPE)0x0200
843 #define CIW_TEST2 (ASC_CS_TYPE)0x0400
844 #define CIW_SEL_33MHZ (ASC_CS_TYPE)0x0800
845 #define CIW_IRQ_ACT (ASC_CS_TYPE)0x1000
846 #define CC_CHIP_RESET (uchar)0x80
847 #define CC_SCSI_RESET (uchar)0x40
848 #define CC_HALT (uchar)0x20
849 #define CC_SINGLE_STEP (uchar)0x10
850 #define CC_DMA_ABLE (uchar)0x08
851 #define CC_TEST (uchar)0x04
852 #define CC_BANK_ONE (uchar)0x02
853 #define CC_DIAG (uchar)0x01
854 #define ASC_1000_ID0W 0x04C1
855 #define ASC_1000_ID0W_FIX 0x00C1
856 #define ASC_1000_ID1B 0x25
857 #define ASC_EISA_REV_IOP_MASK (0x0C83)
858 #define ASC_EISA_CFG_IOP_MASK (0x0C86)
859 #define ASC_GET_EISA_SLOT(iop) (PortAddr)((iop) & 0xF000)
860 #define INS_HALTINT (ushort)0x6281
861 #define INS_HALT (ushort)0x6280
862 #define INS_SINT (ushort)0x6200
863 #define INS_RFLAG_WTM (ushort)0x7380
864 #define ASC_MC_SAVE_CODE_WSIZE 0x500
865 #define ASC_MC_SAVE_DATA_WSIZE 0x40
867 typedef struct asc_mc_saved {
868 ushort data[ASC_MC_SAVE_DATA_WSIZE];
869 ushort code[ASC_MC_SAVE_CODE_WSIZE];
872 #define AscGetQDoneInProgress(port) AscReadLramByte((port), ASCV_Q_DONE_IN_PROGRESS_B)
873 #define AscPutQDoneInProgress(port, val) AscWriteLramByte((port), ASCV_Q_DONE_IN_PROGRESS_B, val)
874 #define AscGetVarFreeQHead(port) AscReadLramWord((port), ASCV_FREE_Q_HEAD_W)
875 #define AscGetVarDoneQTail(port) AscReadLramWord((port), ASCV_DONE_Q_TAIL_W)
876 #define AscPutVarFreeQHead(port, val) AscWriteLramWord((port), ASCV_FREE_Q_HEAD_W, val)
877 #define AscPutVarDoneQTail(port, val) AscWriteLramWord((port), ASCV_DONE_Q_TAIL_W, val)
878 #define AscGetRiscVarFreeQHead(port) AscReadLramByte((port), ASCV_NEXTRDY_B)
879 #define AscGetRiscVarDoneQTail(port) AscReadLramByte((port), ASCV_DONENEXT_B)
880 #define AscPutRiscVarFreeQHead(port, val) AscWriteLramByte((port), ASCV_NEXTRDY_B, val)
881 #define AscPutRiscVarDoneQTail(port, val) AscWriteLramByte((port), ASCV_DONENEXT_B, val)
882 #define AscPutMCodeSDTRDoneAtID(port, id, data) AscWriteLramByte((port), (ushort)((ushort)ASCV_SDTR_DONE_BEG+(ushort)id), (data))
883 #define AscGetMCodeSDTRDoneAtID(port, id) AscReadLramByte((port), (ushort)((ushort)ASCV_SDTR_DONE_BEG+(ushort)id))
884 #define AscPutMCodeInitSDTRAtID(port, id, data) AscWriteLramByte((port), (ushort)((ushort)ASCV_SDTR_DATA_BEG+(ushort)id), data)
885 #define AscGetMCodeInitSDTRAtID(port, id) AscReadLramByte((port), (ushort)((ushort)ASCV_SDTR_DATA_BEG+(ushort)id))
886 #define AscGetChipSignatureByte(port) (uchar)inp((port)+IOP_SIG_BYTE)
887 #define AscGetChipSignatureWord(port) (ushort)inpw((port)+IOP_SIG_WORD)
888 #define AscGetChipVerNo(port) (uchar)inp((port)+IOP_VERSION)
889 #define AscGetChipCfgLsw(port) (ushort)inpw((port)+IOP_CONFIG_LOW)
890 #define AscGetChipCfgMsw(port) (ushort)inpw((port)+IOP_CONFIG_HIGH)
891 #define AscSetChipCfgLsw(port, data) outpw((port)+IOP_CONFIG_LOW, data)
892 #define AscSetChipCfgMsw(port, data) outpw((port)+IOP_CONFIG_HIGH, data)
893 #define AscGetChipEEPCmd(port) (uchar)inp((port)+IOP_EEP_CMD)
894 #define AscSetChipEEPCmd(port, data) outp((port)+IOP_EEP_CMD, data)
895 #define AscGetChipEEPData(port) (ushort)inpw((port)+IOP_EEP_DATA)
896 #define AscSetChipEEPData(port, data) outpw((port)+IOP_EEP_DATA, data)
897 #define AscGetChipLramAddr(port) (ushort)inpw((PortAddr)((port)+IOP_RAM_ADDR))
898 #define AscSetChipLramAddr(port, addr) outpw((PortAddr)((port)+IOP_RAM_ADDR), addr)
899 #define AscGetChipLramData(port) (ushort)inpw((port)+IOP_RAM_DATA)
900 #define AscSetChipLramData(port, data) outpw((port)+IOP_RAM_DATA, data)
901 #define AscGetChipIFC(port) (uchar)inp((port)+IOP_REG_IFC)
902 #define AscSetChipIFC(port, data) outp((port)+IOP_REG_IFC, data)
903 #define AscGetChipStatus(port) (ASC_CS_TYPE)inpw((port)+IOP_STATUS)
904 #define AscSetChipStatus(port, cs_val) outpw((port)+IOP_STATUS, cs_val)
905 #define AscGetChipControl(port) (uchar)inp((port)+IOP_CTRL)
906 #define AscSetChipControl(port, cc_val) outp((port)+IOP_CTRL, cc_val)
907 #define AscGetChipSyn(port) (uchar)inp((port)+IOP_SYN_OFFSET)
908 #define AscSetChipSyn(port, data) outp((port)+IOP_SYN_OFFSET, data)
909 #define AscSetPCAddr(port, data) outpw((port)+IOP_REG_PC, data)
910 #define AscGetPCAddr(port) (ushort)inpw((port)+IOP_REG_PC)
911 #define AscIsIntPending(port) (AscGetChipStatus(port) & (CSW_INT_PENDING | CSW_SCSI_RESET_LATCH))
912 #define AscGetChipScsiID(port) ((AscGetChipCfgLsw(port) >> 8) & ASC_MAX_TID)
913 #define AscGetExtraControl(port) (uchar)inp((port)+IOP_EXTRA_CONTROL)
914 #define AscSetExtraControl(port, data) outp((port)+IOP_EXTRA_CONTROL, data)
915 #define AscReadChipAX(port) (ushort)inpw((port)+IOP_REG_AX)
916 #define AscWriteChipAX(port, data) outpw((port)+IOP_REG_AX, data)
917 #define AscReadChipIX(port) (uchar)inp((port)+IOP_REG_IX)
918 #define AscWriteChipIX(port, data) outp((port)+IOP_REG_IX, data)
919 #define AscReadChipIH(port) (ushort)inpw((port)+IOP_REG_IH)
920 #define AscWriteChipIH(port, data) outpw((port)+IOP_REG_IH, data)
921 #define AscReadChipQP(port) (uchar)inp((port)+IOP_REG_QP)
922 #define AscWriteChipQP(port, data) outp((port)+IOP_REG_QP, data)
923 #define AscReadChipFIFO_L(port) (ushort)inpw((port)+IOP_REG_FIFO_L)
924 #define AscWriteChipFIFO_L(port, data) outpw((port)+IOP_REG_FIFO_L, data)
925 #define AscReadChipFIFO_H(port) (ushort)inpw((port)+IOP_REG_FIFO_H)
926 #define AscWriteChipFIFO_H(port, data) outpw((port)+IOP_REG_FIFO_H, data)
927 #define AscReadChipDmaSpeed(port) (uchar)inp((port)+IOP_DMA_SPEED)
928 #define AscWriteChipDmaSpeed(port, data) outp((port)+IOP_DMA_SPEED, data)
929 #define AscReadChipDA0(port) (ushort)inpw((port)+IOP_REG_DA0)
930 #define AscWriteChipDA0(port) outpw((port)+IOP_REG_DA0, data)
931 #define AscReadChipDA1(port) (ushort)inpw((port)+IOP_REG_DA1)
932 #define AscWriteChipDA1(port) outpw((port)+IOP_REG_DA1, data)
933 #define AscReadChipDC0(port) (ushort)inpw((port)+IOP_REG_DC0)
934 #define AscWriteChipDC0(port) outpw((port)+IOP_REG_DC0, data)
935 #define AscReadChipDC1(port) (ushort)inpw((port)+IOP_REG_DC1)
936 #define AscWriteChipDC1(port) outpw((port)+IOP_REG_DC1, data)
937 #define AscReadChipDvcID(port) (uchar)inp((port)+IOP_REG_ID)
938 #define AscWriteChipDvcID(port, data) outp((port)+IOP_REG_ID, data)
941 * Portable Data Types
943 * Any instance where a 32-bit long or pointer type is assumed
944 * for precision or HW defined structures, the following define
945 * types must be used. In Linux the char, short, and int types
946 * are all consistent at 8, 16, and 32 bits respectively. Pointers
947 * and long types are 64 bits on Alpha and UltraSPARC.
949 #define ADV_PADDR __u32 /* Physical address data type. */
950 #define ADV_VADDR __u32 /* Virtual address data type. */
951 #define ADV_DCNT __u32 /* Unsigned Data count type. */
952 #define ADV_SDCNT __s32 /* Signed Data count type. */
955 * These macros are used to convert a virtual address to a
956 * 32-bit value. This currently can be used on Linux Alpha
957 * which uses 64-bit virtual address but a 32-bit bus address.
958 * This is likely to break in the future, but doing this now
959 * will give us time to change the HW and FW to handle 64-bit
962 #define ADV_VADDR_TO_U32 virt_to_bus
963 #define ADV_U32_TO_VADDR bus_to_virt
965 #define AdvPortAddr void __iomem * /* Virtual memory address size */
968 * Define Adv Library required memory access macros.
970 #define ADV_MEM_READB(addr) readb(addr)
971 #define ADV_MEM_READW(addr) readw(addr)
972 #define ADV_MEM_WRITEB(addr, byte) writeb(byte, addr)
973 #define ADV_MEM_WRITEW(addr, word) writew(word, addr)
974 #define ADV_MEM_WRITEDW(addr, dword) writel(dword, addr)
976 #define ADV_CARRIER_COUNT (ASC_DEF_MAX_HOST_QNG + 15)
979 * Define total number of simultaneous maximum element scatter-gather
980 * request blocks per wide adapter. ASC_DEF_MAX_HOST_QNG (253) is the
981 * maximum number of outstanding commands per wide host adapter. Each
982 * command uses one or more ADV_SG_BLOCK each with 15 scatter-gather
983 * elements. Allow each command to have at least one ADV_SG_BLOCK structure.
984 * This allows about 15 commands to have the maximum 17 ADV_SG_BLOCK
985 * structures or 255 scatter-gather elements.
987 #define ADV_TOT_SG_BLOCK ASC_DEF_MAX_HOST_QNG
990 * Define maximum number of scatter-gather elements per request.
992 #define ADV_MAX_SG_LIST 255
993 #define NO_OF_SG_PER_BLOCK 15
995 /* Number of SG blocks needed. */
996 #define ADV_NUM_SG_BLOCK \
997 ((ADV_MAX_SG_LIST + (NO_OF_SG_PER_BLOCK - 1))/NO_OF_SG_PER_BLOCK)
999 /* Total contiguous memory needed for SG blocks. */
1000 #define ADV_SG_TOTAL_MEM_SIZE \
1001 (sizeof(ADV_SG_BLOCK) * ADV_NUM_SG_BLOCK)
1003 #define ADV_PAGE_SIZE PAGE_SIZE
1005 #define ADV_NUM_PAGE_CROSSING \
1006 ((ADV_SG_TOTAL_MEM_SIZE + (ADV_PAGE_SIZE - 1))/ADV_PAGE_SIZE)
1008 #define ADV_EEP_DVC_CFG_BEGIN (0x00)
1009 #define ADV_EEP_DVC_CFG_END (0x15)
1010 #define ADV_EEP_DVC_CTL_BEGIN (0x16) /* location of OEM name */
1011 #define ADV_EEP_MAX_WORD_ADDR (0x1E)
1013 #define ADV_EEP_DELAY_MS 100
1015 #define ADV_EEPROM_BIG_ENDIAN 0x8000 /* EEPROM Bit 15 */
1016 #define ADV_EEPROM_BIOS_ENABLE 0x4000 /* EEPROM Bit 14 */
1018 * For the ASC3550 Bit 13 is Termination Polarity control bit.
1019 * For later ICs Bit 13 controls whether the CIS (Card Information
1020 * Service Section) is loaded from EEPROM.
1022 #define ADV_EEPROM_TERM_POL 0x2000 /* EEPROM Bit 13 */
1023 #define ADV_EEPROM_CIS_LD 0x2000 /* EEPROM Bit 13 */
1027 * If EEPROM Bit 11 is 0 for Function 0, then Function 0 will specify
1028 * INT A in the PCI Configuration Space Int Pin field. If it is 1, then
1029 * Function 0 will specify INT B.
1031 * If EEPROM Bit 11 is 0 for Function 1, then Function 1 will specify
1032 * INT B in the PCI Configuration Space Int Pin field. If it is 1, then
1033 * Function 1 will specify INT A.
1035 #define ADV_EEPROM_INTAB 0x0800 /* EEPROM Bit 11 */
1037 typedef struct adveep_3550_config {
1038 /* Word Offset, Description */
1040 ushort cfg_lsw; /* 00 power up initialization */
1041 /* bit 13 set - Term Polarity Control */
1042 /* bit 14 set - BIOS Enable */
1043 /* bit 15 set - Big Endian Mode */
1044 ushort cfg_msw; /* 01 unused */
1045 ushort disc_enable; /* 02 disconnect enable */
1046 ushort wdtr_able; /* 03 Wide DTR able */
1047 ushort sdtr_able; /* 04 Synchronous DTR able */
1048 ushort start_motor; /* 05 send start up motor */
1049 ushort tagqng_able; /* 06 tag queuing able */
1050 ushort bios_scan; /* 07 BIOS device control */
1051 ushort scam_tolerant; /* 08 no scam */
1053 uchar adapter_scsi_id; /* 09 Host Adapter ID */
1054 uchar bios_boot_delay; /* power up wait */
1056 uchar scsi_reset_delay; /* 10 reset delay */
1057 uchar bios_id_lun; /* first boot device scsi id & lun */
1058 /* high nibble is lun */
1059 /* low nibble is scsi id */
1061 uchar termination; /* 11 0 - automatic */
1062 /* 1 - low off / high off */
1063 /* 2 - low off / high on */
1064 /* 3 - low on / high on */
1065 /* There is no low on / high off */
1067 uchar reserved1; /* reserved byte (not used) */
1069 ushort bios_ctrl; /* 12 BIOS control bits */
1070 /* bit 0 BIOS don't act as initiator. */
1071 /* bit 1 BIOS > 1 GB support */
1072 /* bit 2 BIOS > 2 Disk Support */
1073 /* bit 3 BIOS don't support removables */
1074 /* bit 4 BIOS support bootable CD */
1075 /* bit 5 BIOS scan enabled */
1076 /* bit 6 BIOS support multiple LUNs */
1077 /* bit 7 BIOS display of message */
1078 /* bit 8 SCAM disabled */
1079 /* bit 9 Reset SCSI bus during init. */
1081 /* bit 11 No verbose initialization. */
1082 /* bit 12 SCSI parity enabled */
1086 ushort ultra_able; /* 13 ULTRA speed able */
1087 ushort reserved2; /* 14 reserved */
1088 uchar max_host_qng; /* 15 maximum host queuing */
1089 uchar max_dvc_qng; /* maximum per device queuing */
1090 ushort dvc_cntl; /* 16 control bit for driver */
1091 ushort bug_fix; /* 17 control bit for bug fix */
1092 ushort serial_number_word1; /* 18 Board serial number word 1 */
1093 ushort serial_number_word2; /* 19 Board serial number word 2 */
1094 ushort serial_number_word3; /* 20 Board serial number word 3 */
1095 ushort check_sum; /* 21 EEP check sum */
1096 uchar oem_name[16]; /* 22 OEM name */
1097 ushort dvc_err_code; /* 30 last device driver error code */
1098 ushort adv_err_code; /* 31 last uc and Adv Lib error code */
1099 ushort adv_err_addr; /* 32 last uc error address */
1100 ushort saved_dvc_err_code; /* 33 saved last dev. driver error code */
1101 ushort saved_adv_err_code; /* 34 saved last uc and Adv Lib error code */
1102 ushort saved_adv_err_addr; /* 35 saved last uc error address */
1103 ushort num_of_err; /* 36 number of error */
1104 } ADVEEP_3550_CONFIG;
1106 typedef struct adveep_38C0800_config {
1107 /* Word Offset, Description */
1109 ushort cfg_lsw; /* 00 power up initialization */
1110 /* bit 13 set - Load CIS */
1111 /* bit 14 set - BIOS Enable */
1112 /* bit 15 set - Big Endian Mode */
1113 ushort cfg_msw; /* 01 unused */
1114 ushort disc_enable; /* 02 disconnect enable */
1115 ushort wdtr_able; /* 03 Wide DTR able */
1116 ushort sdtr_speed1; /* 04 SDTR Speed TID 0-3 */
1117 ushort start_motor; /* 05 send start up motor */
1118 ushort tagqng_able; /* 06 tag queuing able */
1119 ushort bios_scan; /* 07 BIOS device control */
1120 ushort scam_tolerant; /* 08 no scam */
1122 uchar adapter_scsi_id; /* 09 Host Adapter ID */
1123 uchar bios_boot_delay; /* power up wait */
1125 uchar scsi_reset_delay; /* 10 reset delay */
1126 uchar bios_id_lun; /* first boot device scsi id & lun */
1127 /* high nibble is lun */
1128 /* low nibble is scsi id */
1130 uchar termination_se; /* 11 0 - automatic */
1131 /* 1 - low off / high off */
1132 /* 2 - low off / high on */
1133 /* 3 - low on / high on */
1134 /* There is no low on / high off */
1136 uchar termination_lvd; /* 11 0 - automatic */
1137 /* 1 - low off / high off */
1138 /* 2 - low off / high on */
1139 /* 3 - low on / high on */
1140 /* There is no low on / high off */
1142 ushort bios_ctrl; /* 12 BIOS control bits */
1143 /* bit 0 BIOS don't act as initiator. */
1144 /* bit 1 BIOS > 1 GB support */
1145 /* bit 2 BIOS > 2 Disk Support */
1146 /* bit 3 BIOS don't support removables */
1147 /* bit 4 BIOS support bootable CD */
1148 /* bit 5 BIOS scan enabled */
1149 /* bit 6 BIOS support multiple LUNs */
1150 /* bit 7 BIOS display of message */
1151 /* bit 8 SCAM disabled */
1152 /* bit 9 Reset SCSI bus during init. */
1154 /* bit 11 No verbose initialization. */
1155 /* bit 12 SCSI parity enabled */
1159 ushort sdtr_speed2; /* 13 SDTR speed TID 4-7 */
1160 ushort sdtr_speed3; /* 14 SDTR speed TID 8-11 */
1161 uchar max_host_qng; /* 15 maximum host queueing */
1162 uchar max_dvc_qng; /* maximum per device queuing */
1163 ushort dvc_cntl; /* 16 control bit for driver */
1164 ushort sdtr_speed4; /* 17 SDTR speed 4 TID 12-15 */
1165 ushort serial_number_word1; /* 18 Board serial number word 1 */
1166 ushort serial_number_word2; /* 19 Board serial number word 2 */
1167 ushort serial_number_word3; /* 20 Board serial number word 3 */
1168 ushort check_sum; /* 21 EEP check sum */
1169 uchar oem_name[16]; /* 22 OEM name */
1170 ushort dvc_err_code; /* 30 last device driver error code */
1171 ushort adv_err_code; /* 31 last uc and Adv Lib error code */
1172 ushort adv_err_addr; /* 32 last uc error address */
1173 ushort saved_dvc_err_code; /* 33 saved last dev. driver error code */
1174 ushort saved_adv_err_code; /* 34 saved last uc and Adv Lib error code */
1175 ushort saved_adv_err_addr; /* 35 saved last uc error address */
1176 ushort reserved36; /* 36 reserved */
1177 ushort reserved37; /* 37 reserved */
1178 ushort reserved38; /* 38 reserved */
1179 ushort reserved39; /* 39 reserved */
1180 ushort reserved40; /* 40 reserved */
1181 ushort reserved41; /* 41 reserved */
1182 ushort reserved42; /* 42 reserved */
1183 ushort reserved43; /* 43 reserved */
1184 ushort reserved44; /* 44 reserved */
1185 ushort reserved45; /* 45 reserved */
1186 ushort reserved46; /* 46 reserved */
1187 ushort reserved47; /* 47 reserved */
1188 ushort reserved48; /* 48 reserved */
1189 ushort reserved49; /* 49 reserved */
1190 ushort reserved50; /* 50 reserved */
1191 ushort reserved51; /* 51 reserved */
1192 ushort reserved52; /* 52 reserved */
1193 ushort reserved53; /* 53 reserved */
1194 ushort reserved54; /* 54 reserved */
1195 ushort reserved55; /* 55 reserved */
1196 ushort cisptr_lsw; /* 56 CIS PTR LSW */
1197 ushort cisprt_msw; /* 57 CIS PTR MSW */
1198 ushort subsysvid; /* 58 SubSystem Vendor ID */
1199 ushort subsysid; /* 59 SubSystem ID */
1200 ushort reserved60; /* 60 reserved */
1201 ushort reserved61; /* 61 reserved */
1202 ushort reserved62; /* 62 reserved */
1203 ushort reserved63; /* 63 reserved */
1204 } ADVEEP_38C0800_CONFIG;
1206 typedef struct adveep_38C1600_config {
1207 /* Word Offset, Description */
1209 ushort cfg_lsw; /* 00 power up initialization */
1210 /* bit 11 set - Func. 0 INTB, Func. 1 INTA */
1211 /* clear - Func. 0 INTA, Func. 1 INTB */
1212 /* bit 13 set - Load CIS */
1213 /* bit 14 set - BIOS Enable */
1214 /* bit 15 set - Big Endian Mode */
1215 ushort cfg_msw; /* 01 unused */
1216 ushort disc_enable; /* 02 disconnect enable */
1217 ushort wdtr_able; /* 03 Wide DTR able */
1218 ushort sdtr_speed1; /* 04 SDTR Speed TID 0-3 */
1219 ushort start_motor; /* 05 send start up motor */
1220 ushort tagqng_able; /* 06 tag queuing able */
1221 ushort bios_scan; /* 07 BIOS device control */
1222 ushort scam_tolerant; /* 08 no scam */
1224 uchar adapter_scsi_id; /* 09 Host Adapter ID */
1225 uchar bios_boot_delay; /* power up wait */
1227 uchar scsi_reset_delay; /* 10 reset delay */
1228 uchar bios_id_lun; /* first boot device scsi id & lun */
1229 /* high nibble is lun */
1230 /* low nibble is scsi id */
1232 uchar termination_se; /* 11 0 - automatic */
1233 /* 1 - low off / high off */
1234 /* 2 - low off / high on */
1235 /* 3 - low on / high on */
1236 /* There is no low on / high off */
1238 uchar termination_lvd; /* 11 0 - automatic */
1239 /* 1 - low off / high off */
1240 /* 2 - low off / high on */
1241 /* 3 - low on / high on */
1242 /* There is no low on / high off */
1244 ushort bios_ctrl; /* 12 BIOS control bits */
1245 /* bit 0 BIOS don't act as initiator. */
1246 /* bit 1 BIOS > 1 GB support */
1247 /* bit 2 BIOS > 2 Disk Support */
1248 /* bit 3 BIOS don't support removables */
1249 /* bit 4 BIOS support bootable CD */
1250 /* bit 5 BIOS scan enabled */
1251 /* bit 6 BIOS support multiple LUNs */
1252 /* bit 7 BIOS display of message */
1253 /* bit 8 SCAM disabled */
1254 /* bit 9 Reset SCSI bus during init. */
1255 /* bit 10 Basic Integrity Checking disabled */
1256 /* bit 11 No verbose initialization. */
1257 /* bit 12 SCSI parity enabled */
1258 /* bit 13 AIPP (Asyn. Info. Ph. Prot.) dis. */
1261 ushort sdtr_speed2; /* 13 SDTR speed TID 4-7 */
1262 ushort sdtr_speed3; /* 14 SDTR speed TID 8-11 */
1263 uchar max_host_qng; /* 15 maximum host queueing */
1264 uchar max_dvc_qng; /* maximum per device queuing */
1265 ushort dvc_cntl; /* 16 control bit for driver */
1266 ushort sdtr_speed4; /* 17 SDTR speed 4 TID 12-15 */
1267 ushort serial_number_word1; /* 18 Board serial number word 1 */
1268 ushort serial_number_word2; /* 19 Board serial number word 2 */
1269 ushort serial_number_word3; /* 20 Board serial number word 3 */
1270 ushort check_sum; /* 21 EEP check sum */
1271 uchar oem_name[16]; /* 22 OEM name */
1272 ushort dvc_err_code; /* 30 last device driver error code */
1273 ushort adv_err_code; /* 31 last uc and Adv Lib error code */
1274 ushort adv_err_addr; /* 32 last uc error address */
1275 ushort saved_dvc_err_code; /* 33 saved last dev. driver error code */
1276 ushort saved_adv_err_code; /* 34 saved last uc and Adv Lib error code */
1277 ushort saved_adv_err_addr; /* 35 saved last uc error address */
1278 ushort reserved36; /* 36 reserved */
1279 ushort reserved37; /* 37 reserved */
1280 ushort reserved38; /* 38 reserved */
1281 ushort reserved39; /* 39 reserved */
1282 ushort reserved40; /* 40 reserved */
1283 ushort reserved41; /* 41 reserved */
1284 ushort reserved42; /* 42 reserved */
1285 ushort reserved43; /* 43 reserved */
1286 ushort reserved44; /* 44 reserved */
1287 ushort reserved45; /* 45 reserved */
1288 ushort reserved46; /* 46 reserved */
1289 ushort reserved47; /* 47 reserved */
1290 ushort reserved48; /* 48 reserved */
1291 ushort reserved49; /* 49 reserved */
1292 ushort reserved50; /* 50 reserved */
1293 ushort reserved51; /* 51 reserved */
1294 ushort reserved52; /* 52 reserved */
1295 ushort reserved53; /* 53 reserved */
1296 ushort reserved54; /* 54 reserved */
1297 ushort reserved55; /* 55 reserved */
1298 ushort cisptr_lsw; /* 56 CIS PTR LSW */
1299 ushort cisprt_msw; /* 57 CIS PTR MSW */
1300 ushort subsysvid; /* 58 SubSystem Vendor ID */
1301 ushort subsysid; /* 59 SubSystem ID */
1302 ushort reserved60; /* 60 reserved */
1303 ushort reserved61; /* 61 reserved */
1304 ushort reserved62; /* 62 reserved */
1305 ushort reserved63; /* 63 reserved */
1306 } ADVEEP_38C1600_CONFIG;
1311 #define ASC_EEP_CMD_DONE 0x0200
1314 #define BIOS_CTRL_BIOS 0x0001
1315 #define BIOS_CTRL_EXTENDED_XLAT 0x0002
1316 #define BIOS_CTRL_GT_2_DISK 0x0004
1317 #define BIOS_CTRL_BIOS_REMOVABLE 0x0008
1318 #define BIOS_CTRL_BOOTABLE_CD 0x0010
1319 #define BIOS_CTRL_MULTIPLE_LUN 0x0040
1320 #define BIOS_CTRL_DISPLAY_MSG 0x0080
1321 #define BIOS_CTRL_NO_SCAM 0x0100
1322 #define BIOS_CTRL_RESET_SCSI_BUS 0x0200
1323 #define BIOS_CTRL_INIT_VERBOSE 0x0800
1324 #define BIOS_CTRL_SCSI_PARITY 0x1000
1325 #define BIOS_CTRL_AIPP_DIS 0x2000
1327 #define ADV_3550_MEMSIZE 0x2000 /* 8 KB Internal Memory */
1329 #define ADV_38C0800_MEMSIZE 0x4000 /* 16 KB Internal Memory */
1332 * XXX - Since ASC38C1600 Rev.3 has a local RAM failure issue, there is
1333 * a special 16K Adv Library and Microcode version. After the issue is
1334 * resolved, should restore 32K support.
1336 * #define ADV_38C1600_MEMSIZE 0x8000L * 32 KB Internal Memory *
1338 #define ADV_38C1600_MEMSIZE 0x4000 /* 16 KB Internal Memory */
1341 * Byte I/O register address from base of 'iop_base'.
1343 #define IOPB_INTR_STATUS_REG 0x00
1344 #define IOPB_CHIP_ID_1 0x01
1345 #define IOPB_INTR_ENABLES 0x02
1346 #define IOPB_CHIP_TYPE_REV 0x03
1347 #define IOPB_RES_ADDR_4 0x04
1348 #define IOPB_RES_ADDR_5 0x05
1349 #define IOPB_RAM_DATA 0x06
1350 #define IOPB_RES_ADDR_7 0x07
1351 #define IOPB_FLAG_REG 0x08
1352 #define IOPB_RES_ADDR_9 0x09
1353 #define IOPB_RISC_CSR 0x0A
1354 #define IOPB_RES_ADDR_B 0x0B
1355 #define IOPB_RES_ADDR_C 0x0C
1356 #define IOPB_RES_ADDR_D 0x0D
1357 #define IOPB_SOFT_OVER_WR 0x0E
1358 #define IOPB_RES_ADDR_F 0x0F
1359 #define IOPB_MEM_CFG 0x10
1360 #define IOPB_RES_ADDR_11 0x11
1361 #define IOPB_GPIO_DATA 0x12
1362 #define IOPB_RES_ADDR_13 0x13
1363 #define IOPB_FLASH_PAGE 0x14
1364 #define IOPB_RES_ADDR_15 0x15
1365 #define IOPB_GPIO_CNTL 0x16
1366 #define IOPB_RES_ADDR_17 0x17
1367 #define IOPB_FLASH_DATA 0x18
1368 #define IOPB_RES_ADDR_19 0x19
1369 #define IOPB_RES_ADDR_1A 0x1A
1370 #define IOPB_RES_ADDR_1B 0x1B
1371 #define IOPB_RES_ADDR_1C 0x1C
1372 #define IOPB_RES_ADDR_1D 0x1D
1373 #define IOPB_RES_ADDR_1E 0x1E
1374 #define IOPB_RES_ADDR_1F 0x1F
1375 #define IOPB_DMA_CFG0 0x20
1376 #define IOPB_DMA_CFG1 0x21
1377 #define IOPB_TICKLE 0x22
1378 #define IOPB_DMA_REG_WR 0x23
1379 #define IOPB_SDMA_STATUS 0x24
1380 #define IOPB_SCSI_BYTE_CNT 0x25
1381 #define IOPB_HOST_BYTE_CNT 0x26
1382 #define IOPB_BYTE_LEFT_TO_XFER 0x27
1383 #define IOPB_BYTE_TO_XFER_0 0x28
1384 #define IOPB_BYTE_TO_XFER_1 0x29
1385 #define IOPB_BYTE_TO_XFER_2 0x2A
1386 #define IOPB_BYTE_TO_XFER_3 0x2B
1387 #define IOPB_ACC_GRP 0x2C
1388 #define IOPB_RES_ADDR_2D 0x2D
1389 #define IOPB_DEV_ID 0x2E
1390 #define IOPB_RES_ADDR_2F 0x2F
1391 #define IOPB_SCSI_DATA 0x30
1392 #define IOPB_RES_ADDR_31 0x31
1393 #define IOPB_RES_ADDR_32 0x32
1394 #define IOPB_SCSI_DATA_HSHK 0x33
1395 #define IOPB_SCSI_CTRL 0x34
1396 #define IOPB_RES_ADDR_35 0x35
1397 #define IOPB_RES_ADDR_36 0x36
1398 #define IOPB_RES_ADDR_37 0x37
1399 #define IOPB_RAM_BIST 0x38
1400 #define IOPB_PLL_TEST 0x39
1401 #define IOPB_PCI_INT_CFG 0x3A
1402 #define IOPB_RES_ADDR_3B 0x3B
1403 #define IOPB_RFIFO_CNT 0x3C
1404 #define IOPB_RES_ADDR_3D 0x3D
1405 #define IOPB_RES_ADDR_3E 0x3E
1406 #define IOPB_RES_ADDR_3F 0x3F
1409 * Word I/O register address from base of 'iop_base'.
1411 #define IOPW_CHIP_ID_0 0x00 /* CID0 */
1412 #define IOPW_CTRL_REG 0x02 /* CC */
1413 #define IOPW_RAM_ADDR 0x04 /* LA */
1414 #define IOPW_RAM_DATA 0x06 /* LD */
1415 #define IOPW_RES_ADDR_08 0x08
1416 #define IOPW_RISC_CSR 0x0A /* CSR */
1417 #define IOPW_SCSI_CFG0 0x0C /* CFG0 */
1418 #define IOPW_SCSI_CFG1 0x0E /* CFG1 */
1419 #define IOPW_RES_ADDR_10 0x10
1420 #define IOPW_SEL_MASK 0x12 /* SM */
1421 #define IOPW_RES_ADDR_14 0x14
1422 #define IOPW_FLASH_ADDR 0x16 /* FA */
1423 #define IOPW_RES_ADDR_18 0x18
1424 #define IOPW_EE_CMD 0x1A /* EC */
1425 #define IOPW_EE_DATA 0x1C /* ED */
1426 #define IOPW_SFIFO_CNT 0x1E /* SFC */
1427 #define IOPW_RES_ADDR_20 0x20
1428 #define IOPW_Q_BASE 0x22 /* QB */
1429 #define IOPW_QP 0x24 /* QP */
1430 #define IOPW_IX 0x26 /* IX */
1431 #define IOPW_SP 0x28 /* SP */
1432 #define IOPW_PC 0x2A /* PC */
1433 #define IOPW_RES_ADDR_2C 0x2C
1434 #define IOPW_RES_ADDR_2E 0x2E
1435 #define IOPW_SCSI_DATA 0x30 /* SD */
1436 #define IOPW_SCSI_DATA_HSHK 0x32 /* SDH */
1437 #define IOPW_SCSI_CTRL 0x34 /* SC */
1438 #define IOPW_HSHK_CFG 0x36 /* HCFG */
1439 #define IOPW_SXFR_STATUS 0x36 /* SXS */
1440 #define IOPW_SXFR_CNTL 0x38 /* SXL */
1441 #define IOPW_SXFR_CNTH 0x3A /* SXH */
1442 #define IOPW_RES_ADDR_3C 0x3C
1443 #define IOPW_RFIFO_DATA 0x3E /* RFD */
1446 * Doubleword I/O register address from base of 'iop_base'.
1448 #define IOPDW_RES_ADDR_0 0x00
1449 #define IOPDW_RAM_DATA 0x04
1450 #define IOPDW_RES_ADDR_8 0x08
1451 #define IOPDW_RES_ADDR_C 0x0C
1452 #define IOPDW_RES_ADDR_10 0x10
1453 #define IOPDW_COMMA 0x14
1454 #define IOPDW_COMMB 0x18
1455 #define IOPDW_RES_ADDR_1C 0x1C
1456 #define IOPDW_SDMA_ADDR0 0x20
1457 #define IOPDW_SDMA_ADDR1 0x24
1458 #define IOPDW_SDMA_COUNT 0x28
1459 #define IOPDW_SDMA_ERROR 0x2C
1460 #define IOPDW_RDMA_ADDR0 0x30
1461 #define IOPDW_RDMA_ADDR1 0x34
1462 #define IOPDW_RDMA_COUNT 0x38
1463 #define IOPDW_RDMA_ERROR 0x3C
1465 #define ADV_CHIP_ID_BYTE 0x25
1466 #define ADV_CHIP_ID_WORD 0x04C1
1468 #define ADV_INTR_ENABLE_HOST_INTR 0x01
1469 #define ADV_INTR_ENABLE_SEL_INTR 0x02
1470 #define ADV_INTR_ENABLE_DPR_INTR 0x04
1471 #define ADV_INTR_ENABLE_RTA_INTR 0x08
1472 #define ADV_INTR_ENABLE_RMA_INTR 0x10
1473 #define ADV_INTR_ENABLE_RST_INTR 0x20
1474 #define ADV_INTR_ENABLE_DPE_INTR 0x40
1475 #define ADV_INTR_ENABLE_GLOBAL_INTR 0x80
1477 #define ADV_INTR_STATUS_INTRA 0x01
1478 #define ADV_INTR_STATUS_INTRB 0x02
1479 #define ADV_INTR_STATUS_INTRC 0x04
1481 #define ADV_RISC_CSR_STOP (0x0000)
1482 #define ADV_RISC_TEST_COND (0x2000)
1483 #define ADV_RISC_CSR_RUN (0x4000)
1484 #define ADV_RISC_CSR_SINGLE_STEP (0x8000)
1486 #define ADV_CTRL_REG_HOST_INTR 0x0100
1487 #define ADV_CTRL_REG_SEL_INTR 0x0200
1488 #define ADV_CTRL_REG_DPR_INTR 0x0400
1489 #define ADV_CTRL_REG_RTA_INTR 0x0800
1490 #define ADV_CTRL_REG_RMA_INTR 0x1000
1491 #define ADV_CTRL_REG_RES_BIT14 0x2000
1492 #define ADV_CTRL_REG_DPE_INTR 0x4000
1493 #define ADV_CTRL_REG_POWER_DONE 0x8000
1494 #define ADV_CTRL_REG_ANY_INTR 0xFF00
1496 #define ADV_CTRL_REG_CMD_RESET 0x00C6
1497 #define ADV_CTRL_REG_CMD_WR_IO_REG 0x00C5
1498 #define ADV_CTRL_REG_CMD_RD_IO_REG 0x00C4
1499 #define ADV_CTRL_REG_CMD_WR_PCI_CFG_SPACE 0x00C3
1500 #define ADV_CTRL_REG_CMD_RD_PCI_CFG_SPACE 0x00C2
1502 #define ADV_TICKLE_NOP 0x00
1503 #define ADV_TICKLE_A 0x01
1504 #define ADV_TICKLE_B 0x02
1505 #define ADV_TICKLE_C 0x03
1507 #define AdvIsIntPending(port) \
1508 (AdvReadWordRegister(port, IOPW_CTRL_REG) & ADV_CTRL_REG_HOST_INTR)
1511 * SCSI_CFG0 Register bit definitions
1513 #define TIMER_MODEAB 0xC000 /* Watchdog, Second, and Select. Timer Ctrl. */
1514 #define PARITY_EN 0x2000 /* Enable SCSI Parity Error detection */
1515 #define EVEN_PARITY 0x1000 /* Select Even Parity */
1516 #define WD_LONG 0x0800 /* Watchdog Interval, 1: 57 min, 0: 13 sec */
1517 #define QUEUE_128 0x0400 /* Queue Size, 1: 128 byte, 0: 64 byte */
1518 #define PRIM_MODE 0x0100 /* Primitive SCSI mode */
1519 #define SCAM_EN 0x0080 /* Enable SCAM selection */
1520 #define SEL_TMO_LONG 0x0040 /* Sel/Resel Timeout, 1: 400 ms, 0: 1.6 ms */
1521 #define CFRM_ID 0x0020 /* SCAM id sel. confirm., 1: fast, 0: 6.4 ms */
1522 #define OUR_ID_EN 0x0010 /* Enable OUR_ID bits */
1523 #define OUR_ID 0x000F /* SCSI ID */
1526 * SCSI_CFG1 Register bit definitions
1528 #define BIG_ENDIAN 0x8000 /* Enable Big Endian Mode MIO:15, EEP:15 */
1529 #define TERM_POL 0x2000 /* Terminator Polarity Ctrl. MIO:13, EEP:13 */
1530 #define SLEW_RATE 0x1000 /* SCSI output buffer slew rate */
1531 #define FILTER_SEL 0x0C00 /* Filter Period Selection */
1532 #define FLTR_DISABLE 0x0000 /* Input Filtering Disabled */
1533 #define FLTR_11_TO_20NS 0x0800 /* Input Filtering 11ns to 20ns */
1534 #define FLTR_21_TO_39NS 0x0C00 /* Input Filtering 21ns to 39ns */
1535 #define ACTIVE_DBL 0x0200 /* Disable Active Negation */
1536 #define DIFF_MODE 0x0100 /* SCSI differential Mode (Read-Only) */
1537 #define DIFF_SENSE 0x0080 /* 1: No SE cables, 0: SE cable (Read-Only) */
1538 #define TERM_CTL_SEL 0x0040 /* Enable TERM_CTL_H and TERM_CTL_L */
1539 #define TERM_CTL 0x0030 /* External SCSI Termination Bits */
1540 #define TERM_CTL_H 0x0020 /* Enable External SCSI Upper Termination */
1541 #define TERM_CTL_L 0x0010 /* Enable External SCSI Lower Termination */
1542 #define CABLE_DETECT 0x000F /* External SCSI Cable Connection Status */
1545 * Addendum for ASC-38C0800 Chip
1547 * The ASC-38C1600 Chip uses the same definitions except that the
1548 * bus mode override bits [12:10] have been moved to byte register
1549 * offset 0xE (IOPB_SOFT_OVER_WR) bits [12:10]. The [12:10] bits in
1550 * SCSI_CFG1 are read-only and always available. Bit 14 (DIS_TERM_DRV)
1551 * is not needed. The [12:10] bits in IOPB_SOFT_OVER_WR are write-only.
1552 * Also each ASC-38C1600 function or channel uses only cable bits [5:4]
1553 * and [1:0]. Bits [14], [7:6], [3:2] are unused.
1555 #define DIS_TERM_DRV 0x4000 /* 1: Read c_det[3:0], 0: cannot read */
1556 #define HVD_LVD_SE 0x1C00 /* Device Detect Bits */
1557 #define HVD 0x1000 /* HVD Device Detect */
1558 #define LVD 0x0800 /* LVD Device Detect */
1559 #define SE 0x0400 /* SE Device Detect */
1560 #define TERM_LVD 0x00C0 /* LVD Termination Bits */
1561 #define TERM_LVD_HI 0x0080 /* Enable LVD Upper Termination */
1562 #define TERM_LVD_LO 0x0040 /* Enable LVD Lower Termination */
1563 #define TERM_SE 0x0030 /* SE Termination Bits */
1564 #define TERM_SE_HI 0x0020 /* Enable SE Upper Termination */
1565 #define TERM_SE_LO 0x0010 /* Enable SE Lower Termination */
1566 #define C_DET_LVD 0x000C /* LVD Cable Detect Bits */
1567 #define C_DET3 0x0008 /* Cable Detect for LVD External Wide */
1568 #define C_DET2 0x0004 /* Cable Detect for LVD Internal Wide */
1569 #define C_DET_SE 0x0003 /* SE Cable Detect Bits */
1570 #define C_DET1 0x0002 /* Cable Detect for SE Internal Wide */
1571 #define C_DET0 0x0001 /* Cable Detect for SE Internal Narrow */
1573 #define CABLE_ILLEGAL_A 0x7
1574 /* x 0 0 0 | on on | Illegal (all 3 connectors are used) */
1576 #define CABLE_ILLEGAL_B 0xB
1577 /* 0 x 0 0 | on on | Illegal (all 3 connectors are used) */
1580 * MEM_CFG Register bit definitions
1582 #define BIOS_EN 0x40 /* BIOS Enable MIO:14,EEP:14 */
1583 #define FAST_EE_CLK 0x20 /* Diagnostic Bit */
1584 #define RAM_SZ 0x1C /* Specify size of RAM to RISC */
1585 #define RAM_SZ_2KB 0x00 /* 2 KB */
1586 #define RAM_SZ_4KB 0x04 /* 4 KB */
1587 #define RAM_SZ_8KB 0x08 /* 8 KB */
1588 #define RAM_SZ_16KB 0x0C /* 16 KB */
1589 #define RAM_SZ_32KB 0x10 /* 32 KB */
1590 #define RAM_SZ_64KB 0x14 /* 64 KB */
1593 * DMA_CFG0 Register bit definitions
1595 * This register is only accessible to the host.
1597 #define BC_THRESH_ENB 0x80 /* PCI DMA Start Conditions */
1598 #define FIFO_THRESH 0x70 /* PCI DMA FIFO Threshold */
1599 #define FIFO_THRESH_16B 0x00 /* 16 bytes */
1600 #define FIFO_THRESH_32B 0x20 /* 32 bytes */
1601 #define FIFO_THRESH_48B 0x30 /* 48 bytes */
1602 #define FIFO_THRESH_64B 0x40 /* 64 bytes */
1603 #define FIFO_THRESH_80B 0x50 /* 80 bytes (default) */
1604 #define FIFO_THRESH_96B 0x60 /* 96 bytes */
1605 #define FIFO_THRESH_112B 0x70 /* 112 bytes */
1606 #define START_CTL 0x0C /* DMA start conditions */
1607 #define START_CTL_TH 0x00 /* Wait threshold level (default) */
1608 #define START_CTL_ID 0x04 /* Wait SDMA/SBUS idle */
1609 #define START_CTL_THID 0x08 /* Wait threshold and SDMA/SBUS idle */
1610 #define START_CTL_EMFU 0x0C /* Wait SDMA FIFO empty/full */
1611 #define READ_CMD 0x03 /* Memory Read Method */
1612 #define READ_CMD_MR 0x00 /* Memory Read */
1613 #define READ_CMD_MRL 0x02 /* Memory Read Long */
1614 #define READ_CMD_MRM 0x03 /* Memory Read Multiple (default) */
1617 * ASC-38C0800 RAM BIST Register bit definitions
1619 #define RAM_TEST_MODE 0x80
1620 #define PRE_TEST_MODE 0x40
1621 #define NORMAL_MODE 0x00
1622 #define RAM_TEST_DONE 0x10
1623 #define RAM_TEST_STATUS 0x0F
1624 #define RAM_TEST_HOST_ERROR 0x08
1625 #define RAM_TEST_INTRAM_ERROR 0x04
1626 #define RAM_TEST_RISC_ERROR 0x02
1627 #define RAM_TEST_SCSI_ERROR 0x01
1628 #define RAM_TEST_SUCCESS 0x00
1629 #define PRE_TEST_VALUE 0x05
1630 #define NORMAL_VALUE 0x00
1633 * ASC38C1600 Definitions
1635 * IOPB_PCI_INT_CFG Bit Field Definitions
1638 #define INTAB_LD 0x80 /* Value loaded from EEPROM Bit 11. */
1641 * Bit 1 can be set to change the interrupt for the Function to operate in
1642 * Totem Pole mode. By default Bit 1 is 0 and the interrupt operates in
1643 * Open Drain mode. Both functions of the ASC38C1600 must be set to the same
1644 * mode, otherwise the operating mode is undefined.
1646 #define TOTEMPOLE 0x02
1649 * Bit 0 can be used to change the Int Pin for the Function. The value is
1650 * 0 by default for both Functions with Function 0 using INT A and Function
1651 * B using INT B. For Function 0 if set, INT B is used. For Function 1 if set,
1654 * EEPROM Word 0 Bit 11 for each Function may change the initial Int Pin
1655 * value specified in the PCI Configuration Space.
1660 * Adv Library Status Definitions
1664 #define ADV_SUCCESS 1
1666 #define ADV_ERROR (-1)
1669 * ADV_DVC_VAR 'warn_code' values
1671 #define ASC_WARN_BUSRESET_ERROR 0x0001 /* SCSI Bus Reset error */
1672 #define ASC_WARN_EEPROM_CHKSUM 0x0002 /* EEP check sum error */
1673 #define ASC_WARN_EEPROM_TERMINATION 0x0004 /* EEP termination bad field */
1674 #define ASC_WARN_ERROR 0xFFFF /* ADV_ERROR return */
1676 #define ADV_MAX_TID 15 /* max. target identifier */
1677 #define ADV_MAX_LUN 7 /* max. logical unit number */
1680 * Fixed locations of microcode operating variables.
1682 #define ASC_MC_CODE_BEGIN_ADDR 0x0028 /* microcode start address */
1683 #define ASC_MC_CODE_END_ADDR 0x002A /* microcode end address */
1684 #define ASC_MC_CODE_CHK_SUM 0x002C /* microcode code checksum */
1685 #define ASC_MC_VERSION_DATE 0x0038 /* microcode version */
1686 #define ASC_MC_VERSION_NUM 0x003A /* microcode number */
1687 #define ASC_MC_BIOSMEM 0x0040 /* BIOS RISC Memory Start */
1688 #define ASC_MC_BIOSLEN 0x0050 /* BIOS RISC Memory Length */
1689 #define ASC_MC_BIOS_SIGNATURE 0x0058 /* BIOS Signature 0x55AA */
1690 #define ASC_MC_BIOS_VERSION 0x005A /* BIOS Version (2 bytes) */
1691 #define ASC_MC_SDTR_SPEED1 0x0090 /* SDTR Speed for TID 0-3 */
1692 #define ASC_MC_SDTR_SPEED2 0x0092 /* SDTR Speed for TID 4-7 */
1693 #define ASC_MC_SDTR_SPEED3 0x0094 /* SDTR Speed for TID 8-11 */
1694 #define ASC_MC_SDTR_SPEED4 0x0096 /* SDTR Speed for TID 12-15 */
1695 #define ASC_MC_CHIP_TYPE 0x009A
1696 #define ASC_MC_INTRB_CODE 0x009B
1697 #define ASC_MC_WDTR_ABLE 0x009C
1698 #define ASC_MC_SDTR_ABLE 0x009E
1699 #define ASC_MC_TAGQNG_ABLE 0x00A0
1700 #define ASC_MC_DISC_ENABLE 0x00A2
1701 #define ASC_MC_IDLE_CMD_STATUS 0x00A4
1702 #define ASC_MC_IDLE_CMD 0x00A6
1703 #define ASC_MC_IDLE_CMD_PARAMETER 0x00A8
1704 #define ASC_MC_DEFAULT_SCSI_CFG0 0x00AC
1705 #define ASC_MC_DEFAULT_SCSI_CFG1 0x00AE
1706 #define ASC_MC_DEFAULT_MEM_CFG 0x00B0
1707 #define ASC_MC_DEFAULT_SEL_MASK 0x00B2
1708 #define ASC_MC_SDTR_DONE 0x00B6
1709 #define ASC_MC_NUMBER_OF_QUEUED_CMD 0x00C0
1710 #define ASC_MC_NUMBER_OF_MAX_CMD 0x00D0
1711 #define ASC_MC_DEVICE_HSHK_CFG_TABLE 0x0100
1712 #define ASC_MC_CONTROL_FLAG 0x0122 /* Microcode control flag. */
1713 #define ASC_MC_WDTR_DONE 0x0124
1714 #define ASC_MC_CAM_MODE_MASK 0x015E /* CAM mode TID bitmask. */
1715 #define ASC_MC_ICQ 0x0160
1716 #define ASC_MC_IRQ 0x0164
1717 #define ASC_MC_PPR_ABLE 0x017A
1720 * BIOS LRAM variable absolute offsets.
1722 #define BIOS_CODESEG 0x54
1723 #define BIOS_CODELEN 0x56
1724 #define BIOS_SIGNATURE 0x58
1725 #define BIOS_VERSION 0x5A
1728 * Microcode Control Flags
1730 * Flags set by the Adv Library in RISC variable 'control_flag' (0x122)
1731 * and handled by the microcode.
1733 #define CONTROL_FLAG_IGNORE_PERR 0x0001 /* Ignore DMA Parity Errors */
1734 #define CONTROL_FLAG_ENABLE_AIPP 0x0002 /* Enabled AIPP checking. */
1737 * ASC_MC_DEVICE_HSHK_CFG_TABLE microcode table or HSHK_CFG register format
1739 #define HSHK_CFG_WIDE_XFR 0x8000
1740 #define HSHK_CFG_RATE 0x0F00
1741 #define HSHK_CFG_OFFSET 0x001F
1743 #define ASC_DEF_MAX_HOST_QNG 0xFD /* Max. number of host commands (253) */
1744 #define ASC_DEF_MIN_HOST_QNG 0x10 /* Min. number of host commands (16) */
1745 #define ASC_DEF_MAX_DVC_QNG 0x3F /* Max. number commands per device (63) */
1746 #define ASC_DEF_MIN_DVC_QNG 0x04 /* Min. number commands per device (4) */
1748 #define ASC_QC_DATA_CHECK 0x01 /* Require ASC_QC_DATA_OUT set or clear. */
1749 #define ASC_QC_DATA_OUT 0x02 /* Data out DMA transfer. */
1750 #define ASC_QC_START_MOTOR 0x04 /* Send auto-start motor before request. */
1751 #define ASC_QC_NO_OVERRUN 0x08 /* Don't report overrun. */
1752 #define ASC_QC_FREEZE_TIDQ 0x10 /* Freeze TID queue after request. XXX TBD */
1754 #define ASC_QSC_NO_DISC 0x01 /* Don't allow disconnect for request. */
1755 #define ASC_QSC_NO_TAGMSG 0x02 /* Don't allow tag queuing for request. */
1756 #define ASC_QSC_NO_SYNC 0x04 /* Don't use Synch. transfer on request. */
1757 #define ASC_QSC_NO_WIDE 0x08 /* Don't use Wide transfer on request. */
1758 #define ASC_QSC_REDO_DTR 0x10 /* Renegotiate WDTR/SDTR before request. */
1760 * Note: If a Tag Message is to be sent and neither ASC_QSC_HEAD_TAG or
1761 * ASC_QSC_ORDERED_TAG is set, then a Simple Tag Message (0x20) is used.
1763 #define ASC_QSC_HEAD_TAG 0x40 /* Use Head Tag Message (0x21). */
1764 #define ASC_QSC_ORDERED_TAG 0x80 /* Use Ordered Tag Message (0x22). */
1767 * All fields here are accessed by the board microcode and need to be
1770 typedef struct adv_carr_t {
1771 ADV_VADDR carr_va; /* Carrier Virtual Address */
1772 ADV_PADDR carr_pa; /* Carrier Physical Address */
1773 ADV_VADDR areq_vpa; /* ASC_SCSI_REQ_Q Virtual or Physical Address */
1775 * next_vpa [31:4] Carrier Virtual or Physical Next Pointer
1777 * next_vpa [3:1] Reserved Bits
1778 * next_vpa [0] Done Flag set in Response Queue.
1784 * Mask used to eliminate low 4 bits of carrier 'next_vpa' field.
1786 #define ASC_NEXT_VPA_MASK 0xFFFFFFF0
1788 #define ASC_RQ_DONE 0x00000001
1789 #define ASC_RQ_GOOD 0x00000002
1790 #define ASC_CQ_STOPPER 0x00000000
1792 #define ASC_GET_CARRP(carrp) ((carrp) & ASC_NEXT_VPA_MASK)
1794 #define ADV_CARRIER_NUM_PAGE_CROSSING \
1795 (((ADV_CARRIER_COUNT * sizeof(ADV_CARR_T)) + \
1796 (ADV_PAGE_SIZE - 1))/ADV_PAGE_SIZE)
1798 #define ADV_CARRIER_BUFSIZE \
1799 ((ADV_CARRIER_COUNT + ADV_CARRIER_NUM_PAGE_CROSSING) * sizeof(ADV_CARR_T))
1802 * ASC_SCSI_REQ_Q 'a_flag' definitions
1804 * The Adv Library should limit use to the lower nibble (4 bits) of
1805 * a_flag. Drivers are free to use the upper nibble (4 bits) of a_flag.
1807 #define ADV_POLL_REQUEST 0x01 /* poll for request completion */
1808 #define ADV_SCSIQ_DONE 0x02 /* request done */
1809 #define ADV_DONT_RETRY 0x08 /* don't do retry */
1811 #define ADV_CHIP_ASC3550 0x01 /* Ultra-Wide IC */
1812 #define ADV_CHIP_ASC38C0800 0x02 /* Ultra2-Wide/LVD IC */
1813 #define ADV_CHIP_ASC38C1600 0x03 /* Ultra3-Wide/LVD2 IC */
1816 * Adapter temporary configuration structure
1818 * This structure can be discarded after initialization. Don't add
1819 * fields here needed after initialization.
1821 * Field naming convention:
1823 * *_enable indicates the field enables or disables a feature. The
1824 * value of the field is never reset.
1826 typedef struct adv_dvc_cfg {
1827 ushort disc_enable; /* enable disconnection */
1828 uchar chip_version; /* chip version */
1829 uchar termination; /* Term. Ctrl. bits 6-5 of SCSI_CFG1 register */
1830 ushort control_flag; /* Microcode Control Flag */
1831 ushort mcode_date; /* Microcode date */
1832 ushort mcode_version; /* Microcode version */
1833 ushort serial1; /* EEPROM serial number word 1 */
1834 ushort serial2; /* EEPROM serial number word 2 */
1835 ushort serial3; /* EEPROM serial number word 3 */
1839 struct adv_scsi_req_q;
1841 typedef struct asc_sg_block {
1845 uchar sg_cnt; /* Valid entries in block. */
1846 ADV_PADDR sg_ptr; /* Pointer to next sg block. */
1848 ADV_PADDR sg_addr; /* SG element address. */
1849 ADV_DCNT sg_count; /* SG element count. */
1850 } sg_list[NO_OF_SG_PER_BLOCK];
1854 * ADV_SCSI_REQ_Q - microcode request structure
1856 * All fields in this structure up to byte 60 are used by the microcode.
1857 * The microcode makes assumptions about the size and ordering of fields
1858 * in this structure. Do not change the structure definition here without
1859 * coordinating the change with the microcode.
1861 * All fields accessed by microcode must be maintained in little_endian
1864 typedef struct adv_scsi_req_q {
1865 uchar cntl; /* Ucode flags and state (ASC_MC_QC_*). */
1867 uchar target_id; /* Device target identifier. */
1868 uchar target_lun; /* Device target logical unit number. */
1869 ADV_PADDR data_addr; /* Data buffer physical address. */
1870 ADV_DCNT data_cnt; /* Data count. Ucode sets to residual. */
1871 ADV_PADDR sense_addr;
1875 uchar cdb_len; /* SCSI CDB length. Must <= 16 bytes. */
1877 uchar done_status; /* Completion status. */
1878 uchar scsi_status; /* SCSI status byte. */
1879 uchar host_status; /* Ucode host status. */
1880 uchar sg_working_ix;
1881 uchar cdb[12]; /* SCSI CDB bytes 0-11. */
1882 ADV_PADDR sg_real_addr; /* SG list physical address. */
1883 ADV_PADDR scsiq_rptr;
1884 uchar cdb16[4]; /* SCSI CDB bytes 12-15. */
1885 ADV_VADDR scsiq_ptr;
1888 * End of microcode structure - 60 bytes. The rest of the structure
1889 * is used by the Adv Library and ignored by the microcode.
1892 ADV_SG_BLOCK *sg_list_ptr; /* SG list virtual address. */
1893 char *vdata_addr; /* Data buffer virtual address. */
1895 uchar pad[2]; /* Pad out to a word boundary. */
1899 * The following two structures are used to process Wide Board requests.
1901 * The ADV_SCSI_REQ_Q structure in adv_req_t is passed to the Adv Library
1902 * and microcode with the ADV_SCSI_REQ_Q field 'srb_ptr' pointing to the
1903 * adv_req_t. The adv_req_t structure 'cmndp' field in turn points to the
1904 * Mid-Level SCSI request structure.
1906 * Zero or more ADV_SG_BLOCK are used with each ADV_SCSI_REQ_Q. Each
1907 * ADV_SG_BLOCK structure holds 15 scatter-gather elements. Under Linux
1908 * up to 255 scatter-gather elements may be used per request or
1911 * Both structures must be 32 byte aligned.
1913 typedef struct adv_sgblk {
1914 ADV_SG_BLOCK sg_block; /* Sgblock structure. */
1915 uchar align[32]; /* Sgblock structure padding. */
1916 struct adv_sgblk *next_sgblkp; /* Next scatter-gather structure. */
1919 typedef struct adv_req {
1920 ADV_SCSI_REQ_Q scsi_req_q; /* Adv Library request structure. */
1921 uchar align[32]; /* Request structure padding. */
1922 struct scsi_cmnd *cmndp; /* Mid-Level SCSI command pointer. */
1923 adv_sgblk_t *sgblkp; /* Adv Library scatter-gather pointer. */
1924 struct adv_req *next_reqp; /* Next Request Structure. */
1928 * Adapter operation variable structure.
1930 * One structure is required per host adapter.
1932 * Field naming convention:
1934 * *_able indicates both whether a feature should be enabled or disabled
1935 * and whether a device isi capable of the feature. At initialization
1936 * this field may be set, but later if a device is found to be incapable
1937 * of the feature, the field is cleared.
1939 typedef struct adv_dvc_var {
1940 AdvPortAddr iop_base; /* I/O port address */
1941 ushort err_code; /* fatal error code */
1942 ushort bios_ctrl; /* BIOS control word, EEPROM word 12 */
1943 ushort wdtr_able; /* try WDTR for a device */
1944 ushort sdtr_able; /* try SDTR for a device */
1945 ushort ultra_able; /* try SDTR Ultra speed for a device */
1946 ushort sdtr_speed1; /* EEPROM SDTR Speed for TID 0-3 */
1947 ushort sdtr_speed2; /* EEPROM SDTR Speed for TID 4-7 */
1948 ushort sdtr_speed3; /* EEPROM SDTR Speed for TID 8-11 */
1949 ushort sdtr_speed4; /* EEPROM SDTR Speed for TID 12-15 */
1950 ushort tagqng_able; /* try tagged queuing with a device */
1951 ushort ppr_able; /* PPR message capable per TID bitmask. */
1952 uchar max_dvc_qng; /* maximum number of tagged commands per device */
1953 ushort start_motor; /* start motor command allowed */
1954 uchar scsi_reset_wait; /* delay in seconds after scsi bus reset */
1955 uchar chip_no; /* should be assigned by caller */
1956 uchar max_host_qng; /* maximum number of Q'ed command allowed */
1957 ushort no_scam; /* scam_tolerant of EEPROM */
1958 struct asc_board *drv_ptr; /* driver pointer to private structure */
1959 uchar chip_scsi_id; /* chip SCSI target ID */
1961 uchar bist_err_code;
1962 ADV_CARR_T *carrier_buf;
1963 ADV_CARR_T *carr_freelist; /* Carrier free list. */
1964 ADV_CARR_T *icq_sp; /* Initiator command queue stopper pointer. */
1965 ADV_CARR_T *irq_sp; /* Initiator response queue stopper pointer. */
1966 ushort carr_pending_cnt; /* Count of pending carriers. */
1967 struct adv_req *orig_reqp; /* adv_req_t memory block. */
1969 * Note: The following fields will not be used after initialization. The
1970 * driver may discard the buffer after initialization is done.
1972 ADV_DVC_CFG *cfg; /* temporary configuration structure */
1976 * Microcode idle loop commands
1978 #define IDLE_CMD_COMPLETED 0
1979 #define IDLE_CMD_STOP_CHIP 0x0001
1980 #define IDLE_CMD_STOP_CHIP_SEND_INT 0x0002
1981 #define IDLE_CMD_SEND_INT 0x0004
1982 #define IDLE_CMD_ABORT 0x0008
1983 #define IDLE_CMD_DEVICE_RESET 0x0010
1984 #define IDLE_CMD_SCSI_RESET_START 0x0020 /* Assert SCSI Bus Reset */
1985 #define IDLE_CMD_SCSI_RESET_END 0x0040 /* Deassert SCSI Bus Reset */
1986 #define IDLE_CMD_SCSIREQ 0x0080
1988 #define IDLE_CMD_STATUS_SUCCESS 0x0001
1989 #define IDLE_CMD_STATUS_FAILURE 0x0002
1992 * AdvSendIdleCmd() flag definitions.
1994 #define ADV_NOWAIT 0x01
1997 * Wait loop time out values.
1999 #define SCSI_WAIT_100_MSEC 100UL /* 100 milliseconds */
2000 #define SCSI_US_PER_MSEC 1000 /* microseconds per millisecond */
2001 #define SCSI_MAX_RETRY 10 /* retry count */
2003 #define ADV_ASYNC_RDMA_FAILURE 0x01 /* Fatal RDMA failure. */
2004 #define ADV_ASYNC_SCSI_BUS_RESET_DET 0x02 /* Detected SCSI Bus Reset. */
2005 #define ADV_ASYNC_CARRIER_READY_FAILURE 0x03 /* Carrier Ready failure. */
2006 #define ADV_RDMA_IN_CARR_AND_Q_INVALID 0x04 /* RDMAed-in data invalid. */
2008 #define ADV_HOST_SCSI_BUS_RESET 0x80 /* Host Initiated SCSI Bus Reset. */
2010 /* Read byte from a register. */
2011 #define AdvReadByteRegister(iop_base, reg_off) \
2012 (ADV_MEM_READB((iop_base) + (reg_off)))
2014 /* Write byte to a register. */
2015 #define AdvWriteByteRegister(iop_base, reg_off, byte) \
2016 (ADV_MEM_WRITEB((iop_base) + (reg_off), (byte)))
2018 /* Read word (2 bytes) from a register. */
2019 #define AdvReadWordRegister(iop_base, reg_off) \
2020 (ADV_MEM_READW((iop_base) + (reg_off)))
2022 /* Write word (2 bytes) to a register. */
2023 #define AdvWriteWordRegister(iop_base, reg_off, word) \
2024 (ADV_MEM_WRITEW((iop_base) + (reg_off), (word)))
2026 /* Write dword (4 bytes) to a register. */
2027 #define AdvWriteDWordRegister(iop_base, reg_off, dword) \
2028 (ADV_MEM_WRITEDW((iop_base) + (reg_off), (dword)))
2030 /* Read byte from LRAM. */
2031 #define AdvReadByteLram(iop_base, addr, byte) \
2033 ADV_MEM_WRITEW((iop_base) + IOPW_RAM_ADDR, (addr)); \
2034 (byte) = ADV_MEM_READB((iop_base) + IOPB_RAM_DATA); \
2037 /* Write byte to LRAM. */
2038 #define AdvWriteByteLram(iop_base, addr, byte) \
2039 (ADV_MEM_WRITEW((iop_base) + IOPW_RAM_ADDR, (addr)), \
2040 ADV_MEM_WRITEB((iop_base) + IOPB_RAM_DATA, (byte)))
2042 /* Read word (2 bytes) from LRAM. */
2043 #define AdvReadWordLram(iop_base, addr, word) \
2045 ADV_MEM_WRITEW((iop_base) + IOPW_RAM_ADDR, (addr)); \
2046 (word) = (ADV_MEM_READW((iop_base) + IOPW_RAM_DATA)); \
2049 /* Write word (2 bytes) to LRAM. */
2050 #define AdvWriteWordLram(iop_base, addr, word) \
2051 (ADV_MEM_WRITEW((iop_base) + IOPW_RAM_ADDR, (addr)), \
2052 ADV_MEM_WRITEW((iop_base) + IOPW_RAM_DATA, (word)))
2054 /* Write little-endian double word (4 bytes) to LRAM */
2055 /* Because of unspecified C language ordering don't use auto-increment. */
2056 #define AdvWriteDWordLramNoSwap(iop_base, addr, dword) \
2057 ((ADV_MEM_WRITEW((iop_base) + IOPW_RAM_ADDR, (addr)), \
2058 ADV_MEM_WRITEW((iop_base) + IOPW_RAM_DATA, \
2059 cpu_to_le16((ushort) ((dword) & 0xFFFF)))), \
2060 (ADV_MEM_WRITEW((iop_base) + IOPW_RAM_ADDR, (addr) + 2), \
2061 ADV_MEM_WRITEW((iop_base) + IOPW_RAM_DATA, \
2062 cpu_to_le16((ushort) ((dword >> 16) & 0xFFFF)))))
2064 /* Read word (2 bytes) from LRAM assuming that the address is already set. */
2065 #define AdvReadWordAutoIncLram(iop_base) \
2066 (ADV_MEM_READW((iop_base) + IOPW_RAM_DATA))
2068 /* Write word (2 bytes) to LRAM assuming that the address is already set. */
2069 #define AdvWriteWordAutoIncLram(iop_base, word) \
2070 (ADV_MEM_WRITEW((iop_base) + IOPW_RAM_DATA, (word)))
2073 * Define macro to check for Condor signature.
2075 * Evaluate to ADV_TRUE if a Condor chip is found the specified port
2076 * address 'iop_base'. Otherwise evalue to ADV_FALSE.
2078 #define AdvFindSignature(iop_base) \
2079 (((AdvReadByteRegister((iop_base), IOPB_CHIP_ID_1) == \
2080 ADV_CHIP_ID_BYTE) && \
2081 (AdvReadWordRegister((iop_base), IOPW_CHIP_ID_0) == \
2082 ADV_CHIP_ID_WORD)) ? ADV_TRUE : ADV_FALSE)
2085 * Define macro to Return the version number of the chip at 'iop_base'.
2087 * The second parameter 'bus_type' is currently unused.
2089 #define AdvGetChipVersion(iop_base, bus_type) \
2090 AdvReadByteRegister((iop_base), IOPB_CHIP_TYPE_REV)
2093 * Abort an SRB in the chip's RISC Memory. The 'srb_ptr' argument must
2094 * match the ASC_SCSI_REQ_Q 'srb_ptr' field.
2096 * If the request has not yet been sent to the device it will simply be
2097 * aborted from RISC memory. If the request is disconnected it will be
2098 * aborted on reselection by sending an Abort Message to the target ID.
2101 * ADV_TRUE(1) - Queue was successfully aborted.
2102 * ADV_FALSE(0) - Queue was not found on the active queue list.
2104 #define AdvAbortQueue(asc_dvc, scsiq) \
2105 AdvSendIdleCmd((asc_dvc), (ushort) IDLE_CMD_ABORT, \
2109 * Send a Bus Device Reset Message to the specified target ID.
2111 * All outstanding commands will be purged if sending the
2112 * Bus Device Reset Message is successful.
2115 * ADV_TRUE(1) - All requests on the target are purged.
2116 * ADV_FALSE(0) - Couldn't issue Bus Device Reset Message; Requests
2119 #define AdvResetDevice(asc_dvc, target_id) \
2120 AdvSendIdleCmd((asc_dvc), (ushort) IDLE_CMD_DEVICE_RESET, \
2121 (ADV_DCNT) (target_id))
2124 * SCSI Wide Type definition.
2126 #define ADV_SCSI_BIT_ID_TYPE ushort
2129 * AdvInitScsiTarget() 'cntl_flag' options.
2131 #define ADV_SCAN_LUN 0x01
2132 #define ADV_CAPINFO_NOLUN 0x02
2135 * Convert target id to target id bit mask.
2137 #define ADV_TID_TO_TIDMASK(tid) (0x01 << ((tid) & ADV_MAX_TID))
2140 * ASC_SCSI_REQ_Q 'done_status' and 'host_status' return values.
2143 #define QD_NO_STATUS 0x00 /* Request not completed yet. */
2144 #define QD_NO_ERROR 0x01
2145 #define QD_ABORTED_BY_HOST 0x02
2146 #define QD_WITH_ERROR 0x04
2148 #define QHSTA_NO_ERROR 0x00
2149 #define QHSTA_M_SEL_TIMEOUT 0x11
2150 #define QHSTA_M_DATA_OVER_RUN 0x12
2151 #define QHSTA_M_UNEXPECTED_BUS_FREE 0x13
2152 #define QHSTA_M_QUEUE_ABORTED 0x15
2153 #define QHSTA_M_SXFR_SDMA_ERR 0x16 /* SXFR_STATUS SCSI DMA Error */
2154 #define QHSTA_M_SXFR_SXFR_PERR 0x17 /* SXFR_STATUS SCSI Bus Parity Error */
2155 #define QHSTA_M_RDMA_PERR 0x18 /* RISC PCI DMA parity error */
2156 #define QHSTA_M_SXFR_OFF_UFLW 0x19 /* SXFR_STATUS Offset Underflow */
2157 #define QHSTA_M_SXFR_OFF_OFLW 0x20 /* SXFR_STATUS Offset Overflow */
2158 #define QHSTA_M_SXFR_WD_TMO 0x21 /* SXFR_STATUS Watchdog Timeout */
2159 #define QHSTA_M_SXFR_DESELECTED 0x22 /* SXFR_STATUS Deselected */
2160 /* Note: QHSTA_M_SXFR_XFR_OFLW is identical to QHSTA_M_DATA_OVER_RUN. */
2161 #define QHSTA_M_SXFR_XFR_OFLW 0x12 /* SXFR_STATUS Transfer Overflow */
2162 #define QHSTA_M_SXFR_XFR_PH_ERR 0x24 /* SXFR_STATUS Transfer Phase Error */
2163 #define QHSTA_M_SXFR_UNKNOWN_ERROR 0x25 /* SXFR_STATUS Unknown Error */
2164 #define QHSTA_M_SCSI_BUS_RESET 0x30 /* Request aborted from SBR */
2165 #define QHSTA_M_SCSI_BUS_RESET_UNSOL 0x31 /* Request aborted from unsol. SBR */
2166 #define QHSTA_M_BUS_DEVICE_RESET 0x32 /* Request aborted from BDR */
2167 #define QHSTA_M_DIRECTION_ERR 0x35 /* Data Phase mismatch */
2168 #define QHSTA_M_DIRECTION_ERR_HUNG 0x36 /* Data Phase mismatch and bus hang */
2169 #define QHSTA_M_WTM_TIMEOUT 0x41
2170 #define QHSTA_M_BAD_CMPL_STATUS_IN 0x42
2171 #define QHSTA_M_NO_AUTO_REQ_SENSE 0x43
2172 #define QHSTA_M_AUTO_REQ_SENSE_FAIL 0x44
2173 #define QHSTA_M_INVALID_DEVICE 0x45 /* Bad target ID */
2174 #define QHSTA_M_FROZEN_TIDQ 0x46 /* TID Queue frozen. */
2175 #define QHSTA_M_SGBACKUP_ERROR 0x47 /* Scatter-Gather backup error */
2178 * DvcGetPhyAddr() flag arguments
2180 #define ADV_IS_SCSIQ_FLAG 0x01 /* 'addr' is ASC_SCSI_REQ_Q pointer */
2181 #define ADV_ASCGETSGLIST_VADDR 0x02 /* 'addr' is AscGetSGList() virtual addr */
2182 #define ADV_IS_SENSE_FLAG 0x04 /* 'addr' is sense virtual pointer */
2183 #define ADV_IS_DATA_FLAG 0x08 /* 'addr' is data virtual pointer */
2184 #define ADV_IS_SGLIST_FLAG 0x10 /* 'addr' is sglist virtual pointer */
2185 #define ADV_IS_CARRIER_FLAG 0x20 /* 'addr' is ADV_CARR_T pointer */
2187 /* Return the address that is aligned at the next doubleword >= to 'addr'. */
2188 #define ADV_8BALIGN(addr) (((ulong) (addr) + 0x7) & ~0x7)
2189 #define ADV_16BALIGN(addr) (((ulong) (addr) + 0xF) & ~0xF)
2190 #define ADV_32BALIGN(addr) (((ulong) (addr) + 0x1F) & ~0x1F)
2193 * Total contiguous memory needed for driver SG blocks.
2195 * ADV_MAX_SG_LIST must be defined by a driver. It is the maximum
2196 * number of scatter-gather elements the driver supports in a
2200 #define ADV_SG_LIST_MAX_BYTE_SIZE \
2201 (sizeof(ADV_SG_BLOCK) * \
2202 ((ADV_MAX_SG_LIST + (NO_OF_SG_PER_BLOCK - 1))/NO_OF_SG_PER_BLOCK))
2204 /* struct asc_board flags */
2205 #define ASC_IS_WIDE_BOARD 0x04 /* AdvanSys Wide Board */
2207 #define ASC_NARROW_BOARD(boardp) (((boardp)->flags & ASC_IS_WIDE_BOARD) == 0)
2209 #define NO_ISA_DMA 0xff /* No ISA DMA Channel Used */
2211 #define ASC_INFO_SIZE 128 /* advansys_info() line size */
2213 #ifdef CONFIG_PROC_FS
2214 /* /proc/scsi/advansys/[0...] related definitions */
2215 #define ASC_PRTBUF_SIZE 2048
2216 #define ASC_PRTLINE_SIZE 160
2218 #define ASC_PRT_NEXT() \
2222 if (leftlen == 0) { \
2227 #endif /* CONFIG_PROC_FS */
2229 /* Asc Library return codes */
2232 #define ASC_NOERROR 1
2234 #define ASC_ERROR (-1)
2236 /* struct scsi_cmnd function return codes */
2237 #define STATUS_BYTE(byte) (byte)
2238 #define MSG_BYTE(byte) ((byte) << 8)
2239 #define HOST_BYTE(byte) ((byte) << 16)
2240 #define DRIVER_BYTE(byte) ((byte) << 24)
2242 #define ASC_STATS(shost, counter) ASC_STATS_ADD(shost, counter, 1)
2243 #ifndef ADVANSYS_STATS
2244 #define ASC_STATS_ADD(shost, counter, count)
2245 #else /* ADVANSYS_STATS */
2246 #define ASC_STATS_ADD(shost, counter, count) \
2247 (((struct asc_board *) shost_priv(shost))->asc_stats.counter += (count))
2248 #endif /* ADVANSYS_STATS */
2250 #define ASC_CEILING(val, unit) (((val) + ((unit) - 1))/(unit))
2252 /* If the result wraps when calculating tenths, return 0. */
2253 #define ASC_TENTHS(num, den) \
2254 (((10 * ((num)/(den))) > (((num) * 10)/(den))) ? \
2255 0 : ((((num) * 10)/(den)) - (10 * ((num)/(den)))))
2258 * Display a message to the console.
2260 #define ASC_PRINT(s) \
2262 printk("advansys: "); \
2266 #define ASC_PRINT1(s, a1) \
2268 printk("advansys: "); \
2269 printk((s), (a1)); \
2272 #define ASC_PRINT2(s, a1, a2) \
2274 printk("advansys: "); \
2275 printk((s), (a1), (a2)); \
2278 #define ASC_PRINT3(s, a1, a2, a3) \
2280 printk("advansys: "); \
2281 printk((s), (a1), (a2), (a3)); \
2284 #define ASC_PRINT4(s, a1, a2, a3, a4) \
2286 printk("advansys: "); \
2287 printk((s), (a1), (a2), (a3), (a4)); \
2290 #ifndef ADVANSYS_DEBUG
2292 #define ASC_DBG(lvl, s...)
2293 #define ASC_DBG_PRT_SCSI_HOST(lvl, s)
2294 #define ASC_DBG_PRT_ASC_SCSI_Q(lvl, scsiqp)
2295 #define ASC_DBG_PRT_ADV_SCSI_REQ_Q(lvl, scsiqp)
2296 #define ASC_DBG_PRT_ASC_QDONE_INFO(lvl, qdone)
2297 #define ADV_DBG_PRT_ADV_SCSI_REQ_Q(lvl, scsiqp)
2298 #define ASC_DBG_PRT_HEX(lvl, name, start, length)
2299 #define ASC_DBG_PRT_CDB(lvl, cdb, len)
2300 #define ASC_DBG_PRT_SENSE(lvl, sense, len)
2301 #define ASC_DBG_PRT_INQUIRY(lvl, inq, len)
2303 #else /* ADVANSYS_DEBUG */
2306 * Debugging Message Levels:
2308 * 1: High-Level Tracing
2309 * 2-N: Verbose Tracing
2312 #define ASC_DBG(lvl, format, arg...) { \
2313 if (asc_dbglvl >= (lvl)) \
2314 printk(KERN_DEBUG "%s: %s: " format, DRV_NAME, \
2315 __FUNCTION__ , ## arg); \
2318 #define ASC_DBG_PRT_SCSI_HOST(lvl, s) \
2320 if (asc_dbglvl >= (lvl)) { \
2321 asc_prt_scsi_host(s); \
2325 #define ASC_DBG_PRT_ASC_SCSI_Q(lvl, scsiqp) \
2327 if (asc_dbglvl >= (lvl)) { \
2328 asc_prt_asc_scsi_q(scsiqp); \
2332 #define ASC_DBG_PRT_ASC_QDONE_INFO(lvl, qdone) \
2334 if (asc_dbglvl >= (lvl)) { \
2335 asc_prt_asc_qdone_info(qdone); \
2339 #define ASC_DBG_PRT_ADV_SCSI_REQ_Q(lvl, scsiqp) \
2341 if (asc_dbglvl >= (lvl)) { \
2342 asc_prt_adv_scsi_req_q(scsiqp); \
2346 #define ASC_DBG_PRT_HEX(lvl, name, start, length) \
2348 if (asc_dbglvl >= (lvl)) { \
2349 asc_prt_hex((name), (start), (length)); \
2353 #define ASC_DBG_PRT_CDB(lvl, cdb, len) \
2354 ASC_DBG_PRT_HEX((lvl), "CDB", (uchar *) (cdb), (len));
2356 #define ASC_DBG_PRT_SENSE(lvl, sense, len) \
2357 ASC_DBG_PRT_HEX((lvl), "SENSE", (uchar *) (sense), (len));
2359 #define ASC_DBG_PRT_INQUIRY(lvl, inq, len) \
2360 ASC_DBG_PRT_HEX((lvl), "INQUIRY", (uchar *) (inq), (len));
2361 #endif /* ADVANSYS_DEBUG */
2363 #ifdef ADVANSYS_STATS
2365 /* Per board statistics structure */
2367 /* Driver Entrypoint Statistics */
2368 ADV_DCNT queuecommand; /* # calls to advansys_queuecommand() */
2369 ADV_DCNT reset; /* # calls to advansys_eh_bus_reset() */
2370 ADV_DCNT biosparam; /* # calls to advansys_biosparam() */
2371 ADV_DCNT interrupt; /* # advansys_interrupt() calls */
2372 ADV_DCNT callback; /* # calls to asc/adv_isr_callback() */
2373 ADV_DCNT done; /* # calls to request's scsi_done function */
2374 ADV_DCNT build_error; /* # asc/adv_build_req() ASC_ERROR returns. */
2375 ADV_DCNT adv_build_noreq; /* # adv_build_req() adv_req_t alloc. fail. */
2376 ADV_DCNT adv_build_nosg; /* # adv_build_req() adv_sgblk_t alloc. fail. */
2377 /* AscExeScsiQueue()/AdvExeScsiQueue() Statistics */
2378 ADV_DCNT exe_noerror; /* # ASC_NOERROR returns. */
2379 ADV_DCNT exe_busy; /* # ASC_BUSY returns. */
2380 ADV_DCNT exe_error; /* # ASC_ERROR returns. */
2381 ADV_DCNT exe_unknown; /* # unknown returns. */
2382 /* Data Transfer Statistics */
2383 ADV_DCNT cont_cnt; /* # non-scatter-gather I/O requests received */
2384 ADV_DCNT cont_xfer; /* # contiguous transfer 512-bytes */
2385 ADV_DCNT sg_cnt; /* # scatter-gather I/O requests received */
2386 ADV_DCNT sg_elem; /* # scatter-gather elements */
2387 ADV_DCNT sg_xfer; /* # scatter-gather transfer 512-bytes */
2389 #endif /* ADVANSYS_STATS */
2392 * Structure allocated for each board.
2394 * This structure is allocated by scsi_host_alloc() at the end
2395 * of the 'Scsi_Host' structure starting at the 'hostdata'
2396 * field. It is guaranteed to be allocated from DMA-able memory.
2400 uint flags; /* Board flags */
2403 ASC_DVC_VAR asc_dvc_var; /* Narrow board */
2404 ADV_DVC_VAR adv_dvc_var; /* Wide board */
2407 ASC_DVC_CFG asc_dvc_cfg; /* Narrow board */
2408 ADV_DVC_CFG adv_dvc_cfg; /* Wide board */
2410 ushort asc_n_io_port; /* Number I/O ports. */
2411 ADV_SCSI_BIT_ID_TYPE init_tidmask; /* Target init./valid mask */
2412 ushort reqcnt[ADV_MAX_TID + 1]; /* Starvation request count */
2413 ADV_SCSI_BIT_ID_TYPE queue_full; /* Queue full mask */
2414 ushort queue_full_cnt[ADV_MAX_TID + 1]; /* Queue full count */
2416 ASCEEP_CONFIG asc_eep; /* Narrow EEPROM config. */
2417 ADVEEP_3550_CONFIG adv_3550_eep; /* 3550 EEPROM config. */
2418 ADVEEP_38C0800_CONFIG adv_38C0800_eep; /* 38C0800 EEPROM config. */
2419 ADVEEP_38C1600_CONFIG adv_38C1600_eep; /* 38C1600 EEPROM config. */
2421 ulong last_reset; /* Saved last reset time */
2422 /* /proc/scsi/advansys/[0...] */
2423 char *prtbuf; /* /proc print buffer */
2424 #ifdef ADVANSYS_STATS
2425 struct asc_stats asc_stats; /* Board statistics */
2426 #endif /* ADVANSYS_STATS */
2428 * The following fields are used only for Narrow Boards.
2430 uchar sdtr_data[ASC_MAX_TID + 1]; /* SDTR information */
2432 * The following fields are used only for Wide Boards.
2434 void __iomem *ioremap_addr; /* I/O Memory remap address. */
2435 ushort ioport; /* I/O Port address. */
2436 adv_req_t *adv_reqp; /* Request structures. */
2437 adv_sgblk_t *adv_sgblkp; /* Scatter-gather structures. */
2438 ushort bios_signature; /* BIOS Signature. */
2439 ushort bios_version; /* BIOS Version. */
2440 ushort bios_codeseg; /* BIOS Code Segment. */
2441 ushort bios_codelen; /* BIOS Code Segment Length. */
2444 #define adv_dvc_to_board(adv_dvc) container_of(adv_dvc, struct asc_board, \
2445 dvc_var.adv_dvc_var)
2446 #define adv_dvc_to_pdev(adv_dvc) to_pci_dev(adv_dvc_to_board(adv_dvc)->dev)
2448 /* Overrun buffer used by all narrow boards. */
2449 static uchar overrun_buf[ASC_OVERRUN_BSIZE] = { 0 };
2451 #ifdef ADVANSYS_DEBUG
2452 static int asc_dbglvl = 3;
2455 * asc_prt_asc_dvc_var()
2457 static void asc_prt_asc_dvc_var(ASC_DVC_VAR *h)
2459 printk("ASC_DVC_VAR at addr 0x%lx\n", (ulong)h);
2461 printk(" iop_base 0x%x, err_code 0x%x, dvc_cntl 0x%x, bug_fix_cntl "
2462 "%d,\n", h->iop_base, h->err_code, h->dvc_cntl, h->bug_fix_cntl);
2464 printk(" bus_type %d, init_sdtr 0x%x,\n", h->bus_type,
2465 (unsigned)h->init_sdtr);
2467 printk(" sdtr_done 0x%x, use_tagged_qng 0x%x, unit_not_ready 0x%x, "
2468 "chip_no 0x%x,\n", (unsigned)h->sdtr_done,
2469 (unsigned)h->use_tagged_qng, (unsigned)h->unit_not_ready,
2470 (unsigned)h->chip_no);
2472 printk(" queue_full_or_busy 0x%x, start_motor 0x%x, scsi_reset_wait "
2473 "%u,\n", (unsigned)h->queue_full_or_busy,
2474 (unsigned)h->start_motor, (unsigned)h->scsi_reset_wait);
2476 printk(" is_in_int %u, max_total_qng %u, cur_total_qng %u, "
2477 "in_critical_cnt %u,\n", (unsigned)h->is_in_int,
2478 (unsigned)h->max_total_qng, (unsigned)h->cur_total_qng,
2479 (unsigned)h->in_critical_cnt);
2481 printk(" last_q_shortage %u, init_state 0x%x, no_scam 0x%x, "
2482 "pci_fix_asyn_xfer 0x%x,\n", (unsigned)h->last_q_shortage,
2483 (unsigned)h->init_state, (unsigned)h->no_scam,
2484 (unsigned)h->pci_fix_asyn_xfer);
2486 printk(" cfg 0x%lx\n", (ulong)h->cfg);
2490 * asc_prt_asc_dvc_cfg()
2492 static void asc_prt_asc_dvc_cfg(ASC_DVC_CFG *h)
2494 printk("ASC_DVC_CFG at addr 0x%lx\n", (ulong)h);
2496 printk(" can_tagged_qng 0x%x, cmd_qng_enabled 0x%x,\n",
2497 h->can_tagged_qng, h->cmd_qng_enabled);
2498 printk(" disc_enable 0x%x, sdtr_enable 0x%x,\n",
2499 h->disc_enable, h->sdtr_enable);
2501 printk(" chip_scsi_id %d, isa_dma_speed %d, isa_dma_channel %d, "
2502 "chip_version %d,\n", h->chip_scsi_id, h->isa_dma_speed,
2503 h->isa_dma_channel, h->chip_version);
2505 printk(" mcode_date 0x%x, mcode_version %d, overrun_buf 0x%p\n",
2506 h->mcode_date, h->mcode_version, h->overrun_buf);
2510 * asc_prt_adv_dvc_var()
2512 * Display an ADV_DVC_VAR structure.
2514 static void asc_prt_adv_dvc_var(ADV_DVC_VAR *h)
2516 printk(" ADV_DVC_VAR at addr 0x%lx\n", (ulong)h);
2518 printk(" iop_base 0x%lx, err_code 0x%x, ultra_able 0x%x\n",
2519 (ulong)h->iop_base, h->err_code, (unsigned)h->ultra_able);
2521 printk(" sdtr_able 0x%x, wdtr_able 0x%x\n",
2522 (unsigned)h->sdtr_able, (unsigned)h->wdtr_able);
2524 printk(" start_motor 0x%x, scsi_reset_wait 0x%x\n",
2525 (unsigned)h->start_motor, (unsigned)h->scsi_reset_wait);
2527 printk(" max_host_qng %u, max_dvc_qng %u, carr_freelist 0x%lxn\n",
2528 (unsigned)h->max_host_qng, (unsigned)h->max_dvc_qng,
2529 (ulong)h->carr_freelist);
2531 printk(" icq_sp 0x%lx, irq_sp 0x%lx\n",
2532 (ulong)h->icq_sp, (ulong)h->irq_sp);
2534 printk(" no_scam 0x%x, tagqng_able 0x%x\n",
2535 (unsigned)h->no_scam, (unsigned)h->tagqng_able);
2537 printk(" chip_scsi_id 0x%x, cfg 0x%lx\n",
2538 (unsigned)h->chip_scsi_id, (ulong)h->cfg);
2542 * asc_prt_adv_dvc_cfg()
2544 * Display an ADV_DVC_CFG structure.
2546 static void asc_prt_adv_dvc_cfg(ADV_DVC_CFG *h)
2548 printk(" ADV_DVC_CFG at addr 0x%lx\n", (ulong)h);
2550 printk(" disc_enable 0x%x, termination 0x%x\n",
2551 h->disc_enable, h->termination);
2553 printk(" chip_version 0x%x, mcode_date 0x%x\n",
2554 h->chip_version, h->mcode_date);
2556 printk(" mcode_version 0x%x, control_flag 0x%x\n",
2557 h->mcode_version, h->control_flag);
2561 * asc_prt_scsi_host()
2563 static void asc_prt_scsi_host(struct Scsi_Host *s)
2565 struct asc_board *boardp = shost_priv(s);
2567 printk("Scsi_Host at addr 0x%p, device %s\n", s, boardp->dev->bus_id);
2568 printk(" host_busy %u, host_no %d, last_reset %d,\n",
2569 s->host_busy, s->host_no, (unsigned)s->last_reset);
2571 printk(" base 0x%lx, io_port 0x%lx, irq %d,\n",
2572 (ulong)s->base, (ulong)s->io_port, boardp->irq);
2574 printk(" dma_channel %d, this_id %d, can_queue %d,\n",
2575 s->dma_channel, s->this_id, s->can_queue);
2577 printk(" cmd_per_lun %d, sg_tablesize %d, unchecked_isa_dma %d\n",
2578 s->cmd_per_lun, s->sg_tablesize, s->unchecked_isa_dma);
2580 if (ASC_NARROW_BOARD(boardp)) {
2581 asc_prt_asc_dvc_var(&boardp->dvc_var.asc_dvc_var);
2582 asc_prt_asc_dvc_cfg(&boardp->dvc_cfg.asc_dvc_cfg);
2584 asc_prt_adv_dvc_var(&boardp->dvc_var.adv_dvc_var);
2585 asc_prt_adv_dvc_cfg(&boardp->dvc_cfg.adv_dvc_cfg);
2592 * Print hexadecimal output in 4 byte groupings 32 bytes
2593 * or 8 double-words per line.
2595 static void asc_prt_hex(char *f, uchar *s, int l)
2602 printk("%s: (%d bytes)\n", f, l);
2604 for (i = 0; i < l; i += 32) {
2606 /* Display a maximum of 8 double-words per line. */
2607 if ((k = (l - i) / 4) >= 8) {
2614 for (j = 0; j < k; j++) {
2615 printk(" %2.2X%2.2X%2.2X%2.2X",
2616 (unsigned)s[i + (j * 4)],
2617 (unsigned)s[i + (j * 4) + 1],
2618 (unsigned)s[i + (j * 4) + 2],
2619 (unsigned)s[i + (j * 4) + 3]);
2627 printk(" %2.2X", (unsigned)s[i + (j * 4)]);
2630 printk(" %2.2X%2.2X",
2631 (unsigned)s[i + (j * 4)],
2632 (unsigned)s[i + (j * 4) + 1]);
2635 printk(" %2.2X%2.2X%2.2X",
2636 (unsigned)s[i + (j * 4) + 1],
2637 (unsigned)s[i + (j * 4) + 2],
2638 (unsigned)s[i + (j * 4) + 3]);
2647 * asc_prt_asc_scsi_q()
2649 static void asc_prt_asc_scsi_q(ASC_SCSI_Q *q)
2654 printk("ASC_SCSI_Q at addr 0x%lx\n", (ulong)q);
2657 (" target_ix 0x%x, target_lun %u, srb_ptr 0x%lx, tag_code 0x%x,\n",
2658 q->q2.target_ix, q->q1.target_lun, (ulong)q->q2.srb_ptr,
2662 (" data_addr 0x%lx, data_cnt %lu, sense_addr 0x%lx, sense_len %u,\n",
2663 (ulong)le32_to_cpu(q->q1.data_addr),
2664 (ulong)le32_to_cpu(q->q1.data_cnt),
2665 (ulong)le32_to_cpu(q->q1.sense_addr), q->q1.sense_len);
2667 printk(" cdbptr 0x%lx, cdb_len %u, sg_head 0x%lx, sg_queue_cnt %u\n",
2668 (ulong)q->cdbptr, q->q2.cdb_len,
2669 (ulong)q->sg_head, q->q1.sg_queue_cnt);
2673 printk("ASC_SG_HEAD at addr 0x%lx\n", (ulong)sgp);
2674 printk(" entry_cnt %u, queue_cnt %u\n", sgp->entry_cnt,
2676 for (i = 0; i < sgp->entry_cnt; i++) {
2677 printk(" [%u]: addr 0x%lx, bytes %lu\n",
2678 i, (ulong)le32_to_cpu(sgp->sg_list[i].addr),
2679 (ulong)le32_to_cpu(sgp->sg_list[i].bytes));
2686 * asc_prt_asc_qdone_info()
2688 static void asc_prt_asc_qdone_info(ASC_QDONE_INFO *q)
2690 printk("ASC_QDONE_INFO at addr 0x%lx\n", (ulong)q);
2691 printk(" srb_ptr 0x%lx, target_ix %u, cdb_len %u, tag_code %u,\n",
2692 (ulong)q->d2.srb_ptr, q->d2.target_ix, q->d2.cdb_len,
2695 (" done_stat 0x%x, host_stat 0x%x, scsi_stat 0x%x, scsi_msg 0x%x\n",
2696 q->d3.done_stat, q->d3.host_stat, q->d3.scsi_stat, q->d3.scsi_msg);
2700 * asc_prt_adv_sgblock()
2702 * Display an ADV_SG_BLOCK structure.
2704 static void asc_prt_adv_sgblock(int sgblockno, ADV_SG_BLOCK *b)
2708 printk(" ASC_SG_BLOCK at addr 0x%lx (sgblockno %d)\n",
2709 (ulong)b, sgblockno);
2710 printk(" sg_cnt %u, sg_ptr 0x%lx\n",
2711 b->sg_cnt, (ulong)le32_to_cpu(b->sg_ptr));
2712 BUG_ON(b->sg_cnt > NO_OF_SG_PER_BLOCK);
2714 BUG_ON(b->sg_cnt != NO_OF_SG_PER_BLOCK);
2715 for (i = 0; i < b->sg_cnt; i++) {
2716 printk(" [%u]: sg_addr 0x%lx, sg_count 0x%lx\n",
2717 i, (ulong)b->sg_list[i].sg_addr,
2718 (ulong)b->sg_list[i].sg_count);
2723 * asc_prt_adv_scsi_req_q()
2725 * Display an ADV_SCSI_REQ_Q structure.
2727 static void asc_prt_adv_scsi_req_q(ADV_SCSI_REQ_Q *q)
2730 struct asc_sg_block *sg_ptr;
2732 printk("ADV_SCSI_REQ_Q at addr 0x%lx\n", (ulong)q);
2734 printk(" target_id %u, target_lun %u, srb_ptr 0x%lx, a_flag 0x%x\n",
2735 q->target_id, q->target_lun, (ulong)q->srb_ptr, q->a_flag);
2737 printk(" cntl 0x%x, data_addr 0x%lx, vdata_addr 0x%lx\n",
2738 q->cntl, (ulong)le32_to_cpu(q->data_addr), (ulong)q->vdata_addr);
2740 printk(" data_cnt %lu, sense_addr 0x%lx, sense_len %u,\n",
2741 (ulong)le32_to_cpu(q->data_cnt),
2742 (ulong)le32_to_cpu(q->sense_addr), q->sense_len);
2745 (" cdb_len %u, done_status 0x%x, host_status 0x%x, scsi_status 0x%x\n",
2746 q->cdb_len, q->done_status, q->host_status, q->scsi_status);
2748 printk(" sg_working_ix 0x%x, target_cmd %u\n",
2749 q->sg_working_ix, q->target_cmd);
2751 printk(" scsiq_rptr 0x%lx, sg_real_addr 0x%lx, sg_list_ptr 0x%lx\n",
2752 (ulong)le32_to_cpu(q->scsiq_rptr),
2753 (ulong)le32_to_cpu(q->sg_real_addr), (ulong)q->sg_list_ptr);
2755 /* Display the request's ADV_SG_BLOCK structures. */
2756 if (q->sg_list_ptr != NULL) {
2760 * 'sg_ptr' is a physical address. Convert it to a virtual
2761 * address by indexing 'sg_blk_cnt' into the virtual address
2762 * array 'sg_list_ptr'.
2764 * XXX - Assumes all SG physical blocks are virtually contiguous.
2767 &(((ADV_SG_BLOCK *)(q->sg_list_ptr))[sg_blk_cnt]);
2768 asc_prt_adv_sgblock(sg_blk_cnt, sg_ptr);
2769 if (sg_ptr->sg_ptr == 0) {
2776 #endif /* ADVANSYS_DEBUG */
2781 * Return suitable for printing on the console with the argument
2782 * adapter's configuration information.
2784 * Note: The information line should not exceed ASC_INFO_SIZE bytes,
2785 * otherwise the static 'info' array will be overrun.
2787 static const char *advansys_info(struct Scsi_Host *shost)
2789 static char info[ASC_INFO_SIZE];
2790 struct asc_board *boardp = shost_priv(shost);
2791 ASC_DVC_VAR *asc_dvc_varp;
2792 ADV_DVC_VAR *adv_dvc_varp;
2794 char *widename = NULL;
2796 if (ASC_NARROW_BOARD(boardp)) {
2797 asc_dvc_varp = &boardp->dvc_var.asc_dvc_var;
2798 ASC_DBG(1, "begin\n");
2799 if (asc_dvc_varp->bus_type & ASC_IS_ISA) {
2800 if ((asc_dvc_varp->bus_type & ASC_IS_ISAPNP) ==
2802 busname = "ISA PnP";
2807 "AdvanSys SCSI %s: %s: IO 0x%lX-0x%lX, IRQ 0x%X, DMA 0x%X",
2808 ASC_VERSION, busname,
2809 (ulong)shost->io_port,
2810 (ulong)shost->io_port + ASC_IOADR_GAP - 1,
2811 boardp->irq, shost->dma_channel);
2813 if (asc_dvc_varp->bus_type & ASC_IS_VL) {
2815 } else if (asc_dvc_varp->bus_type & ASC_IS_EISA) {
2817 } else if (asc_dvc_varp->bus_type & ASC_IS_PCI) {
2818 if ((asc_dvc_varp->bus_type & ASC_IS_PCI_ULTRA)
2819 == ASC_IS_PCI_ULTRA) {
2820 busname = "PCI Ultra";
2826 shost_printk(KERN_ERR, shost, "unknown bus "
2827 "type %d\n", asc_dvc_varp->bus_type);
2830 "AdvanSys SCSI %s: %s: IO 0x%lX-0x%lX, IRQ 0x%X",
2831 ASC_VERSION, busname, (ulong)shost->io_port,
2832 (ulong)shost->io_port + ASC_IOADR_GAP - 1,
2837 * Wide Adapter Information
2839 * Memory-mapped I/O is used instead of I/O space to access
2840 * the adapter, but display the I/O Port range. The Memory
2841 * I/O address is displayed through the driver /proc file.
2843 adv_dvc_varp = &boardp->dvc_var.adv_dvc_var;
2844 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
2845 widename = "Ultra-Wide";
2846 } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
2847 widename = "Ultra2-Wide";
2849 widename = "Ultra3-Wide";
2852 "AdvanSys SCSI %s: PCI %s: PCIMEM 0x%lX-0x%lX, IRQ 0x%X",
2853 ASC_VERSION, widename, (ulong)adv_dvc_varp->iop_base,
2854 (ulong)adv_dvc_varp->iop_base + boardp->asc_n_io_port - 1, boardp->irq);
2856 BUG_ON(strlen(info) >= ASC_INFO_SIZE);
2857 ASC_DBG(1, "end\n");
2861 #ifdef CONFIG_PROC_FS
2865 * If 'cp' is NULL print to the console, otherwise print to a buffer.
2867 * Return 0 if printing to the console, otherwise return the number of
2868 * bytes written to the buffer.
2870 * Note: If any single line is greater than ASC_PRTLINE_SIZE bytes the stack
2871 * will be corrupted. 's[]' is defined to be ASC_PRTLINE_SIZE bytes.
2873 static int asc_prt_line(char *buf, int buflen, char *fmt, ...)
2877 char s[ASC_PRTLINE_SIZE];
2879 va_start(args, fmt);
2880 ret = vsprintf(s, fmt, args);
2881 BUG_ON(ret >= ASC_PRTLINE_SIZE);
2886 ret = min(buflen, ret);
2887 memcpy(buf, s, ret);
2894 * asc_prt_board_devices()
2896 * Print driver information for devices attached to the board.
2898 * Note: no single line should be greater than ASC_PRTLINE_SIZE,
2899 * cf. asc_prt_line().
2901 * Return the number of characters copied into 'cp'. No more than
2902 * 'cplen' characters will be copied to 'cp'.
2904 static int asc_prt_board_devices(struct Scsi_Host *shost, char *cp, int cplen)
2906 struct asc_board *boardp = shost_priv(shost);
2916 len = asc_prt_line(cp, leftlen,
2917 "\nDevice Information for AdvanSys SCSI Host %d:\n",
2921 if (ASC_NARROW_BOARD(boardp)) {
2922 chip_scsi_id = boardp->dvc_cfg.asc_dvc_cfg.chip_scsi_id;
2924 chip_scsi_id = boardp->dvc_var.adv_dvc_var.chip_scsi_id;
2927 len = asc_prt_line(cp, leftlen, "Target IDs Detected:");
2929 for (i = 0; i <= ADV_MAX_TID; i++) {
2930 if (boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) {
2931 len = asc_prt_line(cp, leftlen, " %X,", i);
2935 len = asc_prt_line(cp, leftlen, " (%X=Host Adapter)\n", chip_scsi_id);
2942 * Display Wide Board BIOS Information.
2944 static int asc_prt_adv_bios(struct Scsi_Host *shost, char *cp, int cplen)
2946 struct asc_board *boardp = shost_priv(shost);
2950 ushort major, minor, letter;
2955 len = asc_prt_line(cp, leftlen, "\nROM BIOS Version: ");
2959 * If the BIOS saved a valid signature, then fill in
2960 * the BIOS code segment base address.
2962 if (boardp->bios_signature != 0x55AA) {
2963 len = asc_prt_line(cp, leftlen, "Disabled or Pre-3.1\n");
2965 len = asc_prt_line(cp, leftlen,
2966 "BIOS either disabled or Pre-3.1. If it is pre-3.1, then a newer version\n");
2968 len = asc_prt_line(cp, leftlen,
2969 "can be found at the ConnectCom FTP site: ftp://ftp.connectcom.net/pub\n");
2972 major = (boardp->bios_version >> 12) & 0xF;
2973 minor = (boardp->bios_version >> 8) & 0xF;
2974 letter = (boardp->bios_version & 0xFF);
2976 len = asc_prt_line(cp, leftlen, "%d.%d%c\n",
2978 letter >= 26 ? '?' : letter + 'A');
2982 * Current available ROM BIOS release is 3.1I for UW
2983 * and 3.2I for U2W. This code doesn't differentiate
2984 * UW and U2W boards.
2986 if (major < 3 || (major <= 3 && minor < 1) ||
2987 (major <= 3 && minor <= 1 && letter < ('I' - 'A'))) {
2988 len = asc_prt_line(cp, leftlen,
2989 "Newer version of ROM BIOS is available at the ConnectCom FTP site:\n");
2991 len = asc_prt_line(cp, leftlen,
2992 "ftp://ftp.connectcom.net/pub\n");
3001 * Add serial number to information bar if signature AAh
3002 * is found in at bit 15-9 (7 bits) of word 1.
3004 * Serial Number consists fo 12 alpha-numeric digits.
3006 * 1 - Product type (A,B,C,D..) Word0: 15-13 (3 bits)
3007 * 2 - MFG Location (A,B,C,D..) Word0: 12-10 (3 bits)
3008 * 3-4 - Product ID (0-99) Word0: 9-0 (10 bits)
3009 * 5 - Product revision (A-J) Word0: " "
3011 * Signature Word1: 15-9 (7 bits)
3012 * 6 - Year (0-9) Word1: 8-6 (3 bits) & Word2: 15 (1 bit)
3013 * 7-8 - Week of the year (1-52) Word1: 5-0 (6 bits)
3015 * 9-12 - Serial Number (A001-Z999) Word2: 14-0 (15 bits)
3017 * Note 1: Only production cards will have a serial number.
3019 * Note 2: Signature is most significant 7 bits (0xFE).
3021 * Returns ASC_TRUE if serial number found, otherwise returns ASC_FALSE.
3023 static int asc_get_eeprom_string(ushort *serialnum, uchar *cp)
3027 if ((serialnum[1] & 0xFE00) != ((ushort)0xAA << 8)) {
3031 * First word - 6 digits.
3035 /* Product type - 1st digit. */
3036 if ((*cp = 'A' + ((w & 0xE000) >> 13)) == 'H') {
3037 /* Product type is P=Prototype */
3042 /* Manufacturing location - 2nd digit. */
3043 *cp++ = 'A' + ((w & 0x1C00) >> 10);
3045 /* Product ID - 3rd, 4th digits. */
3047 *cp++ = '0' + (num / 100);
3049 *cp++ = '0' + (num / 10);
3051 /* Product revision - 5th digit. */
3052 *cp++ = 'A' + (num % 10);
3062 * If bit 15 of third word is set, then the
3063 * last digit of the year is greater than 7.
3065 if (serialnum[2] & 0x8000) {
3066 *cp++ = '8' + ((w & 0x1C0) >> 6);
3068 *cp++ = '0' + ((w & 0x1C0) >> 6);
3071 /* Week of year - 7th, 8th digits. */
3073 *cp++ = '0' + num / 10;
3080 w = serialnum[2] & 0x7FFF;
3082 /* Serial number - 9th digit. */
3083 *cp++ = 'A' + (w / 1000);
3085 /* 10th, 11th, 12th digits. */
3087 *cp++ = '0' + num / 100;
3089 *cp++ = '0' + num / 10;
3093 *cp = '\0'; /* Null Terminate the string. */
3099 * asc_prt_asc_board_eeprom()
3101 * Print board EEPROM configuration.
3103 * Note: no single line should be greater than ASC_PRTLINE_SIZE,
3104 * cf. asc_prt_line().
3106 * Return the number of characters copied into 'cp'. No more than
3107 * 'cplen' characters will be copied to 'cp'.
3109 static int asc_prt_asc_board_eeprom(struct Scsi_Host *shost, char *cp, int cplen)
3111 struct asc_board *boardp = shost_priv(shost);
3112 ASC_DVC_VAR *asc_dvc_varp;
3119 int isa_dma_speed[] = { 10, 8, 7, 6, 5, 4, 3, 2 };
3120 #endif /* CONFIG_ISA */
3121 uchar serialstr[13];
3123 asc_dvc_varp = &boardp->dvc_var.asc_dvc_var;
3124 ep = &boardp->eep_config.asc_eep;
3129 len = asc_prt_line(cp, leftlen,
3130 "\nEEPROM Settings for AdvanSys SCSI Host %d:\n",
3134 if (asc_get_eeprom_string((ushort *)&ep->adapter_info[0], serialstr)
3137 asc_prt_line(cp, leftlen, " Serial Number: %s\n",
3141 if (ep->adapter_info[5] == 0xBB) {
3142 len = asc_prt_line(cp, leftlen,
3143 " Default Settings Used for EEPROM-less Adapter.\n");
3146 len = asc_prt_line(cp, leftlen,
3147 " Serial Number Signature Not Present.\n");
3152 len = asc_prt_line(cp, leftlen,
3153 " Host SCSI ID: %u, Host Queue Size: %u, Device Queue Size: %u\n",
3154 ASC_EEP_GET_CHIP_ID(ep), ep->max_total_qng,
3158 len = asc_prt_line(cp, leftlen,
3159 " cntl 0x%x, no_scam 0x%x\n", ep->cntl, ep->no_scam);
3162 len = asc_prt_line(cp, leftlen, " Target ID: ");
3164 for (i = 0; i <= ASC_MAX_TID; i++) {
3165 len = asc_prt_line(cp, leftlen, " %d", i);
3168 len = asc_prt_line(cp, leftlen, "\n");
3171 len = asc_prt_line(cp, leftlen, " Disconnects: ");
3173 for (i = 0; i <= ASC_MAX_TID; i++) {
3174 len = asc_prt_line(cp, leftlen, " %c",
3176 disc_enable & ADV_TID_TO_TIDMASK(i)) ? 'Y' :
3180 len = asc_prt_line(cp, leftlen, "\n");
3183 len = asc_prt_line(cp, leftlen, " Command Queuing: ");
3185 for (i = 0; i <= ASC_MAX_TID; i++) {
3186 len = asc_prt_line(cp, leftlen, " %c",
3188 use_cmd_qng & ADV_TID_TO_TIDMASK(i)) ? 'Y' :
3192 len = asc_prt_line(cp, leftlen, "\n");
3195 len = asc_prt_line(cp, leftlen, " Start Motor: ");
3197 for (i = 0; i <= ASC_MAX_TID; i++) {
3198 len = asc_prt_line(cp, leftlen, " %c",
3200 start_motor & ADV_TID_TO_TIDMASK(i)) ? 'Y' :
3204 len = asc_prt_line(cp, leftlen, "\n");
3207 len = asc_prt_line(cp, leftlen, " Synchronous Transfer:");
3209 for (i = 0; i <= ASC_MAX_TID; i++) {
3210 len = asc_prt_line(cp, leftlen, " %c",
3212 init_sdtr & ADV_TID_TO_TIDMASK(i)) ? 'Y' :
3216 len = asc_prt_line(cp, leftlen, "\n");
3220 if (asc_dvc_varp->bus_type & ASC_IS_ISA) {
3221 len = asc_prt_line(cp, leftlen,
3222 " Host ISA DMA speed: %d MB/S\n",
3223 isa_dma_speed[ASC_EEP_GET_DMA_SPD(ep)]);
3226 #endif /* CONFIG_ISA */
3232 * asc_prt_adv_board_eeprom()
3234 * Print board EEPROM configuration.
3236 * Note: no single line should be greater than ASC_PRTLINE_SIZE,
3237 * cf. asc_prt_line().
3239 * Return the number of characters copied into 'cp'. No more than
3240 * 'cplen' characters will be copied to 'cp'.
3242 static int asc_prt_adv_board_eeprom(struct Scsi_Host *shost, char *cp, int cplen)
3244 struct asc_board *boardp = shost_priv(shost);
3245 ADV_DVC_VAR *adv_dvc_varp;
3251 uchar serialstr[13];
3252 ADVEEP_3550_CONFIG *ep_3550 = NULL;
3253 ADVEEP_38C0800_CONFIG *ep_38C0800 = NULL;
3254 ADVEEP_38C1600_CONFIG *ep_38C1600 = NULL;
3257 ushort sdtr_speed = 0;
3259 adv_dvc_varp = &boardp->dvc_var.adv_dvc_var;
3260 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
3261 ep_3550 = &boardp->eep_config.adv_3550_eep;
3262 } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
3263 ep_38C0800 = &boardp->eep_config.adv_38C0800_eep;
3265 ep_38C1600 = &boardp->eep_config.adv_38C1600_eep;
3271 len = asc_prt_line(cp, leftlen,
3272 "\nEEPROM Settings for AdvanSys SCSI Host %d:\n",
3276 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
3277 wordp = &ep_3550->serial_number_word1;
3278 } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
3279 wordp = &ep_38C0800->serial_number_word1;
3281 wordp = &ep_38C1600->serial_number_word1;
3284 if (asc_get_eeprom_string(wordp, serialstr) == ASC_TRUE) {
3286 asc_prt_line(cp, leftlen, " Serial Number: %s\n",
3290 len = asc_prt_line(cp, leftlen,
3291 " Serial Number Signature Not Present.\n");
3295 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
3296 len = asc_prt_line(cp, leftlen,
3297 " Host SCSI ID: %u, Host Queue Size: %u, Device Queue Size: %u\n",
3298 ep_3550->adapter_scsi_id,
3299 ep_3550->max_host_qng, ep_3550->max_dvc_qng);
3301 } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
3302 len = asc_prt_line(cp, leftlen,
3303 " Host SCSI ID: %u, Host Queue Size: %u, Device Queue Size: %u\n",
3304 ep_38C0800->adapter_scsi_id,
3305 ep_38C0800->max_host_qng,
3306 ep_38C0800->max_dvc_qng);
3309 len = asc_prt_line(cp, leftlen,
3310 " Host SCSI ID: %u, Host Queue Size: %u, Device Queue Size: %u\n",
3311 ep_38C1600->adapter_scsi_id,
3312 ep_38C1600->max_host_qng,
3313 ep_38C1600->max_dvc_qng);
3316 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
3317 word = ep_3550->termination;
3318 } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
3319 word = ep_38C0800->termination_lvd;
3321 word = ep_38C1600->termination_lvd;
3325 termstr = "Low Off/High Off";
3328 termstr = "Low Off/High On";
3331 termstr = "Low On/High On";
3335 termstr = "Automatic";
3339 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
3340 len = asc_prt_line(cp, leftlen,
3341 " termination: %u (%s), bios_ctrl: 0x%x\n",
3342 ep_3550->termination, termstr,
3343 ep_3550->bios_ctrl);
3345 } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
3346 len = asc_prt_line(cp, leftlen,
3347 " termination: %u (%s), bios_ctrl: 0x%x\n",
3348 ep_38C0800->termination_lvd, termstr,
3349 ep_38C0800->bios_ctrl);
3352 len = asc_prt_line(cp, leftlen,
3353 " termination: %u (%s), bios_ctrl: 0x%x\n",
3354 ep_38C1600->termination_lvd, termstr,
3355 ep_38C1600->bios_ctrl);
3359 len = asc_prt_line(cp, leftlen, " Target ID: ");
3361 for (i = 0; i <= ADV_MAX_TID; i++) {
3362 len = asc_prt_line(cp, leftlen, " %X", i);
3365 len = asc_prt_line(cp, leftlen, "\n");
3368 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
3369 word = ep_3550->disc_enable;
3370 } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
3371 word = ep_38C0800->disc_enable;
3373 word = ep_38C1600->disc_enable;
3375 len = asc_prt_line(cp, leftlen, " Disconnects: ");
3377 for (i = 0; i <= ADV_MAX_TID; i++) {
3378 len = asc_prt_line(cp, leftlen, " %c",
3379 (word & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
3382 len = asc_prt_line(cp, leftlen, "\n");
3385 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
3386 word = ep_3550->tagqng_able;
3387 } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
3388 word = ep_38C0800->tagqng_able;
3390 word = ep_38C1600->tagqng_able;
3392 len = asc_prt_line(cp, leftlen, " Command Queuing: ");
3394 for (i = 0; i <= ADV_MAX_TID; i++) {
3395 len = asc_prt_line(cp, leftlen, " %c",
3396 (word & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
3399 len = asc_prt_line(cp, leftlen, "\n");
3402 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
3403 word = ep_3550->start_motor;
3404 } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
3405 word = ep_38C0800->start_motor;
3407 word = ep_38C1600->start_motor;
3409 len = asc_prt_line(cp, leftlen, " Start Motor: ");
3411 for (i = 0; i <= ADV_MAX_TID; i++) {
3412 len = asc_prt_line(cp, leftlen, " %c",
3413 (word & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
3416 len = asc_prt_line(cp, leftlen, "\n");
3419 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
3420 len = asc_prt_line(cp, leftlen, " Synchronous Transfer:");
3422 for (i = 0; i <= ADV_MAX_TID; i++) {
3423 len = asc_prt_line(cp, leftlen, " %c",
3425 sdtr_able & ADV_TID_TO_TIDMASK(i)) ?
3429 len = asc_prt_line(cp, leftlen, "\n");
3433 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
3434 len = asc_prt_line(cp, leftlen, " Ultra Transfer: ");
3436 for (i = 0; i <= ADV_MAX_TID; i++) {
3437 len = asc_prt_line(cp, leftlen, " %c",
3439 ultra_able & ADV_TID_TO_TIDMASK(i))
3443 len = asc_prt_line(cp, leftlen, "\n");
3447 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
3448 word = ep_3550->wdtr_able;
3449 } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
3450 word = ep_38C0800->wdtr_able;
3452 word = ep_38C1600->wdtr_able;
3454 len = asc_prt_line(cp, leftlen, " Wide Transfer: ");
3456 for (i = 0; i <= ADV_MAX_TID; i++) {
3457 len = asc_prt_line(cp, leftlen, " %c",
3458 (word & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
3461 len = asc_prt_line(cp, leftlen, "\n");
3464 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800 ||
3465 adv_dvc_varp->chip_type == ADV_CHIP_ASC38C1600) {
3466 len = asc_prt_line(cp, leftlen,
3467 " Synchronous Transfer Speed (Mhz):\n ");
3469 for (i = 0; i <= ADV_MAX_TID; i++) {
3473 sdtr_speed = adv_dvc_varp->sdtr_speed1;
3474 } else if (i == 4) {
3475 sdtr_speed = adv_dvc_varp->sdtr_speed2;
3476 } else if (i == 8) {
3477 sdtr_speed = adv_dvc_varp->sdtr_speed3;
3478 } else if (i == 12) {
3479 sdtr_speed = adv_dvc_varp->sdtr_speed4;
3481 switch (sdtr_speed & ADV_MAX_TID) {
3504 len = asc_prt_line(cp, leftlen, "%X:%s ", i, speed_str);
3507 len = asc_prt_line(cp, leftlen, "\n ");
3512 len = asc_prt_line(cp, leftlen, "\n");
3520 * asc_prt_driver_conf()
3522 * Note: no single line should be greater than ASC_PRTLINE_SIZE,
3523 * cf. asc_prt_line().
3525 * Return the number of characters copied into 'cp'. No more than
3526 * 'cplen' characters will be copied to 'cp'.
3528 static int asc_prt_driver_conf(struct Scsi_Host *shost, char *cp, int cplen)
3530 struct asc_board *boardp = shost_priv(shost);
3539 len = asc_prt_line(cp, leftlen,
3540 "\nLinux Driver Configuration and Information for AdvanSys SCSI Host %d:\n",
3544 len = asc_prt_line(cp, leftlen,
3545 " host_busy %u, last_reset %u, max_id %u, max_lun %u, max_channel %u\n",
3546 shost->host_busy, shost->last_reset, shost->max_id,
3547 shost->max_lun, shost->max_channel);
3550 len = asc_prt_line(cp, leftlen,
3551 " unique_id %d, can_queue %d, this_id %d, sg_tablesize %u, cmd_per_lun %u\n",
3552 shost->unique_id, shost->can_queue, shost->this_id,
3553 shost->sg_tablesize, shost->cmd_per_lun);
3556 len = asc_prt_line(cp, leftlen,
3557 " unchecked_isa_dma %d, use_clustering %d\n",
3558 shost->unchecked_isa_dma, shost->use_clustering);
3561 len = asc_prt_line(cp, leftlen,
3562 " flags 0x%x, last_reset 0x%x, jiffies 0x%x, asc_n_io_port 0x%x\n",
3563 boardp->flags, boardp->last_reset, jiffies,
3564 boardp->asc_n_io_port);
3567 len = asc_prt_line(cp, leftlen, " io_port 0x%x\n", shost->io_port);
3570 if (ASC_NARROW_BOARD(boardp)) {
3571 chip_scsi_id = boardp->dvc_cfg.asc_dvc_cfg.chip_scsi_id;
3573 chip_scsi_id = boardp->dvc_var.adv_dvc_var.chip_scsi_id;
3580 * asc_prt_asc_board_info()
3582 * Print dynamic board configuration information.
3584 * Note: no single line should be greater than ASC_PRTLINE_SIZE,
3585 * cf. asc_prt_line().
3587 * Return the number of characters copied into 'cp'. No more than
3588 * 'cplen' characters will be copied to 'cp'.
3590 static int asc_prt_asc_board_info(struct Scsi_Host *shost, char *cp, int cplen)
3592 struct asc_board *boardp = shost_priv(shost);
3600 int renegotiate = 0;
3602 v = &boardp->dvc_var.asc_dvc_var;
3603 c = &boardp->dvc_cfg.asc_dvc_cfg;
3604 chip_scsi_id = c->chip_scsi_id;
3609 len = asc_prt_line(cp, leftlen,
3610 "\nAsc Library Configuration and Statistics for AdvanSys SCSI Host %d:\n",
3614 len = asc_prt_line(cp, leftlen, " chip_version %u, mcode_date 0x%x, "
3615 "mcode_version 0x%x, err_code %u\n",
3616 c->chip_version, c->mcode_date, c->mcode_version,
3620 /* Current number of commands waiting for the host. */
3621 len = asc_prt_line(cp, leftlen,
3622 " Total Command Pending: %d\n", v->cur_total_qng);
3625 len = asc_prt_line(cp, leftlen, " Command Queuing:");
3627 for (i = 0; i <= ASC_MAX_TID; i++) {
3628 if ((chip_scsi_id == i) ||
3629 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
3632 len = asc_prt_line(cp, leftlen, " %X:%c",
3635 use_tagged_qng & ADV_TID_TO_TIDMASK(i)) ?
3639 len = asc_prt_line(cp, leftlen, "\n");
3642 /* Current number of commands waiting for a device. */
3643 len = asc_prt_line(cp, leftlen, " Command Queue Pending:");
3645 for (i = 0; i <= ASC_MAX_TID; i++) {
3646 if ((chip_scsi_id == i) ||
3647 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
3650 len = asc_prt_line(cp, leftlen, " %X:%u", i, v->cur_dvc_qng[i]);
3653 len = asc_prt_line(cp, leftlen, "\n");
3656 /* Current limit on number of commands that can be sent to a device. */
3657 len = asc_prt_line(cp, leftlen, " Command Queue Limit:");
3659 for (i = 0; i <= ASC_MAX_TID; i++) {
3660 if ((chip_scsi_id == i) ||
3661 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
3664 len = asc_prt_line(cp, leftlen, " %X:%u", i, v->max_dvc_qng[i]);
3667 len = asc_prt_line(cp, leftlen, "\n");
3670 /* Indicate whether the device has returned queue full status. */
3671 len = asc_prt_line(cp, leftlen, " Command Queue Full:");
3673 for (i = 0; i <= ASC_MAX_TID; i++) {
3674 if ((chip_scsi_id == i) ||
3675 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
3678 if (boardp->queue_full & ADV_TID_TO_TIDMASK(i)) {
3679 len = asc_prt_line(cp, leftlen, " %X:Y-%d",
3680 i, boardp->queue_full_cnt[i]);
3682 len = asc_prt_line(cp, leftlen, " %X:N", i);
3686 len = asc_prt_line(cp, leftlen, "\n");
3689 len = asc_prt_line(cp, leftlen, " Synchronous Transfer:");
3691 for (i = 0; i <= ASC_MAX_TID; i++) {
3692 if ((chip_scsi_id == i) ||
3693 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
3696 len = asc_prt_line(cp, leftlen, " %X:%c",
3699 sdtr_done & ADV_TID_TO_TIDMASK(i)) ? 'Y' :
3703 len = asc_prt_line(cp, leftlen, "\n");
3706 for (i = 0; i <= ASC_MAX_TID; i++) {
3707 uchar syn_period_ix;
3709 if ((chip_scsi_id == i) ||
3710 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0) ||
3711 ((v->init_sdtr & ADV_TID_TO_TIDMASK(i)) == 0)) {
3715 len = asc_prt_line(cp, leftlen, " %X:", i);
3718 if ((boardp->sdtr_data[i] & ASC_SYN_MAX_OFFSET) == 0) {
3719 len = asc_prt_line(cp, leftlen, " Asynchronous");
3723 (boardp->sdtr_data[i] >> 4) & (v->max_sdtr_index -
3726 len = asc_prt_line(cp, leftlen,
3727 " Transfer Period Factor: %d (%d.%d Mhz),",
3728 v->sdtr_period_tbl[syn_period_ix],
3730 v->sdtr_period_tbl[syn_period_ix],
3737 len = asc_prt_line(cp, leftlen, " REQ/ACK Offset: %d",
3739 sdtr_data[i] & ASC_SYN_MAX_OFFSET);
3743 if ((v->sdtr_done & ADV_TID_TO_TIDMASK(i)) == 0) {
3744 len = asc_prt_line(cp, leftlen, "*\n");
3747 len = asc_prt_line(cp, leftlen, "\n");
3753 len = asc_prt_line(cp, leftlen,
3754 " * = Re-negotiation pending before next command.\n");
3762 * asc_prt_adv_board_info()
3764 * Print dynamic board configuration information.
3766 * Note: no single line should be greater than ASC_PRTLINE_SIZE,
3767 * cf. asc_prt_line().
3769 * Return the number of characters copied into 'cp'. No more than
3770 * 'cplen' characters will be copied to 'cp'.
3772 static int asc_prt_adv_board_info(struct Scsi_Host *shost, char *cp, int cplen)
3774 struct asc_board *boardp = shost_priv(shost);
3781 AdvPortAddr iop_base;
3782 ushort chip_scsi_id;
3786 ushort sdtr_able, wdtr_able;
3787 ushort wdtr_done, sdtr_done;
3789 int renegotiate = 0;
3791 v = &boardp->dvc_var.adv_dvc_var;
3792 c = &boardp->dvc_cfg.adv_dvc_cfg;
3793 iop_base = v->iop_base;
3794 chip_scsi_id = v->chip_scsi_id;
3799 len = asc_prt_line(cp, leftlen,
3800 "\nAdv Library Configuration and Statistics for AdvanSys SCSI Host %d:\n",
3804 len = asc_prt_line(cp, leftlen,
3805 " iop_base 0x%lx, cable_detect: %X, err_code %u\n",
3807 AdvReadWordRegister(iop_base,
3808 IOPW_SCSI_CFG1) & CABLE_DETECT,
3812 len = asc_prt_line(cp, leftlen, " chip_version %u, mcode_date 0x%x, "
3813 "mcode_version 0x%x\n", c->chip_version,
3814 c->mcode_date, c->mcode_version);
3817 AdvReadWordLram(iop_base, ASC_MC_TAGQNG_ABLE, tagqng_able);
3818 len = asc_prt_line(cp, leftlen, " Queuing Enabled:");
3820 for (i = 0; i <= ADV_MAX_TID; i++) {
3821 if ((chip_scsi_id == i) ||
3822 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
3826 len = asc_prt_line(cp, leftlen, " %X:%c",
3828 (tagqng_able & ADV_TID_TO_TIDMASK(i)) ? 'Y' :
3832 len = asc_prt_line(cp, leftlen, "\n");
3835 len = asc_prt_line(cp, leftlen, " Queue Limit:");
3837 for (i = 0; i <= ADV_MAX_TID; i++) {
3838 if ((chip_scsi_id == i) ||
3839 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
3843 AdvReadByteLram(iop_base, ASC_MC_NUMBER_OF_MAX_CMD + i,
3846 len = asc_prt_line(cp, leftlen, " %X:%d", i, lrambyte);
3849 len = asc_prt_line(cp, leftlen, "\n");
3852 len = asc_prt_line(cp, leftlen, " Command Pending:");
3854 for (i = 0; i <= ADV_MAX_TID; i++) {
3855 if ((chip_scsi_id == i) ||
3856 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
3860 AdvReadByteLram(iop_base, ASC_MC_NUMBER_OF_QUEUED_CMD + i,
3863 len = asc_prt_line(cp, leftlen, " %X:%d", i, lrambyte);
3866 len = asc_prt_line(cp, leftlen, "\n");
3869 AdvReadWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able);
3870 len = asc_prt_line(cp, leftlen, " Wide Enabled:");
3872 for (i = 0; i <= ADV_MAX_TID; i++) {
3873 if ((chip_scsi_id == i) ||
3874 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
3878 len = asc_prt_line(cp, leftlen, " %X:%c",
3880 (wdtr_able & ADV_TID_TO_TIDMASK(i)) ? 'Y' :
3884 len = asc_prt_line(cp, leftlen, "\n");
3887 AdvReadWordLram(iop_base, ASC_MC_WDTR_DONE, wdtr_done);
3888 len = asc_prt_line(cp, leftlen, " Transfer Bit Width:");
3890 for (i = 0; i <= ADV_MAX_TID; i++) {
3891 if ((chip_scsi_id == i) ||
3892 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
3896 AdvReadWordLram(iop_base,
3897 ASC_MC_DEVICE_HSHK_CFG_TABLE + (2 * i),
3900 len = asc_prt_line(cp, leftlen, " %X:%d",
3901 i, (lramword & 0x8000) ? 16 : 8);
3904 if ((wdtr_able & ADV_TID_TO_TIDMASK(i)) &&
3905 (wdtr_done & ADV_TID_TO_TIDMASK(i)) == 0) {
3906 len = asc_prt_line(cp, leftlen, "*");
3911 len = asc_prt_line(cp, leftlen, "\n");
3914 AdvReadWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
3915 len = asc_prt_line(cp, leftlen, " Synchronous Enabled:");
3917 for (i = 0; i <= ADV_MAX_TID; i++) {
3918 if ((chip_scsi_id == i) ||
3919 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
3923 len = asc_prt_line(cp, leftlen, " %X:%c",
3925 (sdtr_able & ADV_TID_TO_TIDMASK(i)) ? 'Y' :
3929 len = asc_prt_line(cp, leftlen, "\n");
3932 AdvReadWordLram(iop_base, ASC_MC_SDTR_DONE, sdtr_done);
3933 for (i = 0; i <= ADV_MAX_TID; i++) {
3935 AdvReadWordLram(iop_base,
3936 ASC_MC_DEVICE_HSHK_CFG_TABLE + (2 * i),
3938 lramword &= ~0x8000;
3940 if ((chip_scsi_id == i) ||
3941 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0) ||
3942 ((sdtr_able & ADV_TID_TO_TIDMASK(i)) == 0)) {
3946 len = asc_prt_line(cp, leftlen, " %X:", i);
3949 if ((lramword & 0x1F) == 0) { /* Check for REQ/ACK Offset 0. */
3950 len = asc_prt_line(cp, leftlen, " Asynchronous");
3954 asc_prt_line(cp, leftlen,
3955 " Transfer Period Factor: ");
3958 if ((lramword & 0x1F00) == 0x1100) { /* 80 Mhz */
3960 asc_prt_line(cp, leftlen, "9 (80.0 Mhz),");
3962 } else if ((lramword & 0x1F00) == 0x1000) { /* 40 Mhz */
3964 asc_prt_line(cp, leftlen, "10 (40.0 Mhz),");
3966 } else { /* 20 Mhz or below. */
3968 period = (((lramword >> 8) * 25) + 50) / 4;
3970 if (period == 0) { /* Should never happen. */
3972 asc_prt_line(cp, leftlen,
3976 len = asc_prt_line(cp, leftlen,
3978 period, 250 / period,
3985 len = asc_prt_line(cp, leftlen, " REQ/ACK Offset: %d",
3990 if ((sdtr_done & ADV_TID_TO_TIDMASK(i)) == 0) {
3991 len = asc_prt_line(cp, leftlen, "*\n");
3994 len = asc_prt_line(cp, leftlen, "\n");
4000 len = asc_prt_line(cp, leftlen,
4001 " * = Re-negotiation pending before next command.\n");
4011 * Copy proc information to a read buffer taking into account the current
4012 * read offset in the file and the remaining space in the read buffer.
4015 asc_proc_copy(off_t advoffset, off_t offset, char *curbuf, int leftlen,
4016 char *cp, int cplen)
4020 ASC_DBG(2, "offset %d, advoffset %d, cplen %d\n",
4021 (unsigned)offset, (unsigned)advoffset, cplen);
4022 if (offset <= advoffset) {
4023 /* Read offset below current offset, copy everything. */
4024 cnt = min(cplen, leftlen);
4025 ASC_DBG(2, "curbuf 0x%lx, cp 0x%lx, cnt %d\n",
4026 (ulong)curbuf, (ulong)cp, cnt);
4027 memcpy(curbuf, cp, cnt);
4028 } else if (offset < advoffset + cplen) {
4029 /* Read offset within current range, partial copy. */
4030 cnt = (advoffset + cplen) - offset;
4031 cp = (cp + cplen) - cnt;
4032 cnt = min(cnt, leftlen);
4033 ASC_DBG(2, "curbuf 0x%lx, cp 0x%lx, cnt %d\n",
4034 (ulong)curbuf, (ulong)cp, cnt);
4035 memcpy(curbuf, cp, cnt);
4040 #ifdef ADVANSYS_STATS
4042 * asc_prt_board_stats()
4044 * Note: no single line should be greater than ASC_PRTLINE_SIZE,
4045 * cf. asc_prt_line().
4047 * Return the number of characters copied into 'cp'. No more than
4048 * 'cplen' characters will be copied to 'cp'.
4050 static int asc_prt_board_stats(struct Scsi_Host *shost, char *cp, int cplen)
4052 struct asc_board *boardp = shost_priv(shost);
4053 struct asc_stats *s = &boardp->asc_stats;
4055 int leftlen = cplen;
4056 int len, totlen = 0;
4058 len = asc_prt_line(cp, leftlen,
4059 "\nLinux Driver Statistics for AdvanSys SCSI Host %d:\n",
4063 len = asc_prt_line(cp, leftlen,
4064 " queuecommand %lu, reset %lu, biosparam %lu, interrupt %lu\n",
4065 s->queuecommand, s->reset, s->biosparam,
4069 len = asc_prt_line(cp, leftlen,
4070 " callback %lu, done %lu, build_error %lu, build_noreq %lu, build_nosg %lu\n",
4071 s->callback, s->done, s->build_error,
4072 s->adv_build_noreq, s->adv_build_nosg);
4075 len = asc_prt_line(cp, leftlen,
4076 " exe_noerror %lu, exe_busy %lu, exe_error %lu, exe_unknown %lu\n",
4077 s->exe_noerror, s->exe_busy, s->exe_error,
4082 * Display data transfer statistics.
4084 if (s->cont_cnt > 0) {
4085 len = asc_prt_line(cp, leftlen, " cont_cnt %lu, ", s->cont_cnt);
4088 len = asc_prt_line(cp, leftlen, "cont_xfer %lu.%01lu kb ",
4090 ASC_TENTHS(s->cont_xfer, 2));
4093 /* Contiguous transfer average size */
4094 len = asc_prt_line(cp, leftlen, "avg_xfer %lu.%01lu kb\n",
4095 (s->cont_xfer / 2) / s->cont_cnt,
4096 ASC_TENTHS((s->cont_xfer / 2), s->cont_cnt));
4100 if (s->sg_cnt > 0) {
4102 len = asc_prt_line(cp, leftlen, " sg_cnt %lu, sg_elem %lu, ",
4103 s->sg_cnt, s->sg_elem);
4106 len = asc_prt_line(cp, leftlen, "sg_xfer %lu.%01lu kb\n",
4107 s->sg_xfer / 2, ASC_TENTHS(s->sg_xfer, 2));
4110 /* Scatter gather transfer statistics */
4111 len = asc_prt_line(cp, leftlen, " avg_num_elem %lu.%01lu, ",
4112 s->sg_elem / s->sg_cnt,
4113 ASC_TENTHS(s->sg_elem, s->sg_cnt));
4116 len = asc_prt_line(cp, leftlen, "avg_elem_size %lu.%01lu kb, ",
4117 (s->sg_xfer / 2) / s->sg_elem,
4118 ASC_TENTHS((s->sg_xfer / 2), s->sg_elem));
4121 len = asc_prt_line(cp, leftlen, "avg_xfer_size %lu.%01lu kb\n",
4122 (s->sg_xfer / 2) / s->sg_cnt,
4123 ASC_TENTHS((s->sg_xfer / 2), s->sg_cnt));
4128 * Display request queuing statistics.
4130 len = asc_prt_line(cp, leftlen,
4131 " Active and Waiting Request Queues (Time Unit: %d HZ):\n",
4137 #endif /* ADVANSYS_STATS */
4140 * advansys_proc_info() - /proc/scsi/advansys/{0,1,2,3,...}
4142 * *buffer: I/O buffer
4143 * **start: if inout == FALSE pointer into buffer where user read should start
4144 * offset: current offset into a /proc/scsi/advansys/[0...] file
4145 * length: length of buffer
4146 * hostno: Scsi_Host host_no
4147 * inout: TRUE - user is writing; FALSE - user is reading
4149 * Return the number of bytes read from or written to a
4150 * /proc/scsi/advansys/[0...] file.
4152 * Note: This function uses the per board buffer 'prtbuf' which is
4153 * allocated when the board is initialized in advansys_detect(). The
4154 * buffer is ASC_PRTBUF_SIZE bytes. The function asc_proc_copy() is
4155 * used to write to the buffer. The way asc_proc_copy() is written
4156 * if 'prtbuf' is too small it will not be overwritten. Instead the
4157 * user just won't get all the available statistics.
4160 advansys_proc_info(struct Scsi_Host *shost, char *buffer, char **start,
4161 off_t offset, int length, int inout)
4163 struct asc_board *boardp = shost_priv(shost);
4172 ASC_DBG(1, "begin\n");
4175 * User write not supported.
4181 * User read of /proc/scsi/advansys/[0...] file.
4184 /* Copy read data starting at the beginning of the buffer. */
4192 * Get board configuration information.
4194 * advansys_info() returns the board string from its own static buffer.
4196 cp = (char *)advansys_info(shost);
4199 /* Copy board information. */
4200 cnt = asc_proc_copy(advoffset, offset, curbuf, leftlen, cp, cplen);
4204 ASC_DBG(1, "totcnt %d\n", totcnt);
4211 * Display Wide Board BIOS Information.
4213 if (!ASC_NARROW_BOARD(boardp)) {
4214 cp = boardp->prtbuf;
4215 cplen = asc_prt_adv_bios(shost, cp, ASC_PRTBUF_SIZE);
4216 BUG_ON(cplen >= ASC_PRTBUF_SIZE);
4217 cnt = asc_proc_copy(advoffset, offset, curbuf, leftlen, cp,
4222 ASC_DBG(1, "totcnt %d\n", totcnt);
4230 * Display driver information for each device attached to the board.
4232 cp = boardp->prtbuf;
4233 cplen = asc_prt_board_devices(shost, cp, ASC_PRTBUF_SIZE);
4234 BUG_ON(cplen >= ASC_PRTBUF_SIZE);
4235 cnt = asc_proc_copy(advoffset, offset, curbuf, leftlen, cp, cplen);
4239 ASC_DBG(1, "totcnt %d\n", totcnt);
4246 * Display EEPROM configuration for the board.
4248 cp = boardp->prtbuf;
4249 if (ASC_NARROW_BOARD(boardp)) {
4250 cplen = asc_prt_asc_board_eeprom(shost, cp, ASC_PRTBUF_SIZE);
4252 cplen = asc_prt_adv_board_eeprom(shost, cp, ASC_PRTBUF_SIZE);
4254 BUG_ON(cplen >= ASC_PRTBUF_SIZE);
4255 cnt = asc_proc_copy(advoffset, offset, curbuf, leftlen, cp, cplen);
4259 ASC_DBG(1, "totcnt %d\n", totcnt);
4266 * Display driver configuration and information for the board.
4268 cp = boardp->prtbuf;
4269 cplen = asc_prt_driver_conf(shost, cp, ASC_PRTBUF_SIZE);
4270 BUG_ON(cplen >= ASC_PRTBUF_SIZE);
4271 cnt = asc_proc_copy(advoffset, offset, curbuf, leftlen, cp, cplen);
4275 ASC_DBG(1, "totcnt %d\n", totcnt);
4281 #ifdef ADVANSYS_STATS
4283 * Display driver statistics for the board.
4285 cp = boardp->prtbuf;
4286 cplen = asc_prt_board_stats(shost, cp, ASC_PRTBUF_SIZE);
4287 BUG_ON(cplen >= ASC_PRTBUF_SIZE);
4288 cnt = asc_proc_copy(advoffset, offset, curbuf, leftlen, cp, cplen);
4292 ASC_DBG(1, "totcnt %d\n", totcnt);
4297 #endif /* ADVANSYS_STATS */
4300 * Display Asc Library dynamic configuration information
4303 cp = boardp->prtbuf;
4304 if (ASC_NARROW_BOARD(boardp)) {
4305 cplen = asc_prt_asc_board_info(shost, cp, ASC_PRTBUF_SIZE);
4307 cplen = asc_prt_adv_board_info(shost, cp, ASC_PRTBUF_SIZE);
4309 BUG_ON(cplen >= ASC_PRTBUF_SIZE);
4310 cnt = asc_proc_copy(advoffset, offset, curbuf, leftlen, cp, cplen);
4314 ASC_DBG(1, "totcnt %d\n", totcnt);
4320 ASC_DBG(1, "totcnt %d\n", totcnt);
4324 #endif /* CONFIG_PROC_FS */
4326 static void asc_scsi_done(struct scsi_cmnd *scp)
4328 struct asc_board *boardp = shost_priv(scp->device->host);
4331 dma_unmap_sg(boardp->dev,
4332 (struct scatterlist *)scp->request_buffer,
4333 scp->use_sg, scp->sc_data_direction);
4334 else if (scp->request_bufflen)
4335 dma_unmap_single(boardp->dev, scp->SCp.dma_handle,
4336 scp->request_bufflen, scp->sc_data_direction);
4338 ASC_STATS(scp->device->host, done);
4340 scp->scsi_done(scp);
4343 static void AscSetBank(PortAddr iop_base, uchar bank)
4347 val = AscGetChipControl(iop_base) &
4349 (CC_SINGLE_STEP | CC_TEST | CC_DIAG | CC_SCSI_RESET |
4353 } else if (bank == 2) {
4354 val |= CC_DIAG | CC_BANK_ONE;
4356 val &= ~CC_BANK_ONE;
4358 AscSetChipControl(iop_base, val);
4361 static void AscSetChipIH(PortAddr iop_base, ushort ins_code)
4363 AscSetBank(iop_base, 1);
4364 AscWriteChipIH(iop_base, ins_code);
4365 AscSetBank(iop_base, 0);
4368 static int AscStartChip(PortAddr iop_base)
4370 AscSetChipControl(iop_base, 0);
4371 if ((AscGetChipStatus(iop_base) & CSW_HALTED) != 0) {
4377 static int AscStopChip(PortAddr iop_base)
4382 AscGetChipControl(iop_base) &
4383 (~(CC_SINGLE_STEP | CC_TEST | CC_DIAG));
4384 AscSetChipControl(iop_base, (uchar)(cc_val | CC_HALT));
4385 AscSetChipIH(iop_base, INS_HALT);
4386 AscSetChipIH(iop_base, INS_RFLAG_WTM);
4387 if ((AscGetChipStatus(iop_base) & CSW_HALTED) == 0) {
4393 static int AscIsChipHalted(PortAddr iop_base)
4395 if ((AscGetChipStatus(iop_base) & CSW_HALTED) != 0) {
4396 if ((AscGetChipControl(iop_base) & CC_HALT) != 0) {
4403 static int AscResetChipAndScsiBus(ASC_DVC_VAR *asc_dvc)
4408 iop_base = asc_dvc->iop_base;
4409 while ((AscGetChipStatus(iop_base) & CSW_SCSI_RESET_ACTIVE)
4413 AscStopChip(iop_base);
4414 AscSetChipControl(iop_base, CC_CHIP_RESET | CC_SCSI_RESET | CC_HALT);
4416 AscSetChipIH(iop_base, INS_RFLAG_WTM);
4417 AscSetChipIH(iop_base, INS_HALT);
4418 AscSetChipControl(iop_base, CC_CHIP_RESET | CC_HALT);
4419 AscSetChipControl(iop_base, CC_HALT);
4421 AscSetChipStatus(iop_base, CIW_CLR_SCSI_RESET_INT);
4422 AscSetChipStatus(iop_base, 0);
4423 return (AscIsChipHalted(iop_base));
4426 static int AscFindSignature(PortAddr iop_base)
4430 ASC_DBG(1, "AscGetChipSignatureByte(0x%x) 0x%x\n",
4431 iop_base, AscGetChipSignatureByte(iop_base));
4432 if (AscGetChipSignatureByte(iop_base) == (uchar)ASC_1000_ID1B) {
4433 ASC_DBG(1, "AscGetChipSignatureWord(0x%x) 0x%x\n",
4434 iop_base, AscGetChipSignatureWord(iop_base));
4435 sig_word = AscGetChipSignatureWord(iop_base);
4436 if ((sig_word == (ushort)ASC_1000_ID0W) ||
4437 (sig_word == (ushort)ASC_1000_ID0W_FIX)) {
4444 static void AscEnableInterrupt(PortAddr iop_base)
4448 cfg = AscGetChipCfgLsw(iop_base);
4449 AscSetChipCfgLsw(iop_base, cfg | ASC_CFG0_HOST_INT_ON);
4452 static void AscDisableInterrupt(PortAddr iop_base)
4456 cfg = AscGetChipCfgLsw(iop_base);
4457 AscSetChipCfgLsw(iop_base, cfg & (~ASC_CFG0_HOST_INT_ON));
4460 static uchar AscReadLramByte(PortAddr iop_base, ushort addr)
4462 unsigned char byte_data;
4463 unsigned short word_data;
4465 if (isodd_word(addr)) {
4466 AscSetChipLramAddr(iop_base, addr - 1);
4467 word_data = AscGetChipLramData(iop_base);
4468 byte_data = (word_data >> 8) & 0xFF;
4470 AscSetChipLramAddr(iop_base, addr);
4471 word_data = AscGetChipLramData(iop_base);
4472 byte_data = word_data & 0xFF;
4477 static ushort AscReadLramWord(PortAddr iop_base, ushort addr)
4481 AscSetChipLramAddr(iop_base, addr);
4482 word_data = AscGetChipLramData(iop_base);
4486 #if CC_VERY_LONG_SG_LIST
4487 static ASC_DCNT AscReadLramDWord(PortAddr iop_base, ushort addr)
4489 ushort val_low, val_high;
4490 ASC_DCNT dword_data;
4492 AscSetChipLramAddr(iop_base, addr);
4493 val_low = AscGetChipLramData(iop_base);
4494 val_high = AscGetChipLramData(iop_base);
4495 dword_data = ((ASC_DCNT) val_high << 16) | (ASC_DCNT) val_low;
4496 return (dword_data);
4498 #endif /* CC_VERY_LONG_SG_LIST */
4501 AscMemWordSetLram(PortAddr iop_base, ushort s_addr, ushort set_wval, int words)
4505 AscSetChipLramAddr(iop_base, s_addr);
4506 for (i = 0; i < words; i++) {
4507 AscSetChipLramData(iop_base, set_wval);
4511 static void AscWriteLramWord(PortAddr iop_base, ushort addr, ushort word_val)
4513 AscSetChipLramAddr(iop_base, addr);
4514 AscSetChipLramData(iop_base, word_val);
4517 static void AscWriteLramByte(PortAddr iop_base, ushort addr, uchar byte_val)
4521 if (isodd_word(addr)) {
4523 word_data = AscReadLramWord(iop_base, addr);
4524 word_data &= 0x00FF;
4525 word_data |= (((ushort)byte_val << 8) & 0xFF00);
4527 word_data = AscReadLramWord(iop_base, addr);
4528 word_data &= 0xFF00;
4529 word_data |= ((ushort)byte_val & 0x00FF);
4531 AscWriteLramWord(iop_base, addr, word_data);
4535 * Copy 2 bytes to LRAM.
4537 * The source data is assumed to be in little-endian order in memory
4538 * and is maintained in little-endian order when written to LRAM.
4541 AscMemWordCopyPtrToLram(PortAddr iop_base,
4542 ushort s_addr, uchar *s_buffer, int words)
4546 AscSetChipLramAddr(iop_base, s_addr);
4547 for (i = 0; i < 2 * words; i += 2) {
4549 * On a little-endian system the second argument below
4550 * produces a little-endian ushort which is written to
4551 * LRAM in little-endian order. On a big-endian system
4552 * the second argument produces a big-endian ushort which
4553 * is "transparently" byte-swapped by outpw() and written
4554 * in little-endian order to LRAM.
4556 outpw(iop_base + IOP_RAM_DATA,
4557 ((ushort)s_buffer[i + 1] << 8) | s_buffer[i]);
4562 * Copy 4 bytes to LRAM.
4564 * The source data is assumed to be in little-endian order in memory
4565 * and is maintained in little-endian order when writen to LRAM.
4568 AscMemDWordCopyPtrToLram(PortAddr iop_base,
4569 ushort s_addr, uchar *s_buffer, int dwords)
4573 AscSetChipLramAddr(iop_base, s_addr);
4574 for (i = 0; i < 4 * dwords; i += 4) {
4575 outpw(iop_base + IOP_RAM_DATA, ((ushort)s_buffer[i + 1] << 8) | s_buffer[i]); /* LSW */
4576 outpw(iop_base + IOP_RAM_DATA, ((ushort)s_buffer[i + 3] << 8) | s_buffer[i + 2]); /* MSW */
4581 * Copy 2 bytes from LRAM.
4583 * The source data is assumed to be in little-endian order in LRAM
4584 * and is maintained in little-endian order when written to memory.
4587 AscMemWordCopyPtrFromLram(PortAddr iop_base,
4588 ushort s_addr, uchar *d_buffer, int words)
4593 AscSetChipLramAddr(iop_base, s_addr);
4594 for (i = 0; i < 2 * words; i += 2) {
4595 word = inpw(iop_base + IOP_RAM_DATA);
4596 d_buffer[i] = word & 0xff;
4597 d_buffer[i + 1] = (word >> 8) & 0xff;
4601 static ASC_DCNT AscMemSumLramWord(PortAddr iop_base, ushort s_addr, int words)
4607 for (i = 0; i < words; i++, s_addr += 2) {
4608 sum += AscReadLramWord(iop_base, s_addr);
4613 static ushort AscInitLram(ASC_DVC_VAR *asc_dvc)
4620 iop_base = asc_dvc->iop_base;
4622 AscMemWordSetLram(iop_base, ASC_QADR_BEG, 0,
4623 (ushort)(((int)(asc_dvc->max_total_qng + 2 + 1) *
4625 i = ASC_MIN_ACTIVE_QNO;
4626 s_addr = ASC_QADR_BEG + ASC_QBLK_SIZE;
4627 AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_FWD),
4629 AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_BWD),
4630 (uchar)(asc_dvc->max_total_qng));
4631 AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_QNO),
4634 s_addr += ASC_QBLK_SIZE;
4635 for (; i < asc_dvc->max_total_qng; i++, s_addr += ASC_QBLK_SIZE) {
4636 AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_FWD),
4638 AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_BWD),
4640 AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_QNO),
4643 AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_FWD),
4644 (uchar)ASC_QLINK_END);
4645 AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_BWD),
4646 (uchar)(asc_dvc->max_total_qng - 1));
4647 AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_QNO),
4648 (uchar)asc_dvc->max_total_qng);
4650 s_addr += ASC_QBLK_SIZE;
4651 for (; i <= (uchar)(asc_dvc->max_total_qng + 3);
4652 i++, s_addr += ASC_QBLK_SIZE) {
4653 AscWriteLramByte(iop_base,
4654 (ushort)(s_addr + (ushort)ASC_SCSIQ_B_FWD), i);
4655 AscWriteLramByte(iop_base,
4656 (ushort)(s_addr + (ushort)ASC_SCSIQ_B_BWD), i);
4657 AscWriteLramByte(iop_base,
4658 (ushort)(s_addr + (ushort)ASC_SCSIQ_B_QNO), i);
4664 AscLoadMicroCode(PortAddr iop_base,
4665 ushort s_addr, uchar *mcode_buf, ushort mcode_size)
4668 ushort mcode_word_size;
4669 ushort mcode_chksum;
4671 /* Write the microcode buffer starting at LRAM address 0. */
4672 mcode_word_size = (ushort)(mcode_size >> 1);
4673 AscMemWordSetLram(iop_base, s_addr, 0, mcode_word_size);
4674 AscMemWordCopyPtrToLram(iop_base, s_addr, mcode_buf, mcode_word_size);
4676 chksum = AscMemSumLramWord(iop_base, s_addr, mcode_word_size);
4677 ASC_DBG(1, "chksum 0x%lx\n", (ulong)chksum);
4678 mcode_chksum = (ushort)AscMemSumLramWord(iop_base,
4679 (ushort)ASC_CODE_SEC_BEG,
4680 (ushort)((mcode_size -
4684 ASC_DBG(1, "mcode_chksum 0x%lx\n", (ulong)mcode_chksum);
4685 AscWriteLramWord(iop_base, ASCV_MCODE_CHKSUM_W, mcode_chksum);
4686 AscWriteLramWord(iop_base, ASCV_MCODE_SIZE_W, mcode_size);
4690 /* Microcode buffer is kept after initialization for error recovery. */
4691 static uchar _asc_mcode_buf[] = {
4692 0x01, 0x03, 0x01, 0x19, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
4693 0x00, 0x00, 0x00, 0x00, 0x0F, 0x0F, 0x0F, 0x0F, 0x0F, 0x0F, 0x0F, 0x0F,
4694 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
4695 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
4696 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
4697 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC3, 0x12, 0x0D, 0x05,
4698 0x01, 0x00, 0x00, 0x00, 0x00, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
4699 0xFF, 0x80, 0xFF, 0xFF, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
4700 0x00, 0x00, 0x00, 0x23, 0x00, 0x00, 0x00, 0x00, 0x00, 0x07, 0x00, 0xFF,
4701 0x00, 0x00, 0x00, 0x00, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00,
4702 0x00, 0x00, 0xE4, 0x88, 0x00, 0x00, 0x00, 0x00, 0x80, 0x73, 0x48, 0x04,
4703 0x36, 0x00, 0x00, 0xA2, 0xC2, 0x00, 0x80, 0x73, 0x03, 0x23, 0x36, 0x40,
4704 0xB6, 0x00, 0x36, 0x00, 0x05, 0xD6, 0x0C, 0xD2, 0x12, 0xDA, 0x00, 0xA2,
4705 0xC2, 0x00, 0x92, 0x80, 0x1E, 0x98, 0x50, 0x00, 0xF5, 0x00, 0x48, 0x98,
4706 0xDF, 0x23, 0x36, 0x60, 0xB6, 0x00, 0x92, 0x80, 0x4F, 0x00, 0xF5, 0x00,
4707 0x48, 0x98, 0xEF, 0x23, 0x36, 0x60, 0xB6, 0x00, 0x92, 0x80, 0x80, 0x62,
4708 0x92, 0x80, 0x00, 0x46, 0x15, 0xEE, 0x13, 0xEA, 0x02, 0x01, 0x09, 0xD8,
4709 0xCD, 0x04, 0x4D, 0x00, 0x00, 0xA3, 0xD6, 0x00, 0xA6, 0x97, 0x7F, 0x23,
4710 0x04, 0x61, 0x84, 0x01, 0xE6, 0x84, 0xD2, 0xC1, 0x80, 0x73, 0xCD, 0x04,
4711 0x4D, 0x00, 0x00, 0xA3, 0xDA, 0x01, 0xA6, 0x97, 0xC6, 0x81, 0xC2, 0x88,
4712 0x80, 0x73, 0x80, 0x77, 0x00, 0x01, 0x01, 0xA1, 0xFE, 0x00, 0x4F, 0x00,
4713 0x84, 0x97, 0x07, 0xA6, 0x08, 0x01, 0x00, 0x33, 0x03, 0x00, 0xC2, 0x88,
4714 0x03, 0x03, 0x01, 0xDE, 0xC2, 0x88, 0xCE, 0x00, 0x69, 0x60, 0xCE, 0x00,
4715 0x02, 0x03, 0x4A, 0x60, 0x00, 0xA2, 0x78, 0x01, 0x80, 0x63, 0x07, 0xA6,
4716 0x24, 0x01, 0x78, 0x81, 0x03, 0x03, 0x80, 0x63, 0xE2, 0x00, 0x07, 0xA6,
4717 0x34, 0x01, 0x00, 0x33, 0x04, 0x00, 0xC2, 0x88, 0x03, 0x07, 0x02, 0x01,
4718 0x04, 0xCA, 0x0D, 0x23, 0x68, 0x98, 0x4D, 0x04, 0x04, 0x85, 0x05, 0xD8,
4719 0x0D, 0x23, 0x68, 0x98, 0xCD, 0x04, 0x15, 0x23, 0xF8, 0x88, 0xFB, 0x23,
4720 0x02, 0x61, 0x82, 0x01, 0x80, 0x63, 0x02, 0x03, 0x06, 0xA3, 0x62, 0x01,
4721 0x00, 0x33, 0x0A, 0x00, 0xC2, 0x88, 0x4E, 0x00, 0x07, 0xA3, 0x6E, 0x01,
4722 0x00, 0x33, 0x0B, 0x00, 0xC2, 0x88, 0xCD, 0x04, 0x36, 0x2D, 0x00, 0x33,
4723 0x1A, 0x00, 0xC2, 0x88, 0x50, 0x04, 0x88, 0x81, 0x06, 0xAB, 0x82, 0x01,
4724 0x88, 0x81, 0x4E, 0x00, 0x07, 0xA3, 0x92, 0x01, 0x50, 0x00, 0x00, 0xA3,
4725 0x3C, 0x01, 0x00, 0x05, 0x7C, 0x81, 0x46, 0x97, 0x02, 0x01, 0x05, 0xC6,
4726 0x04, 0x23, 0xA0, 0x01, 0x15, 0x23, 0xA1, 0x01, 0xBE, 0x81, 0xFD, 0x23,
4727 0x02, 0x61, 0x82, 0x01, 0x0A, 0xDA, 0x4A, 0x00, 0x06, 0x61, 0x00, 0xA0,
4728 0xB4, 0x01, 0x80, 0x63, 0xCD, 0x04, 0x36, 0x2D, 0x00, 0x33, 0x1B, 0x00,
4729 0xC2, 0x88, 0x06, 0x23, 0x68, 0x98, 0xCD, 0x04, 0xE6, 0x84, 0x06, 0x01,
4730 0x00, 0xA2, 0xD4, 0x01, 0x57, 0x60, 0x00, 0xA0, 0xDA, 0x01, 0xE6, 0x84,
4731 0x80, 0x23, 0xA0, 0x01, 0xE6, 0x84, 0x80, 0x73, 0x4B, 0x00, 0x06, 0x61,
4732 0x00, 0xA2, 0x00, 0x02, 0x04, 0x01, 0x0C, 0xDE, 0x02, 0x01, 0x03, 0xCC,
4733 0x4F, 0x00, 0x84, 0x97, 0xFC, 0x81, 0x08, 0x23, 0x02, 0x41, 0x82, 0x01,
4734 0x4F, 0x00, 0x62, 0x97, 0x48, 0x04, 0x84, 0x80, 0xF0, 0x97, 0x00, 0x46,
4735 0x56, 0x00, 0x03, 0xC0, 0x01, 0x23, 0xE8, 0x00, 0x81, 0x73, 0x06, 0x29,
4736 0x03, 0x42, 0x06, 0xE2, 0x03, 0xEE, 0x6B, 0xEB, 0x11, 0x23, 0xF8, 0x88,
4737 0x04, 0x98, 0xF0, 0x80, 0x80, 0x73, 0x80, 0x77, 0x07, 0xA4, 0x2A, 0x02,
4738 0x7C, 0x95, 0x06, 0xA6, 0x34, 0x02, 0x03, 0xA6, 0x4C, 0x04, 0x46, 0x82,
4739 0x04, 0x01, 0x03, 0xD8, 0xB4, 0x98, 0x6A, 0x96, 0x46, 0x82, 0xFE, 0x95,
4740 0x80, 0x67, 0x83, 0x03, 0x80, 0x63, 0xB6, 0x2D, 0x02, 0xA6, 0x6C, 0x02,
4741 0x07, 0xA6, 0x5A, 0x02, 0x06, 0xA6, 0x5E, 0x02, 0x03, 0xA6, 0x62, 0x02,
4742 0xC2, 0x88, 0x7C, 0x95, 0x48, 0x82, 0x60, 0x96, 0x48, 0x82, 0x04, 0x23,
4743 0xA0, 0x01, 0x14, 0x23, 0xA1, 0x01, 0x3C, 0x84, 0x04, 0x01, 0x0C, 0xDC,
4744 0xE0, 0x23, 0x25, 0x61, 0xEF, 0x00, 0x14, 0x01, 0x4F, 0x04, 0xA8, 0x01,
4745 0x6F, 0x00, 0xA5, 0x01, 0x03, 0x23, 0xA4, 0x01, 0x06, 0x23, 0x9C, 0x01,
4746 0x24, 0x2B, 0x1C, 0x01, 0x02, 0xA6, 0xAA, 0x02, 0x07, 0xA6, 0x5A, 0x02,
4747 0x06, 0xA6, 0x5E, 0x02, 0x03, 0xA6, 0x20, 0x04, 0x01, 0xA6, 0xB4, 0x02,
4748 0x00, 0xA6, 0xB4, 0x02, 0x00, 0x33, 0x12, 0x00, 0xC2, 0x88, 0x00, 0x0E,
4749 0x80, 0x63, 0x00, 0x43, 0x00, 0xA0, 0x8C, 0x02, 0x4D, 0x04, 0x04, 0x01,
4750 0x0B, 0xDC, 0xE7, 0x23, 0x04, 0x61, 0x84, 0x01, 0x10, 0x31, 0x12, 0x35,
4751 0x14, 0x01, 0xEC, 0x00, 0x6C, 0x38, 0x00, 0x3F, 0x00, 0x00, 0xEA, 0x82,
4752 0x18, 0x23, 0x04, 0x61, 0x18, 0xA0, 0xE2, 0x02, 0x04, 0x01, 0xA2, 0xC8,
4753 0x00, 0x33, 0x1F, 0x00, 0xC2, 0x88, 0x08, 0x31, 0x0A, 0x35, 0x0C, 0x39,
4754 0x0E, 0x3D, 0x7E, 0x98, 0xB6, 0x2D, 0x01, 0xA6, 0x14, 0x03, 0x00, 0xA6,
4755 0x14, 0x03, 0x07, 0xA6, 0x0C, 0x03, 0x06, 0xA6, 0x10, 0x03, 0x03, 0xA6,
4756 0x20, 0x04, 0x02, 0xA6, 0x6C, 0x02, 0x00, 0x33, 0x33, 0x00, 0xC2, 0x88,
4757 0x7C, 0x95, 0xEE, 0x82, 0x60, 0x96, 0xEE, 0x82, 0x82, 0x98, 0x80, 0x42,
4758 0x7E, 0x98, 0x64, 0xE4, 0x04, 0x01, 0x2D, 0xC8, 0x31, 0x05, 0x07, 0x01,
4759 0x00, 0xA2, 0x54, 0x03, 0x00, 0x43, 0x87, 0x01, 0x05, 0x05, 0x86, 0x98,
4760 0x7E, 0x98, 0x00, 0xA6, 0x16, 0x03, 0x07, 0xA6, 0x4C, 0x03, 0x03, 0xA6,
4761 0x3C, 0x04, 0x06, 0xA6, 0x50, 0x03, 0x01, 0xA6, 0x16, 0x03, 0x00, 0x33,
4762 0x25, 0x00, 0xC2, 0x88, 0x7C, 0x95, 0x32, 0x83, 0x60, 0x96, 0x32, 0x83,
4763 0x04, 0x01, 0x10, 0xCE, 0x07, 0xC8, 0x05, 0x05, 0xEB, 0x04, 0x00, 0x33,
4764 0x00, 0x20, 0xC0, 0x20, 0x81, 0x62, 0x72, 0x83, 0x00, 0x01, 0x05, 0x05,
4765 0xFF, 0xA2, 0x7A, 0x03, 0xB1, 0x01, 0x08, 0x23, 0xB2, 0x01, 0x2E, 0x83,
4766 0x05, 0x05, 0x15, 0x01, 0x00, 0xA2, 0x9A, 0x03, 0xEC, 0x00, 0x6E, 0x00,
4767 0x95, 0x01, 0x6C, 0x38, 0x00, 0x3F, 0x00, 0x00, 0x01, 0xA6, 0x96, 0x03,
4768 0x00, 0xA6, 0x96, 0x03, 0x10, 0x84, 0x80, 0x42, 0x7E, 0x98, 0x01, 0xA6,
4769 0xA4, 0x03, 0x00, 0xA6, 0xBC, 0x03, 0x10, 0x84, 0xA8, 0x98, 0x80, 0x42,
4770 0x01, 0xA6, 0xA4, 0x03, 0x07, 0xA6, 0xB2, 0x03, 0xD4, 0x83, 0x7C, 0x95,
4771 0xA8, 0x83, 0x00, 0x33, 0x2F, 0x00, 0xC2, 0x88, 0xA8, 0x98, 0x80, 0x42,
4772 0x00, 0xA6, 0xBC, 0x03, 0x07, 0xA6, 0xCA, 0x03, 0xD4, 0x83, 0x7C, 0x95,
4773 0xC0, 0x83, 0x00, 0x33, 0x26, 0x00, 0xC2, 0x88, 0x38, 0x2B, 0x80, 0x32,
4774 0x80, 0x36, 0x04, 0x23, 0xA0, 0x01, 0x12, 0x23, 0xA1, 0x01, 0x10, 0x84,
4775 0x07, 0xF0, 0x06, 0xA4, 0xF4, 0x03, 0x80, 0x6B, 0x80, 0x67, 0x05, 0x23,
4776 0x83, 0x03, 0x80, 0x63, 0x03, 0xA6, 0x0E, 0x04, 0x07, 0xA6, 0x06, 0x04,
4777 0x06, 0xA6, 0x0A, 0x04, 0x00, 0x33, 0x17, 0x00, 0xC2, 0x88, 0x7C, 0x95,
4778 0xF4, 0x83, 0x60, 0x96, 0xF4, 0x83, 0x20, 0x84, 0x07, 0xF0, 0x06, 0xA4,
4779 0x20, 0x04, 0x80, 0x6B, 0x80, 0x67, 0x05, 0x23, 0x83, 0x03, 0x80, 0x63,
4780 0xB6, 0x2D, 0x03, 0xA6, 0x3C, 0x04, 0x07, 0xA6, 0x34, 0x04, 0x06, 0xA6,
4781 0x38, 0x04, 0x00, 0x33, 0x30, 0x00, 0xC2, 0x88, 0x7C, 0x95, 0x20, 0x84,
4782 0x60, 0x96, 0x20, 0x84, 0x1D, 0x01, 0x06, 0xCC, 0x00, 0x33, 0x00, 0x84,
4783 0xC0, 0x20, 0x00, 0x23, 0xEA, 0x00, 0x81, 0x62, 0xA2, 0x0D, 0x80, 0x63,
4784 0x07, 0xA6, 0x5A, 0x04, 0x00, 0x33, 0x18, 0x00, 0xC2, 0x88, 0x03, 0x03,
4785 0x80, 0x63, 0xA3, 0x01, 0x07, 0xA4, 0x64, 0x04, 0x23, 0x01, 0x00, 0xA2,
4786 0x86, 0x04, 0x0A, 0xA0, 0x76, 0x04, 0xE0, 0x00, 0x00, 0x33, 0x1D, 0x00,
4787 0xC2, 0x88, 0x0B, 0xA0, 0x82, 0x04, 0xE0, 0x00, 0x00, 0x33, 0x1E, 0x00,
4788 0xC2, 0x88, 0x42, 0x23, 0xF8, 0x88, 0x00, 0x23, 0x22, 0xA3, 0xE6, 0x04,
4789 0x08, 0x23, 0x22, 0xA3, 0xA2, 0x04, 0x28, 0x23, 0x22, 0xA3, 0xAE, 0x04,
4790 0x02, 0x23, 0x22, 0xA3, 0xC4, 0x04, 0x42, 0x23, 0xF8, 0x88, 0x4A, 0x00,
4791 0x06, 0x61, 0x00, 0xA0, 0xAE, 0x04, 0x45, 0x23, 0xF8, 0x88, 0x04, 0x98,
4792 0x00, 0xA2, 0xC0, 0x04, 0xB4, 0x98, 0x00, 0x33, 0x00, 0x82, 0xC0, 0x20,
4793 0x81, 0x62, 0xE8, 0x81, 0x47, 0x23, 0xF8, 0x88, 0x04, 0x01, 0x0B, 0xDE,
4794 0x04, 0x98, 0xB4, 0x98, 0x00, 0x33, 0x00, 0x81, 0xC0, 0x20, 0x81, 0x62,
4795 0x14, 0x01, 0x00, 0xA0, 0x00, 0x02, 0x43, 0x23, 0xF8, 0x88, 0x04, 0x23,
4796 0xA0, 0x01, 0x44, 0x23, 0xA1, 0x01, 0x80, 0x73, 0x4D, 0x00, 0x03, 0xA3,
4797 0xF4, 0x04, 0x00, 0x33, 0x27, 0x00, 0xC2, 0x88, 0x04, 0x01, 0x04, 0xDC,
4798 0x02, 0x23, 0xA2, 0x01, 0x04, 0x23, 0xA0, 0x01, 0x04, 0x98, 0x26, 0x95,
4799 0x4B, 0x00, 0xF6, 0x00, 0x4F, 0x04, 0x4F, 0x00, 0x00, 0xA3, 0x22, 0x05,
4800 0x00, 0x05, 0x76, 0x00, 0x06, 0x61, 0x00, 0xA2, 0x1C, 0x05, 0x0A, 0x85,
4801 0x46, 0x97, 0xCD, 0x04, 0x24, 0x85, 0x48, 0x04, 0x84, 0x80, 0x02, 0x01,
4802 0x03, 0xDA, 0x80, 0x23, 0x82, 0x01, 0x34, 0x85, 0x02, 0x23, 0xA0, 0x01,
4803 0x4A, 0x00, 0x06, 0x61, 0x00, 0xA2, 0x40, 0x05, 0x1D, 0x01, 0x04, 0xD6,
4804 0xFF, 0x23, 0x86, 0x41, 0x4B, 0x60, 0xCB, 0x00, 0xFF, 0x23, 0x80, 0x01,
4805 0x49, 0x00, 0x81, 0x01, 0x04, 0x01, 0x02, 0xC8, 0x30, 0x01, 0x80, 0x01,
4806 0xF7, 0x04, 0x03, 0x01, 0x49, 0x04, 0x80, 0x01, 0xC9, 0x00, 0x00, 0x05,
4807 0x00, 0x01, 0xFF, 0xA0, 0x60, 0x05, 0x77, 0x04, 0x01, 0x23, 0xEA, 0x00,
4808 0x5D, 0x00, 0xFE, 0xC7, 0x00, 0x62, 0x00, 0x23, 0xEA, 0x00, 0x00, 0x63,
4809 0x07, 0xA4, 0xF8, 0x05, 0x03, 0x03, 0x02, 0xA0, 0x8E, 0x05, 0xF4, 0x85,
4810 0x00, 0x33, 0x2D, 0x00, 0xC2, 0x88, 0x04, 0xA0, 0xB8, 0x05, 0x80, 0x63,
4811 0x00, 0x23, 0xDF, 0x00, 0x4A, 0x00, 0x06, 0x61, 0x00, 0xA2, 0xA4, 0x05,
4812 0x1D, 0x01, 0x06, 0xD6, 0x02, 0x23, 0x02, 0x41, 0x82, 0x01, 0x50, 0x00,
4813 0x62, 0x97, 0x04, 0x85, 0x04, 0x23, 0x02, 0x41, 0x82, 0x01, 0x04, 0x85,
4814 0x08, 0xA0, 0xBE, 0x05, 0xF4, 0x85, 0x03, 0xA0, 0xC4, 0x05, 0xF4, 0x85,
4815 0x01, 0xA0, 0xCE, 0x05, 0x88, 0x00, 0x80, 0x63, 0xCC, 0x86, 0x07, 0xA0,
4816 0xEE, 0x05, 0x5F, 0x00, 0x00, 0x2B, 0xDF, 0x08, 0x00, 0xA2, 0xE6, 0x05,
4817 0x80, 0x67, 0x80, 0x63, 0x01, 0xA2, 0x7A, 0x06, 0x7C, 0x85, 0x06, 0x23,
4818 0x68, 0x98, 0x48, 0x23, 0xF8, 0x88, 0x07, 0x23, 0x80, 0x00, 0x06, 0x87,
4819 0x80, 0x63, 0x7C, 0x85, 0x00, 0x23, 0xDF, 0x00, 0x00, 0x63, 0x4A, 0x00,
4820 0x06, 0x61, 0x00, 0xA2, 0x36, 0x06, 0x1D, 0x01, 0x16, 0xD4, 0xC0, 0x23,
4821 0x07, 0x41, 0x83, 0x03, 0x80, 0x63, 0x06, 0xA6, 0x1C, 0x06, 0x00, 0x33,
4822 0x37, 0x00, 0xC2, 0x88, 0x1D, 0x01, 0x01, 0xD6, 0x20, 0x23, 0x63, 0x60,
4823 0x83, 0x03, 0x80, 0x63, 0x02, 0x23, 0xDF, 0x00, 0x07, 0xA6, 0x7C, 0x05,
4824 0xEF, 0x04, 0x6F, 0x00, 0x00, 0x63, 0x4B, 0x00, 0x06, 0x41, 0xCB, 0x00,
4825 0x52, 0x00, 0x06, 0x61, 0x00, 0xA2, 0x4E, 0x06, 0x1D, 0x01, 0x03, 0xCA,
4826 0xC0, 0x23, 0x07, 0x41, 0x00, 0x63, 0x1D, 0x01, 0x04, 0xCC, 0x00, 0x33,
4827 0x00, 0x83, 0xC0, 0x20, 0x81, 0x62, 0x80, 0x23, 0x07, 0x41, 0x00, 0x63,
4828 0x80, 0x67, 0x08, 0x23, 0x83, 0x03, 0x80, 0x63, 0x00, 0x63, 0x01, 0x23,
4829 0xDF, 0x00, 0x06, 0xA6, 0x84, 0x06, 0x07, 0xA6, 0x7C, 0x05, 0x80, 0x67,
4830 0x80, 0x63, 0x00, 0x33, 0x00, 0x40, 0xC0, 0x20, 0x81, 0x62, 0x00, 0x63,
4831 0x00, 0x00, 0xFE, 0x95, 0x83, 0x03, 0x80, 0x63, 0x06, 0xA6, 0x94, 0x06,
4832 0x07, 0xA6, 0x7C, 0x05, 0x00, 0x00, 0x01, 0xA0, 0x14, 0x07, 0x00, 0x2B,
4833 0x40, 0x0E, 0x80, 0x63, 0x01, 0x00, 0x06, 0xA6, 0xAA, 0x06, 0x07, 0xA6,
4834 0x7C, 0x05, 0x40, 0x0E, 0x80, 0x63, 0x00, 0x43, 0x00, 0xA0, 0xA2, 0x06,
4835 0x06, 0xA6, 0xBC, 0x06, 0x07, 0xA6, 0x7C, 0x05, 0x80, 0x67, 0x40, 0x0E,
4836 0x80, 0x63, 0x07, 0xA6, 0x7C, 0x05, 0x00, 0x23, 0xDF, 0x00, 0x00, 0x63,
4837 0x07, 0xA6, 0xD6, 0x06, 0x00, 0x33, 0x2A, 0x00, 0xC2, 0x88, 0x03, 0x03,
4838 0x80, 0x63, 0x89, 0x00, 0x0A, 0x2B, 0x07, 0xA6, 0xE8, 0x06, 0x00, 0x33,
4839 0x29, 0x00, 0xC2, 0x88, 0x00, 0x43, 0x00, 0xA2, 0xF4, 0x06, 0xC0, 0x0E,
4840 0x80, 0x63, 0xDE, 0x86, 0xC0, 0x0E, 0x00, 0x33, 0x00, 0x80, 0xC0, 0x20,
4841 0x81, 0x62, 0x04, 0x01, 0x02, 0xDA, 0x80, 0x63, 0x7C, 0x85, 0x80, 0x7B,
4842 0x80, 0x63, 0x06, 0xA6, 0x8C, 0x06, 0x00, 0x33, 0x2C, 0x00, 0xC2, 0x88,
4843 0x0C, 0xA2, 0x2E, 0x07, 0xFE, 0x95, 0x83, 0x03, 0x80, 0x63, 0x06, 0xA6,
4844 0x2C, 0x07, 0x07, 0xA6, 0x7C, 0x05, 0x00, 0x33, 0x3D, 0x00, 0xC2, 0x88,
4845 0x00, 0x00, 0x80, 0x67, 0x83, 0x03, 0x80, 0x63, 0x0C, 0xA0, 0x44, 0x07,
4846 0x07, 0xA6, 0x7C, 0x05, 0xBF, 0x23, 0x04, 0x61, 0x84, 0x01, 0xE6, 0x84,
4847 0x00, 0x63, 0xF0, 0x04, 0x01, 0x01, 0xF1, 0x00, 0x00, 0x01, 0xF2, 0x00,
4848 0x01, 0x05, 0x80, 0x01, 0x72, 0x04, 0x71, 0x00, 0x81, 0x01, 0x70, 0x04,
4849 0x80, 0x05, 0x81, 0x05, 0x00, 0x63, 0xF0, 0x04, 0xF2, 0x00, 0x72, 0x04,
4850 0x01, 0x01, 0xF1, 0x00, 0x70, 0x00, 0x81, 0x01, 0x70, 0x04, 0x71, 0x00,
4851 0x81, 0x01, 0x72, 0x00, 0x80, 0x01, 0x71, 0x04, 0x70, 0x00, 0x80, 0x01,
4852 0x70, 0x04, 0x00, 0x63, 0xF0, 0x04, 0xF2, 0x00, 0x72, 0x04, 0x00, 0x01,
4853 0xF1, 0x00, 0x70, 0x00, 0x80, 0x01, 0x70, 0x04, 0x71, 0x00, 0x80, 0x01,
4854 0x72, 0x00, 0x81, 0x01, 0x71, 0x04, 0x70, 0x00, 0x81, 0x01, 0x70, 0x04,
4855 0x00, 0x63, 0x00, 0x23, 0xB3, 0x01, 0x83, 0x05, 0xA3, 0x01, 0xA2, 0x01,
4856 0xA1, 0x01, 0x01, 0x23, 0xA0, 0x01, 0x00, 0x01, 0xC8, 0x00, 0x03, 0xA1,
4857 0xC4, 0x07, 0x00, 0x33, 0x07, 0x00, 0xC2, 0x88, 0x80, 0x05, 0x81, 0x05,
4858 0x04, 0x01, 0x11, 0xC8, 0x48, 0x00, 0xB0, 0x01, 0xB1, 0x01, 0x08, 0x23,
4859 0xB2, 0x01, 0x05, 0x01, 0x48, 0x04, 0x00, 0x43, 0x00, 0xA2, 0xE4, 0x07,
4860 0x00, 0x05, 0xDA, 0x87, 0x00, 0x01, 0xC8, 0x00, 0xFF, 0x23, 0x80, 0x01,
4861 0x05, 0x05, 0x00, 0x63, 0xF7, 0x04, 0x1A, 0x09, 0xF6, 0x08, 0x6E, 0x04,
4862 0x00, 0x02, 0x80, 0x43, 0x76, 0x08, 0x80, 0x02, 0x77, 0x04, 0x00, 0x63,
4863 0xF7, 0x04, 0x1A, 0x09, 0xF6, 0x08, 0x6E, 0x04, 0x00, 0x02, 0x00, 0xA0,
4864 0x14, 0x08, 0x16, 0x88, 0x00, 0x43, 0x76, 0x08, 0x80, 0x02, 0x77, 0x04,
4865 0x00, 0x63, 0xF3, 0x04, 0x00, 0x23, 0xF4, 0x00, 0x74, 0x00, 0x80, 0x43,
4866 0xF4, 0x00, 0xCF, 0x40, 0x00, 0xA2, 0x44, 0x08, 0x74, 0x04, 0x02, 0x01,
4867 0xF7, 0xC9, 0xF6, 0xD9, 0x00, 0x01, 0x01, 0xA1, 0x24, 0x08, 0x04, 0x98,
4868 0x26, 0x95, 0x24, 0x88, 0x73, 0x04, 0x00, 0x63, 0xF3, 0x04, 0x75, 0x04,
4869 0x5A, 0x88, 0x02, 0x01, 0x04, 0xD8, 0x46, 0x97, 0x04, 0x98, 0x26, 0x95,
4870 0x4A, 0x88, 0x75, 0x00, 0x00, 0xA3, 0x64, 0x08, 0x00, 0x05, 0x4E, 0x88,
4871 0x73, 0x04, 0x00, 0x63, 0x80, 0x7B, 0x80, 0x63, 0x06, 0xA6, 0x76, 0x08,
4872 0x00, 0x33, 0x3E, 0x00, 0xC2, 0x88, 0x80, 0x67, 0x83, 0x03, 0x80, 0x63,
4873 0x00, 0x63, 0x38, 0x2B, 0x9C, 0x88, 0x38, 0x2B, 0x92, 0x88, 0x32, 0x09,
4874 0x31, 0x05, 0x92, 0x98, 0x05, 0x05, 0xB2, 0x09, 0x00, 0x63, 0x00, 0x32,
4875 0x00, 0x36, 0x00, 0x3A, 0x00, 0x3E, 0x00, 0x63, 0x80, 0x32, 0x80, 0x36,
4876 0x80, 0x3A, 0x80, 0x3E, 0xB4, 0x3D, 0x00, 0x63, 0x38, 0x2B, 0x40, 0x32,
4877 0x40, 0x36, 0x40, 0x3A, 0x40, 0x3E, 0x00, 0x63, 0x5A, 0x20, 0xC9, 0x40,
4878 0x00, 0xA0, 0xB4, 0x08, 0x5D, 0x00, 0xFE, 0xC3, 0x00, 0x63, 0x80, 0x73,
4879 0xE6, 0x20, 0x02, 0x23, 0xE8, 0x00, 0x82, 0x73, 0xFF, 0xFD, 0x80, 0x73,
4880 0x13, 0x23, 0xF8, 0x88, 0x66, 0x20, 0xC0, 0x20, 0x04, 0x23, 0xA0, 0x01,
4881 0xA1, 0x23, 0xA1, 0x01, 0x81, 0x62, 0xE2, 0x88, 0x80, 0x73, 0x80, 0x77,
4882 0x68, 0x00, 0x00, 0xA2, 0x80, 0x00, 0x03, 0xC2, 0xF1, 0xC7, 0x41, 0x23,
4883 0xF8, 0x88, 0x11, 0x23, 0xA1, 0x01, 0x04, 0x23, 0xA0, 0x01, 0xE6, 0x84,
4886 static unsigned short _asc_mcode_size = sizeof(_asc_mcode_buf);
4887 static ADV_DCNT _asc_mcode_chksum = 0x012C453FUL;
4889 /* Microcode buffer is kept after initialization for error recovery. */
4890 static unsigned char _adv_asc3550_buf[] = {
4891 0x00, 0x00, 0x00, 0xf2, 0x00, 0xf0, 0x00, 0x16, 0x18, 0xe4, 0x00, 0xfc,
4892 0x01, 0x00, 0x48, 0xe4, 0xbe, 0x18, 0x18, 0x80, 0x03, 0xf6, 0x02, 0x00,
4893 0x00, 0xfa, 0xff, 0xff, 0x28, 0x0e, 0x9e, 0xe7, 0xff, 0x00, 0x82, 0xe7,
4894 0x00, 0xea, 0x00, 0xf6, 0x01, 0xe6, 0x09, 0xe7, 0x55, 0xf0, 0x01, 0xf6,
4895 0x01, 0xfa, 0x08, 0x00, 0x03, 0x00, 0x04, 0x00, 0x18, 0xf4, 0x10, 0x00,
4896 0x00, 0xec, 0x85, 0xf0, 0xbc, 0x00, 0xd5, 0xf0, 0x8e, 0x0c, 0x38, 0x54,
4897 0x00, 0xe6, 0x1e, 0xf0, 0x86, 0xf0, 0xb4, 0x00, 0x98, 0x57, 0xd0, 0x01,
4898 0x0c, 0x1c, 0x3e, 0x1c, 0x0c, 0x00, 0xbb, 0x00, 0xaa, 0x18, 0x02, 0x80,
4899 0x32, 0xf0, 0x01, 0xfc, 0x88, 0x0c, 0xc6, 0x12, 0x02, 0x13, 0x18, 0x40,
4900 0x00, 0x57, 0x01, 0xea, 0x3c, 0x00, 0x6c, 0x01, 0x6e, 0x01, 0x04, 0x12,
4901 0x3e, 0x57, 0x00, 0x80, 0x03, 0xe6, 0xb6, 0x00, 0xc0, 0x00, 0x01, 0x01,
4902 0x3e, 0x01, 0xda, 0x0f, 0x22, 0x10, 0x08, 0x12, 0x02, 0x4a, 0xb9, 0x54,
4903 0x03, 0x58, 0x1b, 0x80, 0x30, 0xe4, 0x4b, 0xe4, 0x20, 0x00, 0x32, 0x00,
4904 0x3e, 0x00, 0x80, 0x00, 0x24, 0x01, 0x3c, 0x01, 0x68, 0x01, 0x6a, 0x01,
4905 0x70, 0x01, 0x72, 0x01, 0x74, 0x01, 0x76, 0x01, 0x78, 0x01, 0x62, 0x0a,
4906 0x92, 0x0c, 0x2c, 0x10, 0x2e, 0x10, 0x06, 0x13, 0x4c, 0x1c, 0xbb, 0x55,
4907 0x3c, 0x56, 0x04, 0x80, 0x4a, 0xe4, 0x02, 0xee, 0x5b, 0xf0, 0xb1, 0xf0,
4908 0x03, 0xf7, 0x06, 0xf7, 0x03, 0xfc, 0x0f, 0x00, 0x40, 0x00, 0xbe, 0x00,
4909 0x00, 0x01, 0xb0, 0x08, 0x30, 0x13, 0x64, 0x15, 0x32, 0x1c, 0x38, 0x1c,
4910 0x4e, 0x1c, 0x10, 0x44, 0x02, 0x48, 0x00, 0x4c, 0x04, 0xea, 0x5d, 0xf0,
4911 0x04, 0xf6, 0x02, 0xfc, 0x05, 0x00, 0x34, 0x00, 0x36, 0x00, 0x98, 0x00,
4912 0xcc, 0x00, 0x20, 0x01, 0x4e, 0x01, 0x4e, 0x0b, 0x1e, 0x0e, 0x0c, 0x10,
4913 0x0a, 0x12, 0x04, 0x13, 0x40, 0x13, 0x30, 0x1c, 0x00, 0x4e, 0xbd, 0x56,
4914 0x06, 0x83, 0x00, 0xdc, 0x05, 0xf0, 0x09, 0xf0, 0x59, 0xf0, 0xa7, 0xf0,
4915 0xb8, 0xf0, 0x0e, 0xf7, 0x06, 0x00, 0x19, 0x00, 0x33, 0x00, 0x9b, 0x00,
4916 0xa4, 0x00, 0xb5, 0x00, 0xba, 0x00, 0xd0, 0x00, 0xe1, 0x00, 0xe7, 0x00,
4917 0xde, 0x03, 0x56, 0x0a, 0x14, 0x0e, 0x02, 0x10, 0x04, 0x10, 0x0a, 0x10,
4918 0x36, 0x10, 0x0a, 0x13, 0x12, 0x13, 0x52, 0x13, 0x10, 0x15, 0x14, 0x15,
4919 0xac, 0x16, 0x20, 0x1c, 0x34, 0x1c, 0x36, 0x1c, 0x08, 0x44, 0x38, 0x44,
4920 0x91, 0x44, 0x0a, 0x45, 0x48, 0x46, 0x01, 0x48, 0x68, 0x54, 0x83, 0x55,
4921 0xb0, 0x57, 0x01, 0x58, 0x83, 0x59, 0x05, 0xe6, 0x0b, 0xf0, 0x0c, 0xf0,
4922 0x5c, 0xf0, 0x4b, 0xf4, 0x04, 0xf8, 0x05, 0xf8, 0x02, 0xfa, 0x03, 0xfa,
4923 0x04, 0xfc, 0x05, 0xfc, 0x07, 0x00, 0x0a, 0x00, 0x0d, 0x00, 0x1c, 0x00,
4924 0x9e, 0x00, 0xa8, 0x00, 0xaa, 0x00, 0xb9, 0x00, 0xe0, 0x00, 0x22, 0x01,
4925 0x26, 0x01, 0x79, 0x01, 0x7a, 0x01, 0xc0, 0x01, 0xc2, 0x01, 0x7c, 0x02,
4926 0x5a, 0x03, 0xea, 0x04, 0xe8, 0x07, 0x68, 0x08, 0x69, 0x08, 0xba, 0x08,
4927 0xe9, 0x09, 0x06, 0x0b, 0x3a, 0x0e, 0x00, 0x10, 0x1a, 0x10, 0xed, 0x10,
4928 0xf1, 0x10, 0x06, 0x12, 0x0c, 0x13, 0x16, 0x13, 0x1e, 0x13, 0x82, 0x13,
4929 0x42, 0x14, 0xd6, 0x14, 0x8a, 0x15, 0xc6, 0x17, 0xd2, 0x17, 0x6b, 0x18,
4930 0x12, 0x1c, 0x46, 0x1c, 0x9c, 0x32, 0x00, 0x40, 0x0e, 0x47, 0x48, 0x47,
4931 0x41, 0x48, 0x89, 0x48, 0x80, 0x4c, 0x00, 0x54, 0x44, 0x55, 0xe5, 0x55,
4932 0x14, 0x56, 0x77, 0x57, 0xbf, 0x57, 0x40, 0x5c, 0x06, 0x80, 0x08, 0x90,
4933 0x03, 0xa1, 0xfe, 0x9c, 0xf0, 0x29, 0x02, 0xfe, 0xb8, 0x0c, 0xff, 0x10,
4934 0x00, 0x00, 0xd0, 0xfe, 0xcc, 0x18, 0x00, 0xcf, 0xfe, 0x80, 0x01, 0xff,
4935 0x03, 0x00, 0x00, 0xfe, 0x93, 0x15, 0xfe, 0x0f, 0x05, 0xff, 0x38, 0x00,
4936 0x00, 0xfe, 0x57, 0x24, 0x00, 0xfe, 0x48, 0x00, 0x4f, 0xff, 0x04, 0x00,
4937 0x00, 0x10, 0xff, 0x09, 0x00, 0x00, 0xff, 0x08, 0x01, 0x01, 0xff, 0x08,
4938 0xff, 0xff, 0xff, 0x27, 0x00, 0x00, 0xff, 0x10, 0xff, 0xff, 0xff, 0x0f,
4939 0x00, 0x00, 0xfe, 0x78, 0x56, 0xfe, 0x34, 0x12, 0xff, 0x21, 0x00, 0x00,
4940 0xfe, 0x04, 0xf7, 0xcf, 0x2a, 0x67, 0x0b, 0x01, 0xfe, 0xce, 0x0e, 0xfe,
4941 0x04, 0xf7, 0xcf, 0x67, 0x0b, 0x3c, 0x2a, 0xfe, 0x3d, 0xf0, 0xfe, 0x02,
4942 0x02, 0xfe, 0x20, 0xf0, 0x9c, 0xfe, 0x91, 0xf0, 0xfe, 0xf0, 0x01, 0xfe,
4943 0x90, 0xf0, 0xfe, 0xf0, 0x01, 0xfe, 0x8f, 0xf0, 0x9c, 0x05, 0x51, 0x3b,
4944 0x02, 0xfe, 0xd4, 0x0c, 0x01, 0xfe, 0x44, 0x0d, 0xfe, 0xdd, 0x12, 0xfe,
4945 0xfc, 0x10, 0xfe, 0x28, 0x1c, 0x05, 0xfe, 0xa6, 0x00, 0xfe, 0xd3, 0x12,
4946 0x47, 0x18, 0xfe, 0xa6, 0x00, 0xb5, 0xfe, 0x48, 0xf0, 0xfe, 0x86, 0x02,
4947 0xfe, 0x49, 0xf0, 0xfe, 0xa0, 0x02, 0xfe, 0x4a, 0xf0, 0xfe, 0xbe, 0x02,
4948 0xfe, 0x46, 0xf0, 0xfe, 0x50, 0x02, 0xfe, 0x47, 0xf0, 0xfe, 0x56, 0x02,
4949 0xfe, 0x43, 0xf0, 0xfe, 0x44, 0x02, 0xfe, 0x44, 0xf0, 0xfe, 0x48, 0x02,
4950 0xfe, 0x45, 0xf0, 0xfe, 0x4c, 0x02, 0x17, 0x0b, 0xa0, 0x17, 0x06, 0x18,
4951 0x96, 0x02, 0x29, 0xfe, 0x00, 0x1c, 0xde, 0xfe, 0x02, 0x1c, 0xdd, 0xfe,
4952 0x1e, 0x1c, 0xfe, 0xe9, 0x10, 0x01, 0xfe, 0x20, 0x17, 0xfe, 0xe7, 0x10,
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5248 0x4a, 0x01, 0x08, 0x03, 0x60, 0x03, 0x1e, 0xcc, 0x07, 0x06, 0xfe, 0x44,
5249 0x13, 0xad, 0x12, 0xcc, 0xfe, 0x49, 0xf4, 0x00, 0x3b, 0x72, 0x9f, 0x5e,
5250 0xfe, 0x01, 0xec, 0xfe, 0x27, 0x01, 0xf1, 0x01, 0x08, 0x2f, 0x07, 0xfe,
5251 0xe3, 0x00, 0xfe, 0x20, 0x13, 0x1f, 0xfe, 0x5a, 0x15, 0x23, 0x12, 0xcd,
5252 0x01, 0x43, 0x1e, 0xcd, 0x07, 0x06, 0x45, 0x09, 0x4a, 0x06, 0x35, 0x03,
5253 0x0a, 0x42, 0x01, 0x0e, 0xed, 0x88, 0x07, 0x10, 0xa4, 0x0a, 0x80, 0x01,
5254 0x0e, 0x88, 0x0a, 0x51, 0x01, 0x9e, 0x03, 0x0a, 0x80, 0x01, 0x0e, 0x88,
5255 0xfe, 0x80, 0xe7, 0x10, 0x07, 0x10, 0x84, 0xfe, 0x45, 0x58, 0x01, 0xe3,
5256 0x88, 0x03, 0x0a, 0x42, 0x01, 0x0e, 0x88, 0x0a, 0x51, 0x01, 0x9e, 0x03,
5257 0x0a, 0x42, 0x01, 0x0e, 0xfe, 0x80, 0x80, 0xf2, 0xfe, 0x49, 0xe4, 0x10,
5258 0xa4, 0x0a, 0x80, 0x01, 0x0e, 0xf2, 0x0a, 0x51, 0x01, 0x82, 0x03, 0x17,
5259 0x10, 0x71, 0x66, 0xfe, 0x60, 0x01, 0xfe, 0x18, 0xdf, 0xfe, 0x19, 0xde,
5260 0xfe, 0x24, 0x1c, 0xfe, 0x1d, 0xf7, 0x1d, 0x90, 0xfe, 0xf6, 0x15, 0x01,
5261 0xfe, 0xfc, 0x16, 0xe0, 0x91, 0x1d, 0x66, 0xfe, 0x2c, 0x01, 0xfe, 0x2f,
5262 0x19, 0x03, 0xae, 0x21, 0xfe, 0xe6, 0x15, 0xfe, 0xda, 0x10, 0x17, 0x10,
5263 0x71, 0x05, 0xfe, 0x64, 0x01, 0xfe, 0x00, 0xf4, 0x19, 0xfe, 0x18, 0x58,
5264 0x05, 0xfe, 0x66, 0x01, 0xfe, 0x19, 0x58, 0x91, 0x19, 0xfe, 0x3c, 0x90,
5265 0xfe, 0x30, 0xf4, 0x06, 0xfe, 0x3c, 0x50, 0x66, 0xfe, 0x38, 0x00, 0xfe,
5266 0x0f, 0x79, 0xfe, 0x1c, 0xf7, 0x19, 0x90, 0xfe, 0x40, 0x16, 0xfe, 0xb6,
5267 0x14, 0x34, 0x03, 0xae, 0x21, 0xfe, 0x18, 0x16, 0xfe, 0x9c, 0x10, 0x17,
5268 0x10, 0x71, 0xfe, 0x83, 0x5a, 0xfe, 0x18, 0xdf, 0xfe, 0x19, 0xde, 0xfe,
5269 0x1d, 0xf7, 0x38, 0x90, 0xfe, 0x62, 0x16, 0xfe, 0x94, 0x14, 0xfe, 0x10,
5270 0x13, 0x91, 0x38, 0x66, 0x1b, 0xfe, 0xaf, 0x19, 0xfe, 0x98, 0xe7, 0x00,
5271 0x03, 0xae, 0x21, 0xfe, 0x56, 0x16, 0xfe, 0x6c, 0x10, 0x17, 0x10, 0x71,
5272 0xfe, 0x30, 0xbc, 0xfe, 0xb2, 0xbc, 0x91, 0xc5, 0x66, 0x1b, 0xfe, 0x0f,
5273 0x79, 0xfe, 0x1c, 0xf7, 0xc5, 0x90, 0xfe, 0x9a, 0x16, 0xfe, 0x5c, 0x14,
5274 0x34, 0x03, 0xae, 0x21, 0xfe, 0x86, 0x16, 0xfe, 0x42, 0x10, 0xfe, 0x02,
5275 0xf6, 0x10, 0x71, 0xfe, 0x18, 0xfe, 0x54, 0xfe, 0x19, 0xfe, 0x55, 0xfc,
5276 0xfe, 0x1d, 0xf7, 0x4f, 0x90, 0xfe, 0xc0, 0x16, 0xfe, 0x36, 0x14, 0xfe,
5277 0x1c, 0x13, 0x91, 0x4f, 0x47, 0xfe, 0x83, 0x58, 0xfe, 0xaf, 0x19, 0xfe,
5278 0x80, 0xe7, 0x10, 0xfe, 0x81, 0xe7, 0x10, 0x11, 0xfe, 0xdd, 0x00, 0x63,
5279 0x27, 0x03, 0x63, 0x27, 0xfe, 0x12, 0x45, 0x21, 0xfe, 0xb0, 0x16, 0x14,
5280 0x06, 0x37, 0x95, 0xa9, 0x02, 0x29, 0xfe, 0x39, 0xf0, 0xfe, 0x04, 0x17,
5281 0x23, 0x03, 0xfe, 0x7e, 0x18, 0x1c, 0x1a, 0x5d, 0x13, 0x0d, 0x03, 0x71,
5282 0x05, 0xcb, 0x1c, 0x06, 0xfe, 0xef, 0x12, 0xfe, 0xe1, 0x10, 0x78, 0x2c,
5283 0x46, 0x2f, 0x07, 0x2d, 0xfe, 0x3c, 0x13, 0xfe, 0x82, 0x14, 0xfe, 0x42,
5284 0x13, 0x3c, 0x8a, 0x0a, 0x42, 0x01, 0x0e, 0xb0, 0xfe, 0x3e, 0x12, 0xf0,
5285 0xfe, 0x45, 0x48, 0x01, 0xe3, 0xfe, 0x00, 0xcc, 0xb0, 0xfe, 0xf3, 0x13,
5286 0x3d, 0x75, 0x07, 0x10, 0xa3, 0x0a, 0x80, 0x01, 0x0e, 0xf2, 0x01, 0x6f,
5287 0xfe, 0x16, 0x10, 0x07, 0x7e, 0x85, 0xfe, 0x40, 0x14, 0xfe, 0x24, 0x12,
5288 0xf6, 0xfe, 0xd6, 0xf0, 0xfe, 0x24, 0x17, 0x17, 0x0b, 0x03, 0xfe, 0x9c,
5289 0xe7, 0x0b, 0x0f, 0xfe, 0x15, 0x00, 0x59, 0x76, 0x27, 0x01, 0xda, 0x17,
5290 0x06, 0x03, 0x3c, 0x8a, 0x09, 0x4a, 0x1d, 0x35, 0x11, 0x2d, 0x01, 0x6f,
5291 0x17, 0x06, 0x03, 0xfe, 0x38, 0x90, 0xfe, 0xba, 0x90, 0x79, 0xc7, 0x68,
5292 0xc8, 0xfe, 0x48, 0x55, 0x34, 0xfe, 0xc9, 0x55, 0x03, 0x1e, 0x98, 0x73,
5293 0x12, 0x98, 0x03, 0x0a, 0x99, 0x01, 0x0e, 0xf0, 0x0a, 0x40, 0x01, 0x0e,
5294 0xfe, 0x49, 0x44, 0x16, 0xfe, 0xf0, 0x17, 0x73, 0x75, 0x03, 0x0a, 0x42,
5295 0x01, 0x0e, 0x07, 0x10, 0x45, 0x0a, 0x51, 0x01, 0x9e, 0x0a, 0x40, 0x01,
5296 0x0e, 0x73, 0x75, 0x03, 0xfe, 0x4e, 0xe4, 0x1a, 0x64, 0xfe, 0x24, 0x18,
5297 0x05, 0xfe, 0x90, 0x00, 0xfe, 0x3a, 0x45, 0x5b, 0xfe, 0x4e, 0xe4, 0xc2,
5298 0x64, 0xfe, 0x36, 0x18, 0x05, 0xfe, 0x92, 0x00, 0xfe, 0x02, 0xe6, 0x1b,
5299 0xdc, 0xfe, 0x4e, 0xe4, 0xfe, 0x0b, 0x00, 0x64, 0xfe, 0x48, 0x18, 0x05,
5300 0xfe, 0x94, 0x00, 0xfe, 0x02, 0xe6, 0x19, 0xfe, 0x08, 0x10, 0x05, 0xfe,
5301 0x96, 0x00, 0xfe, 0x02, 0xe6, 0x2c, 0xfe, 0x4e, 0x45, 0xfe, 0x0c, 0x12,
5302 0xaf, 0xff, 0x04, 0x68, 0x54, 0xde, 0x1c, 0x69, 0x03, 0x07, 0x7a, 0xfe,
5303 0x5a, 0xf0, 0xfe, 0x74, 0x18, 0x24, 0xfe, 0x09, 0x00, 0xfe, 0x34, 0x10,
5304 0x07, 0x1b, 0xfe, 0x5a, 0xf0, 0xfe, 0x82, 0x18, 0x24, 0xc3, 0xfe, 0x26,
5305 0x10, 0x07, 0x1a, 0x5d, 0x24, 0x2c, 0xdc, 0x07, 0x0b, 0x5d, 0x24, 0x93,
5306 0xfe, 0x0e, 0x10, 0x07, 0x06, 0x5d, 0x24, 0x4d, 0x9f, 0xad, 0x03, 0x14,
5307 0xfe, 0x09, 0x00, 0x01, 0x33, 0xfe, 0x04, 0xfe, 0x7d, 0x05, 0x7f, 0xf9,
5308 0x03, 0x25, 0xfe, 0xca, 0x18, 0xfe, 0x14, 0xf0, 0x08, 0x65, 0xfe, 0xc6,
5309 0x18, 0x03, 0xff, 0x1a, 0x00, 0x00,
5312 static unsigned short _adv_asc3550_size = sizeof(_adv_asc3550_buf); /* 0x13AD */
5313 static ADV_DCNT _adv_asc3550_chksum = 0x04D52DDDUL; /* Expanded little-endian checksum. */
5315 /* Microcode buffer is kept after initialization for error recovery. */
5316 static unsigned char _adv_asc38C0800_buf[] = {
5317 0x00, 0x00, 0x00, 0xf2, 0x00, 0xf0, 0x00, 0xfc, 0x00, 0x16, 0x18, 0xe4,
5318 0x01, 0x00, 0x48, 0xe4, 0x18, 0x80, 0x03, 0xf6, 0x02, 0x00, 0xce, 0x19,
5319 0x00, 0xfa, 0xff, 0xff, 0x1c, 0x0f, 0x00, 0xf6, 0x9e, 0xe7, 0xff, 0x00,
5320 0x82, 0xe7, 0x00, 0xea, 0x01, 0xfa, 0x01, 0xe6, 0x09, 0xe7, 0x55, 0xf0,
5321 0x01, 0xf6, 0x03, 0x00, 0x04, 0x00, 0x10, 0x00, 0x1e, 0xf0, 0x85, 0xf0,
5322 0x18, 0xf4, 0x08, 0x00, 0xbc, 0x00, 0x38, 0x54, 0x00, 0xec, 0xd5, 0xf0,
5323 0x82, 0x0d, 0x00, 0xe6, 0x86, 0xf0, 0xb1, 0xf0, 0x98, 0x57, 0x01, 0xfc,
5324 0xb4, 0x00, 0xd4, 0x01, 0x0c, 0x1c, 0x3e, 0x1c, 0x3c, 0x00, 0xbb, 0x00,
5325 0x00, 0x10, 0xba, 0x19, 0x02, 0x80, 0x32, 0xf0, 0x7c, 0x0d, 0x02, 0x13,
5326 0xba, 0x13, 0x18, 0x40, 0x00, 0x57, 0x01, 0xea, 0x02, 0xfc, 0x03, 0xfc,
5327 0x3e, 0x00, 0x6c, 0x01, 0x6e, 0x01, 0x74, 0x01, 0x76, 0x01, 0xb9, 0x54,
5328 0x3e, 0x57, 0x00, 0x80, 0x03, 0xe6, 0xb6, 0x00, 0xc0, 0x00, 0x01, 0x01,
5329 0x3e, 0x01, 0x7a, 0x01, 0xca, 0x08, 0xce, 0x10, 0x16, 0x11, 0x04, 0x12,
5330 0x08, 0x12, 0x02, 0x4a, 0xbb, 0x55, 0x3c, 0x56, 0x03, 0x58, 0x1b, 0x80,
5331 0x30, 0xe4, 0x4b, 0xe4, 0x5d, 0xf0, 0x02, 0xfa, 0x20, 0x00, 0x32, 0x00,
5332 0x40, 0x00, 0x80, 0x00, 0x24, 0x01, 0x3c, 0x01, 0x68, 0x01, 0x6a, 0x01,
5333 0x70, 0x01, 0x72, 0x01, 0x78, 0x01, 0x7c, 0x01, 0x62, 0x0a, 0x86, 0x0d,
5334 0x06, 0x13, 0x4c, 0x1c, 0x04, 0x80, 0x4a, 0xe4, 0x02, 0xee, 0x5b, 0xf0,
5335 0x03, 0xf7, 0x0c, 0x00, 0x0f, 0x00, 0x47, 0x00, 0xbe, 0x00, 0x00, 0x01,
5336 0x20, 0x11, 0x5c, 0x16, 0x32, 0x1c, 0x38, 0x1c, 0x4e, 0x1c, 0x10, 0x44,
5337 0x00, 0x4c, 0x04, 0xea, 0x5c, 0xf0, 0xa7, 0xf0, 0x04, 0xf6, 0x03, 0xfa,
5338 0x05, 0x00, 0x34, 0x00, 0x36, 0x00, 0x98, 0x00, 0xcc, 0x00, 0x20, 0x01,
5339 0x4e, 0x01, 0x4a, 0x0b, 0x42, 0x0c, 0x12, 0x0f, 0x0c, 0x10, 0x22, 0x11,
5340 0x0a, 0x12, 0x04, 0x13, 0x30, 0x1c, 0x02, 0x48, 0x00, 0x4e, 0x42, 0x54,
5341 0x44, 0x55, 0xbd, 0x56, 0x06, 0x83, 0x00, 0xdc, 0x05, 0xf0, 0x09, 0xf0,
5342 0x59, 0xf0, 0xb8, 0xf0, 0x4b, 0xf4, 0x06, 0xf7, 0x0e, 0xf7, 0x04, 0xfc,
5343 0x05, 0xfc, 0x06, 0x00, 0x19, 0x00, 0x33, 0x00, 0x9b, 0x00, 0xa4, 0x00,
5344 0xb5, 0x00, 0xba, 0x00, 0xd0, 0x00, 0xe1, 0x00, 0xe7, 0x00, 0xe2, 0x03,
5345 0x08, 0x0f, 0x02, 0x10, 0x04, 0x10, 0x0a, 0x10, 0x0a, 0x13, 0x0c, 0x13,
5346 0x12, 0x13, 0x24, 0x14, 0x34, 0x14, 0x04, 0x16, 0x08, 0x16, 0xa4, 0x17,
5347 0x20, 0x1c, 0x34, 0x1c, 0x36, 0x1c, 0x08, 0x44, 0x38, 0x44, 0x91, 0x44,
5348 0x0a, 0x45, 0x48, 0x46, 0x01, 0x48, 0x68, 0x54, 0x3a, 0x55, 0x83, 0x55,
5349 0xe5, 0x55, 0xb0, 0x57, 0x01, 0x58, 0x83, 0x59, 0x05, 0xe6, 0x0b, 0xf0,
5350 0x0c, 0xf0, 0x04, 0xf8, 0x05, 0xf8, 0x07, 0x00, 0x0a, 0x00, 0x1c, 0x00,
5351 0x1e, 0x00, 0x9e, 0x00, 0xa8, 0x00, 0xaa, 0x00, 0xb9, 0x00, 0xe0, 0x00,
5352 0x22, 0x01, 0x26, 0x01, 0x79, 0x01, 0x7e, 0x01, 0xc4, 0x01, 0xc6, 0x01,
5353 0x80, 0x02, 0x5e, 0x03, 0xee, 0x04, 0x9a, 0x06, 0xf8, 0x07, 0x62, 0x08,
5354 0x68, 0x08, 0x69, 0x08, 0xd6, 0x08, 0xe9, 0x09, 0xfa, 0x0b, 0x2e, 0x0f,
5355 0x12, 0x10, 0x1a, 0x10, 0xed, 0x10, 0xf1, 0x10, 0x2a, 0x11, 0x06, 0x12,
5356 0x0c, 0x12, 0x3e, 0x12, 0x10, 0x13, 0x16, 0x13, 0x1e, 0x13, 0x46, 0x14,
5357 0x76, 0x14, 0x82, 0x14, 0x36, 0x15, 0xca, 0x15, 0x6b, 0x18, 0xbe, 0x18,
5358 0xca, 0x18, 0xe6, 0x19, 0x12, 0x1c, 0x46, 0x1c, 0x9c, 0x32, 0x00, 0x40,
5359 0x0e, 0x47, 0xfe, 0x9c, 0xf0, 0x2b, 0x02, 0xfe, 0xac, 0x0d, 0xff, 0x10,
5360 0x00, 0x00, 0xd7, 0xfe, 0xe8, 0x19, 0x00, 0xd6, 0xfe, 0x84, 0x01, 0xff,
5361 0x03, 0x00, 0x00, 0xfe, 0x93, 0x15, 0xfe, 0x0f, 0x05, 0xff, 0x38, 0x00,
5362 0x00, 0xfe, 0x57, 0x24, 0x00, 0xfe, 0x4c, 0x00, 0x5b, 0xff, 0x04, 0x00,
5363 0x00, 0x11, 0xff, 0x09, 0x00, 0x00, 0xff, 0x08, 0x01, 0x01, 0xff, 0x08,
5364 0xff, 0xff, 0xff, 0x27, 0x00, 0x00, 0xff, 0x10, 0xff, 0xff, 0xff, 0x11,
5365 0x00, 0x00, 0xfe, 0x78, 0x56, 0xfe, 0x34, 0x12, 0xff, 0x21, 0x00, 0x00,
5366 0xfe, 0x04, 0xf7, 0xd6, 0x2c, 0x99, 0x0a, 0x01, 0xfe, 0xc2, 0x0f, 0xfe,
5367 0x04, 0xf7, 0xd6, 0x99, 0x0a, 0x42, 0x2c, 0xfe, 0x3d, 0xf0, 0xfe, 0x06,
5368 0x02, 0xfe, 0x20, 0xf0, 0xa7, 0xfe, 0x91, 0xf0, 0xfe, 0xf4, 0x01, 0xfe,
5369 0x90, 0xf0, 0xfe, 0xf4, 0x01, 0xfe, 0x8f, 0xf0, 0xa7, 0x03, 0x5d, 0x4d,
5370 0x02, 0xfe, 0xc8, 0x0d, 0x01, 0xfe, 0x38, 0x0e, 0xfe, 0xdd, 0x12, 0xfe,
5371 0xfc, 0x10, 0xfe, 0x28, 0x1c, 0x03, 0xfe, 0xa6, 0x00, 0xfe, 0xd3, 0x12,
5372 0x41, 0x14, 0xfe, 0xa6, 0x00, 0xc2, 0xfe, 0x48, 0xf0, 0xfe, 0x8a, 0x02,
5373 0xfe, 0x49, 0xf0, 0xfe, 0xa4, 0x02, 0xfe, 0x4a, 0xf0, 0xfe, 0xc2, 0x02,
5374 0xfe, 0x46, 0xf0, 0xfe, 0x54, 0x02, 0xfe, 0x47, 0xf0, 0xfe, 0x5a, 0x02,
5375 0xfe, 0x43, 0xf0, 0xfe, 0x48, 0x02, 0xfe, 0x44, 0xf0, 0xfe, 0x4c, 0x02,
5376 0xfe, 0x45, 0xf0, 0xfe, 0x50, 0x02, 0x18, 0x0a, 0xaa, 0x18, 0x06, 0x14,
5377 0xa1, 0x02, 0x2b, 0xfe, 0x00, 0x1c, 0xe7, 0xfe, 0x02, 0x1c, 0xe6, 0xfe,
5378 0x1e, 0x1c, 0xfe, 0xe9, 0x10, 0x01, 0xfe, 0x18, 0x18, 0xfe, 0xe7, 0x10,
5379 0xfe, 0x06, 0xfc, 0xce, 0x09, 0x70, 0x01, 0xa8, 0x02, 0x2b, 0x15, 0x59,
5380 0x39, 0xa2, 0x01, 0xfe, 0x58, 0x10, 0x09, 0x70, 0x01, 0x87, 0xfe, 0xbd,
5381 0x10, 0x09, 0x70, 0x01, 0x87, 0xfe, 0xad, 0x10, 0xfe, 0x16, 0x1c, 0xfe,
5382 0x58, 0x1c, 0x18, 0x06, 0x14, 0xa1, 0x2c, 0x1c, 0x2b, 0xfe, 0x3d, 0xf0,
5383 0xfe, 0x06, 0x02, 0x23, 0xfe, 0x98, 0x02, 0xfe, 0x5a, 0x1c, 0xf8, 0xfe,
5384 0x14, 0x1c, 0x15, 0xfe, 0x30, 0x00, 0x39, 0xa2, 0x01, 0xfe, 0x48, 0x10,
5385 0x18, 0x06, 0x14, 0xa1, 0x02, 0xd7, 0x22, 0x20, 0x07, 0x11, 0x35, 0xfe,
5386 0x69, 0x10, 0x18, 0x06, 0x14, 0xa1, 0xfe, 0x04, 0xec, 0x20, 0x4f, 0x43,
5387 0x13, 0x20, 0xfe, 0x05, 0xf6, 0xce, 0x01, 0xfe, 0x4a, 0x17, 0x08, 0x54,
5388 0x58, 0x37, 0x12, 0x2f, 0x42, 0x92, 0x01, 0xfe, 0x82, 0x16, 0x02, 0x2b,
5389 0x09, 0x46, 0x01, 0x0e, 0x07, 0x00, 0x66, 0x01, 0x73, 0xfe, 0x18, 0x10,
5390 0xfe, 0x41, 0x58, 0x09, 0xa4, 0x01, 0x0e, 0xfe, 0xc8, 0x54, 0x6b, 0xfe,
5391 0x10, 0x03, 0x01, 0xfe, 0x82, 0x16, 0x02, 0x2b, 0x2c, 0x4f, 0xfe, 0x02,
5392 0xe8, 0x2a, 0xfe, 0xbf, 0x57, 0xfe, 0x9e, 0x43, 0xfe, 0x77, 0x57, 0xfe,
5393 0x27, 0xf0, 0xfe, 0xe0, 0x01, 0xfe, 0x07, 0x4b, 0xfe, 0x20, 0xf0, 0xa7,
5394 0xfe, 0x40, 0x1c, 0x1c, 0xd9, 0xfe, 0x26, 0xf0, 0xfe, 0x5a, 0x03, 0xfe,
5395 0xa0, 0xf0, 0xfe, 0x48, 0x03, 0xfe, 0x11, 0xf0, 0xa7, 0xfe, 0xef, 0x10,
5396 0xfe, 0x9f, 0xf0, 0xfe, 0x68, 0x03, 0xf9, 0x10, 0xfe, 0x11, 0x00, 0x02,
5397 0x65, 0x2c, 0xfe, 0x48, 0x1c, 0xf9, 0x08, 0x05, 0x1b, 0xfe, 0x18, 0x13,
5398 0x21, 0x22, 0xa3, 0xb7, 0x13, 0xa3, 0x09, 0x46, 0x01, 0x0e, 0xb7, 0x78,
5399 0x01, 0xfe, 0xb4, 0x16, 0x12, 0xd1, 0x1c, 0xd9, 0xfe, 0x01, 0xf0, 0xd9,
5400 0xfe, 0x82, 0xf0, 0xfe, 0x96, 0x03, 0xfa, 0x12, 0xfe, 0xe4, 0x00, 0x27,
5401 0xfe, 0xa8, 0x03, 0x1c, 0x34, 0x1d, 0xfe, 0xb8, 0x03, 0x01, 0x4b, 0xfe,
5402 0x06, 0xf0, 0xfe, 0xc8, 0x03, 0x95, 0x86, 0xfe, 0x0a, 0xf0, 0xfe, 0x8a,
5403 0x06, 0x02, 0x24, 0x03, 0x70, 0x28, 0x17, 0xfe, 0xfa, 0x04, 0x15, 0x6d,
5404 0x01, 0x36, 0x7b, 0xfe, 0x6a, 0x02, 0x02, 0xd8, 0xf9, 0x2c, 0x99, 0x19,
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5701 0x4e, 0x08, 0x54, 0x06, 0x37, 0x04, 0x09, 0x48, 0x01, 0x0e, 0xfb, 0x8e,
5702 0x07, 0x11, 0xae, 0x09, 0x84, 0x01, 0x0e, 0x8e, 0x09, 0x5d, 0x01, 0xa8,
5703 0x04, 0x09, 0x84, 0x01, 0x0e, 0x8e, 0xfe, 0x80, 0xe7, 0x11, 0x07, 0x11,
5704 0x8a, 0xfe, 0x45, 0x58, 0x01, 0xf0, 0x8e, 0x04, 0x09, 0x48, 0x01, 0x0e,
5705 0x8e, 0x09, 0x5d, 0x01, 0xa8, 0x04, 0x09, 0x48, 0x01, 0x0e, 0xfe, 0x80,
5706 0x80, 0xfe, 0x80, 0x4c, 0xfe, 0x49, 0xe4, 0x11, 0xae, 0x09, 0x84, 0x01,
5707 0x0e, 0xfe, 0x80, 0x4c, 0x09, 0x5d, 0x01, 0x87, 0x04, 0x18, 0x11, 0x75,
5708 0x6c, 0xfe, 0x60, 0x01, 0xfe, 0x18, 0xdf, 0xfe, 0x19, 0xde, 0xfe, 0x24,
5709 0x1c, 0xfe, 0x1d, 0xf7, 0x1b, 0x97, 0xfe, 0xee, 0x16, 0x01, 0xfe, 0xf4,
5710 0x17, 0xad, 0x9a, 0x1b, 0x6c, 0xfe, 0x2c, 0x01, 0xfe, 0x2f, 0x19, 0x04,
5711 0xb9, 0x23, 0xfe, 0xde, 0x16, 0xfe, 0xda, 0x10, 0x18, 0x11, 0x75, 0x03,
5712 0xfe, 0x64, 0x01, 0xfe, 0x00, 0xf4, 0x1f, 0xfe, 0x18, 0x58, 0x03, 0xfe,
5713 0x66, 0x01, 0xfe, 0x19, 0x58, 0x9a, 0x1f, 0xfe, 0x3c, 0x90, 0xfe, 0x30,
5714 0xf4, 0x06, 0xfe, 0x3c, 0x50, 0x6c, 0xfe, 0x38, 0x00, 0xfe, 0x0f, 0x79,
5715 0xfe, 0x1c, 0xf7, 0x1f, 0x97, 0xfe, 0x38, 0x17, 0xfe, 0xb6, 0x14, 0x35,
5716 0x04, 0xb9, 0x23, 0xfe, 0x10, 0x17, 0xfe, 0x9c, 0x10, 0x18, 0x11, 0x75,
5717 0xfe, 0x83, 0x5a, 0xfe, 0x18, 0xdf, 0xfe, 0x19, 0xde, 0xfe, 0x1d, 0xf7,
5718 0x2e, 0x97, 0xfe, 0x5a, 0x17, 0xfe, 0x94, 0x14, 0xec, 0x9a, 0x2e, 0x6c,
5719 0x1a, 0xfe, 0xaf, 0x19, 0xfe, 0x98, 0xe7, 0x00, 0x04, 0xb9, 0x23, 0xfe,
5720 0x4e, 0x17, 0xfe, 0x6c, 0x10, 0x18, 0x11, 0x75, 0xfe, 0x30, 0xbc, 0xfe,
5721 0xb2, 0xbc, 0x9a, 0xcb, 0x6c, 0x1a, 0xfe, 0x0f, 0x79, 0xfe, 0x1c, 0xf7,
5722 0xcb, 0x97, 0xfe, 0x92, 0x17, 0xfe, 0x5c, 0x14, 0x35, 0x04, 0xb9, 0x23,
5723 0xfe, 0x7e, 0x17, 0xfe, 0x42, 0x10, 0xfe, 0x02, 0xf6, 0x11, 0x75, 0xfe,
5724 0x18, 0xfe, 0x60, 0xfe, 0x19, 0xfe, 0x61, 0xfe, 0x03, 0xa1, 0xfe, 0x1d,
5725 0xf7, 0x5b, 0x97, 0xfe, 0xb8, 0x17, 0xfe, 0x36, 0x14, 0xfe, 0x1c, 0x13,
5726 0x9a, 0x5b, 0x41, 0xfe, 0x83, 0x58, 0xfe, 0xaf, 0x19, 0xfe, 0x80, 0xe7,
5727 0x11, 0xfe, 0x81, 0xe7, 0x11, 0x12, 0xfe, 0xdd, 0x00, 0x6a, 0x2a, 0x04,
5728 0x6a, 0x2a, 0xfe, 0x12, 0x45, 0x23, 0xfe, 0xa8, 0x17, 0x15, 0x06, 0x39,
5729 0xa0, 0xb4, 0x02, 0x2b, 0xfe, 0x39, 0xf0, 0xfe, 0xfc, 0x17, 0x21, 0x04,
5730 0xfe, 0x7e, 0x18, 0x1e, 0x19, 0x66, 0x0f, 0x0d, 0x04, 0x75, 0x03, 0xd2,
5731 0x1e, 0x06, 0xfe, 0xef, 0x12, 0xfe, 0xe1, 0x10, 0x7c, 0x6f, 0x4f, 0x32,
5732 0x07, 0x2f, 0xfe, 0x3c, 0x13, 0xf1, 0xfe, 0x42, 0x13, 0x42, 0x92, 0x09,
5733 0x48, 0x01, 0x0e, 0xbb, 0xeb, 0xfe, 0x41, 0x48, 0xfe, 0x45, 0x48, 0x01,
5734 0xf0, 0xfe, 0x00, 0xcc, 0xbb, 0xfe, 0xf3, 0x13, 0x43, 0x78, 0x07, 0x11,
5735 0xac, 0x09, 0x84, 0x01, 0x0e, 0xfe, 0x80, 0x4c, 0x01, 0x73, 0xfe, 0x16,
5736 0x10, 0x07, 0x82, 0x8b, 0xfe, 0x40, 0x14, 0xfe, 0x24, 0x12, 0xfe, 0x14,
5737 0x56, 0xfe, 0xd6, 0xf0, 0xfe, 0x1c, 0x18, 0x18, 0x0a, 0x04, 0xfe, 0x9c,
5738 0xe7, 0x0a, 0x10, 0xfe, 0x15, 0x00, 0x64, 0x79, 0x2a, 0x01, 0xe3, 0x18,
5739 0x06, 0x04, 0x42, 0x92, 0x08, 0x54, 0x1b, 0x37, 0x12, 0x2f, 0x01, 0x73,
5740 0x18, 0x06, 0x04, 0xfe, 0x38, 0x90, 0xfe, 0xba, 0x90, 0x3a, 0xce, 0x3b,
5741 0xcf, 0xfe, 0x48, 0x55, 0x35, 0xfe, 0xc9, 0x55, 0x04, 0x22, 0xa3, 0x77,
5742 0x13, 0xa3, 0x04, 0x09, 0xa4, 0x01, 0x0e, 0xfe, 0x41, 0x48, 0x09, 0x46,
5743 0x01, 0x0e, 0xfe, 0x49, 0x44, 0x17, 0xfe, 0xe8, 0x18, 0x77, 0x78, 0x04,
5744 0x09, 0x48, 0x01, 0x0e, 0x07, 0x11, 0x4e, 0x09, 0x5d, 0x01, 0xa8, 0x09,
5745 0x46, 0x01, 0x0e, 0x77, 0x78, 0x04, 0xfe, 0x4e, 0xe4, 0x19, 0x6b, 0xfe,
5746 0x1c, 0x19, 0x03, 0xfe, 0x90, 0x00, 0xfe, 0x3a, 0x45, 0xfe, 0x2c, 0x10,
5747 0xfe, 0x4e, 0xe4, 0xc9, 0x6b, 0xfe, 0x2e, 0x19, 0x03, 0xfe, 0x92, 0x00,
5748 0xfe, 0x02, 0xe6, 0x1a, 0xe5, 0xfe, 0x4e, 0xe4, 0xfe, 0x0b, 0x00, 0x6b,
5749 0xfe, 0x40, 0x19, 0x03, 0xfe, 0x94, 0x00, 0xfe, 0x02, 0xe6, 0x1f, 0xfe,
5750 0x08, 0x10, 0x03, 0xfe, 0x96, 0x00, 0xfe, 0x02, 0xe6, 0x6d, 0xfe, 0x4e,
5751 0x45, 0xea, 0xba, 0xff, 0x04, 0x68, 0x54, 0xe7, 0x1e, 0x6e, 0xfe, 0x08,
5752 0x1c, 0xfe, 0x67, 0x19, 0xfe, 0x0a, 0x1c, 0xfe, 0x1a, 0xf4, 0xfe, 0x00,
5753 0x04, 0xea, 0xfe, 0x48, 0xf4, 0x19, 0x7a, 0xfe, 0x74, 0x19, 0x0f, 0x19,
5754 0x04, 0x07, 0x7e, 0xfe, 0x5a, 0xf0, 0xfe, 0x84, 0x19, 0x25, 0xfe, 0x09,
5755 0x00, 0xfe, 0x34, 0x10, 0x07, 0x1a, 0xfe, 0x5a, 0xf0, 0xfe, 0x92, 0x19,
5756 0x25, 0xca, 0xfe, 0x26, 0x10, 0x07, 0x19, 0x66, 0x25, 0x6d, 0xe5, 0x07,
5757 0x0a, 0x66, 0x25, 0x9e, 0xfe, 0x0e, 0x10, 0x07, 0x06, 0x66, 0x25, 0x59,
5758 0xa9, 0xb8, 0x04, 0x15, 0xfe, 0x09, 0x00, 0x01, 0x36, 0xfe, 0x04, 0xfe,
5759 0x81, 0x03, 0x83, 0xfe, 0x40, 0x5c, 0x04, 0x1c, 0xf7, 0xfe, 0x14, 0xf0,
5760 0x0b, 0x27, 0xfe, 0xd6, 0x19, 0x1c, 0xf7, 0x7b, 0xf7, 0xfe, 0x82, 0xf0,
5761 0xfe, 0xda, 0x19, 0x04, 0xff, 0xcc, 0x00, 0x00,
5764 static unsigned short _adv_asc38C0800_size = sizeof(_adv_asc38C0800_buf); /* 0x14E1 */
5765 static ADV_DCNT _adv_asc38C0800_chksum = 0x050D3FD8UL; /* Expanded little-endian checksum. */
5767 /* Microcode buffer is kept after initialization for error recovery. */
5768 static unsigned char _adv_asc38C1600_buf[] = {
5769 0x00, 0x00, 0x00, 0xf2, 0x00, 0x16, 0x00, 0xfc, 0x00, 0x10, 0x00, 0xf0,
5770 0x18, 0xe4, 0x01, 0x00, 0x04, 0x1e, 0x48, 0xe4, 0x03, 0xf6, 0xf7, 0x13,
5771 0x2e, 0x1e, 0x02, 0x00, 0x07, 0x17, 0xc0, 0x5f, 0x00, 0xfa, 0xff, 0xff,
5772 0x04, 0x00, 0x00, 0xf6, 0x09, 0xe7, 0x82, 0xe7, 0x85, 0xf0, 0x86, 0xf0,
5773 0x4e, 0x10, 0x9e, 0xe7, 0xff, 0x00, 0x55, 0xf0, 0x01, 0xf6, 0x03, 0x00,
5774 0x98, 0x57, 0x01, 0xe6, 0x00, 0xea, 0x00, 0xec, 0x01, 0xfa, 0x18, 0xf4,
5775 0x08, 0x00, 0xf0, 0x1d, 0x38, 0x54, 0x32, 0xf0, 0x10, 0x00, 0xc2, 0x0e,
5776 0x1e, 0xf0, 0xd5, 0xf0, 0xbc, 0x00, 0x4b, 0xe4, 0x00, 0xe6, 0xb1, 0xf0,
5777 0xb4, 0x00, 0x02, 0x13, 0x3e, 0x1c, 0xc8, 0x47, 0x3e, 0x00, 0xd8, 0x01,
5778 0x06, 0x13, 0x0c, 0x1c, 0x5e, 0x1e, 0x00, 0x57, 0xc8, 0x57, 0x01, 0xfc,
5779 0xbc, 0x0e, 0xa2, 0x12, 0xb9, 0x54, 0x00, 0x80, 0x62, 0x0a, 0x5a, 0x12,
5780 0xc8, 0x15, 0x3e, 0x1e, 0x18, 0x40, 0xbd, 0x56, 0x03, 0xe6, 0x01, 0xea,
5781 0x5c, 0xf0, 0x0f, 0x00, 0x20, 0x00, 0x6c, 0x01, 0x6e, 0x01, 0x04, 0x12,
5782 0x04, 0x13, 0xbb, 0x55, 0x3c, 0x56, 0x3e, 0x57, 0x03, 0x58, 0x4a, 0xe4,
5783 0x40, 0x00, 0xb6, 0x00, 0xbb, 0x00, 0xc0, 0x00, 0x00, 0x01, 0x01, 0x01,
5784 0x3e, 0x01, 0x58, 0x0a, 0x44, 0x10, 0x0a, 0x12, 0x4c, 0x1c, 0x4e, 0x1c,
5785 0x02, 0x4a, 0x30, 0xe4, 0x05, 0xe6, 0x0c, 0x00, 0x3c, 0x00, 0x80, 0x00,
5786 0x24, 0x01, 0x3c, 0x01, 0x68, 0x01, 0x6a, 0x01, 0x70, 0x01, 0x72, 0x01,
5787 0x74, 0x01, 0x76, 0x01, 0x78, 0x01, 0x7c, 0x01, 0xc6, 0x0e, 0x0c, 0x10,
5788 0xac, 0x12, 0xae, 0x12, 0x16, 0x1a, 0x32, 0x1c, 0x6e, 0x1e, 0x02, 0x48,
5789 0x3a, 0x55, 0xc9, 0x57, 0x02, 0xee, 0x5b, 0xf0, 0x03, 0xf7, 0x06, 0xf7,
5790 0x03, 0xfc, 0x06, 0x00, 0x1e, 0x00, 0xbe, 0x00, 0xe1, 0x00, 0x0c, 0x12,
5791 0x18, 0x1a, 0x70, 0x1a, 0x30, 0x1c, 0x38, 0x1c, 0x10, 0x44, 0x00, 0x4c,
5792 0xb0, 0x57, 0x40, 0x5c, 0x4d, 0xe4, 0x04, 0xea, 0x5d, 0xf0, 0xa7, 0xf0,
5793 0x04, 0xf6, 0x02, 0xfc, 0x05, 0x00, 0x09, 0x00, 0x19, 0x00, 0x32, 0x00,
5794 0x33, 0x00, 0x34, 0x00, 0x36, 0x00, 0x98, 0x00, 0x9e, 0x00, 0xcc, 0x00,
5795 0x20, 0x01, 0x4e, 0x01, 0x79, 0x01, 0x3c, 0x09, 0x68, 0x0d, 0x02, 0x10,
5796 0x04, 0x10, 0x3a, 0x10, 0x08, 0x12, 0x0a, 0x13, 0x40, 0x16, 0x50, 0x16,
5797 0x00, 0x17, 0x4a, 0x19, 0x00, 0x4e, 0x00, 0x54, 0x01, 0x58, 0x00, 0xdc,
5798 0x05, 0xf0, 0x09, 0xf0, 0x59, 0xf0, 0xb8, 0xf0, 0x48, 0xf4, 0x0e, 0xf7,
5799 0x0a, 0x00, 0x9b, 0x00, 0x9c, 0x00, 0xa4, 0x00, 0xb5, 0x00, 0xba, 0x00,
5800 0xd0, 0x00, 0xe7, 0x00, 0xf0, 0x03, 0x69, 0x08, 0xe9, 0x09, 0x5c, 0x0c,
5801 0xb6, 0x12, 0xbc, 0x19, 0xd8, 0x1b, 0x20, 0x1c, 0x34, 0x1c, 0x36, 0x1c,
5802 0x42, 0x1d, 0x08, 0x44, 0x38, 0x44, 0x91, 0x44, 0x0a, 0x45, 0x48, 0x46,
5803 0x89, 0x48, 0x68, 0x54, 0x83, 0x55, 0x83, 0x59, 0x31, 0xe4, 0x02, 0xe6,
5804 0x07, 0xf0, 0x08, 0xf0, 0x0b, 0xf0, 0x0c, 0xf0, 0x4b, 0xf4, 0x04, 0xf8,
5805 0x05, 0xf8, 0x02, 0xfa, 0x03, 0xfa, 0x04, 0xfc, 0x05, 0xfc, 0x07, 0x00,
5806 0xa8, 0x00, 0xaa, 0x00, 0xb9, 0x00, 0xe0, 0x00, 0xe5, 0x00, 0x22, 0x01,
5807 0x26, 0x01, 0x60, 0x01, 0x7a, 0x01, 0x82, 0x01, 0xc8, 0x01, 0xca, 0x01,
5808 0x86, 0x02, 0x6a, 0x03, 0x18, 0x05, 0xb2, 0x07, 0x68, 0x08, 0x10, 0x0d,
5809 0x06, 0x10, 0x0a, 0x10, 0x0e, 0x10, 0x12, 0x10, 0x60, 0x10, 0xed, 0x10,
5810 0xf3, 0x10, 0x06, 0x12, 0x10, 0x12, 0x1e, 0x12, 0x0c, 0x13, 0x0e, 0x13,
5811 0x10, 0x13, 0xfe, 0x9c, 0xf0, 0x35, 0x05, 0xfe, 0xec, 0x0e, 0xff, 0x10,
5812 0x00, 0x00, 0xe9, 0xfe, 0x34, 0x1f, 0x00, 0xe8, 0xfe, 0x88, 0x01, 0xff,
5813 0x03, 0x00, 0x00, 0xfe, 0x93, 0x15, 0xfe, 0x0f, 0x05, 0xff, 0x38, 0x00,
5814 0x00, 0xfe, 0x57, 0x24, 0x00, 0xfe, 0x4c, 0x00, 0x65, 0xff, 0x04, 0x00,
5815 0x00, 0x1a, 0xff, 0x09, 0x00, 0x00, 0xff, 0x08, 0x01, 0x01, 0xff, 0x08,
5816 0xff, 0xff, 0xff, 0x27, 0x00, 0x00, 0xff, 0x10, 0xff, 0xff, 0xff, 0x13,
5817 0x00, 0x00, 0xfe, 0x78, 0x56, 0xfe, 0x34, 0x12, 0xff, 0x21, 0x00, 0x00,
5818 0xfe, 0x04, 0xf7, 0xe8, 0x37, 0x7d, 0x0d, 0x01, 0xfe, 0x4a, 0x11, 0xfe,
5819 0x04, 0xf7, 0xe8, 0x7d, 0x0d, 0x51, 0x37, 0xfe, 0x3d, 0xf0, 0xfe, 0x0c,
5820 0x02, 0xfe, 0x20, 0xf0, 0xbc, 0xfe, 0x91, 0xf0, 0xfe, 0xf8, 0x01, 0xfe,
5821 0x90, 0xf0, 0xfe, 0xf8, 0x01, 0xfe, 0x8f, 0xf0, 0xbc, 0x03, 0x67, 0x4d,
5822 0x05, 0xfe, 0x08, 0x0f, 0x01, 0xfe, 0x78, 0x0f, 0xfe, 0xdd, 0x12, 0x05,
5823 0xfe, 0x0e, 0x03, 0xfe, 0x28, 0x1c, 0x03, 0xfe, 0xa6, 0x00, 0xfe, 0xd1,
5824 0x12, 0x3e, 0x22, 0xfe, 0xa6, 0x00, 0xac, 0xfe, 0x48, 0xf0, 0xfe, 0x90,
5825 0x02, 0xfe, 0x49, 0xf0, 0xfe, 0xaa, 0x02, 0xfe, 0x4a, 0xf0, 0xfe, 0xc8,
5826 0x02, 0xfe, 0x46, 0xf0, 0xfe, 0x5a, 0x02, 0xfe, 0x47, 0xf0, 0xfe, 0x60,
5827 0x02, 0xfe, 0x43, 0xf0, 0xfe, 0x4e, 0x02, 0xfe, 0x44, 0xf0, 0xfe, 0x52,
5828 0x02, 0xfe, 0x45, 0xf0, 0xfe, 0x56, 0x02, 0x1c, 0x0d, 0xa2, 0x1c, 0x07,
5829 0x22, 0xb7, 0x05, 0x35, 0xfe, 0x00, 0x1c, 0xfe, 0xf1, 0x10, 0xfe, 0x02,
5830 0x1c, 0xf5, 0xfe, 0x1e, 0x1c, 0xfe, 0xe9, 0x10, 0x01, 0x5f, 0xfe, 0xe7,
5831 0x10, 0xfe, 0x06, 0xfc, 0xde, 0x0a, 0x81, 0x01, 0xa3, 0x05, 0x35, 0x1f,
5832 0x95, 0x47, 0xb8, 0x01, 0xfe, 0xe4, 0x11, 0x0a, 0x81, 0x01, 0x5c, 0xfe,
5833 0xbd, 0x10, 0x0a, 0x81, 0x01, 0x5c, 0xfe, 0xad, 0x10, 0xfe, 0x16, 0x1c,
5834 0xfe, 0x58, 0x1c, 0x1c, 0x07, 0x22, 0xb7, 0x37, 0x2a, 0x35, 0xfe, 0x3d,
5835 0xf0, 0xfe, 0x0c, 0x02, 0x2b, 0xfe, 0x9e, 0x02, 0xfe, 0x5a, 0x1c, 0xfe,
5836 0x12, 0x1c, 0xfe, 0x14, 0x1c, 0x1f, 0xfe, 0x30, 0x00, 0x47, 0xb8, 0x01,
5837 0xfe, 0xd4, 0x11, 0x1c, 0x07, 0x22, 0xb7, 0x05, 0xe9, 0x21, 0x2c, 0x09,
5838 0x1a, 0x31, 0xfe, 0x69, 0x10, 0x1c, 0x07, 0x22, 0xb7, 0xfe, 0x04, 0xec,
5839 0x2c, 0x60, 0x01, 0xfe, 0x1e, 0x1e, 0x20, 0x2c, 0xfe, 0x05, 0xf6, 0xde,
5840 0x01, 0xfe, 0x62, 0x1b, 0x01, 0x0c, 0x61, 0x4a, 0x44, 0x15, 0x56, 0x51,
5841 0x01, 0xfe, 0x9e, 0x1e, 0x01, 0xfe, 0x96, 0x1a, 0x05, 0x35, 0x0a, 0x57,
5842 0x01, 0x18, 0x09, 0x00, 0x36, 0x01, 0x85, 0xfe, 0x18, 0x10, 0xfe, 0x41,
5843 0x58, 0x0a, 0xba, 0x01, 0x18, 0xfe, 0xc8, 0x54, 0x7b, 0xfe, 0x1c, 0x03,
5844 0x01, 0xfe, 0x96, 0x1a, 0x05, 0x35, 0x37, 0x60, 0xfe, 0x02, 0xe8, 0x30,
5845 0xfe, 0xbf, 0x57, 0xfe, 0x9e, 0x43, 0xfe, 0x77, 0x57, 0xfe, 0x27, 0xf0,
5846 0xfe, 0xe4, 0x01, 0xfe, 0x07, 0x4b, 0xfe, 0x20, 0xf0, 0xbc, 0xfe, 0x40,
5847 0x1c, 0x2a, 0xeb, 0xfe, 0x26, 0xf0, 0xfe, 0x66, 0x03, 0xfe, 0xa0, 0xf0,
5848 0xfe, 0x54, 0x03, 0xfe, 0x11, 0xf0, 0xbc, 0xfe, 0xef, 0x10, 0xfe, 0x9f,
5849 0xf0, 0xfe, 0x74, 0x03, 0xfe, 0x46, 0x1c, 0x19, 0xfe, 0x11, 0x00, 0x05,
5850 0x70, 0x37, 0xfe, 0x48, 0x1c, 0xfe, 0x46, 0x1c, 0x01, 0x0c, 0x06, 0x28,
5851 0xfe, 0x18, 0x13, 0x26, 0x21, 0xb9, 0xc7, 0x20, 0xb9, 0x0a, 0x57, 0x01,
5852 0x18, 0xc7, 0x89, 0x01, 0xfe, 0xc8, 0x1a, 0x15, 0xe1, 0x2a, 0xeb, 0xfe,
5853 0x01, 0xf0, 0xeb, 0xfe, 0x82, 0xf0, 0xfe, 0xa4, 0x03, 0xfe, 0x9c, 0x32,
5854 0x15, 0xfe, 0xe4, 0x00, 0x2f, 0xfe, 0xb6, 0x03, 0x2a, 0x3c, 0x16, 0xfe,
5855 0xc6, 0x03, 0x01, 0x41, 0xfe, 0x06, 0xf0, 0xfe, 0xd6, 0x03, 0xaf, 0xa0,
5856 0xfe, 0x0a, 0xf0, 0xfe, 0xa2, 0x07, 0x05, 0x29, 0x03, 0x81, 0x1e, 0x1b,
5857 0xfe, 0x24, 0x05, 0x1f, 0x63, 0x01, 0x42, 0x8f, 0xfe, 0x70, 0x02, 0x05,
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6154 0x7c, 0x3a, 0x0b, 0x0e, 0xfe, 0x00, 0x71, 0xfe, 0xf9, 0x18, 0xfe, 0x7a,
6155 0x19, 0xfe, 0xfb, 0x19, 0xfe, 0x1a, 0xf7, 0x00, 0xfe, 0x1b, 0xf7, 0x00,
6156 0x7a, 0x30, 0x10, 0x68, 0x22, 0x69, 0xd9, 0x6c, 0xda, 0x6d, 0x02, 0xfe,
6157 0x62, 0x08, 0xfe, 0x82, 0x4a, 0xfe, 0xe1, 0x1a, 0xfe, 0x83, 0x5a, 0x77,
6158 0x02, 0x01, 0xc6, 0xfe, 0x42, 0x48, 0x4f, 0x50, 0x45, 0x01, 0x08, 0x16,
6159 0xfe, 0xe0, 0x17, 0x27, 0x25, 0xbe, 0x01, 0x08, 0x16, 0xfe, 0xe0, 0x17,
6160 0x27, 0x25, 0xfe, 0xe8, 0x0a, 0xfe, 0xc1, 0x59, 0x03, 0x9a, 0x1e, 0xfe,
6161 0xda, 0x12, 0x01, 0x38, 0x06, 0x12, 0xfe, 0xd0, 0x13, 0x26, 0x53, 0x12,
6162 0x48, 0xfe, 0x08, 0x17, 0xd1, 0x12, 0x53, 0x12, 0xfe, 0x1e, 0x13, 0x2d,
6163 0xb4, 0x7b, 0xfe, 0x26, 0x17, 0x4d, 0x13, 0x07, 0x1c, 0xb4, 0x90, 0x04,
6164 0xfe, 0x78, 0x10, 0xff, 0x02, 0x83, 0x55, 0xf1, 0xff, 0x02, 0x83, 0x55,
6165 0x53, 0x1d, 0xfe, 0x12, 0x13, 0xd6, 0xfe, 0x30, 0x00, 0xb0, 0xfe, 0x80,
6166 0x17, 0x1c, 0x63, 0x13, 0x07, 0xfe, 0x56, 0x10, 0x53, 0x0d, 0xfe, 0x16,
6167 0x13, 0xd6, 0xfe, 0x64, 0x00, 0xb0, 0xfe, 0x80, 0x17, 0x0a, 0xfe, 0x64,
6168 0x00, 0x1c, 0x94, 0x13, 0x07, 0xfe, 0x28, 0x10, 0x53, 0x07, 0xfe, 0x60,
6169 0x13, 0xd6, 0xfe, 0xc8, 0x00, 0xb0, 0xfe, 0x80, 0x17, 0x0a, 0xfe, 0xc8,
6170 0x00, 0x1c, 0x95, 0x13, 0x07, 0x71, 0xd6, 0xfe, 0x90, 0x01, 0x48, 0xfe,
6171 0x8c, 0x17, 0x45, 0xf3, 0xfe, 0x43, 0xf4, 0x96, 0xfe, 0x56, 0xf0, 0xfe,
6172 0x9e, 0x17, 0xfe, 0x04, 0xf4, 0x58, 0xfe, 0x43, 0xf4, 0x94, 0xf6, 0x8b,
6173 0x01, 0xfe, 0x24, 0x16, 0x23, 0x3f, 0xfc, 0xa8, 0x8c, 0x49, 0x48, 0xfe,
6174 0xda, 0x17, 0x62, 0x49, 0xfe, 0x1c, 0x10, 0xa8, 0x8c, 0x80, 0x48, 0xfe,
6175 0xda, 0x17, 0x62, 0x80, 0x71, 0x50, 0x26, 0xfe, 0x4d, 0xf4, 0x00, 0xf7,
6176 0x45, 0x13, 0x07, 0xfe, 0xb4, 0x56, 0xfe, 0xc3, 0x58, 0x02, 0x50, 0x13,
6177 0x0d, 0x02, 0x50, 0x3e, 0x78, 0x4f, 0x45, 0x01, 0x08, 0x16, 0xa9, 0x27,
6178 0x25, 0xbe, 0xfe, 0x03, 0xea, 0xfe, 0x7e, 0x01, 0x01, 0x08, 0x16, 0xa9,
6179 0x27, 0x25, 0xfe, 0xe9, 0x0a, 0x01, 0x08, 0x16, 0xa9, 0x27, 0x25, 0xfe,
6180 0xe9, 0x0a, 0xfe, 0x05, 0xea, 0xfe, 0x7f, 0x01, 0x01, 0x08, 0x16, 0xa9,
6181 0x27, 0x25, 0xfe, 0x69, 0x09, 0xfe, 0x02, 0xea, 0xfe, 0x80, 0x01, 0x01,
6182 0x08, 0x16, 0xa9, 0x27, 0x25, 0xfe, 0xe8, 0x08, 0x47, 0xfe, 0x81, 0x01,
6183 0x03, 0xb6, 0x1e, 0x83, 0x01, 0x38, 0x06, 0x24, 0x31, 0xa2, 0x78, 0xf2,
6184 0x53, 0x07, 0x36, 0xfe, 0x34, 0xf4, 0x3f, 0xa1, 0x78, 0x03, 0x9a, 0x1e,
6185 0x83, 0x01, 0x38, 0x06, 0x12, 0x31, 0xf0, 0x4f, 0x45, 0xfe, 0x90, 0x10,
6186 0xfe, 0x40, 0x5a, 0x23, 0x3f, 0xfb, 0x8c, 0x49, 0x48, 0xfe, 0xaa, 0x18,
6187 0x62, 0x49, 0x71, 0x8c, 0x80, 0x48, 0xfe, 0xaa, 0x18, 0x62, 0x80, 0xfe,
6188 0xb4, 0x56, 0xfe, 0x40, 0x5d, 0x01, 0xc6, 0x01, 0xfe, 0xac, 0x1d, 0xfe,
6189 0x02, 0x17, 0xfe, 0xc8, 0x45, 0xfe, 0x5a, 0xf0, 0xfe, 0xc0, 0x18, 0xfe,
6190 0x43, 0x48, 0x2d, 0x93, 0x36, 0xfe, 0x34, 0xf4, 0xfe, 0x00, 0x11, 0xfe,
6191 0x40, 0x10, 0x2d, 0xb4, 0x36, 0xfe, 0x34, 0xf4, 0x04, 0xfe, 0x34, 0x10,
6192 0x2d, 0xfe, 0x0b, 0x00, 0x36, 0x46, 0x63, 0xfe, 0x28, 0x10, 0xfe, 0xc0,
6193 0x49, 0xff, 0x02, 0x00, 0x54, 0xb2, 0xfe, 0x90, 0x01, 0x48, 0xfe, 0xfa,
6194 0x18, 0x45, 0xfe, 0x1c, 0xf4, 0x3f, 0xf3, 0xfe, 0x40, 0xf4, 0x96, 0xfe,
6195 0x56, 0xf0, 0xfe, 0x0c, 0x19, 0xfe, 0x04, 0xf4, 0x58, 0xfe, 0x40, 0xf4,
6196 0x94, 0xf6, 0x3e, 0x2d, 0x93, 0x4e, 0xd0, 0x0d, 0x21, 0xfe, 0x7f, 0x01,
6197 0xfe, 0xc8, 0x46, 0xfe, 0x24, 0x13, 0x8c, 0x00, 0x5d, 0x26, 0x21, 0xfe,
6198 0x7e, 0x01, 0xfe, 0xc8, 0x45, 0xfe, 0x14, 0x13, 0x21, 0xfe, 0x80, 0x01,
6199 0xfe, 0x48, 0x45, 0xfa, 0x21, 0xfe, 0x81, 0x01, 0xfe, 0xc8, 0x44, 0x4e,
6200 0x26, 0x02, 0x13, 0x07, 0x02, 0x78, 0x45, 0x50, 0x13, 0x0d, 0x02, 0x14,
6201 0x07, 0x01, 0x08, 0x17, 0xfe, 0x82, 0x19, 0x14, 0x0d, 0x01, 0x08, 0x17,
6202 0xfe, 0x82, 0x19, 0x14, 0x1d, 0x01, 0x08, 0x17, 0xfe, 0x82, 0x19, 0x5f,
6203 0xfe, 0x89, 0x49, 0x01, 0x08, 0x02, 0x14, 0x07, 0x01, 0x08, 0x17, 0xc1,
6204 0x14, 0x1d, 0x01, 0x08, 0x17, 0xc1, 0x14, 0x07, 0x01, 0x08, 0x17, 0xc1,
6205 0xfe, 0x89, 0x49, 0x01, 0x08, 0x17, 0xc1, 0x5f, 0xfe, 0x89, 0x4a, 0x01,
6206 0x08, 0x02, 0x50, 0x02, 0x14, 0x07, 0x01, 0x08, 0x17, 0x74, 0x14, 0x7f,
6207 0x01, 0x08, 0x17, 0x74, 0x14, 0x12, 0x01, 0x08, 0x17, 0x74, 0xfe, 0x89,
6208 0x49, 0x01, 0x08, 0x17, 0x74, 0x14, 0x00, 0x01, 0x08, 0x17, 0x74, 0xfe,
6209 0x89, 0x4a, 0x01, 0x08, 0x17, 0x74, 0xfe, 0x09, 0x49, 0x01, 0x08, 0x17,
6210 0x74, 0x5f, 0xcc, 0x01, 0x08, 0x02, 0x21, 0xe4, 0x09, 0x07, 0xfe, 0x4c,
6211 0x13, 0xc8, 0x20, 0xe4, 0xfe, 0x49, 0xf4, 0x00, 0x4d, 0x5f, 0xa1, 0x5e,
6212 0xfe, 0x01, 0xec, 0xfe, 0x27, 0x01, 0xcc, 0xff, 0x02, 0x00, 0x10, 0x2f,
6213 0xfe, 0x3e, 0x1a, 0x01, 0x43, 0x09, 0xfe, 0xe3, 0x00, 0xfe, 0x22, 0x13,
6214 0x16, 0xfe, 0x64, 0x1a, 0x26, 0x20, 0x9e, 0x01, 0x41, 0x21, 0x9e, 0x09,
6215 0x07, 0x5d, 0x01, 0x0c, 0x61, 0x07, 0x44, 0x02, 0x0a, 0x5a, 0x01, 0x18,
6216 0xfe, 0x00, 0x40, 0xaa, 0x09, 0x1a, 0xfe, 0x12, 0x13, 0x0a, 0x9d, 0x01,
6217 0x18, 0xaa, 0x0a, 0x67, 0x01, 0xa3, 0x02, 0x0a, 0x9d, 0x01, 0x18, 0xaa,
6218 0xfe, 0x80, 0xe7, 0x1a, 0x09, 0x1a, 0x5d, 0xfe, 0x45, 0x58, 0x01, 0xfe,
6219 0xb2, 0x16, 0xaa, 0x02, 0x0a, 0x5a, 0x01, 0x18, 0xaa, 0x0a, 0x67, 0x01,
6220 0xa3, 0x02, 0x0a, 0x5a, 0x01, 0x18, 0x01, 0xfe, 0x7e, 0x1e, 0xfe, 0x80,
6221 0x4c, 0xfe, 0x49, 0xe4, 0x1a, 0xfe, 0x12, 0x13, 0x0a, 0x9d, 0x01, 0x18,
6222 0xfe, 0x80, 0x4c, 0x0a, 0x67, 0x01, 0x5c, 0x02, 0x1c, 0x1a, 0x87, 0x7c,
6223 0xe5, 0xfe, 0x18, 0xdf, 0xfe, 0x19, 0xde, 0xfe, 0x24, 0x1c, 0xfe, 0x1d,
6224 0xf7, 0x28, 0xb1, 0xfe, 0x04, 0x1b, 0x01, 0xfe, 0x2a, 0x1c, 0xfa, 0xb3,
6225 0x28, 0x7c, 0xfe, 0x2c, 0x01, 0xfe, 0x2f, 0x19, 0x02, 0xc9, 0x2b, 0xfe,
6226 0xf4, 0x1a, 0xfe, 0xfa, 0x10, 0x1c, 0x1a, 0x87, 0x03, 0xfe, 0x64, 0x01,
6227 0xfe, 0x00, 0xf4, 0x24, 0xfe, 0x18, 0x58, 0x03, 0xfe, 0x66, 0x01, 0xfe,
6228 0x19, 0x58, 0xb3, 0x24, 0x01, 0xfe, 0x0e, 0x1f, 0xfe, 0x30, 0xf4, 0x07,
6229 0xfe, 0x3c, 0x50, 0x7c, 0xfe, 0x38, 0x00, 0xfe, 0x0f, 0x79, 0xfe, 0x1c,
6230 0xf7, 0x24, 0xb1, 0xfe, 0x50, 0x1b, 0xfe, 0xd4, 0x14, 0x31, 0x02, 0xc9,
6231 0x2b, 0xfe, 0x26, 0x1b, 0xfe, 0xba, 0x10, 0x1c, 0x1a, 0x87, 0xfe, 0x83,
6232 0x5a, 0xfe, 0x18, 0xdf, 0xfe, 0x19, 0xde, 0xfe, 0x1d, 0xf7, 0x54, 0xb1,
6233 0xfe, 0x72, 0x1b, 0xfe, 0xb2, 0x14, 0xfc, 0xb3, 0x54, 0x7c, 0x12, 0xfe,
6234 0xaf, 0x19, 0xfe, 0x98, 0xe7, 0x00, 0x02, 0xc9, 0x2b, 0xfe, 0x66, 0x1b,
6235 0xfe, 0x8a, 0x10, 0x1c, 0x1a, 0x87, 0x8b, 0x0f, 0xfe, 0x30, 0x90, 0x04,
6236 0xfe, 0xb0, 0x93, 0x3a, 0x0b, 0xfe, 0x18, 0x58, 0xfe, 0x32, 0x90, 0x04,
6237 0xfe, 0xb2, 0x93, 0x3a, 0x0b, 0xfe, 0x19, 0x58, 0x0e, 0xa8, 0xb3, 0x4a,
6238 0x7c, 0x12, 0xfe, 0x0f, 0x79, 0xfe, 0x1c, 0xf7, 0x4a, 0xb1, 0xfe, 0xc6,
6239 0x1b, 0xfe, 0x5e, 0x14, 0x31, 0x02, 0xc9, 0x2b, 0xfe, 0x96, 0x1b, 0x5c,
6240 0xfe, 0x02, 0xf6, 0x1a, 0x87, 0xfe, 0x18, 0xfe, 0x6a, 0xfe, 0x19, 0xfe,
6241 0x6b, 0x01, 0xfe, 0x1e, 0x1f, 0xfe, 0x1d, 0xf7, 0x65, 0xb1, 0xfe, 0xee,
6242 0x1b, 0xfe, 0x36, 0x14, 0xfe, 0x1c, 0x13, 0xb3, 0x65, 0x3e, 0xfe, 0x83,
6243 0x58, 0xfe, 0xaf, 0x19, 0xfe, 0x80, 0xe7, 0x1a, 0xfe, 0x81, 0xe7, 0x1a,
6244 0x15, 0xfe, 0xdd, 0x00, 0x7a, 0x30, 0x02, 0x7a, 0x30, 0xfe, 0x12, 0x45,
6245 0x2b, 0xfe, 0xdc, 0x1b, 0x1f, 0x07, 0x47, 0xb5, 0xc3, 0x05, 0x35, 0xfe,
6246 0x39, 0xf0, 0x75, 0x26, 0x02, 0xfe, 0x7e, 0x18, 0x23, 0x1d, 0x36, 0x13,
6247 0x11, 0x02, 0x87, 0x03, 0xe3, 0x23, 0x07, 0xfe, 0xef, 0x12, 0xfe, 0xe1,
6248 0x10, 0x90, 0x34, 0x60, 0xfe, 0x02, 0x80, 0x09, 0x56, 0xfe, 0x3c, 0x13,
6249 0xfe, 0x82, 0x14, 0xfe, 0x42, 0x13, 0x51, 0xfe, 0x06, 0x83, 0x0a, 0x5a,
6250 0x01, 0x18, 0xcb, 0xfe, 0x3e, 0x12, 0xfe, 0x41, 0x48, 0xfe, 0x45, 0x48,
6251 0x01, 0xfe, 0xb2, 0x16, 0xfe, 0x00, 0xcc, 0xcb, 0xfe, 0xf3, 0x13, 0x3f,
6252 0x89, 0x09, 0x1a, 0xa5, 0x0a, 0x9d, 0x01, 0x18, 0xfe, 0x80, 0x4c, 0x01,
6253 0x85, 0xfe, 0x16, 0x10, 0x09, 0x9b, 0x4e, 0xfe, 0x40, 0x14, 0xfe, 0x24,
6254 0x12, 0xfe, 0x14, 0x56, 0xfe, 0xd6, 0xf0, 0xfe, 0x52, 0x1c, 0x1c, 0x0d,
6255 0x02, 0xfe, 0x9c, 0xe7, 0x0d, 0x19, 0xfe, 0x15, 0x00, 0x40, 0x8d, 0x30,
6256 0x01, 0xf4, 0x1c, 0x07, 0x02, 0x51, 0xfe, 0x06, 0x83, 0xfe, 0x18, 0x80,
6257 0x61, 0x28, 0x44, 0x15, 0x56, 0x01, 0x85, 0x1c, 0x07, 0x02, 0xfe, 0x38,
6258 0x90, 0xfe, 0xba, 0x90, 0x91, 0xde, 0x7e, 0xdf, 0xfe, 0x48, 0x55, 0x31,
6259 0xfe, 0xc9, 0x55, 0x02, 0x21, 0xb9, 0x88, 0x20, 0xb9, 0x02, 0x0a, 0xba,
6260 0x01, 0x18, 0xfe, 0x41, 0x48, 0x0a, 0x57, 0x01, 0x18, 0xfe, 0x49, 0x44,
6261 0x1b, 0xfe, 0x1e, 0x1d, 0x88, 0x89, 0x02, 0x0a, 0x5a, 0x01, 0x18, 0x09,
6262 0x1a, 0xa4, 0x0a, 0x67, 0x01, 0xa3, 0x0a, 0x57, 0x01, 0x18, 0x88, 0x89,
6263 0x02, 0xfe, 0x4e, 0xe4, 0x1d, 0x7b, 0xfe, 0x52, 0x1d, 0x03, 0xfe, 0x90,
6264 0x00, 0xfe, 0x3a, 0x45, 0xfe, 0x2c, 0x10, 0xfe, 0x4e, 0xe4, 0xdd, 0x7b,
6265 0xfe, 0x64, 0x1d, 0x03, 0xfe, 0x92, 0x00, 0xd1, 0x12, 0xfe, 0x1a, 0x10,
6266 0xfe, 0x4e, 0xe4, 0xfe, 0x0b, 0x00, 0x7b, 0xfe, 0x76, 0x1d, 0x03, 0xfe,
6267 0x94, 0x00, 0xd1, 0x24, 0xfe, 0x08, 0x10, 0x03, 0xfe, 0x96, 0x00, 0xd1,
6268 0x63, 0xfe, 0x4e, 0x45, 0x83, 0xca, 0xff, 0x04, 0x68, 0x54, 0xfe, 0xf1,
6269 0x10, 0x23, 0x49, 0xfe, 0x08, 0x1c, 0xfe, 0x67, 0x19, 0xfe, 0x0a, 0x1c,
6270 0xfe, 0x1a, 0xf4, 0xfe, 0x00, 0x04, 0x83, 0xb2, 0x1d, 0x48, 0xfe, 0xaa,
6271 0x1d, 0x13, 0x1d, 0x02, 0x09, 0x92, 0xfe, 0x5a, 0xf0, 0xfe, 0xba, 0x1d,
6272 0x2e, 0x93, 0xfe, 0x34, 0x10, 0x09, 0x12, 0xfe, 0x5a, 0xf0, 0xfe, 0xc8,
6273 0x1d, 0x2e, 0xb4, 0xfe, 0x26, 0x10, 0x09, 0x1d, 0x36, 0x2e, 0x63, 0xfe,
6274 0x1a, 0x10, 0x09, 0x0d, 0x36, 0x2e, 0x94, 0xf2, 0x09, 0x07, 0x36, 0x2e,
6275 0x95, 0xa1, 0xc8, 0x02, 0x1f, 0x93, 0x01, 0x42, 0xfe, 0x04, 0xfe, 0x99,
6276 0x03, 0x9c, 0x8b, 0x02, 0x2a, 0xfe, 0x1c, 0x1e, 0xfe, 0x14, 0xf0, 0x08,
6277 0x2f, 0xfe, 0x0c, 0x1e, 0x2a, 0xfe, 0x1c, 0x1e, 0x8f, 0xfe, 0x1c, 0x1e,
6278 0xfe, 0x82, 0xf0, 0xfe, 0x10, 0x1e, 0x02, 0x0f, 0x3f, 0x04, 0xfe, 0x80,
6279 0x83, 0x33, 0x0b, 0x0e, 0x02, 0x0f, 0xfe, 0x18, 0x80, 0x04, 0xfe, 0x98,
6280 0x83, 0x33, 0x0b, 0x0e, 0x02, 0x0f, 0xfe, 0x02, 0x80, 0x04, 0xfe, 0x82,
6281 0x83, 0x33, 0x0b, 0x0e, 0x02, 0x0f, 0xfe, 0x06, 0x80, 0x04, 0xfe, 0x86,
6282 0x83, 0x33, 0x0b, 0x0e, 0x02, 0x0f, 0xfe, 0x1b, 0x80, 0x04, 0xfe, 0x9b,
6283 0x83, 0x33, 0x0b, 0x0e, 0x02, 0x0f, 0xfe, 0x04, 0x80, 0x04, 0xfe, 0x84,
6284 0x83, 0x33, 0x0b, 0x0e, 0x02, 0x0f, 0xfe, 0x80, 0x80, 0x04, 0xfe, 0x80,
6285 0x83, 0xfe, 0xc9, 0x47, 0x0b, 0x0e, 0x02, 0x0f, 0xfe, 0x19, 0x81, 0x04,
6286 0xfe, 0x99, 0x83, 0xfe, 0xca, 0x47, 0x0b, 0x0e, 0x02, 0x0f, 0xfe, 0x06,
6287 0x83, 0x04, 0xfe, 0x86, 0x83, 0xfe, 0xce, 0x47, 0x0b, 0x0e, 0x02, 0x0f,
6288 0xfe, 0x2c, 0x90, 0x04, 0xfe, 0xac, 0x93, 0x3a, 0x0b, 0x0e, 0x02, 0x0f,
6289 0xfe, 0xae, 0x90, 0x04, 0xfe, 0xae, 0x93, 0x79, 0x0b, 0x0e, 0x02, 0x0f,
6290 0xfe, 0x08, 0x90, 0x04, 0xfe, 0x88, 0x93, 0x3a, 0x0b, 0x0e, 0x02, 0x0f,
6291 0xfe, 0x8a, 0x90, 0x04, 0xfe, 0x8a, 0x93, 0x79, 0x0b, 0x0e, 0x02, 0x0f,
6292 0xfe, 0x0c, 0x90, 0x04, 0xfe, 0x8c, 0x93, 0x3a, 0x0b, 0x0e, 0x02, 0x0f,
6293 0xfe, 0x8e, 0x90, 0x04, 0xfe, 0x8e, 0x93, 0x79, 0x0b, 0x0e, 0x02, 0x0f,
6294 0xfe, 0x3c, 0x90, 0x04, 0xfe, 0xbc, 0x93, 0x3a, 0x0b, 0x0e, 0x02, 0x8b,
6295 0x0f, 0xfe, 0x03, 0x80, 0x04, 0xfe, 0x83, 0x83, 0x33, 0x0b, 0x77, 0x0e,
6296 0xa8, 0x02, 0xff, 0x66, 0x00, 0x00,
6299 static unsigned short _adv_asc38C1600_size = sizeof(_adv_asc38C1600_buf); /* 0x1673 */
6300 static ADV_DCNT _adv_asc38C1600_chksum = 0x0604EF77UL; /* Expanded little-endian checksum. */
6302 static void AscInitQLinkVar(ASC_DVC_VAR *asc_dvc)
6308 iop_base = asc_dvc->iop_base;
6309 AscPutRiscVarFreeQHead(iop_base, 1);
6310 AscPutRiscVarDoneQTail(iop_base, asc_dvc->max_total_qng);
6311 AscPutVarFreeQHead(iop_base, 1);
6312 AscPutVarDoneQTail(iop_base, asc_dvc->max_total_qng);
6313 AscWriteLramByte(iop_base, ASCV_BUSY_QHEAD_B,
6314 (uchar)((int)asc_dvc->max_total_qng + 1));
6315 AscWriteLramByte(iop_base, ASCV_DISC1_QHEAD_B,
6316 (uchar)((int)asc_dvc->max_total_qng + 2));
6317 AscWriteLramByte(iop_base, (ushort)ASCV_TOTAL_READY_Q_B,
6318 asc_dvc->max_total_qng);
6319 AscWriteLramWord(iop_base, ASCV_ASCDVC_ERR_CODE_W, 0);
6320 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
6321 AscWriteLramByte(iop_base, ASCV_STOP_CODE_B, 0);
6322 AscWriteLramByte(iop_base, ASCV_SCSIBUSY_B, 0);
6323 AscWriteLramByte(iop_base, ASCV_WTM_FLAG_B, 0);
6324 AscPutQDoneInProgress(iop_base, 0);
6325 lram_addr = ASC_QADR_BEG;
6326 for (i = 0; i < 32; i++, lram_addr += 2) {
6327 AscWriteLramWord(iop_base, lram_addr, 0);
6331 static ushort AscInitMicroCodeVar(ASC_DVC_VAR *asc_dvc)
6339 iop_base = asc_dvc->iop_base;
6341 for (i = 0; i <= ASC_MAX_TID; i++) {
6342 AscPutMCodeInitSDTRAtID(iop_base, i,
6343 asc_dvc->cfg->sdtr_period_offset[i]);
6346 AscInitQLinkVar(asc_dvc);
6347 AscWriteLramByte(iop_base, ASCV_DISC_ENABLE_B,
6348 asc_dvc->cfg->disc_enable);
6349 AscWriteLramByte(iop_base, ASCV_HOSTSCSI_ID_B,
6350 ASC_TID_TO_TARGET_ID(asc_dvc->cfg->chip_scsi_id));
6352 /* Align overrun buffer on an 8 byte boundary. */
6353 phy_addr = virt_to_bus(asc_dvc->cfg->overrun_buf);
6354 phy_addr = cpu_to_le32((phy_addr + 7) & ~0x7);
6355 AscMemDWordCopyPtrToLram(iop_base, ASCV_OVERRUN_PADDR_D,
6356 (uchar *)&phy_addr, 1);
6357 phy_size = cpu_to_le32(ASC_OVERRUN_BSIZE - 8);
6358 AscMemDWordCopyPtrToLram(iop_base, ASCV_OVERRUN_BSIZE_D,
6359 (uchar *)&phy_size, 1);
6361 asc_dvc->cfg->mcode_date =
6362 AscReadLramWord(iop_base, (ushort)ASCV_MC_DATE_W);
6363 asc_dvc->cfg->mcode_version =
6364 AscReadLramWord(iop_base, (ushort)ASCV_MC_VER_W);
6366 AscSetPCAddr(iop_base, ASC_MCODE_START_ADDR);
6367 if (AscGetPCAddr(iop_base) != ASC_MCODE_START_ADDR) {
6368 asc_dvc->err_code |= ASC_IERR_SET_PC_ADDR;
6371 if (AscStartChip(iop_base) != 1) {
6372 asc_dvc->err_code |= ASC_IERR_START_STOP_CHIP;
6379 static ushort AscInitAsc1000Driver(ASC_DVC_VAR *asc_dvc)
6384 iop_base = asc_dvc->iop_base;
6386 if ((asc_dvc->dvc_cntl & ASC_CNTL_RESET_SCSI) &&
6387 !(asc_dvc->init_state & ASC_INIT_RESET_SCSI_DONE)) {
6388 AscResetChipAndScsiBus(asc_dvc);
6389 mdelay(asc_dvc->scsi_reset_wait * 1000); /* XXX: msleep? */
6391 asc_dvc->init_state |= ASC_INIT_STATE_BEG_LOAD_MC;
6392 if (asc_dvc->err_code != 0)
6394 if (!AscFindSignature(asc_dvc->iop_base)) {
6395 asc_dvc->err_code = ASC_IERR_BAD_SIGNATURE;
6398 AscDisableInterrupt(iop_base);
6399 warn_code |= AscInitLram(asc_dvc);
6400 if (asc_dvc->err_code != 0)
6402 ASC_DBG(1, "_asc_mcode_chksum 0x%lx\n", (ulong)_asc_mcode_chksum);
6403 if (AscLoadMicroCode(iop_base, 0, _asc_mcode_buf,
6404 _asc_mcode_size) != _asc_mcode_chksum) {
6405 asc_dvc->err_code |= ASC_IERR_MCODE_CHKSUM;
6408 warn_code |= AscInitMicroCodeVar(asc_dvc);
6409 asc_dvc->init_state |= ASC_INIT_STATE_END_LOAD_MC;
6410 AscEnableInterrupt(iop_base);
6415 * Load the Microcode
6417 * Write the microcode image to RISC memory starting at address 0.
6419 * The microcode is stored compressed in the following format:
6421 * 254 word (508 byte) table indexed by byte code followed
6422 * by the following byte codes:
6425 * 00: Emit word 0 in table.
6426 * 01: Emit word 1 in table.
6428 * FD: Emit word 253 in table.
6431 * FE WW WW: (3 byte code) Word to emit is the next word WW WW.
6432 * FF BB WW WW: (4 byte code) Emit BB count times next word WW WW.
6434 * Returns 0 or an error if the checksum doesn't match
6436 static int AdvLoadMicrocode(AdvPortAddr iop_base, unsigned char *buf, int size,
6437 int memsize, int chksum)
6439 int i, j, end, len = 0;
6442 AdvWriteWordRegister(iop_base, IOPW_RAM_ADDR, 0);
6444 for (i = 253 * 2; i < size; i++) {
6445 if (buf[i] == 0xff) {
6446 unsigned short word = (buf[i + 3] << 8) | buf[i + 2];
6447 for (j = 0; j < buf[i + 1]; j++) {
6448 AdvWriteWordAutoIncLram(iop_base, word);
6452 } else if (buf[i] == 0xfe) {
6453 unsigned short word = (buf[i + 2] << 8) | buf[i + 1];
6454 AdvWriteWordAutoIncLram(iop_base, word);
6458 unsigned char off = buf[i] * 2;
6459 unsigned short word = (buf[off + 1] << 8) | buf[off];
6460 AdvWriteWordAutoIncLram(iop_base, word);
6467 while (len < memsize) {
6468 AdvWriteWordAutoIncLram(iop_base, 0);
6472 /* Verify the microcode checksum. */
6474 AdvWriteWordRegister(iop_base, IOPW_RAM_ADDR, 0);
6476 for (len = 0; len < end; len += 2) {
6477 sum += AdvReadWordAutoIncLram(iop_base);
6481 return ASC_IERR_MCODE_CHKSUM;
6489 * Return the physical address of 'vaddr' and set '*lenp' to the
6490 * number of physically contiguous bytes that follow 'vaddr'.
6491 * 'flag' indicates the type of structure whose physical address
6492 * is being translated.
6494 * Note: Because Linux currently doesn't page the kernel and all
6495 * kernel buffers are physically contiguous, leave '*lenp' unchanged.
6498 DvcGetPhyAddr(ADV_DVC_VAR *asc_dvc, ADV_SCSI_REQ_Q *scsiq,
6499 uchar *vaddr, ADV_SDCNT *lenp, int flag)
6501 ADV_PADDR paddr = virt_to_bus(vaddr);
6503 ASC_DBG(4, "vaddr 0x%p, lenp 0x%p *lenp %lu, paddr 0x%lx\n",
6504 vaddr, lenp, (ulong)*((ulong *)lenp), (ulong)paddr);
6509 static void AdvBuildCarrierFreelist(struct adv_dvc_var *asc_dvc)
6513 ADV_PADDR carr_paddr;
6515 carrp = (ADV_CARR_T *) ADV_16BALIGN(asc_dvc->carrier_buf);
6516 asc_dvc->carr_freelist = NULL;
6517 if (carrp == asc_dvc->carrier_buf) {
6518 buf_size = ADV_CARRIER_BUFSIZE;
6520 buf_size = ADV_CARRIER_BUFSIZE - sizeof(ADV_CARR_T);
6524 /* Get physical address of the carrier 'carrp'. */
6525 ADV_DCNT contig_len = sizeof(ADV_CARR_T);
6526 carr_paddr = cpu_to_le32(DvcGetPhyAddr(asc_dvc, NULL,
6528 (ADV_SDCNT *)&contig_len,
6529 ADV_IS_CARRIER_FLAG));
6531 buf_size -= sizeof(ADV_CARR_T);
6534 * If the current carrier is not physically contiguous, then
6535 * maybe there was a page crossing. Try the next carrier
6536 * aligned start address.
6538 if (contig_len < sizeof(ADV_CARR_T)) {
6543 carrp->carr_pa = carr_paddr;
6544 carrp->carr_va = cpu_to_le32(ADV_VADDR_TO_U32(carrp));
6547 * Insert the carrier at the beginning of the freelist.
6550 cpu_to_le32(ADV_VADDR_TO_U32(asc_dvc->carr_freelist));
6551 asc_dvc->carr_freelist = carrp;
6554 } while (buf_size > 0);
6558 * Send an idle command to the chip and wait for completion.
6560 * Command completion is polled for once per microsecond.
6562 * The function can be called from anywhere including an interrupt handler.
6563 * But the function is not re-entrant, so it uses the DvcEnter/LeaveCritical()
6564 * functions to prevent reentrancy.
6567 * ADV_TRUE - command completed successfully
6568 * ADV_FALSE - command failed
6569 * ADV_ERROR - command timed out
6572 AdvSendIdleCmd(ADV_DVC_VAR *asc_dvc,
6573 ushort idle_cmd, ADV_DCNT idle_cmd_parameter)
6577 AdvPortAddr iop_base;
6579 iop_base = asc_dvc->iop_base;
6582 * Clear the idle command status which is set by the microcode
6583 * to a non-zero value to indicate when the command is completed.
6584 * The non-zero result is one of the IDLE_CMD_STATUS_* values
6586 AdvWriteWordLram(iop_base, ASC_MC_IDLE_CMD_STATUS, (ushort)0);
6589 * Write the idle command value after the idle command parameter
6590 * has been written to avoid a race condition. If the order is not
6591 * followed, the microcode may process the idle command before the
6592 * parameters have been written to LRAM.
6594 AdvWriteDWordLramNoSwap(iop_base, ASC_MC_IDLE_CMD_PARAMETER,
6595 cpu_to_le32(idle_cmd_parameter));
6596 AdvWriteWordLram(iop_base, ASC_MC_IDLE_CMD, idle_cmd);
6599 * Tickle the RISC to tell it to process the idle command.
6601 AdvWriteByteRegister(iop_base, IOPB_TICKLE, ADV_TICKLE_B);
6602 if (asc_dvc->chip_type == ADV_CHIP_ASC3550) {
6604 * Clear the tickle value. In the ASC-3550 the RISC flag
6605 * command 'clr_tickle_b' does not work unless the host
6608 AdvWriteByteRegister(iop_base, IOPB_TICKLE, ADV_TICKLE_NOP);
6611 /* Wait for up to 100 millisecond for the idle command to timeout. */
6612 for (i = 0; i < SCSI_WAIT_100_MSEC; i++) {
6613 /* Poll once each microsecond for command completion. */
6614 for (j = 0; j < SCSI_US_PER_MSEC; j++) {
6615 AdvReadWordLram(iop_base, ASC_MC_IDLE_CMD_STATUS,
6623 BUG(); /* The idle command should never timeout. */
6628 * Reset SCSI Bus and purge all outstanding requests.
6631 * ADV_TRUE(1) - All requests are purged and SCSI Bus is reset.
6632 * ADV_FALSE(0) - Microcode command failed.
6633 * ADV_ERROR(-1) - Microcode command timed-out. Microcode or IC
6634 * may be hung which requires driver recovery.
6636 static int AdvResetSB(ADV_DVC_VAR *asc_dvc)
6641 * Send the SCSI Bus Reset idle start idle command which asserts
6642 * the SCSI Bus Reset signal.
6644 status = AdvSendIdleCmd(asc_dvc, (ushort)IDLE_CMD_SCSI_RESET_START, 0L);
6645 if (status != ADV_TRUE) {
6650 * Delay for the specified SCSI Bus Reset hold time.
6652 * The hold time delay is done on the host because the RISC has no
6653 * microsecond accurate timer.
6655 udelay(ASC_SCSI_RESET_HOLD_TIME_US);
6658 * Send the SCSI Bus Reset end idle command which de-asserts
6659 * the SCSI Bus Reset signal and purges any pending requests.
6661 status = AdvSendIdleCmd(asc_dvc, (ushort)IDLE_CMD_SCSI_RESET_END, 0L);
6662 if (status != ADV_TRUE) {
6666 mdelay(asc_dvc->scsi_reset_wait * 1000); /* XXX: msleep? */
6672 * Initialize the ASC-3550.
6674 * On failure set the ADV_DVC_VAR field 'err_code' and return ADV_ERROR.
6676 * For a non-fatal error return a warning code. If there are no warnings
6677 * then 0 is returned.
6679 * Needed after initialization for error recovery.
6681 static int AdvInitAsc3550Driver(ADV_DVC_VAR *asc_dvc)
6683 AdvPortAddr iop_base;
6692 ushort bios_mem[ASC_MC_BIOSLEN / 2]; /* BIOS RISC Memory 0x40-0x8F. */
6693 ushort wdtr_able = 0, sdtr_able, tagqng_able;
6694 uchar max_cmd[ADV_MAX_TID + 1];
6696 /* If there is already an error, don't continue. */
6697 if (asc_dvc->err_code != 0)
6701 * The caller must set 'chip_type' to ADV_CHIP_ASC3550.
6703 if (asc_dvc->chip_type != ADV_CHIP_ASC3550) {
6704 asc_dvc->err_code = ASC_IERR_BAD_CHIPTYPE;
6709 iop_base = asc_dvc->iop_base;
6712 * Save the RISC memory BIOS region before writing the microcode.
6713 * The BIOS may already be loaded and using its RISC LRAM region
6714 * so its region must be saved and restored.
6716 * Note: This code makes the assumption, which is currently true,
6717 * that a chip reset does not clear RISC LRAM.
6719 for (i = 0; i < ASC_MC_BIOSLEN / 2; i++) {
6720 AdvReadWordLram(iop_base, ASC_MC_BIOSMEM + (2 * i),
6725 * Save current per TID negotiated values.
6727 if (bios_mem[(ASC_MC_BIOS_SIGNATURE - ASC_MC_BIOSMEM) / 2] == 0x55AA) {
6728 ushort bios_version, major, minor;
6731 bios_mem[(ASC_MC_BIOS_VERSION - ASC_MC_BIOSMEM) / 2];
6732 major = (bios_version >> 12) & 0xF;
6733 minor = (bios_version >> 8) & 0xF;
6734 if (major < 3 || (major == 3 && minor == 1)) {
6735 /* BIOS 3.1 and earlier location of 'wdtr_able' variable. */
6736 AdvReadWordLram(iop_base, 0x120, wdtr_able);
6738 AdvReadWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able);
6741 AdvReadWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
6742 AdvReadWordLram(iop_base, ASC_MC_TAGQNG_ABLE, tagqng_able);
6743 for (tid = 0; tid <= ADV_MAX_TID; tid++) {
6744 AdvReadByteLram(iop_base, ASC_MC_NUMBER_OF_MAX_CMD + tid,
6748 asc_dvc->err_code = AdvLoadMicrocode(iop_base, _adv_asc3550_buf,
6749 _adv_asc3550_size, ADV_3550_MEMSIZE,
6750 _adv_asc3550_chksum);
6751 if (asc_dvc->err_code)
6755 * Restore the RISC memory BIOS region.
6757 for (i = 0; i < ASC_MC_BIOSLEN / 2; i++) {
6758 AdvWriteWordLram(iop_base, ASC_MC_BIOSMEM + (2 * i),
6763 * Calculate and write the microcode code checksum to the microcode
6764 * code checksum location ASC_MC_CODE_CHK_SUM (0x2C).
6766 AdvReadWordLram(iop_base, ASC_MC_CODE_BEGIN_ADDR, begin_addr);
6767 AdvReadWordLram(iop_base, ASC_MC_CODE_END_ADDR, end_addr);
6769 AdvWriteWordRegister(iop_base, IOPW_RAM_ADDR, begin_addr);
6770 for (word = begin_addr; word < end_addr; word += 2) {
6771 code_sum += AdvReadWordAutoIncLram(iop_base);
6773 AdvWriteWordLram(iop_base, ASC_MC_CODE_CHK_SUM, code_sum);
6776 * Read and save microcode version and date.
6778 AdvReadWordLram(iop_base, ASC_MC_VERSION_DATE,
6779 asc_dvc->cfg->mcode_date);
6780 AdvReadWordLram(iop_base, ASC_MC_VERSION_NUM,
6781 asc_dvc->cfg->mcode_version);
6784 * Set the chip type to indicate the ASC3550.
6786 AdvWriteWordLram(iop_base, ASC_MC_CHIP_TYPE, ADV_CHIP_ASC3550);
6789 * If the PCI Configuration Command Register "Parity Error Response
6790 * Control" Bit was clear (0), then set the microcode variable
6791 * 'control_flag' CONTROL_FLAG_IGNORE_PERR flag to tell the microcode
6792 * to ignore DMA parity errors.
6794 if (asc_dvc->cfg->control_flag & CONTROL_FLAG_IGNORE_PERR) {
6795 AdvReadWordLram(iop_base, ASC_MC_CONTROL_FLAG, word);
6796 word |= CONTROL_FLAG_IGNORE_PERR;
6797 AdvWriteWordLram(iop_base, ASC_MC_CONTROL_FLAG, word);
6801 * For ASC-3550, setting the START_CTL_EMFU [3:2] bits sets a FIFO
6802 * threshold of 128 bytes. This register is only accessible to the host.
6804 AdvWriteByteRegister(iop_base, IOPB_DMA_CFG0,
6805 START_CTL_EMFU | READ_CMD_MRM);
6808 * Microcode operating variables for WDTR, SDTR, and command tag
6809 * queuing will be set in slave_configure() based on what a
6810 * device reports it is capable of in Inquiry byte 7.
6812 * If SCSI Bus Resets have been disabled, then directly set
6813 * SDTR and WDTR from the EEPROM configuration. This will allow
6814 * the BIOS and warm boot to work without a SCSI bus hang on
6815 * the Inquiry caused by host and target mismatched DTR values.
6816 * Without the SCSI Bus Reset, before an Inquiry a device can't
6817 * be assumed to be in Asynchronous, Narrow mode.
6819 if ((asc_dvc->bios_ctrl & BIOS_CTRL_RESET_SCSI_BUS) == 0) {
6820 AdvWriteWordLram(iop_base, ASC_MC_WDTR_ABLE,
6821 asc_dvc->wdtr_able);
6822 AdvWriteWordLram(iop_base, ASC_MC_SDTR_ABLE,
6823 asc_dvc->sdtr_able);
6827 * Set microcode operating variables for SDTR_SPEED1, SDTR_SPEED2,
6828 * SDTR_SPEED3, and SDTR_SPEED4 based on the ULTRA EEPROM per TID
6829 * bitmask. These values determine the maximum SDTR speed negotiated
6832 * The SDTR per TID bitmask overrides the SDTR_SPEED1, SDTR_SPEED2,
6833 * SDTR_SPEED3, and SDTR_SPEED4 values so it is safe to set them
6834 * without determining here whether the device supports SDTR.
6836 * 4-bit speed SDTR speed name
6837 * =========== ===============
6838 * 0000b (0x0) SDTR disabled
6840 * 0010b (0x2) 10 Mhz
6841 * 0011b (0x3) 20 Mhz (Ultra)
6842 * 0100b (0x4) 40 Mhz (LVD/Ultra2)
6843 * 0101b (0x5) 80 Mhz (LVD2/Ultra3)
6844 * 0110b (0x6) Undefined
6846 * 1111b (0xF) Undefined
6849 for (tid = 0; tid <= ADV_MAX_TID; tid++) {
6850 if (ADV_TID_TO_TIDMASK(tid) & asc_dvc->ultra_able) {
6851 /* Set Ultra speed for TID 'tid'. */
6852 word |= (0x3 << (4 * (tid % 4)));
6854 /* Set Fast speed for TID 'tid'. */
6855 word |= (0x2 << (4 * (tid % 4)));
6857 if (tid == 3) { /* Check if done with sdtr_speed1. */
6858 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED1, word);
6860 } else if (tid == 7) { /* Check if done with sdtr_speed2. */
6861 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED2, word);
6863 } else if (tid == 11) { /* Check if done with sdtr_speed3. */
6864 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED3, word);
6866 } else if (tid == 15) { /* Check if done with sdtr_speed4. */
6867 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED4, word);
6873 * Set microcode operating variable for the disconnect per TID bitmask.
6875 AdvWriteWordLram(iop_base, ASC_MC_DISC_ENABLE,
6876 asc_dvc->cfg->disc_enable);
6879 * Set SCSI_CFG0 Microcode Default Value.
6881 * The microcode will set the SCSI_CFG0 register using this value
6882 * after it is started below.
6884 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SCSI_CFG0,
6885 PARITY_EN | QUEUE_128 | SEL_TMO_LONG | OUR_ID_EN |
6886 asc_dvc->chip_scsi_id);
6889 * Determine SCSI_CFG1 Microcode Default Value.
6891 * The microcode will set the SCSI_CFG1 register using this value
6892 * after it is started below.
6895 /* Read current SCSI_CFG1 Register value. */
6896 scsi_cfg1 = AdvReadWordRegister(iop_base, IOPW_SCSI_CFG1);
6899 * If all three connectors are in use, return an error.
6901 if ((scsi_cfg1 & CABLE_ILLEGAL_A) == 0 ||
6902 (scsi_cfg1 & CABLE_ILLEGAL_B) == 0) {
6903 asc_dvc->err_code |= ASC_IERR_ILLEGAL_CONNECTION;
6908 * If the internal narrow cable is reversed all of the SCSI_CTRL
6909 * register signals will be set. Check for and return an error if
6910 * this condition is found.
6912 if ((AdvReadWordRegister(iop_base, IOPW_SCSI_CTRL) & 0x3F07) == 0x3F07) {
6913 asc_dvc->err_code |= ASC_IERR_REVERSED_CABLE;
6918 * If this is a differential board and a single-ended device
6919 * is attached to one of the connectors, return an error.
6921 if ((scsi_cfg1 & DIFF_MODE) && (scsi_cfg1 & DIFF_SENSE) == 0) {
6922 asc_dvc->err_code |= ASC_IERR_SINGLE_END_DEVICE;
6927 * If automatic termination control is enabled, then set the
6928 * termination value based on a table listed in a_condor.h.
6930 * If manual termination was specified with an EEPROM setting
6931 * then 'termination' was set-up in AdvInitFrom3550EEPROM() and
6932 * is ready to be 'ored' into SCSI_CFG1.
6934 if (asc_dvc->cfg->termination == 0) {
6936 * The software always controls termination by setting TERM_CTL_SEL.
6937 * If TERM_CTL_SEL were set to 0, the hardware would set termination.
6939 asc_dvc->cfg->termination |= TERM_CTL_SEL;
6941 switch (scsi_cfg1 & CABLE_DETECT) {
6942 /* TERM_CTL_H: on, TERM_CTL_L: on */
6949 asc_dvc->cfg->termination |= (TERM_CTL_H | TERM_CTL_L);
6952 /* TERM_CTL_H: on, TERM_CTL_L: off */
6958 asc_dvc->cfg->termination |= TERM_CTL_H;
6961 /* TERM_CTL_H: off, TERM_CTL_L: off */
6969 * Clear any set TERM_CTL_H and TERM_CTL_L bits.
6971 scsi_cfg1 &= ~TERM_CTL;
6974 * Invert the TERM_CTL_H and TERM_CTL_L bits and then
6975 * set 'scsi_cfg1'. The TERM_POL bit does not need to be
6976 * referenced, because the hardware internally inverts
6977 * the Termination High and Low bits if TERM_POL is set.
6979 scsi_cfg1 |= (TERM_CTL_SEL | (~asc_dvc->cfg->termination & TERM_CTL));
6982 * Set SCSI_CFG1 Microcode Default Value
6984 * Set filter value and possibly modified termination control
6985 * bits in the Microcode SCSI_CFG1 Register Value.
6987 * The microcode will set the SCSI_CFG1 register using this value
6988 * after it is started below.
6990 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SCSI_CFG1,
6991 FLTR_DISABLE | scsi_cfg1);
6994 * Set MEM_CFG Microcode Default Value
6996 * The microcode will set the MEM_CFG register using this value
6997 * after it is started below.
6999 * MEM_CFG may be accessed as a word or byte, but only bits 0-7
7002 * ASC-3550 has 8KB internal memory.
7004 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_MEM_CFG,
7005 BIOS_EN | RAM_SZ_8KB);
7008 * Set SEL_MASK Microcode Default Value
7010 * The microcode will set the SEL_MASK register using this value
7011 * after it is started below.
7013 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SEL_MASK,
7014 ADV_TID_TO_TIDMASK(asc_dvc->chip_scsi_id));
7016 AdvBuildCarrierFreelist(asc_dvc);
7019 * Set-up the Host->RISC Initiator Command Queue (ICQ).
7022 if ((asc_dvc->icq_sp = asc_dvc->carr_freelist) == NULL) {
7023 asc_dvc->err_code |= ASC_IERR_NO_CARRIER;
7026 asc_dvc->carr_freelist = (ADV_CARR_T *)
7027 ADV_U32_TO_VADDR(le32_to_cpu(asc_dvc->icq_sp->next_vpa));
7030 * The first command issued will be placed in the stopper carrier.
7032 asc_dvc->icq_sp->next_vpa = cpu_to_le32(ASC_CQ_STOPPER);
7035 * Set RISC ICQ physical address start value.
7037 AdvWriteDWordLramNoSwap(iop_base, ASC_MC_ICQ, asc_dvc->icq_sp->carr_pa);
7040 * Set-up the RISC->Host Initiator Response Queue (IRQ).
7042 if ((asc_dvc->irq_sp = asc_dvc->carr_freelist) == NULL) {
7043 asc_dvc->err_code |= ASC_IERR_NO_CARRIER;
7046 asc_dvc->carr_freelist = (ADV_CARR_T *)
7047 ADV_U32_TO_VADDR(le32_to_cpu(asc_dvc->irq_sp->next_vpa));
7050 * The first command completed by the RISC will be placed in
7053 * Note: Set 'next_vpa' to ASC_CQ_STOPPER. When the request is
7054 * completed the RISC will set the ASC_RQ_STOPPER bit.
7056 asc_dvc->irq_sp->next_vpa = cpu_to_le32(ASC_CQ_STOPPER);
7059 * Set RISC IRQ physical address start value.
7061 AdvWriteDWordLramNoSwap(iop_base, ASC_MC_IRQ, asc_dvc->irq_sp->carr_pa);
7062 asc_dvc->carr_pending_cnt = 0;
7064 AdvWriteByteRegister(iop_base, IOPB_INTR_ENABLES,
7065 (ADV_INTR_ENABLE_HOST_INTR |
7066 ADV_INTR_ENABLE_GLOBAL_INTR));
7068 AdvReadWordLram(iop_base, ASC_MC_CODE_BEGIN_ADDR, word);
7069 AdvWriteWordRegister(iop_base, IOPW_PC, word);
7071 /* finally, finally, gentlemen, start your engine */
7072 AdvWriteWordRegister(iop_base, IOPW_RISC_CSR, ADV_RISC_CSR_RUN);
7075 * Reset the SCSI Bus if the EEPROM indicates that SCSI Bus
7076 * Resets should be performed. The RISC has to be running
7077 * to issue a SCSI Bus Reset.
7079 if (asc_dvc->bios_ctrl & BIOS_CTRL_RESET_SCSI_BUS) {
7081 * If the BIOS Signature is present in memory, restore the
7082 * BIOS Handshake Configuration Table and do not perform
7085 if (bios_mem[(ASC_MC_BIOS_SIGNATURE - ASC_MC_BIOSMEM) / 2] ==
7088 * Restore per TID negotiated values.
7090 AdvWriteWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able);
7091 AdvWriteWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
7092 AdvWriteWordLram(iop_base, ASC_MC_TAGQNG_ABLE,
7094 for (tid = 0; tid <= ADV_MAX_TID; tid++) {
7095 AdvWriteByteLram(iop_base,
7096 ASC_MC_NUMBER_OF_MAX_CMD + tid,
7100 if (AdvResetSB(asc_dvc) != ADV_TRUE) {
7101 warn_code = ASC_WARN_BUSRESET_ERROR;
7110 * Initialize the ASC-38C0800.
7112 * On failure set the ADV_DVC_VAR field 'err_code' and return ADV_ERROR.
7114 * For a non-fatal error return a warning code. If there are no warnings
7115 * then 0 is returned.
7117 * Needed after initialization for error recovery.
7119 static int AdvInitAsc38C0800Driver(ADV_DVC_VAR *asc_dvc)
7121 AdvPortAddr iop_base;
7131 ushort bios_mem[ASC_MC_BIOSLEN / 2]; /* BIOS RISC Memory 0x40-0x8F. */
7132 ushort wdtr_able, sdtr_able, tagqng_able;
7133 uchar max_cmd[ADV_MAX_TID + 1];
7135 /* If there is already an error, don't continue. */
7136 if (asc_dvc->err_code != 0)
7140 * The caller must set 'chip_type' to ADV_CHIP_ASC38C0800.
7142 if (asc_dvc->chip_type != ADV_CHIP_ASC38C0800) {
7143 asc_dvc->err_code = ASC_IERR_BAD_CHIPTYPE;
7148 iop_base = asc_dvc->iop_base;
7151 * Save the RISC memory BIOS region before writing the microcode.
7152 * The BIOS may already be loaded and using its RISC LRAM region
7153 * so its region must be saved and restored.
7155 * Note: This code makes the assumption, which is currently true,
7156 * that a chip reset does not clear RISC LRAM.
7158 for (i = 0; i < ASC_MC_BIOSLEN / 2; i++) {
7159 AdvReadWordLram(iop_base, ASC_MC_BIOSMEM + (2 * i),
7164 * Save current per TID negotiated values.
7166 AdvReadWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able);
7167 AdvReadWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
7168 AdvReadWordLram(iop_base, ASC_MC_TAGQNG_ABLE, tagqng_able);
7169 for (tid = 0; tid <= ADV_MAX_TID; tid++) {
7170 AdvReadByteLram(iop_base, ASC_MC_NUMBER_OF_MAX_CMD + tid,
7175 * RAM BIST (RAM Built-In Self Test)
7177 * Address : I/O base + offset 0x38h register (byte).
7178 * Function: Bit 7-6(RW) : RAM mode
7179 * Normal Mode : 0x00
7180 * Pre-test Mode : 0x40
7181 * RAM Test Mode : 0x80
7183 * Bit 4(RO) : Done bit
7184 * Bit 3-0(RO) : Status
7186 * Int_RAM Error : 0x04
7191 * Note: RAM BIST code should be put right here, before loading the
7192 * microcode and after saving the RISC memory BIOS region.
7198 * Write PRE_TEST_MODE (0x40) to register and wait for 10 milliseconds.
7199 * If Done bit not set or low nibble not PRE_TEST_VALUE (0x05), return
7200 * an error. Reset to NORMAL_MODE (0x00) and do again. If cannot reset
7201 * to NORMAL_MODE, return an error too.
7203 for (i = 0; i < 2; i++) {
7204 AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, PRE_TEST_MODE);
7205 mdelay(10); /* Wait for 10ms before reading back. */
7206 byte = AdvReadByteRegister(iop_base, IOPB_RAM_BIST);
7207 if ((byte & RAM_TEST_DONE) == 0
7208 || (byte & 0x0F) != PRE_TEST_VALUE) {
7209 asc_dvc->err_code = ASC_IERR_BIST_PRE_TEST;
7213 AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, NORMAL_MODE);
7214 mdelay(10); /* Wait for 10ms before reading back. */
7215 if (AdvReadByteRegister(iop_base, IOPB_RAM_BIST)
7217 asc_dvc->err_code = ASC_IERR_BIST_PRE_TEST;
7223 * LRAM Test - It takes about 1.5 ms to run through the test.
7225 * Write RAM_TEST_MODE (0x80) to register and wait for 10 milliseconds.
7226 * If Done bit not set or Status not 0, save register byte, set the
7227 * err_code, and return an error.
7229 AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, RAM_TEST_MODE);
7230 mdelay(10); /* Wait for 10ms before checking status. */
7232 byte = AdvReadByteRegister(iop_base, IOPB_RAM_BIST);
7233 if ((byte & RAM_TEST_DONE) == 0 || (byte & RAM_TEST_STATUS) != 0) {
7234 /* Get here if Done bit not set or Status not 0. */
7235 asc_dvc->bist_err_code = byte; /* for BIOS display message */
7236 asc_dvc->err_code = ASC_IERR_BIST_RAM_TEST;
7240 /* We need to reset back to normal mode after LRAM test passes. */
7241 AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, NORMAL_MODE);
7243 asc_dvc->err_code = AdvLoadMicrocode(iop_base, _adv_asc38C0800_buf,
7244 _adv_asc38C0800_size, ADV_38C0800_MEMSIZE,
7245 _adv_asc38C0800_chksum);
7246 if (asc_dvc->err_code)
7250 * Restore the RISC memory BIOS region.
7252 for (i = 0; i < ASC_MC_BIOSLEN / 2; i++) {
7253 AdvWriteWordLram(iop_base, ASC_MC_BIOSMEM + (2 * i),
7258 * Calculate and write the microcode code checksum to the microcode
7259 * code checksum location ASC_MC_CODE_CHK_SUM (0x2C).
7261 AdvReadWordLram(iop_base, ASC_MC_CODE_BEGIN_ADDR, begin_addr);
7262 AdvReadWordLram(iop_base, ASC_MC_CODE_END_ADDR, end_addr);
7264 AdvWriteWordRegister(iop_base, IOPW_RAM_ADDR, begin_addr);
7265 for (word = begin_addr; word < end_addr; word += 2) {
7266 code_sum += AdvReadWordAutoIncLram(iop_base);
7268 AdvWriteWordLram(iop_base, ASC_MC_CODE_CHK_SUM, code_sum);
7271 * Read microcode version and date.
7273 AdvReadWordLram(iop_base, ASC_MC_VERSION_DATE,
7274 asc_dvc->cfg->mcode_date);
7275 AdvReadWordLram(iop_base, ASC_MC_VERSION_NUM,
7276 asc_dvc->cfg->mcode_version);
7279 * Set the chip type to indicate the ASC38C0800.
7281 AdvWriteWordLram(iop_base, ASC_MC_CHIP_TYPE, ADV_CHIP_ASC38C0800);
7284 * Write 1 to bit 14 'DIS_TERM_DRV' in the SCSI_CFG1 register.
7285 * When DIS_TERM_DRV set to 1, C_DET[3:0] will reflect current
7286 * cable detection and then we are able to read C_DET[3:0].
7288 * Note: We will reset DIS_TERM_DRV to 0 in the 'Set SCSI_CFG1
7289 * Microcode Default Value' section below.
7291 scsi_cfg1 = AdvReadWordRegister(iop_base, IOPW_SCSI_CFG1);
7292 AdvWriteWordRegister(iop_base, IOPW_SCSI_CFG1,
7293 scsi_cfg1 | DIS_TERM_DRV);
7296 * If the PCI Configuration Command Register "Parity Error Response
7297 * Control" Bit was clear (0), then set the microcode variable
7298 * 'control_flag' CONTROL_FLAG_IGNORE_PERR flag to tell the microcode
7299 * to ignore DMA parity errors.
7301 if (asc_dvc->cfg->control_flag & CONTROL_FLAG_IGNORE_PERR) {
7302 AdvReadWordLram(iop_base, ASC_MC_CONTROL_FLAG, word);
7303 word |= CONTROL_FLAG_IGNORE_PERR;
7304 AdvWriteWordLram(iop_base, ASC_MC_CONTROL_FLAG, word);
7308 * For ASC-38C0800, set FIFO_THRESH_80B [6:4] bits and START_CTL_TH [3:2]
7309 * bits for the default FIFO threshold.
7311 * Note: ASC-38C0800 FIFO threshold has been changed to 256 bytes.
7313 * For DMA Errata #4 set the BC_THRESH_ENB bit.
7315 AdvWriteByteRegister(iop_base, IOPB_DMA_CFG0,
7316 BC_THRESH_ENB | FIFO_THRESH_80B | START_CTL_TH |
7320 * Microcode operating variables for WDTR, SDTR, and command tag
7321 * queuing will be set in slave_configure() based on what a
7322 * device reports it is capable of in Inquiry byte 7.
7324 * If SCSI Bus Resets have been disabled, then directly set
7325 * SDTR and WDTR from the EEPROM configuration. This will allow
7326 * the BIOS and warm boot to work without a SCSI bus hang on
7327 * the Inquiry caused by host and target mismatched DTR values.
7328 * Without the SCSI Bus Reset, before an Inquiry a device can't
7329 * be assumed to be in Asynchronous, Narrow mode.
7331 if ((asc_dvc->bios_ctrl & BIOS_CTRL_RESET_SCSI_BUS) == 0) {
7332 AdvWriteWordLram(iop_base, ASC_MC_WDTR_ABLE,
7333 asc_dvc->wdtr_able);
7334 AdvWriteWordLram(iop_base, ASC_MC_SDTR_ABLE,
7335 asc_dvc->sdtr_able);
7339 * Set microcode operating variables for DISC and SDTR_SPEED1,
7340 * SDTR_SPEED2, SDTR_SPEED3, and SDTR_SPEED4 based on the EEPROM
7341 * configuration values.
7343 * The SDTR per TID bitmask overrides the SDTR_SPEED1, SDTR_SPEED2,
7344 * SDTR_SPEED3, and SDTR_SPEED4 values so it is safe to set them
7345 * without determining here whether the device supports SDTR.
7347 AdvWriteWordLram(iop_base, ASC_MC_DISC_ENABLE,
7348 asc_dvc->cfg->disc_enable);
7349 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED1, asc_dvc->sdtr_speed1);
7350 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED2, asc_dvc->sdtr_speed2);
7351 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED3, asc_dvc->sdtr_speed3);
7352 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED4, asc_dvc->sdtr_speed4);
7355 * Set SCSI_CFG0 Microcode Default Value.
7357 * The microcode will set the SCSI_CFG0 register using this value
7358 * after it is started below.
7360 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SCSI_CFG0,
7361 PARITY_EN | QUEUE_128 | SEL_TMO_LONG | OUR_ID_EN |
7362 asc_dvc->chip_scsi_id);
7365 * Determine SCSI_CFG1 Microcode Default Value.
7367 * The microcode will set the SCSI_CFG1 register using this value
7368 * after it is started below.
7371 /* Read current SCSI_CFG1 Register value. */
7372 scsi_cfg1 = AdvReadWordRegister(iop_base, IOPW_SCSI_CFG1);
7375 * If the internal narrow cable is reversed all of the SCSI_CTRL
7376 * register signals will be set. Check for and return an error if
7377 * this condition is found.
7379 if ((AdvReadWordRegister(iop_base, IOPW_SCSI_CTRL) & 0x3F07) == 0x3F07) {
7380 asc_dvc->err_code |= ASC_IERR_REVERSED_CABLE;
7385 * All kind of combinations of devices attached to one of four
7386 * connectors are acceptable except HVD device attached. For example,
7387 * LVD device can be attached to SE connector while SE device attached
7388 * to LVD connector. If LVD device attached to SE connector, it only
7389 * runs up to Ultra speed.
7391 * If an HVD device is attached to one of LVD connectors, return an
7392 * error. However, there is no way to detect HVD device attached to
7395 if (scsi_cfg1 & HVD) {
7396 asc_dvc->err_code = ASC_IERR_HVD_DEVICE;
7401 * If either SE or LVD automatic termination control is enabled, then
7402 * set the termination value based on a table listed in a_condor.h.
7404 * If manual termination was specified with an EEPROM setting then
7405 * 'termination' was set-up in AdvInitFrom38C0800EEPROM() and is ready
7406 * to be 'ored' into SCSI_CFG1.
7408 if ((asc_dvc->cfg->termination & TERM_SE) == 0) {
7409 /* SE automatic termination control is enabled. */
7410 switch (scsi_cfg1 & C_DET_SE) {
7411 /* TERM_SE_HI: on, TERM_SE_LO: on */
7415 asc_dvc->cfg->termination |= TERM_SE;
7418 /* TERM_SE_HI: on, TERM_SE_LO: off */
7420 asc_dvc->cfg->termination |= TERM_SE_HI;
7425 if ((asc_dvc->cfg->termination & TERM_LVD) == 0) {
7426 /* LVD automatic termination control is enabled. */
7427 switch (scsi_cfg1 & C_DET_LVD) {
7428 /* TERM_LVD_HI: on, TERM_LVD_LO: on */
7432 asc_dvc->cfg->termination |= TERM_LVD;
7435 /* TERM_LVD_HI: off, TERM_LVD_LO: off */
7442 * Clear any set TERM_SE and TERM_LVD bits.
7444 scsi_cfg1 &= (~TERM_SE & ~TERM_LVD);
7447 * Invert the TERM_SE and TERM_LVD bits and then set 'scsi_cfg1'.
7449 scsi_cfg1 |= (~asc_dvc->cfg->termination & 0xF0);
7452 * Clear BIG_ENDIAN, DIS_TERM_DRV, Terminator Polarity and HVD/LVD/SE
7453 * bits and set possibly modified termination control bits in the
7454 * Microcode SCSI_CFG1 Register Value.
7456 scsi_cfg1 &= (~BIG_ENDIAN & ~DIS_TERM_DRV & ~TERM_POL & ~HVD_LVD_SE);
7459 * Set SCSI_CFG1 Microcode Default Value
7461 * Set possibly modified termination control and reset DIS_TERM_DRV
7462 * bits in the Microcode SCSI_CFG1 Register Value.
7464 * The microcode will set the SCSI_CFG1 register using this value
7465 * after it is started below.
7467 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SCSI_CFG1, scsi_cfg1);
7470 * Set MEM_CFG Microcode Default Value
7472 * The microcode will set the MEM_CFG register using this value
7473 * after it is started below.
7475 * MEM_CFG may be accessed as a word or byte, but only bits 0-7
7478 * ASC-38C0800 has 16KB internal memory.
7480 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_MEM_CFG,
7481 BIOS_EN | RAM_SZ_16KB);
7484 * Set SEL_MASK Microcode Default Value
7486 * The microcode will set the SEL_MASK register using this value
7487 * after it is started below.
7489 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SEL_MASK,
7490 ADV_TID_TO_TIDMASK(asc_dvc->chip_scsi_id));
7492 AdvBuildCarrierFreelist(asc_dvc);
7495 * Set-up the Host->RISC Initiator Command Queue (ICQ).
7498 if ((asc_dvc->icq_sp = asc_dvc->carr_freelist) == NULL) {
7499 asc_dvc->err_code |= ASC_IERR_NO_CARRIER;
7502 asc_dvc->carr_freelist = (ADV_CARR_T *)
7503 ADV_U32_TO_VADDR(le32_to_cpu(asc_dvc->icq_sp->next_vpa));
7506 * The first command issued will be placed in the stopper carrier.
7508 asc_dvc->icq_sp->next_vpa = cpu_to_le32(ASC_CQ_STOPPER);
7511 * Set RISC ICQ physical address start value.
7512 * carr_pa is LE, must be native before write
7514 AdvWriteDWordLramNoSwap(iop_base, ASC_MC_ICQ, asc_dvc->icq_sp->carr_pa);
7517 * Set-up the RISC->Host Initiator Response Queue (IRQ).
7519 if ((asc_dvc->irq_sp = asc_dvc->carr_freelist) == NULL) {
7520 asc_dvc->err_code |= ASC_IERR_NO_CARRIER;
7523 asc_dvc->carr_freelist = (ADV_CARR_T *)
7524 ADV_U32_TO_VADDR(le32_to_cpu(asc_dvc->irq_sp->next_vpa));
7527 * The first command completed by the RISC will be placed in
7530 * Note: Set 'next_vpa' to ASC_CQ_STOPPER. When the request is
7531 * completed the RISC will set the ASC_RQ_STOPPER bit.
7533 asc_dvc->irq_sp->next_vpa = cpu_to_le32(ASC_CQ_STOPPER);
7536 * Set RISC IRQ physical address start value.
7538 * carr_pa is LE, must be native before write *
7540 AdvWriteDWordLramNoSwap(iop_base, ASC_MC_IRQ, asc_dvc->irq_sp->carr_pa);
7541 asc_dvc->carr_pending_cnt = 0;
7543 AdvWriteByteRegister(iop_base, IOPB_INTR_ENABLES,
7544 (ADV_INTR_ENABLE_HOST_INTR |
7545 ADV_INTR_ENABLE_GLOBAL_INTR));
7547 AdvReadWordLram(iop_base, ASC_MC_CODE_BEGIN_ADDR, word);
7548 AdvWriteWordRegister(iop_base, IOPW_PC, word);
7550 /* finally, finally, gentlemen, start your engine */
7551 AdvWriteWordRegister(iop_base, IOPW_RISC_CSR, ADV_RISC_CSR_RUN);
7554 * Reset the SCSI Bus if the EEPROM indicates that SCSI Bus
7555 * Resets should be performed. The RISC has to be running
7556 * to issue a SCSI Bus Reset.
7558 if (asc_dvc->bios_ctrl & BIOS_CTRL_RESET_SCSI_BUS) {
7560 * If the BIOS Signature is present in memory, restore the
7561 * BIOS Handshake Configuration Table and do not perform
7564 if (bios_mem[(ASC_MC_BIOS_SIGNATURE - ASC_MC_BIOSMEM) / 2] ==
7567 * Restore per TID negotiated values.
7569 AdvWriteWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able);
7570 AdvWriteWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
7571 AdvWriteWordLram(iop_base, ASC_MC_TAGQNG_ABLE,
7573 for (tid = 0; tid <= ADV_MAX_TID; tid++) {
7574 AdvWriteByteLram(iop_base,
7575 ASC_MC_NUMBER_OF_MAX_CMD + tid,
7579 if (AdvResetSB(asc_dvc) != ADV_TRUE) {
7580 warn_code = ASC_WARN_BUSRESET_ERROR;
7589 * Initialize the ASC-38C1600.
7591 * On failure set the ASC_DVC_VAR field 'err_code' and return ADV_ERROR.
7593 * For a non-fatal error return a warning code. If there are no warnings
7594 * then 0 is returned.
7596 * Needed after initialization for error recovery.
7598 static int AdvInitAsc38C1600Driver(ADV_DVC_VAR *asc_dvc)
7600 AdvPortAddr iop_base;
7610 ushort bios_mem[ASC_MC_BIOSLEN / 2]; /* BIOS RISC Memory 0x40-0x8F. */
7611 ushort wdtr_able, sdtr_able, ppr_able, tagqng_able;
7612 uchar max_cmd[ASC_MAX_TID + 1];
7614 /* If there is already an error, don't continue. */
7615 if (asc_dvc->err_code != 0) {
7620 * The caller must set 'chip_type' to ADV_CHIP_ASC38C1600.
7622 if (asc_dvc->chip_type != ADV_CHIP_ASC38C1600) {
7623 asc_dvc->err_code = ASC_IERR_BAD_CHIPTYPE;
7628 iop_base = asc_dvc->iop_base;
7631 * Save the RISC memory BIOS region before writing the microcode.
7632 * The BIOS may already be loaded and using its RISC LRAM region
7633 * so its region must be saved and restored.
7635 * Note: This code makes the assumption, which is currently true,
7636 * that a chip reset does not clear RISC LRAM.
7638 for (i = 0; i < ASC_MC_BIOSLEN / 2; i++) {
7639 AdvReadWordLram(iop_base, ASC_MC_BIOSMEM + (2 * i),
7644 * Save current per TID negotiated values.
7646 AdvReadWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able);
7647 AdvReadWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
7648 AdvReadWordLram(iop_base, ASC_MC_PPR_ABLE, ppr_able);
7649 AdvReadWordLram(iop_base, ASC_MC_TAGQNG_ABLE, tagqng_able);
7650 for (tid = 0; tid <= ASC_MAX_TID; tid++) {
7651 AdvReadByteLram(iop_base, ASC_MC_NUMBER_OF_MAX_CMD + tid,
7656 * RAM BIST (Built-In Self Test)
7658 * Address : I/O base + offset 0x38h register (byte).
7659 * Function: Bit 7-6(RW) : RAM mode
7660 * Normal Mode : 0x00
7661 * Pre-test Mode : 0x40
7662 * RAM Test Mode : 0x80
7664 * Bit 4(RO) : Done bit
7665 * Bit 3-0(RO) : Status
7667 * Int_RAM Error : 0x04
7672 * Note: RAM BIST code should be put right here, before loading the
7673 * microcode and after saving the RISC memory BIOS region.
7679 * Write PRE_TEST_MODE (0x40) to register and wait for 10 milliseconds.
7680 * If Done bit not set or low nibble not PRE_TEST_VALUE (0x05), return
7681 * an error. Reset to NORMAL_MODE (0x00) and do again. If cannot reset
7682 * to NORMAL_MODE, return an error too.
7684 for (i = 0; i < 2; i++) {
7685 AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, PRE_TEST_MODE);
7686 mdelay(10); /* Wait for 10ms before reading back. */
7687 byte = AdvReadByteRegister(iop_base, IOPB_RAM_BIST);
7688 if ((byte & RAM_TEST_DONE) == 0
7689 || (byte & 0x0F) != PRE_TEST_VALUE) {
7690 asc_dvc->err_code = ASC_IERR_BIST_PRE_TEST;
7694 AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, NORMAL_MODE);
7695 mdelay(10); /* Wait for 10ms before reading back. */
7696 if (AdvReadByteRegister(iop_base, IOPB_RAM_BIST)
7698 asc_dvc->err_code = ASC_IERR_BIST_PRE_TEST;
7704 * LRAM Test - It takes about 1.5 ms to run through the test.
7706 * Write RAM_TEST_MODE (0x80) to register and wait for 10 milliseconds.
7707 * If Done bit not set or Status not 0, save register byte, set the
7708 * err_code, and return an error.
7710 AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, RAM_TEST_MODE);
7711 mdelay(10); /* Wait for 10ms before checking status. */
7713 byte = AdvReadByteRegister(iop_base, IOPB_RAM_BIST);
7714 if ((byte & RAM_TEST_DONE) == 0 || (byte & RAM_TEST_STATUS) != 0) {
7715 /* Get here if Done bit not set or Status not 0. */
7716 asc_dvc->bist_err_code = byte; /* for BIOS display message */
7717 asc_dvc->err_code = ASC_IERR_BIST_RAM_TEST;
7721 /* We need to reset back to normal mode after LRAM test passes. */
7722 AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, NORMAL_MODE);
7724 asc_dvc->err_code = AdvLoadMicrocode(iop_base, _adv_asc38C1600_buf,
7725 _adv_asc38C1600_size, ADV_38C1600_MEMSIZE,
7726 _adv_asc38C1600_chksum);
7727 if (asc_dvc->err_code)
7731 * Restore the RISC memory BIOS region.
7733 for (i = 0; i < ASC_MC_BIOSLEN / 2; i++) {
7734 AdvWriteWordLram(iop_base, ASC_MC_BIOSMEM + (2 * i),
7739 * Calculate and write the microcode code checksum to the microcode
7740 * code checksum location ASC_MC_CODE_CHK_SUM (0x2C).
7742 AdvReadWordLram(iop_base, ASC_MC_CODE_BEGIN_ADDR, begin_addr);
7743 AdvReadWordLram(iop_base, ASC_MC_CODE_END_ADDR, end_addr);
7745 AdvWriteWordRegister(iop_base, IOPW_RAM_ADDR, begin_addr);
7746 for (word = begin_addr; word < end_addr; word += 2) {
7747 code_sum += AdvReadWordAutoIncLram(iop_base);
7749 AdvWriteWordLram(iop_base, ASC_MC_CODE_CHK_SUM, code_sum);
7752 * Read microcode version and date.
7754 AdvReadWordLram(iop_base, ASC_MC_VERSION_DATE,
7755 asc_dvc->cfg->mcode_date);
7756 AdvReadWordLram(iop_base, ASC_MC_VERSION_NUM,
7757 asc_dvc->cfg->mcode_version);
7760 * Set the chip type to indicate the ASC38C1600.
7762 AdvWriteWordLram(iop_base, ASC_MC_CHIP_TYPE, ADV_CHIP_ASC38C1600);
7765 * Write 1 to bit 14 'DIS_TERM_DRV' in the SCSI_CFG1 register.
7766 * When DIS_TERM_DRV set to 1, C_DET[3:0] will reflect current
7767 * cable detection and then we are able to read C_DET[3:0].
7769 * Note: We will reset DIS_TERM_DRV to 0 in the 'Set SCSI_CFG1
7770 * Microcode Default Value' section below.
7772 scsi_cfg1 = AdvReadWordRegister(iop_base, IOPW_SCSI_CFG1);
7773 AdvWriteWordRegister(iop_base, IOPW_SCSI_CFG1,
7774 scsi_cfg1 | DIS_TERM_DRV);
7777 * If the PCI Configuration Command Register "Parity Error Response
7778 * Control" Bit was clear (0), then set the microcode variable
7779 * 'control_flag' CONTROL_FLAG_IGNORE_PERR flag to tell the microcode
7780 * to ignore DMA parity errors.
7782 if (asc_dvc->cfg->control_flag & CONTROL_FLAG_IGNORE_PERR) {
7783 AdvReadWordLram(iop_base, ASC_MC_CONTROL_FLAG, word);
7784 word |= CONTROL_FLAG_IGNORE_PERR;
7785 AdvWriteWordLram(iop_base, ASC_MC_CONTROL_FLAG, word);
7789 * If the BIOS control flag AIPP (Asynchronous Information
7790 * Phase Protection) disable bit is not set, then set the firmware
7791 * 'control_flag' CONTROL_FLAG_ENABLE_AIPP bit to enable
7792 * AIPP checking and encoding.
7794 if ((asc_dvc->bios_ctrl & BIOS_CTRL_AIPP_DIS) == 0) {
7795 AdvReadWordLram(iop_base, ASC_MC_CONTROL_FLAG, word);
7796 word |= CONTROL_FLAG_ENABLE_AIPP;
7797 AdvWriteWordLram(iop_base, ASC_MC_CONTROL_FLAG, word);
7801 * For ASC-38C1600 use DMA_CFG0 default values: FIFO_THRESH_80B [6:4],
7802 * and START_CTL_TH [3:2].
7804 AdvWriteByteRegister(iop_base, IOPB_DMA_CFG0,
7805 FIFO_THRESH_80B | START_CTL_TH | READ_CMD_MRM);
7808 * Microcode operating variables for WDTR, SDTR, and command tag
7809 * queuing will be set in slave_configure() based on what a
7810 * device reports it is capable of in Inquiry byte 7.
7812 * If SCSI Bus Resets have been disabled, then directly set
7813 * SDTR and WDTR from the EEPROM configuration. This will allow
7814 * the BIOS and warm boot to work without a SCSI bus hang on
7815 * the Inquiry caused by host and target mismatched DTR values.
7816 * Without the SCSI Bus Reset, before an Inquiry a device can't
7817 * be assumed to be in Asynchronous, Narrow mode.
7819 if ((asc_dvc->bios_ctrl & BIOS_CTRL_RESET_SCSI_BUS) == 0) {
7820 AdvWriteWordLram(iop_base, ASC_MC_WDTR_ABLE,
7821 asc_dvc->wdtr_able);
7822 AdvWriteWordLram(iop_base, ASC_MC_SDTR_ABLE,
7823 asc_dvc->sdtr_able);
7827 * Set microcode operating variables for DISC and SDTR_SPEED1,
7828 * SDTR_SPEED2, SDTR_SPEED3, and SDTR_SPEED4 based on the EEPROM
7829 * configuration values.
7831 * The SDTR per TID bitmask overrides the SDTR_SPEED1, SDTR_SPEED2,
7832 * SDTR_SPEED3, and SDTR_SPEED4 values so it is safe to set them
7833 * without determining here whether the device supports SDTR.
7835 AdvWriteWordLram(iop_base, ASC_MC_DISC_ENABLE,
7836 asc_dvc->cfg->disc_enable);
7837 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED1, asc_dvc->sdtr_speed1);
7838 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED2, asc_dvc->sdtr_speed2);
7839 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED3, asc_dvc->sdtr_speed3);
7840 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED4, asc_dvc->sdtr_speed4);
7843 * Set SCSI_CFG0 Microcode Default Value.
7845 * The microcode will set the SCSI_CFG0 register using this value
7846 * after it is started below.
7848 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SCSI_CFG0,
7849 PARITY_EN | QUEUE_128 | SEL_TMO_LONG | OUR_ID_EN |
7850 asc_dvc->chip_scsi_id);
7853 * Calculate SCSI_CFG1 Microcode Default Value.
7855 * The microcode will set the SCSI_CFG1 register using this value
7856 * after it is started below.
7858 * Each ASC-38C1600 function has only two cable detect bits.
7859 * The bus mode override bits are in IOPB_SOFT_OVER_WR.
7861 scsi_cfg1 = AdvReadWordRegister(iop_base, IOPW_SCSI_CFG1);
7864 * If the cable is reversed all of the SCSI_CTRL register signals
7865 * will be set. Check for and return an error if this condition is
7868 if ((AdvReadWordRegister(iop_base, IOPW_SCSI_CTRL) & 0x3F07) == 0x3F07) {
7869 asc_dvc->err_code |= ASC_IERR_REVERSED_CABLE;
7874 * Each ASC-38C1600 function has two connectors. Only an HVD device
7875 * can not be connected to either connector. An LVD device or SE device
7876 * may be connected to either connecor. If an SE device is connected,
7877 * then at most Ultra speed (20 Mhz) can be used on both connectors.
7879 * If an HVD device is attached, return an error.
7881 if (scsi_cfg1 & HVD) {
7882 asc_dvc->err_code |= ASC_IERR_HVD_DEVICE;
7887 * Each function in the ASC-38C1600 uses only the SE cable detect and
7888 * termination because there are two connectors for each function. Each
7889 * function may use either LVD or SE mode. Corresponding the SE automatic
7890 * termination control EEPROM bits are used for each function. Each
7891 * function has its own EEPROM. If SE automatic control is enabled for
7892 * the function, then set the termination value based on a table listed
7895 * If manual termination is specified in the EEPROM for the function,
7896 * then 'termination' was set-up in AscInitFrom38C1600EEPROM() and is
7897 * ready to be 'ored' into SCSI_CFG1.
7899 if ((asc_dvc->cfg->termination & TERM_SE) == 0) {
7900 struct pci_dev *pdev = adv_dvc_to_pdev(asc_dvc);
7901 /* SE automatic termination control is enabled. */
7902 switch (scsi_cfg1 & C_DET_SE) {
7903 /* TERM_SE_HI: on, TERM_SE_LO: on */
7907 asc_dvc->cfg->termination |= TERM_SE;
7911 if (PCI_FUNC(pdev->devfn) == 0) {
7912 /* Function 0 - TERM_SE_HI: off, TERM_SE_LO: off */
7914 /* Function 1 - TERM_SE_HI: on, TERM_SE_LO: off */
7915 asc_dvc->cfg->termination |= TERM_SE_HI;
7922 * Clear any set TERM_SE bits.
7924 scsi_cfg1 &= ~TERM_SE;
7927 * Invert the TERM_SE bits and then set 'scsi_cfg1'.
7929 scsi_cfg1 |= (~asc_dvc->cfg->termination & TERM_SE);
7932 * Clear Big Endian and Terminator Polarity bits and set possibly
7933 * modified termination control bits in the Microcode SCSI_CFG1
7936 * Big Endian bit is not used even on big endian machines.
7938 scsi_cfg1 &= (~BIG_ENDIAN & ~DIS_TERM_DRV & ~TERM_POL);
7941 * Set SCSI_CFG1 Microcode Default Value
7943 * Set possibly modified termination control bits in the Microcode
7944 * SCSI_CFG1 Register Value.
7946 * The microcode will set the SCSI_CFG1 register using this value
7947 * after it is started below.
7949 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SCSI_CFG1, scsi_cfg1);
7952 * Set MEM_CFG Microcode Default Value
7954 * The microcode will set the MEM_CFG register using this value
7955 * after it is started below.
7957 * MEM_CFG may be accessed as a word or byte, but only bits 0-7
7960 * ASC-38C1600 has 32KB internal memory.
7962 * XXX - Since ASC38C1600 Rev.3 has a Local RAM failure issue, we come
7963 * out a special 16K Adv Library and Microcode version. After the issue
7964 * resolved, we should turn back to the 32K support. Both a_condor.h and
7965 * mcode.sas files also need to be updated.
7967 * AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_MEM_CFG,
7968 * BIOS_EN | RAM_SZ_32KB);
7970 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_MEM_CFG,
7971 BIOS_EN | RAM_SZ_16KB);
7974 * Set SEL_MASK Microcode Default Value
7976 * The microcode will set the SEL_MASK register using this value
7977 * after it is started below.
7979 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SEL_MASK,
7980 ADV_TID_TO_TIDMASK(asc_dvc->chip_scsi_id));
7982 AdvBuildCarrierFreelist(asc_dvc);
7985 * Set-up the Host->RISC Initiator Command Queue (ICQ).
7987 if ((asc_dvc->icq_sp = asc_dvc->carr_freelist) == NULL) {
7988 asc_dvc->err_code |= ASC_IERR_NO_CARRIER;
7991 asc_dvc->carr_freelist = (ADV_CARR_T *)
7992 ADV_U32_TO_VADDR(le32_to_cpu(asc_dvc->icq_sp->next_vpa));
7995 * The first command issued will be placed in the stopper carrier.
7997 asc_dvc->icq_sp->next_vpa = cpu_to_le32(ASC_CQ_STOPPER);
8000 * Set RISC ICQ physical address start value. Initialize the
8001 * COMMA register to the same value otherwise the RISC will
8002 * prematurely detect a command is available.
8004 AdvWriteDWordLramNoSwap(iop_base, ASC_MC_ICQ, asc_dvc->icq_sp->carr_pa);
8005 AdvWriteDWordRegister(iop_base, IOPDW_COMMA,
8006 le32_to_cpu(asc_dvc->icq_sp->carr_pa));
8009 * Set-up the RISC->Host Initiator Response Queue (IRQ).
8011 if ((asc_dvc->irq_sp = asc_dvc->carr_freelist) == NULL) {
8012 asc_dvc->err_code |= ASC_IERR_NO_CARRIER;
8015 asc_dvc->carr_freelist = (ADV_CARR_T *)
8016 ADV_U32_TO_VADDR(le32_to_cpu(asc_dvc->irq_sp->next_vpa));
8019 * The first command completed by the RISC will be placed in
8022 * Note: Set 'next_vpa' to ASC_CQ_STOPPER. When the request is
8023 * completed the RISC will set the ASC_RQ_STOPPER bit.
8025 asc_dvc->irq_sp->next_vpa = cpu_to_le32(ASC_CQ_STOPPER);
8028 * Set RISC IRQ physical address start value.
8030 AdvWriteDWordLramNoSwap(iop_base, ASC_MC_IRQ, asc_dvc->irq_sp->carr_pa);
8031 asc_dvc->carr_pending_cnt = 0;
8033 AdvWriteByteRegister(iop_base, IOPB_INTR_ENABLES,
8034 (ADV_INTR_ENABLE_HOST_INTR |
8035 ADV_INTR_ENABLE_GLOBAL_INTR));
8036 AdvReadWordLram(iop_base, ASC_MC_CODE_BEGIN_ADDR, word);
8037 AdvWriteWordRegister(iop_base, IOPW_PC, word);
8039 /* finally, finally, gentlemen, start your engine */
8040 AdvWriteWordRegister(iop_base, IOPW_RISC_CSR, ADV_RISC_CSR_RUN);
8043 * Reset the SCSI Bus if the EEPROM indicates that SCSI Bus
8044 * Resets should be performed. The RISC has to be running
8045 * to issue a SCSI Bus Reset.
8047 if (asc_dvc->bios_ctrl & BIOS_CTRL_RESET_SCSI_BUS) {
8049 * If the BIOS Signature is present in memory, restore the
8050 * per TID microcode operating variables.
8052 if (bios_mem[(ASC_MC_BIOS_SIGNATURE - ASC_MC_BIOSMEM) / 2] ==
8055 * Restore per TID negotiated values.
8057 AdvWriteWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able);
8058 AdvWriteWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
8059 AdvWriteWordLram(iop_base, ASC_MC_PPR_ABLE, ppr_able);
8060 AdvWriteWordLram(iop_base, ASC_MC_TAGQNG_ABLE,
8062 for (tid = 0; tid <= ASC_MAX_TID; tid++) {
8063 AdvWriteByteLram(iop_base,
8064 ASC_MC_NUMBER_OF_MAX_CMD + tid,
8068 if (AdvResetSB(asc_dvc) != ADV_TRUE) {
8069 warn_code = ASC_WARN_BUSRESET_ERROR;
8078 * Reset chip and SCSI Bus.
8081 * ADV_TRUE(1) - Chip re-initialization and SCSI Bus Reset successful.
8082 * ADV_FALSE(0) - Chip re-initialization and SCSI Bus Reset failure.
8084 static int AdvResetChipAndSB(ADV_DVC_VAR *asc_dvc)
8087 ushort wdtr_able, sdtr_able, tagqng_able;
8088 ushort ppr_able = 0;
8089 uchar tid, max_cmd[ADV_MAX_TID + 1];
8090 AdvPortAddr iop_base;
8093 iop_base = asc_dvc->iop_base;
8096 * Save current per TID negotiated values.
8098 AdvReadWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able);
8099 AdvReadWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
8100 if (asc_dvc->chip_type == ADV_CHIP_ASC38C1600) {
8101 AdvReadWordLram(iop_base, ASC_MC_PPR_ABLE, ppr_able);
8103 AdvReadWordLram(iop_base, ASC_MC_TAGQNG_ABLE, tagqng_able);
8104 for (tid = 0; tid <= ADV_MAX_TID; tid++) {
8105 AdvReadByteLram(iop_base, ASC_MC_NUMBER_OF_MAX_CMD + tid,
8110 * Force the AdvInitAsc3550/38C0800Driver() function to
8111 * perform a SCSI Bus Reset by clearing the BIOS signature word.
8112 * The initialization functions assumes a SCSI Bus Reset is not
8113 * needed if the BIOS signature word is present.
8115 AdvReadWordLram(iop_base, ASC_MC_BIOS_SIGNATURE, bios_sig);
8116 AdvWriteWordLram(iop_base, ASC_MC_BIOS_SIGNATURE, 0);
8119 * Stop chip and reset it.
8121 AdvWriteWordRegister(iop_base, IOPW_RISC_CSR, ADV_RISC_CSR_STOP);
8122 AdvWriteWordRegister(iop_base, IOPW_CTRL_REG, ADV_CTRL_REG_CMD_RESET);
8124 AdvWriteWordRegister(iop_base, IOPW_CTRL_REG,
8125 ADV_CTRL_REG_CMD_WR_IO_REG);
8128 * Reset Adv Library error code, if any, and try
8129 * re-initializing the chip.
8131 asc_dvc->err_code = 0;
8132 if (asc_dvc->chip_type == ADV_CHIP_ASC38C1600) {
8133 status = AdvInitAsc38C1600Driver(asc_dvc);
8134 } else if (asc_dvc->chip_type == ADV_CHIP_ASC38C0800) {
8135 status = AdvInitAsc38C0800Driver(asc_dvc);
8137 status = AdvInitAsc3550Driver(asc_dvc);
8140 /* Translate initialization return value to status value. */
8148 * Restore the BIOS signature word.
8150 AdvWriteWordLram(iop_base, ASC_MC_BIOS_SIGNATURE, bios_sig);
8153 * Restore per TID negotiated values.
8155 AdvWriteWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able);
8156 AdvWriteWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
8157 if (asc_dvc->chip_type == ADV_CHIP_ASC38C1600) {
8158 AdvWriteWordLram(iop_base, ASC_MC_PPR_ABLE, ppr_able);
8160 AdvWriteWordLram(iop_base, ASC_MC_TAGQNG_ABLE, tagqng_able);
8161 for (tid = 0; tid <= ADV_MAX_TID; tid++) {
8162 AdvWriteByteLram(iop_base, ASC_MC_NUMBER_OF_MAX_CMD + tid,
8170 * adv_async_callback() - Adv Library asynchronous event callback function.
8172 static void adv_async_callback(ADV_DVC_VAR *adv_dvc_varp, uchar code)
8175 case ADV_ASYNC_SCSI_BUS_RESET_DET:
8177 * The firmware detected a SCSI Bus reset.
8179 ASC_DBG(0, "ADV_ASYNC_SCSI_BUS_RESET_DET\n");
8182 case ADV_ASYNC_RDMA_FAILURE:
8184 * Handle RDMA failure by resetting the SCSI Bus and
8185 * possibly the chip if it is unresponsive. Log the error
8186 * with a unique code.
8188 ASC_DBG(0, "ADV_ASYNC_RDMA_FAILURE\n");
8189 AdvResetChipAndSB(adv_dvc_varp);
8192 case ADV_HOST_SCSI_BUS_RESET:
8194 * Host generated SCSI bus reset occurred.
8196 ASC_DBG(0, "ADV_HOST_SCSI_BUS_RESET\n");
8200 ASC_DBG(0, "unknown code 0x%x\n", code);
8206 * adv_isr_callback() - Second Level Interrupt Handler called by AdvISR().
8208 * Callback function for the Wide SCSI Adv Library.
8210 static void adv_isr_callback(ADV_DVC_VAR *adv_dvc_varp, ADV_SCSI_REQ_Q *scsiqp)
8212 struct asc_board *boardp;
8214 adv_sgblk_t *sgblkp;
8215 struct scsi_cmnd *scp;
8216 struct Scsi_Host *shost;
8219 ASC_DBG(1, "adv_dvc_varp 0x%lx, scsiqp 0x%lx\n",
8220 (ulong)adv_dvc_varp, (ulong)scsiqp);
8221 ASC_DBG_PRT_ADV_SCSI_REQ_Q(2, scsiqp);
8224 * Get the adv_req_t structure for the command that has been
8225 * completed. The adv_req_t structure actually contains the
8226 * completed ADV_SCSI_REQ_Q structure.
8228 reqp = (adv_req_t *)ADV_U32_TO_VADDR(scsiqp->srb_ptr);
8229 ASC_DBG(1, "reqp 0x%lx\n", (ulong)reqp);
8231 ASC_PRINT("adv_isr_callback: reqp is NULL\n");
8236 * Get the struct scsi_cmnd structure and Scsi_Host structure for the
8237 * command that has been completed.
8239 * Note: The adv_req_t request structure and adv_sgblk_t structure,
8240 * if any, are dropped, because a board structure pointer can not be
8244 ASC_DBG(1, "scp 0x%p\n", scp);
8247 ("adv_isr_callback: scp is NULL; adv_req_t dropped.\n");
8250 ASC_DBG_PRT_CDB(2, scp->cmnd, scp->cmd_len);
8252 shost = scp->device->host;
8253 ASC_STATS(shost, callback);
8254 ASC_DBG(1, "shost 0x%p\n", shost);
8256 boardp = shost_priv(shost);
8257 BUG_ON(adv_dvc_varp != &boardp->dvc_var.adv_dvc_var);
8260 * 'done_status' contains the command's ending status.
8262 switch (scsiqp->done_status) {
8264 ASC_DBG(2, "QD_NO_ERROR\n");
8268 * Check for an underrun condition.
8270 * If there was no error and an underrun condition, then
8271 * then return the number of underrun bytes.
8273 resid_cnt = le32_to_cpu(scsiqp->data_cnt);
8274 if (scp->request_bufflen != 0 && resid_cnt != 0 &&
8275 resid_cnt <= scp->request_bufflen) {
8276 ASC_DBG(1, "underrun condition %lu bytes\n",
8278 scp->resid = resid_cnt;
8283 ASC_DBG(2, "QD_WITH_ERROR\n");
8284 switch (scsiqp->host_status) {
8285 case QHSTA_NO_ERROR:
8286 if (scsiqp->scsi_status == SAM_STAT_CHECK_CONDITION) {
8287 ASC_DBG(2, "SAM_STAT_CHECK_CONDITION\n");
8288 ASC_DBG_PRT_SENSE(2, scp->sense_buffer,
8289 sizeof(scp->sense_buffer));
8291 * Note: The 'status_byte()' macro used by
8292 * target drivers defined in scsi.h shifts the
8293 * status byte returned by host drivers right
8294 * by 1 bit. This is why target drivers also
8295 * use right shifted status byte definitions.
8296 * For instance target drivers use
8297 * CHECK_CONDITION, defined to 0x1, instead of
8298 * the SCSI defined check condition value of
8299 * 0x2. Host drivers are supposed to return
8300 * the status byte as it is defined by SCSI.
8302 scp->result = DRIVER_BYTE(DRIVER_SENSE) |
8303 STATUS_BYTE(scsiqp->scsi_status);
8305 scp->result = STATUS_BYTE(scsiqp->scsi_status);
8310 /* Some other QHSTA error occurred. */
8311 ASC_DBG(1, "host_status 0x%x\n", scsiqp->host_status);
8312 scp->result = HOST_BYTE(DID_BAD_TARGET);
8317 case QD_ABORTED_BY_HOST:
8318 ASC_DBG(1, "QD_ABORTED_BY_HOST\n");
8320 HOST_BYTE(DID_ABORT) | STATUS_BYTE(scsiqp->scsi_status);
8324 ASC_DBG(1, "done_status 0x%x\n", scsiqp->done_status);
8326 HOST_BYTE(DID_ERROR) | STATUS_BYTE(scsiqp->scsi_status);
8331 * If the 'init_tidmask' bit isn't already set for the target and the
8332 * current request finished normally, then set the bit for the target
8333 * to indicate that a device is present.
8335 if ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(scp->device->id)) == 0 &&
8336 scsiqp->done_status == QD_NO_ERROR &&
8337 scsiqp->host_status == QHSTA_NO_ERROR) {
8338 boardp->init_tidmask |= ADV_TID_TO_TIDMASK(scp->device->id);
8344 * Free all 'adv_sgblk_t' structures allocated for the request.
8346 while ((sgblkp = reqp->sgblkp) != NULL) {
8347 /* Remove 'sgblkp' from the request list. */
8348 reqp->sgblkp = sgblkp->next_sgblkp;
8350 /* Add 'sgblkp' to the board free list. */
8351 sgblkp->next_sgblkp = boardp->adv_sgblkp;
8352 boardp->adv_sgblkp = sgblkp;
8356 * Free the adv_req_t structure used with the command by adding
8357 * it back to the board free list.
8359 reqp->next_reqp = boardp->adv_reqp;
8360 boardp->adv_reqp = reqp;
8362 ASC_DBG(1, "done\n");
8366 * Adv Library Interrupt Service Routine
8368 * This function is called by a driver's interrupt service routine.
8369 * The function disables and re-enables interrupts.
8371 * When a microcode idle command is completed, the ADV_DVC_VAR
8372 * 'idle_cmd_done' field is set to ADV_TRUE.
8374 * Note: AdvISR() can be called when interrupts are disabled or even
8375 * when there is no hardware interrupt condition present. It will
8376 * always check for completed idle commands and microcode requests.
8377 * This is an important feature that shouldn't be changed because it
8378 * allows commands to be completed from polling mode loops.
8381 * ADV_TRUE(1) - interrupt was pending
8382 * ADV_FALSE(0) - no interrupt was pending
8384 static int AdvISR(ADV_DVC_VAR *asc_dvc)
8386 AdvPortAddr iop_base;
8389 ADV_CARR_T *free_carrp;
8390 ADV_VADDR irq_next_vpa;
8391 ADV_SCSI_REQ_Q *scsiq;
8393 iop_base = asc_dvc->iop_base;
8395 /* Reading the register clears the interrupt. */
8396 int_stat = AdvReadByteRegister(iop_base, IOPB_INTR_STATUS_REG);
8398 if ((int_stat & (ADV_INTR_STATUS_INTRA | ADV_INTR_STATUS_INTRB |
8399 ADV_INTR_STATUS_INTRC)) == 0) {
8404 * Notify the driver of an asynchronous microcode condition by
8405 * calling the adv_async_callback function. The function
8406 * is passed the microcode ASC_MC_INTRB_CODE byte value.
8408 if (int_stat & ADV_INTR_STATUS_INTRB) {
8411 AdvReadByteLram(iop_base, ASC_MC_INTRB_CODE, intrb_code);
8413 if (asc_dvc->chip_type == ADV_CHIP_ASC3550 ||
8414 asc_dvc->chip_type == ADV_CHIP_ASC38C0800) {
8415 if (intrb_code == ADV_ASYNC_CARRIER_READY_FAILURE &&
8416 asc_dvc->carr_pending_cnt != 0) {
8417 AdvWriteByteRegister(iop_base, IOPB_TICKLE,
8419 if (asc_dvc->chip_type == ADV_CHIP_ASC3550) {
8420 AdvWriteByteRegister(iop_base,
8427 adv_async_callback(asc_dvc, intrb_code);
8431 * Check if the IRQ stopper carrier contains a completed request.
8433 while (((irq_next_vpa =
8434 le32_to_cpu(asc_dvc->irq_sp->next_vpa)) & ASC_RQ_DONE) != 0) {
8436 * Get a pointer to the newly completed ADV_SCSI_REQ_Q structure.
8437 * The RISC will have set 'areq_vpa' to a virtual address.
8439 * The firmware will have copied the ASC_SCSI_REQ_Q.scsiq_ptr
8440 * field to the carrier ADV_CARR_T.areq_vpa field. The conversion
8441 * below complements the conversion of ASC_SCSI_REQ_Q.scsiq_ptr'
8442 * in AdvExeScsiQueue().
8444 scsiq = (ADV_SCSI_REQ_Q *)
8445 ADV_U32_TO_VADDR(le32_to_cpu(asc_dvc->irq_sp->areq_vpa));
8448 * Request finished with good status and the queue was not
8449 * DMAed to host memory by the firmware. Set all status fields
8450 * to indicate good status.
8452 if ((irq_next_vpa & ASC_RQ_GOOD) != 0) {
8453 scsiq->done_status = QD_NO_ERROR;
8454 scsiq->host_status = scsiq->scsi_status = 0;
8455 scsiq->data_cnt = 0L;
8459 * Advance the stopper pointer to the next carrier
8460 * ignoring the lower four bits. Free the previous
8463 free_carrp = asc_dvc->irq_sp;
8464 asc_dvc->irq_sp = (ADV_CARR_T *)
8465 ADV_U32_TO_VADDR(ASC_GET_CARRP(irq_next_vpa));
8467 free_carrp->next_vpa =
8468 cpu_to_le32(ADV_VADDR_TO_U32(asc_dvc->carr_freelist));
8469 asc_dvc->carr_freelist = free_carrp;
8470 asc_dvc->carr_pending_cnt--;
8472 target_bit = ADV_TID_TO_TIDMASK(scsiq->target_id);
8475 * Clear request microcode control flag.
8480 * Notify the driver of the completed request by passing
8481 * the ADV_SCSI_REQ_Q pointer to its callback function.
8483 scsiq->a_flag |= ADV_SCSIQ_DONE;
8484 adv_isr_callback(asc_dvc, scsiq);
8486 * Note: After the driver callback function is called, 'scsiq'
8487 * can no longer be referenced.
8489 * Fall through and continue processing other completed
8496 static int AscSetLibErrorCode(ASC_DVC_VAR *asc_dvc, ushort err_code)
8498 if (asc_dvc->err_code == 0) {
8499 asc_dvc->err_code = err_code;
8500 AscWriteLramWord(asc_dvc->iop_base, ASCV_ASCDVC_ERR_CODE_W,
8506 static void AscAckInterrupt(PortAddr iop_base)
8514 risc_flag = AscReadLramByte(iop_base, ASCV_RISC_FLAG_B);
8515 if (loop++ > 0x7FFF) {
8518 } while ((risc_flag & ASC_RISC_FLAG_GEN_INT) != 0);
8520 AscReadLramByte(iop_base,
8521 ASCV_HOST_FLAG_B) & (~ASC_HOST_FLAG_ACK_INT);
8522 AscWriteLramByte(iop_base, ASCV_HOST_FLAG_B,
8523 (uchar)(host_flag | ASC_HOST_FLAG_ACK_INT));
8524 AscSetChipStatus(iop_base, CIW_INT_ACK);
8526 while (AscGetChipStatus(iop_base) & CSW_INT_PENDING) {
8527 AscSetChipStatus(iop_base, CIW_INT_ACK);
8532 AscWriteLramByte(iop_base, ASCV_HOST_FLAG_B, host_flag);
8535 static uchar AscGetSynPeriodIndex(ASC_DVC_VAR *asc_dvc, uchar syn_time)
8537 const uchar *period_table;
8542 period_table = asc_dvc->sdtr_period_tbl;
8543 max_index = (int)asc_dvc->max_sdtr_index;
8544 min_index = (int)asc_dvc->min_sdtr_index;
8545 if ((syn_time <= period_table[max_index])) {
8546 for (i = min_index; i < (max_index - 1); i++) {
8547 if (syn_time <= period_table[i]) {
8551 return (uchar)max_index;
8553 return (uchar)(max_index + 1);
8558 AscMsgOutSDTR(ASC_DVC_VAR *asc_dvc, uchar sdtr_period, uchar sdtr_offset)
8561 uchar sdtr_period_index;
8564 iop_base = asc_dvc->iop_base;
8565 sdtr_buf.msg_type = EXTENDED_MESSAGE;
8566 sdtr_buf.msg_len = MS_SDTR_LEN;
8567 sdtr_buf.msg_req = EXTENDED_SDTR;
8568 sdtr_buf.xfer_period = sdtr_period;
8569 sdtr_offset &= ASC_SYN_MAX_OFFSET;
8570 sdtr_buf.req_ack_offset = sdtr_offset;
8571 sdtr_period_index = AscGetSynPeriodIndex(asc_dvc, sdtr_period);
8572 if (sdtr_period_index <= asc_dvc->max_sdtr_index) {
8573 AscMemWordCopyPtrToLram(iop_base, ASCV_MSGOUT_BEG,
8575 sizeof(EXT_MSG) >> 1);
8576 return ((sdtr_period_index << 4) | sdtr_offset);
8578 sdtr_buf.req_ack_offset = 0;
8579 AscMemWordCopyPtrToLram(iop_base, ASCV_MSGOUT_BEG,
8581 sizeof(EXT_MSG) >> 1);
8587 AscCalSDTRData(ASC_DVC_VAR *asc_dvc, uchar sdtr_period, uchar syn_offset)
8590 uchar sdtr_period_ix;
8592 sdtr_period_ix = AscGetSynPeriodIndex(asc_dvc, sdtr_period);
8593 if (sdtr_period_ix > asc_dvc->max_sdtr_index)
8595 byte = (sdtr_period_ix << 4) | (syn_offset & ASC_SYN_MAX_OFFSET);
8599 static int AscSetChipSynRegAtID(PortAddr iop_base, uchar id, uchar sdtr_data)
8601 ASC_SCSI_BIT_ID_TYPE org_id;
8605 AscSetBank(iop_base, 1);
8606 org_id = AscReadChipDvcID(iop_base);
8607 for (i = 0; i <= ASC_MAX_TID; i++) {
8608 if (org_id == (0x01 << i))
8611 org_id = (ASC_SCSI_BIT_ID_TYPE) i;
8612 AscWriteChipDvcID(iop_base, id);
8613 if (AscReadChipDvcID(iop_base) == (0x01 << id)) {
8614 AscSetBank(iop_base, 0);
8615 AscSetChipSyn(iop_base, sdtr_data);
8616 if (AscGetChipSyn(iop_base) != sdtr_data) {
8622 AscSetBank(iop_base, 1);
8623 AscWriteChipDvcID(iop_base, org_id);
8624 AscSetBank(iop_base, 0);
8628 static void AscSetChipSDTR(PortAddr iop_base, uchar sdtr_data, uchar tid_no)
8630 AscSetChipSynRegAtID(iop_base, tid_no, sdtr_data);
8631 AscPutMCodeSDTRDoneAtID(iop_base, tid_no, sdtr_data);
8634 static int AscIsrChipHalted(ASC_DVC_VAR *asc_dvc)
8640 ushort int_halt_code;
8641 ASC_SCSI_BIT_ID_TYPE scsi_busy;
8642 ASC_SCSI_BIT_ID_TYPE target_id;
8649 uchar q_cntl, tid_no;
8653 struct asc_board *boardp;
8655 BUG_ON(!asc_dvc->drv_ptr);
8656 boardp = asc_dvc->drv_ptr;
8658 iop_base = asc_dvc->iop_base;
8659 int_halt_code = AscReadLramWord(iop_base, ASCV_HALTCODE_W);
8661 halt_qp = AscReadLramByte(iop_base, ASCV_CURCDB_B);
8662 halt_q_addr = ASC_QNO_TO_QADDR(halt_qp);
8663 target_ix = AscReadLramByte(iop_base,
8664 (ushort)(halt_q_addr +
8665 (ushort)ASC_SCSIQ_B_TARGET_IX));
8666 q_cntl = AscReadLramByte(iop_base,
8667 (ushort)(halt_q_addr + (ushort)ASC_SCSIQ_B_CNTL));
8668 tid_no = ASC_TIX_TO_TID(target_ix);
8669 target_id = (uchar)ASC_TID_TO_TARGET_ID(tid_no);
8670 if (asc_dvc->pci_fix_asyn_xfer & target_id) {
8671 asyn_sdtr = ASYN_SDTR_DATA_FIX_PCI_REV_AB;
8675 if (int_halt_code == ASC_HALT_DISABLE_ASYN_USE_SYN_FIX) {
8676 if (asc_dvc->pci_fix_asyn_xfer & target_id) {
8677 AscSetChipSDTR(iop_base, 0, tid_no);
8678 boardp->sdtr_data[tid_no] = 0;
8680 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
8682 } else if (int_halt_code == ASC_HALT_ENABLE_ASYN_USE_SYN_FIX) {
8683 if (asc_dvc->pci_fix_asyn_xfer & target_id) {
8684 AscSetChipSDTR(iop_base, asyn_sdtr, tid_no);
8685 boardp->sdtr_data[tid_no] = asyn_sdtr;
8687 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
8689 } else if (int_halt_code == ASC_HALT_EXTMSG_IN) {
8690 AscMemWordCopyPtrFromLram(iop_base,
8693 sizeof(EXT_MSG) >> 1);
8695 if (ext_msg.msg_type == EXTENDED_MESSAGE &&
8696 ext_msg.msg_req == EXTENDED_SDTR &&
8697 ext_msg.msg_len == MS_SDTR_LEN) {
8699 if ((ext_msg.req_ack_offset > ASC_SYN_MAX_OFFSET)) {
8701 sdtr_accept = FALSE;
8702 ext_msg.req_ack_offset = ASC_SYN_MAX_OFFSET;
8704 if ((ext_msg.xfer_period <
8705 asc_dvc->sdtr_period_tbl[asc_dvc->min_sdtr_index])
8706 || (ext_msg.xfer_period >
8707 asc_dvc->sdtr_period_tbl[asc_dvc->
8709 sdtr_accept = FALSE;
8710 ext_msg.xfer_period =
8711 asc_dvc->sdtr_period_tbl[asc_dvc->
8716 AscCalSDTRData(asc_dvc, ext_msg.xfer_period,
8717 ext_msg.req_ack_offset);
8718 if ((sdtr_data == 0xFF)) {
8720 q_cntl |= QC_MSG_OUT;
8721 asc_dvc->init_sdtr &= ~target_id;
8722 asc_dvc->sdtr_done &= ~target_id;
8723 AscSetChipSDTR(iop_base, asyn_sdtr,
8725 boardp->sdtr_data[tid_no] = asyn_sdtr;
8728 if (ext_msg.req_ack_offset == 0) {
8730 q_cntl &= ~QC_MSG_OUT;
8731 asc_dvc->init_sdtr &= ~target_id;
8732 asc_dvc->sdtr_done &= ~target_id;
8733 AscSetChipSDTR(iop_base, asyn_sdtr, tid_no);
8735 if (sdtr_accept && (q_cntl & QC_MSG_OUT)) {
8736 q_cntl &= ~QC_MSG_OUT;
8737 asc_dvc->sdtr_done |= target_id;
8738 asc_dvc->init_sdtr |= target_id;
8739 asc_dvc->pci_fix_asyn_xfer &=
8742 AscCalSDTRData(asc_dvc,
8743 ext_msg.xfer_period,
8746 AscSetChipSDTR(iop_base, sdtr_data,
8748 boardp->sdtr_data[tid_no] = sdtr_data;
8750 q_cntl |= QC_MSG_OUT;
8751 AscMsgOutSDTR(asc_dvc,
8752 ext_msg.xfer_period,
8753 ext_msg.req_ack_offset);
8754 asc_dvc->pci_fix_asyn_xfer &=
8757 AscCalSDTRData(asc_dvc,
8758 ext_msg.xfer_period,
8761 AscSetChipSDTR(iop_base, sdtr_data,
8763 boardp->sdtr_data[tid_no] = sdtr_data;
8764 asc_dvc->sdtr_done |= target_id;
8765 asc_dvc->init_sdtr |= target_id;
8769 AscWriteLramByte(iop_base,
8770 (ushort)(halt_q_addr +
8771 (ushort)ASC_SCSIQ_B_CNTL),
8773 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
8775 } else if (ext_msg.msg_type == EXTENDED_MESSAGE &&
8776 ext_msg.msg_req == EXTENDED_WDTR &&
8777 ext_msg.msg_len == MS_WDTR_LEN) {
8779 ext_msg.wdtr_width = 0;
8780 AscMemWordCopyPtrToLram(iop_base,
8783 sizeof(EXT_MSG) >> 1);
8784 q_cntl |= QC_MSG_OUT;
8785 AscWriteLramByte(iop_base,
8786 (ushort)(halt_q_addr +
8787 (ushort)ASC_SCSIQ_B_CNTL),
8789 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
8793 ext_msg.msg_type = MESSAGE_REJECT;
8794 AscMemWordCopyPtrToLram(iop_base,
8797 sizeof(EXT_MSG) >> 1);
8798 q_cntl |= QC_MSG_OUT;
8799 AscWriteLramByte(iop_base,
8800 (ushort)(halt_q_addr +
8801 (ushort)ASC_SCSIQ_B_CNTL),
8803 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
8806 } else if (int_halt_code == ASC_HALT_CHK_CONDITION) {
8808 q_cntl |= QC_REQ_SENSE;
8810 if ((asc_dvc->init_sdtr & target_id) != 0) {
8812 asc_dvc->sdtr_done &= ~target_id;
8814 sdtr_data = AscGetMCodeInitSDTRAtID(iop_base, tid_no);
8815 q_cntl |= QC_MSG_OUT;
8816 AscMsgOutSDTR(asc_dvc,
8818 sdtr_period_tbl[(sdtr_data >> 4) &
8822 (uchar)(sdtr_data & (uchar)
8823 ASC_SYN_MAX_OFFSET));
8826 AscWriteLramByte(iop_base,
8827 (ushort)(halt_q_addr +
8828 (ushort)ASC_SCSIQ_B_CNTL), q_cntl);
8830 tag_code = AscReadLramByte(iop_base,
8831 (ushort)(halt_q_addr + (ushort)
8832 ASC_SCSIQ_B_TAG_CODE));
8834 if ((asc_dvc->pci_fix_asyn_xfer & target_id)
8835 && !(asc_dvc->pci_fix_asyn_xfer_always & target_id)
8838 tag_code |= (ASC_TAG_FLAG_DISABLE_DISCONNECT
8839 | ASC_TAG_FLAG_DISABLE_ASYN_USE_SYN_FIX);
8842 AscWriteLramByte(iop_base,
8843 (ushort)(halt_q_addr +
8844 (ushort)ASC_SCSIQ_B_TAG_CODE),
8847 q_status = AscReadLramByte(iop_base,
8848 (ushort)(halt_q_addr + (ushort)
8849 ASC_SCSIQ_B_STATUS));
8850 q_status |= (QS_READY | QS_BUSY);
8851 AscWriteLramByte(iop_base,
8852 (ushort)(halt_q_addr +
8853 (ushort)ASC_SCSIQ_B_STATUS),
8856 scsi_busy = AscReadLramByte(iop_base, (ushort)ASCV_SCSIBUSY_B);
8857 scsi_busy &= ~target_id;
8858 AscWriteLramByte(iop_base, (ushort)ASCV_SCSIBUSY_B, scsi_busy);
8860 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
8862 } else if (int_halt_code == ASC_HALT_SDTR_REJECTED) {
8864 AscMemWordCopyPtrFromLram(iop_base,
8867 sizeof(EXT_MSG) >> 1);
8869 if ((out_msg.msg_type == EXTENDED_MESSAGE) &&
8870 (out_msg.msg_len == MS_SDTR_LEN) &&
8871 (out_msg.msg_req == EXTENDED_SDTR)) {
8873 asc_dvc->init_sdtr &= ~target_id;
8874 asc_dvc->sdtr_done &= ~target_id;
8875 AscSetChipSDTR(iop_base, asyn_sdtr, tid_no);
8876 boardp->sdtr_data[tid_no] = asyn_sdtr;
8878 q_cntl &= ~QC_MSG_OUT;
8879 AscWriteLramByte(iop_base,
8880 (ushort)(halt_q_addr +
8881 (ushort)ASC_SCSIQ_B_CNTL), q_cntl);
8882 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
8884 } else if (int_halt_code == ASC_HALT_SS_QUEUE_FULL) {
8886 scsi_status = AscReadLramByte(iop_base,
8887 (ushort)((ushort)halt_q_addr +
8889 ASC_SCSIQ_SCSI_STATUS));
8891 AscReadLramByte(iop_base,
8892 (ushort)((ushort)ASC_QADR_BEG +
8893 (ushort)target_ix));
8894 if ((cur_dvc_qng > 0) && (asc_dvc->cur_dvc_qng[tid_no] > 0)) {
8896 scsi_busy = AscReadLramByte(iop_base,
8897 (ushort)ASCV_SCSIBUSY_B);
8898 scsi_busy |= target_id;
8899 AscWriteLramByte(iop_base,
8900 (ushort)ASCV_SCSIBUSY_B, scsi_busy);
8901 asc_dvc->queue_full_or_busy |= target_id;
8903 if (scsi_status == SAM_STAT_TASK_SET_FULL) {
8904 if (cur_dvc_qng > ASC_MIN_TAGGED_CMD) {
8906 asc_dvc->max_dvc_qng[tid_no] =
8909 AscWriteLramByte(iop_base,
8911 ASCV_MAX_DVC_QNG_BEG
8917 * Set the device queue depth to the
8918 * number of active requests when the
8919 * QUEUE FULL condition was encountered.
8921 boardp->queue_full |= target_id;
8922 boardp->queue_full_cnt[tid_no] =
8927 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
8930 #if CC_VERY_LONG_SG_LIST
8931 else if (int_halt_code == ASC_HALT_HOST_COPY_SG_LIST_TO_RISC) {
8935 uchar first_sg_wk_q_no;
8936 ASC_SCSI_Q *scsiq; /* Ptr to driver request. */
8937 ASC_SG_HEAD *sg_head; /* Ptr to driver SG request. */
8938 ASC_SG_LIST_Q scsi_sg_q; /* Structure written to queue. */
8939 ushort sg_list_dwords;
8940 ushort sg_entry_cnt;
8944 q_no = AscReadLramByte(iop_base, (ushort)ASCV_REQ_SG_LIST_QP);
8945 if (q_no == ASC_QLINK_END)
8948 q_addr = ASC_QNO_TO_QADDR(q_no);
8951 * Convert the request's SRB pointer to a host ASC_SCSI_REQ
8952 * structure pointer using a macro provided by the driver.
8953 * The ASC_SCSI_REQ pointer provides a pointer to the
8954 * host ASC_SG_HEAD structure.
8956 /* Read request's SRB pointer. */
8957 scsiq = (ASC_SCSI_Q *)
8958 ASC_SRB2SCSIQ(ASC_U32_TO_VADDR(AscReadLramDWord(iop_base,
8961 ASC_SCSIQ_D_SRBPTR))));
8964 * Get request's first and working SG queue.
8966 sg_wk_q_no = AscReadLramByte(iop_base,
8968 ASC_SCSIQ_B_SG_WK_QP));
8970 first_sg_wk_q_no = AscReadLramByte(iop_base,
8972 ASC_SCSIQ_B_FIRST_SG_WK_QP));
8975 * Reset request's working SG queue back to the
8978 AscWriteLramByte(iop_base,
8980 (ushort)ASC_SCSIQ_B_SG_WK_QP),
8983 sg_head = scsiq->sg_head;
8986 * Set sg_entry_cnt to the number of SG elements
8987 * that will be completed on this interrupt.
8989 * Note: The allocated SG queues contain ASC_MAX_SG_LIST - 1
8990 * SG elements. The data_cnt and data_addr fields which
8991 * add 1 to the SG element capacity are not used when
8992 * restarting SG handling after a halt.
8994 if (scsiq->remain_sg_entry_cnt > (ASC_MAX_SG_LIST - 1)) {
8995 sg_entry_cnt = ASC_MAX_SG_LIST - 1;
8998 * Keep track of remaining number of SG elements that
8999 * will need to be handled on the next interrupt.
9001 scsiq->remain_sg_entry_cnt -= (ASC_MAX_SG_LIST - 1);
9003 sg_entry_cnt = scsiq->remain_sg_entry_cnt;
9004 scsiq->remain_sg_entry_cnt = 0;
9008 * Copy SG elements into the list of allocated SG queues.
9010 * Last index completed is saved in scsiq->next_sg_index.
9012 next_qp = first_sg_wk_q_no;
9013 q_addr = ASC_QNO_TO_QADDR(next_qp);
9014 scsi_sg_q.sg_head_qp = q_no;
9015 scsi_sg_q.cntl = QCSG_SG_XFER_LIST;
9016 for (i = 0; i < sg_head->queue_cnt; i++) {
9017 scsi_sg_q.seq_no = i + 1;
9018 if (sg_entry_cnt > ASC_SG_LIST_PER_Q) {
9019 sg_list_dwords = (uchar)(ASC_SG_LIST_PER_Q * 2);
9020 sg_entry_cnt -= ASC_SG_LIST_PER_Q;
9022 * After very first SG queue RISC FW uses next
9023 * SG queue first element then checks sg_list_cnt
9024 * against zero and then decrements, so set
9025 * sg_list_cnt 1 less than number of SG elements
9028 scsi_sg_q.sg_list_cnt = ASC_SG_LIST_PER_Q - 1;
9029 scsi_sg_q.sg_cur_list_cnt =
9030 ASC_SG_LIST_PER_Q - 1;
9033 * This is the last SG queue in the list of
9034 * allocated SG queues. If there are more
9035 * SG elements than will fit in the allocated
9036 * queues, then set the QCSG_SG_XFER_MORE flag.
9038 if (scsiq->remain_sg_entry_cnt != 0) {
9039 scsi_sg_q.cntl |= QCSG_SG_XFER_MORE;
9041 scsi_sg_q.cntl |= QCSG_SG_XFER_END;
9043 /* equals sg_entry_cnt * 2 */
9044 sg_list_dwords = sg_entry_cnt << 1;
9045 scsi_sg_q.sg_list_cnt = sg_entry_cnt - 1;
9046 scsi_sg_q.sg_cur_list_cnt = sg_entry_cnt - 1;
9050 scsi_sg_q.q_no = next_qp;
9051 AscMemWordCopyPtrToLram(iop_base,
9052 q_addr + ASC_SCSIQ_SGHD_CPY_BEG,
9053 (uchar *)&scsi_sg_q,
9054 sizeof(ASC_SG_LIST_Q) >> 1);
9056 AscMemDWordCopyPtrToLram(iop_base,
9057 q_addr + ASC_SGQ_LIST_BEG,
9059 sg_list[scsiq->next_sg_index],
9062 scsiq->next_sg_index += ASC_SG_LIST_PER_Q;
9065 * If the just completed SG queue contained the
9066 * last SG element, then no more SG queues need
9069 if (scsi_sg_q.cntl & QCSG_SG_XFER_END) {
9073 next_qp = AscReadLramByte(iop_base,
9076 q_addr = ASC_QNO_TO_QADDR(next_qp);
9080 * Clear the halt condition so the RISC will be restarted
9083 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
9086 #endif /* CC_VERY_LONG_SG_LIST */
9092 * DvcGetQinfo(PortAddr iop_base, ushort s_addr, uchar *inbuf, int words)
9094 * Calling/Exit State:
9098 * Input an ASC_QDONE_INFO structure from the chip
9101 DvcGetQinfo(PortAddr iop_base, ushort s_addr, uchar *inbuf, int words)
9106 AscSetChipLramAddr(iop_base, s_addr);
9107 for (i = 0; i < 2 * words; i += 2) {
9111 word = inpw(iop_base + IOP_RAM_DATA);
9112 inbuf[i] = word & 0xff;
9113 inbuf[i + 1] = (word >> 8) & 0xff;
9115 ASC_DBG_PRT_HEX(2, "DvcGetQinfo", inbuf, 2 * words);
9119 _AscCopyLramScsiDoneQ(PortAddr iop_base,
9121 ASC_QDONE_INFO *scsiq, ASC_DCNT max_dma_count)
9126 DvcGetQinfo(iop_base,
9127 q_addr + ASC_SCSIQ_DONE_INFO_BEG,
9129 (sizeof(ASC_SCSIQ_2) + sizeof(ASC_SCSIQ_3)) / 2);
9131 _val = AscReadLramWord(iop_base,
9132 (ushort)(q_addr + (ushort)ASC_SCSIQ_B_STATUS));
9133 scsiq->q_status = (uchar)_val;
9134 scsiq->q_no = (uchar)(_val >> 8);
9135 _val = AscReadLramWord(iop_base,
9136 (ushort)(q_addr + (ushort)ASC_SCSIQ_B_CNTL));
9137 scsiq->cntl = (uchar)_val;
9138 sg_queue_cnt = (uchar)(_val >> 8);
9139 _val = AscReadLramWord(iop_base,
9141 (ushort)ASC_SCSIQ_B_SENSE_LEN));
9142 scsiq->sense_len = (uchar)_val;
9143 scsiq->extra_bytes = (uchar)(_val >> 8);
9146 * Read high word of remain bytes from alternate location.
9148 scsiq->remain_bytes = (((ADV_DCNT)AscReadLramWord(iop_base,
9151 ASC_SCSIQ_W_ALT_DC1)))
9154 * Read low word of remain bytes from original location.
9156 scsiq->remain_bytes += AscReadLramWord(iop_base,
9157 (ushort)(q_addr + (ushort)
9158 ASC_SCSIQ_DW_REMAIN_XFER_CNT));
9160 scsiq->remain_bytes &= max_dma_count;
9161 return sg_queue_cnt;
9165 * asc_isr_callback() - Second Level Interrupt Handler called by AscISR().
9167 * Interrupt callback function for the Narrow SCSI Asc Library.
9169 static void asc_isr_callback(ASC_DVC_VAR *asc_dvc_varp, ASC_QDONE_INFO *qdonep)
9171 struct asc_board *boardp;
9172 struct scsi_cmnd *scp;
9173 struct Scsi_Host *shost;
9175 ASC_DBG(1, "asc_dvc_varp 0x%p, qdonep 0x%p\n", asc_dvc_varp, qdonep);
9176 ASC_DBG_PRT_ASC_QDONE_INFO(2, qdonep);
9179 * Get the struct scsi_cmnd structure and Scsi_Host structure for the
9180 * command that has been completed.
9182 scp = (struct scsi_cmnd *)ASC_U32_TO_VADDR(qdonep->d2.srb_ptr);
9183 ASC_DBG(1, "scp 0x%p\n", scp);
9186 ASC_PRINT("asc_isr_callback: scp is NULL\n");
9189 ASC_DBG_PRT_CDB(2, scp->cmnd, scp->cmd_len);
9191 shost = scp->device->host;
9192 ASC_STATS(shost, callback);
9193 ASC_DBG(1, "shost 0x%p\n", shost);
9195 boardp = shost_priv(shost);
9196 BUG_ON(asc_dvc_varp != &boardp->dvc_var.asc_dvc_var);
9199 * 'qdonep' contains the command's ending status.
9201 switch (qdonep->d3.done_stat) {
9203 ASC_DBG(2, "QD_NO_ERROR\n");
9207 * Check for an underrun condition.
9209 * If there was no error and an underrun condition, then
9210 * return the number of underrun bytes.
9212 if (scp->request_bufflen != 0 && qdonep->remain_bytes != 0 &&
9213 qdonep->remain_bytes <= scp->request_bufflen) {
9214 ASC_DBG(1, "underrun condition %u bytes\n",
9215 (unsigned)qdonep->remain_bytes);
9216 scp->resid = qdonep->remain_bytes;
9221 ASC_DBG(2, "QD_WITH_ERROR\n");
9222 switch (qdonep->d3.host_stat) {
9223 case QHSTA_NO_ERROR:
9224 if (qdonep->d3.scsi_stat == SAM_STAT_CHECK_CONDITION) {
9225 ASC_DBG(2, "SAM_STAT_CHECK_CONDITION\n");
9226 ASC_DBG_PRT_SENSE(2, scp->sense_buffer,
9227 sizeof(scp->sense_buffer));
9229 * Note: The 'status_byte()' macro used by
9230 * target drivers defined in scsi.h shifts the
9231 * status byte returned by host drivers right
9232 * by 1 bit. This is why target drivers also
9233 * use right shifted status byte definitions.
9234 * For instance target drivers use
9235 * CHECK_CONDITION, defined to 0x1, instead of
9236 * the SCSI defined check condition value of
9237 * 0x2. Host drivers are supposed to return
9238 * the status byte as it is defined by SCSI.
9240 scp->result = DRIVER_BYTE(DRIVER_SENSE) |
9241 STATUS_BYTE(qdonep->d3.scsi_stat);
9243 scp->result = STATUS_BYTE(qdonep->d3.scsi_stat);
9248 /* QHSTA error occurred */
9249 ASC_DBG(1, "host_stat 0x%x\n", qdonep->d3.host_stat);
9250 scp->result = HOST_BYTE(DID_BAD_TARGET);
9255 case QD_ABORTED_BY_HOST:
9256 ASC_DBG(1, "QD_ABORTED_BY_HOST\n");
9258 HOST_BYTE(DID_ABORT) | MSG_BYTE(qdonep->d3.
9260 STATUS_BYTE(qdonep->d3.scsi_stat);
9264 ASC_DBG(1, "done_stat 0x%x\n", qdonep->d3.done_stat);
9266 HOST_BYTE(DID_ERROR) | MSG_BYTE(qdonep->d3.
9268 STATUS_BYTE(qdonep->d3.scsi_stat);
9273 * If the 'init_tidmask' bit isn't already set for the target and the
9274 * current request finished normally, then set the bit for the target
9275 * to indicate that a device is present.
9277 if ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(scp->device->id)) == 0 &&
9278 qdonep->d3.done_stat == QD_NO_ERROR &&
9279 qdonep->d3.host_stat == QHSTA_NO_ERROR) {
9280 boardp->init_tidmask |= ADV_TID_TO_TIDMASK(scp->device->id);
9286 static int AscIsrQDone(ASC_DVC_VAR *asc_dvc)
9295 ASC_SCSI_BIT_ID_TYPE scsi_busy;
9296 ASC_SCSI_BIT_ID_TYPE target_id;
9300 uchar cur_target_qng;
9301 ASC_QDONE_INFO scsiq_buf;
9302 ASC_QDONE_INFO *scsiq;
9305 iop_base = asc_dvc->iop_base;
9307 scsiq = (ASC_QDONE_INFO *)&scsiq_buf;
9308 done_q_tail = (uchar)AscGetVarDoneQTail(iop_base);
9309 q_addr = ASC_QNO_TO_QADDR(done_q_tail);
9310 next_qp = AscReadLramByte(iop_base,
9311 (ushort)(q_addr + (ushort)ASC_SCSIQ_B_FWD));
9312 if (next_qp != ASC_QLINK_END) {
9313 AscPutVarDoneQTail(iop_base, next_qp);
9314 q_addr = ASC_QNO_TO_QADDR(next_qp);
9315 sg_queue_cnt = _AscCopyLramScsiDoneQ(iop_base, q_addr, scsiq,
9316 asc_dvc->max_dma_count);
9317 AscWriteLramByte(iop_base,
9319 (ushort)ASC_SCSIQ_B_STATUS),
9321 q_status & (uchar)~(QS_READY |
9323 tid_no = ASC_TIX_TO_TID(scsiq->d2.target_ix);
9324 target_id = ASC_TIX_TO_TARGET_ID(scsiq->d2.target_ix);
9325 if ((scsiq->cntl & QC_SG_HEAD) != 0) {
9327 sg_list_qp = next_qp;
9328 for (q_cnt = 0; q_cnt < sg_queue_cnt; q_cnt++) {
9329 sg_list_qp = AscReadLramByte(iop_base,
9333 sg_q_addr = ASC_QNO_TO_QADDR(sg_list_qp);
9334 if (sg_list_qp == ASC_QLINK_END) {
9335 AscSetLibErrorCode(asc_dvc,
9336 ASCQ_ERR_SG_Q_LINKS);
9337 scsiq->d3.done_stat = QD_WITH_ERROR;
9338 scsiq->d3.host_stat =
9339 QHSTA_D_QDONE_SG_LIST_CORRUPTED;
9340 goto FATAL_ERR_QDONE;
9342 AscWriteLramByte(iop_base,
9343 (ushort)(sg_q_addr + (ushort)
9344 ASC_SCSIQ_B_STATUS),
9347 n_q_used = sg_queue_cnt + 1;
9348 AscPutVarDoneQTail(iop_base, sg_list_qp);
9350 if (asc_dvc->queue_full_or_busy & target_id) {
9351 cur_target_qng = AscReadLramByte(iop_base,
9357 if (cur_target_qng < asc_dvc->max_dvc_qng[tid_no]) {
9358 scsi_busy = AscReadLramByte(iop_base, (ushort)
9360 scsi_busy &= ~target_id;
9361 AscWriteLramByte(iop_base,
9362 (ushort)ASCV_SCSIBUSY_B,
9364 asc_dvc->queue_full_or_busy &= ~target_id;
9367 if (asc_dvc->cur_total_qng >= n_q_used) {
9368 asc_dvc->cur_total_qng -= n_q_used;
9369 if (asc_dvc->cur_dvc_qng[tid_no] != 0) {
9370 asc_dvc->cur_dvc_qng[tid_no]--;
9373 AscSetLibErrorCode(asc_dvc, ASCQ_ERR_CUR_QNG);
9374 scsiq->d3.done_stat = QD_WITH_ERROR;
9375 goto FATAL_ERR_QDONE;
9377 if ((scsiq->d2.srb_ptr == 0UL) ||
9378 ((scsiq->q_status & QS_ABORTED) != 0)) {
9380 } else if (scsiq->q_status == QS_DONE) {
9381 false_overrun = FALSE;
9382 if (scsiq->extra_bytes != 0) {
9383 scsiq->remain_bytes +=
9384 (ADV_DCNT)scsiq->extra_bytes;
9386 if (scsiq->d3.done_stat == QD_WITH_ERROR) {
9387 if (scsiq->d3.host_stat ==
9388 QHSTA_M_DATA_OVER_RUN) {
9390 cntl & (QC_DATA_IN | QC_DATA_OUT))
9392 scsiq->d3.done_stat =
9394 scsiq->d3.host_stat =
9396 } else if (false_overrun) {
9397 scsiq->d3.done_stat =
9399 scsiq->d3.host_stat =
9402 } else if (scsiq->d3.host_stat ==
9403 QHSTA_M_HUNG_REQ_SCSI_BUS_RESET) {
9404 AscStopChip(iop_base);
9405 AscSetChipControl(iop_base,
9406 (uchar)(CC_SCSI_RESET
9409 AscSetChipControl(iop_base, CC_HALT);
9410 AscSetChipStatus(iop_base,
9411 CIW_CLR_SCSI_RESET_INT);
9412 AscSetChipStatus(iop_base, 0);
9413 AscSetChipControl(iop_base, 0);
9416 if ((scsiq->cntl & QC_NO_CALLBACK) == 0) {
9417 asc_isr_callback(asc_dvc, scsiq);
9419 if ((AscReadLramByte(iop_base,
9420 (ushort)(q_addr + (ushort)
9423 asc_dvc->unit_not_ready &= ~target_id;
9424 if (scsiq->d3.done_stat != QD_NO_ERROR) {
9425 asc_dvc->start_motor &=
9432 AscSetLibErrorCode(asc_dvc, ASCQ_ERR_Q_STATUS);
9434 if ((scsiq->cntl & QC_NO_CALLBACK) == 0) {
9435 asc_isr_callback(asc_dvc, scsiq);
9443 static int AscISR(ASC_DVC_VAR *asc_dvc)
9445 ASC_CS_TYPE chipstat;
9447 ushort saved_ram_addr;
9449 uchar saved_ctrl_reg;
9454 iop_base = asc_dvc->iop_base;
9455 int_pending = FALSE;
9457 if (AscIsIntPending(iop_base) == 0)
9460 if ((asc_dvc->init_state & ASC_INIT_STATE_END_LOAD_MC) == 0) {
9463 if (asc_dvc->in_critical_cnt != 0) {
9464 AscSetLibErrorCode(asc_dvc, ASCQ_ERR_ISR_ON_CRITICAL);
9467 if (asc_dvc->is_in_int) {
9468 AscSetLibErrorCode(asc_dvc, ASCQ_ERR_ISR_RE_ENTRY);
9471 asc_dvc->is_in_int = TRUE;
9472 ctrl_reg = AscGetChipControl(iop_base);
9473 saved_ctrl_reg = ctrl_reg & (~(CC_SCSI_RESET | CC_CHIP_RESET |
9474 CC_SINGLE_STEP | CC_DIAG | CC_TEST));
9475 chipstat = AscGetChipStatus(iop_base);
9476 if (chipstat & CSW_SCSI_RESET_LATCH) {
9477 if (!(asc_dvc->bus_type & (ASC_IS_VL | ASC_IS_EISA))) {
9480 asc_dvc->sdtr_done = 0;
9481 saved_ctrl_reg &= (uchar)(~CC_HALT);
9482 while ((AscGetChipStatus(iop_base) &
9483 CSW_SCSI_RESET_ACTIVE) && (i-- > 0)) {
9486 AscSetChipControl(iop_base, (CC_CHIP_RESET | CC_HALT));
9487 AscSetChipControl(iop_base, CC_HALT);
9488 AscSetChipStatus(iop_base, CIW_CLR_SCSI_RESET_INT);
9489 AscSetChipStatus(iop_base, 0);
9490 chipstat = AscGetChipStatus(iop_base);
9493 saved_ram_addr = AscGetChipLramAddr(iop_base);
9494 host_flag = AscReadLramByte(iop_base,
9496 (uchar)(~ASC_HOST_FLAG_IN_ISR);
9497 AscWriteLramByte(iop_base, ASCV_HOST_FLAG_B,
9498 (uchar)(host_flag | (uchar)ASC_HOST_FLAG_IN_ISR));
9499 if ((chipstat & CSW_INT_PENDING) || (int_pending)) {
9500 AscAckInterrupt(iop_base);
9502 if ((chipstat & CSW_HALTED) && (ctrl_reg & CC_SINGLE_STEP)) {
9503 if (AscIsrChipHalted(asc_dvc) == ERR) {
9504 goto ISR_REPORT_QDONE_FATAL_ERROR;
9506 saved_ctrl_reg &= (uchar)(~CC_HALT);
9509 ISR_REPORT_QDONE_FATAL_ERROR:
9510 if ((asc_dvc->dvc_cntl & ASC_CNTL_INT_MULTI_Q) != 0) {
9512 AscIsrQDone(asc_dvc)) & 0x01) != 0) {
9517 AscIsrQDone(asc_dvc)) == 1) {
9520 } while (status == 0x11);
9522 if ((status & 0x80) != 0)
9526 AscWriteLramByte(iop_base, ASCV_HOST_FLAG_B, host_flag);
9527 AscSetChipLramAddr(iop_base, saved_ram_addr);
9528 AscSetChipControl(iop_base, saved_ctrl_reg);
9529 asc_dvc->is_in_int = FALSE;
9536 * Reset the bus associated with the command 'scp'.
9538 * This function runs its own thread. Interrupts must be blocked but
9539 * sleeping is allowed and no locking other than for host structures is
9540 * required. Returns SUCCESS or FAILED.
9542 static int advansys_reset(struct scsi_cmnd *scp)
9544 struct Scsi_Host *shost = scp->device->host;
9545 struct asc_board *boardp = shost_priv(shost);
9546 unsigned long flags;
9550 ASC_DBG(1, "0x%p\n", scp);
9552 ASC_STATS(shost, reset);
9554 scmd_printk(KERN_INFO, scp, "SCSI bus reset started...\n");
9556 if (ASC_NARROW_BOARD(boardp)) {
9557 ASC_DVC_VAR *asc_dvc = &boardp->dvc_var.asc_dvc_var;
9559 /* Reset the chip and SCSI bus. */
9560 ASC_DBG(1, "before AscInitAsc1000Driver()\n");
9561 status = AscInitAsc1000Driver(asc_dvc);
9563 /* Refer to ASC_IERR_* defintions for meaning of 'err_code'. */
9564 if (asc_dvc->err_code) {
9565 scmd_printk(KERN_INFO, scp, "SCSI bus reset error: "
9566 "0x%x\n", asc_dvc->err_code);
9568 } else if (status) {
9569 scmd_printk(KERN_INFO, scp, "SCSI bus reset warning: "
9572 scmd_printk(KERN_INFO, scp, "SCSI bus reset "
9576 ASC_DBG(1, "after AscInitAsc1000Driver()\n");
9577 spin_lock_irqsave(shost->host_lock, flags);
9580 * If the suggest reset bus flags are set, then reset the bus.
9581 * Otherwise only reset the device.
9583 ADV_DVC_VAR *adv_dvc = &boardp->dvc_var.adv_dvc_var;
9586 * Reset the target's SCSI bus.
9588 ASC_DBG(1, "before AdvResetChipAndSB()\n");
9589 switch (AdvResetChipAndSB(adv_dvc)) {
9591 scmd_printk(KERN_INFO, scp, "SCSI bus reset "
9596 scmd_printk(KERN_INFO, scp, "SCSI bus reset error\n");
9600 spin_lock_irqsave(shost->host_lock, flags);
9604 /* Save the time of the most recently completed reset. */
9605 boardp->last_reset = jiffies;
9606 spin_unlock_irqrestore(shost->host_lock, flags);
9608 ASC_DBG(1, "ret %d\n", ret);
9614 * advansys_biosparam()
9616 * Translate disk drive geometry if the "BIOS greater than 1 GB"
9617 * support is enabled for a drive.
9619 * ip (information pointer) is an int array with the following definition:
9625 advansys_biosparam(struct scsi_device *sdev, struct block_device *bdev,
9626 sector_t capacity, int ip[])
9628 struct asc_board *boardp = shost_priv(sdev->host);
9630 ASC_DBG(1, "begin\n");
9631 ASC_STATS(sdev->host, biosparam);
9632 if (ASC_NARROW_BOARD(boardp)) {
9633 if ((boardp->dvc_var.asc_dvc_var.dvc_cntl &
9634 ASC_CNTL_BIOS_GT_1GB) && capacity > 0x200000) {
9642 if ((boardp->dvc_var.adv_dvc_var.bios_ctrl &
9643 BIOS_CTRL_EXTENDED_XLAT) && capacity > 0x200000) {
9651 ip[2] = (unsigned long)capacity / (ip[0] * ip[1]);
9652 ASC_DBG(1, "end\n");
9657 * First-level interrupt handler.
9659 * 'dev_id' is a pointer to the interrupting adapter's Scsi_Host.
9661 static irqreturn_t advansys_interrupt(int irq, void *dev_id)
9663 struct Scsi_Host *shost = dev_id;
9664 struct asc_board *boardp = shost_priv(shost);
9665 irqreturn_t result = IRQ_NONE;
9667 ASC_DBG(2, "boardp 0x%p\n", boardp);
9668 spin_lock(shost->host_lock);
9669 if (ASC_NARROW_BOARD(boardp)) {
9670 if (AscIsIntPending(shost->io_port)) {
9671 result = IRQ_HANDLED;
9672 ASC_STATS(shost, interrupt);
9673 ASC_DBG(1, "before AscISR()\n");
9674 AscISR(&boardp->dvc_var.asc_dvc_var);
9677 ASC_DBG(1, "before AdvISR()\n");
9678 if (AdvISR(&boardp->dvc_var.adv_dvc_var)) {
9679 result = IRQ_HANDLED;
9680 ASC_STATS(shost, interrupt);
9683 spin_unlock(shost->host_lock);
9685 ASC_DBG(1, "end\n");
9689 static int AscHostReqRiscHalt(PortAddr iop_base)
9693 uchar saved_stop_code;
9695 if (AscIsChipHalted(iop_base))
9697 saved_stop_code = AscReadLramByte(iop_base, ASCV_STOP_CODE_B);
9698 AscWriteLramByte(iop_base, ASCV_STOP_CODE_B,
9699 ASC_STOP_HOST_REQ_RISC_HALT | ASC_STOP_REQ_RISC_STOP);
9701 if (AscIsChipHalted(iop_base)) {
9706 } while (count++ < 20);
9707 AscWriteLramByte(iop_base, ASCV_STOP_CODE_B, saved_stop_code);
9712 AscSetRunChipSynRegAtID(PortAddr iop_base, uchar tid_no, uchar sdtr_data)
9716 if (AscHostReqRiscHalt(iop_base)) {
9717 sta = AscSetChipSynRegAtID(iop_base, tid_no, sdtr_data);
9718 AscStartChip(iop_base);
9723 static void AscAsyncFix(ASC_DVC_VAR *asc_dvc, struct scsi_device *sdev)
9725 char type = sdev->type;
9726 ASC_SCSI_BIT_ID_TYPE tid_bits = 1 << sdev->id;
9728 if (!(asc_dvc->bug_fix_cntl & ASC_BUG_FIX_ASYN_USE_SYN))
9730 if (asc_dvc->init_sdtr & tid_bits)
9733 if ((type == TYPE_ROM) && (strncmp(sdev->vendor, "HP ", 3) == 0))
9734 asc_dvc->pci_fix_asyn_xfer_always |= tid_bits;
9736 asc_dvc->pci_fix_asyn_xfer |= tid_bits;
9737 if ((type == TYPE_PROCESSOR) || (type == TYPE_SCANNER) ||
9738 (type == TYPE_ROM) || (type == TYPE_TAPE))
9739 asc_dvc->pci_fix_asyn_xfer &= ~tid_bits;
9741 if (asc_dvc->pci_fix_asyn_xfer & tid_bits)
9742 AscSetRunChipSynRegAtID(asc_dvc->iop_base, sdev->id,
9743 ASYN_SDTR_DATA_FIX_PCI_REV_AB);
9747 advansys_narrow_slave_configure(struct scsi_device *sdev, ASC_DVC_VAR *asc_dvc)
9749 ASC_SCSI_BIT_ID_TYPE tid_bit = 1 << sdev->id;
9750 ASC_SCSI_BIT_ID_TYPE orig_use_tagged_qng = asc_dvc->use_tagged_qng;
9752 if (sdev->lun == 0) {
9753 ASC_SCSI_BIT_ID_TYPE orig_init_sdtr = asc_dvc->init_sdtr;
9754 if ((asc_dvc->cfg->sdtr_enable & tid_bit) && sdev->sdtr) {
9755 asc_dvc->init_sdtr |= tid_bit;
9757 asc_dvc->init_sdtr &= ~tid_bit;
9760 if (orig_init_sdtr != asc_dvc->init_sdtr)
9761 AscAsyncFix(asc_dvc, sdev);
9764 if (sdev->tagged_supported) {
9765 if (asc_dvc->cfg->cmd_qng_enabled & tid_bit) {
9766 if (sdev->lun == 0) {
9767 asc_dvc->cfg->can_tagged_qng |= tid_bit;
9768 asc_dvc->use_tagged_qng |= tid_bit;
9770 scsi_adjust_queue_depth(sdev, MSG_ORDERED_TAG,
9771 asc_dvc->max_dvc_qng[sdev->id]);
9774 if (sdev->lun == 0) {
9775 asc_dvc->cfg->can_tagged_qng &= ~tid_bit;
9776 asc_dvc->use_tagged_qng &= ~tid_bit;
9778 scsi_adjust_queue_depth(sdev, 0, sdev->host->cmd_per_lun);
9781 if ((sdev->lun == 0) &&
9782 (orig_use_tagged_qng != asc_dvc->use_tagged_qng)) {
9783 AscWriteLramByte(asc_dvc->iop_base, ASCV_DISC_ENABLE_B,
9784 asc_dvc->cfg->disc_enable);
9785 AscWriteLramByte(asc_dvc->iop_base, ASCV_USE_TAGGED_QNG_B,
9786 asc_dvc->use_tagged_qng);
9787 AscWriteLramByte(asc_dvc->iop_base, ASCV_CAN_TAGGED_QNG_B,
9788 asc_dvc->cfg->can_tagged_qng);
9790 asc_dvc->max_dvc_qng[sdev->id] =
9791 asc_dvc->cfg->max_tag_qng[sdev->id];
9792 AscWriteLramByte(asc_dvc->iop_base,
9793 (ushort)(ASCV_MAX_DVC_QNG_BEG + sdev->id),
9794 asc_dvc->max_dvc_qng[sdev->id]);
9801 * If the EEPROM enabled WDTR for the device and the device supports wide
9802 * bus (16 bit) transfers, then turn on the device's 'wdtr_able' bit and
9803 * write the new value to the microcode.
9806 advansys_wide_enable_wdtr(AdvPortAddr iop_base, unsigned short tidmask)
9808 unsigned short cfg_word;
9809 AdvReadWordLram(iop_base, ASC_MC_WDTR_ABLE, cfg_word);
9810 if ((cfg_word & tidmask) != 0)
9813 cfg_word |= tidmask;
9814 AdvWriteWordLram(iop_base, ASC_MC_WDTR_ABLE, cfg_word);
9817 * Clear the microcode SDTR and WDTR negotiation done indicators for
9818 * the target to cause it to negotiate with the new setting set above.
9819 * WDTR when accepted causes the target to enter asynchronous mode, so
9820 * SDTR must be negotiated.
9822 AdvReadWordLram(iop_base, ASC_MC_SDTR_DONE, cfg_word);
9823 cfg_word &= ~tidmask;
9824 AdvWriteWordLram(iop_base, ASC_MC_SDTR_DONE, cfg_word);
9825 AdvReadWordLram(iop_base, ASC_MC_WDTR_DONE, cfg_word);
9826 cfg_word &= ~tidmask;
9827 AdvWriteWordLram(iop_base, ASC_MC_WDTR_DONE, cfg_word);
9831 * Synchronous Transfers
9833 * If the EEPROM enabled SDTR for the device and the device
9834 * supports synchronous transfers, then turn on the device's
9835 * 'sdtr_able' bit. Write the new value to the microcode.
9838 advansys_wide_enable_sdtr(AdvPortAddr iop_base, unsigned short tidmask)
9840 unsigned short cfg_word;
9841 AdvReadWordLram(iop_base, ASC_MC_SDTR_ABLE, cfg_word);
9842 if ((cfg_word & tidmask) != 0)
9845 cfg_word |= tidmask;
9846 AdvWriteWordLram(iop_base, ASC_MC_SDTR_ABLE, cfg_word);
9849 * Clear the microcode "SDTR negotiation" done indicator for the
9850 * target to cause it to negotiate with the new setting set above.
9852 AdvReadWordLram(iop_base, ASC_MC_SDTR_DONE, cfg_word);
9853 cfg_word &= ~tidmask;
9854 AdvWriteWordLram(iop_base, ASC_MC_SDTR_DONE, cfg_word);
9858 * PPR (Parallel Protocol Request) Capable
9860 * If the device supports DT mode, then it must be PPR capable.
9861 * The PPR message will be used in place of the SDTR and WDTR
9862 * messages to negotiate synchronous speed and offset, transfer
9863 * width, and protocol options.
9865 static void advansys_wide_enable_ppr(ADV_DVC_VAR *adv_dvc,
9866 AdvPortAddr iop_base, unsigned short tidmask)
9868 AdvReadWordLram(iop_base, ASC_MC_PPR_ABLE, adv_dvc->ppr_able);
9869 adv_dvc->ppr_able |= tidmask;
9870 AdvWriteWordLram(iop_base, ASC_MC_PPR_ABLE, adv_dvc->ppr_able);
9874 advansys_wide_slave_configure(struct scsi_device *sdev, ADV_DVC_VAR *adv_dvc)
9876 AdvPortAddr iop_base = adv_dvc->iop_base;
9877 unsigned short tidmask = 1 << sdev->id;
9879 if (sdev->lun == 0) {
9881 * Handle WDTR, SDTR, and Tag Queuing. If the feature
9882 * is enabled in the EEPROM and the device supports the
9883 * feature, then enable it in the microcode.
9886 if ((adv_dvc->wdtr_able & tidmask) && sdev->wdtr)
9887 advansys_wide_enable_wdtr(iop_base, tidmask);
9888 if ((adv_dvc->sdtr_able & tidmask) && sdev->sdtr)
9889 advansys_wide_enable_sdtr(iop_base, tidmask);
9890 if (adv_dvc->chip_type == ADV_CHIP_ASC38C1600 && sdev->ppr)
9891 advansys_wide_enable_ppr(adv_dvc, iop_base, tidmask);
9894 * Tag Queuing is disabled for the BIOS which runs in polled
9895 * mode and would see no benefit from Tag Queuing. Also by
9896 * disabling Tag Queuing in the BIOS devices with Tag Queuing
9897 * bugs will at least work with the BIOS.
9899 if ((adv_dvc->tagqng_able & tidmask) &&
9900 sdev->tagged_supported) {
9901 unsigned short cfg_word;
9902 AdvReadWordLram(iop_base, ASC_MC_TAGQNG_ABLE, cfg_word);
9903 cfg_word |= tidmask;
9904 AdvWriteWordLram(iop_base, ASC_MC_TAGQNG_ABLE,
9906 AdvWriteByteLram(iop_base,
9907 ASC_MC_NUMBER_OF_MAX_CMD + sdev->id,
9908 adv_dvc->max_dvc_qng);
9912 if ((adv_dvc->tagqng_able & tidmask) && sdev->tagged_supported) {
9913 scsi_adjust_queue_depth(sdev, MSG_ORDERED_TAG,
9914 adv_dvc->max_dvc_qng);
9916 scsi_adjust_queue_depth(sdev, 0, sdev->host->cmd_per_lun);
9921 * Set the number of commands to queue per device for the
9922 * specified host adapter.
9924 static int advansys_slave_configure(struct scsi_device *sdev)
9926 struct asc_board *boardp = shost_priv(sdev->host);
9928 if (ASC_NARROW_BOARD(boardp))
9929 advansys_narrow_slave_configure(sdev,
9930 &boardp->dvc_var.asc_dvc_var);
9932 advansys_wide_slave_configure(sdev,
9933 &boardp->dvc_var.adv_dvc_var);
9938 static int asc_build_req(struct asc_board *boardp, struct scsi_cmnd *scp,
9939 struct asc_scsi_q *asc_scsi_q)
9941 memset(asc_scsi_q, 0, sizeof(*asc_scsi_q));
9944 * Point the ASC_SCSI_Q to the 'struct scsi_cmnd'.
9946 asc_scsi_q->q2.srb_ptr = ASC_VADDR_TO_U32(scp);
9949 * Build the ASC_SCSI_Q request.
9951 asc_scsi_q->cdbptr = &scp->cmnd[0];
9952 asc_scsi_q->q2.cdb_len = scp->cmd_len;
9953 asc_scsi_q->q1.target_id = ASC_TID_TO_TARGET_ID(scp->device->id);
9954 asc_scsi_q->q1.target_lun = scp->device->lun;
9955 asc_scsi_q->q2.target_ix =
9956 ASC_TIDLUN_TO_IX(scp->device->id, scp->device->lun);
9957 asc_scsi_q->q1.sense_addr =
9958 cpu_to_le32(virt_to_bus(&scp->sense_buffer[0]));
9959 asc_scsi_q->q1.sense_len = sizeof(scp->sense_buffer);
9962 * If there are any outstanding requests for the current target,
9963 * then every 255th request send an ORDERED request. This heuristic
9964 * tries to retain the benefit of request sorting while preventing
9965 * request starvation. 255 is the max number of tags or pending commands
9966 * a device may have outstanding.
9968 * The request count is incremented below for every successfully
9972 if ((boardp->dvc_var.asc_dvc_var.cur_dvc_qng[scp->device->id] > 0) &&
9973 (boardp->reqcnt[scp->device->id] % 255) == 0) {
9974 asc_scsi_q->q2.tag_code = MSG_ORDERED_TAG;
9976 asc_scsi_q->q2.tag_code = MSG_SIMPLE_TAG;
9980 * Build ASC_SCSI_Q for a contiguous buffer or a scatter-gather
9983 if (scp->use_sg == 0) {
9985 * CDB request of single contiguous buffer.
9987 ASC_STATS(scp->device->host, cont_cnt);
9988 scp->SCp.dma_handle = scp->request_bufflen ?
9989 dma_map_single(boardp->dev, scp->request_buffer,
9990 scp->request_bufflen,
9991 scp->sc_data_direction) : 0;
9992 asc_scsi_q->q1.data_addr = cpu_to_le32(scp->SCp.dma_handle);
9993 asc_scsi_q->q1.data_cnt = cpu_to_le32(scp->request_bufflen);
9994 ASC_STATS_ADD(scp->device->host, cont_xfer,
9995 ASC_CEILING(scp->request_bufflen, 512));
9996 asc_scsi_q->q1.sg_queue_cnt = 0;
9997 asc_scsi_q->sg_head = NULL;
10000 * CDB scatter-gather request list.
10004 struct scatterlist *slp;
10005 struct asc_sg_head *asc_sg_head;
10007 slp = (struct scatterlist *)scp->request_buffer;
10008 use_sg = dma_map_sg(boardp->dev, slp, scp->use_sg,
10009 scp->sc_data_direction);
10011 if (use_sg > scp->device->host->sg_tablesize) {
10012 scmd_printk(KERN_ERR, scp, "use_sg %d > "
10013 "sg_tablesize %d\n", use_sg,
10014 scp->device->host->sg_tablesize);
10015 dma_unmap_sg(boardp->dev, slp, scp->use_sg,
10016 scp->sc_data_direction);
10017 scp->result = HOST_BYTE(DID_ERROR);
10021 ASC_STATS(scp->device->host, sg_cnt);
10023 asc_sg_head = kzalloc(sizeof(asc_scsi_q->sg_head) +
10024 use_sg * sizeof(struct asc_sg_list), GFP_ATOMIC);
10025 if (!asc_sg_head) {
10026 dma_unmap_sg(boardp->dev, slp, scp->use_sg,
10027 scp->sc_data_direction);
10028 scp->result = HOST_BYTE(DID_SOFT_ERROR);
10032 asc_scsi_q->q1.cntl |= QC_SG_HEAD;
10033 asc_scsi_q->sg_head = asc_sg_head;
10034 asc_scsi_q->q1.data_cnt = 0;
10035 asc_scsi_q->q1.data_addr = 0;
10036 /* This is a byte value, otherwise it would need to be swapped. */
10037 asc_sg_head->entry_cnt = asc_scsi_q->q1.sg_queue_cnt = use_sg;
10038 ASC_STATS_ADD(scp->device->host, sg_elem,
10039 asc_sg_head->entry_cnt);
10042 * Convert scatter-gather list into ASC_SG_HEAD list.
10044 for (sgcnt = 0; sgcnt < use_sg; sgcnt++, slp++) {
10045 asc_sg_head->sg_list[sgcnt].addr =
10046 cpu_to_le32(sg_dma_address(slp));
10047 asc_sg_head->sg_list[sgcnt].bytes =
10048 cpu_to_le32(sg_dma_len(slp));
10049 ASC_STATS_ADD(scp->device->host, sg_xfer,
10050 ASC_CEILING(sg_dma_len(slp), 512));
10054 ASC_DBG_PRT_ASC_SCSI_Q(2, asc_scsi_q);
10055 ASC_DBG_PRT_CDB(1, scp->cmnd, scp->cmd_len);
10057 return ASC_NOERROR;
10061 * Build scatter-gather list for Adv Library (Wide Board).
10063 * Additional ADV_SG_BLOCK structures will need to be allocated
10064 * if the total number of scatter-gather elements exceeds
10065 * NO_OF_SG_PER_BLOCK (15). The ADV_SG_BLOCK structures are
10066 * assumed to be physically contiguous.
10069 * ADV_SUCCESS(1) - SG List successfully created
10070 * ADV_ERROR(-1) - SG List creation failed
10073 adv_get_sglist(struct asc_board *boardp, adv_req_t *reqp, struct scsi_cmnd *scp,
10076 adv_sgblk_t *sgblkp;
10077 ADV_SCSI_REQ_Q *scsiqp;
10078 struct scatterlist *slp;
10080 ADV_SG_BLOCK *sg_block, *prev_sg_block;
10081 ADV_PADDR sg_block_paddr;
10084 scsiqp = (ADV_SCSI_REQ_Q *)ADV_32BALIGN(&reqp->scsi_req_q);
10085 slp = (struct scatterlist *)scp->request_buffer;
10086 sg_elem_cnt = use_sg;
10087 prev_sg_block = NULL;
10088 reqp->sgblkp = NULL;
10092 * Allocate a 'adv_sgblk_t' structure from the board free
10093 * list. One 'adv_sgblk_t' structure holds NO_OF_SG_PER_BLOCK
10094 * (15) scatter-gather elements.
10096 if ((sgblkp = boardp->adv_sgblkp) == NULL) {
10097 ASC_DBG(1, "no free adv_sgblk_t\n");
10098 ASC_STATS(scp->device->host, adv_build_nosg);
10101 * Allocation failed. Free 'adv_sgblk_t' structures
10102 * already allocated for the request.
10104 while ((sgblkp = reqp->sgblkp) != NULL) {
10105 /* Remove 'sgblkp' from the request list. */
10106 reqp->sgblkp = sgblkp->next_sgblkp;
10108 /* Add 'sgblkp' to the board free list. */
10109 sgblkp->next_sgblkp = boardp->adv_sgblkp;
10110 boardp->adv_sgblkp = sgblkp;
10115 /* Complete 'adv_sgblk_t' board allocation. */
10116 boardp->adv_sgblkp = sgblkp->next_sgblkp;
10117 sgblkp->next_sgblkp = NULL;
10120 * Get 8 byte aligned virtual and physical addresses
10121 * for the allocated ADV_SG_BLOCK structure.
10123 sg_block = (ADV_SG_BLOCK *)ADV_8BALIGN(&sgblkp->sg_block);
10124 sg_block_paddr = virt_to_bus(sg_block);
10127 * Check if this is the first 'adv_sgblk_t' for the
10130 if (reqp->sgblkp == NULL) {
10131 /* Request's first scatter-gather block. */
10132 reqp->sgblkp = sgblkp;
10135 * Set ADV_SCSI_REQ_T ADV_SG_BLOCK virtual and physical
10136 * address pointers.
10138 scsiqp->sg_list_ptr = sg_block;
10139 scsiqp->sg_real_addr = cpu_to_le32(sg_block_paddr);
10141 /* Request's second or later scatter-gather block. */
10142 sgblkp->next_sgblkp = reqp->sgblkp;
10143 reqp->sgblkp = sgblkp;
10146 * Point the previous ADV_SG_BLOCK structure to
10147 * the newly allocated ADV_SG_BLOCK structure.
10149 prev_sg_block->sg_ptr = cpu_to_le32(sg_block_paddr);
10152 for (i = 0; i < NO_OF_SG_PER_BLOCK; i++) {
10153 sg_block->sg_list[i].sg_addr =
10154 cpu_to_le32(sg_dma_address(slp));
10155 sg_block->sg_list[i].sg_count =
10156 cpu_to_le32(sg_dma_len(slp));
10157 ASC_STATS_ADD(scp->device->host, sg_xfer,
10158 ASC_CEILING(sg_dma_len(slp), 512));
10160 if (--sg_elem_cnt == 0) { /* Last ADV_SG_BLOCK and scatter-gather entry. */
10161 sg_block->sg_cnt = i + 1;
10162 sg_block->sg_ptr = 0L; /* Last ADV_SG_BLOCK in list. */
10163 return ADV_SUCCESS;
10167 sg_block->sg_cnt = NO_OF_SG_PER_BLOCK;
10168 prev_sg_block = sg_block;
10173 * Build a request structure for the Adv Library (Wide Board).
10175 * If an adv_req_t can not be allocated to issue the request,
10176 * then return ASC_BUSY. If an error occurs, then return ASC_ERROR.
10178 * Multi-byte fields in the ASC_SCSI_REQ_Q that are used by the
10179 * microcode for DMA addresses or math operations are byte swapped
10180 * to little-endian order.
10183 adv_build_req(struct asc_board *boardp, struct scsi_cmnd *scp,
10184 ADV_SCSI_REQ_Q **adv_scsiqpp)
10187 ADV_SCSI_REQ_Q *scsiqp;
10192 * Allocate an adv_req_t structure from the board to execute
10195 if (boardp->adv_reqp == NULL) {
10196 ASC_DBG(1, "no free adv_req_t\n");
10197 ASC_STATS(scp->device->host, adv_build_noreq);
10200 reqp = boardp->adv_reqp;
10201 boardp->adv_reqp = reqp->next_reqp;
10202 reqp->next_reqp = NULL;
10206 * Get 32-byte aligned ADV_SCSI_REQ_Q and ADV_SG_BLOCK pointers.
10208 scsiqp = (ADV_SCSI_REQ_Q *)ADV_32BALIGN(&reqp->scsi_req_q);
10211 * Initialize the structure.
10213 scsiqp->cntl = scsiqp->scsi_cntl = scsiqp->done_status = 0;
10216 * Set the ADV_SCSI_REQ_Q 'srb_ptr' to point to the adv_req_t structure.
10218 scsiqp->srb_ptr = ASC_VADDR_TO_U32(reqp);
10221 * Set the adv_req_t 'cmndp' to point to the struct scsi_cmnd structure.
10226 * Build the ADV_SCSI_REQ_Q request.
10229 /* Set CDB length and copy it to the request structure. */
10230 scsiqp->cdb_len = scp->cmd_len;
10231 /* Copy first 12 CDB bytes to cdb[]. */
10232 for (i = 0; i < scp->cmd_len && i < 12; i++) {
10233 scsiqp->cdb[i] = scp->cmnd[i];
10235 /* Copy last 4 CDB bytes, if present, to cdb16[]. */
10236 for (; i < scp->cmd_len; i++) {
10237 scsiqp->cdb16[i - 12] = scp->cmnd[i];
10240 scsiqp->target_id = scp->device->id;
10241 scsiqp->target_lun = scp->device->lun;
10243 scsiqp->sense_addr = cpu_to_le32(virt_to_bus(&scp->sense_buffer[0]));
10244 scsiqp->sense_len = sizeof(scp->sense_buffer);
10247 * Build ADV_SCSI_REQ_Q for a contiguous buffer or a scatter-gather
10251 scsiqp->data_cnt = cpu_to_le32(scp->request_bufflen);
10252 scsiqp->vdata_addr = scp->request_buffer;
10253 scsiqp->data_addr = cpu_to_le32(virt_to_bus(scp->request_buffer));
10255 if (scp->use_sg == 0) {
10257 * CDB request of single contiguous buffer.
10259 reqp->sgblkp = NULL;
10260 scsiqp->data_cnt = cpu_to_le32(scp->request_bufflen);
10261 if (scp->request_bufflen) {
10262 scsiqp->vdata_addr = scp->request_buffer;
10263 scp->SCp.dma_handle =
10264 dma_map_single(boardp->dev, scp->request_buffer,
10265 scp->request_bufflen,
10266 scp->sc_data_direction);
10268 scsiqp->vdata_addr = NULL;
10269 scp->SCp.dma_handle = 0;
10271 scsiqp->data_addr = cpu_to_le32(scp->SCp.dma_handle);
10272 scsiqp->sg_list_ptr = NULL;
10273 scsiqp->sg_real_addr = 0;
10274 ASC_STATS(scp->device->host, cont_cnt);
10275 ASC_STATS_ADD(scp->device->host, cont_xfer,
10276 ASC_CEILING(scp->request_bufflen, 512));
10279 * CDB scatter-gather request list.
10281 struct scatterlist *slp;
10284 slp = (struct scatterlist *)scp->request_buffer;
10285 use_sg = dma_map_sg(boardp->dev, slp, scp->use_sg,
10286 scp->sc_data_direction);
10288 if (use_sg > ADV_MAX_SG_LIST) {
10289 scmd_printk(KERN_ERR, scp, "use_sg %d > "
10290 "ADV_MAX_SG_LIST %d\n", use_sg,
10291 scp->device->host->sg_tablesize);
10292 dma_unmap_sg(boardp->dev, slp, scp->use_sg,
10293 scp->sc_data_direction);
10294 scp->result = HOST_BYTE(DID_ERROR);
10297 * Free the 'adv_req_t' structure by adding it back
10298 * to the board free list.
10300 reqp->next_reqp = boardp->adv_reqp;
10301 boardp->adv_reqp = reqp;
10306 ret = adv_get_sglist(boardp, reqp, scp, use_sg);
10307 if (ret != ADV_SUCCESS) {
10309 * Free the adv_req_t structure by adding it back to
10310 * the board free list.
10312 reqp->next_reqp = boardp->adv_reqp;
10313 boardp->adv_reqp = reqp;
10318 ASC_STATS(scp->device->host, sg_cnt);
10319 ASC_STATS_ADD(scp->device->host, sg_elem, use_sg);
10322 ASC_DBG_PRT_ADV_SCSI_REQ_Q(2, scsiqp);
10323 ASC_DBG_PRT_CDB(1, scp->cmnd, scp->cmd_len);
10325 *adv_scsiqpp = scsiqp;
10327 return ASC_NOERROR;
10330 static int AscSgListToQueue(int sg_list)
10334 n_sg_list_qs = ((sg_list - 1) / ASC_SG_LIST_PER_Q);
10335 if (((sg_list - 1) % ASC_SG_LIST_PER_Q) != 0)
10337 return n_sg_list_qs + 1;
10341 AscGetNumOfFreeQueue(ASC_DVC_VAR *asc_dvc, uchar target_ix, uchar n_qs)
10345 ASC_SCSI_BIT_ID_TYPE target_id;
10348 target_id = ASC_TIX_TO_TARGET_ID(target_ix);
10349 tid_no = ASC_TIX_TO_TID(target_ix);
10350 if ((asc_dvc->unit_not_ready & target_id) ||
10351 (asc_dvc->queue_full_or_busy & target_id)) {
10355 cur_used_qs = (uint) asc_dvc->cur_total_qng +
10356 (uint) asc_dvc->last_q_shortage + (uint) ASC_MIN_FREE_Q;
10358 cur_used_qs = (uint) asc_dvc->cur_total_qng +
10359 (uint) ASC_MIN_FREE_Q;
10361 if ((uint) (cur_used_qs + n_qs) <= (uint) asc_dvc->max_total_qng) {
10362 cur_free_qs = (uint) asc_dvc->max_total_qng - cur_used_qs;
10363 if (asc_dvc->cur_dvc_qng[tid_no] >=
10364 asc_dvc->max_dvc_qng[tid_no]) {
10367 return cur_free_qs;
10370 if ((n_qs > asc_dvc->last_q_shortage)
10371 && (n_qs <= (asc_dvc->max_total_qng - ASC_MIN_FREE_Q))) {
10372 asc_dvc->last_q_shortage = n_qs;
10378 static uchar AscAllocFreeQueue(PortAddr iop_base, uchar free_q_head)
10384 q_addr = ASC_QNO_TO_QADDR(free_q_head);
10385 q_status = (uchar)AscReadLramByte(iop_base,
10387 ASC_SCSIQ_B_STATUS));
10388 next_qp = AscReadLramByte(iop_base, (ushort)(q_addr + ASC_SCSIQ_B_FWD));
10389 if (((q_status & QS_READY) == 0) && (next_qp != ASC_QLINK_END))
10391 return ASC_QLINK_END;
10395 AscAllocMultipleFreeQueue(PortAddr iop_base, uchar free_q_head, uchar n_free_q)
10399 for (i = 0; i < n_free_q; i++) {
10400 free_q_head = AscAllocFreeQueue(iop_base, free_q_head);
10401 if (free_q_head == ASC_QLINK_END)
10404 return free_q_head;
10409 * DvcPutScsiQ(PortAddr iop_base, ushort s_addr, uchar *outbuf, int words)
10411 * Calling/Exit State:
10415 * Output an ASC_SCSI_Q structure to the chip
10418 DvcPutScsiQ(PortAddr iop_base, ushort s_addr, uchar *outbuf, int words)
10422 ASC_DBG_PRT_HEX(2, "DvcPutScsiQ", outbuf, 2 * words);
10423 AscSetChipLramAddr(iop_base, s_addr);
10424 for (i = 0; i < 2 * words; i += 2) {
10425 if (i == 4 || i == 20) {
10428 outpw(iop_base + IOP_RAM_DATA,
10429 ((ushort)outbuf[i + 1] << 8) | outbuf[i]);
10433 static int AscPutReadyQueue(ASC_DVC_VAR *asc_dvc, ASC_SCSI_Q *scsiq, uchar q_no)
10438 uchar syn_period_ix;
10442 iop_base = asc_dvc->iop_base;
10443 if (((asc_dvc->init_sdtr & scsiq->q1.target_id) != 0) &&
10444 ((asc_dvc->sdtr_done & scsiq->q1.target_id) == 0)) {
10445 tid_no = ASC_TIX_TO_TID(scsiq->q2.target_ix);
10446 sdtr_data = AscGetMCodeInitSDTRAtID(iop_base, tid_no);
10448 (sdtr_data >> 4) & (asc_dvc->max_sdtr_index - 1);
10449 syn_offset = sdtr_data & ASC_SYN_MAX_OFFSET;
10450 AscMsgOutSDTR(asc_dvc,
10451 asc_dvc->sdtr_period_tbl[syn_period_ix],
10453 scsiq->q1.cntl |= QC_MSG_OUT;
10455 q_addr = ASC_QNO_TO_QADDR(q_no);
10456 if ((scsiq->q1.target_id & asc_dvc->use_tagged_qng) == 0) {
10457 scsiq->q2.tag_code &= ~MSG_SIMPLE_TAG;
10459 scsiq->q1.status = QS_FREE;
10460 AscMemWordCopyPtrToLram(iop_base,
10461 q_addr + ASC_SCSIQ_CDB_BEG,
10462 (uchar *)scsiq->cdbptr, scsiq->q2.cdb_len >> 1);
10464 DvcPutScsiQ(iop_base,
10465 q_addr + ASC_SCSIQ_CPY_BEG,
10466 (uchar *)&scsiq->q1.cntl,
10467 ((sizeof(ASC_SCSIQ_1) + sizeof(ASC_SCSIQ_2)) / 2) - 1);
10468 AscWriteLramWord(iop_base,
10469 (ushort)(q_addr + (ushort)ASC_SCSIQ_B_STATUS),
10470 (ushort)(((ushort)scsiq->q1.
10471 q_no << 8) | (ushort)QS_READY));
10476 AscPutReadySgListQueue(ASC_DVC_VAR *asc_dvc, ASC_SCSI_Q *scsiq, uchar q_no)
10480 ASC_SG_HEAD *sg_head;
10481 ASC_SG_LIST_Q scsi_sg_q;
10482 ASC_DCNT saved_data_addr;
10483 ASC_DCNT saved_data_cnt;
10485 ushort sg_list_dwords;
10487 ushort sg_entry_cnt;
10491 iop_base = asc_dvc->iop_base;
10492 sg_head = scsiq->sg_head;
10493 saved_data_addr = scsiq->q1.data_addr;
10494 saved_data_cnt = scsiq->q1.data_cnt;
10495 scsiq->q1.data_addr = (ASC_PADDR) sg_head->sg_list[0].addr;
10496 scsiq->q1.data_cnt = (ASC_DCNT) sg_head->sg_list[0].bytes;
10497 #if CC_VERY_LONG_SG_LIST
10499 * If sg_head->entry_cnt is greater than ASC_MAX_SG_LIST
10500 * then not all SG elements will fit in the allocated queues.
10501 * The rest of the SG elements will be copied when the RISC
10502 * completes the SG elements that fit and halts.
10504 if (sg_head->entry_cnt > ASC_MAX_SG_LIST) {
10506 * Set sg_entry_cnt to be the number of SG elements that
10507 * will fit in the allocated SG queues. It is minus 1, because
10508 * the first SG element is handled above. ASC_MAX_SG_LIST is
10509 * already inflated by 1 to account for this. For example it
10510 * may be 50 which is 1 + 7 queues * 7 SG elements.
10512 sg_entry_cnt = ASC_MAX_SG_LIST - 1;
10515 * Keep track of remaining number of SG elements that will
10516 * need to be handled from a_isr.c.
10518 scsiq->remain_sg_entry_cnt =
10519 sg_head->entry_cnt - ASC_MAX_SG_LIST;
10521 #endif /* CC_VERY_LONG_SG_LIST */
10523 * Set sg_entry_cnt to be the number of SG elements that
10524 * will fit in the allocated SG queues. It is minus 1, because
10525 * the first SG element is handled above.
10527 sg_entry_cnt = sg_head->entry_cnt - 1;
10528 #if CC_VERY_LONG_SG_LIST
10530 #endif /* CC_VERY_LONG_SG_LIST */
10531 if (sg_entry_cnt != 0) {
10532 scsiq->q1.cntl |= QC_SG_HEAD;
10533 q_addr = ASC_QNO_TO_QADDR(q_no);
10535 scsiq->q1.sg_queue_cnt = sg_head->queue_cnt;
10536 scsi_sg_q.sg_head_qp = q_no;
10537 scsi_sg_q.cntl = QCSG_SG_XFER_LIST;
10538 for (i = 0; i < sg_head->queue_cnt; i++) {
10539 scsi_sg_q.seq_no = i + 1;
10540 if (sg_entry_cnt > ASC_SG_LIST_PER_Q) {
10541 sg_list_dwords = (uchar)(ASC_SG_LIST_PER_Q * 2);
10542 sg_entry_cnt -= ASC_SG_LIST_PER_Q;
10544 scsi_sg_q.sg_list_cnt =
10546 scsi_sg_q.sg_cur_list_cnt =
10549 scsi_sg_q.sg_list_cnt =
10550 ASC_SG_LIST_PER_Q - 1;
10551 scsi_sg_q.sg_cur_list_cnt =
10552 ASC_SG_LIST_PER_Q - 1;
10555 #if CC_VERY_LONG_SG_LIST
10557 * This is the last SG queue in the list of
10558 * allocated SG queues. If there are more
10559 * SG elements than will fit in the allocated
10560 * queues, then set the QCSG_SG_XFER_MORE flag.
10562 if (sg_head->entry_cnt > ASC_MAX_SG_LIST) {
10563 scsi_sg_q.cntl |= QCSG_SG_XFER_MORE;
10565 #endif /* CC_VERY_LONG_SG_LIST */
10566 scsi_sg_q.cntl |= QCSG_SG_XFER_END;
10567 #if CC_VERY_LONG_SG_LIST
10569 #endif /* CC_VERY_LONG_SG_LIST */
10570 sg_list_dwords = sg_entry_cnt << 1;
10572 scsi_sg_q.sg_list_cnt = sg_entry_cnt;
10573 scsi_sg_q.sg_cur_list_cnt =
10576 scsi_sg_q.sg_list_cnt =
10578 scsi_sg_q.sg_cur_list_cnt =
10583 next_qp = AscReadLramByte(iop_base,
10586 scsi_sg_q.q_no = next_qp;
10587 q_addr = ASC_QNO_TO_QADDR(next_qp);
10588 AscMemWordCopyPtrToLram(iop_base,
10589 q_addr + ASC_SCSIQ_SGHD_CPY_BEG,
10590 (uchar *)&scsi_sg_q,
10591 sizeof(ASC_SG_LIST_Q) >> 1);
10592 AscMemDWordCopyPtrToLram(iop_base,
10593 q_addr + ASC_SGQ_LIST_BEG,
10594 (uchar *)&sg_head->
10597 sg_index += ASC_SG_LIST_PER_Q;
10598 scsiq->next_sg_index = sg_index;
10601 scsiq->q1.cntl &= ~QC_SG_HEAD;
10603 sta = AscPutReadyQueue(asc_dvc, scsiq, q_no);
10604 scsiq->q1.data_addr = saved_data_addr;
10605 scsiq->q1.data_cnt = saved_data_cnt;
10610 AscSendScsiQueue(ASC_DVC_VAR *asc_dvc, ASC_SCSI_Q *scsiq, uchar n_q_required)
10619 iop_base = asc_dvc->iop_base;
10620 target_ix = scsiq->q2.target_ix;
10621 tid_no = ASC_TIX_TO_TID(target_ix);
10623 free_q_head = (uchar)AscGetVarFreeQHead(iop_base);
10624 if (n_q_required > 1) {
10625 next_qp = AscAllocMultipleFreeQueue(iop_base, free_q_head,
10626 (uchar)n_q_required);
10627 if (next_qp != ASC_QLINK_END) {
10628 asc_dvc->last_q_shortage = 0;
10629 scsiq->sg_head->queue_cnt = n_q_required - 1;
10630 scsiq->q1.q_no = free_q_head;
10631 sta = AscPutReadySgListQueue(asc_dvc, scsiq,
10634 } else if (n_q_required == 1) {
10635 next_qp = AscAllocFreeQueue(iop_base, free_q_head);
10636 if (next_qp != ASC_QLINK_END) {
10637 scsiq->q1.q_no = free_q_head;
10638 sta = AscPutReadyQueue(asc_dvc, scsiq, free_q_head);
10642 AscPutVarFreeQHead(iop_base, next_qp);
10643 asc_dvc->cur_total_qng += n_q_required;
10644 asc_dvc->cur_dvc_qng[tid_no]++;
10649 #define ASC_SYN_OFFSET_ONE_DISABLE_LIST 16
10650 static uchar _syn_offset_one_disable_cmd[ASC_SYN_OFFSET_ONE_DISABLE_LIST] = {
10669 static int AscExeScsiQueue(ASC_DVC_VAR *asc_dvc, ASC_SCSI_Q *scsiq)
10674 int disable_syn_offset_one_fix;
10677 ushort sg_entry_cnt = 0;
10678 ushort sg_entry_cnt_minus_one = 0;
10685 ASC_SG_HEAD *sg_head;
10688 iop_base = asc_dvc->iop_base;
10689 sg_head = scsiq->sg_head;
10690 if (asc_dvc->err_code != 0)
10692 scsiq->q1.q_no = 0;
10693 if ((scsiq->q2.tag_code & ASC_TAG_FLAG_EXTRA_BYTES) == 0) {
10694 scsiq->q1.extra_bytes = 0;
10697 target_ix = scsiq->q2.target_ix;
10698 tid_no = ASC_TIX_TO_TID(target_ix);
10700 if (scsiq->cdbptr[0] == REQUEST_SENSE) {
10701 if ((asc_dvc->init_sdtr & scsiq->q1.target_id) != 0) {
10702 asc_dvc->sdtr_done &= ~scsiq->q1.target_id;
10703 sdtr_data = AscGetMCodeInitSDTRAtID(iop_base, tid_no);
10704 AscMsgOutSDTR(asc_dvc,
10706 sdtr_period_tbl[(sdtr_data >> 4) &
10710 (uchar)(sdtr_data & (uchar)
10711 ASC_SYN_MAX_OFFSET));
10712 scsiq->q1.cntl |= (QC_MSG_OUT | QC_URGENT);
10715 if (asc_dvc->in_critical_cnt != 0) {
10716 AscSetLibErrorCode(asc_dvc, ASCQ_ERR_CRITICAL_RE_ENTRY);
10719 asc_dvc->in_critical_cnt++;
10720 if ((scsiq->q1.cntl & QC_SG_HEAD) != 0) {
10721 if ((sg_entry_cnt = sg_head->entry_cnt) == 0) {
10722 asc_dvc->in_critical_cnt--;
10725 #if !CC_VERY_LONG_SG_LIST
10726 if (sg_entry_cnt > ASC_MAX_SG_LIST) {
10727 asc_dvc->in_critical_cnt--;
10730 #endif /* !CC_VERY_LONG_SG_LIST */
10731 if (sg_entry_cnt == 1) {
10732 scsiq->q1.data_addr =
10733 (ADV_PADDR)sg_head->sg_list[0].addr;
10734 scsiq->q1.data_cnt =
10735 (ADV_DCNT)sg_head->sg_list[0].bytes;
10736 scsiq->q1.cntl &= ~(QC_SG_HEAD | QC_SG_SWAP_QUEUE);
10738 sg_entry_cnt_minus_one = sg_entry_cnt - 1;
10740 scsi_cmd = scsiq->cdbptr[0];
10741 disable_syn_offset_one_fix = FALSE;
10742 if ((asc_dvc->pci_fix_asyn_xfer & scsiq->q1.target_id) &&
10743 !(asc_dvc->pci_fix_asyn_xfer_always & scsiq->q1.target_id)) {
10744 if (scsiq->q1.cntl & QC_SG_HEAD) {
10746 for (i = 0; i < sg_entry_cnt; i++) {
10748 (ADV_DCNT)le32_to_cpu(sg_head->sg_list[i].
10752 data_cnt = le32_to_cpu(scsiq->q1.data_cnt);
10754 if (data_cnt != 0UL) {
10755 if (data_cnt < 512UL) {
10756 disable_syn_offset_one_fix = TRUE;
10758 for (i = 0; i < ASC_SYN_OFFSET_ONE_DISABLE_LIST;
10761 _syn_offset_one_disable_cmd[i];
10762 if (disable_cmd == 0xFF) {
10765 if (scsi_cmd == disable_cmd) {
10766 disable_syn_offset_one_fix =
10774 if (disable_syn_offset_one_fix) {
10775 scsiq->q2.tag_code &= ~MSG_SIMPLE_TAG;
10776 scsiq->q2.tag_code |= (ASC_TAG_FLAG_DISABLE_ASYN_USE_SYN_FIX |
10777 ASC_TAG_FLAG_DISABLE_DISCONNECT);
10779 scsiq->q2.tag_code &= 0x27;
10781 if ((scsiq->q1.cntl & QC_SG_HEAD) != 0) {
10782 if (asc_dvc->bug_fix_cntl) {
10783 if (asc_dvc->bug_fix_cntl & ASC_BUG_FIX_IF_NOT_DWB) {
10784 if ((scsi_cmd == READ_6) ||
10785 (scsi_cmd == READ_10)) {
10787 (ADV_PADDR)le32_to_cpu(sg_head->
10789 [sg_entry_cnt_minus_one].
10791 (ADV_DCNT)le32_to_cpu(sg_head->
10793 [sg_entry_cnt_minus_one].
10796 (uchar)((ushort)addr & 0x0003);
10797 if ((extra_bytes != 0)
10801 ASC_TAG_FLAG_EXTRA_BYTES)
10803 scsiq->q2.tag_code |=
10804 ASC_TAG_FLAG_EXTRA_BYTES;
10805 scsiq->q1.extra_bytes =
10808 le32_to_cpu(sg_head->
10810 [sg_entry_cnt_minus_one].
10813 (ASC_DCNT) extra_bytes;
10816 [sg_entry_cnt_minus_one].
10818 cpu_to_le32(data_cnt);
10823 sg_head->entry_to_copy = sg_head->entry_cnt;
10824 #if CC_VERY_LONG_SG_LIST
10826 * Set the sg_entry_cnt to the maximum possible. The rest of
10827 * the SG elements will be copied when the RISC completes the
10828 * SG elements that fit and halts.
10830 if (sg_entry_cnt > ASC_MAX_SG_LIST) {
10831 sg_entry_cnt = ASC_MAX_SG_LIST;
10833 #endif /* CC_VERY_LONG_SG_LIST */
10834 n_q_required = AscSgListToQueue(sg_entry_cnt);
10835 if ((AscGetNumOfFreeQueue(asc_dvc, target_ix, n_q_required) >=
10836 (uint) n_q_required)
10837 || ((scsiq->q1.cntl & QC_URGENT) != 0)) {
10839 AscSendScsiQueue(asc_dvc, scsiq,
10840 n_q_required)) == 1) {
10841 asc_dvc->in_critical_cnt--;
10846 if (asc_dvc->bug_fix_cntl) {
10847 if (asc_dvc->bug_fix_cntl & ASC_BUG_FIX_IF_NOT_DWB) {
10848 if ((scsi_cmd == READ_6) ||
10849 (scsi_cmd == READ_10)) {
10851 le32_to_cpu(scsiq->q1.data_addr) +
10852 le32_to_cpu(scsiq->q1.data_cnt);
10854 (uchar)((ushort)addr & 0x0003);
10855 if ((extra_bytes != 0)
10859 ASC_TAG_FLAG_EXTRA_BYTES)
10862 le32_to_cpu(scsiq->q1.
10864 if (((ushort)data_cnt & 0x01FF)
10866 scsiq->q2.tag_code |=
10867 ASC_TAG_FLAG_EXTRA_BYTES;
10868 data_cnt -= (ASC_DCNT)
10870 scsiq->q1.data_cnt =
10873 scsiq->q1.extra_bytes =
10881 if ((AscGetNumOfFreeQueue(asc_dvc, target_ix, 1) >= 1) ||
10882 ((scsiq->q1.cntl & QC_URGENT) != 0)) {
10883 if ((sta = AscSendScsiQueue(asc_dvc, scsiq,
10884 n_q_required)) == 1) {
10885 asc_dvc->in_critical_cnt--;
10890 asc_dvc->in_critical_cnt--;
10895 * AdvExeScsiQueue() - Send a request to the RISC microcode program.
10897 * Allocate a carrier structure, point the carrier to the ADV_SCSI_REQ_Q,
10898 * add the carrier to the ICQ (Initiator Command Queue), and tickle the
10899 * RISC to notify it a new command is ready to be executed.
10901 * If 'done_status' is not set to QD_DO_RETRY, then 'error_retry' will be
10902 * set to SCSI_MAX_RETRY.
10904 * Multi-byte fields in the ASC_SCSI_REQ_Q that are used by the microcode
10905 * for DMA addresses or math operations are byte swapped to little-endian
10909 * ADV_SUCCESS(1) - The request was successfully queued.
10910 * ADV_BUSY(0) - Resource unavailable; Retry again after pending
10911 * request completes.
10912 * ADV_ERROR(-1) - Invalid ADV_SCSI_REQ_Q request structure
10915 static int AdvExeScsiQueue(ADV_DVC_VAR *asc_dvc, ADV_SCSI_REQ_Q *scsiq)
10917 AdvPortAddr iop_base;
10919 ADV_PADDR req_paddr;
10920 ADV_CARR_T *new_carrp;
10923 * The ADV_SCSI_REQ_Q 'target_id' field should never exceed ADV_MAX_TID.
10925 if (scsiq->target_id > ADV_MAX_TID) {
10926 scsiq->host_status = QHSTA_M_INVALID_DEVICE;
10927 scsiq->done_status = QD_WITH_ERROR;
10931 iop_base = asc_dvc->iop_base;
10934 * Allocate a carrier ensuring at least one carrier always
10935 * remains on the freelist and initialize fields.
10937 if ((new_carrp = asc_dvc->carr_freelist) == NULL) {
10940 asc_dvc->carr_freelist = (ADV_CARR_T *)
10941 ADV_U32_TO_VADDR(le32_to_cpu(new_carrp->next_vpa));
10942 asc_dvc->carr_pending_cnt++;
10945 * Set the carrier to be a stopper by setting 'next_vpa'
10946 * to the stopper value. The current stopper will be changed
10947 * below to point to the new stopper.
10949 new_carrp->next_vpa = cpu_to_le32(ASC_CQ_STOPPER);
10952 * Clear the ADV_SCSI_REQ_Q done flag.
10954 scsiq->a_flag &= ~ADV_SCSIQ_DONE;
10956 req_size = sizeof(ADV_SCSI_REQ_Q);
10957 req_paddr = DvcGetPhyAddr(asc_dvc, scsiq, (uchar *)scsiq,
10958 (ADV_SDCNT *)&req_size, ADV_IS_SCSIQ_FLAG);
10960 BUG_ON(req_paddr & 31);
10961 BUG_ON(req_size < sizeof(ADV_SCSI_REQ_Q));
10963 /* Wait for assertion before making little-endian */
10964 req_paddr = cpu_to_le32(req_paddr);
10966 /* Save virtual and physical address of ADV_SCSI_REQ_Q and carrier. */
10967 scsiq->scsiq_ptr = cpu_to_le32(ADV_VADDR_TO_U32(scsiq));
10968 scsiq->scsiq_rptr = req_paddr;
10970 scsiq->carr_va = cpu_to_le32(ADV_VADDR_TO_U32(asc_dvc->icq_sp));
10972 * Every ADV_CARR_T.carr_pa is byte swapped to little-endian
10973 * order during initialization.
10975 scsiq->carr_pa = asc_dvc->icq_sp->carr_pa;
10978 * Use the current stopper to send the ADV_SCSI_REQ_Q command to
10979 * the microcode. The newly allocated stopper will become the new
10982 asc_dvc->icq_sp->areq_vpa = req_paddr;
10985 * Set the 'next_vpa' pointer for the old stopper to be the
10986 * physical address of the new stopper. The RISC can only
10987 * follow physical addresses.
10989 asc_dvc->icq_sp->next_vpa = new_carrp->carr_pa;
10992 * Set the host adapter stopper pointer to point to the new carrier.
10994 asc_dvc->icq_sp = new_carrp;
10996 if (asc_dvc->chip_type == ADV_CHIP_ASC3550 ||
10997 asc_dvc->chip_type == ADV_CHIP_ASC38C0800) {
10999 * Tickle the RISC to tell it to read its Command Queue Head pointer.
11001 AdvWriteByteRegister(iop_base, IOPB_TICKLE, ADV_TICKLE_A);
11002 if (asc_dvc->chip_type == ADV_CHIP_ASC3550) {
11004 * Clear the tickle value. In the ASC-3550 the RISC flag
11005 * command 'clr_tickle_a' does not work unless the host
11006 * value is cleared.
11008 AdvWriteByteRegister(iop_base, IOPB_TICKLE,
11011 } else if (asc_dvc->chip_type == ADV_CHIP_ASC38C1600) {
11013 * Notify the RISC a carrier is ready by writing the physical
11014 * address of the new carrier stopper to the COMMA register.
11016 AdvWriteDWordRegister(iop_base, IOPDW_COMMA,
11017 le32_to_cpu(new_carrp->carr_pa));
11020 return ADV_SUCCESS;
11024 * Execute a single 'Scsi_Cmnd'.
11026 * The function 'done' is called when the request has been completed.
11030 * host - board controlling device
11031 * device - device to send command
11032 * target - target of device
11033 * lun - lun of device
11034 * cmd_len - length of SCSI CDB
11035 * cmnd - buffer for SCSI 8, 10, or 12 byte CDB
11036 * use_sg - if non-zero indicates scatter-gather request with use_sg elements
11038 * if (use_sg == 0) {
11039 * request_buffer - buffer address for request
11040 * request_bufflen - length of request buffer
11042 * request_buffer - pointer to scatterlist structure
11045 * sense_buffer - sense command buffer
11047 * result (4 bytes of an int):
11049 * 0 SCSI Status Byte Code
11050 * 1 SCSI One Byte Message Code
11051 * 2 Host Error Code
11052 * 3 Mid-Level Error Code
11054 * host driver fields:
11055 * SCp - Scsi_Pointer used for command processing status
11056 * scsi_done - used to save caller's done function
11057 * host_scribble - used for pointer to another struct scsi_cmnd
11059 * If this function returns ASC_NOERROR the request will be completed
11060 * from the interrupt handler.
11062 * If this function returns ASC_ERROR the host error code has been set,
11063 * and the called must call asc_scsi_done.
11065 * If ASC_BUSY is returned the request will be returned to the midlayer
11066 * and re-tried later.
11068 static int asc_execute_scsi_cmnd(struct scsi_cmnd *scp)
11071 struct asc_board *boardp = shost_priv(scp->device->host);
11073 ASC_DBG(1, "scp 0x%p\n", scp);
11075 if (ASC_NARROW_BOARD(boardp)) {
11076 ASC_DVC_VAR *asc_dvc = &boardp->dvc_var.asc_dvc_var;
11077 struct asc_scsi_q asc_scsi_q;
11079 /* asc_build_req() can not return ASC_BUSY. */
11080 ret = asc_build_req(boardp, scp, &asc_scsi_q);
11081 if (ret == ASC_ERROR) {
11082 ASC_STATS(scp->device->host, build_error);
11086 ret = AscExeScsiQueue(asc_dvc, &asc_scsi_q);
11087 kfree(asc_scsi_q.sg_head);
11088 err_code = asc_dvc->err_code;
11090 ADV_DVC_VAR *adv_dvc = &boardp->dvc_var.adv_dvc_var;
11091 ADV_SCSI_REQ_Q *adv_scsiqp;
11093 switch (adv_build_req(boardp, scp, &adv_scsiqp)) {
11095 ASC_DBG(3, "adv_build_req ASC_NOERROR\n");
11098 ASC_DBG(1, "adv_build_req ASC_BUSY\n");
11100 * The asc_stats fields 'adv_build_noreq' and
11101 * 'adv_build_nosg' count wide board busy conditions.
11102 * They are updated in adv_build_req and
11103 * adv_get_sglist, respectively.
11108 ASC_DBG(1, "adv_build_req ASC_ERROR\n");
11109 ASC_STATS(scp->device->host, build_error);
11113 ret = AdvExeScsiQueue(adv_dvc, adv_scsiqp);
11114 err_code = adv_dvc->err_code;
11119 ASC_STATS(scp->device->host, exe_noerror);
11121 * Increment monotonically increasing per device
11122 * successful request counter. Wrapping doesn't matter.
11124 boardp->reqcnt[scp->device->id]++;
11125 ASC_DBG(1, "ExeScsiQueue() ASC_NOERROR\n");
11128 ASC_STATS(scp->device->host, exe_busy);
11131 scmd_printk(KERN_ERR, scp, "ExeScsiQueue() ASC_ERROR, "
11132 "err_code 0x%x\n", err_code);
11133 ASC_STATS(scp->device->host, exe_error);
11134 scp->result = HOST_BYTE(DID_ERROR);
11137 scmd_printk(KERN_ERR, scp, "ExeScsiQueue() unknown, "
11138 "err_code 0x%x\n", err_code);
11139 ASC_STATS(scp->device->host, exe_unknown);
11140 scp->result = HOST_BYTE(DID_ERROR);
11144 ASC_DBG(1, "end\n");
11149 * advansys_queuecommand() - interrupt-driven I/O entrypoint.
11151 * This function always returns 0. Command return status is saved
11152 * in the 'scp' result field.
11155 advansys_queuecommand(struct scsi_cmnd *scp, void (*done)(struct scsi_cmnd *))
11157 struct Scsi_Host *shost = scp->device->host;
11158 int asc_res, result = 0;
11160 ASC_STATS(shost, queuecommand);
11161 scp->scsi_done = done;
11163 asc_res = asc_execute_scsi_cmnd(scp);
11169 result = SCSI_MLQUEUE_HOST_BUSY;
11173 asc_scsi_done(scp);
11180 static ushort __devinit AscGetEisaChipCfg(PortAddr iop_base)
11182 PortAddr eisa_cfg_iop = (PortAddr) ASC_GET_EISA_SLOT(iop_base) |
11183 (PortAddr) (ASC_EISA_CFG_IOP_MASK);
11184 return inpw(eisa_cfg_iop);
11188 * Return the BIOS address of the adapter at the specified
11189 * I/O port and with the specified bus type.
11191 static unsigned short __devinit
11192 AscGetChipBiosAddress(PortAddr iop_base, unsigned short bus_type)
11194 unsigned short cfg_lsw;
11195 unsigned short bios_addr;
11198 * The PCI BIOS is re-located by the motherboard BIOS. Because
11199 * of this the driver can not determine where a PCI BIOS is
11200 * loaded and executes.
11202 if (bus_type & ASC_IS_PCI)
11205 if ((bus_type & ASC_IS_EISA) != 0) {
11206 cfg_lsw = AscGetEisaChipCfg(iop_base);
11208 bios_addr = ASC_BIOS_MIN_ADDR + cfg_lsw * ASC_BIOS_BANK_SIZE;
11212 cfg_lsw = AscGetChipCfgLsw(iop_base);
11215 * ISA PnP uses the top bit as the 32K BIOS flag
11217 if (bus_type == ASC_IS_ISAPNP)
11219 bios_addr = ASC_BIOS_MIN_ADDR + (cfg_lsw >> 12) * ASC_BIOS_BANK_SIZE;
11223 static uchar __devinit AscSetChipScsiID(PortAddr iop_base, uchar new_host_id)
11227 if (AscGetChipScsiID(iop_base) == new_host_id) {
11228 return (new_host_id);
11230 cfg_lsw = AscGetChipCfgLsw(iop_base);
11232 cfg_lsw |= (ushort)((new_host_id & ASC_MAX_TID) << 8);
11233 AscSetChipCfgLsw(iop_base, cfg_lsw);
11234 return (AscGetChipScsiID(iop_base));
11237 static unsigned char __devinit AscGetChipScsiCtrl(PortAddr iop_base)
11241 AscSetBank(iop_base, 1);
11242 sc = inp(iop_base + IOP_REG_SC);
11243 AscSetBank(iop_base, 0);
11247 static unsigned char __devinit
11248 AscGetChipVersion(PortAddr iop_base, unsigned short bus_type)
11250 if (bus_type & ASC_IS_EISA) {
11252 unsigned char revision;
11253 eisa_iop = (PortAddr) ASC_GET_EISA_SLOT(iop_base) |
11254 (PortAddr) ASC_EISA_REV_IOP_MASK;
11255 revision = inp(eisa_iop);
11256 return ASC_CHIP_MIN_VER_EISA - 1 + revision;
11258 return AscGetChipVerNo(iop_base);
11262 static void __devinit AscEnableIsaDma(uchar dma_channel)
11264 if (dma_channel < 4) {
11265 outp(0x000B, (ushort)(0xC0 | dma_channel));
11266 outp(0x000A, dma_channel);
11267 } else if (dma_channel < 8) {
11268 outp(0x00D6, (ushort)(0xC0 | (dma_channel - 4)));
11269 outp(0x00D4, (ushort)(dma_channel - 4));
11272 #endif /* CONFIG_ISA */
11274 static int AscStopQueueExe(PortAddr iop_base)
11278 if (AscReadLramByte(iop_base, ASCV_STOP_CODE_B) == 0) {
11279 AscWriteLramByte(iop_base, ASCV_STOP_CODE_B,
11280 ASC_STOP_REQ_RISC_STOP);
11282 if (AscReadLramByte(iop_base, ASCV_STOP_CODE_B) &
11283 ASC_STOP_ACK_RISC_STOP) {
11287 } while (count++ < 20);
11292 static ASC_DCNT __devinit AscGetMaxDmaCount(ushort bus_type)
11294 if (bus_type & ASC_IS_ISA)
11295 return ASC_MAX_ISA_DMA_COUNT;
11296 else if (bus_type & (ASC_IS_EISA | ASC_IS_VL))
11297 return ASC_MAX_VL_DMA_COUNT;
11298 return ASC_MAX_PCI_DMA_COUNT;
11302 static ushort __devinit AscGetIsaDmaChannel(PortAddr iop_base)
11306 channel = AscGetChipCfgLsw(iop_base) & 0x0003;
11307 if (channel == 0x03)
11309 else if (channel == 0x00)
11311 return (channel + 4);
11314 static ushort __devinit AscSetIsaDmaChannel(PortAddr iop_base, ushort dma_channel)
11319 if ((dma_channel >= 5) && (dma_channel <= 7)) {
11320 if (dma_channel == 7)
11323 value = dma_channel - 4;
11324 cfg_lsw = AscGetChipCfgLsw(iop_base) & 0xFFFC;
11326 AscSetChipCfgLsw(iop_base, cfg_lsw);
11327 return (AscGetIsaDmaChannel(iop_base));
11332 static uchar __devinit AscGetIsaDmaSpeed(PortAddr iop_base)
11336 AscSetBank(iop_base, 1);
11337 speed_value = AscReadChipDmaSpeed(iop_base);
11338 speed_value &= 0x07;
11339 AscSetBank(iop_base, 0);
11340 return speed_value;
11343 static uchar __devinit AscSetIsaDmaSpeed(PortAddr iop_base, uchar speed_value)
11345 speed_value &= 0x07;
11346 AscSetBank(iop_base, 1);
11347 AscWriteChipDmaSpeed(iop_base, speed_value);
11348 AscSetBank(iop_base, 0);
11349 return AscGetIsaDmaSpeed(iop_base);
11351 #endif /* CONFIG_ISA */
11353 static ushort __devinit AscInitAscDvcVar(ASC_DVC_VAR *asc_dvc)
11358 uchar chip_version;
11360 iop_base = asc_dvc->iop_base;
11362 asc_dvc->err_code = 0;
11363 if ((asc_dvc->bus_type &
11364 (ASC_IS_ISA | ASC_IS_PCI | ASC_IS_EISA | ASC_IS_VL)) == 0) {
11365 asc_dvc->err_code |= ASC_IERR_NO_BUS_TYPE;
11367 AscSetChipControl(iop_base, CC_HALT);
11368 AscSetChipStatus(iop_base, 0);
11369 asc_dvc->bug_fix_cntl = 0;
11370 asc_dvc->pci_fix_asyn_xfer = 0;
11371 asc_dvc->pci_fix_asyn_xfer_always = 0;
11372 /* asc_dvc->init_state initalized in AscInitGetConfig(). */
11373 asc_dvc->sdtr_done = 0;
11374 asc_dvc->cur_total_qng = 0;
11375 asc_dvc->is_in_int = 0;
11376 asc_dvc->in_critical_cnt = 0;
11377 asc_dvc->last_q_shortage = 0;
11378 asc_dvc->use_tagged_qng = 0;
11379 asc_dvc->no_scam = 0;
11380 asc_dvc->unit_not_ready = 0;
11381 asc_dvc->queue_full_or_busy = 0;
11382 asc_dvc->redo_scam = 0;
11384 asc_dvc->min_sdtr_index = 0;
11385 asc_dvc->cfg->can_tagged_qng = 0;
11386 asc_dvc->cfg->cmd_qng_enabled = 0;
11387 asc_dvc->dvc_cntl = ASC_DEF_DVC_CNTL;
11388 asc_dvc->init_sdtr = 0;
11389 asc_dvc->max_total_qng = ASC_DEF_MAX_TOTAL_QNG;
11390 asc_dvc->scsi_reset_wait = 3;
11391 asc_dvc->start_motor = ASC_SCSI_WIDTH_BIT_SET;
11392 asc_dvc->max_dma_count = AscGetMaxDmaCount(asc_dvc->bus_type);
11393 asc_dvc->cfg->sdtr_enable = ASC_SCSI_WIDTH_BIT_SET;
11394 asc_dvc->cfg->disc_enable = ASC_SCSI_WIDTH_BIT_SET;
11395 asc_dvc->cfg->chip_scsi_id = ASC_DEF_CHIP_SCSI_ID;
11396 chip_version = AscGetChipVersion(iop_base, asc_dvc->bus_type);
11397 asc_dvc->cfg->chip_version = chip_version;
11398 asc_dvc->sdtr_period_tbl = asc_syn_xfer_period;
11399 asc_dvc->max_sdtr_index = 7;
11400 if ((asc_dvc->bus_type & ASC_IS_PCI) &&
11401 (chip_version >= ASC_CHIP_VER_PCI_ULTRA_3150)) {
11402 asc_dvc->bus_type = ASC_IS_PCI_ULTRA;
11403 asc_dvc->sdtr_period_tbl = asc_syn_ultra_xfer_period;
11404 asc_dvc->max_sdtr_index = 15;
11405 if (chip_version == ASC_CHIP_VER_PCI_ULTRA_3150) {
11406 AscSetExtraControl(iop_base,
11407 (SEC_ACTIVE_NEGATE | SEC_SLEW_RATE));
11408 } else if (chip_version >= ASC_CHIP_VER_PCI_ULTRA_3050) {
11409 AscSetExtraControl(iop_base,
11410 (SEC_ACTIVE_NEGATE |
11411 SEC_ENABLE_FILTER));
11414 if (asc_dvc->bus_type == ASC_IS_PCI) {
11415 AscSetExtraControl(iop_base,
11416 (SEC_ACTIVE_NEGATE | SEC_SLEW_RATE));
11419 asc_dvc->cfg->isa_dma_speed = ASC_DEF_ISA_DMA_SPEED;
11421 if ((asc_dvc->bus_type & ASC_IS_ISA) != 0) {
11422 if (chip_version >= ASC_CHIP_MIN_VER_ISA_PNP) {
11423 AscSetChipIFC(iop_base, IFC_INIT_DEFAULT);
11424 asc_dvc->bus_type = ASC_IS_ISAPNP;
11426 asc_dvc->cfg->isa_dma_channel =
11427 (uchar)AscGetIsaDmaChannel(iop_base);
11429 #endif /* CONFIG_ISA */
11430 for (i = 0; i <= ASC_MAX_TID; i++) {
11431 asc_dvc->cur_dvc_qng[i] = 0;
11432 asc_dvc->max_dvc_qng[i] = ASC_MAX_SCSI1_QNG;
11433 asc_dvc->scsiq_busy_head[i] = (ASC_SCSI_Q *)0L;
11434 asc_dvc->scsiq_busy_tail[i] = (ASC_SCSI_Q *)0L;
11435 asc_dvc->cfg->max_tag_qng[i] = ASC_MAX_INRAM_TAG_QNG;
11440 static int __devinit AscWriteEEPCmdReg(PortAddr iop_base, uchar cmd_reg)
11444 for (retry = 0; retry < ASC_EEP_MAX_RETRY; retry++) {
11445 unsigned char read_back;
11446 AscSetChipEEPCmd(iop_base, cmd_reg);
11448 read_back = AscGetChipEEPCmd(iop_base);
11449 if (read_back == cmd_reg)
11455 static void __devinit AscWaitEEPRead(void)
11460 static ushort __devinit AscReadEEPWord(PortAddr iop_base, uchar addr)
11465 AscWriteEEPCmdReg(iop_base, ASC_EEP_CMD_WRITE_DISABLE);
11467 cmd_reg = addr | ASC_EEP_CMD_READ;
11468 AscWriteEEPCmdReg(iop_base, cmd_reg);
11470 read_wval = AscGetChipEEPData(iop_base);
11475 static ushort __devinit
11476 AscGetEEPConfig(PortAddr iop_base, ASCEEP_CONFIG *cfg_buf, ushort bus_type)
11483 int uchar_end_in_config = ASC_EEP_MAX_DVC_ADDR - 2;
11486 wbuf = (ushort *)cfg_buf;
11488 /* Read two config words; Byte-swapping done by AscReadEEPWord(). */
11489 for (s_addr = 0; s_addr < 2; s_addr++, wbuf++) {
11490 *wbuf = AscReadEEPWord(iop_base, (uchar)s_addr);
11493 if (bus_type & ASC_IS_VL) {
11494 cfg_beg = ASC_EEP_DVC_CFG_BEG_VL;
11495 cfg_end = ASC_EEP_MAX_DVC_ADDR_VL;
11497 cfg_beg = ASC_EEP_DVC_CFG_BEG;
11498 cfg_end = ASC_EEP_MAX_DVC_ADDR;
11500 for (s_addr = cfg_beg; s_addr <= (cfg_end - 1); s_addr++, wbuf++) {
11501 wval = AscReadEEPWord(iop_base, (uchar)s_addr);
11502 if (s_addr <= uchar_end_in_config) {
11504 * Swap all char fields - must unswap bytes already swapped
11505 * by AscReadEEPWord().
11507 *wbuf = le16_to_cpu(wval);
11509 /* Don't swap word field at the end - cntl field. */
11512 sum += wval; /* Checksum treats all EEPROM data as words. */
11515 * Read the checksum word which will be compared against 'sum'
11516 * by the caller. Word field already swapped.
11518 *wbuf = AscReadEEPWord(iop_base, (uchar)s_addr);
11522 static int __devinit AscTestExternalLram(ASC_DVC_VAR *asc_dvc)
11529 iop_base = asc_dvc->iop_base;
11531 q_addr = ASC_QNO_TO_QADDR(241);
11532 saved_word = AscReadLramWord(iop_base, q_addr);
11533 AscSetChipLramAddr(iop_base, q_addr);
11534 AscSetChipLramData(iop_base, 0x55AA);
11536 AscSetChipLramAddr(iop_base, q_addr);
11537 if (AscGetChipLramData(iop_base) == 0x55AA) {
11539 AscWriteLramWord(iop_base, q_addr, saved_word);
11544 static void __devinit AscWaitEEPWrite(void)
11549 static int __devinit AscWriteEEPDataReg(PortAddr iop_base, ushort data_reg)
11556 AscSetChipEEPData(iop_base, data_reg);
11558 read_back = AscGetChipEEPData(iop_base);
11559 if (read_back == data_reg) {
11562 if (retry++ > ASC_EEP_MAX_RETRY) {
11568 static ushort __devinit
11569 AscWriteEEPWord(PortAddr iop_base, uchar addr, ushort word_val)
11573 read_wval = AscReadEEPWord(iop_base, addr);
11574 if (read_wval != word_val) {
11575 AscWriteEEPCmdReg(iop_base, ASC_EEP_CMD_WRITE_ABLE);
11577 AscWriteEEPDataReg(iop_base, word_val);
11579 AscWriteEEPCmdReg(iop_base,
11580 (uchar)((uchar)ASC_EEP_CMD_WRITE | addr));
11582 AscWriteEEPCmdReg(iop_base, ASC_EEP_CMD_WRITE_DISABLE);
11584 return (AscReadEEPWord(iop_base, addr));
11586 return (read_wval);
11589 static int __devinit
11590 AscSetEEPConfigOnce(PortAddr iop_base, ASCEEP_CONFIG *cfg_buf, ushort bus_type)
11599 int uchar_end_in_config = ASC_EEP_MAX_DVC_ADDR - 2;
11601 wbuf = (ushort *)cfg_buf;
11604 /* Write two config words; AscWriteEEPWord() will swap bytes. */
11605 for (s_addr = 0; s_addr < 2; s_addr++, wbuf++) {
11607 if (*wbuf != AscWriteEEPWord(iop_base, (uchar)s_addr, *wbuf)) {
11611 if (bus_type & ASC_IS_VL) {
11612 cfg_beg = ASC_EEP_DVC_CFG_BEG_VL;
11613 cfg_end = ASC_EEP_MAX_DVC_ADDR_VL;
11615 cfg_beg = ASC_EEP_DVC_CFG_BEG;
11616 cfg_end = ASC_EEP_MAX_DVC_ADDR;
11618 for (s_addr = cfg_beg; s_addr <= (cfg_end - 1); s_addr++, wbuf++) {
11619 if (s_addr <= uchar_end_in_config) {
11621 * This is a char field. Swap char fields before they are
11622 * swapped again by AscWriteEEPWord().
11624 word = cpu_to_le16(*wbuf);
11626 AscWriteEEPWord(iop_base, (uchar)s_addr, word)) {
11630 /* Don't swap word field at the end - cntl field. */
11632 AscWriteEEPWord(iop_base, (uchar)s_addr, *wbuf)) {
11636 sum += *wbuf; /* Checksum calculated from word values. */
11638 /* Write checksum word. It will be swapped by AscWriteEEPWord(). */
11640 if (sum != AscWriteEEPWord(iop_base, (uchar)s_addr, sum)) {
11644 /* Read EEPROM back again. */
11645 wbuf = (ushort *)cfg_buf;
11647 * Read two config words; Byte-swapping done by AscReadEEPWord().
11649 for (s_addr = 0; s_addr < 2; s_addr++, wbuf++) {
11650 if (*wbuf != AscReadEEPWord(iop_base, (uchar)s_addr)) {
11654 if (bus_type & ASC_IS_VL) {
11655 cfg_beg = ASC_EEP_DVC_CFG_BEG_VL;
11656 cfg_end = ASC_EEP_MAX_DVC_ADDR_VL;
11658 cfg_beg = ASC_EEP_DVC_CFG_BEG;
11659 cfg_end = ASC_EEP_MAX_DVC_ADDR;
11661 for (s_addr = cfg_beg; s_addr <= (cfg_end - 1); s_addr++, wbuf++) {
11662 if (s_addr <= uchar_end_in_config) {
11664 * Swap all char fields. Must unswap bytes already swapped
11665 * by AscReadEEPWord().
11668 le16_to_cpu(AscReadEEPWord
11669 (iop_base, (uchar)s_addr));
11671 /* Don't swap word field at the end - cntl field. */
11672 word = AscReadEEPWord(iop_base, (uchar)s_addr);
11674 if (*wbuf != word) {
11678 /* Read checksum; Byte swapping not needed. */
11679 if (AscReadEEPWord(iop_base, (uchar)s_addr) != sum) {
11685 static int __devinit
11686 AscSetEEPConfig(PortAddr iop_base, ASCEEP_CONFIG *cfg_buf, ushort bus_type)
11693 if ((n_error = AscSetEEPConfigOnce(iop_base, cfg_buf,
11697 if (++retry > ASC_EEP_MAX_RETRY) {
11704 static ushort __devinit AscInitFromEEP(ASC_DVC_VAR *asc_dvc)
11706 ASCEEP_CONFIG eep_config_buf;
11707 ASCEEP_CONFIG *eep_config;
11711 ushort cfg_msw, cfg_lsw;
11715 iop_base = asc_dvc->iop_base;
11717 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0x00FE);
11718 AscStopQueueExe(iop_base);
11719 if ((AscStopChip(iop_base) == FALSE) ||
11720 (AscGetChipScsiCtrl(iop_base) != 0)) {
11721 asc_dvc->init_state |= ASC_INIT_RESET_SCSI_DONE;
11722 AscResetChipAndScsiBus(asc_dvc);
11723 mdelay(asc_dvc->scsi_reset_wait * 1000); /* XXX: msleep? */
11725 if (AscIsChipHalted(iop_base) == FALSE) {
11726 asc_dvc->err_code |= ASC_IERR_START_STOP_CHIP;
11727 return (warn_code);
11729 AscSetPCAddr(iop_base, ASC_MCODE_START_ADDR);
11730 if (AscGetPCAddr(iop_base) != ASC_MCODE_START_ADDR) {
11731 asc_dvc->err_code |= ASC_IERR_SET_PC_ADDR;
11732 return (warn_code);
11734 eep_config = (ASCEEP_CONFIG *)&eep_config_buf;
11735 cfg_msw = AscGetChipCfgMsw(iop_base);
11736 cfg_lsw = AscGetChipCfgLsw(iop_base);
11737 if ((cfg_msw & ASC_CFG_MSW_CLR_MASK) != 0) {
11738 cfg_msw &= ~ASC_CFG_MSW_CLR_MASK;
11739 warn_code |= ASC_WARN_CFG_MSW_RECOVER;
11740 AscSetChipCfgMsw(iop_base, cfg_msw);
11742 chksum = AscGetEEPConfig(iop_base, eep_config, asc_dvc->bus_type);
11743 ASC_DBG(1, "chksum 0x%x\n", chksum);
11747 if (AscGetChipStatus(iop_base) & CSW_AUTO_CONFIG) {
11748 warn_code |= ASC_WARN_AUTO_CONFIG;
11749 if (asc_dvc->cfg->chip_version == 3) {
11750 if (eep_config->cfg_lsw != cfg_lsw) {
11751 warn_code |= ASC_WARN_EEPROM_RECOVER;
11752 eep_config->cfg_lsw =
11753 AscGetChipCfgLsw(iop_base);
11755 if (eep_config->cfg_msw != cfg_msw) {
11756 warn_code |= ASC_WARN_EEPROM_RECOVER;
11757 eep_config->cfg_msw =
11758 AscGetChipCfgMsw(iop_base);
11762 eep_config->cfg_msw &= ~ASC_CFG_MSW_CLR_MASK;
11763 eep_config->cfg_lsw |= ASC_CFG0_HOST_INT_ON;
11764 ASC_DBG(1, "eep_config->chksum 0x%x\n", eep_config->chksum);
11765 if (chksum != eep_config->chksum) {
11766 if (AscGetChipVersion(iop_base, asc_dvc->bus_type) ==
11767 ASC_CHIP_VER_PCI_ULTRA_3050) {
11768 ASC_DBG(1, "chksum error ignored; EEPROM-less board\n");
11769 eep_config->init_sdtr = 0xFF;
11770 eep_config->disc_enable = 0xFF;
11771 eep_config->start_motor = 0xFF;
11772 eep_config->use_cmd_qng = 0;
11773 eep_config->max_total_qng = 0xF0;
11774 eep_config->max_tag_qng = 0x20;
11775 eep_config->cntl = 0xBFFF;
11776 ASC_EEP_SET_CHIP_ID(eep_config, 7);
11777 eep_config->no_scam = 0;
11778 eep_config->adapter_info[0] = 0;
11779 eep_config->adapter_info[1] = 0;
11780 eep_config->adapter_info[2] = 0;
11781 eep_config->adapter_info[3] = 0;
11782 eep_config->adapter_info[4] = 0;
11783 /* Indicate EEPROM-less board. */
11784 eep_config->adapter_info[5] = 0xBB;
11787 ("AscInitFromEEP: EEPROM checksum error; Will try to re-write EEPROM.\n");
11789 warn_code |= ASC_WARN_EEPROM_CHKSUM;
11792 asc_dvc->cfg->sdtr_enable = eep_config->init_sdtr;
11793 asc_dvc->cfg->disc_enable = eep_config->disc_enable;
11794 asc_dvc->cfg->cmd_qng_enabled = eep_config->use_cmd_qng;
11795 asc_dvc->cfg->isa_dma_speed = ASC_EEP_GET_DMA_SPD(eep_config);
11796 asc_dvc->start_motor = eep_config->start_motor;
11797 asc_dvc->dvc_cntl = eep_config->cntl;
11798 asc_dvc->no_scam = eep_config->no_scam;
11799 asc_dvc->cfg->adapter_info[0] = eep_config->adapter_info[0];
11800 asc_dvc->cfg->adapter_info[1] = eep_config->adapter_info[1];
11801 asc_dvc->cfg->adapter_info[2] = eep_config->adapter_info[2];
11802 asc_dvc->cfg->adapter_info[3] = eep_config->adapter_info[3];
11803 asc_dvc->cfg->adapter_info[4] = eep_config->adapter_info[4];
11804 asc_dvc->cfg->adapter_info[5] = eep_config->adapter_info[5];
11805 if (!AscTestExternalLram(asc_dvc)) {
11806 if (((asc_dvc->bus_type & ASC_IS_PCI_ULTRA) ==
11807 ASC_IS_PCI_ULTRA)) {
11808 eep_config->max_total_qng =
11809 ASC_MAX_PCI_ULTRA_INRAM_TOTAL_QNG;
11810 eep_config->max_tag_qng =
11811 ASC_MAX_PCI_ULTRA_INRAM_TAG_QNG;
11813 eep_config->cfg_msw |= 0x0800;
11815 AscSetChipCfgMsw(iop_base, cfg_msw);
11816 eep_config->max_total_qng = ASC_MAX_PCI_INRAM_TOTAL_QNG;
11817 eep_config->max_tag_qng = ASC_MAX_INRAM_TAG_QNG;
11821 if (eep_config->max_total_qng < ASC_MIN_TOTAL_QNG) {
11822 eep_config->max_total_qng = ASC_MIN_TOTAL_QNG;
11824 if (eep_config->max_total_qng > ASC_MAX_TOTAL_QNG) {
11825 eep_config->max_total_qng = ASC_MAX_TOTAL_QNG;
11827 if (eep_config->max_tag_qng > eep_config->max_total_qng) {
11828 eep_config->max_tag_qng = eep_config->max_total_qng;
11830 if (eep_config->max_tag_qng < ASC_MIN_TAG_Q_PER_DVC) {
11831 eep_config->max_tag_qng = ASC_MIN_TAG_Q_PER_DVC;
11833 asc_dvc->max_total_qng = eep_config->max_total_qng;
11834 if ((eep_config->use_cmd_qng & eep_config->disc_enable) !=
11835 eep_config->use_cmd_qng) {
11836 eep_config->disc_enable = eep_config->use_cmd_qng;
11837 warn_code |= ASC_WARN_CMD_QNG_CONFLICT;
11839 ASC_EEP_SET_CHIP_ID(eep_config,
11840 ASC_EEP_GET_CHIP_ID(eep_config) & ASC_MAX_TID);
11841 asc_dvc->cfg->chip_scsi_id = ASC_EEP_GET_CHIP_ID(eep_config);
11842 if (((asc_dvc->bus_type & ASC_IS_PCI_ULTRA) == ASC_IS_PCI_ULTRA) &&
11843 !(asc_dvc->dvc_cntl & ASC_CNTL_SDTR_ENABLE_ULTRA)) {
11844 asc_dvc->min_sdtr_index = ASC_SDTR_ULTRA_PCI_10MB_INDEX;
11847 for (i = 0; i <= ASC_MAX_TID; i++) {
11848 asc_dvc->dos_int13_table[i] = eep_config->dos_int13_table[i];
11849 asc_dvc->cfg->max_tag_qng[i] = eep_config->max_tag_qng;
11850 asc_dvc->cfg->sdtr_period_offset[i] =
11851 (uchar)(ASC_DEF_SDTR_OFFSET |
11852 (asc_dvc->min_sdtr_index << 4));
11854 eep_config->cfg_msw = AscGetChipCfgMsw(iop_base);
11856 if ((i = AscSetEEPConfig(iop_base, eep_config,
11857 asc_dvc->bus_type)) != 0) {
11859 ("AscInitFromEEP: Failed to re-write EEPROM with %d errors.\n",
11863 ("AscInitFromEEP: Successfully re-wrote EEPROM.\n");
11866 return (warn_code);
11869 static int __devinit AscInitGetConfig(struct Scsi_Host *shost)
11871 struct asc_board *board = shost_priv(shost);
11872 ASC_DVC_VAR *asc_dvc = &board->dvc_var.asc_dvc_var;
11873 unsigned short warn_code = 0;
11875 asc_dvc->init_state = ASC_INIT_STATE_BEG_GET_CFG;
11876 if (asc_dvc->err_code != 0)
11877 return asc_dvc->err_code;
11879 if (AscFindSignature(asc_dvc->iop_base)) {
11880 warn_code |= AscInitAscDvcVar(asc_dvc);
11881 warn_code |= AscInitFromEEP(asc_dvc);
11882 asc_dvc->init_state |= ASC_INIT_STATE_END_GET_CFG;
11883 if (asc_dvc->scsi_reset_wait > ASC_MAX_SCSI_RESET_WAIT)
11884 asc_dvc->scsi_reset_wait = ASC_MAX_SCSI_RESET_WAIT;
11886 asc_dvc->err_code = ASC_IERR_BAD_SIGNATURE;
11889 switch (warn_code) {
11890 case 0: /* No error */
11892 case ASC_WARN_IO_PORT_ROTATE:
11893 shost_printk(KERN_WARNING, shost, "I/O port address "
11896 case ASC_WARN_AUTO_CONFIG:
11897 shost_printk(KERN_WARNING, shost, "I/O port increment switch "
11900 case ASC_WARN_EEPROM_CHKSUM:
11901 shost_printk(KERN_WARNING, shost, "EEPROM checksum error\n");
11903 case ASC_WARN_IRQ_MODIFIED:
11904 shost_printk(KERN_WARNING, shost, "IRQ modified\n");
11906 case ASC_WARN_CMD_QNG_CONFLICT:
11907 shost_printk(KERN_WARNING, shost, "tag queuing enabled w/o "
11911 shost_printk(KERN_WARNING, shost, "unknown warning: 0x%x\n",
11916 if (asc_dvc->err_code != 0)
11917 shost_printk(KERN_ERR, shost, "error 0x%x at init_state "
11918 "0x%x\n", asc_dvc->err_code, asc_dvc->init_state);
11920 return asc_dvc->err_code;
11923 static int __devinit AscInitSetConfig(struct pci_dev *pdev, struct Scsi_Host *shost)
11925 struct asc_board *board = shost_priv(shost);
11926 ASC_DVC_VAR *asc_dvc = &board->dvc_var.asc_dvc_var;
11927 PortAddr iop_base = asc_dvc->iop_base;
11928 unsigned short cfg_msw;
11929 unsigned short warn_code = 0;
11931 asc_dvc->init_state |= ASC_INIT_STATE_BEG_SET_CFG;
11932 if (asc_dvc->err_code != 0)
11933 return asc_dvc->err_code;
11934 if (!AscFindSignature(asc_dvc->iop_base)) {
11935 asc_dvc->err_code = ASC_IERR_BAD_SIGNATURE;
11936 return asc_dvc->err_code;
11939 cfg_msw = AscGetChipCfgMsw(iop_base);
11940 if ((cfg_msw & ASC_CFG_MSW_CLR_MASK) != 0) {
11941 cfg_msw &= ~ASC_CFG_MSW_CLR_MASK;
11942 warn_code |= ASC_WARN_CFG_MSW_RECOVER;
11943 AscSetChipCfgMsw(iop_base, cfg_msw);
11945 if ((asc_dvc->cfg->cmd_qng_enabled & asc_dvc->cfg->disc_enable) !=
11946 asc_dvc->cfg->cmd_qng_enabled) {
11947 asc_dvc->cfg->disc_enable = asc_dvc->cfg->cmd_qng_enabled;
11948 warn_code |= ASC_WARN_CMD_QNG_CONFLICT;
11950 if (AscGetChipStatus(iop_base) & CSW_AUTO_CONFIG) {
11951 warn_code |= ASC_WARN_AUTO_CONFIG;
11954 if (asc_dvc->bus_type & ASC_IS_PCI) {
11956 AscSetChipCfgMsw(iop_base, cfg_msw);
11957 if ((asc_dvc->bus_type & ASC_IS_PCI_ULTRA) == ASC_IS_PCI_ULTRA) {
11959 if ((pdev->device == PCI_DEVICE_ID_ASP_1200A) ||
11960 (pdev->device == PCI_DEVICE_ID_ASP_ABP940)) {
11961 asc_dvc->bug_fix_cntl |= ASC_BUG_FIX_IF_NOT_DWB;
11962 asc_dvc->bug_fix_cntl |=
11963 ASC_BUG_FIX_ASYN_USE_SYN;
11967 #endif /* CONFIG_PCI */
11968 if (asc_dvc->bus_type == ASC_IS_ISAPNP) {
11969 if (AscGetChipVersion(iop_base, asc_dvc->bus_type)
11970 == ASC_CHIP_VER_ASYN_BUG) {
11971 asc_dvc->bug_fix_cntl |= ASC_BUG_FIX_ASYN_USE_SYN;
11974 if (AscSetChipScsiID(iop_base, asc_dvc->cfg->chip_scsi_id) !=
11975 asc_dvc->cfg->chip_scsi_id) {
11976 asc_dvc->err_code |= ASC_IERR_SET_SCSI_ID;
11979 if (asc_dvc->bus_type & ASC_IS_ISA) {
11980 AscSetIsaDmaChannel(iop_base, asc_dvc->cfg->isa_dma_channel);
11981 AscSetIsaDmaSpeed(iop_base, asc_dvc->cfg->isa_dma_speed);
11983 #endif /* CONFIG_ISA */
11985 asc_dvc->init_state |= ASC_INIT_STATE_END_SET_CFG;
11987 switch (warn_code) {
11988 case 0: /* No error. */
11990 case ASC_WARN_IO_PORT_ROTATE:
11991 shost_printk(KERN_WARNING, shost, "I/O port address "
11994 case ASC_WARN_AUTO_CONFIG:
11995 shost_printk(KERN_WARNING, shost, "I/O port increment switch "
11998 case ASC_WARN_EEPROM_CHKSUM:
11999 shost_printk(KERN_WARNING, shost, "EEPROM checksum error\n");
12001 case ASC_WARN_IRQ_MODIFIED:
12002 shost_printk(KERN_WARNING, shost, "IRQ modified\n");
12004 case ASC_WARN_CMD_QNG_CONFLICT:
12005 shost_printk(KERN_WARNING, shost, "tag queuing w/o "
12009 shost_printk(KERN_WARNING, shost, "unknown warning: 0x%x\n",
12014 if (asc_dvc->err_code != 0)
12015 shost_printk(KERN_ERR, shost, "error 0x%x at init_state "
12016 "0x%x\n", asc_dvc->err_code, asc_dvc->init_state);
12018 return asc_dvc->err_code;
12022 * EEPROM Configuration.
12024 * All drivers should use this structure to set the default EEPROM
12025 * configuration. The BIOS now uses this structure when it is built.
12026 * Additional structure information can be found in a_condor.h where
12027 * the structure is defined.
12029 * The *_Field_IsChar structs are needed to correct for endianness.
12030 * These values are read from the board 16 bits at a time directly
12031 * into the structs. Because some fields are char, the values will be
12032 * in the wrong order. The *_Field_IsChar tells when to flip the
12033 * bytes. Data read and written to PCI memory is automatically swapped
12034 * on big-endian platforms so char fields read as words are actually being
12035 * unswapped on big-endian platforms.
12037 static ADVEEP_3550_CONFIG Default_3550_EEPROM_Config __devinitdata = {
12038 ADV_EEPROM_BIOS_ENABLE, /* cfg_lsw */
12039 0x0000, /* cfg_msw */
12040 0xFFFF, /* disc_enable */
12041 0xFFFF, /* wdtr_able */
12042 0xFFFF, /* sdtr_able */
12043 0xFFFF, /* start_motor */
12044 0xFFFF, /* tagqng_able */
12045 0xFFFF, /* bios_scan */
12046 0, /* scam_tolerant */
12047 7, /* adapter_scsi_id */
12048 0, /* bios_boot_delay */
12049 3, /* scsi_reset_delay */
12050 0, /* bios_id_lun */
12051 0, /* termination */
12053 0xFFE7, /* bios_ctrl */
12054 0xFFFF, /* ultra_able */
12056 ASC_DEF_MAX_HOST_QNG, /* max_host_qng */
12057 ASC_DEF_MAX_DVC_QNG, /* max_dvc_qng */
12060 0, /* serial_number_word1 */
12061 0, /* serial_number_word2 */
12062 0, /* serial_number_word3 */
12064 {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
12065 , /* oem_name[16] */
12066 0, /* dvc_err_code */
12067 0, /* adv_err_code */
12068 0, /* adv_err_addr */
12069 0, /* saved_dvc_err_code */
12070 0, /* saved_adv_err_code */
12071 0, /* saved_adv_err_addr */
12075 static ADVEEP_3550_CONFIG ADVEEP_3550_Config_Field_IsChar __devinitdata = {
12078 0, /* -disc_enable */
12081 0, /* start_motor */
12082 0, /* tagqng_able */
12084 0, /* scam_tolerant */
12085 1, /* adapter_scsi_id */
12086 1, /* bios_boot_delay */
12087 1, /* scsi_reset_delay */
12088 1, /* bios_id_lun */
12089 1, /* termination */
12092 0, /* ultra_able */
12094 1, /* max_host_qng */
12095 1, /* max_dvc_qng */
12098 0, /* serial_number_word1 */
12099 0, /* serial_number_word2 */
12100 0, /* serial_number_word3 */
12102 {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1}
12103 , /* oem_name[16] */
12104 0, /* dvc_err_code */
12105 0, /* adv_err_code */
12106 0, /* adv_err_addr */
12107 0, /* saved_dvc_err_code */
12108 0, /* saved_adv_err_code */
12109 0, /* saved_adv_err_addr */
12113 static ADVEEP_38C0800_CONFIG Default_38C0800_EEPROM_Config __devinitdata = {
12114 ADV_EEPROM_BIOS_ENABLE, /* 00 cfg_lsw */
12115 0x0000, /* 01 cfg_msw */
12116 0xFFFF, /* 02 disc_enable */
12117 0xFFFF, /* 03 wdtr_able */
12118 0x4444, /* 04 sdtr_speed1 */
12119 0xFFFF, /* 05 start_motor */
12120 0xFFFF, /* 06 tagqng_able */
12121 0xFFFF, /* 07 bios_scan */
12122 0, /* 08 scam_tolerant */
12123 7, /* 09 adapter_scsi_id */
12124 0, /* bios_boot_delay */
12125 3, /* 10 scsi_reset_delay */
12126 0, /* bios_id_lun */
12127 0, /* 11 termination_se */
12128 0, /* termination_lvd */
12129 0xFFE7, /* 12 bios_ctrl */
12130 0x4444, /* 13 sdtr_speed2 */
12131 0x4444, /* 14 sdtr_speed3 */
12132 ASC_DEF_MAX_HOST_QNG, /* 15 max_host_qng */
12133 ASC_DEF_MAX_DVC_QNG, /* max_dvc_qng */
12134 0, /* 16 dvc_cntl */
12135 0x4444, /* 17 sdtr_speed4 */
12136 0, /* 18 serial_number_word1 */
12137 0, /* 19 serial_number_word2 */
12138 0, /* 20 serial_number_word3 */
12139 0, /* 21 check_sum */
12140 {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
12141 , /* 22-29 oem_name[16] */
12142 0, /* 30 dvc_err_code */
12143 0, /* 31 adv_err_code */
12144 0, /* 32 adv_err_addr */
12145 0, /* 33 saved_dvc_err_code */
12146 0, /* 34 saved_adv_err_code */
12147 0, /* 35 saved_adv_err_addr */
12148 0, /* 36 reserved */
12149 0, /* 37 reserved */
12150 0, /* 38 reserved */
12151 0, /* 39 reserved */
12152 0, /* 40 reserved */
12153 0, /* 41 reserved */
12154 0, /* 42 reserved */
12155 0, /* 43 reserved */
12156 0, /* 44 reserved */
12157 0, /* 45 reserved */
12158 0, /* 46 reserved */
12159 0, /* 47 reserved */
12160 0, /* 48 reserved */
12161 0, /* 49 reserved */
12162 0, /* 50 reserved */
12163 0, /* 51 reserved */
12164 0, /* 52 reserved */
12165 0, /* 53 reserved */
12166 0, /* 54 reserved */
12167 0, /* 55 reserved */
12168 0, /* 56 cisptr_lsw */
12169 0, /* 57 cisprt_msw */
12170 PCI_VENDOR_ID_ASP, /* 58 subsysvid */
12171 PCI_DEVICE_ID_38C0800_REV1, /* 59 subsysid */
12172 0, /* 60 reserved */
12173 0, /* 61 reserved */
12174 0, /* 62 reserved */
12175 0 /* 63 reserved */
12178 static ADVEEP_38C0800_CONFIG ADVEEP_38C0800_Config_Field_IsChar __devinitdata = {
12179 0, /* 00 cfg_lsw */
12180 0, /* 01 cfg_msw */
12181 0, /* 02 disc_enable */
12182 0, /* 03 wdtr_able */
12183 0, /* 04 sdtr_speed1 */
12184 0, /* 05 start_motor */
12185 0, /* 06 tagqng_able */
12186 0, /* 07 bios_scan */
12187 0, /* 08 scam_tolerant */
12188 1, /* 09 adapter_scsi_id */
12189 1, /* bios_boot_delay */
12190 1, /* 10 scsi_reset_delay */
12191 1, /* bios_id_lun */
12192 1, /* 11 termination_se */
12193 1, /* termination_lvd */
12194 0, /* 12 bios_ctrl */
12195 0, /* 13 sdtr_speed2 */
12196 0, /* 14 sdtr_speed3 */
12197 1, /* 15 max_host_qng */
12198 1, /* max_dvc_qng */
12199 0, /* 16 dvc_cntl */
12200 0, /* 17 sdtr_speed4 */
12201 0, /* 18 serial_number_word1 */
12202 0, /* 19 serial_number_word2 */
12203 0, /* 20 serial_number_word3 */
12204 0, /* 21 check_sum */
12205 {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1}
12206 , /* 22-29 oem_name[16] */
12207 0, /* 30 dvc_err_code */
12208 0, /* 31 adv_err_code */
12209 0, /* 32 adv_err_addr */
12210 0, /* 33 saved_dvc_err_code */
12211 0, /* 34 saved_adv_err_code */
12212 0, /* 35 saved_adv_err_addr */
12213 0, /* 36 reserved */
12214 0, /* 37 reserved */
12215 0, /* 38 reserved */
12216 0, /* 39 reserved */
12217 0, /* 40 reserved */
12218 0, /* 41 reserved */
12219 0, /* 42 reserved */
12220 0, /* 43 reserved */
12221 0, /* 44 reserved */
12222 0, /* 45 reserved */
12223 0, /* 46 reserved */
12224 0, /* 47 reserved */
12225 0, /* 48 reserved */
12226 0, /* 49 reserved */
12227 0, /* 50 reserved */
12228 0, /* 51 reserved */
12229 0, /* 52 reserved */
12230 0, /* 53 reserved */
12231 0, /* 54 reserved */
12232 0, /* 55 reserved */
12233 0, /* 56 cisptr_lsw */
12234 0, /* 57 cisprt_msw */
12235 0, /* 58 subsysvid */
12236 0, /* 59 subsysid */
12237 0, /* 60 reserved */
12238 0, /* 61 reserved */
12239 0, /* 62 reserved */
12240 0 /* 63 reserved */
12243 static ADVEEP_38C1600_CONFIG Default_38C1600_EEPROM_Config __devinitdata = {
12244 ADV_EEPROM_BIOS_ENABLE, /* 00 cfg_lsw */
12245 0x0000, /* 01 cfg_msw */
12246 0xFFFF, /* 02 disc_enable */
12247 0xFFFF, /* 03 wdtr_able */
12248 0x5555, /* 04 sdtr_speed1 */
12249 0xFFFF, /* 05 start_motor */
12250 0xFFFF, /* 06 tagqng_able */
12251 0xFFFF, /* 07 bios_scan */
12252 0, /* 08 scam_tolerant */
12253 7, /* 09 adapter_scsi_id */
12254 0, /* bios_boot_delay */
12255 3, /* 10 scsi_reset_delay */
12256 0, /* bios_id_lun */
12257 0, /* 11 termination_se */
12258 0, /* termination_lvd */
12259 0xFFE7, /* 12 bios_ctrl */
12260 0x5555, /* 13 sdtr_speed2 */
12261 0x5555, /* 14 sdtr_speed3 */
12262 ASC_DEF_MAX_HOST_QNG, /* 15 max_host_qng */
12263 ASC_DEF_MAX_DVC_QNG, /* max_dvc_qng */
12264 0, /* 16 dvc_cntl */
12265 0x5555, /* 17 sdtr_speed4 */
12266 0, /* 18 serial_number_word1 */
12267 0, /* 19 serial_number_word2 */
12268 0, /* 20 serial_number_word3 */
12269 0, /* 21 check_sum */
12270 {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
12271 , /* 22-29 oem_name[16] */
12272 0, /* 30 dvc_err_code */
12273 0, /* 31 adv_err_code */
12274 0, /* 32 adv_err_addr */
12275 0, /* 33 saved_dvc_err_code */
12276 0, /* 34 saved_adv_err_code */
12277 0, /* 35 saved_adv_err_addr */
12278 0, /* 36 reserved */
12279 0, /* 37 reserved */
12280 0, /* 38 reserved */
12281 0, /* 39 reserved */
12282 0, /* 40 reserved */
12283 0, /* 41 reserved */
12284 0, /* 42 reserved */
12285 0, /* 43 reserved */
12286 0, /* 44 reserved */
12287 0, /* 45 reserved */
12288 0, /* 46 reserved */
12289 0, /* 47 reserved */
12290 0, /* 48 reserved */
12291 0, /* 49 reserved */
12292 0, /* 50 reserved */
12293 0, /* 51 reserved */
12294 0, /* 52 reserved */
12295 0, /* 53 reserved */
12296 0, /* 54 reserved */
12297 0, /* 55 reserved */
12298 0, /* 56 cisptr_lsw */
12299 0, /* 57 cisprt_msw */
12300 PCI_VENDOR_ID_ASP, /* 58 subsysvid */
12301 PCI_DEVICE_ID_38C1600_REV1, /* 59 subsysid */
12302 0, /* 60 reserved */
12303 0, /* 61 reserved */
12304 0, /* 62 reserved */
12305 0 /* 63 reserved */
12308 static ADVEEP_38C1600_CONFIG ADVEEP_38C1600_Config_Field_IsChar __devinitdata = {
12309 0, /* 00 cfg_lsw */
12310 0, /* 01 cfg_msw */
12311 0, /* 02 disc_enable */
12312 0, /* 03 wdtr_able */
12313 0, /* 04 sdtr_speed1 */
12314 0, /* 05 start_motor */
12315 0, /* 06 tagqng_able */
12316 0, /* 07 bios_scan */
12317 0, /* 08 scam_tolerant */
12318 1, /* 09 adapter_scsi_id */
12319 1, /* bios_boot_delay */
12320 1, /* 10 scsi_reset_delay */
12321 1, /* bios_id_lun */
12322 1, /* 11 termination_se */
12323 1, /* termination_lvd */
12324 0, /* 12 bios_ctrl */
12325 0, /* 13 sdtr_speed2 */
12326 0, /* 14 sdtr_speed3 */
12327 1, /* 15 max_host_qng */
12328 1, /* max_dvc_qng */
12329 0, /* 16 dvc_cntl */
12330 0, /* 17 sdtr_speed4 */
12331 0, /* 18 serial_number_word1 */
12332 0, /* 19 serial_number_word2 */
12333 0, /* 20 serial_number_word3 */
12334 0, /* 21 check_sum */
12335 {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1}
12336 , /* 22-29 oem_name[16] */
12337 0, /* 30 dvc_err_code */
12338 0, /* 31 adv_err_code */
12339 0, /* 32 adv_err_addr */
12340 0, /* 33 saved_dvc_err_code */
12341 0, /* 34 saved_adv_err_code */
12342 0, /* 35 saved_adv_err_addr */
12343 0, /* 36 reserved */
12344 0, /* 37 reserved */
12345 0, /* 38 reserved */
12346 0, /* 39 reserved */
12347 0, /* 40 reserved */
12348 0, /* 41 reserved */
12349 0, /* 42 reserved */
12350 0, /* 43 reserved */
12351 0, /* 44 reserved */
12352 0, /* 45 reserved */
12353 0, /* 46 reserved */
12354 0, /* 47 reserved */
12355 0, /* 48 reserved */
12356 0, /* 49 reserved */
12357 0, /* 50 reserved */
12358 0, /* 51 reserved */
12359 0, /* 52 reserved */
12360 0, /* 53 reserved */
12361 0, /* 54 reserved */
12362 0, /* 55 reserved */
12363 0, /* 56 cisptr_lsw */
12364 0, /* 57 cisprt_msw */
12365 0, /* 58 subsysvid */
12366 0, /* 59 subsysid */
12367 0, /* 60 reserved */
12368 0, /* 61 reserved */
12369 0, /* 62 reserved */
12370 0 /* 63 reserved */
12375 * Wait for EEPROM command to complete
12377 static void __devinit AdvWaitEEPCmd(AdvPortAddr iop_base)
12381 for (eep_delay_ms = 0; eep_delay_ms < ADV_EEP_DELAY_MS; eep_delay_ms++) {
12382 if (AdvReadWordRegister(iop_base, IOPW_EE_CMD) &
12383 ASC_EEP_CMD_DONE) {
12388 if ((AdvReadWordRegister(iop_base, IOPW_EE_CMD) & ASC_EEP_CMD_DONE) ==
12394 * Read the EEPROM from specified location
12396 static ushort __devinit AdvReadEEPWord(AdvPortAddr iop_base, int eep_word_addr)
12398 AdvWriteWordRegister(iop_base, IOPW_EE_CMD,
12399 ASC_EEP_CMD_READ | eep_word_addr);
12400 AdvWaitEEPCmd(iop_base);
12401 return AdvReadWordRegister(iop_base, IOPW_EE_DATA);
12405 * Write the EEPROM from 'cfg_buf'.
12408 AdvSet3550EEPConfig(AdvPortAddr iop_base, ADVEEP_3550_CONFIG *cfg_buf)
12411 ushort addr, chksum;
12412 ushort *charfields;
12414 wbuf = (ushort *)cfg_buf;
12415 charfields = (ushort *)&ADVEEP_3550_Config_Field_IsChar;
12418 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE_ABLE);
12419 AdvWaitEEPCmd(iop_base);
12422 * Write EEPROM from word 0 to word 20.
12424 for (addr = ADV_EEP_DVC_CFG_BEGIN;
12425 addr < ADV_EEP_DVC_CFG_END; addr++, wbuf++) {
12428 if (*charfields++) {
12429 word = cpu_to_le16(*wbuf);
12433 chksum += *wbuf; /* Checksum is calculated from word values. */
12434 AdvWriteWordRegister(iop_base, IOPW_EE_DATA, word);
12435 AdvWriteWordRegister(iop_base, IOPW_EE_CMD,
12436 ASC_EEP_CMD_WRITE | addr);
12437 AdvWaitEEPCmd(iop_base);
12438 mdelay(ADV_EEP_DELAY_MS);
12442 * Write EEPROM checksum at word 21.
12444 AdvWriteWordRegister(iop_base, IOPW_EE_DATA, chksum);
12445 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE | addr);
12446 AdvWaitEEPCmd(iop_base);
12451 * Write EEPROM OEM name at words 22 to 29.
12453 for (addr = ADV_EEP_DVC_CTL_BEGIN;
12454 addr < ADV_EEP_MAX_WORD_ADDR; addr++, wbuf++) {
12457 if (*charfields++) {
12458 word = cpu_to_le16(*wbuf);
12462 AdvWriteWordRegister(iop_base, IOPW_EE_DATA, word);
12463 AdvWriteWordRegister(iop_base, IOPW_EE_CMD,
12464 ASC_EEP_CMD_WRITE | addr);
12465 AdvWaitEEPCmd(iop_base);
12467 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE_DISABLE);
12468 AdvWaitEEPCmd(iop_base);
12472 * Write the EEPROM from 'cfg_buf'.
12475 AdvSet38C0800EEPConfig(AdvPortAddr iop_base, ADVEEP_38C0800_CONFIG *cfg_buf)
12478 ushort *charfields;
12479 ushort addr, chksum;
12481 wbuf = (ushort *)cfg_buf;
12482 charfields = (ushort *)&ADVEEP_38C0800_Config_Field_IsChar;
12485 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE_ABLE);
12486 AdvWaitEEPCmd(iop_base);
12489 * Write EEPROM from word 0 to word 20.
12491 for (addr = ADV_EEP_DVC_CFG_BEGIN;
12492 addr < ADV_EEP_DVC_CFG_END; addr++, wbuf++) {
12495 if (*charfields++) {
12496 word = cpu_to_le16(*wbuf);
12500 chksum += *wbuf; /* Checksum is calculated from word values. */
12501 AdvWriteWordRegister(iop_base, IOPW_EE_DATA, word);
12502 AdvWriteWordRegister(iop_base, IOPW_EE_CMD,
12503 ASC_EEP_CMD_WRITE | addr);
12504 AdvWaitEEPCmd(iop_base);
12505 mdelay(ADV_EEP_DELAY_MS);
12509 * Write EEPROM checksum at word 21.
12511 AdvWriteWordRegister(iop_base, IOPW_EE_DATA, chksum);
12512 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE | addr);
12513 AdvWaitEEPCmd(iop_base);
12518 * Write EEPROM OEM name at words 22 to 29.
12520 for (addr = ADV_EEP_DVC_CTL_BEGIN;
12521 addr < ADV_EEP_MAX_WORD_ADDR; addr++, wbuf++) {
12524 if (*charfields++) {
12525 word = cpu_to_le16(*wbuf);
12529 AdvWriteWordRegister(iop_base, IOPW_EE_DATA, word);
12530 AdvWriteWordRegister(iop_base, IOPW_EE_CMD,
12531 ASC_EEP_CMD_WRITE | addr);
12532 AdvWaitEEPCmd(iop_base);
12534 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE_DISABLE);
12535 AdvWaitEEPCmd(iop_base);
12539 * Write the EEPROM from 'cfg_buf'.
12542 AdvSet38C1600EEPConfig(AdvPortAddr iop_base, ADVEEP_38C1600_CONFIG *cfg_buf)
12545 ushort *charfields;
12546 ushort addr, chksum;
12548 wbuf = (ushort *)cfg_buf;
12549 charfields = (ushort *)&ADVEEP_38C1600_Config_Field_IsChar;
12552 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE_ABLE);
12553 AdvWaitEEPCmd(iop_base);
12556 * Write EEPROM from word 0 to word 20.
12558 for (addr = ADV_EEP_DVC_CFG_BEGIN;
12559 addr < ADV_EEP_DVC_CFG_END; addr++, wbuf++) {
12562 if (*charfields++) {
12563 word = cpu_to_le16(*wbuf);
12567 chksum += *wbuf; /* Checksum is calculated from word values. */
12568 AdvWriteWordRegister(iop_base, IOPW_EE_DATA, word);
12569 AdvWriteWordRegister(iop_base, IOPW_EE_CMD,
12570 ASC_EEP_CMD_WRITE | addr);
12571 AdvWaitEEPCmd(iop_base);
12572 mdelay(ADV_EEP_DELAY_MS);
12576 * Write EEPROM checksum at word 21.
12578 AdvWriteWordRegister(iop_base, IOPW_EE_DATA, chksum);
12579 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE | addr);
12580 AdvWaitEEPCmd(iop_base);
12585 * Write EEPROM OEM name at words 22 to 29.
12587 for (addr = ADV_EEP_DVC_CTL_BEGIN;
12588 addr < ADV_EEP_MAX_WORD_ADDR; addr++, wbuf++) {
12591 if (*charfields++) {
12592 word = cpu_to_le16(*wbuf);
12596 AdvWriteWordRegister(iop_base, IOPW_EE_DATA, word);
12597 AdvWriteWordRegister(iop_base, IOPW_EE_CMD,
12598 ASC_EEP_CMD_WRITE | addr);
12599 AdvWaitEEPCmd(iop_base);
12601 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE_DISABLE);
12602 AdvWaitEEPCmd(iop_base);
12606 * Read EEPROM configuration into the specified buffer.
12608 * Return a checksum based on the EEPROM configuration read.
12610 static ushort __devinit
12611 AdvGet3550EEPConfig(AdvPortAddr iop_base, ADVEEP_3550_CONFIG *cfg_buf)
12613 ushort wval, chksum;
12616 ushort *charfields;
12618 charfields = (ushort *)&ADVEEP_3550_Config_Field_IsChar;
12619 wbuf = (ushort *)cfg_buf;
12622 for (eep_addr = ADV_EEP_DVC_CFG_BEGIN;
12623 eep_addr < ADV_EEP_DVC_CFG_END; eep_addr++, wbuf++) {
12624 wval = AdvReadEEPWord(iop_base, eep_addr);
12625 chksum += wval; /* Checksum is calculated from word values. */
12626 if (*charfields++) {
12627 *wbuf = le16_to_cpu(wval);
12632 /* Read checksum word. */
12633 *wbuf = AdvReadEEPWord(iop_base, eep_addr);
12637 /* Read rest of EEPROM not covered by the checksum. */
12638 for (eep_addr = ADV_EEP_DVC_CTL_BEGIN;
12639 eep_addr < ADV_EEP_MAX_WORD_ADDR; eep_addr++, wbuf++) {
12640 *wbuf = AdvReadEEPWord(iop_base, eep_addr);
12641 if (*charfields++) {
12642 *wbuf = le16_to_cpu(*wbuf);
12649 * Read EEPROM configuration into the specified buffer.
12651 * Return a checksum based on the EEPROM configuration read.
12653 static ushort __devinit
12654 AdvGet38C0800EEPConfig(AdvPortAddr iop_base, ADVEEP_38C0800_CONFIG *cfg_buf)
12656 ushort wval, chksum;
12659 ushort *charfields;
12661 charfields = (ushort *)&ADVEEP_38C0800_Config_Field_IsChar;
12662 wbuf = (ushort *)cfg_buf;
12665 for (eep_addr = ADV_EEP_DVC_CFG_BEGIN;
12666 eep_addr < ADV_EEP_DVC_CFG_END; eep_addr++, wbuf++) {
12667 wval = AdvReadEEPWord(iop_base, eep_addr);
12668 chksum += wval; /* Checksum is calculated from word values. */
12669 if (*charfields++) {
12670 *wbuf = le16_to_cpu(wval);
12675 /* Read checksum word. */
12676 *wbuf = AdvReadEEPWord(iop_base, eep_addr);
12680 /* Read rest of EEPROM not covered by the checksum. */
12681 for (eep_addr = ADV_EEP_DVC_CTL_BEGIN;
12682 eep_addr < ADV_EEP_MAX_WORD_ADDR; eep_addr++, wbuf++) {
12683 *wbuf = AdvReadEEPWord(iop_base, eep_addr);
12684 if (*charfields++) {
12685 *wbuf = le16_to_cpu(*wbuf);
12692 * Read EEPROM configuration into the specified buffer.
12694 * Return a checksum based on the EEPROM configuration read.
12696 static ushort __devinit
12697 AdvGet38C1600EEPConfig(AdvPortAddr iop_base, ADVEEP_38C1600_CONFIG *cfg_buf)
12699 ushort wval, chksum;
12702 ushort *charfields;
12704 charfields = (ushort *)&ADVEEP_38C1600_Config_Field_IsChar;
12705 wbuf = (ushort *)cfg_buf;
12708 for (eep_addr = ADV_EEP_DVC_CFG_BEGIN;
12709 eep_addr < ADV_EEP_DVC_CFG_END; eep_addr++, wbuf++) {
12710 wval = AdvReadEEPWord(iop_base, eep_addr);
12711 chksum += wval; /* Checksum is calculated from word values. */
12712 if (*charfields++) {
12713 *wbuf = le16_to_cpu(wval);
12718 /* Read checksum word. */
12719 *wbuf = AdvReadEEPWord(iop_base, eep_addr);
12723 /* Read rest of EEPROM not covered by the checksum. */
12724 for (eep_addr = ADV_EEP_DVC_CTL_BEGIN;
12725 eep_addr < ADV_EEP_MAX_WORD_ADDR; eep_addr++, wbuf++) {
12726 *wbuf = AdvReadEEPWord(iop_base, eep_addr);
12727 if (*charfields++) {
12728 *wbuf = le16_to_cpu(*wbuf);
12735 * Read the board's EEPROM configuration. Set fields in ADV_DVC_VAR and
12736 * ADV_DVC_CFG based on the EEPROM settings. The chip is stopped while
12737 * all of this is done.
12739 * On failure set the ADV_DVC_VAR field 'err_code' and return ADV_ERROR.
12741 * For a non-fatal error return a warning code. If there are no warnings
12742 * then 0 is returned.
12744 * Note: Chip is stopped on entry.
12746 static int __devinit AdvInitFrom3550EEP(ADV_DVC_VAR *asc_dvc)
12748 AdvPortAddr iop_base;
12750 ADVEEP_3550_CONFIG eep_config;
12752 iop_base = asc_dvc->iop_base;
12757 * Read the board's EEPROM configuration.
12759 * Set default values if a bad checksum is found.
12761 if (AdvGet3550EEPConfig(iop_base, &eep_config) != eep_config.check_sum) {
12762 warn_code |= ASC_WARN_EEPROM_CHKSUM;
12765 * Set EEPROM default values.
12767 memcpy(&eep_config, &Default_3550_EEPROM_Config,
12768 sizeof(ADVEEP_3550_CONFIG));
12771 * Assume the 6 byte board serial number that was read from
12772 * EEPROM is correct even if the EEPROM checksum failed.
12774 eep_config.serial_number_word3 =
12775 AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 1);
12777 eep_config.serial_number_word2 =
12778 AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 2);
12780 eep_config.serial_number_word1 =
12781 AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 3);
12783 AdvSet3550EEPConfig(iop_base, &eep_config);
12786 * Set ASC_DVC_VAR and ASC_DVC_CFG variables from the
12787 * EEPROM configuration that was read.
12789 * This is the mapping of EEPROM fields to Adv Library fields.
12791 asc_dvc->wdtr_able = eep_config.wdtr_able;
12792 asc_dvc->sdtr_able = eep_config.sdtr_able;
12793 asc_dvc->ultra_able = eep_config.ultra_able;
12794 asc_dvc->tagqng_able = eep_config.tagqng_able;
12795 asc_dvc->cfg->disc_enable = eep_config.disc_enable;
12796 asc_dvc->max_host_qng = eep_config.max_host_qng;
12797 asc_dvc->max_dvc_qng = eep_config.max_dvc_qng;
12798 asc_dvc->chip_scsi_id = (eep_config.adapter_scsi_id & ADV_MAX_TID);
12799 asc_dvc->start_motor = eep_config.start_motor;
12800 asc_dvc->scsi_reset_wait = eep_config.scsi_reset_delay;
12801 asc_dvc->bios_ctrl = eep_config.bios_ctrl;
12802 asc_dvc->no_scam = eep_config.scam_tolerant;
12803 asc_dvc->cfg->serial1 = eep_config.serial_number_word1;
12804 asc_dvc->cfg->serial2 = eep_config.serial_number_word2;
12805 asc_dvc->cfg->serial3 = eep_config.serial_number_word3;
12808 * Set the host maximum queuing (max. 253, min. 16) and the per device
12809 * maximum queuing (max. 63, min. 4).
12811 if (eep_config.max_host_qng > ASC_DEF_MAX_HOST_QNG) {
12812 eep_config.max_host_qng = ASC_DEF_MAX_HOST_QNG;
12813 } else if (eep_config.max_host_qng < ASC_DEF_MIN_HOST_QNG) {
12814 /* If the value is zero, assume it is uninitialized. */
12815 if (eep_config.max_host_qng == 0) {
12816 eep_config.max_host_qng = ASC_DEF_MAX_HOST_QNG;
12818 eep_config.max_host_qng = ASC_DEF_MIN_HOST_QNG;
12822 if (eep_config.max_dvc_qng > ASC_DEF_MAX_DVC_QNG) {
12823 eep_config.max_dvc_qng = ASC_DEF_MAX_DVC_QNG;
12824 } else if (eep_config.max_dvc_qng < ASC_DEF_MIN_DVC_QNG) {
12825 /* If the value is zero, assume it is uninitialized. */
12826 if (eep_config.max_dvc_qng == 0) {
12827 eep_config.max_dvc_qng = ASC_DEF_MAX_DVC_QNG;
12829 eep_config.max_dvc_qng = ASC_DEF_MIN_DVC_QNG;
12834 * If 'max_dvc_qng' is greater than 'max_host_qng', then
12835 * set 'max_dvc_qng' to 'max_host_qng'.
12837 if (eep_config.max_dvc_qng > eep_config.max_host_qng) {
12838 eep_config.max_dvc_qng = eep_config.max_host_qng;
12842 * Set ADV_DVC_VAR 'max_host_qng' and ADV_DVC_VAR 'max_dvc_qng'
12843 * values based on possibly adjusted EEPROM values.
12845 asc_dvc->max_host_qng = eep_config.max_host_qng;
12846 asc_dvc->max_dvc_qng = eep_config.max_dvc_qng;
12849 * If the EEPROM 'termination' field is set to automatic (0), then set
12850 * the ADV_DVC_CFG 'termination' field to automatic also.
12852 * If the termination is specified with a non-zero 'termination'
12853 * value check that a legal value is set and set the ADV_DVC_CFG
12854 * 'termination' field appropriately.
12856 if (eep_config.termination == 0) {
12857 asc_dvc->cfg->termination = 0; /* auto termination */
12859 /* Enable manual control with low off / high off. */
12860 if (eep_config.termination == 1) {
12861 asc_dvc->cfg->termination = TERM_CTL_SEL;
12863 /* Enable manual control with low off / high on. */
12864 } else if (eep_config.termination == 2) {
12865 asc_dvc->cfg->termination = TERM_CTL_SEL | TERM_CTL_H;
12867 /* Enable manual control with low on / high on. */
12868 } else if (eep_config.termination == 3) {
12869 asc_dvc->cfg->termination =
12870 TERM_CTL_SEL | TERM_CTL_H | TERM_CTL_L;
12873 * The EEPROM 'termination' field contains a bad value. Use
12874 * automatic termination instead.
12876 asc_dvc->cfg->termination = 0;
12877 warn_code |= ASC_WARN_EEPROM_TERMINATION;
12885 * Read the board's EEPROM configuration. Set fields in ADV_DVC_VAR and
12886 * ADV_DVC_CFG based on the EEPROM settings. The chip is stopped while
12887 * all of this is done.
12889 * On failure set the ADV_DVC_VAR field 'err_code' and return ADV_ERROR.
12891 * For a non-fatal error return a warning code. If there are no warnings
12892 * then 0 is returned.
12894 * Note: Chip is stopped on entry.
12896 static int __devinit AdvInitFrom38C0800EEP(ADV_DVC_VAR *asc_dvc)
12898 AdvPortAddr iop_base;
12900 ADVEEP_38C0800_CONFIG eep_config;
12901 uchar tid, termination;
12902 ushort sdtr_speed = 0;
12904 iop_base = asc_dvc->iop_base;
12909 * Read the board's EEPROM configuration.
12911 * Set default values if a bad checksum is found.
12913 if (AdvGet38C0800EEPConfig(iop_base, &eep_config) !=
12914 eep_config.check_sum) {
12915 warn_code |= ASC_WARN_EEPROM_CHKSUM;
12918 * Set EEPROM default values.
12920 memcpy(&eep_config, &Default_38C0800_EEPROM_Config,
12921 sizeof(ADVEEP_38C0800_CONFIG));
12924 * Assume the 6 byte board serial number that was read from
12925 * EEPROM is correct even if the EEPROM checksum failed.
12927 eep_config.serial_number_word3 =
12928 AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 1);
12930 eep_config.serial_number_word2 =
12931 AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 2);
12933 eep_config.serial_number_word1 =
12934 AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 3);
12936 AdvSet38C0800EEPConfig(iop_base, &eep_config);
12939 * Set ADV_DVC_VAR and ADV_DVC_CFG variables from the
12940 * EEPROM configuration that was read.
12942 * This is the mapping of EEPROM fields to Adv Library fields.
12944 asc_dvc->wdtr_able = eep_config.wdtr_able;
12945 asc_dvc->sdtr_speed1 = eep_config.sdtr_speed1;
12946 asc_dvc->sdtr_speed2 = eep_config.sdtr_speed2;
12947 asc_dvc->sdtr_speed3 = eep_config.sdtr_speed3;
12948 asc_dvc->sdtr_speed4 = eep_config.sdtr_speed4;
12949 asc_dvc->tagqng_able = eep_config.tagqng_able;
12950 asc_dvc->cfg->disc_enable = eep_config.disc_enable;
12951 asc_dvc->max_host_qng = eep_config.max_host_qng;
12952 asc_dvc->max_dvc_qng = eep_config.max_dvc_qng;
12953 asc_dvc->chip_scsi_id = (eep_config.adapter_scsi_id & ADV_MAX_TID);
12954 asc_dvc->start_motor = eep_config.start_motor;
12955 asc_dvc->scsi_reset_wait = eep_config.scsi_reset_delay;
12956 asc_dvc->bios_ctrl = eep_config.bios_ctrl;
12957 asc_dvc->no_scam = eep_config.scam_tolerant;
12958 asc_dvc->cfg->serial1 = eep_config.serial_number_word1;
12959 asc_dvc->cfg->serial2 = eep_config.serial_number_word2;
12960 asc_dvc->cfg->serial3 = eep_config.serial_number_word3;
12963 * For every Target ID if any of its 'sdtr_speed[1234]' bits
12964 * are set, then set an 'sdtr_able' bit for it.
12966 asc_dvc->sdtr_able = 0;
12967 for (tid = 0; tid <= ADV_MAX_TID; tid++) {
12969 sdtr_speed = asc_dvc->sdtr_speed1;
12970 } else if (tid == 4) {
12971 sdtr_speed = asc_dvc->sdtr_speed2;
12972 } else if (tid == 8) {
12973 sdtr_speed = asc_dvc->sdtr_speed3;
12974 } else if (tid == 12) {
12975 sdtr_speed = asc_dvc->sdtr_speed4;
12977 if (sdtr_speed & ADV_MAX_TID) {
12978 asc_dvc->sdtr_able |= (1 << tid);
12984 * Set the host maximum queuing (max. 253, min. 16) and the per device
12985 * maximum queuing (max. 63, min. 4).
12987 if (eep_config.max_host_qng > ASC_DEF_MAX_HOST_QNG) {
12988 eep_config.max_host_qng = ASC_DEF_MAX_HOST_QNG;
12989 } else if (eep_config.max_host_qng < ASC_DEF_MIN_HOST_QNG) {
12990 /* If the value is zero, assume it is uninitialized. */
12991 if (eep_config.max_host_qng == 0) {
12992 eep_config.max_host_qng = ASC_DEF_MAX_HOST_QNG;
12994 eep_config.max_host_qng = ASC_DEF_MIN_HOST_QNG;
12998 if (eep_config.max_dvc_qng > ASC_DEF_MAX_DVC_QNG) {
12999 eep_config.max_dvc_qng = ASC_DEF_MAX_DVC_QNG;
13000 } else if (eep_config.max_dvc_qng < ASC_DEF_MIN_DVC_QNG) {
13001 /* If the value is zero, assume it is uninitialized. */
13002 if (eep_config.max_dvc_qng == 0) {
13003 eep_config.max_dvc_qng = ASC_DEF_MAX_DVC_QNG;
13005 eep_config.max_dvc_qng = ASC_DEF_MIN_DVC_QNG;
13010 * If 'max_dvc_qng' is greater than 'max_host_qng', then
13011 * set 'max_dvc_qng' to 'max_host_qng'.
13013 if (eep_config.max_dvc_qng > eep_config.max_host_qng) {
13014 eep_config.max_dvc_qng = eep_config.max_host_qng;
13018 * Set ADV_DVC_VAR 'max_host_qng' and ADV_DVC_VAR 'max_dvc_qng'
13019 * values based on possibly adjusted EEPROM values.
13021 asc_dvc->max_host_qng = eep_config.max_host_qng;
13022 asc_dvc->max_dvc_qng = eep_config.max_dvc_qng;
13025 * If the EEPROM 'termination' field is set to automatic (0), then set
13026 * the ADV_DVC_CFG 'termination' field to automatic also.
13028 * If the termination is specified with a non-zero 'termination'
13029 * value check that a legal value is set and set the ADV_DVC_CFG
13030 * 'termination' field appropriately.
13032 if (eep_config.termination_se == 0) {
13033 termination = 0; /* auto termination for SE */
13035 /* Enable manual control with low off / high off. */
13036 if (eep_config.termination_se == 1) {
13039 /* Enable manual control with low off / high on. */
13040 } else if (eep_config.termination_se == 2) {
13041 termination = TERM_SE_HI;
13043 /* Enable manual control with low on / high on. */
13044 } else if (eep_config.termination_se == 3) {
13045 termination = TERM_SE;
13048 * The EEPROM 'termination_se' field contains a bad value.
13049 * Use automatic termination instead.
13052 warn_code |= ASC_WARN_EEPROM_TERMINATION;
13056 if (eep_config.termination_lvd == 0) {
13057 asc_dvc->cfg->termination = termination; /* auto termination for LVD */
13059 /* Enable manual control with low off / high off. */
13060 if (eep_config.termination_lvd == 1) {
13061 asc_dvc->cfg->termination = termination;
13063 /* Enable manual control with low off / high on. */
13064 } else if (eep_config.termination_lvd == 2) {
13065 asc_dvc->cfg->termination = termination | TERM_LVD_HI;
13067 /* Enable manual control with low on / high on. */
13068 } else if (eep_config.termination_lvd == 3) {
13069 asc_dvc->cfg->termination = termination | TERM_LVD;
13072 * The EEPROM 'termination_lvd' field contains a bad value.
13073 * Use automatic termination instead.
13075 asc_dvc->cfg->termination = termination;
13076 warn_code |= ASC_WARN_EEPROM_TERMINATION;
13084 * Read the board's EEPROM configuration. Set fields in ASC_DVC_VAR and
13085 * ASC_DVC_CFG based on the EEPROM settings. The chip is stopped while
13086 * all of this is done.
13088 * On failure set the ASC_DVC_VAR field 'err_code' and return ADV_ERROR.
13090 * For a non-fatal error return a warning code. If there are no warnings
13091 * then 0 is returned.
13093 * Note: Chip is stopped on entry.
13095 static int __devinit AdvInitFrom38C1600EEP(ADV_DVC_VAR *asc_dvc)
13097 AdvPortAddr iop_base;
13099 ADVEEP_38C1600_CONFIG eep_config;
13100 uchar tid, termination;
13101 ushort sdtr_speed = 0;
13103 iop_base = asc_dvc->iop_base;
13108 * Read the board's EEPROM configuration.
13110 * Set default values if a bad checksum is found.
13112 if (AdvGet38C1600EEPConfig(iop_base, &eep_config) !=
13113 eep_config.check_sum) {
13114 struct pci_dev *pdev = adv_dvc_to_pdev(asc_dvc);
13115 warn_code |= ASC_WARN_EEPROM_CHKSUM;
13118 * Set EEPROM default values.
13120 memcpy(&eep_config, &Default_38C1600_EEPROM_Config,
13121 sizeof(ADVEEP_38C1600_CONFIG));
13123 if (PCI_FUNC(pdev->devfn) != 0) {
13126 * Disable Bit 14 (BIOS_ENABLE) to fix SPARC Ultra 60
13127 * and old Mac system booting problem. The Expansion
13128 * ROM must be disabled in Function 1 for these systems
13130 eep_config.cfg_lsw &= ~ADV_EEPROM_BIOS_ENABLE;
13132 * Clear the INTAB (bit 11) if the GPIO 0 input
13133 * indicates the Function 1 interrupt line is wired
13136 * Set/Clear Bit 11 (INTAB) from the GPIO bit 0 input:
13137 * 1 - Function 1 interrupt line wired to INT A.
13138 * 0 - Function 1 interrupt line wired to INT B.
13140 * Note: Function 0 is always wired to INTA.
13141 * Put all 5 GPIO bits in input mode and then read
13142 * their input values.
13144 AdvWriteByteRegister(iop_base, IOPB_GPIO_CNTL, 0);
13145 ints = AdvReadByteRegister(iop_base, IOPB_GPIO_DATA);
13146 if ((ints & 0x01) == 0)
13147 eep_config.cfg_lsw &= ~ADV_EEPROM_INTAB;
13151 * Assume the 6 byte board serial number that was read from
13152 * EEPROM is correct even if the EEPROM checksum failed.
13154 eep_config.serial_number_word3 =
13155 AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 1);
13156 eep_config.serial_number_word2 =
13157 AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 2);
13158 eep_config.serial_number_word1 =
13159 AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 3);
13161 AdvSet38C1600EEPConfig(iop_base, &eep_config);
13165 * Set ASC_DVC_VAR and ASC_DVC_CFG variables from the
13166 * EEPROM configuration that was read.
13168 * This is the mapping of EEPROM fields to Adv Library fields.
13170 asc_dvc->wdtr_able = eep_config.wdtr_able;
13171 asc_dvc->sdtr_speed1 = eep_config.sdtr_speed1;
13172 asc_dvc->sdtr_speed2 = eep_config.sdtr_speed2;
13173 asc_dvc->sdtr_speed3 = eep_config.sdtr_speed3;
13174 asc_dvc->sdtr_speed4 = eep_config.sdtr_speed4;
13175 asc_dvc->ppr_able = 0;
13176 asc_dvc->tagqng_able = eep_config.tagqng_able;
13177 asc_dvc->cfg->disc_enable = eep_config.disc_enable;
13178 asc_dvc->max_host_qng = eep_config.max_host_qng;
13179 asc_dvc->max_dvc_qng = eep_config.max_dvc_qng;
13180 asc_dvc->chip_scsi_id = (eep_config.adapter_scsi_id & ASC_MAX_TID);
13181 asc_dvc->start_motor = eep_config.start_motor;
13182 asc_dvc->scsi_reset_wait = eep_config.scsi_reset_delay;
13183 asc_dvc->bios_ctrl = eep_config.bios_ctrl;
13184 asc_dvc->no_scam = eep_config.scam_tolerant;
13187 * For every Target ID if any of its 'sdtr_speed[1234]' bits
13188 * are set, then set an 'sdtr_able' bit for it.
13190 asc_dvc->sdtr_able = 0;
13191 for (tid = 0; tid <= ASC_MAX_TID; tid++) {
13193 sdtr_speed = asc_dvc->sdtr_speed1;
13194 } else if (tid == 4) {
13195 sdtr_speed = asc_dvc->sdtr_speed2;
13196 } else if (tid == 8) {
13197 sdtr_speed = asc_dvc->sdtr_speed3;
13198 } else if (tid == 12) {
13199 sdtr_speed = asc_dvc->sdtr_speed4;
13201 if (sdtr_speed & ASC_MAX_TID) {
13202 asc_dvc->sdtr_able |= (1 << tid);
13208 * Set the host maximum queuing (max. 253, min. 16) and the per device
13209 * maximum queuing (max. 63, min. 4).
13211 if (eep_config.max_host_qng > ASC_DEF_MAX_HOST_QNG) {
13212 eep_config.max_host_qng = ASC_DEF_MAX_HOST_QNG;
13213 } else if (eep_config.max_host_qng < ASC_DEF_MIN_HOST_QNG) {
13214 /* If the value is zero, assume it is uninitialized. */
13215 if (eep_config.max_host_qng == 0) {
13216 eep_config.max_host_qng = ASC_DEF_MAX_HOST_QNG;
13218 eep_config.max_host_qng = ASC_DEF_MIN_HOST_QNG;
13222 if (eep_config.max_dvc_qng > ASC_DEF_MAX_DVC_QNG) {
13223 eep_config.max_dvc_qng = ASC_DEF_MAX_DVC_QNG;
13224 } else if (eep_config.max_dvc_qng < ASC_DEF_MIN_DVC_QNG) {
13225 /* If the value is zero, assume it is uninitialized. */
13226 if (eep_config.max_dvc_qng == 0) {
13227 eep_config.max_dvc_qng = ASC_DEF_MAX_DVC_QNG;
13229 eep_config.max_dvc_qng = ASC_DEF_MIN_DVC_QNG;
13234 * If 'max_dvc_qng' is greater than 'max_host_qng', then
13235 * set 'max_dvc_qng' to 'max_host_qng'.
13237 if (eep_config.max_dvc_qng > eep_config.max_host_qng) {
13238 eep_config.max_dvc_qng = eep_config.max_host_qng;
13242 * Set ASC_DVC_VAR 'max_host_qng' and ASC_DVC_VAR 'max_dvc_qng'
13243 * values based on possibly adjusted EEPROM values.
13245 asc_dvc->max_host_qng = eep_config.max_host_qng;
13246 asc_dvc->max_dvc_qng = eep_config.max_dvc_qng;
13249 * If the EEPROM 'termination' field is set to automatic (0), then set
13250 * the ASC_DVC_CFG 'termination' field to automatic also.
13252 * If the termination is specified with a non-zero 'termination'
13253 * value check that a legal value is set and set the ASC_DVC_CFG
13254 * 'termination' field appropriately.
13256 if (eep_config.termination_se == 0) {
13257 termination = 0; /* auto termination for SE */
13259 /* Enable manual control with low off / high off. */
13260 if (eep_config.termination_se == 1) {
13263 /* Enable manual control with low off / high on. */
13264 } else if (eep_config.termination_se == 2) {
13265 termination = TERM_SE_HI;
13267 /* Enable manual control with low on / high on. */
13268 } else if (eep_config.termination_se == 3) {
13269 termination = TERM_SE;
13272 * The EEPROM 'termination_se' field contains a bad value.
13273 * Use automatic termination instead.
13276 warn_code |= ASC_WARN_EEPROM_TERMINATION;
13280 if (eep_config.termination_lvd == 0) {
13281 asc_dvc->cfg->termination = termination; /* auto termination for LVD */
13283 /* Enable manual control with low off / high off. */
13284 if (eep_config.termination_lvd == 1) {
13285 asc_dvc->cfg->termination = termination;
13287 /* Enable manual control with low off / high on. */
13288 } else if (eep_config.termination_lvd == 2) {
13289 asc_dvc->cfg->termination = termination | TERM_LVD_HI;
13291 /* Enable manual control with low on / high on. */
13292 } else if (eep_config.termination_lvd == 3) {
13293 asc_dvc->cfg->termination = termination | TERM_LVD;
13296 * The EEPROM 'termination_lvd' field contains a bad value.
13297 * Use automatic termination instead.
13299 asc_dvc->cfg->termination = termination;
13300 warn_code |= ASC_WARN_EEPROM_TERMINATION;
13308 * Initialize the ADV_DVC_VAR structure.
13310 * On failure set the ADV_DVC_VAR field 'err_code' and return ADV_ERROR.
13312 * For a non-fatal error return a warning code. If there are no warnings
13313 * then 0 is returned.
13315 static int __devinit
13316 AdvInitGetConfig(struct pci_dev *pdev, struct Scsi_Host *shost)
13318 struct asc_board *board = shost_priv(shost);
13319 ADV_DVC_VAR *asc_dvc = &board->dvc_var.adv_dvc_var;
13320 unsigned short warn_code = 0;
13321 AdvPortAddr iop_base = asc_dvc->iop_base;
13325 asc_dvc->err_code = 0;
13328 * Save the state of the PCI Configuration Command Register
13329 * "Parity Error Response Control" Bit. If the bit is clear (0),
13330 * in AdvInitAsc3550/38C0800Driver() tell the microcode to ignore
13331 * DMA parity errors.
13333 asc_dvc->cfg->control_flag = 0;
13334 pci_read_config_word(pdev, PCI_COMMAND, &cmd);
13335 if ((cmd & PCI_COMMAND_PARITY) == 0)
13336 asc_dvc->cfg->control_flag |= CONTROL_FLAG_IGNORE_PERR;
13338 asc_dvc->cfg->chip_version =
13339 AdvGetChipVersion(iop_base, asc_dvc->bus_type);
13341 ASC_DBG(1, "iopb_chip_id_1: 0x%x 0x%x\n",
13342 (ushort)AdvReadByteRegister(iop_base, IOPB_CHIP_ID_1),
13343 (ushort)ADV_CHIP_ID_BYTE);
13345 ASC_DBG(1, "iopw_chip_id_0: 0x%x 0x%x\n",
13346 (ushort)AdvReadWordRegister(iop_base, IOPW_CHIP_ID_0),
13347 (ushort)ADV_CHIP_ID_WORD);
13350 * Reset the chip to start and allow register writes.
13352 if (AdvFindSignature(iop_base) == 0) {
13353 asc_dvc->err_code = ASC_IERR_BAD_SIGNATURE;
13357 * The caller must set 'chip_type' to a valid setting.
13359 if (asc_dvc->chip_type != ADV_CHIP_ASC3550 &&
13360 asc_dvc->chip_type != ADV_CHIP_ASC38C0800 &&
13361 asc_dvc->chip_type != ADV_CHIP_ASC38C1600) {
13362 asc_dvc->err_code |= ASC_IERR_BAD_CHIPTYPE;
13369 AdvWriteWordRegister(iop_base, IOPW_CTRL_REG,
13370 ADV_CTRL_REG_CMD_RESET);
13372 AdvWriteWordRegister(iop_base, IOPW_CTRL_REG,
13373 ADV_CTRL_REG_CMD_WR_IO_REG);
13375 if (asc_dvc->chip_type == ADV_CHIP_ASC38C1600) {
13376 status = AdvInitFrom38C1600EEP(asc_dvc);
13377 } else if (asc_dvc->chip_type == ADV_CHIP_ASC38C0800) {
13378 status = AdvInitFrom38C0800EEP(asc_dvc);
13380 status = AdvInitFrom3550EEP(asc_dvc);
13382 warn_code |= status;
13385 if (warn_code != 0)
13386 shost_printk(KERN_WARNING, shost, "warning: 0x%x\n", warn_code);
13388 if (asc_dvc->err_code)
13389 shost_printk(KERN_ERR, shost, "error code 0x%x\n",
13390 asc_dvc->err_code);
13392 return asc_dvc->err_code;
13396 static struct scsi_host_template advansys_template = {
13397 .proc_name = DRV_NAME,
13398 #ifdef CONFIG_PROC_FS
13399 .proc_info = advansys_proc_info,
13402 .info = advansys_info,
13403 .queuecommand = advansys_queuecommand,
13404 .eh_bus_reset_handler = advansys_reset,
13405 .bios_param = advansys_biosparam,
13406 .slave_configure = advansys_slave_configure,
13408 * Because the driver may control an ISA adapter 'unchecked_isa_dma'
13409 * must be set. The flag will be cleared in advansys_board_found
13410 * for non-ISA adapters.
13412 .unchecked_isa_dma = 1,
13414 * All adapters controlled by this driver are capable of large
13415 * scatter-gather lists. According to the mid-level SCSI documentation
13416 * this obviates any performance gain provided by setting
13417 * 'use_clustering'. But empirically while CPU utilization is increased
13418 * by enabling clustering, I/O throughput increases as well.
13420 .use_clustering = ENABLE_CLUSTERING,
13423 static int __devinit advansys_wide_init_chip(struct Scsi_Host *shost)
13425 struct asc_board *board = shost_priv(shost);
13426 struct adv_dvc_var *adv_dvc = &board->dvc_var.adv_dvc_var;
13428 adv_req_t *reqp = NULL;
13431 int warn_code, err_code;
13434 * Allocate buffer carrier structures. The total size
13435 * is about 4 KB, so allocate all at once.
13437 adv_dvc->carrier_buf = kmalloc(ADV_CARRIER_BUFSIZE, GFP_KERNEL);
13438 ASC_DBG(1, "carrier_buf 0x%p\n", adv_dvc->carrier_buf);
13440 if (!adv_dvc->carrier_buf)
13441 goto kmalloc_failed;
13444 * Allocate up to 'max_host_qng' request structures for the Wide
13445 * board. The total size is about 16 KB, so allocate all at once.
13446 * If the allocation fails decrement and try again.
13448 for (req_cnt = adv_dvc->max_host_qng; req_cnt > 0; req_cnt--) {
13449 reqp = kmalloc(sizeof(adv_req_t) * req_cnt, GFP_KERNEL);
13451 ASC_DBG(1, "reqp 0x%p, req_cnt %d, bytes %lu\n", reqp, req_cnt,
13452 (ulong)sizeof(adv_req_t) * req_cnt);
13459 goto kmalloc_failed;
13461 adv_dvc->orig_reqp = reqp;
13464 * Allocate up to ADV_TOT_SG_BLOCK request structures for
13465 * the Wide board. Each structure is about 136 bytes.
13467 board->adv_sgblkp = NULL;
13468 for (sg_cnt = 0; sg_cnt < ADV_TOT_SG_BLOCK; sg_cnt++) {
13469 sgp = kmalloc(sizeof(adv_sgblk_t), GFP_KERNEL);
13474 sgp->next_sgblkp = board->adv_sgblkp;
13475 board->adv_sgblkp = sgp;
13479 ASC_DBG(1, "sg_cnt %d * %u = %u bytes\n", sg_cnt, sizeof(adv_sgblk_t),
13480 (unsigned)(sizeof(adv_sgblk_t) * sg_cnt));
13482 if (!board->adv_sgblkp)
13483 goto kmalloc_failed;
13486 * Point 'adv_reqp' to the request structures and
13487 * link them together.
13490 reqp[req_cnt].next_reqp = NULL;
13491 for (; req_cnt > 0; req_cnt--) {
13492 reqp[req_cnt - 1].next_reqp = &reqp[req_cnt];
13494 board->adv_reqp = &reqp[0];
13496 if (adv_dvc->chip_type == ADV_CHIP_ASC3550) {
13497 ASC_DBG(2, "AdvInitAsc3550Driver()\n");
13498 warn_code = AdvInitAsc3550Driver(adv_dvc);
13499 } else if (adv_dvc->chip_type == ADV_CHIP_ASC38C0800) {
13500 ASC_DBG(2, "AdvInitAsc38C0800Driver()\n");
13501 warn_code = AdvInitAsc38C0800Driver(adv_dvc);
13503 ASC_DBG(2, "AdvInitAsc38C1600Driver()\n");
13504 warn_code = AdvInitAsc38C1600Driver(adv_dvc);
13506 err_code = adv_dvc->err_code;
13508 if (warn_code || err_code) {
13509 shost_printk(KERN_WARNING, shost, "error: warn 0x%x, error "
13510 "0x%x\n", warn_code, err_code);
13516 shost_printk(KERN_ERR, shost, "error: kmalloc() failed\n");
13517 err_code = ADV_ERROR;
13522 static void advansys_wide_free_mem(struct asc_board *board)
13524 struct adv_dvc_var *adv_dvc = &board->dvc_var.adv_dvc_var;
13525 kfree(adv_dvc->carrier_buf);
13526 adv_dvc->carrier_buf = NULL;
13527 kfree(adv_dvc->orig_reqp);
13528 adv_dvc->orig_reqp = board->adv_reqp = NULL;
13529 while (board->adv_sgblkp) {
13530 adv_sgblk_t *sgp = board->adv_sgblkp;
13531 board->adv_sgblkp = sgp->next_sgblkp;
13536 static int __devinit advansys_board_found(struct Scsi_Host *shost,
13537 unsigned int iop, int bus_type)
13539 struct pci_dev *pdev;
13540 struct asc_board *boardp = shost_priv(shost);
13541 ASC_DVC_VAR *asc_dvc_varp = NULL;
13542 ADV_DVC_VAR *adv_dvc_varp = NULL;
13543 int share_irq, warn_code, ret;
13545 pdev = (bus_type == ASC_IS_PCI) ? to_pci_dev(boardp->dev) : NULL;
13547 if (ASC_NARROW_BOARD(boardp)) {
13548 ASC_DBG(1, "narrow board\n");
13549 asc_dvc_varp = &boardp->dvc_var.asc_dvc_var;
13550 asc_dvc_varp->bus_type = bus_type;
13551 asc_dvc_varp->drv_ptr = boardp;
13552 asc_dvc_varp->cfg = &boardp->dvc_cfg.asc_dvc_cfg;
13553 asc_dvc_varp->cfg->overrun_buf = &overrun_buf[0];
13554 asc_dvc_varp->iop_base = iop;
13557 adv_dvc_varp = &boardp->dvc_var.adv_dvc_var;
13558 adv_dvc_varp->drv_ptr = boardp;
13559 adv_dvc_varp->cfg = &boardp->dvc_cfg.adv_dvc_cfg;
13560 if (pdev->device == PCI_DEVICE_ID_ASP_ABP940UW) {
13561 ASC_DBG(1, "wide board ASC-3550\n");
13562 adv_dvc_varp->chip_type = ADV_CHIP_ASC3550;
13563 } else if (pdev->device == PCI_DEVICE_ID_38C0800_REV1) {
13564 ASC_DBG(1, "wide board ASC-38C0800\n");
13565 adv_dvc_varp->chip_type = ADV_CHIP_ASC38C0800;
13567 ASC_DBG(1, "wide board ASC-38C1600\n");
13568 adv_dvc_varp->chip_type = ADV_CHIP_ASC38C1600;
13571 boardp->asc_n_io_port = pci_resource_len(pdev, 1);
13572 boardp->ioremap_addr = ioremap(pci_resource_start(pdev, 1),
13573 boardp->asc_n_io_port);
13574 if (!boardp->ioremap_addr) {
13575 shost_printk(KERN_ERR, shost, "ioremap(%x, %d) "
13577 pci_resource_start(pdev, 1),
13578 boardp->asc_n_io_port);
13582 adv_dvc_varp->iop_base = (AdvPortAddr)boardp->ioremap_addr;
13583 ASC_DBG(1, "iop_base: 0x%p\n", adv_dvc_varp->iop_base);
13586 * Even though it isn't used to access wide boards, other
13587 * than for the debug line below, save I/O Port address so
13588 * that it can be reported.
13590 boardp->ioport = iop;
13592 ASC_DBG(1, "iopb_chip_id_1 0x%x, iopw_chip_id_0 0x%x\n",
13593 (ushort)inp(iop + 1), (ushort)inpw(iop));
13594 #endif /* CONFIG_PCI */
13597 #ifdef CONFIG_PROC_FS
13599 * Allocate buffer for printing information from
13600 * /proc/scsi/advansys/[0...].
13602 boardp->prtbuf = kmalloc(ASC_PRTBUF_SIZE, GFP_KERNEL);
13603 if (!boardp->prtbuf) {
13604 shost_printk(KERN_ERR, shost, "kmalloc(%d) returned NULL\n",
13609 #endif /* CONFIG_PROC_FS */
13611 if (ASC_NARROW_BOARD(boardp)) {
13613 * Set the board bus type and PCI IRQ before
13614 * calling AscInitGetConfig().
13616 switch (asc_dvc_varp->bus_type) {
13619 shost->unchecked_isa_dma = TRUE;
13623 shost->unchecked_isa_dma = FALSE;
13627 shost->unchecked_isa_dma = FALSE;
13628 share_irq = IRQF_SHARED;
13630 #endif /* CONFIG_ISA */
13633 shost->unchecked_isa_dma = FALSE;
13634 share_irq = IRQF_SHARED;
13636 #endif /* CONFIG_PCI */
13638 shost_printk(KERN_ERR, shost, "unknown adapter type: "
13639 "%d\n", asc_dvc_varp->bus_type);
13640 shost->unchecked_isa_dma = TRUE;
13646 * NOTE: AscInitGetConfig() may change the board's
13647 * bus_type value. The bus_type value should no
13648 * longer be used. If the bus_type field must be
13649 * referenced only use the bit-wise AND operator "&".
13651 ASC_DBG(2, "AscInitGetConfig()\n");
13652 ret = AscInitGetConfig(shost) ? -ENODEV : 0;
13656 * For Wide boards set PCI information before calling
13657 * AdvInitGetConfig().
13659 shost->unchecked_isa_dma = FALSE;
13660 share_irq = IRQF_SHARED;
13661 ASC_DBG(2, "AdvInitGetConfig()\n");
13663 ret = AdvInitGetConfig(pdev, shost) ? -ENODEV : 0;
13664 #endif /* CONFIG_PCI */
13668 goto err_free_proc;
13671 * Save the EEPROM configuration so that it can be displayed
13672 * from /proc/scsi/advansys/[0...].
13674 if (ASC_NARROW_BOARD(boardp)) {
13679 * Set the adapter's target id bit in the 'init_tidmask' field.
13681 boardp->init_tidmask |=
13682 ADV_TID_TO_TIDMASK(asc_dvc_varp->cfg->chip_scsi_id);
13685 * Save EEPROM settings for the board.
13687 ep = &boardp->eep_config.asc_eep;
13689 ep->init_sdtr = asc_dvc_varp->cfg->sdtr_enable;
13690 ep->disc_enable = asc_dvc_varp->cfg->disc_enable;
13691 ep->use_cmd_qng = asc_dvc_varp->cfg->cmd_qng_enabled;
13692 ASC_EEP_SET_DMA_SPD(ep, asc_dvc_varp->cfg->isa_dma_speed);
13693 ep->start_motor = asc_dvc_varp->start_motor;
13694 ep->cntl = asc_dvc_varp->dvc_cntl;
13695 ep->no_scam = asc_dvc_varp->no_scam;
13696 ep->max_total_qng = asc_dvc_varp->max_total_qng;
13697 ASC_EEP_SET_CHIP_ID(ep, asc_dvc_varp->cfg->chip_scsi_id);
13698 /* 'max_tag_qng' is set to the same value for every device. */
13699 ep->max_tag_qng = asc_dvc_varp->cfg->max_tag_qng[0];
13700 ep->adapter_info[0] = asc_dvc_varp->cfg->adapter_info[0];
13701 ep->adapter_info[1] = asc_dvc_varp->cfg->adapter_info[1];
13702 ep->adapter_info[2] = asc_dvc_varp->cfg->adapter_info[2];
13703 ep->adapter_info[3] = asc_dvc_varp->cfg->adapter_info[3];
13704 ep->adapter_info[4] = asc_dvc_varp->cfg->adapter_info[4];
13705 ep->adapter_info[5] = asc_dvc_varp->cfg->adapter_info[5];
13708 * Modify board configuration.
13710 ASC_DBG(2, "AscInitSetConfig()\n");
13711 ret = AscInitSetConfig(pdev, shost) ? -ENODEV : 0;
13713 goto err_free_proc;
13715 ADVEEP_3550_CONFIG *ep_3550;
13716 ADVEEP_38C0800_CONFIG *ep_38C0800;
13717 ADVEEP_38C1600_CONFIG *ep_38C1600;
13720 * Save Wide EEP Configuration Information.
13722 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
13723 ep_3550 = &boardp->eep_config.adv_3550_eep;
13725 ep_3550->adapter_scsi_id = adv_dvc_varp->chip_scsi_id;
13726 ep_3550->max_host_qng = adv_dvc_varp->max_host_qng;
13727 ep_3550->max_dvc_qng = adv_dvc_varp->max_dvc_qng;
13728 ep_3550->termination = adv_dvc_varp->cfg->termination;
13729 ep_3550->disc_enable = adv_dvc_varp->cfg->disc_enable;
13730 ep_3550->bios_ctrl = adv_dvc_varp->bios_ctrl;
13731 ep_3550->wdtr_able = adv_dvc_varp->wdtr_able;
13732 ep_3550->sdtr_able = adv_dvc_varp->sdtr_able;
13733 ep_3550->ultra_able = adv_dvc_varp->ultra_able;
13734 ep_3550->tagqng_able = adv_dvc_varp->tagqng_able;
13735 ep_3550->start_motor = adv_dvc_varp->start_motor;
13736 ep_3550->scsi_reset_delay =
13737 adv_dvc_varp->scsi_reset_wait;
13738 ep_3550->serial_number_word1 =
13739 adv_dvc_varp->cfg->serial1;
13740 ep_3550->serial_number_word2 =
13741 adv_dvc_varp->cfg->serial2;
13742 ep_3550->serial_number_word3 =
13743 adv_dvc_varp->cfg->serial3;
13744 } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
13745 ep_38C0800 = &boardp->eep_config.adv_38C0800_eep;
13747 ep_38C0800->adapter_scsi_id =
13748 adv_dvc_varp->chip_scsi_id;
13749 ep_38C0800->max_host_qng = adv_dvc_varp->max_host_qng;
13750 ep_38C0800->max_dvc_qng = adv_dvc_varp->max_dvc_qng;
13751 ep_38C0800->termination_lvd =
13752 adv_dvc_varp->cfg->termination;
13753 ep_38C0800->disc_enable =
13754 adv_dvc_varp->cfg->disc_enable;
13755 ep_38C0800->bios_ctrl = adv_dvc_varp->bios_ctrl;
13756 ep_38C0800->wdtr_able = adv_dvc_varp->wdtr_able;
13757 ep_38C0800->tagqng_able = adv_dvc_varp->tagqng_able;
13758 ep_38C0800->sdtr_speed1 = adv_dvc_varp->sdtr_speed1;
13759 ep_38C0800->sdtr_speed2 = adv_dvc_varp->sdtr_speed2;
13760 ep_38C0800->sdtr_speed3 = adv_dvc_varp->sdtr_speed3;
13761 ep_38C0800->sdtr_speed4 = adv_dvc_varp->sdtr_speed4;
13762 ep_38C0800->tagqng_able = adv_dvc_varp->tagqng_able;
13763 ep_38C0800->start_motor = adv_dvc_varp->start_motor;
13764 ep_38C0800->scsi_reset_delay =
13765 adv_dvc_varp->scsi_reset_wait;
13766 ep_38C0800->serial_number_word1 =
13767 adv_dvc_varp->cfg->serial1;
13768 ep_38C0800->serial_number_word2 =
13769 adv_dvc_varp->cfg->serial2;
13770 ep_38C0800->serial_number_word3 =
13771 adv_dvc_varp->cfg->serial3;
13773 ep_38C1600 = &boardp->eep_config.adv_38C1600_eep;
13775 ep_38C1600->adapter_scsi_id =
13776 adv_dvc_varp->chip_scsi_id;
13777 ep_38C1600->max_host_qng = adv_dvc_varp->max_host_qng;
13778 ep_38C1600->max_dvc_qng = adv_dvc_varp->max_dvc_qng;
13779 ep_38C1600->termination_lvd =
13780 adv_dvc_varp->cfg->termination;
13781 ep_38C1600->disc_enable =
13782 adv_dvc_varp->cfg->disc_enable;
13783 ep_38C1600->bios_ctrl = adv_dvc_varp->bios_ctrl;
13784 ep_38C1600->wdtr_able = adv_dvc_varp->wdtr_able;
13785 ep_38C1600->tagqng_able = adv_dvc_varp->tagqng_able;
13786 ep_38C1600->sdtr_speed1 = adv_dvc_varp->sdtr_speed1;
13787 ep_38C1600->sdtr_speed2 = adv_dvc_varp->sdtr_speed2;
13788 ep_38C1600->sdtr_speed3 = adv_dvc_varp->sdtr_speed3;
13789 ep_38C1600->sdtr_speed4 = adv_dvc_varp->sdtr_speed4;
13790 ep_38C1600->tagqng_able = adv_dvc_varp->tagqng_able;
13791 ep_38C1600->start_motor = adv_dvc_varp->start_motor;
13792 ep_38C1600->scsi_reset_delay =
13793 adv_dvc_varp->scsi_reset_wait;
13794 ep_38C1600->serial_number_word1 =
13795 adv_dvc_varp->cfg->serial1;
13796 ep_38C1600->serial_number_word2 =
13797 adv_dvc_varp->cfg->serial2;
13798 ep_38C1600->serial_number_word3 =
13799 adv_dvc_varp->cfg->serial3;
13803 * Set the adapter's target id bit in the 'init_tidmask' field.
13805 boardp->init_tidmask |=
13806 ADV_TID_TO_TIDMASK(adv_dvc_varp->chip_scsi_id);
13810 * Channels are numbered beginning with 0. For AdvanSys one host
13811 * structure supports one channel. Multi-channel boards have a
13812 * separate host structure for each channel.
13814 shost->max_channel = 0;
13815 if (ASC_NARROW_BOARD(boardp)) {
13816 shost->max_id = ASC_MAX_TID + 1;
13817 shost->max_lun = ASC_MAX_LUN + 1;
13818 shost->max_cmd_len = ASC_MAX_CDB_LEN;
13820 shost->io_port = asc_dvc_varp->iop_base;
13821 boardp->asc_n_io_port = ASC_IOADR_GAP;
13822 shost->this_id = asc_dvc_varp->cfg->chip_scsi_id;
13824 /* Set maximum number of queues the adapter can handle. */
13825 shost->can_queue = asc_dvc_varp->max_total_qng;
13827 shost->max_id = ADV_MAX_TID + 1;
13828 shost->max_lun = ADV_MAX_LUN + 1;
13829 shost->max_cmd_len = ADV_MAX_CDB_LEN;
13832 * Save the I/O Port address and length even though
13833 * I/O ports are not used to access Wide boards.
13834 * Instead the Wide boards are accessed with
13835 * PCI Memory Mapped I/O.
13837 shost->io_port = iop;
13839 shost->this_id = adv_dvc_varp->chip_scsi_id;
13841 /* Set maximum number of queues the adapter can handle. */
13842 shost->can_queue = adv_dvc_varp->max_host_qng;
13846 * Following v1.3.89, 'cmd_per_lun' is no longer needed
13847 * and should be set to zero.
13849 * But because of a bug introduced in v1.3.89 if the driver is
13850 * compiled as a module and 'cmd_per_lun' is zero, the Mid-Level
13851 * SCSI function 'allocate_device' will panic. To allow the driver
13852 * to work as a module in these kernels set 'cmd_per_lun' to 1.
13854 * Note: This is wrong. cmd_per_lun should be set to the depth
13855 * you want on untagged devices always.
13858 shost->cmd_per_lun = 1;
13860 shost->cmd_per_lun = 0;
13864 * Set the maximum number of scatter-gather elements the
13865 * adapter can handle.
13867 if (ASC_NARROW_BOARD(boardp)) {
13869 * Allow two commands with 'sg_tablesize' scatter-gather
13870 * elements to be executed simultaneously. This value is
13871 * the theoretical hardware limit. It may be decreased
13874 shost->sg_tablesize =
13875 (((asc_dvc_varp->max_total_qng - 2) / 2) *
13876 ASC_SG_LIST_PER_Q) + 1;
13878 shost->sg_tablesize = ADV_MAX_SG_LIST;
13882 * The value of 'sg_tablesize' can not exceed the SCSI
13883 * mid-level driver definition of SG_ALL. SG_ALL also
13884 * must not be exceeded, because it is used to define the
13885 * size of the scatter-gather table in 'struct asc_sg_head'.
13887 if (shost->sg_tablesize > SG_ALL) {
13888 shost->sg_tablesize = SG_ALL;
13891 ASC_DBG(1, "sg_tablesize: %d\n", shost->sg_tablesize);
13893 /* BIOS start address. */
13894 if (ASC_NARROW_BOARD(boardp)) {
13895 shost->base = AscGetChipBiosAddress(asc_dvc_varp->iop_base,
13896 asc_dvc_varp->bus_type);
13899 * Fill-in BIOS board variables. The Wide BIOS saves
13900 * information in LRAM that is used by the driver.
13902 AdvReadWordLram(adv_dvc_varp->iop_base,
13903 BIOS_SIGNATURE, boardp->bios_signature);
13904 AdvReadWordLram(adv_dvc_varp->iop_base,
13905 BIOS_VERSION, boardp->bios_version);
13906 AdvReadWordLram(adv_dvc_varp->iop_base,
13907 BIOS_CODESEG, boardp->bios_codeseg);
13908 AdvReadWordLram(adv_dvc_varp->iop_base,
13909 BIOS_CODELEN, boardp->bios_codelen);
13911 ASC_DBG(1, "bios_signature 0x%x, bios_version 0x%x\n",
13912 boardp->bios_signature, boardp->bios_version);
13914 ASC_DBG(1, "bios_codeseg 0x%x, bios_codelen 0x%x\n",
13915 boardp->bios_codeseg, boardp->bios_codelen);
13918 * If the BIOS saved a valid signature, then fill in
13919 * the BIOS code segment base address.
13921 if (boardp->bios_signature == 0x55AA) {
13923 * Convert x86 realmode code segment to a linear
13924 * address by shifting left 4.
13926 shost->base = ((ulong)boardp->bios_codeseg << 4);
13933 * Register Board Resources - I/O Port, DMA, IRQ
13936 /* Register DMA Channel for Narrow boards. */
13937 shost->dma_channel = NO_ISA_DMA; /* Default to no ISA DMA. */
13939 if (ASC_NARROW_BOARD(boardp)) {
13940 /* Register DMA channel for ISA bus. */
13941 if (asc_dvc_varp->bus_type & ASC_IS_ISA) {
13942 shost->dma_channel = asc_dvc_varp->cfg->isa_dma_channel;
13943 ret = request_dma(shost->dma_channel, DRV_NAME);
13945 shost_printk(KERN_ERR, shost, "request_dma() "
13947 shost->dma_channel, ret);
13948 goto err_free_proc;
13950 AscEnableIsaDma(shost->dma_channel);
13953 #endif /* CONFIG_ISA */
13955 /* Register IRQ Number. */
13956 ASC_DBG(2, "request_irq(%d, %p)\n", boardp->irq, shost);
13958 ret = request_irq(boardp->irq, advansys_interrupt, share_irq,
13962 if (ret == -EBUSY) {
13963 shost_printk(KERN_ERR, shost, "request_irq(): IRQ 0x%x "
13964 "already in use\n", boardp->irq);
13965 } else if (ret == -EINVAL) {
13966 shost_printk(KERN_ERR, shost, "request_irq(): IRQ 0x%x "
13967 "not valid\n", boardp->irq);
13969 shost_printk(KERN_ERR, shost, "request_irq(): IRQ 0x%x "
13970 "failed with %d\n", boardp->irq, ret);
13976 * Initialize board RISC chip and enable interrupts.
13978 if (ASC_NARROW_BOARD(boardp)) {
13979 ASC_DBG(2, "AscInitAsc1000Driver()\n");
13980 warn_code = AscInitAsc1000Driver(asc_dvc_varp);
13982 if (warn_code || asc_dvc_varp->err_code) {
13983 shost_printk(KERN_ERR, shost, "error: init_state 0x%x, "
13984 "warn 0x%x, error 0x%x\n",
13985 asc_dvc_varp->init_state, warn_code,
13986 asc_dvc_varp->err_code);
13987 if (asc_dvc_varp->err_code)
13991 if (advansys_wide_init_chip(shost))
13996 goto err_free_wide_mem;
13998 ASC_DBG_PRT_SCSI_HOST(2, shost);
14000 ret = scsi_add_host(shost, boardp->dev);
14002 goto err_free_wide_mem;
14004 scsi_scan_host(shost);
14008 advansys_wide_free_mem(boardp);
14009 free_irq(boardp->irq, shost);
14011 if (shost->dma_channel != NO_ISA_DMA)
14012 free_dma(shost->dma_channel);
14014 kfree(boardp->prtbuf);
14016 if (boardp->ioremap_addr)
14017 iounmap(boardp->ioremap_addr);
14023 * advansys_release()
14025 * Release resources allocated for a single AdvanSys adapter.
14027 static int advansys_release(struct Scsi_Host *shost)
14029 struct asc_board *boardp = shost_priv(shost);
14030 ASC_DBG(1, "begin\n");
14031 scsi_remove_host(shost);
14032 free_irq(boardp->irq, shost);
14033 if (shost->dma_channel != NO_ISA_DMA) {
14034 ASC_DBG(1, "free_dma()\n");
14035 free_dma(shost->dma_channel);
14037 if (!ASC_NARROW_BOARD(boardp)) {
14038 iounmap(boardp->ioremap_addr);
14039 advansys_wide_free_mem(boardp);
14041 kfree(boardp->prtbuf);
14042 scsi_host_put(shost);
14043 ASC_DBG(1, "end\n");
14047 #define ASC_IOADR_TABLE_MAX_IX 11
14049 static PortAddr _asc_def_iop_base[ASC_IOADR_TABLE_MAX_IX] __devinitdata = {
14050 0x100, 0x0110, 0x120, 0x0130, 0x140, 0x0150, 0x0190,
14051 0x0210, 0x0230, 0x0250, 0x0330
14055 * The ISA IRQ number is found in bits 2 and 3 of the CfgLsw. It decodes as:
14061 static unsigned int __devinit advansys_isa_irq_no(PortAddr iop_base)
14063 unsigned short cfg_lsw = AscGetChipCfgLsw(iop_base);
14064 unsigned int chip_irq = ((cfg_lsw >> 2) & 0x03) + 10;
14065 if (chip_irq == 13)
14070 static int __devinit advansys_isa_probe(struct device *dev, unsigned int id)
14073 PortAddr iop_base = _asc_def_iop_base[id];
14074 struct Scsi_Host *shost;
14075 struct asc_board *board;
14077 if (!request_region(iop_base, ASC_IOADR_GAP, DRV_NAME)) {
14078 ASC_DBG(1, "I/O port 0x%x busy\n", iop_base);
14081 ASC_DBG(1, "probing I/O port 0x%x\n", iop_base);
14082 if (!AscFindSignature(iop_base))
14083 goto release_region;
14084 if (!(AscGetChipVersion(iop_base, ASC_IS_ISA) & ASC_CHIP_VER_ISA_BIT))
14085 goto release_region;
14088 shost = scsi_host_alloc(&advansys_template, sizeof(*board));
14090 goto release_region;
14092 board = shost_priv(shost);
14093 board->irq = advansys_isa_irq_no(iop_base);
14096 err = advansys_board_found(shost, iop_base, ASC_IS_ISA);
14100 dev_set_drvdata(dev, shost);
14104 scsi_host_put(shost);
14106 release_region(iop_base, ASC_IOADR_GAP);
14110 static int __devexit advansys_isa_remove(struct device *dev, unsigned int id)
14112 int ioport = _asc_def_iop_base[id];
14113 advansys_release(dev_get_drvdata(dev));
14114 release_region(ioport, ASC_IOADR_GAP);
14118 static struct isa_driver advansys_isa_driver = {
14119 .probe = advansys_isa_probe,
14120 .remove = __devexit_p(advansys_isa_remove),
14122 .owner = THIS_MODULE,
14128 * The VLB IRQ number is found in bits 2 to 4 of the CfgLsw. It decodes as:
14138 static unsigned int __devinit advansys_vlb_irq_no(PortAddr iop_base)
14140 unsigned short cfg_lsw = AscGetChipCfgLsw(iop_base);
14141 unsigned int chip_irq = ((cfg_lsw >> 2) & 0x07) + 9;
14142 if ((chip_irq < 10) || (chip_irq == 13) || (chip_irq > 15))
14147 static int __devinit advansys_vlb_probe(struct device *dev, unsigned int id)
14150 PortAddr iop_base = _asc_def_iop_base[id];
14151 struct Scsi_Host *shost;
14152 struct asc_board *board;
14154 if (!request_region(iop_base, ASC_IOADR_GAP, DRV_NAME)) {
14155 ASC_DBG(1, "I/O port 0x%x busy\n", iop_base);
14158 ASC_DBG(1, "probing I/O port 0x%x\n", iop_base);
14159 if (!AscFindSignature(iop_base))
14160 goto release_region;
14162 * I don't think this condition can actually happen, but the old
14163 * driver did it, and the chances of finding a VLB setup in 2007
14164 * to do testing with is slight to none.
14166 if (AscGetChipVersion(iop_base, ASC_IS_VL) > ASC_CHIP_MAX_VER_VL)
14167 goto release_region;
14170 shost = scsi_host_alloc(&advansys_template, sizeof(*board));
14172 goto release_region;
14174 board = shost_priv(shost);
14175 board->irq = advansys_vlb_irq_no(iop_base);
14178 err = advansys_board_found(shost, iop_base, ASC_IS_VL);
14182 dev_set_drvdata(dev, shost);
14186 scsi_host_put(shost);
14188 release_region(iop_base, ASC_IOADR_GAP);
14192 static struct isa_driver advansys_vlb_driver = {
14193 .probe = advansys_vlb_probe,
14194 .remove = __devexit_p(advansys_isa_remove),
14196 .owner = THIS_MODULE,
14197 .name = "advansys_vlb",
14201 static struct eisa_device_id advansys_eisa_table[] __devinitdata = {
14207 MODULE_DEVICE_TABLE(eisa, advansys_eisa_table);
14210 * EISA is a little more tricky than PCI; each EISA device may have two
14211 * channels, and this driver is written to make each channel its own Scsi_Host
14213 struct eisa_scsi_data {
14214 struct Scsi_Host *host[2];
14218 * The EISA IRQ number is found in bits 8 to 10 of the CfgLsw. It decodes as:
14228 static unsigned int __devinit advansys_eisa_irq_no(struct eisa_device *edev)
14230 unsigned short cfg_lsw = inw(edev->base_addr + 0xc86);
14231 unsigned int chip_irq = ((cfg_lsw >> 8) & 0x07) + 10;
14232 if ((chip_irq == 13) || (chip_irq > 15))
14237 static int __devinit advansys_eisa_probe(struct device *dev)
14239 int i, ioport, irq = 0;
14241 struct eisa_device *edev = to_eisa_device(dev);
14242 struct eisa_scsi_data *data;
14245 data = kzalloc(sizeof(*data), GFP_KERNEL);
14248 ioport = edev->base_addr + 0xc30;
14251 for (i = 0; i < 2; i++, ioport += 0x20) {
14252 struct asc_board *board;
14253 struct Scsi_Host *shost;
14254 if (!request_region(ioport, ASC_IOADR_GAP, DRV_NAME)) {
14255 printk(KERN_WARNING "Region %x-%x busy\n", ioport,
14256 ioport + ASC_IOADR_GAP - 1);
14259 if (!AscFindSignature(ioport)) {
14260 release_region(ioport, ASC_IOADR_GAP);
14265 * I don't know why we need to do this for EISA chips, but
14266 * not for any others. It looks to be equivalent to
14267 * AscGetChipCfgMsw, but I may have overlooked something,
14268 * so I'm not converting it until I get an EISA board to
14274 irq = advansys_eisa_irq_no(edev);
14277 shost = scsi_host_alloc(&advansys_template, sizeof(*board));
14279 goto release_region;
14281 board = shost_priv(shost);
14285 err = advansys_board_found(shost, ioport, ASC_IS_EISA);
14287 data->host[i] = shost;
14291 scsi_host_put(shost);
14293 release_region(ioport, ASC_IOADR_GAP);
14299 dev_set_drvdata(dev, data);
14303 kfree(data->host[0]);
14304 kfree(data->host[1]);
14310 static __devexit int advansys_eisa_remove(struct device *dev)
14313 struct eisa_scsi_data *data = dev_get_drvdata(dev);
14315 for (i = 0; i < 2; i++) {
14317 struct Scsi_Host *shost = data->host[i];
14320 ioport = shost->io_port;
14321 advansys_release(shost);
14322 release_region(ioport, ASC_IOADR_GAP);
14329 static struct eisa_driver advansys_eisa_driver = {
14330 .id_table = advansys_eisa_table,
14333 .probe = advansys_eisa_probe,
14334 .remove = __devexit_p(advansys_eisa_remove),
14338 /* PCI Devices supported by this driver */
14339 static struct pci_device_id advansys_pci_tbl[] __devinitdata = {
14340 {PCI_VENDOR_ID_ASP, PCI_DEVICE_ID_ASP_1200A,
14341 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
14342 {PCI_VENDOR_ID_ASP, PCI_DEVICE_ID_ASP_ABP940,
14343 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
14344 {PCI_VENDOR_ID_ASP, PCI_DEVICE_ID_ASP_ABP940U,
14345 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
14346 {PCI_VENDOR_ID_ASP, PCI_DEVICE_ID_ASP_ABP940UW,
14347 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
14348 {PCI_VENDOR_ID_ASP, PCI_DEVICE_ID_38C0800_REV1,
14349 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
14350 {PCI_VENDOR_ID_ASP, PCI_DEVICE_ID_38C1600_REV1,
14351 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
14355 MODULE_DEVICE_TABLE(pci, advansys_pci_tbl);
14357 static void __devinit advansys_set_latency(struct pci_dev *pdev)
14359 if ((pdev->device == PCI_DEVICE_ID_ASP_1200A) ||
14360 (pdev->device == PCI_DEVICE_ID_ASP_ABP940)) {
14361 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0);
14364 pci_read_config_byte(pdev, PCI_LATENCY_TIMER, &latency);
14365 if (latency < 0x20)
14366 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0x20);
14370 static int __devinit
14371 advansys_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
14374 struct Scsi_Host *shost;
14375 struct asc_board *board;
14377 err = pci_enable_device(pdev);
14380 err = pci_request_regions(pdev, DRV_NAME);
14382 goto disable_device;
14383 pci_set_master(pdev);
14384 advansys_set_latency(pdev);
14387 if (pci_resource_len(pdev, 0) == 0)
14388 goto release_region;
14390 ioport = pci_resource_start(pdev, 0);
14393 shost = scsi_host_alloc(&advansys_template, sizeof(*board));
14395 goto release_region;
14397 board = shost_priv(shost);
14398 board->irq = pdev->irq;
14399 board->dev = &pdev->dev;
14401 if (pdev->device == PCI_DEVICE_ID_ASP_ABP940UW ||
14402 pdev->device == PCI_DEVICE_ID_38C0800_REV1 ||
14403 pdev->device == PCI_DEVICE_ID_38C1600_REV1) {
14404 board->flags |= ASC_IS_WIDE_BOARD;
14407 err = advansys_board_found(shost, ioport, ASC_IS_PCI);
14411 pci_set_drvdata(pdev, shost);
14415 scsi_host_put(shost);
14417 pci_release_regions(pdev);
14419 pci_disable_device(pdev);
14424 static void __devexit advansys_pci_remove(struct pci_dev *pdev)
14426 advansys_release(pci_get_drvdata(pdev));
14427 pci_release_regions(pdev);
14428 pci_disable_device(pdev);
14431 static struct pci_driver advansys_pci_driver = {
14433 .id_table = advansys_pci_tbl,
14434 .probe = advansys_pci_probe,
14435 .remove = __devexit_p(advansys_pci_remove),
14438 static int __init advansys_init(void)
14442 error = isa_register_driver(&advansys_isa_driver,
14443 ASC_IOADR_TABLE_MAX_IX);
14447 error = isa_register_driver(&advansys_vlb_driver,
14448 ASC_IOADR_TABLE_MAX_IX);
14450 goto unregister_isa;
14452 error = eisa_driver_register(&advansys_eisa_driver);
14454 goto unregister_vlb;
14456 error = pci_register_driver(&advansys_pci_driver);
14458 goto unregister_eisa;
14463 eisa_driver_unregister(&advansys_eisa_driver);
14465 isa_unregister_driver(&advansys_vlb_driver);
14467 isa_unregister_driver(&advansys_isa_driver);
14472 static void __exit advansys_exit(void)
14474 pci_unregister_driver(&advansys_pci_driver);
14475 eisa_driver_unregister(&advansys_eisa_driver);
14476 isa_unregister_driver(&advansys_vlb_driver);
14477 isa_unregister_driver(&advansys_isa_driver);
14480 module_init(advansys_init);
14481 module_exit(advansys_exit);
14483 MODULE_LICENSE("GPL");