2 * ahci.c - AHCI SATA support
4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
8 * Copyright 2004-2005 Red Hat, Inc.
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/DocBook/libata.*
29 * AHCI hardware documentation:
30 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
31 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
35 #include <linux/kernel.h>
36 #include <linux/module.h>
37 #include <linux/pci.h>
38 #include <linux/init.h>
39 #include <linux/blkdev.h>
40 #include <linux/delay.h>
41 #include <linux/interrupt.h>
42 #include <linux/sched.h>
43 #include <linux/dma-mapping.h>
44 #include <linux/device.h>
45 #include <scsi/scsi_host.h>
46 #include <scsi/scsi_cmnd.h>
47 #include <linux/libata.h>
50 #define DRV_NAME "ahci"
51 #define DRV_VERSION "1.01"
56 AHCI_MAX_SG = 168, /* hardware max is 64K */
57 AHCI_DMA_BOUNDARY = 0xffffffff,
58 AHCI_USE_CLUSTERING = 0,
59 AHCI_CMD_SLOT_SZ = 32 * 32,
61 AHCI_CMD_TBL_HDR = 0x80,
62 AHCI_CMD_TBL_CDB = 0x40,
63 AHCI_CMD_TBL_SZ = AHCI_CMD_TBL_HDR + (AHCI_MAX_SG * 16),
64 AHCI_PORT_PRIV_DMA_SZ = AHCI_CMD_SLOT_SZ + AHCI_CMD_TBL_SZ +
66 AHCI_IRQ_ON_SG = (1 << 31),
67 AHCI_CMD_ATAPI = (1 << 5),
68 AHCI_CMD_WRITE = (1 << 6),
70 RX_FIS_D2H_REG = 0x40, /* offset of D2H Register FIS data */
74 /* global controller registers */
75 HOST_CAP = 0x00, /* host capabilities */
76 HOST_CTL = 0x04, /* global host control */
77 HOST_IRQ_STAT = 0x08, /* interrupt status */
78 HOST_PORTS_IMPL = 0x0c, /* bitmap of implemented ports */
79 HOST_VERSION = 0x10, /* AHCI spec. version compliancy */
82 HOST_RESET = (1 << 0), /* reset controller; self-clear */
83 HOST_IRQ_EN = (1 << 1), /* global IRQ enable */
84 HOST_AHCI_EN = (1 << 31), /* AHCI enabled */
87 HOST_CAP_64 = (1 << 31), /* PCI DAC (64-bit DMA) support */
89 /* registers for each SATA port */
90 PORT_LST_ADDR = 0x00, /* command list DMA addr */
91 PORT_LST_ADDR_HI = 0x04, /* command list DMA addr hi */
92 PORT_FIS_ADDR = 0x08, /* FIS rx buf addr */
93 PORT_FIS_ADDR_HI = 0x0c, /* FIS rx buf addr hi */
94 PORT_IRQ_STAT = 0x10, /* interrupt status */
95 PORT_IRQ_MASK = 0x14, /* interrupt enable/disable mask */
96 PORT_CMD = 0x18, /* port command */
97 PORT_TFDATA = 0x20, /* taskfile data */
98 PORT_SIG = 0x24, /* device TF signature */
99 PORT_CMD_ISSUE = 0x38, /* command issue */
100 PORT_SCR = 0x28, /* SATA phy register block */
101 PORT_SCR_STAT = 0x28, /* SATA phy register: SStatus */
102 PORT_SCR_CTL = 0x2c, /* SATA phy register: SControl */
103 PORT_SCR_ERR = 0x30, /* SATA phy register: SError */
104 PORT_SCR_ACT = 0x34, /* SATA phy register: SActive */
106 /* PORT_IRQ_{STAT,MASK} bits */
107 PORT_IRQ_COLD_PRES = (1 << 31), /* cold presence detect */
108 PORT_IRQ_TF_ERR = (1 << 30), /* task file error */
109 PORT_IRQ_HBUS_ERR = (1 << 29), /* host bus fatal error */
110 PORT_IRQ_HBUS_DATA_ERR = (1 << 28), /* host bus data error */
111 PORT_IRQ_IF_ERR = (1 << 27), /* interface fatal error */
112 PORT_IRQ_IF_NONFATAL = (1 << 26), /* interface non-fatal error */
113 PORT_IRQ_OVERFLOW = (1 << 24), /* xfer exhausted available S/G */
114 PORT_IRQ_BAD_PMP = (1 << 23), /* incorrect port multiplier */
116 PORT_IRQ_PHYRDY = (1 << 22), /* PhyRdy changed */
117 PORT_IRQ_DEV_ILCK = (1 << 7), /* device interlock */
118 PORT_IRQ_CONNECT = (1 << 6), /* port connect change status */
119 PORT_IRQ_SG_DONE = (1 << 5), /* descriptor processed */
120 PORT_IRQ_UNK_FIS = (1 << 4), /* unknown FIS rx'd */
121 PORT_IRQ_SDB_FIS = (1 << 3), /* Set Device Bits FIS rx'd */
122 PORT_IRQ_DMAS_FIS = (1 << 2), /* DMA Setup FIS rx'd */
123 PORT_IRQ_PIOS_FIS = (1 << 1), /* PIO Setup FIS rx'd */
124 PORT_IRQ_D2H_REG_FIS = (1 << 0), /* D2H Register FIS rx'd */
126 PORT_IRQ_FATAL = PORT_IRQ_TF_ERR |
128 PORT_IRQ_HBUS_DATA_ERR |
130 DEF_PORT_IRQ = PORT_IRQ_FATAL | PORT_IRQ_PHYRDY |
131 PORT_IRQ_CONNECT | PORT_IRQ_SG_DONE |
132 PORT_IRQ_UNK_FIS | PORT_IRQ_SDB_FIS |
133 PORT_IRQ_DMAS_FIS | PORT_IRQ_PIOS_FIS |
134 PORT_IRQ_D2H_REG_FIS,
137 PORT_CMD_ATAPI = (1 << 24), /* Device is ATAPI */
138 PORT_CMD_LIST_ON = (1 << 15), /* cmd list DMA engine running */
139 PORT_CMD_FIS_ON = (1 << 14), /* FIS DMA engine running */
140 PORT_CMD_FIS_RX = (1 << 4), /* Enable FIS receive DMA engine */
141 PORT_CMD_POWER_ON = (1 << 2), /* Power up device */
142 PORT_CMD_SPIN_UP = (1 << 1), /* Spin up device */
143 PORT_CMD_START = (1 << 0), /* Enable port DMA engine */
145 PORT_CMD_ICC_ACTIVE = (0x1 << 28), /* Put i/f in active state */
146 PORT_CMD_ICC_PARTIAL = (0x2 << 28), /* Put i/f in partial state */
147 PORT_CMD_ICC_SLUMBER = (0x6 << 28), /* Put i/f in slumber state */
149 /* hpriv->flags bits */
150 AHCI_FLAG_MSI = (1 << 0),
153 struct ahci_cmd_hdr {
168 struct ahci_host_priv {
170 u32 cap; /* cache of HOST_CAP register */
171 u32 port_map; /* cache of HOST_PORTS_IMPL reg */
174 struct ahci_port_priv {
175 struct ahci_cmd_hdr *cmd_slot;
176 dma_addr_t cmd_slot_dma;
178 dma_addr_t cmd_tbl_dma;
179 struct ahci_sg *cmd_tbl_sg;
181 dma_addr_t rx_fis_dma;
184 static u32 ahci_scr_read (struct ata_port *ap, unsigned int sc_reg);
185 static void ahci_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val);
186 static int ahci_init_one (struct pci_dev *pdev, const struct pci_device_id *ent);
187 static int ahci_qc_issue(struct ata_queued_cmd *qc);
188 static irqreturn_t ahci_interrupt (int irq, void *dev_instance, struct pt_regs *regs);
189 static void ahci_phy_reset(struct ata_port *ap);
190 static void ahci_irq_clear(struct ata_port *ap);
191 static void ahci_eng_timeout(struct ata_port *ap);
192 static int ahci_port_start(struct ata_port *ap);
193 static void ahci_port_stop(struct ata_port *ap);
194 static void ahci_tf_read(struct ata_port *ap, struct ata_taskfile *tf);
195 static void ahci_qc_prep(struct ata_queued_cmd *qc);
196 static u8 ahci_check_status(struct ata_port *ap);
197 static inline int ahci_host_intr(struct ata_port *ap, struct ata_queued_cmd *qc);
198 static void ahci_remove_one (struct pci_dev *pdev);
200 static struct scsi_host_template ahci_sht = {
201 .module = THIS_MODULE,
203 .ioctl = ata_scsi_ioctl,
204 .queuecommand = ata_scsi_queuecmd,
205 .eh_strategy_handler = ata_scsi_error,
206 .can_queue = ATA_DEF_QUEUE,
207 .this_id = ATA_SHT_THIS_ID,
208 .sg_tablesize = AHCI_MAX_SG,
209 .max_sectors = ATA_MAX_SECTORS,
210 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
211 .emulated = ATA_SHT_EMULATED,
212 .use_clustering = AHCI_USE_CLUSTERING,
213 .proc_name = DRV_NAME,
214 .dma_boundary = AHCI_DMA_BOUNDARY,
215 .slave_configure = ata_scsi_slave_config,
216 .bios_param = ata_std_bios_param,
220 static const struct ata_port_operations ahci_ops = {
221 .port_disable = ata_port_disable,
223 .check_status = ahci_check_status,
224 .check_altstatus = ahci_check_status,
225 .dev_select = ata_noop_dev_select,
227 .tf_read = ahci_tf_read,
229 .phy_reset = ahci_phy_reset,
231 .qc_prep = ahci_qc_prep,
232 .qc_issue = ahci_qc_issue,
234 .eng_timeout = ahci_eng_timeout,
236 .irq_handler = ahci_interrupt,
237 .irq_clear = ahci_irq_clear,
239 .scr_read = ahci_scr_read,
240 .scr_write = ahci_scr_write,
242 .port_start = ahci_port_start,
243 .port_stop = ahci_port_stop,
246 static struct ata_port_info ahci_port_info[] = {
250 .host_flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
251 ATA_FLAG_SATA_RESET | ATA_FLAG_MMIO |
253 .pio_mask = 0x1f, /* pio0-4 */
254 .udma_mask = 0x7f, /* udma0-6 ; FIXME */
255 .port_ops = &ahci_ops,
259 static const struct pci_device_id ahci_pci_tbl[] = {
260 { PCI_VENDOR_ID_INTEL, 0x2652, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
261 board_ahci }, /* ICH6 */
262 { PCI_VENDOR_ID_INTEL, 0x2653, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
263 board_ahci }, /* ICH6M */
264 { PCI_VENDOR_ID_INTEL, 0x27c1, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
265 board_ahci }, /* ICH7 */
266 { PCI_VENDOR_ID_INTEL, 0x27c5, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
267 board_ahci }, /* ICH7M */
268 { PCI_VENDOR_ID_INTEL, 0x27c3, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
269 board_ahci }, /* ICH7R */
270 { PCI_VENDOR_ID_AL, 0x5288, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
271 board_ahci }, /* ULi M5288 */
272 { PCI_VENDOR_ID_INTEL, 0x2681, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
273 board_ahci }, /* ESB2 */
274 { PCI_VENDOR_ID_INTEL, 0x2682, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
275 board_ahci }, /* ESB2 */
276 { PCI_VENDOR_ID_INTEL, 0x2683, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
277 board_ahci }, /* ESB2 */
278 { PCI_VENDOR_ID_INTEL, 0x27c6, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
279 board_ahci }, /* ICH7-M DH */
280 { } /* terminate list */
284 static struct pci_driver ahci_pci_driver = {
286 .id_table = ahci_pci_tbl,
287 .probe = ahci_init_one,
288 .remove = ahci_remove_one,
292 static inline unsigned long ahci_port_base_ul (unsigned long base, unsigned int port)
294 return base + 0x100 + (port * 0x80);
297 static inline void __iomem *ahci_port_base (void __iomem *base, unsigned int port)
299 return (void __iomem *) ahci_port_base_ul((unsigned long)base, port);
302 static int ahci_port_start(struct ata_port *ap)
304 struct device *dev = ap->host_set->dev;
305 struct ahci_host_priv *hpriv = ap->host_set->private_data;
306 struct ahci_port_priv *pp;
307 void __iomem *mmio = ap->host_set->mmio_base;
308 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
313 pp = kmalloc(sizeof(*pp), GFP_KERNEL);
316 memset(pp, 0, sizeof(*pp));
318 rc = ata_pad_alloc(ap, dev);
324 mem = dma_alloc_coherent(dev, AHCI_PORT_PRIV_DMA_SZ, &mem_dma, GFP_KERNEL);
326 ata_pad_free(ap, dev);
330 memset(mem, 0, AHCI_PORT_PRIV_DMA_SZ);
333 * First item in chunk of DMA memory: 32-slot command table,
334 * 32 bytes each in size
337 pp->cmd_slot_dma = mem_dma;
339 mem += AHCI_CMD_SLOT_SZ;
340 mem_dma += AHCI_CMD_SLOT_SZ;
343 * Second item: Received-FIS area
346 pp->rx_fis_dma = mem_dma;
348 mem += AHCI_RX_FIS_SZ;
349 mem_dma += AHCI_RX_FIS_SZ;
352 * Third item: data area for storing a single command
353 * and its scatter-gather table
356 pp->cmd_tbl_dma = mem_dma;
358 pp->cmd_tbl_sg = mem + AHCI_CMD_TBL_HDR;
360 ap->private_data = pp;
362 if (hpriv->cap & HOST_CAP_64)
363 writel((pp->cmd_slot_dma >> 16) >> 16, port_mmio + PORT_LST_ADDR_HI);
364 writel(pp->cmd_slot_dma & 0xffffffff, port_mmio + PORT_LST_ADDR);
365 readl(port_mmio + PORT_LST_ADDR); /* flush */
367 if (hpriv->cap & HOST_CAP_64)
368 writel((pp->rx_fis_dma >> 16) >> 16, port_mmio + PORT_FIS_ADDR_HI);
369 writel(pp->rx_fis_dma & 0xffffffff, port_mmio + PORT_FIS_ADDR);
370 readl(port_mmio + PORT_FIS_ADDR); /* flush */
372 writel(PORT_CMD_ICC_ACTIVE | PORT_CMD_FIS_RX |
373 PORT_CMD_POWER_ON | PORT_CMD_SPIN_UP |
374 PORT_CMD_START, port_mmio + PORT_CMD);
375 readl(port_mmio + PORT_CMD); /* flush */
381 static void ahci_port_stop(struct ata_port *ap)
383 struct device *dev = ap->host_set->dev;
384 struct ahci_port_priv *pp = ap->private_data;
385 void __iomem *mmio = ap->host_set->mmio_base;
386 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
389 tmp = readl(port_mmio + PORT_CMD);
390 tmp &= ~(PORT_CMD_START | PORT_CMD_FIS_RX);
391 writel(tmp, port_mmio + PORT_CMD);
392 readl(port_mmio + PORT_CMD); /* flush */
394 /* spec says 500 msecs for each PORT_CMD_{START,FIS_RX} bit, so
395 * this is slightly incorrect.
399 ap->private_data = NULL;
400 dma_free_coherent(dev, AHCI_PORT_PRIV_DMA_SZ,
401 pp->cmd_slot, pp->cmd_slot_dma);
402 ata_pad_free(ap, dev);
406 static u32 ahci_scr_read (struct ata_port *ap, unsigned int sc_reg_in)
411 case SCR_STATUS: sc_reg = 0; break;
412 case SCR_CONTROL: sc_reg = 1; break;
413 case SCR_ERROR: sc_reg = 2; break;
414 case SCR_ACTIVE: sc_reg = 3; break;
419 return readl((void __iomem *) ap->ioaddr.scr_addr + (sc_reg * 4));
423 static void ahci_scr_write (struct ata_port *ap, unsigned int sc_reg_in,
429 case SCR_STATUS: sc_reg = 0; break;
430 case SCR_CONTROL: sc_reg = 1; break;
431 case SCR_ERROR: sc_reg = 2; break;
432 case SCR_ACTIVE: sc_reg = 3; break;
437 writel(val, (void __iomem *) ap->ioaddr.scr_addr + (sc_reg * 4));
440 static void ahci_phy_reset(struct ata_port *ap)
442 void __iomem *port_mmio = (void __iomem *) ap->ioaddr.cmd_addr;
443 struct ata_taskfile tf;
444 struct ata_device *dev = &ap->device[0];
447 __sata_phy_reset(ap);
449 if (ap->flags & ATA_FLAG_PORT_DISABLED)
452 tmp = readl(port_mmio + PORT_SIG);
453 tf.lbah = (tmp >> 24) & 0xff;
454 tf.lbam = (tmp >> 16) & 0xff;
455 tf.lbal = (tmp >> 8) & 0xff;
456 tf.nsect = (tmp) & 0xff;
458 dev->class = ata_dev_classify(&tf);
459 if (!ata_dev_present(dev)) {
460 ata_port_disable(ap);
464 /* Make sure port's ATAPI bit is set appropriately */
465 new_tmp = tmp = readl(port_mmio + PORT_CMD);
466 if (dev->class == ATA_DEV_ATAPI)
467 new_tmp |= PORT_CMD_ATAPI;
469 new_tmp &= ~PORT_CMD_ATAPI;
470 if (new_tmp != tmp) {
471 writel(new_tmp, port_mmio + PORT_CMD);
472 readl(port_mmio + PORT_CMD); /* flush */
476 static u8 ahci_check_status(struct ata_port *ap)
478 void __iomem *mmio = (void __iomem *) ap->ioaddr.cmd_addr;
480 return readl(mmio + PORT_TFDATA) & 0xFF;
483 static void ahci_tf_read(struct ata_port *ap, struct ata_taskfile *tf)
485 struct ahci_port_priv *pp = ap->private_data;
486 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
488 ata_tf_from_fis(d2h_fis, tf);
491 static unsigned int ahci_fill_sg(struct ata_queued_cmd *qc)
493 struct ahci_port_priv *pp = qc->ap->private_data;
494 struct scatterlist *sg;
495 struct ahci_sg *ahci_sg;
496 unsigned int n_sg = 0;
501 * Next, the S/G list.
503 ahci_sg = pp->cmd_tbl_sg;
504 ata_for_each_sg(sg, qc) {
505 dma_addr_t addr = sg_dma_address(sg);
506 u32 sg_len = sg_dma_len(sg);
508 ahci_sg->addr = cpu_to_le32(addr & 0xffffffff);
509 ahci_sg->addr_hi = cpu_to_le32((addr >> 16) >> 16);
510 ahci_sg->flags_size = cpu_to_le32(sg_len - 1);
519 static void ahci_qc_prep(struct ata_queued_cmd *qc)
521 struct ata_port *ap = qc->ap;
522 struct ahci_port_priv *pp = ap->private_data;
524 const u32 cmd_fis_len = 5; /* five dwords */
528 * Fill in command slot information (currently only one slot,
529 * slot 0, is currently since we don't do queueing)
533 if (qc->tf.flags & ATA_TFLAG_WRITE)
534 opts |= AHCI_CMD_WRITE;
535 if (is_atapi_taskfile(&qc->tf))
536 opts |= AHCI_CMD_ATAPI;
538 pp->cmd_slot[0].opts = cpu_to_le32(opts);
539 pp->cmd_slot[0].status = 0;
540 pp->cmd_slot[0].tbl_addr = cpu_to_le32(pp->cmd_tbl_dma & 0xffffffff);
541 pp->cmd_slot[0].tbl_addr_hi = cpu_to_le32((pp->cmd_tbl_dma >> 16) >> 16);
544 * Fill in command table information. First, the header,
545 * a SATA Register - Host to Device command FIS.
547 ata_tf_to_fis(&qc->tf, pp->cmd_tbl, 0);
548 if (opts & AHCI_CMD_ATAPI) {
549 memset(pp->cmd_tbl + AHCI_CMD_TBL_CDB, 0, 32);
550 memcpy(pp->cmd_tbl + AHCI_CMD_TBL_CDB, qc->cdb, ap->cdb_len);
553 if (!(qc->flags & ATA_QCFLAG_DMAMAP))
556 n_elem = ahci_fill_sg(qc);
558 pp->cmd_slot[0].opts |= cpu_to_le32(n_elem << 16);
561 static void ahci_intr_error(struct ata_port *ap, u32 irq_stat)
563 void __iomem *mmio = ap->host_set->mmio_base;
564 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
569 tmp = readl(port_mmio + PORT_CMD);
570 tmp &= ~PORT_CMD_START;
571 writel(tmp, port_mmio + PORT_CMD);
573 /* wait for engine to stop. TODO: this could be
574 * as long as 500 msec
578 tmp = readl(port_mmio + PORT_CMD);
579 if ((tmp & PORT_CMD_LIST_ON) == 0)
584 /* clear SATA phy error, if any */
585 tmp = readl(port_mmio + PORT_SCR_ERR);
586 writel(tmp, port_mmio + PORT_SCR_ERR);
588 /* if DRQ/BSY is set, device needs to be reset.
589 * if so, issue COMRESET
591 tmp = readl(port_mmio + PORT_TFDATA);
592 if (tmp & (ATA_BUSY | ATA_DRQ)) {
593 writel(0x301, port_mmio + PORT_SCR_CTL);
594 readl(port_mmio + PORT_SCR_CTL); /* flush */
596 writel(0x300, port_mmio + PORT_SCR_CTL);
597 readl(port_mmio + PORT_SCR_CTL); /* flush */
601 tmp = readl(port_mmio + PORT_CMD);
602 tmp |= PORT_CMD_START;
603 writel(tmp, port_mmio + PORT_CMD);
604 readl(port_mmio + PORT_CMD); /* flush */
606 printk(KERN_WARNING "ata%u: error occurred, port reset\n", ap->id);
609 static void ahci_eng_timeout(struct ata_port *ap)
611 struct ata_host_set *host_set = ap->host_set;
612 void __iomem *mmio = host_set->mmio_base;
613 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
614 struct ata_queued_cmd *qc;
619 spin_lock_irqsave(&host_set->lock, flags);
621 ahci_intr_error(ap, readl(port_mmio + PORT_IRQ_STAT));
623 qc = ata_qc_from_tag(ap, ap->active_tag);
625 printk(KERN_ERR "ata%u: BUG: timeout without command\n",
628 /* hack alert! We cannot use the supplied completion
629 * function from inside the ->eh_strategy_handler() thread.
630 * libata is the only user of ->eh_strategy_handler() in
631 * any kernel, so the default scsi_done() assumes it is
632 * not being called from the SCSI EH.
634 qc->scsidone = scsi_finish_command;
635 ata_qc_complete(qc, AC_ERR_OTHER);
638 spin_unlock_irqrestore(&host_set->lock, flags);
641 static inline int ahci_host_intr(struct ata_port *ap, struct ata_queued_cmd *qc)
643 void __iomem *mmio = ap->host_set->mmio_base;
644 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
645 u32 status, serr, ci;
647 serr = readl(port_mmio + PORT_SCR_ERR);
648 writel(serr, port_mmio + PORT_SCR_ERR);
650 status = readl(port_mmio + PORT_IRQ_STAT);
651 writel(status, port_mmio + PORT_IRQ_STAT);
653 ci = readl(port_mmio + PORT_CMD_ISSUE);
654 if (likely((ci & 0x1) == 0)) {
656 ata_qc_complete(qc, 0);
661 if (status & PORT_IRQ_FATAL) {
662 ahci_intr_error(ap, status);
664 ata_qc_complete(qc, AC_ERR_OTHER);
670 static void ahci_irq_clear(struct ata_port *ap)
675 static irqreturn_t ahci_interrupt (int irq, void *dev_instance, struct pt_regs *regs)
677 struct ata_host_set *host_set = dev_instance;
678 struct ahci_host_priv *hpriv;
679 unsigned int i, handled = 0;
681 u32 irq_stat, irq_ack = 0;
685 hpriv = host_set->private_data;
686 mmio = host_set->mmio_base;
688 /* sigh. 0xffffffff is a valid return from h/w */
689 irq_stat = readl(mmio + HOST_IRQ_STAT);
690 irq_stat &= hpriv->port_map;
694 spin_lock(&host_set->lock);
696 for (i = 0; i < host_set->n_ports; i++) {
699 if (!(irq_stat & (1 << i)))
702 ap = host_set->ports[i];
704 struct ata_queued_cmd *qc;
705 qc = ata_qc_from_tag(ap, ap->active_tag);
706 if (!ahci_host_intr(ap, qc))
707 if (ata_ratelimit()) {
708 struct pci_dev *pdev =
709 to_pci_dev(ap->host_set->dev);
710 dev_printk(KERN_WARNING, &pdev->dev,
711 "unhandled interrupt on port %u\n",
715 VPRINTK("port %u\n", i);
717 VPRINTK("port %u (no irq)\n", i);
718 if (ata_ratelimit()) {
719 struct pci_dev *pdev =
720 to_pci_dev(ap->host_set->dev);
721 dev_printk(KERN_WARNING, &pdev->dev,
722 "interrupt on disabled port %u\n", i);
730 writel(irq_ack, mmio + HOST_IRQ_STAT);
734 spin_unlock(&host_set->lock);
738 return IRQ_RETVAL(handled);
741 static int ahci_qc_issue(struct ata_queued_cmd *qc)
743 struct ata_port *ap = qc->ap;
744 void __iomem *port_mmio = (void __iomem *) ap->ioaddr.cmd_addr;
746 writel(1, port_mmio + PORT_CMD_ISSUE);
747 readl(port_mmio + PORT_CMD_ISSUE); /* flush */
752 static void ahci_setup_port(struct ata_ioports *port, unsigned long base,
753 unsigned int port_idx)
755 VPRINTK("ENTER, base==0x%lx, port_idx %u\n", base, port_idx);
756 base = ahci_port_base_ul(base, port_idx);
757 VPRINTK("base now==0x%lx\n", base);
759 port->cmd_addr = base;
760 port->scr_addr = base + PORT_SCR;
765 static int ahci_host_init(struct ata_probe_ent *probe_ent)
767 struct ahci_host_priv *hpriv = probe_ent->private_data;
768 struct pci_dev *pdev = to_pci_dev(probe_ent->dev);
769 void __iomem *mmio = probe_ent->mmio_base;
772 unsigned int i, j, using_dac;
774 void __iomem *port_mmio;
776 cap_save = readl(mmio + HOST_CAP);
777 cap_save &= ( (1<<28) | (1<<17) );
778 cap_save |= (1 << 27);
780 /* global controller reset */
781 tmp = readl(mmio + HOST_CTL);
782 if ((tmp & HOST_RESET) == 0) {
783 writel(tmp | HOST_RESET, mmio + HOST_CTL);
784 readl(mmio + HOST_CTL); /* flush */
787 /* reset must complete within 1 second, or
788 * the hardware should be considered fried.
792 tmp = readl(mmio + HOST_CTL);
793 if (tmp & HOST_RESET) {
794 dev_printk(KERN_ERR, &pdev->dev,
795 "controller reset failed (0x%x)\n", tmp);
799 writel(HOST_AHCI_EN, mmio + HOST_CTL);
800 (void) readl(mmio + HOST_CTL); /* flush */
801 writel(cap_save, mmio + HOST_CAP);
802 writel(0xf, mmio + HOST_PORTS_IMPL);
803 (void) readl(mmio + HOST_PORTS_IMPL); /* flush */
805 pci_read_config_word(pdev, 0x92, &tmp16);
807 pci_write_config_word(pdev, 0x92, tmp16);
809 hpriv->cap = readl(mmio + HOST_CAP);
810 hpriv->port_map = readl(mmio + HOST_PORTS_IMPL);
811 probe_ent->n_ports = (hpriv->cap & 0x1f) + 1;
813 VPRINTK("cap 0x%x port_map 0x%x n_ports %d\n",
814 hpriv->cap, hpriv->port_map, probe_ent->n_ports);
816 using_dac = hpriv->cap & HOST_CAP_64;
818 !pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
819 rc = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
821 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
823 dev_printk(KERN_ERR, &pdev->dev,
824 "64-bit DMA enable failed\n");
829 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
831 dev_printk(KERN_ERR, &pdev->dev,
832 "32-bit DMA enable failed\n");
835 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
837 dev_printk(KERN_ERR, &pdev->dev,
838 "32-bit consistent DMA enable failed\n");
843 for (i = 0; i < probe_ent->n_ports; i++) {
844 #if 0 /* BIOSen initialize this incorrectly */
845 if (!(hpriv->port_map & (1 << i)))
849 port_mmio = ahci_port_base(mmio, i);
850 VPRINTK("mmio %p port_mmio %p\n", mmio, port_mmio);
852 ahci_setup_port(&probe_ent->port[i],
853 (unsigned long) mmio, i);
855 /* make sure port is not active */
856 tmp = readl(port_mmio + PORT_CMD);
857 VPRINTK("PORT_CMD 0x%x\n", tmp);
858 if (tmp & (PORT_CMD_LIST_ON | PORT_CMD_FIS_ON |
859 PORT_CMD_FIS_RX | PORT_CMD_START)) {
860 tmp &= ~(PORT_CMD_LIST_ON | PORT_CMD_FIS_ON |
861 PORT_CMD_FIS_RX | PORT_CMD_START);
862 writel(tmp, port_mmio + PORT_CMD);
863 readl(port_mmio + PORT_CMD); /* flush */
865 /* spec says 500 msecs for each bit, so
866 * this is slightly incorrect.
871 writel(PORT_CMD_SPIN_UP, port_mmio + PORT_CMD);
876 tmp = readl(port_mmio + PORT_SCR_STAT);
877 if ((tmp & 0xf) == 0x3)
882 tmp = readl(port_mmio + PORT_SCR_ERR);
883 VPRINTK("PORT_SCR_ERR 0x%x\n", tmp);
884 writel(tmp, port_mmio + PORT_SCR_ERR);
886 /* ack any pending irq events for this port */
887 tmp = readl(port_mmio + PORT_IRQ_STAT);
888 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
890 writel(tmp, port_mmio + PORT_IRQ_STAT);
892 writel(1 << i, mmio + HOST_IRQ_STAT);
894 /* set irq mask (enables interrupts) */
895 writel(DEF_PORT_IRQ, port_mmio + PORT_IRQ_MASK);
898 tmp = readl(mmio + HOST_CTL);
899 VPRINTK("HOST_CTL 0x%x\n", tmp);
900 writel(tmp | HOST_IRQ_EN, mmio + HOST_CTL);
901 tmp = readl(mmio + HOST_CTL);
902 VPRINTK("HOST_CTL 0x%x\n", tmp);
904 pci_set_master(pdev);
909 static void ahci_print_info(struct ata_probe_ent *probe_ent)
911 struct ahci_host_priv *hpriv = probe_ent->private_data;
912 struct pci_dev *pdev = to_pci_dev(probe_ent->dev);
913 void __iomem *mmio = probe_ent->mmio_base;
914 u32 vers, cap, impl, speed;
919 vers = readl(mmio + HOST_VERSION);
921 impl = hpriv->port_map;
923 speed = (cap >> 20) & 0xf;
931 pci_read_config_word(pdev, 0x0a, &cc);
934 else if (cc == 0x0106)
936 else if (cc == 0x0104)
941 dev_printk(KERN_INFO, &pdev->dev,
942 "AHCI %02x%02x.%02x%02x "
943 "%u slots %u ports %s Gbps 0x%x impl %s mode\n"
951 ((cap >> 8) & 0x1f) + 1,
957 dev_printk(KERN_INFO, &pdev->dev,
963 cap & (1 << 31) ? "64bit " : "",
964 cap & (1 << 30) ? "ncq " : "",
965 cap & (1 << 28) ? "ilck " : "",
966 cap & (1 << 27) ? "stag " : "",
967 cap & (1 << 26) ? "pm " : "",
968 cap & (1 << 25) ? "led " : "",
970 cap & (1 << 24) ? "clo " : "",
971 cap & (1 << 19) ? "nz " : "",
972 cap & (1 << 18) ? "only " : "",
973 cap & (1 << 17) ? "pmp " : "",
974 cap & (1 << 15) ? "pio " : "",
975 cap & (1 << 14) ? "slum " : "",
976 cap & (1 << 13) ? "part " : ""
980 static int ahci_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
982 static int printed_version;
983 struct ata_probe_ent *probe_ent = NULL;
984 struct ahci_host_priv *hpriv;
986 void __iomem *mmio_base;
987 unsigned int board_idx = (unsigned int) ent->driver_data;
988 int have_msi, pci_dev_busy = 0;
993 if (!printed_version++)
994 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
996 rc = pci_enable_device(pdev);
1000 rc = pci_request_regions(pdev, DRV_NAME);
1006 if (pci_enable_msi(pdev) == 0)
1013 probe_ent = kmalloc(sizeof(*probe_ent), GFP_KERNEL);
1014 if (probe_ent == NULL) {
1019 memset(probe_ent, 0, sizeof(*probe_ent));
1020 probe_ent->dev = pci_dev_to_dev(pdev);
1021 INIT_LIST_HEAD(&probe_ent->node);
1023 mmio_base = pci_iomap(pdev, AHCI_PCI_BAR, 0);
1024 if (mmio_base == NULL) {
1026 goto err_out_free_ent;
1028 base = (unsigned long) mmio_base;
1030 hpriv = kmalloc(sizeof(*hpriv), GFP_KERNEL);
1033 goto err_out_iounmap;
1035 memset(hpriv, 0, sizeof(*hpriv));
1037 probe_ent->sht = ahci_port_info[board_idx].sht;
1038 probe_ent->host_flags = ahci_port_info[board_idx].host_flags;
1039 probe_ent->pio_mask = ahci_port_info[board_idx].pio_mask;
1040 probe_ent->udma_mask = ahci_port_info[board_idx].udma_mask;
1041 probe_ent->port_ops = ahci_port_info[board_idx].port_ops;
1043 probe_ent->irq = pdev->irq;
1044 probe_ent->irq_flags = SA_SHIRQ;
1045 probe_ent->mmio_base = mmio_base;
1046 probe_ent->private_data = hpriv;
1049 hpriv->flags |= AHCI_FLAG_MSI;
1051 /* initialize adapter */
1052 rc = ahci_host_init(probe_ent);
1056 ahci_print_info(probe_ent);
1058 /* FIXME: check ata_device_add return value */
1059 ata_device_add(probe_ent);
1067 pci_iounmap(pdev, mmio_base);
1072 pci_disable_msi(pdev);
1075 pci_release_regions(pdev);
1078 pci_disable_device(pdev);
1082 static void ahci_remove_one (struct pci_dev *pdev)
1084 struct device *dev = pci_dev_to_dev(pdev);
1085 struct ata_host_set *host_set = dev_get_drvdata(dev);
1086 struct ahci_host_priv *hpriv = host_set->private_data;
1087 struct ata_port *ap;
1091 for (i = 0; i < host_set->n_ports; i++) {
1092 ap = host_set->ports[i];
1094 scsi_remove_host(ap->host);
1097 have_msi = hpriv->flags & AHCI_FLAG_MSI;
1098 free_irq(host_set->irq, host_set);
1100 for (i = 0; i < host_set->n_ports; i++) {
1101 ap = host_set->ports[i];
1103 ata_scsi_release(ap->host);
1104 scsi_host_put(ap->host);
1108 pci_iounmap(pdev, host_set->mmio_base);
1112 pci_disable_msi(pdev);
1115 pci_release_regions(pdev);
1116 pci_disable_device(pdev);
1117 dev_set_drvdata(dev, NULL);
1120 static int __init ahci_init(void)
1122 return pci_module_init(&ahci_pci_driver);
1125 static void __exit ahci_exit(void)
1127 pci_unregister_driver(&ahci_pci_driver);
1131 MODULE_AUTHOR("Jeff Garzik");
1132 MODULE_DESCRIPTION("AHCI SATA low-level driver");
1133 MODULE_LICENSE("GPL");
1134 MODULE_DEVICE_TABLE(pci, ahci_pci_tbl);
1135 MODULE_VERSION(DRV_VERSION);
1137 module_init(ahci_init);
1138 module_exit(ahci_exit);