2 * ata_piix.c - Intel PATA/SATA controllers
4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
9 * Copyright 2003-2005 Red Hat Inc
10 * Copyright 2003-2005 Jeff Garzik
13 * Copyright header from piix.c:
15 * Copyright (C) 1998-1999 Andrzej Krzysztofowicz, Author and Maintainer
16 * Copyright (C) 1998-2000 Andre Hedrick <andre@linux-ide.org>
17 * Copyright (C) 2003 Red Hat Inc <alan@redhat.com>
20 * This program is free software; you can redistribute it and/or modify
21 * it under the terms of the GNU General Public License as published by
22 * the Free Software Foundation; either version 2, or (at your option)
25 * This program is distributed in the hope that it will be useful,
26 * but WITHOUT ANY WARRANTY; without even the implied warranty of
27 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
28 * GNU General Public License for more details.
30 * You should have received a copy of the GNU General Public License
31 * along with this program; see the file COPYING. If not, write to
32 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
35 * libata documentation is available via 'make {ps|pdf}docs',
36 * as Documentation/DocBook/libata.*
38 * Hardware documentation available at http://developer.intel.com/
41 * Publically available from Intel web site. Errata documentation
42 * is also publically available. As an aide to anyone hacking on this
43 * driver the list of errata that are relevant is below.going back to
44 * PIIX4. Older device documentation is now a bit tricky to find.
46 * The chipsets all follow very much the same design. The orginal Triton
47 * series chipsets do _not_ support independant device timings, but this
48 * is fixed in Triton II. With the odd mobile exception the chips then
49 * change little except in gaining more modes until SATA arrives. This
50 * driver supports only the chips with independant timing (that is those
51 * with SITRE and the 0x44 timing register). See pata_oldpiix and pata_mpiix
52 * for the early chip drivers.
57 * PIIX4 errata #9 - Only on ultra obscure hw
58 * ICH3 errata #13 - Not observed to affect real hw
61 * Things we must deal with
62 * PIIX4 errata #10 - BM IDE hang with non UDMA
63 * (must stop/start dma to recover)
64 * 440MX errata #15 - As PIIX4 errata #10
65 * PIIX4 errata #15 - Must not read control registers
66 * during a PIO transfer
67 * 440MX errata #13 - As PIIX4 errata #15
68 * ICH2 errata #21 - DMA mode 0 doesn't work right
69 * ICH0/1 errata #55 - As ICH2 errata #21
70 * ICH2 spec c #9 - Extra operations needed to handle
71 * drive hotswap [NOT YET SUPPORTED]
72 * ICH2 spec c #20 - IDE PRD must not cross a 64K boundary
73 * and must be dword aligned
74 * ICH2 spec c #24 - UDMA mode 4,5 t85/86 should be 6ns not 3.3
76 * Should have been BIOS fixed:
77 * 450NX: errata #19 - DMA hangs on old 450NX
78 * 450NX: errata #20 - DMA hangs on old 450NX
79 * 450NX: errata #25 - Corruption with DMA on old 450NX
80 * ICH3 errata #15 - IDE deadlock under high load
81 * (BIOS must set dev 31 fn 0 bit 23)
82 * ICH3 errata #18 - Don't use native mode
85 #include <linux/kernel.h>
86 #include <linux/module.h>
87 #include <linux/pci.h>
88 #include <linux/init.h>
89 #include <linux/blkdev.h>
90 #include <linux/delay.h>
91 #include <linux/device.h>
92 #include <scsi/scsi_host.h>
93 #include <linux/libata.h>
95 #define DRV_NAME "ata_piix"
96 #define DRV_VERSION "1.05"
99 PIIX_IOCFG = 0x54, /* IDE I/O configuration register */
100 ICH5_PMR = 0x90, /* port mapping register */
101 ICH5_PCS = 0x92, /* port control and status */
102 PIIX_SCC = 0x0A, /* sub-class code register */
104 PIIX_FLAG_AHCI = (1 << 28), /* AHCI possible */
105 PIIX_FLAG_CHECKINTR = (1 << 29), /* make sure PCI INTx enabled */
106 PIIX_FLAG_COMBINED = (1 << 30), /* combined mode possible */
108 /* combined mode. if set, PATA is channel 0.
109 * if clear, PATA is channel 1.
111 PIIX_COMB_PATA_P0 = (1 << 1),
112 PIIX_COMB = (1 << 2), /* combined mode enabled? */
114 PIIX_PORT_ENABLED = (1 << 0),
115 PIIX_PORT_PRESENT = (1 << 4),
117 PIIX_80C_PRI = (1 << 5) | (1 << 4),
118 PIIX_80C_SEC = (1 << 7) | (1 << 6),
126 PIIX_AHCI_DEVICE = 6,
129 static int piix_init_one (struct pci_dev *pdev,
130 const struct pci_device_id *ent);
132 static void piix_pata_phy_reset(struct ata_port *ap);
133 static void piix_sata_phy_reset(struct ata_port *ap);
134 static void piix_set_piomode (struct ata_port *ap, struct ata_device *adev);
135 static void piix_set_dmamode (struct ata_port *ap, struct ata_device *adev);
137 static unsigned int in_module_init = 1;
139 static const struct pci_device_id piix_pci_tbl[] = {
140 #ifdef ATA_ENABLE_PATA
141 { 0x8086, 0x7111, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix4_pata },
142 { 0x8086, 0x24db, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_pata },
143 { 0x8086, 0x25a2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_pata },
146 /* NOTE: The following PCI ids must be kept in sync with the
147 * list in drivers/pci/quirks.c.
150 { 0x8086, 0x24d1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
151 { 0x8086, 0x24df, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
152 { 0x8086, 0x25a3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
153 { 0x8086, 0x25b0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
154 { 0x8086, 0x2651, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata },
155 { 0x8086, 0x2652, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata_ahci },
156 { 0x8086, 0x2653, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata_ahci },
157 { 0x8086, 0x27c0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata_ahci },
158 { 0x8086, 0x27c4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata_ahci },
159 { 0x8086, 0x2680, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata_ahci },
161 { } /* terminate list */
164 static struct pci_driver piix_pci_driver = {
166 .id_table = piix_pci_tbl,
167 .probe = piix_init_one,
168 .remove = ata_pci_remove_one,
169 .suspend = ata_pci_device_suspend,
170 .resume = ata_pci_device_resume,
173 static struct scsi_host_template piix_sht = {
174 .module = THIS_MODULE,
176 .ioctl = ata_scsi_ioctl,
177 .queuecommand = ata_scsi_queuecmd,
178 .eh_strategy_handler = ata_scsi_error,
179 .can_queue = ATA_DEF_QUEUE,
180 .this_id = ATA_SHT_THIS_ID,
181 .sg_tablesize = LIBATA_MAX_PRD,
182 .max_sectors = ATA_MAX_SECTORS,
183 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
184 .emulated = ATA_SHT_EMULATED,
185 .use_clustering = ATA_SHT_USE_CLUSTERING,
186 .proc_name = DRV_NAME,
187 .dma_boundary = ATA_DMA_BOUNDARY,
188 .slave_configure = ata_scsi_slave_config,
189 .bios_param = ata_std_bios_param,
191 .resume = ata_scsi_device_resume,
192 .suspend = ata_scsi_device_suspend,
195 static const struct ata_port_operations piix_pata_ops = {
196 .port_disable = ata_port_disable,
197 .set_piomode = piix_set_piomode,
198 .set_dmamode = piix_set_dmamode,
200 .tf_load = ata_tf_load,
201 .tf_read = ata_tf_read,
202 .check_status = ata_check_status,
203 .exec_command = ata_exec_command,
204 .dev_select = ata_std_dev_select,
206 .phy_reset = piix_pata_phy_reset,
208 .bmdma_setup = ata_bmdma_setup,
209 .bmdma_start = ata_bmdma_start,
210 .bmdma_stop = ata_bmdma_stop,
211 .bmdma_status = ata_bmdma_status,
212 .qc_prep = ata_qc_prep,
213 .qc_issue = ata_qc_issue_prot,
215 .eng_timeout = ata_eng_timeout,
217 .irq_handler = ata_interrupt,
218 .irq_clear = ata_bmdma_irq_clear,
220 .port_start = ata_port_start,
221 .port_stop = ata_port_stop,
222 .host_stop = ata_host_stop,
225 static const struct ata_port_operations piix_sata_ops = {
226 .port_disable = ata_port_disable,
228 .tf_load = ata_tf_load,
229 .tf_read = ata_tf_read,
230 .check_status = ata_check_status,
231 .exec_command = ata_exec_command,
232 .dev_select = ata_std_dev_select,
234 .phy_reset = piix_sata_phy_reset,
236 .bmdma_setup = ata_bmdma_setup,
237 .bmdma_start = ata_bmdma_start,
238 .bmdma_stop = ata_bmdma_stop,
239 .bmdma_status = ata_bmdma_status,
240 .qc_prep = ata_qc_prep,
241 .qc_issue = ata_qc_issue_prot,
243 .eng_timeout = ata_eng_timeout,
245 .irq_handler = ata_interrupt,
246 .irq_clear = ata_bmdma_irq_clear,
248 .port_start = ata_port_start,
249 .port_stop = ata_port_stop,
250 .host_stop = ata_host_stop,
253 static struct ata_port_info piix_port_info[] = {
257 .host_flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST |
259 .pio_mask = 0x1f, /* pio0-4 */
261 .mwdma_mask = 0x06, /* mwdma1-2 */
263 .mwdma_mask = 0x00, /* mwdma broken */
265 .udma_mask = 0x3f, /* udma0-5 */
266 .port_ops = &piix_pata_ops,
272 .host_flags = ATA_FLAG_SATA | ATA_FLAG_SRST |
273 PIIX_FLAG_COMBINED | PIIX_FLAG_CHECKINTR,
274 .pio_mask = 0x1f, /* pio0-4 */
275 .mwdma_mask = 0x07, /* mwdma0-2 */
276 .udma_mask = 0x7f, /* udma0-6 */
277 .port_ops = &piix_sata_ops,
283 .host_flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
284 .pio_mask = 0x1f, /* pio0-4 */
286 .mwdma_mask = 0x06, /* mwdma1-2 */
288 .mwdma_mask = 0x00, /* mwdma broken */
290 .udma_mask = ATA_UDMA_MASK_40C,
291 .port_ops = &piix_pata_ops,
297 .host_flags = ATA_FLAG_SATA | ATA_FLAG_SRST |
298 PIIX_FLAG_COMBINED | PIIX_FLAG_CHECKINTR |
300 .pio_mask = 0x1f, /* pio0-4 */
301 .mwdma_mask = 0x07, /* mwdma0-2 */
302 .udma_mask = 0x7f, /* udma0-6 */
303 .port_ops = &piix_sata_ops,
309 .host_flags = ATA_FLAG_SATA | ATA_FLAG_SRST |
310 PIIX_FLAG_COMBINED | PIIX_FLAG_CHECKINTR |
311 ATA_FLAG_SLAVE_POSS | PIIX_FLAG_AHCI,
312 .pio_mask = 0x1f, /* pio0-4 */
313 .mwdma_mask = 0x07, /* mwdma0-2 */
314 .udma_mask = 0x7f, /* udma0-6 */
315 .port_ops = &piix_sata_ops,
319 static struct pci_bits piix_enable_bits[] = {
320 { 0x41U, 1U, 0x80UL, 0x80UL }, /* port 0 */
321 { 0x43U, 1U, 0x80UL, 0x80UL }, /* port 1 */
324 MODULE_AUTHOR("Andre Hedrick, Alan Cox, Andrzej Krzysztofowicz, Jeff Garzik");
325 MODULE_DESCRIPTION("SCSI low-level driver for Intel PIIX/ICH ATA controllers");
326 MODULE_LICENSE("GPL");
327 MODULE_DEVICE_TABLE(pci, piix_pci_tbl);
328 MODULE_VERSION(DRV_VERSION);
331 * piix_pata_cbl_detect - Probe host controller cable detect info
332 * @ap: Port for which cable detect info is desired
334 * Read 80c cable indicator from ATA PCI device's PCI config
335 * register. This register is normally set by firmware (BIOS).
338 * None (inherited from caller).
340 static void piix_pata_cbl_detect(struct ata_port *ap)
342 struct pci_dev *pdev = to_pci_dev(ap->host_set->dev);
345 /* no 80c support in host controller? */
346 if ((ap->udma_mask & ~ATA_UDMA_MASK_40C) == 0)
349 /* check BIOS cable detect results */
350 mask = ap->hard_port_no == 0 ? PIIX_80C_PRI : PIIX_80C_SEC;
351 pci_read_config_byte(pdev, PIIX_IOCFG, &tmp);
352 if ((tmp & mask) == 0)
355 ap->cbl = ATA_CBL_PATA80;
359 ap->cbl = ATA_CBL_PATA40;
360 ap->udma_mask &= ATA_UDMA_MASK_40C;
364 * piix_pata_phy_reset - Probe specified port on PATA host controller
370 * None (inherited from caller).
373 static void piix_pata_phy_reset(struct ata_port *ap)
375 struct pci_dev *pdev = to_pci_dev(ap->host_set->dev);
377 if (!pci_test_config_bits(pdev, &piix_enable_bits[ap->hard_port_no])) {
378 ata_port_disable(ap);
379 printk(KERN_INFO "ata%u: port disabled. ignoring.\n", ap->id);
383 piix_pata_cbl_detect(ap);
391 * piix_sata_probe - Probe PCI device for present SATA devices
392 * @ap: Port associated with the PCI device we wish to probe
394 * Reads SATA PCI device's PCI config register Port Configuration
395 * and Status (PCS) to determine port and device availability.
398 * None (inherited from caller).
401 * Non-zero if port is enabled, it may or may not have a device
402 * attached in that case (PRESENT bit would only be set if BIOS probe
403 * was done). Zero is returned if port is disabled.
405 static int piix_sata_probe (struct ata_port *ap)
407 struct pci_dev *pdev = to_pci_dev(ap->host_set->dev);
408 int combined = (ap->flags & ATA_FLAG_SLAVE_POSS);
409 int orig_mask, mask, i;
412 mask = (PIIX_PORT_PRESENT << ap->hard_port_no) |
413 (PIIX_PORT_ENABLED << ap->hard_port_no);
415 pci_read_config_byte(pdev, ICH5_PCS, &pcs);
416 orig_mask = (int) pcs & 0xff;
418 /* TODO: this is vaguely wrong for ICH6 combined mode,
419 * where only two of the four SATA ports are mapped
420 * onto a single ATA channel. It is also vaguely inaccurate
421 * for ICH5, which has only two ports. However, this is ok,
422 * as further device presence detection code will handle
423 * any false positives produced here.
426 for (i = 0; i < 4; i++) {
427 mask = (PIIX_PORT_ENABLED << i);
429 if ((orig_mask & mask) == mask)
430 if (combined || (i == ap->hard_port_no))
438 * piix_sata_phy_reset - Probe specified port on SATA host controller
444 * None (inherited from caller).
447 static void piix_sata_phy_reset(struct ata_port *ap)
449 if (!piix_sata_probe(ap)) {
450 ata_port_disable(ap);
451 printk(KERN_INFO "ata%u: SATA port has no device.\n", ap->id);
455 ap->cbl = ATA_CBL_SATA;
463 * piix_set_piomode - Initialize host controller PATA PIO timings
464 * @ap: Port whose timings we are configuring
467 * Set PIO mode for device, in host controller PCI config space.
470 * None (inherited from caller).
473 static void piix_set_piomode (struct ata_port *ap, struct ata_device *adev)
475 unsigned int pio = adev->pio_mode - XFER_PIO_0;
476 struct pci_dev *dev = to_pci_dev(ap->host_set->dev);
477 unsigned int is_slave = (adev->devno != 0);
478 unsigned int master_port= ap->hard_port_no ? 0x42 : 0x40;
479 unsigned int slave_port = 0x44;
483 static const /* ISP RTC */
484 u8 timings[][2] = { { 0, 0 },
490 pci_read_config_word(dev, master_port, &master_data);
492 master_data |= 0x4000;
493 /* enable PPE, IE and TIME */
494 master_data |= 0x0070;
495 pci_read_config_byte(dev, slave_port, &slave_data);
496 slave_data &= (ap->hard_port_no ? 0x0f : 0xf0);
498 (timings[pio][0] << 2) |
499 (timings[pio][1] << (ap->hard_port_no ? 4 : 0));
501 master_data &= 0xccf8;
502 /* enable PPE, IE and TIME */
503 master_data |= 0x0007;
505 (timings[pio][0] << 12) |
506 (timings[pio][1] << 8);
508 pci_write_config_word(dev, master_port, master_data);
510 pci_write_config_byte(dev, slave_port, slave_data);
514 * piix_set_dmamode - Initialize host controller PATA PIO timings
515 * @ap: Port whose timings we are configuring
517 * @udma: udma mode, 0 - 6
519 * Set UDMA mode for device, in host controller PCI config space.
522 * None (inherited from caller).
525 static void piix_set_dmamode (struct ata_port *ap, struct ata_device *adev)
527 unsigned int udma = adev->dma_mode; /* FIXME: MWDMA too */
528 struct pci_dev *dev = to_pci_dev(ap->host_set->dev);
529 u8 maslave = ap->hard_port_no ? 0x42 : 0x40;
531 unsigned int drive_dn = (ap->hard_port_no ? 2 : 0) + adev->devno;
532 int a_speed = 3 << (drive_dn * 4);
533 int u_flag = 1 << drive_dn;
534 int v_flag = 0x01 << drive_dn;
535 int w_flag = 0x10 << drive_dn;
539 u8 reg48, reg54, reg55;
541 pci_read_config_word(dev, maslave, ®4042);
542 DPRINTK("reg4042 = 0x%04x\n", reg4042);
543 sitre = (reg4042 & 0x4000) ? 1 : 0;
544 pci_read_config_byte(dev, 0x48, ®48);
545 pci_read_config_word(dev, 0x4a, ®4a);
546 pci_read_config_byte(dev, 0x54, ®54);
547 pci_read_config_byte(dev, 0x55, ®55);
551 case XFER_UDMA_2: u_speed = 2 << (drive_dn * 4); break;
555 case XFER_UDMA_1: u_speed = 1 << (drive_dn * 4); break;
556 case XFER_UDMA_0: u_speed = 0 << (drive_dn * 4); break;
558 case XFER_MW_DMA_1: break;
564 if (speed >= XFER_UDMA_0) {
565 if (!(reg48 & u_flag))
566 pci_write_config_byte(dev, 0x48, reg48 | u_flag);
567 if (speed == XFER_UDMA_5) {
568 pci_write_config_byte(dev, 0x55, (u8) reg55|w_flag);
570 pci_write_config_byte(dev, 0x55, (u8) reg55 & ~w_flag);
572 if ((reg4a & a_speed) != u_speed)
573 pci_write_config_word(dev, 0x4a, (reg4a & ~a_speed) | u_speed);
574 if (speed > XFER_UDMA_2) {
575 if (!(reg54 & v_flag))
576 pci_write_config_byte(dev, 0x54, reg54 | v_flag);
578 pci_write_config_byte(dev, 0x54, reg54 & ~v_flag);
581 pci_write_config_byte(dev, 0x48, reg48 & ~u_flag);
583 pci_write_config_word(dev, 0x4a, reg4a & ~a_speed);
585 pci_write_config_byte(dev, 0x54, reg54 & ~v_flag);
587 pci_write_config_byte(dev, 0x55, (u8) reg55 & ~w_flag);
591 #define AHCI_PCI_BAR 5
592 #define AHCI_GLOBAL_CTL 0x04
593 #define AHCI_ENABLE (1 << 31)
594 static int piix_disable_ahci(struct pci_dev *pdev)
600 /* BUG: pci_enable_device has not yet been called. This
601 * works because this device is usually set up by BIOS.
604 if (!pci_resource_start(pdev, AHCI_PCI_BAR) ||
605 !pci_resource_len(pdev, AHCI_PCI_BAR))
608 mmio = pci_iomap(pdev, AHCI_PCI_BAR, 64);
612 tmp = readl(mmio + AHCI_GLOBAL_CTL);
613 if (tmp & AHCI_ENABLE) {
615 writel(tmp, mmio + AHCI_GLOBAL_CTL);
617 tmp = readl(mmio + AHCI_GLOBAL_CTL);
618 if (tmp & AHCI_ENABLE)
622 pci_iounmap(pdev, mmio);
627 * piix_check_450nx_errata - Check for problem 450NX setup
629 * Check for the present of 450NX errata #19 and errata #25. If
630 * they are found return an error code so we can turn off DMA
633 static int __devinit piix_check_450nx_errata(struct pci_dev *ata_dev)
635 struct pci_dev *pdev = NULL;
640 while((pdev = pci_get_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, pdev)) != NULL)
642 /* Look for 450NX PXB. Check for problem configurations
643 A PCI quirk checks bit 6 already */
644 pci_read_config_byte(pdev, PCI_REVISION_ID, &rev);
645 pci_read_config_word(pdev, 0x41, &cfg);
646 /* Only on the original revision: IDE DMA can hang */
649 /* On all revisions below 5 PXB bus lock must be disabled for IDE */
650 else if(cfg & (1<<14) && rev < 5)
654 dev_printk(KERN_WARNING, &ata_dev->dev, "450NX errata present, disabling IDE DMA.\n");
656 dev_printk(KERN_WARNING, &ata_dev->dev, "A BIOS update may resolve this.\n");
661 * piix_init_one - Register PIIX ATA PCI device with kernel services
662 * @pdev: PCI device to register
663 * @ent: Entry in piix_pci_tbl matching with @pdev
665 * Called from kernel PCI layer. We probe for combined mode (sigh),
666 * and then hand over control to libata, for it to do the rest.
669 * Inherited from PCI layer (may sleep).
672 * Zero on success, or -ERRNO value.
675 static int piix_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
677 static int printed_version;
678 struct ata_port_info *port_info[2];
679 unsigned int combined = 0;
680 unsigned int pata_chan = 0, sata_chan = 0;
682 if (!printed_version++)
683 dev_printk(KERN_DEBUG, &pdev->dev,
684 "version " DRV_VERSION "\n");
686 /* no hotplugging support (FIXME) */
690 port_info[0] = &piix_port_info[ent->driver_data];
691 port_info[1] = &piix_port_info[ent->driver_data];
693 if (port_info[0]->host_flags & PIIX_FLAG_AHCI) {
695 pci_read_config_byte(pdev, PIIX_SCC, &tmp);
696 if (tmp == PIIX_AHCI_DEVICE) {
697 int rc = piix_disable_ahci(pdev);
703 if (port_info[0]->host_flags & PIIX_FLAG_COMBINED) {
705 pci_read_config_byte(pdev, ICH5_PMR, &tmp);
707 if (tmp & PIIX_COMB) {
709 if (tmp & PIIX_COMB_PATA_P0)
716 /* On ICH5, some BIOSen disable the interrupt using the
717 * PCI_COMMAND_INTX_DISABLE bit added in PCI 2.3.
718 * On ICH6, this bit has the same effect, but only when
719 * MSI is disabled (and it is disabled, as we don't use
720 * message-signalled interrupts currently).
722 if (port_info[0]->host_flags & PIIX_FLAG_CHECKINTR)
726 port_info[sata_chan] = &piix_port_info[ent->driver_data];
727 port_info[sata_chan]->host_flags |= ATA_FLAG_SLAVE_POSS;
728 port_info[pata_chan] = &piix_port_info[ich5_pata];
730 dev_printk(KERN_WARNING, &pdev->dev,
731 "combined mode detected (p=%u, s=%u)\n",
732 pata_chan, sata_chan);
734 if (piix_check_450nx_errata(pdev)) {
735 /* This writes into the master table but it does not
736 really matter for this errata as we will apply it to
737 all the PIIX devices on the board */
738 port_info[0]->mwdma_mask = 0;
739 port_info[0]->udma_mask = 0;
740 port_info[1]->mwdma_mask = 0;
741 port_info[1]->udma_mask = 0;
743 return ata_pci_init_one(pdev, port_info, 2);
746 static int __init piix_init(void)
750 DPRINTK("pci_module_init\n");
751 rc = pci_module_init(&piix_pci_driver);
761 static void __exit piix_exit(void)
763 pci_unregister_driver(&piix_pci_driver);
766 module_init(piix_init);
767 module_exit(piix_exit);