2 * QLogic Fibre Channel HBA Driver
3 * Copyright (c) 2003-2008 QLogic Corporation
5 * See LICENSE.qla2xxx for copyright and licensing details.
9 #include <linux/delay.h>
10 #include <linux/vmalloc.h>
11 #include <asm/uaccess.h>
14 * NVRAM support routines
18 * qla2x00_lock_nvram_access() -
22 qla2x00_lock_nvram_access(struct qla_hw_data *ha)
25 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
27 if (!IS_QLA2100(ha) && !IS_QLA2200(ha) && !IS_QLA2300(ha)) {
28 data = RD_REG_WORD(®->nvram);
29 while (data & NVR_BUSY) {
31 data = RD_REG_WORD(®->nvram);
35 WRT_REG_WORD(®->u.isp2300.host_semaphore, 0x1);
36 RD_REG_WORD(®->u.isp2300.host_semaphore);
38 data = RD_REG_WORD(®->u.isp2300.host_semaphore);
39 while ((data & BIT_0) == 0) {
42 WRT_REG_WORD(®->u.isp2300.host_semaphore, 0x1);
43 RD_REG_WORD(®->u.isp2300.host_semaphore);
45 data = RD_REG_WORD(®->u.isp2300.host_semaphore);
51 * qla2x00_unlock_nvram_access() -
55 qla2x00_unlock_nvram_access(struct qla_hw_data *ha)
57 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
59 if (!IS_QLA2100(ha) && !IS_QLA2200(ha) && !IS_QLA2300(ha)) {
60 WRT_REG_WORD(®->u.isp2300.host_semaphore, 0);
61 RD_REG_WORD(®->u.isp2300.host_semaphore);
66 * qla2x00_nv_write() - Prepare for NVRAM read/write operation.
68 * @data: Serial interface selector
71 qla2x00_nv_write(struct qla_hw_data *ha, uint16_t data)
73 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
75 WRT_REG_WORD(®->nvram, data | NVR_SELECT | NVR_WRT_ENABLE);
76 RD_REG_WORD(®->nvram); /* PCI Posting. */
78 WRT_REG_WORD(®->nvram, data | NVR_SELECT | NVR_CLOCK |
80 RD_REG_WORD(®->nvram); /* PCI Posting. */
82 WRT_REG_WORD(®->nvram, data | NVR_SELECT | NVR_WRT_ENABLE);
83 RD_REG_WORD(®->nvram); /* PCI Posting. */
88 * qla2x00_nvram_request() - Sends read command to NVRAM and gets data from
91 * @nv_cmd: NVRAM command
93 * Bit definitions for NVRAM command:
98 * Bit 15-0 = write data
100 * Returns the word read from nvram @addr.
103 qla2x00_nvram_request(struct qla_hw_data *ha, uint32_t nv_cmd)
106 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
110 /* Send command to NVRAM. */
112 for (cnt = 0; cnt < 11; cnt++) {
114 qla2x00_nv_write(ha, NVR_DATA_OUT);
116 qla2x00_nv_write(ha, 0);
120 /* Read data from NVRAM. */
121 for (cnt = 0; cnt < 16; cnt++) {
122 WRT_REG_WORD(®->nvram, NVR_SELECT | NVR_CLOCK);
123 RD_REG_WORD(®->nvram); /* PCI Posting. */
126 reg_data = RD_REG_WORD(®->nvram);
127 if (reg_data & NVR_DATA_IN)
129 WRT_REG_WORD(®->nvram, NVR_SELECT);
130 RD_REG_WORD(®->nvram); /* PCI Posting. */
135 WRT_REG_WORD(®->nvram, NVR_DESELECT);
136 RD_REG_WORD(®->nvram); /* PCI Posting. */
144 * qla2x00_get_nvram_word() - Calculates word position in NVRAM and calls the
145 * request routine to get the word from NVRAM.
147 * @addr: Address in NVRAM to read
149 * Returns the word read from nvram @addr.
152 qla2x00_get_nvram_word(struct qla_hw_data *ha, uint32_t addr)
158 nv_cmd |= NV_READ_OP;
159 data = qla2x00_nvram_request(ha, nv_cmd);
165 * qla2x00_nv_deselect() - Deselect NVRAM operations.
169 qla2x00_nv_deselect(struct qla_hw_data *ha)
171 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
173 WRT_REG_WORD(®->nvram, NVR_DESELECT);
174 RD_REG_WORD(®->nvram); /* PCI Posting. */
179 * qla2x00_write_nvram_word() - Write NVRAM data.
181 * @addr: Address in NVRAM to write
182 * @data: word to program
185 qla2x00_write_nvram_word(struct qla_hw_data *ha, uint32_t addr, uint16_t data)
189 uint32_t nv_cmd, wait_cnt;
190 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
192 qla2x00_nv_write(ha, NVR_DATA_OUT);
193 qla2x00_nv_write(ha, 0);
194 qla2x00_nv_write(ha, 0);
196 for (word = 0; word < 8; word++)
197 qla2x00_nv_write(ha, NVR_DATA_OUT);
199 qla2x00_nv_deselect(ha);
202 nv_cmd = (addr << 16) | NV_WRITE_OP;
205 for (count = 0; count < 27; count++) {
207 qla2x00_nv_write(ha, NVR_DATA_OUT);
209 qla2x00_nv_write(ha, 0);
214 qla2x00_nv_deselect(ha);
216 /* Wait for NVRAM to become ready */
217 WRT_REG_WORD(®->nvram, NVR_SELECT);
218 RD_REG_WORD(®->nvram); /* PCI Posting. */
219 wait_cnt = NVR_WAIT_CNT;
222 DEBUG9_10(printk("%s(%ld): NVRAM didn't go ready...\n",
223 __func__, vha->host_no));
227 word = RD_REG_WORD(®->nvram);
228 } while ((word & NVR_DATA_IN) == 0);
230 qla2x00_nv_deselect(ha);
233 qla2x00_nv_write(ha, NVR_DATA_OUT);
234 for (count = 0; count < 10; count++)
235 qla2x00_nv_write(ha, 0);
237 qla2x00_nv_deselect(ha);
241 qla2x00_write_nvram_word_tmo(struct qla_hw_data *ha, uint32_t addr,
242 uint16_t data, uint32_t tmo)
247 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
251 qla2x00_nv_write(ha, NVR_DATA_OUT);
252 qla2x00_nv_write(ha, 0);
253 qla2x00_nv_write(ha, 0);
255 for (word = 0; word < 8; word++)
256 qla2x00_nv_write(ha, NVR_DATA_OUT);
258 qla2x00_nv_deselect(ha);
261 nv_cmd = (addr << 16) | NV_WRITE_OP;
264 for (count = 0; count < 27; count++) {
266 qla2x00_nv_write(ha, NVR_DATA_OUT);
268 qla2x00_nv_write(ha, 0);
273 qla2x00_nv_deselect(ha);
275 /* Wait for NVRAM to become ready */
276 WRT_REG_WORD(®->nvram, NVR_SELECT);
277 RD_REG_WORD(®->nvram); /* PCI Posting. */
280 word = RD_REG_WORD(®->nvram);
282 ret = QLA_FUNCTION_FAILED;
285 } while ((word & NVR_DATA_IN) == 0);
287 qla2x00_nv_deselect(ha);
290 qla2x00_nv_write(ha, NVR_DATA_OUT);
291 for (count = 0; count < 10; count++)
292 qla2x00_nv_write(ha, 0);
294 qla2x00_nv_deselect(ha);
300 * qla2x00_clear_nvram_protection() -
304 qla2x00_clear_nvram_protection(struct qla_hw_data *ha)
307 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
308 uint32_t word, wait_cnt;
309 uint16_t wprot, wprot_old;
311 /* Clear NVRAM write protection. */
312 ret = QLA_FUNCTION_FAILED;
314 wprot_old = cpu_to_le16(qla2x00_get_nvram_word(ha, ha->nvram_base));
315 stat = qla2x00_write_nvram_word_tmo(ha, ha->nvram_base,
316 __constant_cpu_to_le16(0x1234), 100000);
317 wprot = cpu_to_le16(qla2x00_get_nvram_word(ha, ha->nvram_base));
318 if (stat != QLA_SUCCESS || wprot != 0x1234) {
320 qla2x00_nv_write(ha, NVR_DATA_OUT);
321 qla2x00_nv_write(ha, 0);
322 qla2x00_nv_write(ha, 0);
323 for (word = 0; word < 8; word++)
324 qla2x00_nv_write(ha, NVR_DATA_OUT);
326 qla2x00_nv_deselect(ha);
328 /* Enable protection register. */
329 qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT);
330 qla2x00_nv_write(ha, NVR_PR_ENABLE);
331 qla2x00_nv_write(ha, NVR_PR_ENABLE);
332 for (word = 0; word < 8; word++)
333 qla2x00_nv_write(ha, NVR_DATA_OUT | NVR_PR_ENABLE);
335 qla2x00_nv_deselect(ha);
337 /* Clear protection register (ffff is cleared). */
338 qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT);
339 qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT);
340 qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT);
341 for (word = 0; word < 8; word++)
342 qla2x00_nv_write(ha, NVR_DATA_OUT | NVR_PR_ENABLE);
344 qla2x00_nv_deselect(ha);
346 /* Wait for NVRAM to become ready. */
347 WRT_REG_WORD(®->nvram, NVR_SELECT);
348 RD_REG_WORD(®->nvram); /* PCI Posting. */
349 wait_cnt = NVR_WAIT_CNT;
352 DEBUG9_10(qla_printk(
353 "NVRAM didn't go ready...\n"));
357 word = RD_REG_WORD(®->nvram);
358 } while ((word & NVR_DATA_IN) == 0);
363 qla2x00_write_nvram_word(ha, ha->nvram_base, wprot_old);
369 qla2x00_set_nvram_protection(struct qla_hw_data *ha, int stat)
371 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
372 uint32_t word, wait_cnt;
374 if (stat != QLA_SUCCESS)
377 /* Set NVRAM write protection. */
379 qla2x00_nv_write(ha, NVR_DATA_OUT);
380 qla2x00_nv_write(ha, 0);
381 qla2x00_nv_write(ha, 0);
382 for (word = 0; word < 8; word++)
383 qla2x00_nv_write(ha, NVR_DATA_OUT);
385 qla2x00_nv_deselect(ha);
387 /* Enable protection register. */
388 qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT);
389 qla2x00_nv_write(ha, NVR_PR_ENABLE);
390 qla2x00_nv_write(ha, NVR_PR_ENABLE);
391 for (word = 0; word < 8; word++)
392 qla2x00_nv_write(ha, NVR_DATA_OUT | NVR_PR_ENABLE);
394 qla2x00_nv_deselect(ha);
396 /* Enable protection register. */
397 qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT);
398 qla2x00_nv_write(ha, NVR_PR_ENABLE);
399 qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT);
400 for (word = 0; word < 8; word++)
401 qla2x00_nv_write(ha, NVR_PR_ENABLE);
403 qla2x00_nv_deselect(ha);
405 /* Wait for NVRAM to become ready. */
406 WRT_REG_WORD(®->nvram, NVR_SELECT);
407 RD_REG_WORD(®->nvram); /* PCI Posting. */
408 wait_cnt = NVR_WAIT_CNT;
411 DEBUG9_10(qla_printk("NVRAM didn't go ready...\n"));
415 word = RD_REG_WORD(®->nvram);
416 } while ((word & NVR_DATA_IN) == 0);
420 /*****************************************************************************/
421 /* Flash Manipulation Routines */
422 /*****************************************************************************/
424 #define OPTROM_BURST_SIZE 0x1000
425 #define OPTROM_BURST_DWORDS (OPTROM_BURST_SIZE / 4)
427 static inline uint32_t
428 flash_conf_to_access_addr(uint32_t faddr)
430 return FARX_ACCESS_FLASH_CONF | faddr;
433 static inline uint32_t
434 flash_data_to_access_addr(uint32_t faddr)
436 return FARX_ACCESS_FLASH_DATA | faddr;
439 static inline uint32_t
440 nvram_conf_to_access_addr(uint32_t naddr)
442 return FARX_ACCESS_NVRAM_CONF | naddr;
445 static inline uint32_t
446 nvram_data_to_access_addr(uint32_t naddr)
448 return FARX_ACCESS_NVRAM_DATA | naddr;
452 qla24xx_read_flash_dword(struct qla_hw_data *ha, uint32_t addr)
456 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
458 WRT_REG_DWORD(®->flash_addr, addr & ~FARX_DATA_FLAG);
459 /* Wait for READ cycle to complete. */
462 (RD_REG_DWORD(®->flash_addr) & FARX_DATA_FLAG) == 0 &&
463 rval == QLA_SUCCESS; cnt--) {
467 rval = QLA_FUNCTION_TIMEOUT;
471 /* TODO: What happens if we time out? */
473 if (rval == QLA_SUCCESS)
474 data = RD_REG_DWORD(®->flash_data);
480 qla24xx_read_flash_data(scsi_qla_host_t *vha, uint32_t *dwptr, uint32_t faddr,
484 /* Dword reads to flash. */
485 for (i = 0; i < dwords; i++, faddr++)
486 dwptr[i] = cpu_to_le32(qla24xx_read_flash_dword(vha->hw,
487 flash_data_to_access_addr(faddr)));
493 qla24xx_write_flash_dword(struct qla_hw_data *ha, uint32_t addr, uint32_t data)
497 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
499 WRT_REG_DWORD(®->flash_data, data);
500 RD_REG_DWORD(®->flash_data); /* PCI Posting. */
501 WRT_REG_DWORD(®->flash_addr, addr | FARX_DATA_FLAG);
502 /* Wait for Write cycle to complete. */
504 for (cnt = 500000; (RD_REG_DWORD(®->flash_addr) & FARX_DATA_FLAG) &&
505 rval == QLA_SUCCESS; cnt--) {
509 rval = QLA_FUNCTION_TIMEOUT;
516 qla24xx_get_flash_manufacturer(struct qla_hw_data *ha, uint8_t *man_id,
521 ids = qla24xx_read_flash_dword(ha, flash_data_to_access_addr(0xd03ab));
523 *flash_id = MSB(ids);
525 /* Check if man_id and flash_id are valid. */
526 if (ids != 0xDEADDEAD && (*man_id == 0 || *flash_id == 0)) {
527 /* Read information using 0x9f opcode
528 * Device ID, Mfg ID would be read in the format:
529 * <Ext Dev Info><Device ID Part2><Device ID Part 1><Mfg ID>
530 * Example: ATMEL 0x00 01 45 1F
531 * Extract MFG and Dev ID from last two bytes.
533 ids = qla24xx_read_flash_dword(ha,
534 flash_data_to_access_addr(0xd009f));
536 *flash_id = MSB(ids);
541 qla2xxx_find_flt_start(scsi_qla_host_t *vha, uint32_t *start)
543 const char *loc, *locations[] = { "DEF", "PCI" };
544 uint32_t pcihdr, pcids;
546 uint8_t *buf, *bcode, last_image;
547 uint16_t cnt, chksum, *wptr;
548 struct qla_flt_location *fltl;
549 struct qla_hw_data *ha = vha->hw;
550 struct req_que *req = ha->req_q_map[0];
553 * FLT-location structure resides after the last PCI region.
556 /* Begin with sane defaults. */
558 *start = IS_QLA24XX_TYPE(ha) ? FA_FLASH_LAYOUT_ADDR_24:
559 FA_FLASH_LAYOUT_ADDR;
561 /* Begin with first PCI expansion ROM header. */
562 buf = (uint8_t *)req->ring;
563 dcode = (uint32_t *)req->ring;
567 /* Verify PCI expansion ROM header. */
568 qla24xx_read_flash_data(vha, dcode, pcihdr >> 2, 0x20);
569 bcode = buf + (pcihdr % 4);
570 if (bcode[0x0] != 0x55 || bcode[0x1] != 0xaa)
573 /* Locate PCI data structure. */
574 pcids = pcihdr + ((bcode[0x19] << 8) | bcode[0x18]);
575 qla24xx_read_flash_data(vha, dcode, pcids >> 2, 0x20);
576 bcode = buf + (pcihdr % 4);
578 /* Validate signature of PCI data structure. */
579 if (bcode[0x0] != 'P' || bcode[0x1] != 'C' ||
580 bcode[0x2] != 'I' || bcode[0x3] != 'R')
583 last_image = bcode[0x15] & BIT_7;
585 /* Locate next PCI expansion ROM. */
586 pcihdr += ((bcode[0x11] << 8) | bcode[0x10]) * 512;
587 } while (!last_image);
589 /* Now verify FLT-location structure. */
590 fltl = (struct qla_flt_location *)req->ring;
591 qla24xx_read_flash_data(vha, dcode, pcihdr >> 2,
592 sizeof(struct qla_flt_location) >> 2);
593 if (fltl->sig[0] != 'Q' || fltl->sig[1] != 'F' ||
594 fltl->sig[2] != 'L' || fltl->sig[3] != 'T')
597 wptr = (uint16_t *)req->ring;
598 cnt = sizeof(struct qla_flt_location) >> 1;
599 for (chksum = 0; cnt; cnt--)
600 chksum += le16_to_cpu(*wptr++);
602 qla_printk(KERN_ERR, ha,
603 "Inconsistent FLTL detected: checksum=0x%x.\n", chksum);
604 qla2x00_dump_buffer(buf, sizeof(struct qla_flt_location));
605 return QLA_FUNCTION_FAILED;
608 /* Good data. Use specified location. */
610 *start = le16_to_cpu(fltl->start_hi) << 16 |
611 le16_to_cpu(fltl->start_lo);
613 DEBUG2(qla_printk(KERN_DEBUG, ha, "FLTL[%s] = 0x%x.\n", loc, *start));
618 qla2xxx_get_flt_info(scsi_qla_host_t *vha, uint32_t flt_addr)
620 const char *loc, *locations[] = { "DEF", "FLT" };
622 uint16_t cnt, chksum;
624 struct qla_flt_header *flt;
625 struct qla_flt_region *region;
626 struct qla_hw_data *ha = vha->hw;
627 struct req_que *req = ha->req_q_map[0];
629 ha->flt_region_flt = flt_addr;
630 wptr = (uint16_t *)req->ring;
631 flt = (struct qla_flt_header *)req->ring;
632 region = (struct qla_flt_region *)&flt[1];
633 ha->isp_ops->read_optrom(vha, (uint8_t *)req->ring,
634 flt_addr << 2, OPTROM_BURST_SIZE);
635 if (*wptr == __constant_cpu_to_le16(0xffff))
637 if (flt->version != __constant_cpu_to_le16(1)) {
638 DEBUG2(qla_printk(KERN_INFO, ha, "Unsupported FLT detected: "
639 "version=0x%x length=0x%x checksum=0x%x.\n",
640 le16_to_cpu(flt->version), le16_to_cpu(flt->length),
641 le16_to_cpu(flt->checksum)));
645 cnt = (sizeof(struct qla_flt_header) + le16_to_cpu(flt->length)) >> 1;
646 for (chksum = 0; cnt; cnt--)
647 chksum += le16_to_cpu(*wptr++);
649 DEBUG2(qla_printk(KERN_INFO, ha, "Inconsistent FLT detected: "
650 "version=0x%x length=0x%x checksum=0x%x.\n",
651 le16_to_cpu(flt->version), le16_to_cpu(flt->length),
657 cnt = le16_to_cpu(flt->length) / sizeof(struct qla_flt_region);
658 for ( ; cnt; cnt--, region++) {
659 /* Store addresses as DWORD offsets. */
660 start = le32_to_cpu(region->start) >> 2;
662 DEBUG3(qla_printk(KERN_DEBUG, ha, "FLT[%02x]: start=0x%x "
663 "end=0x%x size=0x%x.\n", le32_to_cpu(region->code), start,
664 le32_to_cpu(region->end) >> 2, le32_to_cpu(region->size)));
666 switch (le32_to_cpu(region->code)) {
668 ha->flt_region_fw = start;
670 case FLT_REG_BOOT_CODE:
671 ha->flt_region_boot = start;
674 ha->flt_region_vpd_nvram = start;
677 ha->flt_region_fdt = start;
679 case FLT_REG_NPIV_CONF_0:
680 if (!PCI_FUNC(ha->pdev->devfn))
681 ha->flt_region_npiv_conf = start;
683 case FLT_REG_NPIV_CONF_1:
684 if (PCI_FUNC(ha->pdev->devfn))
685 ha->flt_region_npiv_conf = start;
692 /* Use hardcoded defaults. */
694 ha->flt_region_fw = FA_RISC_CODE_ADDR;
695 ha->flt_region_boot = FA_BOOT_CODE_ADDR;
696 ha->flt_region_vpd_nvram = FA_VPD_NVRAM_ADDR;
697 ha->flt_region_fdt = IS_QLA24XX_TYPE(ha) ? FA_FLASH_DESCR_ADDR_24:
699 ha->flt_region_npiv_conf = !PCI_FUNC(ha->pdev->devfn) ?
700 (IS_QLA24XX_TYPE(ha) ? FA_NPIV_CONF0_ADDR_24: FA_NPIV_CONF0_ADDR):
701 (IS_QLA24XX_TYPE(ha) ? FA_NPIV_CONF1_ADDR_24: FA_NPIV_CONF1_ADDR);
703 DEBUG2(qla_printk(KERN_DEBUG, ha, "FLT[%s]: boot=0x%x fw=0x%x "
704 "vpd_nvram=0x%x fdt=0x%x flt=0x%x npiv=0x%x.\n", loc,
705 ha->flt_region_boot, ha->flt_region_fw, ha->flt_region_vpd_nvram,
706 ha->flt_region_fdt, ha->flt_region_flt, ha->flt_region_npiv_conf));
710 qla2xxx_get_fdt_info(scsi_qla_host_t *vha)
712 #define FLASH_BLK_SIZE_4K 0x1000
713 #define FLASH_BLK_SIZE_32K 0x8000
714 #define FLASH_BLK_SIZE_64K 0x10000
715 const char *loc, *locations[] = { "MID", "FDT" };
716 uint16_t cnt, chksum;
718 struct qla_fdt_layout *fdt;
719 uint8_t man_id, flash_id;
721 struct qla_hw_data *ha = vha->hw;
722 struct req_que *req = ha->req_q_map[0];
724 wptr = (uint16_t *)req->ring;
725 fdt = (struct qla_fdt_layout *)req->ring;
726 ha->isp_ops->read_optrom(vha, (uint8_t *)req->ring,
727 ha->flt_region_fdt << 2, OPTROM_BURST_SIZE);
728 if (*wptr == __constant_cpu_to_le16(0xffff))
730 if (fdt->sig[0] != 'Q' || fdt->sig[1] != 'L' || fdt->sig[2] != 'I' ||
734 for (cnt = 0, chksum = 0; cnt < sizeof(struct qla_fdt_layout) >> 1;
736 chksum += le16_to_cpu(*wptr++);
738 DEBUG2(qla_printk(KERN_INFO, ha, "Inconsistent FDT detected: "
739 "checksum=0x%x id=%c version=0x%x.\n", chksum, fdt->sig[0],
740 le16_to_cpu(fdt->version)));
741 DEBUG9(qla2x00_dump_buffer((uint8_t *)fdt, sizeof(*fdt)));
746 mid = le16_to_cpu(fdt->man_id);
747 fid = le16_to_cpu(fdt->id);
748 ha->fdt_wrt_disable = fdt->wrt_disable_bits;
749 ha->fdt_erase_cmd = flash_conf_to_access_addr(0x0300 | fdt->erase_cmd);
750 ha->fdt_block_size = le32_to_cpu(fdt->block_size);
751 if (fdt->unprotect_sec_cmd) {
752 ha->fdt_unprotect_sec_cmd = flash_conf_to_access_addr(0x0300 |
753 fdt->unprotect_sec_cmd);
754 ha->fdt_protect_sec_cmd = fdt->protect_sec_cmd ?
755 flash_conf_to_access_addr(0x0300 | fdt->protect_sec_cmd):
756 flash_conf_to_access_addr(0x0336);
761 qla24xx_get_flash_manufacturer(ha, &man_id, &flash_id);
764 ha->fdt_wrt_disable = 0x9c;
765 ha->fdt_erase_cmd = flash_conf_to_access_addr(0x03d8);
767 case 0xbf: /* STT flash. */
768 if (flash_id == 0x8e)
769 ha->fdt_block_size = FLASH_BLK_SIZE_64K;
771 ha->fdt_block_size = FLASH_BLK_SIZE_32K;
773 if (flash_id == 0x80)
774 ha->fdt_erase_cmd = flash_conf_to_access_addr(0x0352);
776 case 0x13: /* ST M25P80. */
777 ha->fdt_block_size = FLASH_BLK_SIZE_64K;
779 case 0x1f: /* Atmel 26DF081A. */
780 ha->fdt_block_size = FLASH_BLK_SIZE_4K;
781 ha->fdt_erase_cmd = flash_conf_to_access_addr(0x0320);
782 ha->fdt_unprotect_sec_cmd = flash_conf_to_access_addr(0x0339);
783 ha->fdt_protect_sec_cmd = flash_conf_to_access_addr(0x0336);
786 /* Default to 64 kb sector size. */
787 ha->fdt_block_size = FLASH_BLK_SIZE_64K;
791 DEBUG2(qla_printk(KERN_DEBUG, ha, "FDT[%s]: (0x%x/0x%x) erase=0x%x "
792 "pro=%x upro=%x wrtd=0x%x blk=0x%x.\n", loc, mid, fid,
793 ha->fdt_erase_cmd, ha->fdt_protect_sec_cmd,
794 ha->fdt_unprotect_sec_cmd, ha->fdt_wrt_disable,
795 ha->fdt_block_size));
799 qla2xxx_get_flash_info(scsi_qla_host_t *vha)
803 struct qla_hw_data *ha = vha->hw;
805 if (!IS_QLA24XX_TYPE(ha) && !IS_QLA25XX(ha))
808 ret = qla2xxx_find_flt_start(vha, &flt_addr);
809 if (ret != QLA_SUCCESS)
812 qla2xxx_get_flt_info(vha, flt_addr);
813 qla2xxx_get_fdt_info(vha);
819 qla2xxx_flash_npiv_conf(scsi_qla_host_t *vha)
821 #define NPIV_CONFIG_SIZE (16*1024)
824 uint16_t cnt, chksum;
826 struct qla_npiv_header hdr;
827 struct qla_npiv_entry *entry;
828 struct qla_hw_data *ha = vha->hw;
830 if (!IS_QLA24XX_TYPE(ha) && !IS_QLA25XX(ha))
833 ha->isp_ops->read_optrom(vha, (uint8_t *)&hdr,
834 ha->flt_region_npiv_conf << 2, sizeof(struct qla_npiv_header));
835 if (hdr.version == __constant_cpu_to_le16(0xffff))
837 if (hdr.version != __constant_cpu_to_le16(1)) {
838 DEBUG2(qla_printk(KERN_INFO, ha, "Unsupported NPIV-Config "
839 "detected: version=0x%x entries=0x%x checksum=0x%x.\n",
840 le16_to_cpu(hdr.version), le16_to_cpu(hdr.entries),
841 le16_to_cpu(hdr.checksum)));
845 data = kmalloc(NPIV_CONFIG_SIZE, GFP_KERNEL);
847 DEBUG2(qla_printk(KERN_INFO, ha, "NPIV-Config: Unable to "
848 "allocate memory.\n"));
852 ha->isp_ops->read_optrom(vha, (uint8_t *)data,
853 ha->flt_region_npiv_conf << 2, NPIV_CONFIG_SIZE);
855 cnt = (sizeof(struct qla_npiv_header) + le16_to_cpu(hdr.entries) *
856 sizeof(struct qla_npiv_entry)) >> 1;
857 for (wptr = data, chksum = 0; cnt; cnt--)
858 chksum += le16_to_cpu(*wptr++);
860 DEBUG2(qla_printk(KERN_INFO, ha, "Inconsistent NPIV-Config "
861 "detected: version=0x%x entries=0x%x checksum=0x%x.\n",
862 le16_to_cpu(hdr.version), le16_to_cpu(hdr.entries),
867 entry = data + sizeof(struct qla_npiv_header);
868 cnt = le16_to_cpu(hdr.entries);
869 for (i = 0; cnt; cnt--, entry++, i++) {
871 struct fc_vport_identifiers vid;
872 struct fc_vport *vport;
874 flags = le16_to_cpu(entry->flags);
877 if ((flags & BIT_0) == 0)
880 memset(&vid, 0, sizeof(vid));
881 vid.roles = FC_PORT_ROLE_FCP_INITIATOR;
882 vid.vport_type = FC_PORTTYPE_NPIV;
884 vid.port_name = wwn_to_u64(entry->port_name);
885 vid.node_name = wwn_to_u64(entry->node_name);
887 memcpy(&ha->npiv_info[i], entry, sizeof(struct qla_npiv_entry));
889 DEBUG2(qla_printk(KERN_DEBUG, ha, "NPIV[%02x]: wwpn=%llx "
890 "wwnn=%llx vf_id=0x%x Q_qos=0x%x F_qos=0x%x.\n", cnt,
891 vid.port_name, vid.node_name, le16_to_cpu(entry->vf_id),
892 entry->q_qos, entry->f_qos));
894 if (i < QLA_PRECONFIG_VPORTS) {
895 vport = fc_vport_create(vha->host, 0, &vid);
897 qla_printk(KERN_INFO, ha,
898 "NPIV-Config: Failed to create vport [%02x]: "
899 "wwpn=%llx wwnn=%llx.\n", cnt,
900 vid.port_name, vid.node_name);
905 ha->npiv_info = NULL;
909 qla24xx_unprotect_flash(struct qla_hw_data *ha)
911 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
913 /* Enable flash write. */
914 WRT_REG_DWORD(®->ctrl_status,
915 RD_REG_DWORD(®->ctrl_status) | CSRX_FLASH_ENABLE);
916 RD_REG_DWORD(®->ctrl_status); /* PCI Posting. */
918 if (!ha->fdt_wrt_disable)
921 /* Disable flash write-protection. */
922 qla24xx_write_flash_dword(ha, flash_conf_to_access_addr(0x101), 0);
923 /* Some flash parts need an additional zero-write to clear bits.*/
924 qla24xx_write_flash_dword(ha, flash_conf_to_access_addr(0x101), 0);
928 qla24xx_protect_flash(struct qla_hw_data *ha)
931 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
933 if (!ha->fdt_wrt_disable)
934 goto skip_wrt_protect;
936 /* Enable flash write-protection and wait for completion. */
937 qla24xx_write_flash_dword(ha, flash_conf_to_access_addr(0x101),
938 ha->fdt_wrt_disable);
939 for (cnt = 300; cnt &&
940 qla24xx_read_flash_dword(ha,
941 flash_conf_to_access_addr(0x005)) & BIT_0;
947 /* Disable flash write. */
948 WRT_REG_DWORD(®->ctrl_status,
949 RD_REG_DWORD(®->ctrl_status) & ~CSRX_FLASH_ENABLE);
950 RD_REG_DWORD(®->ctrl_status); /* PCI Posting. */
954 qla24xx_write_flash_data(scsi_qla_host_t *vha, uint32_t *dwptr, uint32_t faddr,
958 uint32_t liter, miter;
959 uint32_t sec_mask, rest_addr;
960 uint32_t fdata, findex;
961 dma_addr_t optrom_dma;
964 struct qla_hw_data *ha = vha->hw;
968 /* Prepare burst-capable write on supported ISPs. */
969 if (IS_QLA25XX(ha) && !(faddr & 0xfff) &&
970 dwords > OPTROM_BURST_DWORDS) {
971 optrom = dma_alloc_coherent(&ha->pdev->dev, OPTROM_BURST_SIZE,
972 &optrom_dma, GFP_KERNEL);
974 qla_printk(KERN_DEBUG, ha,
975 "Unable to allocate memory for optrom burst write "
976 "(%x KB).\n", OPTROM_BURST_SIZE / 1024);
980 rest_addr = (ha->fdt_block_size >> 2) - 1;
981 sec_mask = 0x80000 - (ha->fdt_block_size >> 2);
983 qla24xx_unprotect_flash(ha);
985 for (liter = 0; liter < dwords; liter++, faddr++, dwptr++) {
988 fdata = (findex & sec_mask) << 2;
990 /* Are we at the beginning of a sector? */
991 if ((findex & rest_addr) == 0) {
992 /* Do sector unprotect. */
993 if (ha->fdt_unprotect_sec_cmd)
994 qla24xx_write_flash_dword(ha,
995 ha->fdt_unprotect_sec_cmd,
996 (fdata & 0xff00) | ((fdata << 16) &
997 0xff0000) | ((fdata >> 16) & 0xff));
998 ret = qla24xx_write_flash_dword(ha, ha->fdt_erase_cmd,
999 (fdata & 0xff00) |((fdata << 16) &
1000 0xff0000) | ((fdata >> 16) & 0xff));
1001 if (ret != QLA_SUCCESS) {
1002 DEBUG9(qla_printk("Unable to flash sector: "
1003 "address=%x.\n", faddr));
1008 /* Go with burst-write. */
1009 if (optrom && (liter + OPTROM_BURST_DWORDS) <= dwords) {
1010 /* Copy data to DMA'ble buffer. */
1011 for (miter = 0, s = optrom, d = dwptr;
1012 miter < OPTROM_BURST_DWORDS; miter++, s++, d++)
1013 *s = cpu_to_le32(*d);
1015 ret = qla2x00_load_ram(vha, optrom_dma,
1016 flash_data_to_access_addr(faddr),
1017 OPTROM_BURST_DWORDS);
1018 if (ret != QLA_SUCCESS) {
1019 qla_printk(KERN_WARNING, ha,
1020 "Unable to burst-write optrom segment "
1021 "(%x/%x/%llx).\n", ret,
1022 flash_data_to_access_addr(faddr),
1023 (unsigned long long)optrom_dma);
1024 qla_printk(KERN_WARNING, ha,
1025 "Reverting to slow-write.\n");
1027 dma_free_coherent(&ha->pdev->dev,
1028 OPTROM_BURST_SIZE, optrom, optrom_dma);
1031 liter += OPTROM_BURST_DWORDS - 1;
1032 faddr += OPTROM_BURST_DWORDS - 1;
1033 dwptr += OPTROM_BURST_DWORDS - 1;
1038 ret = qla24xx_write_flash_dword(ha,
1039 flash_data_to_access_addr(faddr), cpu_to_le32(*dwptr));
1040 if (ret != QLA_SUCCESS) {
1041 DEBUG9(printk("%s(%ld) Unable to program flash "
1042 "address=%x data=%x.\n", __func__,
1043 vha->host_no, faddr, *dwptr));
1047 /* Do sector protect. */
1048 if (ha->fdt_unprotect_sec_cmd &&
1049 ((faddr & rest_addr) == rest_addr))
1050 qla24xx_write_flash_dword(ha,
1051 ha->fdt_protect_sec_cmd,
1052 (fdata & 0xff00) | ((fdata << 16) &
1053 0xff0000) | ((fdata >> 16) & 0xff));
1056 qla24xx_protect_flash(ha);
1059 dma_free_coherent(&ha->pdev->dev,
1060 OPTROM_BURST_SIZE, optrom, optrom_dma);
1066 qla2x00_read_nvram_data(scsi_qla_host_t *vha, uint8_t *buf, uint32_t naddr,
1071 struct qla_hw_data *ha = vha->hw;
1073 /* Word reads to NVRAM via registers. */
1074 wptr = (uint16_t *)buf;
1075 qla2x00_lock_nvram_access(ha);
1076 for (i = 0; i < bytes >> 1; i++, naddr++)
1077 wptr[i] = cpu_to_le16(qla2x00_get_nvram_word(ha,
1079 qla2x00_unlock_nvram_access(ha);
1085 qla24xx_read_nvram_data(scsi_qla_host_t *vha, uint8_t *buf, uint32_t naddr,
1091 /* Dword reads to flash. */
1092 dwptr = (uint32_t *)buf;
1093 for (i = 0; i < bytes >> 2; i++, naddr++)
1094 dwptr[i] = cpu_to_le32(qla24xx_read_flash_dword(vha->hw,
1095 nvram_data_to_access_addr(naddr)));
1101 qla2x00_write_nvram_data(scsi_qla_host_t *vha, uint8_t *buf, uint32_t naddr,
1107 unsigned long flags;
1108 struct qla_hw_data *ha = vha->hw;
1112 spin_lock_irqsave(&ha->hardware_lock, flags);
1113 qla2x00_lock_nvram_access(ha);
1115 /* Disable NVRAM write-protection. */
1116 stat = qla2x00_clear_nvram_protection(ha);
1118 wptr = (uint16_t *)buf;
1119 for (i = 0; i < bytes >> 1; i++, naddr++) {
1120 qla2x00_write_nvram_word(ha, naddr,
1121 cpu_to_le16(*wptr));
1125 /* Enable NVRAM write-protection. */
1126 qla2x00_set_nvram_protection(ha, stat);
1128 qla2x00_unlock_nvram_access(ha);
1129 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1135 qla24xx_write_nvram_data(scsi_qla_host_t *vha, uint8_t *buf, uint32_t naddr,
1141 struct qla_hw_data *ha = vha->hw;
1142 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1146 /* Enable flash write. */
1147 WRT_REG_DWORD(®->ctrl_status,
1148 RD_REG_DWORD(®->ctrl_status) | CSRX_FLASH_ENABLE);
1149 RD_REG_DWORD(®->ctrl_status); /* PCI Posting. */
1151 /* Disable NVRAM write-protection. */
1152 qla24xx_write_flash_dword(ha, nvram_conf_to_access_addr(0x101),
1154 qla24xx_write_flash_dword(ha, nvram_conf_to_access_addr(0x101),
1157 /* Dword writes to flash. */
1158 dwptr = (uint32_t *)buf;
1159 for (i = 0; i < bytes >> 2; i++, naddr++, dwptr++) {
1160 ret = qla24xx_write_flash_dword(ha,
1161 nvram_data_to_access_addr(naddr),
1162 cpu_to_le32(*dwptr));
1163 if (ret != QLA_SUCCESS) {
1164 DEBUG9(qla_printk("Unable to program nvram address=%x "
1165 "data=%x.\n", naddr, *dwptr));
1170 /* Enable NVRAM write-protection. */
1171 qla24xx_write_flash_dword(ha, nvram_conf_to_access_addr(0x101),
1174 /* Disable flash write. */
1175 WRT_REG_DWORD(®->ctrl_status,
1176 RD_REG_DWORD(®->ctrl_status) & ~CSRX_FLASH_ENABLE);
1177 RD_REG_DWORD(®->ctrl_status); /* PCI Posting. */
1183 qla25xx_read_nvram_data(scsi_qla_host_t *vha, uint8_t *buf, uint32_t naddr,
1188 struct qla_hw_data *ha = vha->hw;
1190 /* Dword reads to flash. */
1191 dwptr = (uint32_t *)buf;
1192 for (i = 0; i < bytes >> 2; i++, naddr++)
1193 dwptr[i] = cpu_to_le32(qla24xx_read_flash_dword(ha,
1194 flash_data_to_access_addr(ha->flt_region_vpd_nvram |
1201 qla25xx_write_nvram_data(scsi_qla_host_t *vha, uint8_t *buf, uint32_t naddr,
1204 struct qla_hw_data *ha = vha->hw;
1205 #define RMW_BUFFER_SIZE (64 * 1024)
1208 dbuf = vmalloc(RMW_BUFFER_SIZE);
1210 return QLA_MEMORY_ALLOC_FAILED;
1211 ha->isp_ops->read_optrom(vha, dbuf, ha->flt_region_vpd_nvram << 2,
1213 memcpy(dbuf + (naddr << 2), buf, bytes);
1214 ha->isp_ops->write_optrom(vha, dbuf, ha->flt_region_vpd_nvram << 2,
1222 qla2x00_flip_colors(struct qla_hw_data *ha, uint16_t *pflags)
1224 if (IS_QLA2322(ha)) {
1225 /* Flip all colors. */
1226 if (ha->beacon_color_state == QLA_LED_ALL_ON) {
1228 ha->beacon_color_state = 0;
1229 *pflags = GPIO_LED_ALL_OFF;
1232 ha->beacon_color_state = QLA_LED_ALL_ON;
1233 *pflags = GPIO_LED_RGA_ON;
1236 /* Flip green led only. */
1237 if (ha->beacon_color_state == QLA_LED_GRN_ON) {
1239 ha->beacon_color_state = 0;
1240 *pflags = GPIO_LED_GREEN_OFF_AMBER_OFF;
1243 ha->beacon_color_state = QLA_LED_GRN_ON;
1244 *pflags = GPIO_LED_GREEN_ON_AMBER_OFF;
1249 #define PIO_REG(h, r) ((h)->pio_address + offsetof(struct device_reg_2xxx, r))
1252 qla2x00_beacon_blink(struct scsi_qla_host *vha)
1254 uint16_t gpio_enable;
1256 uint16_t led_color = 0;
1257 unsigned long flags;
1258 struct qla_hw_data *ha = vha->hw;
1259 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1261 spin_lock_irqsave(&ha->hardware_lock, flags);
1263 /* Save the Original GPIOE. */
1264 if (ha->pio_address) {
1265 gpio_enable = RD_REG_WORD_PIO(PIO_REG(ha, gpioe));
1266 gpio_data = RD_REG_WORD_PIO(PIO_REG(ha, gpiod));
1268 gpio_enable = RD_REG_WORD(®->gpioe);
1269 gpio_data = RD_REG_WORD(®->gpiod);
1272 /* Set the modified gpio_enable values */
1273 gpio_enable |= GPIO_LED_MASK;
1275 if (ha->pio_address) {
1276 WRT_REG_WORD_PIO(PIO_REG(ha, gpioe), gpio_enable);
1278 WRT_REG_WORD(®->gpioe, gpio_enable);
1279 RD_REG_WORD(®->gpioe);
1282 qla2x00_flip_colors(ha, &led_color);
1284 /* Clear out any previously set LED color. */
1285 gpio_data &= ~GPIO_LED_MASK;
1287 /* Set the new input LED color to GPIOD. */
1288 gpio_data |= led_color;
1290 /* Set the modified gpio_data values */
1291 if (ha->pio_address) {
1292 WRT_REG_WORD_PIO(PIO_REG(ha, gpiod), gpio_data);
1294 WRT_REG_WORD(®->gpiod, gpio_data);
1295 RD_REG_WORD(®->gpiod);
1298 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1302 qla2x00_beacon_on(struct scsi_qla_host *vha)
1304 uint16_t gpio_enable;
1306 unsigned long flags;
1307 struct qla_hw_data *ha = vha->hw;
1308 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1310 ha->fw_options[1] &= ~FO1_SET_EMPHASIS_SWING;
1311 ha->fw_options[1] |= FO1_DISABLE_GPIO6_7;
1313 if (qla2x00_set_fw_options(vha, ha->fw_options) != QLA_SUCCESS) {
1314 qla_printk(KERN_WARNING, ha,
1315 "Unable to update fw options (beacon on).\n");
1316 return QLA_FUNCTION_FAILED;
1319 /* Turn off LEDs. */
1320 spin_lock_irqsave(&ha->hardware_lock, flags);
1321 if (ha->pio_address) {
1322 gpio_enable = RD_REG_WORD_PIO(PIO_REG(ha, gpioe));
1323 gpio_data = RD_REG_WORD_PIO(PIO_REG(ha, gpiod));
1325 gpio_enable = RD_REG_WORD(®->gpioe);
1326 gpio_data = RD_REG_WORD(®->gpiod);
1328 gpio_enable |= GPIO_LED_MASK;
1330 /* Set the modified gpio_enable values. */
1331 if (ha->pio_address) {
1332 WRT_REG_WORD_PIO(PIO_REG(ha, gpioe), gpio_enable);
1334 WRT_REG_WORD(®->gpioe, gpio_enable);
1335 RD_REG_WORD(®->gpioe);
1338 /* Clear out previously set LED colour. */
1339 gpio_data &= ~GPIO_LED_MASK;
1340 if (ha->pio_address) {
1341 WRT_REG_WORD_PIO(PIO_REG(ha, gpiod), gpio_data);
1343 WRT_REG_WORD(®->gpiod, gpio_data);
1344 RD_REG_WORD(®->gpiod);
1346 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1349 * Let the per HBA timer kick off the blinking process based on
1350 * the following flags. No need to do anything else now.
1352 ha->beacon_blink_led = 1;
1353 ha->beacon_color_state = 0;
1359 qla2x00_beacon_off(struct scsi_qla_host *vha)
1361 int rval = QLA_SUCCESS;
1362 struct qla_hw_data *ha = vha->hw;
1364 ha->beacon_blink_led = 0;
1366 /* Set the on flag so when it gets flipped it will be off. */
1368 ha->beacon_color_state = QLA_LED_ALL_ON;
1370 ha->beacon_color_state = QLA_LED_GRN_ON;
1372 ha->isp_ops->beacon_blink(vha); /* This turns green LED off */
1374 ha->fw_options[1] &= ~FO1_SET_EMPHASIS_SWING;
1375 ha->fw_options[1] &= ~FO1_DISABLE_GPIO6_7;
1377 rval = qla2x00_set_fw_options(vha, ha->fw_options);
1378 if (rval != QLA_SUCCESS)
1379 qla_printk(KERN_WARNING, ha,
1380 "Unable to update fw options (beacon off).\n");
1386 qla24xx_flip_colors(struct qla_hw_data *ha, uint16_t *pflags)
1388 /* Flip all colors. */
1389 if (ha->beacon_color_state == QLA_LED_ALL_ON) {
1391 ha->beacon_color_state = 0;
1395 ha->beacon_color_state = QLA_LED_ALL_ON;
1396 *pflags = GPDX_LED_YELLOW_ON | GPDX_LED_AMBER_ON;
1401 qla24xx_beacon_blink(struct scsi_qla_host *vha)
1403 uint16_t led_color = 0;
1405 unsigned long flags;
1406 struct qla_hw_data *ha = vha->hw;
1407 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1409 /* Save the Original GPIOD. */
1410 spin_lock_irqsave(&ha->hardware_lock, flags);
1411 gpio_data = RD_REG_DWORD(®->gpiod);
1413 /* Enable the gpio_data reg for update. */
1414 gpio_data |= GPDX_LED_UPDATE_MASK;
1416 WRT_REG_DWORD(®->gpiod, gpio_data);
1417 gpio_data = RD_REG_DWORD(®->gpiod);
1419 /* Set the color bits. */
1420 qla24xx_flip_colors(ha, &led_color);
1422 /* Clear out any previously set LED color. */
1423 gpio_data &= ~GPDX_LED_COLOR_MASK;
1425 /* Set the new input LED color to GPIOD. */
1426 gpio_data |= led_color;
1428 /* Set the modified gpio_data values. */
1429 WRT_REG_DWORD(®->gpiod, gpio_data);
1430 gpio_data = RD_REG_DWORD(®->gpiod);
1431 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1435 qla24xx_beacon_on(struct scsi_qla_host *vha)
1438 unsigned long flags;
1439 struct qla_hw_data *ha = vha->hw;
1440 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1442 if (ha->beacon_blink_led == 0) {
1443 /* Enable firmware for update */
1444 ha->fw_options[1] |= ADD_FO1_DISABLE_GPIO_LED_CTRL;
1446 if (qla2x00_set_fw_options(vha, ha->fw_options) != QLA_SUCCESS)
1447 return QLA_FUNCTION_FAILED;
1449 if (qla2x00_get_fw_options(vha, ha->fw_options) !=
1451 qla_printk(KERN_WARNING, ha,
1452 "Unable to update fw options (beacon on).\n");
1453 return QLA_FUNCTION_FAILED;
1456 spin_lock_irqsave(&ha->hardware_lock, flags);
1457 gpio_data = RD_REG_DWORD(®->gpiod);
1459 /* Enable the gpio_data reg for update. */
1460 gpio_data |= GPDX_LED_UPDATE_MASK;
1461 WRT_REG_DWORD(®->gpiod, gpio_data);
1462 RD_REG_DWORD(®->gpiod);
1464 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1467 /* So all colors blink together. */
1468 ha->beacon_color_state = 0;
1470 /* Let the per HBA timer kick off the blinking process. */
1471 ha->beacon_blink_led = 1;
1477 qla24xx_beacon_off(struct scsi_qla_host *vha)
1480 unsigned long flags;
1481 struct qla_hw_data *ha = vha->hw;
1482 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1484 ha->beacon_blink_led = 0;
1485 ha->beacon_color_state = QLA_LED_ALL_ON;
1487 ha->isp_ops->beacon_blink(vha); /* Will flip to all off. */
1489 /* Give control back to firmware. */
1490 spin_lock_irqsave(&ha->hardware_lock, flags);
1491 gpio_data = RD_REG_DWORD(®->gpiod);
1493 /* Disable the gpio_data reg for update. */
1494 gpio_data &= ~GPDX_LED_UPDATE_MASK;
1495 WRT_REG_DWORD(®->gpiod, gpio_data);
1496 RD_REG_DWORD(®->gpiod);
1497 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1499 ha->fw_options[1] &= ~ADD_FO1_DISABLE_GPIO_LED_CTRL;
1501 if (qla2x00_set_fw_options(vha, ha->fw_options) != QLA_SUCCESS) {
1502 qla_printk(KERN_WARNING, ha,
1503 "Unable to update fw options (beacon off).\n");
1504 return QLA_FUNCTION_FAILED;
1507 if (qla2x00_get_fw_options(vha, ha->fw_options) != QLA_SUCCESS) {
1508 qla_printk(KERN_WARNING, ha,
1509 "Unable to get fw options (beacon off).\n");
1510 return QLA_FUNCTION_FAILED;
1518 * Flash support routines
1522 * qla2x00_flash_enable() - Setup flash for reading and writing.
1526 qla2x00_flash_enable(struct qla_hw_data *ha)
1529 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1531 data = RD_REG_WORD(®->ctrl_status);
1532 data |= CSR_FLASH_ENABLE;
1533 WRT_REG_WORD(®->ctrl_status, data);
1534 RD_REG_WORD(®->ctrl_status); /* PCI Posting. */
1538 * qla2x00_flash_disable() - Disable flash and allow RISC to run.
1542 qla2x00_flash_disable(struct qla_hw_data *ha)
1545 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1547 data = RD_REG_WORD(®->ctrl_status);
1548 data &= ~(CSR_FLASH_ENABLE);
1549 WRT_REG_WORD(®->ctrl_status, data);
1550 RD_REG_WORD(®->ctrl_status); /* PCI Posting. */
1554 * qla2x00_read_flash_byte() - Reads a byte from flash
1556 * @addr: Address in flash to read
1558 * A word is read from the chip, but, only the lower byte is valid.
1560 * Returns the byte read from flash @addr.
1563 qla2x00_read_flash_byte(struct qla_hw_data *ha, uint32_t addr)
1566 uint16_t bank_select;
1567 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1569 bank_select = RD_REG_WORD(®->ctrl_status);
1571 if (IS_QLA2322(ha) || IS_QLA6322(ha)) {
1572 /* Specify 64K address range: */
1573 /* clear out Module Select and Flash Address bits [19:16]. */
1574 bank_select &= ~0xf8;
1575 bank_select |= addr >> 12 & 0xf0;
1576 bank_select |= CSR_FLASH_64K_BANK;
1577 WRT_REG_WORD(®->ctrl_status, bank_select);
1578 RD_REG_WORD(®->ctrl_status); /* PCI Posting. */
1580 WRT_REG_WORD(®->flash_address, (uint16_t)addr);
1581 data = RD_REG_WORD(®->flash_data);
1583 return (uint8_t)data;
1586 /* Setup bit 16 of flash address. */
1587 if ((addr & BIT_16) && ((bank_select & CSR_FLASH_64K_BANK) == 0)) {
1588 bank_select |= CSR_FLASH_64K_BANK;
1589 WRT_REG_WORD(®->ctrl_status, bank_select);
1590 RD_REG_WORD(®->ctrl_status); /* PCI Posting. */
1591 } else if (((addr & BIT_16) == 0) &&
1592 (bank_select & CSR_FLASH_64K_BANK)) {
1593 bank_select &= ~(CSR_FLASH_64K_BANK);
1594 WRT_REG_WORD(®->ctrl_status, bank_select);
1595 RD_REG_WORD(®->ctrl_status); /* PCI Posting. */
1598 /* Always perform IO mapped accesses to the FLASH registers. */
1599 if (ha->pio_address) {
1602 WRT_REG_WORD_PIO(PIO_REG(ha, flash_address), (uint16_t)addr);
1604 data = RD_REG_WORD_PIO(PIO_REG(ha, flash_data));
1607 data2 = RD_REG_WORD_PIO(PIO_REG(ha, flash_data));
1608 } while (data != data2);
1610 WRT_REG_WORD(®->flash_address, (uint16_t)addr);
1611 data = qla2x00_debounce_register(®->flash_data);
1614 return (uint8_t)data;
1618 * qla2x00_write_flash_byte() - Write a byte to flash
1620 * @addr: Address in flash to write
1621 * @data: Data to write
1624 qla2x00_write_flash_byte(struct qla_hw_data *ha, uint32_t addr, uint8_t data)
1626 uint16_t bank_select;
1627 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1629 bank_select = RD_REG_WORD(®->ctrl_status);
1630 if (IS_QLA2322(ha) || IS_QLA6322(ha)) {
1631 /* Specify 64K address range: */
1632 /* clear out Module Select and Flash Address bits [19:16]. */
1633 bank_select &= ~0xf8;
1634 bank_select |= addr >> 12 & 0xf0;
1635 bank_select |= CSR_FLASH_64K_BANK;
1636 WRT_REG_WORD(®->ctrl_status, bank_select);
1637 RD_REG_WORD(®->ctrl_status); /* PCI Posting. */
1639 WRT_REG_WORD(®->flash_address, (uint16_t)addr);
1640 RD_REG_WORD(®->ctrl_status); /* PCI Posting. */
1641 WRT_REG_WORD(®->flash_data, (uint16_t)data);
1642 RD_REG_WORD(®->ctrl_status); /* PCI Posting. */
1647 /* Setup bit 16 of flash address. */
1648 if ((addr & BIT_16) && ((bank_select & CSR_FLASH_64K_BANK) == 0)) {
1649 bank_select |= CSR_FLASH_64K_BANK;
1650 WRT_REG_WORD(®->ctrl_status, bank_select);
1651 RD_REG_WORD(®->ctrl_status); /* PCI Posting. */
1652 } else if (((addr & BIT_16) == 0) &&
1653 (bank_select & CSR_FLASH_64K_BANK)) {
1654 bank_select &= ~(CSR_FLASH_64K_BANK);
1655 WRT_REG_WORD(®->ctrl_status, bank_select);
1656 RD_REG_WORD(®->ctrl_status); /* PCI Posting. */
1659 /* Always perform IO mapped accesses to the FLASH registers. */
1660 if (ha->pio_address) {
1661 WRT_REG_WORD_PIO(PIO_REG(ha, flash_address), (uint16_t)addr);
1662 WRT_REG_WORD_PIO(PIO_REG(ha, flash_data), (uint16_t)data);
1664 WRT_REG_WORD(®->flash_address, (uint16_t)addr);
1665 RD_REG_WORD(®->ctrl_status); /* PCI Posting. */
1666 WRT_REG_WORD(®->flash_data, (uint16_t)data);
1667 RD_REG_WORD(®->ctrl_status); /* PCI Posting. */
1672 * qla2x00_poll_flash() - Polls flash for completion.
1674 * @addr: Address in flash to poll
1675 * @poll_data: Data to be polled
1676 * @man_id: Flash manufacturer ID
1677 * @flash_id: Flash ID
1679 * This function polls the device until bit 7 of what is read matches data
1680 * bit 7 or until data bit 5 becomes a 1. If that hapens, the flash ROM timed
1681 * out (a fatal error). The flash book recommeds reading bit 7 again after
1682 * reading bit 5 as a 1.
1684 * Returns 0 on success, else non-zero.
1687 qla2x00_poll_flash(struct qla_hw_data *ha, uint32_t addr, uint8_t poll_data,
1688 uint8_t man_id, uint8_t flash_id)
1696 /* Wait for 30 seconds for command to finish. */
1698 for (cnt = 3000000; cnt; cnt--) {
1699 flash_data = qla2x00_read_flash_byte(ha, addr);
1700 if ((flash_data & BIT_7) == poll_data) {
1705 if (man_id != 0x40 && man_id != 0xda) {
1706 if ((flash_data & BIT_5) && cnt > 2)
1717 * qla2x00_program_flash_address() - Programs a flash address
1719 * @addr: Address in flash to program
1720 * @data: Data to be written in flash
1721 * @man_id: Flash manufacturer ID
1722 * @flash_id: Flash ID
1724 * Returns 0 on success, else non-zero.
1727 qla2x00_program_flash_address(struct qla_hw_data *ha, uint32_t addr,
1728 uint8_t data, uint8_t man_id, uint8_t flash_id)
1730 /* Write Program Command Sequence. */
1731 if (IS_OEM_001(ha)) {
1732 qla2x00_write_flash_byte(ha, 0xaaa, 0xaa);
1733 qla2x00_write_flash_byte(ha, 0x555, 0x55);
1734 qla2x00_write_flash_byte(ha, 0xaaa, 0xa0);
1735 qla2x00_write_flash_byte(ha, addr, data);
1737 if (man_id == 0xda && flash_id == 0xc1) {
1738 qla2x00_write_flash_byte(ha, addr, data);
1742 qla2x00_write_flash_byte(ha, 0x5555, 0xaa);
1743 qla2x00_write_flash_byte(ha, 0x2aaa, 0x55);
1744 qla2x00_write_flash_byte(ha, 0x5555, 0xa0);
1745 qla2x00_write_flash_byte(ha, addr, data);
1751 /* Wait for write to complete. */
1752 return qla2x00_poll_flash(ha, addr, data, man_id, flash_id);
1756 * qla2x00_erase_flash() - Erase the flash.
1758 * @man_id: Flash manufacturer ID
1759 * @flash_id: Flash ID
1761 * Returns 0 on success, else non-zero.
1764 qla2x00_erase_flash(struct qla_hw_data *ha, uint8_t man_id, uint8_t flash_id)
1766 /* Individual Sector Erase Command Sequence */
1767 if (IS_OEM_001(ha)) {
1768 qla2x00_write_flash_byte(ha, 0xaaa, 0xaa);
1769 qla2x00_write_flash_byte(ha, 0x555, 0x55);
1770 qla2x00_write_flash_byte(ha, 0xaaa, 0x80);
1771 qla2x00_write_flash_byte(ha, 0xaaa, 0xaa);
1772 qla2x00_write_flash_byte(ha, 0x555, 0x55);
1773 qla2x00_write_flash_byte(ha, 0xaaa, 0x10);
1775 qla2x00_write_flash_byte(ha, 0x5555, 0xaa);
1776 qla2x00_write_flash_byte(ha, 0x2aaa, 0x55);
1777 qla2x00_write_flash_byte(ha, 0x5555, 0x80);
1778 qla2x00_write_flash_byte(ha, 0x5555, 0xaa);
1779 qla2x00_write_flash_byte(ha, 0x2aaa, 0x55);
1780 qla2x00_write_flash_byte(ha, 0x5555, 0x10);
1785 /* Wait for erase to complete. */
1786 return qla2x00_poll_flash(ha, 0x00, 0x80, man_id, flash_id);
1790 * qla2x00_erase_flash_sector() - Erase a flash sector.
1792 * @addr: Flash sector to erase
1793 * @sec_mask: Sector address mask
1794 * @man_id: Flash manufacturer ID
1795 * @flash_id: Flash ID
1797 * Returns 0 on success, else non-zero.
1800 qla2x00_erase_flash_sector(struct qla_hw_data *ha, uint32_t addr,
1801 uint32_t sec_mask, uint8_t man_id, uint8_t flash_id)
1803 /* Individual Sector Erase Command Sequence */
1804 qla2x00_write_flash_byte(ha, 0x5555, 0xaa);
1805 qla2x00_write_flash_byte(ha, 0x2aaa, 0x55);
1806 qla2x00_write_flash_byte(ha, 0x5555, 0x80);
1807 qla2x00_write_flash_byte(ha, 0x5555, 0xaa);
1808 qla2x00_write_flash_byte(ha, 0x2aaa, 0x55);
1809 if (man_id == 0x1f && flash_id == 0x13)
1810 qla2x00_write_flash_byte(ha, addr & sec_mask, 0x10);
1812 qla2x00_write_flash_byte(ha, addr & sec_mask, 0x30);
1816 /* Wait for erase to complete. */
1817 return qla2x00_poll_flash(ha, addr, 0x80, man_id, flash_id);
1821 * qla2x00_get_flash_manufacturer() - Read manufacturer ID from flash chip.
1822 * @man_id: Flash manufacturer ID
1823 * @flash_id: Flash ID
1826 qla2x00_get_flash_manufacturer(struct qla_hw_data *ha, uint8_t *man_id,
1829 qla2x00_write_flash_byte(ha, 0x5555, 0xaa);
1830 qla2x00_write_flash_byte(ha, 0x2aaa, 0x55);
1831 qla2x00_write_flash_byte(ha, 0x5555, 0x90);
1832 *man_id = qla2x00_read_flash_byte(ha, 0x0000);
1833 *flash_id = qla2x00_read_flash_byte(ha, 0x0001);
1834 qla2x00_write_flash_byte(ha, 0x5555, 0xaa);
1835 qla2x00_write_flash_byte(ha, 0x2aaa, 0x55);
1836 qla2x00_write_flash_byte(ha, 0x5555, 0xf0);
1840 qla2x00_read_flash_data(struct qla_hw_data *ha, uint8_t *tmp_buf,
1841 uint32_t saddr, uint32_t length)
1843 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1844 uint32_t midpoint, ilength;
1847 midpoint = length / 2;
1849 WRT_REG_WORD(®->nvram, 0);
1850 RD_REG_WORD(®->nvram);
1851 for (ilength = 0; ilength < length; saddr++, ilength++, tmp_buf++) {
1852 if (ilength == midpoint) {
1853 WRT_REG_WORD(®->nvram, NVR_SELECT);
1854 RD_REG_WORD(®->nvram);
1856 data = qla2x00_read_flash_byte(ha, saddr);
1865 qla2x00_suspend_hba(struct scsi_qla_host *vha)
1868 unsigned long flags;
1869 struct qla_hw_data *ha = vha->hw;
1870 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1873 scsi_block_requests(vha->host);
1874 ha->isp_ops->disable_intrs(ha);
1875 set_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags);
1878 spin_lock_irqsave(&ha->hardware_lock, flags);
1879 WRT_REG_WORD(®->hccr, HCCR_PAUSE_RISC);
1880 RD_REG_WORD(®->hccr);
1881 if (IS_QLA2100(ha) || IS_QLA2200(ha) || IS_QLA2300(ha)) {
1882 for (cnt = 0; cnt < 30000; cnt++) {
1883 if ((RD_REG_WORD(®->hccr) & HCCR_RISC_PAUSE) != 0)
1890 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1894 qla2x00_resume_hba(struct scsi_qla_host *vha)
1896 struct qla_hw_data *ha = vha->hw;
1899 clear_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags);
1900 set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
1901 qla2xxx_wake_dpc(vha);
1902 qla2x00_wait_for_hba_online(vha);
1903 scsi_unblock_requests(vha->host);
1907 qla2x00_read_optrom_data(struct scsi_qla_host *vha, uint8_t *buf,
1908 uint32_t offset, uint32_t length)
1910 uint32_t addr, midpoint;
1912 struct qla_hw_data *ha = vha->hw;
1913 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1916 qla2x00_suspend_hba(vha);
1919 midpoint = ha->optrom_size / 2;
1921 qla2x00_flash_enable(ha);
1922 WRT_REG_WORD(®->nvram, 0);
1923 RD_REG_WORD(®->nvram); /* PCI Posting. */
1924 for (addr = offset, data = buf; addr < length; addr++, data++) {
1925 if (addr == midpoint) {
1926 WRT_REG_WORD(®->nvram, NVR_SELECT);
1927 RD_REG_WORD(®->nvram); /* PCI Posting. */
1930 *data = qla2x00_read_flash_byte(ha, addr);
1932 qla2x00_flash_disable(ha);
1935 qla2x00_resume_hba(vha);
1941 qla2x00_write_optrom_data(struct scsi_qla_host *vha, uint8_t *buf,
1942 uint32_t offset, uint32_t length)
1946 uint8_t man_id, flash_id, sec_number, data;
1948 uint32_t addr, liter, sec_mask, rest_addr;
1949 struct qla_hw_data *ha = vha->hw;
1950 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1953 qla2x00_suspend_hba(vha);
1958 /* Reset ISP chip. */
1959 WRT_REG_WORD(®->ctrl_status, CSR_ISP_SOFT_RESET);
1960 pci_read_config_word(ha->pdev, PCI_COMMAND, &wd);
1962 /* Go with write. */
1963 qla2x00_flash_enable(ha);
1964 do { /* Loop once to provide quick error exit */
1965 /* Structure of flash memory based on manufacturer */
1966 if (IS_OEM_001(ha)) {
1967 /* OEM variant with special flash part. */
1968 man_id = flash_id = 0;
1973 qla2x00_get_flash_manufacturer(ha, &man_id, &flash_id);
1975 case 0x20: /* ST flash. */
1976 if (flash_id == 0xd2 || flash_id == 0xe3) {
1978 * ST m29w008at part - 64kb sector size with
1979 * 32kb,8kb,8kb,16kb sectors at memory address
1987 * ST m29w010b part - 16kb sector size
1988 * Default to 16kb sectors
1993 case 0x40: /* Mostel flash. */
1994 /* Mostel v29c51001 part - 512 byte sector size. */
1998 case 0xbf: /* SST flash. */
1999 /* SST39sf10 part - 4kb sector size. */
2003 case 0xda: /* Winbond flash. */
2004 /* Winbond W29EE011 part - 256 byte sector size. */
2008 case 0xc2: /* Macronix flash. */
2009 /* 64k sector size. */
2010 if (flash_id == 0x38 || flash_id == 0x4f) {
2015 /* Fall through... */
2017 case 0x1f: /* Atmel flash. */
2018 /* 512k sector size. */
2019 if (flash_id == 0x13) {
2020 rest_addr = 0x7fffffff;
2021 sec_mask = 0x80000000;
2024 /* Fall through... */
2026 case 0x01: /* AMD flash. */
2027 if (flash_id == 0x38 || flash_id == 0x40 ||
2029 /* Am29LV081 part - 64kb sector size. */
2030 /* Am29LV002BT part - 64kb sector size. */
2034 } else if (flash_id == 0x3e) {
2036 * Am29LV008b part - 64kb sector size with
2037 * 32kb,8kb,8kb,16kb sector at memory address
2043 } else if (flash_id == 0x20 || flash_id == 0x6e) {
2045 * Am29LV010 part or AM29f010 - 16kb sector
2051 } else if (flash_id == 0x6d) {
2052 /* Am29LV001 part - 8kb sector size. */
2058 /* Default to 16 kb sector size. */
2065 if (IS_QLA2322(ha) || IS_QLA6322(ha)) {
2066 if (qla2x00_erase_flash(ha, man_id, flash_id)) {
2067 rval = QLA_FUNCTION_FAILED;
2072 for (addr = offset, liter = 0; liter < length; liter++,
2075 /* Are we at the beginning of a sector? */
2076 if ((addr & rest_addr) == 0) {
2077 if (IS_QLA2322(ha) || IS_QLA6322(ha)) {
2078 if (addr >= 0x10000UL) {
2079 if (((addr >> 12) & 0xf0) &&
2081 flash_id == 0x3e) ||
2083 flash_id == 0xd2))) {
2085 if (sec_number == 1) {
2106 } else if (addr == ha->optrom_size / 2) {
2107 WRT_REG_WORD(®->nvram, NVR_SELECT);
2108 RD_REG_WORD(®->nvram);
2111 if (flash_id == 0xda && man_id == 0xc1) {
2112 qla2x00_write_flash_byte(ha, 0x5555,
2114 qla2x00_write_flash_byte(ha, 0x2aaa,
2116 qla2x00_write_flash_byte(ha, 0x5555,
2118 } else if (!IS_QLA2322(ha) && !IS_QLA6322(ha)) {
2120 if (qla2x00_erase_flash_sector(ha,
2121 addr, sec_mask, man_id,
2123 rval = QLA_FUNCTION_FAILED;
2126 if (man_id == 0x01 && flash_id == 0x6d)
2131 if (man_id == 0x01 && flash_id == 0x6d) {
2132 if (sec_number == 1 &&
2133 addr == (rest_addr - 1)) {
2136 } else if (sec_number == 3 && (addr & 0x7ffe)) {
2142 if (qla2x00_program_flash_address(ha, addr, data,
2143 man_id, flash_id)) {
2144 rval = QLA_FUNCTION_FAILED;
2150 qla2x00_flash_disable(ha);
2153 qla2x00_resume_hba(vha);
2159 qla24xx_read_optrom_data(struct scsi_qla_host *vha, uint8_t *buf,
2160 uint32_t offset, uint32_t length)
2162 struct qla_hw_data *ha = vha->hw;
2165 scsi_block_requests(vha->host);
2166 set_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags);
2169 qla24xx_read_flash_data(vha, (uint32_t *)buf, offset >> 2, length >> 2);
2172 clear_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags);
2173 scsi_unblock_requests(vha->host);
2179 qla24xx_write_optrom_data(struct scsi_qla_host *vha, uint8_t *buf,
2180 uint32_t offset, uint32_t length)
2183 struct qla_hw_data *ha = vha->hw;
2186 scsi_block_requests(vha->host);
2187 set_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags);
2189 /* Go with write. */
2190 rval = qla24xx_write_flash_data(vha, (uint32_t *)buf, offset >> 2,
2193 /* Resume HBA -- RISC reset needed. */
2194 clear_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags);
2195 set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
2196 qla2xxx_wake_dpc(vha);
2197 qla2x00_wait_for_hba_online(vha);
2198 scsi_unblock_requests(vha->host);
2204 qla25xx_read_optrom_data(struct scsi_qla_host *vha, uint8_t *buf,
2205 uint32_t offset, uint32_t length)
2208 dma_addr_t optrom_dma;
2211 uint32_t faddr, left, burst;
2212 struct qla_hw_data *ha = vha->hw;
2216 if (length < OPTROM_BURST_SIZE)
2219 optrom = dma_alloc_coherent(&ha->pdev->dev, OPTROM_BURST_SIZE,
2220 &optrom_dma, GFP_KERNEL);
2222 qla_printk(KERN_DEBUG, ha,
2223 "Unable to allocate memory for optrom burst read "
2224 "(%x KB).\n", OPTROM_BURST_SIZE / 1024);
2230 faddr = offset >> 2;
2232 burst = OPTROM_BURST_DWORDS;
2237 rval = qla2x00_dump_ram(vha, optrom_dma,
2238 flash_data_to_access_addr(faddr), burst);
2240 qla_printk(KERN_WARNING, ha,
2241 "Unable to burst-read optrom segment "
2242 "(%x/%x/%llx).\n", rval,
2243 flash_data_to_access_addr(faddr),
2244 (unsigned long long)optrom_dma);
2245 qla_printk(KERN_WARNING, ha,
2246 "Reverting to slow-read.\n");
2248 dma_free_coherent(&ha->pdev->dev, OPTROM_BURST_SIZE,
2249 optrom, optrom_dma);
2253 memcpy(pbuf, optrom, burst * 4);
2260 dma_free_coherent(&ha->pdev->dev, OPTROM_BURST_SIZE, optrom,
2266 return qla24xx_read_optrom_data(vha, buf, offset, length);
2270 * qla2x00_get_fcode_version() - Determine an FCODE image's version.
2272 * @pcids: Pointer to the FCODE PCI data structure
2274 * The process of retrieving the FCODE version information is at best
2275 * described as interesting.
2277 * Within the first 100h bytes of the image an ASCII string is present
2278 * which contains several pieces of information including the FCODE
2279 * version. Unfortunately it seems the only reliable way to retrieve
2280 * the version is by scanning for another sentinel within the string,
2281 * the FCODE build date:
2283 * ... 2.00.02 10/17/02 ...
2285 * Returns QLA_SUCCESS on successful retrieval of version.
2288 qla2x00_get_fcode_version(struct qla_hw_data *ha, uint32_t pcids)
2290 int ret = QLA_FUNCTION_FAILED;
2291 uint32_t istart, iend, iter, vend;
2292 uint8_t do_next, rbyte, *vbyte;
2294 memset(ha->fcode_revision, 0, sizeof(ha->fcode_revision));
2296 /* Skip the PCI data structure. */
2298 ((qla2x00_read_flash_byte(ha, pcids + 0x0B) << 8) |
2299 qla2x00_read_flash_byte(ha, pcids + 0x0A));
2300 iend = istart + 0x100;
2302 /* Scan for the sentinel date string...eeewww. */
2305 while ((iter < iend) && !do_next) {
2307 if (qla2x00_read_flash_byte(ha, iter) == '/') {
2308 if (qla2x00_read_flash_byte(ha, iter + 2) ==
2311 else if (qla2x00_read_flash_byte(ha,
2319 /* Backtrack to previous ' ' (space). */
2321 while ((iter > istart) && !do_next) {
2323 if (qla2x00_read_flash_byte(ha, iter) == ' ')
2330 * Mark end of version tag, and find previous ' ' (space) or
2331 * string length (recent FCODE images -- major hack ahead!!!).
2335 while ((iter > istart) && !do_next) {
2337 rbyte = qla2x00_read_flash_byte(ha, iter);
2338 if (rbyte == ' ' || rbyte == 0xd || rbyte == 0x10)
2344 /* Mark beginning of version tag, and copy data. */
2346 if ((vend - iter) &&
2347 ((vend - iter) < sizeof(ha->fcode_revision))) {
2348 vbyte = ha->fcode_revision;
2349 while (iter <= vend) {
2350 *vbyte++ = qla2x00_read_flash_byte(ha, iter);
2357 if (ret != QLA_SUCCESS)
2358 memset(ha->fcode_revision, 0, sizeof(ha->fcode_revision));
2362 qla2x00_get_flash_version(scsi_qla_host_t *vha, void *mbuf)
2364 int ret = QLA_SUCCESS;
2365 uint8_t code_type, last_image;
2366 uint32_t pcihdr, pcids;
2369 struct qla_hw_data *ha = vha->hw;
2371 if (!ha->pio_address || !mbuf)
2372 return QLA_FUNCTION_FAILED;
2374 memset(ha->bios_revision, 0, sizeof(ha->bios_revision));
2375 memset(ha->efi_revision, 0, sizeof(ha->efi_revision));
2376 memset(ha->fcode_revision, 0, sizeof(ha->fcode_revision));
2377 memset(ha->fw_revision, 0, sizeof(ha->fw_revision));
2379 qla2x00_flash_enable(ha);
2381 /* Begin with first PCI expansion ROM header. */
2385 /* Verify PCI expansion ROM header. */
2386 if (qla2x00_read_flash_byte(ha, pcihdr) != 0x55 ||
2387 qla2x00_read_flash_byte(ha, pcihdr + 0x01) != 0xaa) {
2389 DEBUG2(qla_printk(KERN_DEBUG, ha, "No matching ROM "
2391 ret = QLA_FUNCTION_FAILED;
2395 /* Locate PCI data structure. */
2397 ((qla2x00_read_flash_byte(ha, pcihdr + 0x19) << 8) |
2398 qla2x00_read_flash_byte(ha, pcihdr + 0x18));
2400 /* Validate signature of PCI data structure. */
2401 if (qla2x00_read_flash_byte(ha, pcids) != 'P' ||
2402 qla2x00_read_flash_byte(ha, pcids + 0x1) != 'C' ||
2403 qla2x00_read_flash_byte(ha, pcids + 0x2) != 'I' ||
2404 qla2x00_read_flash_byte(ha, pcids + 0x3) != 'R') {
2405 /* Incorrect header. */
2406 DEBUG2(qla_printk(KERN_INFO, ha, "PCI data struct not "
2407 "found pcir_adr=%x.\n", pcids));
2408 ret = QLA_FUNCTION_FAILED;
2413 code_type = qla2x00_read_flash_byte(ha, pcids + 0x14);
2414 switch (code_type) {
2415 case ROM_CODE_TYPE_BIOS:
2416 /* Intel x86, PC-AT compatible. */
2417 ha->bios_revision[0] =
2418 qla2x00_read_flash_byte(ha, pcids + 0x12);
2419 ha->bios_revision[1] =
2420 qla2x00_read_flash_byte(ha, pcids + 0x13);
2421 DEBUG3(qla_printk(KERN_DEBUG, ha, "read BIOS %d.%d.\n",
2422 ha->bios_revision[1], ha->bios_revision[0]));
2424 case ROM_CODE_TYPE_FCODE:
2425 /* Open Firmware standard for PCI (FCode). */
2427 qla2x00_get_fcode_version(ha, pcids);
2429 case ROM_CODE_TYPE_EFI:
2430 /* Extensible Firmware Interface (EFI). */
2431 ha->efi_revision[0] =
2432 qla2x00_read_flash_byte(ha, pcids + 0x12);
2433 ha->efi_revision[1] =
2434 qla2x00_read_flash_byte(ha, pcids + 0x13);
2435 DEBUG3(qla_printk(KERN_DEBUG, ha, "read EFI %d.%d.\n",
2436 ha->efi_revision[1], ha->efi_revision[0]));
2439 DEBUG2(qla_printk(KERN_INFO, ha, "Unrecognized code "
2440 "type %x at pcids %x.\n", code_type, pcids));
2444 last_image = qla2x00_read_flash_byte(ha, pcids + 0x15) & BIT_7;
2446 /* Locate next PCI expansion ROM. */
2447 pcihdr += ((qla2x00_read_flash_byte(ha, pcids + 0x11) << 8) |
2448 qla2x00_read_flash_byte(ha, pcids + 0x10)) * 512;
2449 } while (!last_image);
2451 if (IS_QLA2322(ha)) {
2452 /* Read firmware image information. */
2453 memset(ha->fw_revision, 0, sizeof(ha->fw_revision));
2455 memset(dbyte, 0, 8);
2456 dcode = (uint16_t *)dbyte;
2458 qla2x00_read_flash_data(ha, dbyte, ha->flt_region_fw * 4 + 10,
2460 DEBUG3(qla_printk(KERN_DEBUG, ha, "dumping fw ver from "
2462 DEBUG3(qla2x00_dump_buffer((uint8_t *)dbyte, 8));
2464 if ((dcode[0] == 0xffff && dcode[1] == 0xffff &&
2465 dcode[2] == 0xffff && dcode[3] == 0xffff) ||
2466 (dcode[0] == 0 && dcode[1] == 0 && dcode[2] == 0 &&
2468 DEBUG2(qla_printk(KERN_INFO, ha, "Unrecognized fw "
2469 "revision at %x.\n", ha->flt_region_fw * 4));
2471 /* values are in big endian */
2472 ha->fw_revision[0] = dbyte[0] << 16 | dbyte[1];
2473 ha->fw_revision[1] = dbyte[2] << 16 | dbyte[3];
2474 ha->fw_revision[2] = dbyte[4] << 16 | dbyte[5];
2478 qla2x00_flash_disable(ha);
2484 qla24xx_get_flash_version(scsi_qla_host_t *vha, void *mbuf)
2486 int ret = QLA_SUCCESS;
2487 uint32_t pcihdr, pcids;
2490 uint8_t code_type, last_image;
2492 struct qla_hw_data *ha = vha->hw;
2495 return QLA_FUNCTION_FAILED;
2497 memset(ha->bios_revision, 0, sizeof(ha->bios_revision));
2498 memset(ha->efi_revision, 0, sizeof(ha->efi_revision));
2499 memset(ha->fcode_revision, 0, sizeof(ha->fcode_revision));
2500 memset(ha->fw_revision, 0, sizeof(ha->fw_revision));
2504 /* Begin with first PCI expansion ROM header. */
2505 pcihdr = ha->flt_region_boot;
2508 /* Verify PCI expansion ROM header. */
2509 qla24xx_read_flash_data(vha, dcode, pcihdr >> 2, 0x20);
2510 bcode = mbuf + (pcihdr % 4);
2511 if (bcode[0x0] != 0x55 || bcode[0x1] != 0xaa) {
2513 DEBUG2(qla_printk(KERN_DEBUG, ha, "No matching ROM "
2515 ret = QLA_FUNCTION_FAILED;
2519 /* Locate PCI data structure. */
2520 pcids = pcihdr + ((bcode[0x19] << 8) | bcode[0x18]);
2522 qla24xx_read_flash_data(vha, dcode, pcids >> 2, 0x20);
2523 bcode = mbuf + (pcihdr % 4);
2525 /* Validate signature of PCI data structure. */
2526 if (bcode[0x0] != 'P' || bcode[0x1] != 'C' ||
2527 bcode[0x2] != 'I' || bcode[0x3] != 'R') {
2528 /* Incorrect header. */
2529 DEBUG2(qla_printk(KERN_INFO, ha, "PCI data struct not "
2530 "found pcir_adr=%x.\n", pcids));
2531 ret = QLA_FUNCTION_FAILED;
2536 code_type = bcode[0x14];
2537 switch (code_type) {
2538 case ROM_CODE_TYPE_BIOS:
2539 /* Intel x86, PC-AT compatible. */
2540 ha->bios_revision[0] = bcode[0x12];
2541 ha->bios_revision[1] = bcode[0x13];
2542 DEBUG3(qla_printk(KERN_DEBUG, ha, "read BIOS %d.%d.\n",
2543 ha->bios_revision[1], ha->bios_revision[0]));
2545 case ROM_CODE_TYPE_FCODE:
2546 /* Open Firmware standard for PCI (FCode). */
2547 ha->fcode_revision[0] = bcode[0x12];
2548 ha->fcode_revision[1] = bcode[0x13];
2549 DEBUG3(qla_printk(KERN_DEBUG, ha, "read FCODE %d.%d.\n",
2550 ha->fcode_revision[1], ha->fcode_revision[0]));
2552 case ROM_CODE_TYPE_EFI:
2553 /* Extensible Firmware Interface (EFI). */
2554 ha->efi_revision[0] = bcode[0x12];
2555 ha->efi_revision[1] = bcode[0x13];
2556 DEBUG3(qla_printk(KERN_DEBUG, ha, "read EFI %d.%d.\n",
2557 ha->efi_revision[1], ha->efi_revision[0]));
2560 DEBUG2(qla_printk(KERN_INFO, ha, "Unrecognized code "
2561 "type %x at pcids %x.\n", code_type, pcids));
2565 last_image = bcode[0x15] & BIT_7;
2567 /* Locate next PCI expansion ROM. */
2568 pcihdr += ((bcode[0x11] << 8) | bcode[0x10]) * 512;
2569 } while (!last_image);
2571 /* Read firmware image information. */
2572 memset(ha->fw_revision, 0, sizeof(ha->fw_revision));
2575 qla24xx_read_flash_data(vha, dcode, ha->flt_region_fw + 4, 4);
2576 for (i = 0; i < 4; i++)
2577 dcode[i] = be32_to_cpu(dcode[i]);
2579 if ((dcode[0] == 0xffffffff && dcode[1] == 0xffffffff &&
2580 dcode[2] == 0xffffffff && dcode[3] == 0xffffffff) ||
2581 (dcode[0] == 0 && dcode[1] == 0 && dcode[2] == 0 &&
2583 DEBUG2(qla_printk(KERN_INFO, ha, "Unrecognized fw "
2584 "revision at %x.\n", ha->flt_region_fw * 4));
2586 ha->fw_revision[0] = dcode[0];
2587 ha->fw_revision[1] = dcode[1];
2588 ha->fw_revision[2] = dcode[2];
2589 ha->fw_revision[3] = dcode[3];
2596 qla2xxx_is_vpd_valid(uint8_t *pos, uint8_t *end)
2598 if (pos >= end || *pos != 0x82)
2602 if (pos >= end || *pos != 0x90)
2606 if (pos >= end || *pos != 0x78)
2613 qla2xxx_get_vpd_field(scsi_qla_host_t *vha, char *key, char *str, size_t size)
2615 struct qla_hw_data *ha = vha->hw;
2616 uint8_t *pos = ha->vpd;
2617 uint8_t *end = pos + ha->vpd_size;
2620 if (!IS_FWI2_CAPABLE(ha) || !qla2xxx_is_vpd_valid(pos, end))
2623 while (pos < end && *pos != 0x78) {
2624 len = (*pos == 0x82) ? pos[1] : pos[2];
2626 if (!strncmp(pos, key, strlen(key)))
2629 if (*pos != 0x90 && *pos != 0x91)
2635 if (pos < end - len && *pos != 0x78)
2636 return snprintf(str, size, "%.*s", len, pos + 3);