2 * sata_nv.c - NVIDIA nForce SATA
4 * Copyright 2004 NVIDIA Corp. All rights reserved.
5 * Copyright 2004 Andrew Chew
7 * The contents of this file are subject to the Open
8 * Software License version 1.1 that can be found at
9 * http://www.opensource.org/licenses/osl-1.1.txt and is included herein
12 * Alternatively, the contents of this file may be used under the terms
13 * of the GNU General Public License version 2 (the "GPL") as distributed
14 * in the kernel source COPYING file, in which case the provisions of
15 * the GPL are applicable instead of the above. If you wish to allow
16 * the use of your version of this file only under the terms of the
17 * GPL and not to allow others to use your version of this file under
18 * the OSL, indicate your decision by deleting the provisions above and
19 * replace them with the notice and other provisions required by the GPL.
20 * If you do not delete the provisions above, a recipient may use your
21 * version of this file under either the OSL or the GPL.
24 * libata documentation is available via 'make {ps|pdf}docs',
25 * as Documentation/DocBook/libata.*
27 * No hardware documentation available outside of NVIDIA.
28 * This driver programs the NVIDIA SATA controller in a similar
29 * fashion as with other PCI IDE BMDMA controllers, with a few
30 * NV-specific details such as register offsets, SATA phy location,
35 * - Added generic SATA support by using a pci_device_id that filters on
36 * the IDE storage class code.
39 * - Fixed a bug where the hotplug handlers for non-CK804/MCP04 were using
40 * mmio_base, which is only set for the CK804/MCP04 case.
43 * - Added support for CK804 SATA controller.
49 #include <linux/config.h>
50 #include <linux/kernel.h>
51 #include <linux/module.h>
52 #include <linux/pci.h>
53 #include <linux/init.h>
54 #include <linux/blkdev.h>
55 #include <linux/delay.h>
56 #include <linux/interrupt.h>
58 #include <scsi/scsi_host.h>
59 #include <linux/libata.h>
61 #define DRV_NAME "sata_nv"
62 #define DRV_VERSION "0.6"
65 #define NV_PIO_MASK 0x1f
66 #define NV_MWDMA_MASK 0x07
67 #define NV_UDMA_MASK 0x7f
68 #define NV_PORT0_SCR_REG_OFFSET 0x00
69 #define NV_PORT1_SCR_REG_OFFSET 0x40
71 #define NV_INT_STATUS 0x10
72 #define NV_INT_STATUS_CK804 0x440
73 #define NV_INT_STATUS_PDEV_INT 0x01
74 #define NV_INT_STATUS_PDEV_PM 0x02
75 #define NV_INT_STATUS_PDEV_ADDED 0x04
76 #define NV_INT_STATUS_PDEV_REMOVED 0x08
77 #define NV_INT_STATUS_SDEV_INT 0x10
78 #define NV_INT_STATUS_SDEV_PM 0x20
79 #define NV_INT_STATUS_SDEV_ADDED 0x40
80 #define NV_INT_STATUS_SDEV_REMOVED 0x80
81 #define NV_INT_STATUS_PDEV_HOTPLUG (NV_INT_STATUS_PDEV_ADDED | \
82 NV_INT_STATUS_PDEV_REMOVED)
83 #define NV_INT_STATUS_SDEV_HOTPLUG (NV_INT_STATUS_SDEV_ADDED | \
84 NV_INT_STATUS_SDEV_REMOVED)
85 #define NV_INT_STATUS_HOTPLUG (NV_INT_STATUS_PDEV_HOTPLUG | \
86 NV_INT_STATUS_SDEV_HOTPLUG)
88 #define NV_INT_ENABLE 0x11
89 #define NV_INT_ENABLE_CK804 0x441
90 #define NV_INT_ENABLE_PDEV_MASK 0x01
91 #define NV_INT_ENABLE_PDEV_PM 0x02
92 #define NV_INT_ENABLE_PDEV_ADDED 0x04
93 #define NV_INT_ENABLE_PDEV_REMOVED 0x08
94 #define NV_INT_ENABLE_SDEV_MASK 0x10
95 #define NV_INT_ENABLE_SDEV_PM 0x20
96 #define NV_INT_ENABLE_SDEV_ADDED 0x40
97 #define NV_INT_ENABLE_SDEV_REMOVED 0x80
98 #define NV_INT_ENABLE_PDEV_HOTPLUG (NV_INT_ENABLE_PDEV_ADDED | \
99 NV_INT_ENABLE_PDEV_REMOVED)
100 #define NV_INT_ENABLE_SDEV_HOTPLUG (NV_INT_ENABLE_SDEV_ADDED | \
101 NV_INT_ENABLE_SDEV_REMOVED)
102 #define NV_INT_ENABLE_HOTPLUG (NV_INT_ENABLE_PDEV_HOTPLUG | \
103 NV_INT_ENABLE_SDEV_HOTPLUG)
105 #define NV_INT_CONFIG 0x12
106 #define NV_INT_CONFIG_METHD 0x01 // 0 = INT, 1 = SMI
108 // For PCI config register 20
109 #define NV_MCP_SATA_CFG_20 0x50
110 #define NV_MCP_SATA_CFG_20_SATA_SPACE_EN 0x04
112 static int nv_init_one (struct pci_dev *pdev, const struct pci_device_id *ent);
113 static irqreturn_t nv_interrupt (int irq, void *dev_instance,
114 struct pt_regs *regs);
115 static u32 nv_scr_read (struct ata_port *ap, unsigned int sc_reg);
116 static void nv_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val);
117 static void nv_host_stop (struct ata_host_set *host_set);
118 static void nv_enable_hotplug(struct ata_probe_ent *probe_ent);
119 static void nv_disable_hotplug(struct ata_host_set *host_set);
120 static void nv_check_hotplug(struct ata_host_set *host_set);
121 static void nv_enable_hotplug_ck804(struct ata_probe_ent *probe_ent);
122 static void nv_disable_hotplug_ck804(struct ata_host_set *host_set);
123 static void nv_check_hotplug_ck804(struct ata_host_set *host_set);
133 static struct pci_device_id nv_pci_tbl[] = {
134 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE2S_SATA,
135 PCI_ANY_ID, PCI_ANY_ID, 0, 0, NFORCE2 },
136 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE3S_SATA,
137 PCI_ANY_ID, PCI_ANY_ID, 0, 0, NFORCE3 },
138 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE3S_SATA2,
139 PCI_ANY_ID, PCI_ANY_ID, 0, 0, NFORCE3 },
140 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_CK804_SATA,
141 PCI_ANY_ID, PCI_ANY_ID, 0, 0, CK804 },
142 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_CK804_SATA2,
143 PCI_ANY_ID, PCI_ANY_ID, 0, 0, CK804 },
144 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP04_SATA,
145 PCI_ANY_ID, PCI_ANY_ID, 0, 0, CK804 },
146 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP04_SATA2,
147 PCI_ANY_ID, PCI_ANY_ID, 0, 0, CK804 },
148 { PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID,
149 PCI_ANY_ID, PCI_ANY_ID,
150 PCI_CLASS_STORAGE_IDE<<8, 0xffff00, GENERIC },
151 { 0, } /* terminate list */
154 #define NV_HOST_FLAGS_SCR_MMIO 0x00000001
158 enum nv_host_type host_type;
159 void (*enable_hotplug)(struct ata_probe_ent *probe_ent);
160 void (*disable_hotplug)(struct ata_host_set *host_set);
161 void (*check_hotplug)(struct ata_host_set *host_set);
164 static struct nv_host_desc nv_device_tbl[] = {
166 .host_type = GENERIC,
167 .enable_hotplug = NULL,
168 .disable_hotplug= NULL,
169 .check_hotplug = NULL,
172 .host_type = NFORCE2,
173 .enable_hotplug = nv_enable_hotplug,
174 .disable_hotplug= nv_disable_hotplug,
175 .check_hotplug = nv_check_hotplug,
178 .host_type = NFORCE3,
179 .enable_hotplug = nv_enable_hotplug,
180 .disable_hotplug= nv_disable_hotplug,
181 .check_hotplug = nv_check_hotplug,
183 { .host_type = CK804,
184 .enable_hotplug = nv_enable_hotplug_ck804,
185 .disable_hotplug= nv_disable_hotplug_ck804,
186 .check_hotplug = nv_check_hotplug_ck804,
192 struct nv_host_desc *host_desc;
193 unsigned long host_flags;
196 static struct pci_driver nv_pci_driver = {
198 .id_table = nv_pci_tbl,
199 .probe = nv_init_one,
200 .remove = ata_pci_remove_one,
203 static Scsi_Host_Template nv_sht = {
204 .module = THIS_MODULE,
206 .ioctl = ata_scsi_ioctl,
207 .queuecommand = ata_scsi_queuecmd,
208 .eh_strategy_handler = ata_scsi_error,
209 .can_queue = ATA_DEF_QUEUE,
210 .this_id = ATA_SHT_THIS_ID,
211 .sg_tablesize = LIBATA_MAX_PRD,
212 .max_sectors = ATA_MAX_SECTORS,
213 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
214 .emulated = ATA_SHT_EMULATED,
215 .use_clustering = ATA_SHT_USE_CLUSTERING,
216 .proc_name = DRV_NAME,
217 .dma_boundary = ATA_DMA_BOUNDARY,
218 .slave_configure = ata_scsi_slave_config,
219 .bios_param = ata_std_bios_param,
223 static struct ata_port_operations nv_ops = {
224 .port_disable = ata_port_disable,
225 .tf_load = ata_tf_load,
226 .tf_read = ata_tf_read,
227 .exec_command = ata_exec_command,
228 .check_status = ata_check_status,
229 .dev_select = ata_std_dev_select,
230 .phy_reset = sata_phy_reset,
231 .bmdma_setup = ata_bmdma_setup,
232 .bmdma_start = ata_bmdma_start,
233 .bmdma_stop = ata_bmdma_stop,
234 .bmdma_status = ata_bmdma_status,
235 .qc_prep = ata_qc_prep,
236 .qc_issue = ata_qc_issue_prot,
237 .eng_timeout = ata_eng_timeout,
238 .irq_handler = nv_interrupt,
239 .irq_clear = ata_bmdma_irq_clear,
240 .scr_read = nv_scr_read,
241 .scr_write = nv_scr_write,
242 .port_start = ata_port_start,
243 .port_stop = ata_port_stop,
244 .host_stop = nv_host_stop,
247 /* FIXME: The hardware provides the necessary SATA PHY controls
248 * to support ATA_FLAG_SATA_RESET. However, it is currently
249 * necessary to disable that flag, to solve misdetection problems.
250 * See http://bugme.osdl.org/show_bug.cgi?id=3352 for more info.
252 * This problem really needs to be investigated further. But in the
253 * meantime, we avoid ATA_FLAG_SATA_RESET to get people working.
255 static struct ata_port_info nv_port_info = {
257 .host_flags = ATA_FLAG_SATA |
258 /* ATA_FLAG_SATA_RESET | */
261 .pio_mask = NV_PIO_MASK,
262 .mwdma_mask = NV_MWDMA_MASK,
263 .udma_mask = NV_UDMA_MASK,
267 MODULE_AUTHOR("NVIDIA");
268 MODULE_DESCRIPTION("low-level driver for NVIDIA nForce SATA controller");
269 MODULE_LICENSE("GPL");
270 MODULE_DEVICE_TABLE(pci, nv_pci_tbl);
271 MODULE_VERSION(DRV_VERSION);
273 static irqreturn_t nv_interrupt (int irq, void *dev_instance,
274 struct pt_regs *regs)
276 struct ata_host_set *host_set = dev_instance;
277 struct nv_host *host = host_set->private_data;
279 unsigned int handled = 0;
282 spin_lock_irqsave(&host_set->lock, flags);
284 for (i = 0; i < host_set->n_ports; i++) {
287 ap = host_set->ports[i];
288 if (ap && (!(ap->flags & ATA_FLAG_PORT_DISABLED))) {
289 struct ata_queued_cmd *qc;
291 qc = ata_qc_from_tag(ap, ap->active_tag);
292 if (qc && (!(qc->tf.ctl & ATA_NIEN)))
293 handled += ata_host_intr(ap, qc);
298 if (host->host_desc->check_hotplug)
299 host->host_desc->check_hotplug(host_set);
301 spin_unlock_irqrestore(&host_set->lock, flags);
303 return IRQ_RETVAL(handled);
306 static u32 nv_scr_read (struct ata_port *ap, unsigned int sc_reg)
308 struct ata_host_set *host_set = ap->host_set;
309 struct nv_host *host = host_set->private_data;
311 if (sc_reg > SCR_CONTROL)
314 if (host->host_flags & NV_HOST_FLAGS_SCR_MMIO)
315 return readl((void*)ap->ioaddr.scr_addr + (sc_reg * 4));
317 return inl(ap->ioaddr.scr_addr + (sc_reg * 4));
320 static void nv_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val)
322 struct ata_host_set *host_set = ap->host_set;
323 struct nv_host *host = host_set->private_data;
325 if (sc_reg > SCR_CONTROL)
328 if (host->host_flags & NV_HOST_FLAGS_SCR_MMIO)
329 writel(val, (void*)ap->ioaddr.scr_addr + (sc_reg * 4));
331 outl(val, ap->ioaddr.scr_addr + (sc_reg * 4));
334 static void nv_host_stop (struct ata_host_set *host_set)
336 struct nv_host *host = host_set->private_data;
338 // Disable hotplug event interrupts.
339 if (host->host_desc->disable_hotplug)
340 host->host_desc->disable_hotplug(host_set);
344 ata_host_stop(host_set);
347 static int nv_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
349 static int printed_version = 0;
350 struct nv_host *host;
351 struct ata_port_info *ppi;
352 struct ata_probe_ent *probe_ent;
353 int pci_dev_busy = 0;
357 // Make sure this is a SATA controller by counting the number of bars
358 // (NVIDIA SATA controllers will always have six bars). Otherwise,
359 // it's an IDE controller and we ignore it.
360 for (bar=0; bar<6; bar++)
361 if (pci_resource_start(pdev, bar) == 0)
364 if (!printed_version++)
365 printk(KERN_DEBUG DRV_NAME " version " DRV_VERSION "\n");
367 rc = pci_enable_device(pdev);
371 rc = pci_request_regions(pdev, DRV_NAME);
374 goto err_out_disable;
377 rc = pci_set_dma_mask(pdev, ATA_DMA_MASK);
379 goto err_out_regions;
380 rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK);
382 goto err_out_regions;
387 probe_ent = ata_pci_init_native_mode(pdev, &ppi);
389 goto err_out_regions;
391 host = kmalloc(sizeof(struct nv_host), GFP_KERNEL);
393 goto err_out_free_ent;
395 memset(host, 0, sizeof(struct nv_host));
396 host->host_desc = &nv_device_tbl[ent->driver_data];
398 probe_ent->private_data = host;
400 if (pci_resource_flags(pdev, 5) & IORESOURCE_MEM)
401 host->host_flags |= NV_HOST_FLAGS_SCR_MMIO;
403 if (host->host_flags & NV_HOST_FLAGS_SCR_MMIO) {
406 probe_ent->mmio_base = ioremap(pci_resource_start(pdev, 5),
407 pci_resource_len(pdev, 5));
408 if (probe_ent->mmio_base == NULL) {
410 goto err_out_free_host;
413 base = (unsigned long)probe_ent->mmio_base;
415 probe_ent->port[0].scr_addr =
416 base + NV_PORT0_SCR_REG_OFFSET;
417 probe_ent->port[1].scr_addr =
418 base + NV_PORT1_SCR_REG_OFFSET;
421 probe_ent->port[0].scr_addr =
422 pci_resource_start(pdev, 5) | NV_PORT0_SCR_REG_OFFSET;
423 probe_ent->port[1].scr_addr =
424 pci_resource_start(pdev, 5) | NV_PORT1_SCR_REG_OFFSET;
427 pci_set_master(pdev);
429 rc = ata_device_add(probe_ent);
431 goto err_out_iounmap;
433 // Enable hotplug event interrupts.
434 if (host->host_desc->enable_hotplug)
435 host->host_desc->enable_hotplug(probe_ent);
442 if (host->host_flags & NV_HOST_FLAGS_SCR_MMIO)
443 iounmap(probe_ent->mmio_base);
449 pci_release_regions(pdev);
452 pci_disable_device(pdev);
457 static void nv_enable_hotplug(struct ata_probe_ent *probe_ent)
461 outb(NV_INT_STATUS_HOTPLUG,
462 probe_ent->port[0].scr_addr + NV_INT_STATUS);
464 intr_mask = inb(probe_ent->port[0].scr_addr + NV_INT_ENABLE);
465 intr_mask |= NV_INT_ENABLE_HOTPLUG;
467 outb(intr_mask, probe_ent->port[0].scr_addr + NV_INT_ENABLE);
470 static void nv_disable_hotplug(struct ata_host_set *host_set)
474 intr_mask = inb(host_set->ports[0]->ioaddr.scr_addr + NV_INT_ENABLE);
476 intr_mask &= ~(NV_INT_ENABLE_HOTPLUG);
478 outb(intr_mask, host_set->ports[0]->ioaddr.scr_addr + NV_INT_ENABLE);
481 static void nv_check_hotplug(struct ata_host_set *host_set)
485 intr_status = inb(host_set->ports[0]->ioaddr.scr_addr + NV_INT_STATUS);
487 // Clear interrupt status.
488 outb(0xff, host_set->ports[0]->ioaddr.scr_addr + NV_INT_STATUS);
490 if (intr_status & NV_INT_STATUS_HOTPLUG) {
491 if (intr_status & NV_INT_STATUS_PDEV_ADDED)
492 printk(KERN_WARNING "nv_sata: "
493 "Primary device added\n");
495 if (intr_status & NV_INT_STATUS_PDEV_REMOVED)
496 printk(KERN_WARNING "nv_sata: "
497 "Primary device removed\n");
499 if (intr_status & NV_INT_STATUS_SDEV_ADDED)
500 printk(KERN_WARNING "nv_sata: "
501 "Secondary device added\n");
503 if (intr_status & NV_INT_STATUS_SDEV_REMOVED)
504 printk(KERN_WARNING "nv_sata: "
505 "Secondary device removed\n");
509 static void nv_enable_hotplug_ck804(struct ata_probe_ent *probe_ent)
511 struct pci_dev *pdev = to_pci_dev(probe_ent->dev);
515 pci_read_config_byte(pdev, NV_MCP_SATA_CFG_20, ®val);
516 regval |= NV_MCP_SATA_CFG_20_SATA_SPACE_EN;
517 pci_write_config_byte(pdev, NV_MCP_SATA_CFG_20, regval);
519 writeb(NV_INT_STATUS_HOTPLUG, probe_ent->mmio_base + NV_INT_STATUS_CK804);
521 intr_mask = readb(probe_ent->mmio_base + NV_INT_ENABLE_CK804);
522 intr_mask |= NV_INT_ENABLE_HOTPLUG;
524 writeb(intr_mask, probe_ent->mmio_base + NV_INT_ENABLE_CK804);
527 static void nv_disable_hotplug_ck804(struct ata_host_set *host_set)
529 struct pci_dev *pdev = to_pci_dev(host_set->dev);
533 intr_mask = readb(host_set->mmio_base + NV_INT_ENABLE_CK804);
535 intr_mask &= ~(NV_INT_ENABLE_HOTPLUG);
537 writeb(intr_mask, host_set->mmio_base + NV_INT_ENABLE_CK804);
539 pci_read_config_byte(pdev, NV_MCP_SATA_CFG_20, ®val);
540 regval &= ~NV_MCP_SATA_CFG_20_SATA_SPACE_EN;
541 pci_write_config_byte(pdev, NV_MCP_SATA_CFG_20, regval);
544 static void nv_check_hotplug_ck804(struct ata_host_set *host_set)
548 intr_status = readb(host_set->mmio_base + NV_INT_STATUS_CK804);
550 // Clear interrupt status.
551 writeb(0xff, host_set->mmio_base + NV_INT_STATUS_CK804);
553 if (intr_status & NV_INT_STATUS_HOTPLUG) {
554 if (intr_status & NV_INT_STATUS_PDEV_ADDED)
555 printk(KERN_WARNING "nv_sata: "
556 "Primary device added\n");
558 if (intr_status & NV_INT_STATUS_PDEV_REMOVED)
559 printk(KERN_WARNING "nv_sata: "
560 "Primary device removed\n");
562 if (intr_status & NV_INT_STATUS_SDEV_ADDED)
563 printk(KERN_WARNING "nv_sata: "
564 "Secondary device added\n");
566 if (intr_status & NV_INT_STATUS_SDEV_REMOVED)
567 printk(KERN_WARNING "nv_sata: "
568 "Secondary device removed\n");
572 static int __init nv_init(void)
574 return pci_module_init(&nv_pci_driver);
577 static void __exit nv_exit(void)
579 pci_unregister_driver(&nv_pci_driver);
582 module_init(nv_init);
583 module_exit(nv_exit);