2 * sata_sil.c - Silicon Image SATA
4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
8 * Copyright 2003 Red Hat, Inc.
9 * Copyright 2003 Benjamin Herrenschmidt
11 * The contents of this file are subject to the Open
12 * Software License version 1.1 that can be found at
13 * http://www.opensource.org/licenses/osl-1.1.txt and is included herein
16 * Alternatively, the contents of this file may be used under the terms
17 * of the GNU General Public License version 2 (the "GPL") as distributed
18 * in the kernel source COPYING file, in which case the provisions of
19 * the GPL are applicable instead of the above. If you wish to allow
20 * the use of your version of this file only under the terms of the
21 * GPL and not to allow others to use your version of this file under
22 * the OSL, indicate your decision by deleting the provisions above and
23 * replace them with the notice and other provisions required by the GPL.
24 * If you do not delete the provisions above, a recipient may use your
25 * version of this file under either the OSL or the GPL.
29 #include <linux/kernel.h>
30 #include <linux/module.h>
31 #include <linux/pci.h>
32 #include <linux/init.h>
33 #include <linux/blkdev.h>
34 #include <linux/delay.h>
35 #include <linux/interrupt.h>
37 #include <scsi/scsi_host.h>
38 #include <linux/libata.h>
40 #define DRV_NAME "sata_sil"
41 #define DRV_VERSION "0.9"
44 SIL_FLAG_MOD15WRITE = (1 << 30),
60 SIL_MASK_IDE0_INT = (1 << 22),
61 SIL_MASK_IDE1_INT = (1 << 23),
62 SIL_MASK_IDE2_INT = (1 << 24),
63 SIL_MASK_IDE3_INT = (1 << 25),
64 SIL_MASK_2PORT = SIL_MASK_IDE0_INT | SIL_MASK_IDE1_INT,
65 SIL_MASK_4PORT = SIL_MASK_2PORT |
66 SIL_MASK_IDE2_INT | SIL_MASK_IDE3_INT,
68 SIL_IDE2_BMDMA = 0x200,
70 SIL_INTR_STEERING = (1 << 1),
71 SIL_QUIRK_MOD15WRITE = (1 << 0),
72 SIL_QUIRK_UDMA5MAX = (1 << 1),
75 static int sil_init_one (struct pci_dev *pdev, const struct pci_device_id *ent);
76 static void sil_dev_config(struct ata_port *ap, struct ata_device *dev);
77 static u32 sil_scr_read (struct ata_port *ap, unsigned int sc_reg);
78 static void sil_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val);
79 static void sil_post_set_mode (struct ata_port *ap);
81 static struct pci_device_id sil_pci_tbl[] = {
82 { 0x1095, 0x3112, PCI_ANY_ID, PCI_ANY_ID, 0, 0, sil_3112_m15w },
83 { 0x1095, 0x0240, PCI_ANY_ID, PCI_ANY_ID, 0, 0, sil_3112_m15w },
84 { 0x1095, 0x3512, PCI_ANY_ID, PCI_ANY_ID, 0, 0, sil_3112 },
85 { 0x1095, 0x3114, PCI_ANY_ID, PCI_ANY_ID, 0, 0, sil_3114 },
86 { 0x1002, 0x436e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, sil_3112_m15w },
87 { 0x1002, 0x4379, PCI_ANY_ID, PCI_ANY_ID, 0, 0, sil_3112_m15w },
88 { 0x1002, 0x437a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, sil_3112_m15w },
89 { } /* terminate list */
93 /* TODO firmware versions should be added - eric */
94 static const struct sil_drivelist {
97 } sil_blacklist [] = {
98 { "ST320012AS", SIL_QUIRK_MOD15WRITE },
99 { "ST330013AS", SIL_QUIRK_MOD15WRITE },
100 { "ST340017AS", SIL_QUIRK_MOD15WRITE },
101 { "ST360015AS", SIL_QUIRK_MOD15WRITE },
102 { "ST380013AS", SIL_QUIRK_MOD15WRITE },
103 { "ST380023AS", SIL_QUIRK_MOD15WRITE },
104 { "ST3120023AS", SIL_QUIRK_MOD15WRITE },
105 { "ST3160023AS", SIL_QUIRK_MOD15WRITE },
106 { "ST3120026AS", SIL_QUIRK_MOD15WRITE },
107 { "ST3200822AS", SIL_QUIRK_MOD15WRITE },
108 { "ST340014ASL", SIL_QUIRK_MOD15WRITE },
109 { "ST360014ASL", SIL_QUIRK_MOD15WRITE },
110 { "ST380011ASL", SIL_QUIRK_MOD15WRITE },
111 { "ST3120022ASL", SIL_QUIRK_MOD15WRITE },
112 { "ST3160021ASL", SIL_QUIRK_MOD15WRITE },
113 { "Maxtor 4D060H3", SIL_QUIRK_UDMA5MAX },
117 static struct pci_driver sil_pci_driver = {
119 .id_table = sil_pci_tbl,
120 .probe = sil_init_one,
121 .remove = ata_pci_remove_one,
124 static Scsi_Host_Template sil_sht = {
125 .module = THIS_MODULE,
127 .ioctl = ata_scsi_ioctl,
128 .queuecommand = ata_scsi_queuecmd,
129 .eh_strategy_handler = ata_scsi_error,
130 .can_queue = ATA_DEF_QUEUE,
131 .this_id = ATA_SHT_THIS_ID,
132 .sg_tablesize = LIBATA_MAX_PRD,
133 .max_sectors = ATA_MAX_SECTORS,
134 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
135 .emulated = ATA_SHT_EMULATED,
136 .use_clustering = ATA_SHT_USE_CLUSTERING,
137 .proc_name = DRV_NAME,
138 .dma_boundary = ATA_DMA_BOUNDARY,
139 .slave_configure = ata_scsi_slave_config,
140 .bios_param = ata_std_bios_param,
144 static struct ata_port_operations sil_ops = {
145 .port_disable = ata_port_disable,
146 .dev_config = sil_dev_config,
147 .tf_load = ata_tf_load,
148 .tf_read = ata_tf_read,
149 .check_status = ata_check_status,
150 .exec_command = ata_exec_command,
151 .dev_select = ata_std_dev_select,
152 .phy_reset = sata_phy_reset,
153 .post_set_mode = sil_post_set_mode,
154 .bmdma_setup = ata_bmdma_setup,
155 .bmdma_start = ata_bmdma_start,
156 .bmdma_stop = ata_bmdma_stop,
157 .bmdma_status = ata_bmdma_status,
158 .qc_prep = ata_qc_prep,
159 .qc_issue = ata_qc_issue_prot,
160 .eng_timeout = ata_eng_timeout,
161 .irq_handler = ata_interrupt,
162 .irq_clear = ata_bmdma_irq_clear,
163 .scr_read = sil_scr_read,
164 .scr_write = sil_scr_write,
165 .port_start = ata_port_start,
166 .port_stop = ata_port_stop,
167 .host_stop = ata_host_stop,
170 static struct ata_port_info sil_port_info[] = {
174 .host_flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
175 ATA_FLAG_SRST | ATA_FLAG_MMIO,
176 .pio_mask = 0x1f, /* pio0-4 */
177 .mwdma_mask = 0x07, /* mwdma0-2 */
178 .udma_mask = 0x3f, /* udma0-5 */
179 .port_ops = &sil_ops,
180 }, /* sil_3112_15w - keep it sync'd w/ sil_3112 */
183 .host_flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
184 ATA_FLAG_SRST | ATA_FLAG_MMIO |
186 .pio_mask = 0x1f, /* pio0-4 */
187 .mwdma_mask = 0x07, /* mwdma0-2 */
188 .udma_mask = 0x3f, /* udma0-5 */
189 .port_ops = &sil_ops,
193 .host_flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
194 ATA_FLAG_SRST | ATA_FLAG_MMIO,
195 .pio_mask = 0x1f, /* pio0-4 */
196 .mwdma_mask = 0x07, /* mwdma0-2 */
197 .udma_mask = 0x3f, /* udma0-5 */
198 .port_ops = &sil_ops,
202 /* per-port register offsets */
203 /* TODO: we can probably calculate rather than use a table */
204 static const struct {
205 unsigned long tf; /* ATA taskfile register block */
206 unsigned long ctl; /* ATA control/altstatus register block */
207 unsigned long bmdma; /* DMA register block */
208 unsigned long scr; /* SATA control register block */
209 unsigned long sien; /* SATA Interrupt Enable register */
210 unsigned long xfer_mode;/* data transfer mode register */
213 { 0x80, 0x8A, 0x00, 0x100, 0x148, 0xb4 },
214 { 0xC0, 0xCA, 0x08, 0x180, 0x1c8, 0xf4 },
215 { 0x280, 0x28A, 0x200, 0x300, 0x348, 0x2b4 },
216 { 0x2C0, 0x2CA, 0x208, 0x380, 0x3c8, 0x2f4 },
220 MODULE_AUTHOR("Jeff Garzik");
221 MODULE_DESCRIPTION("low-level driver for Silicon Image SATA controller");
222 MODULE_LICENSE("GPL");
223 MODULE_DEVICE_TABLE(pci, sil_pci_tbl);
224 MODULE_VERSION(DRV_VERSION);
226 static unsigned char sil_get_device_cache_line(struct pci_dev *pdev)
229 pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &cache_line);
233 static void sil_post_set_mode (struct ata_port *ap)
235 struct ata_host_set *host_set = ap->host_set;
236 struct ata_device *dev;
237 void *addr = host_set->mmio_base + sil_port[ap->port_no].xfer_mode;
238 u32 tmp, dev_mode[2];
241 for (i = 0; i < 2; i++) {
242 dev = &ap->device[i];
243 if (!ata_dev_present(dev))
244 dev_mode[i] = 0; /* PIO0/1/2 */
245 else if (dev->flags & ATA_DFLAG_PIO)
246 dev_mode[i] = 1; /* PIO3/4 */
248 dev_mode[i] = 3; /* UDMA */
249 /* value 2 indicates MDMA */
253 tmp &= ~((1<<5) | (1<<4) | (1<<1) | (1<<0));
255 tmp |= (dev_mode[1] << 4);
257 readl(addr); /* flush */
260 static inline unsigned long sil_scr_addr(struct ata_port *ap, unsigned int sc_reg)
262 unsigned long offset = ap->ioaddr.scr_addr;
279 static u32 sil_scr_read (struct ata_port *ap, unsigned int sc_reg)
281 void *mmio = (void *) sil_scr_addr(ap, sc_reg);
287 static void sil_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val)
289 void *mmio = (void *) sil_scr_addr(ap, sc_reg);
295 * sil_dev_config - Apply device/host-specific errata fixups
296 * @ap: Port containing device to be examined
297 * @dev: Device to be examined
299 * After the IDENTIFY [PACKET] DEVICE step is complete, and a
300 * device is known to be present, this function is called.
301 * We apply two errata fixups which are specific to Silicon Image,
302 * a Seagate and a Maxtor fixup.
304 * For certain Seagate devices, we must limit the maximum sectors
307 * For certain Maxtor devices, we must not program the drive
310 * Both fixups are unfairly pessimistic. As soon as I get more
311 * information on these errata, I will create a more exhaustive
312 * list, and apply the fixups to only the specific
313 * devices/hosts/firmwares that need it.
315 * 20040111 - Seagate drives affected by the Mod15Write bug are blacklisted
316 * The Maxtor quirk is in the blacklist, but I'm keeping the original
317 * pessimistic fix for the following reasons...
318 * - There seems to be less info on it, only one device gleaned off the
319 * Windows driver, maybe only one is affected. More info would be greatly
321 * - But then again UDMA5 is hardly anything to complain about
323 static void sil_dev_config(struct ata_port *ap, struct ata_device *dev)
325 unsigned int n, quirks = 0;
326 unsigned char model_num[40];
330 ata_dev_id_string(dev->id, model_num, ATA_ID_PROD_OFS,
333 len = strnlen(s, sizeof(model_num));
335 /* ATAPI specifies that empty space is blank-filled; remove blanks */
336 while ((len > 0) && (s[len - 1] == ' '))
339 for (n = 0; sil_blacklist[n].product; n++)
340 if (!memcmp(sil_blacklist[n].product, s,
341 strlen(sil_blacklist[n].product))) {
342 quirks = sil_blacklist[n].quirk;
346 /* limit requests to 15 sectors */
347 if ((ap->flags & SIL_FLAG_MOD15WRITE) && (quirks & SIL_QUIRK_MOD15WRITE)) {
348 printk(KERN_INFO "ata%u(%u): applying Seagate errata fix\n",
350 ap->host->max_sectors = 15;
351 ap->host->hostt->max_sectors = 15;
352 dev->flags |= ATA_DFLAG_LOCK_SECTORS;
357 if (quirks & SIL_QUIRK_UDMA5MAX) {
358 printk(KERN_INFO "ata%u(%u): applying Maxtor errata fix %s\n",
359 ap->id, dev->devno, s);
360 ap->udma_mask &= ATA_UDMA5;
365 static int sil_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
367 static int printed_version;
368 struct ata_probe_ent *probe_ent = NULL;
373 int pci_dev_busy = 0;
377 if (!printed_version++)
378 printk(KERN_DEBUG DRV_NAME " version " DRV_VERSION "\n");
381 * If this driver happens to only be useful on Apple's K2, then
382 * we should check that here as it has a normal Serverworks ID
384 rc = pci_enable_device(pdev);
388 rc = pci_request_regions(pdev, DRV_NAME);
394 rc = pci_set_dma_mask(pdev, ATA_DMA_MASK);
396 goto err_out_regions;
397 rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK);
399 goto err_out_regions;
401 probe_ent = kmalloc(sizeof(*probe_ent), GFP_KERNEL);
402 if (probe_ent == NULL) {
404 goto err_out_regions;
407 memset(probe_ent, 0, sizeof(*probe_ent));
408 INIT_LIST_HEAD(&probe_ent->node);
409 probe_ent->dev = pci_dev_to_dev(pdev);
410 probe_ent->port_ops = sil_port_info[ent->driver_data].port_ops;
411 probe_ent->sht = sil_port_info[ent->driver_data].sht;
412 probe_ent->n_ports = (ent->driver_data == sil_3114) ? 4 : 2;
413 probe_ent->pio_mask = sil_port_info[ent->driver_data].pio_mask;
414 probe_ent->mwdma_mask = sil_port_info[ent->driver_data].mwdma_mask;
415 probe_ent->udma_mask = sil_port_info[ent->driver_data].udma_mask;
416 probe_ent->irq = pdev->irq;
417 probe_ent->irq_flags = SA_SHIRQ;
418 probe_ent->host_flags = sil_port_info[ent->driver_data].host_flags;
420 mmio_base = ioremap(pci_resource_start(pdev, 5),
421 pci_resource_len(pdev, 5));
422 if (mmio_base == NULL) {
424 goto err_out_free_ent;
427 probe_ent->mmio_base = mmio_base;
429 base = (unsigned long) mmio_base;
431 for (i = 0; i < probe_ent->n_ports; i++) {
432 probe_ent->port[i].cmd_addr = base + sil_port[i].tf;
433 probe_ent->port[i].altstatus_addr =
434 probe_ent->port[i].ctl_addr = base + sil_port[i].ctl;
435 probe_ent->port[i].bmdma_addr = base + sil_port[i].bmdma;
436 probe_ent->port[i].scr_addr = base + sil_port[i].scr;
437 ata_std_ports(&probe_ent->port[i]);
440 /* Initialize FIFO PCI bus arbitration */
441 cls = sil_get_device_cache_line(pdev);
444 cls++; /* cls = (line_size/8)+1 */
445 writeb(cls, mmio_base + SIL_FIFO_R0);
446 writeb(cls, mmio_base + SIL_FIFO_W0);
447 writeb(cls, mmio_base + SIL_FIFO_R1);
448 writeb(cls, mmio_base + SIL_FIFO_W1);
449 if (ent->driver_data == sil_3114) {
450 writeb(cls, mmio_base + SIL_FIFO_R2);
451 writeb(cls, mmio_base + SIL_FIFO_W2);
452 writeb(cls, mmio_base + SIL_FIFO_R3);
453 writeb(cls, mmio_base + SIL_FIFO_W3);
456 printk(KERN_WARNING DRV_NAME "(%s): cache line size not set. Driver may not function\n",
459 if (ent->driver_data == sil_3114) {
460 irq_mask = SIL_MASK_4PORT;
462 /* flip the magic "make 4 ports work" bit */
463 tmp = readl(mmio_base + SIL_IDE2_BMDMA);
464 if ((tmp & SIL_INTR_STEERING) == 0)
465 writel(tmp | SIL_INTR_STEERING,
466 mmio_base + SIL_IDE2_BMDMA);
469 irq_mask = SIL_MASK_2PORT;
472 /* make sure IDE0/1/2/3 interrupts are not masked */
473 tmp = readl(mmio_base + SIL_SYSCFG);
474 if (tmp & irq_mask) {
476 writel(tmp, mmio_base + SIL_SYSCFG);
477 readl(mmio_base + SIL_SYSCFG); /* flush */
480 /* mask all SATA phy-related interrupts */
481 /* TODO: unmask bit 6 (SError N bit) for hotplug */
482 for (i = 0; i < probe_ent->n_ports; i++)
483 writel(0, mmio_base + sil_port[i].sien);
485 pci_set_master(pdev);
487 /* FIXME: check ata_device_add return value */
488 ata_device_add(probe_ent);
496 pci_release_regions(pdev);
499 pci_disable_device(pdev);
503 static int __init sil_init(void)
505 return pci_module_init(&sil_pci_driver);
508 static void __exit sil_exit(void)
510 pci_unregister_driver(&sil_pci_driver);
514 module_init(sil_init);
515 module_exit(sil_exit);