drivers/scsi/sata_sx4.c

   1 /*
   2  *  sata_sx4.c - Promise SATA
   3  *
   4  *  Maintained by:  Jeff Garzik <jgarzik@pobox.com>
   5  *                  Please ALWAYS copy linux-ide@vger.kernel.org
   6  *                  on emails.
   7  *
   8  *  Copyright 2003-2004 Red Hat, Inc.
   9  *
  10  *
  11  *  This program is free software; you can redistribute it and/or modify
  12  *  it under the terms of the GNU General Public License as published by
  13  *  the Free Software Foundation; either version 2, or (at your option)
  14  *  any later version.
  15  *
  16  *  This program is distributed in the hope that it will be useful,
  17  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19  *  GNU General Public License for more details.
  20  *
  21  *  You should have received a copy of the GNU General Public License
  22  *  along with this program; see the file COPYING.  If not, write to
  23  *  the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
  24  *
  25  *
  26  *  libata documentation is available via 'make {ps|pdf}docs',
  27  *  as Documentation/DocBook/libata.*
  28  *
  29  *  Hardware documentation available under NDA.
  30  *
  31  */
  32
  33 #include <linux/kernel.h>
  34 #include <linux/module.h>
  35 #include <linux/pci.h>
  36 #include <linux/init.h>
  37 #include <linux/blkdev.h>
  38 #include <linux/delay.h>
  39 #include <linux/interrupt.h>
  40 #include <linux/sched.h>
  41 #include <linux/device.h>
  42 #include <scsi/scsi_host.h>
  43 #include <scsi/scsi_cmnd.h>
  44 #include <linux/libata.h>
  45 #include <asm/io.h>
  46 #include "sata_promise.h"
  47
  48 #define DRV_NAME        "sata_sx4"
  49 #define DRV_VERSION     "0.8"
  50
  51
  52 enum {
  53         PDC_PRD_TBL             = 0x44, /* Direct command DMA table addr */
  54
  55         PDC_PKT_SUBMIT          = 0x40, /* Command packet pointer addr */
  56         PDC_HDMA_PKT_SUBMIT     = 0x100, /* Host DMA packet pointer addr */
  57         PDC_INT_SEQMASK         = 0x40, /* Mask of asserted SEQ INTs */
  58         PDC_HDMA_CTLSTAT        = 0x12C, /* Host DMA control / status */
  59
  60         PDC_20621_SEQCTL        = 0x400,
  61         PDC_20621_SEQMASK       = 0x480,
  62         PDC_20621_GENERAL_CTL   = 0x484,
  63         PDC_20621_PAGE_SIZE     = (32 * 1024),
  64
  65         /* chosen, not constant, values; we design our own DIMM mem map */
  66         PDC_20621_DIMM_WINDOW   = 0x0C, /* page# for 32K DIMM window */
  67         PDC_20621_DIMM_BASE     = 0x00200000,
  68         PDC_20621_DIMM_DATA     = (64 * 1024),
  69         PDC_DIMM_DATA_STEP      = (256 * 1024),
  70         PDC_DIMM_WINDOW_STEP    = (8 * 1024),
  71         PDC_DIMM_HOST_PRD       = (6 * 1024),
  72         PDC_DIMM_HOST_PKT       = (128 * 0),
  73         PDC_DIMM_HPKT_PRD       = (128 * 1),
  74         PDC_DIMM_ATA_PKT        = (128 * 2),
  75         PDC_DIMM_APKT_PRD       = (128 * 3),
  76         PDC_DIMM_HEADER_SZ      = PDC_DIMM_APKT_PRD + 128,
  77         PDC_PAGE_WINDOW         = 0x40,
  78         PDC_PAGE_DATA           = PDC_PAGE_WINDOW +
  79                                   (PDC_20621_DIMM_DATA / PDC_20621_PAGE_SIZE),
  80         PDC_PAGE_SET            = PDC_DIMM_DATA_STEP / PDC_20621_PAGE_SIZE,
  81
  82         PDC_CHIP0_OFS           = 0xC0000, /* offset of chip #0 */
  83
  84         PDC_20621_ERR_MASK      = (1<<19) | (1<<20) | (1<<21) | (1<<22) |
  85                                   (1<<23),
  86
  87         board_20621             = 0,    /* FastTrak S150 SX4 */
  88
  89         PDC_RESET               = (1 << 11), /* HDMA reset */
  90
  91         PDC_MAX_HDMA            = 32,
  92         PDC_HDMA_Q_MASK         = (PDC_MAX_HDMA - 1),
  93
  94         PDC_DIMM0_SPD_DEV_ADDRESS     = 0x50,
  95         PDC_DIMM1_SPD_DEV_ADDRESS     = 0x51,
  96         PDC_MAX_DIMM_MODULE           = 0x02,
  97         PDC_I2C_CONTROL_OFFSET        = 0x48,
  98         PDC_I2C_ADDR_DATA_OFFSET      = 0x4C,
  99         PDC_DIMM0_CONTROL_OFFSET      = 0x80,
 100         PDC_DIMM1_CONTROL_OFFSET      = 0x84,
 101         PDC_SDRAM_CONTROL_OFFSET      = 0x88,
 102         PDC_I2C_WRITE                 = 0x00000000,
 103         PDC_I2C_READ                  = 0x00000040,
 104         PDC_I2C_START                 = 0x00000080,
 105         PDC_I2C_MASK_INT              = 0x00000020,
 106         PDC_I2C_COMPLETE              = 0x00010000,
 107         PDC_I2C_NO_ACK                = 0x00100000,
 108         PDC_DIMM_SPD_SUBADDRESS_START = 0x00,
 109         PDC_DIMM_SPD_SUBADDRESS_END   = 0x7F,
 110         PDC_DIMM_SPD_ROW_NUM          = 3,
 111         PDC_DIMM_SPD_COLUMN_NUM       = 4,
 112         PDC_DIMM_SPD_MODULE_ROW       = 5,
 113         PDC_DIMM_SPD_TYPE             = 11,
 114         PDC_DIMM_SPD_FRESH_RATE       = 12,
 115         PDC_DIMM_SPD_BANK_NUM         = 17,
 116         PDC_DIMM_SPD_CAS_LATENCY      = 18,
 117         PDC_DIMM_SPD_ATTRIBUTE        = 21,
 118         PDC_DIMM_SPD_ROW_PRE_CHARGE   = 27,
 119         PDC_DIMM_SPD_ROW_ACTIVE_DELAY = 28,
 120         PDC_DIMM_SPD_RAS_CAS_DELAY    = 29,
 121         PDC_DIMM_SPD_ACTIVE_PRECHARGE = 30,
 122         PDC_DIMM_SPD_SYSTEM_FREQ      = 126,
 123         PDC_CTL_STATUS                = 0x08,
 124         PDC_DIMM_WINDOW_CTLR          = 0x0C,
 125         PDC_TIME_CONTROL              = 0x3C,
 126         PDC_TIME_PERIOD               = 0x40,
 127         PDC_TIME_COUNTER              = 0x44,
 128         PDC_GENERAL_CTLR              = 0x484,
 129         PCI_PLL_INIT                  = 0x8A531824,
 130         PCI_X_TCOUNT                  = 0xEE1E5CFF
 131 };
 132
 133
 134 struct pdc_port_priv {
 135         u8                      dimm_buf[(ATA_PRD_SZ * ATA_MAX_PRD) + 512];
 136         u8                      *pkt;
 137         dma_addr_t              pkt_dma;
 138 };
 139
 140 struct pdc_host_priv {
 141         void                    __iomem *dimm_mmio;
 142
 143         unsigned int            doing_hdma;
 144         unsigned int            hdma_prod;
 145         unsigned int            hdma_cons;
 146         struct {
 147                 struct ata_queued_cmd *qc;
 148                 unsigned int    seq;
 149                 unsigned long   pkt_ofs;
 150         } hdma[32];
 151 };
 152
 153
 154 static int pdc_sata_init_one (struct pci_dev *pdev, const struct pci_device_id *ent);
 155 static irqreturn_t pdc20621_interrupt (int irq, void *dev_instance, struct pt_regs *regs);
 156 static void pdc_eng_timeout(struct ata_port *ap);
 157 static void pdc_20621_phy_reset (struct ata_port *ap);
 158 static int pdc_port_start(struct ata_port *ap);
 159 static void pdc_port_stop(struct ata_port *ap);
 160 static void pdc20621_qc_prep(struct ata_queued_cmd *qc);
 161 static void pdc_tf_load_mmio(struct ata_port *ap, const struct ata_taskfile *tf);
 162 static void pdc_exec_command_mmio(struct ata_port *ap, const struct ata_taskfile *tf);
 163 static void pdc20621_host_stop(struct ata_host_set *host_set);
 164 static unsigned int pdc20621_dimm_init(struct ata_probe_ent *pe);
 165 static int pdc20621_detect_dimm(struct ata_probe_ent *pe);
 166 static unsigned int pdc20621_i2c_read(struct ata_probe_ent *pe,
 167                                       u32 device, u32 subaddr, u32 *pdata);
 168 static int pdc20621_prog_dimm0(struct ata_probe_ent *pe);
 169 static unsigned int pdc20621_prog_dimm_global(struct ata_probe_ent *pe);
 170 #ifdef ATA_VERBOSE_DEBUG
 171 static void pdc20621_get_from_dimm(struct ata_probe_ent *pe,
 172                                    void *psource, u32 offset, u32 size);
 173 #endif
 174 static void pdc20621_put_to_dimm(struct ata_probe_ent *pe,
 175                                  void *psource, u32 offset, u32 size);
 176 static void pdc20621_irq_clear(struct ata_port *ap);
 177 static unsigned int pdc20621_qc_issue_prot(struct ata_queued_cmd *qc);
 178
 179
 180 static struct scsi_host_template pdc_sata_sht = {
 181         .module                 = THIS_MODULE,
 182         .name                   = DRV_NAME,
 183         .ioctl                  = ata_scsi_ioctl,
 184         .queuecommand           = ata_scsi_queuecmd,
 185         .eh_strategy_handler    = ata_scsi_error,
 186         .can_queue              = ATA_DEF_QUEUE,
 187         .this_id                = ATA_SHT_THIS_ID,
 188         .sg_tablesize           = LIBATA_MAX_PRD,
 189         .max_sectors            = ATA_MAX_SECTORS,
 190         .cmd_per_lun            = ATA_SHT_CMD_PER_LUN,
 191         .emulated               = ATA_SHT_EMULATED,
 192         .use_clustering         = ATA_SHT_USE_CLUSTERING,
 193         .proc_name              = DRV_NAME,
 194         .dma_boundary           = ATA_DMA_BOUNDARY,
 195         .slave_configure        = ata_scsi_slave_config,
 196         .bios_param             = ata_std_bios_param,
 197 };
 198
 199 static const struct ata_port_operations pdc_20621_ops = {
 200         .port_disable           = ata_port_disable,
 201         .tf_load                = pdc_tf_load_mmio,
 202         .tf_read                = ata_tf_read,
 203         .check_status           = ata_check_status,
 204         .exec_command           = pdc_exec_command_mmio,
 205         .dev_select             = ata_std_dev_select,
 206         .phy_reset              = pdc_20621_phy_reset,
 207         .qc_prep                = pdc20621_qc_prep,
 208         .qc_issue               = pdc20621_qc_issue_prot,
 209         .eng_timeout            = pdc_eng_timeout,
 210         .irq_handler            = pdc20621_interrupt,
 211         .irq_clear              = pdc20621_irq_clear,
 212         .port_start             = pdc_port_start,
 213         .port_stop              = pdc_port_stop,
 214         .host_stop              = pdc20621_host_stop,
 215 };
 216
 217 static const struct ata_port_info pdc_port_info[] = {
 218         /* board_20621 */
 219         {
 220                 .sht            = &pdc_sata_sht,
 221                 .host_flags     = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
 222                                   ATA_FLAG_SRST | ATA_FLAG_MMIO |
 223                                   ATA_FLAG_NO_ATAPI,
 224                 .pio_mask       = 0x1f, /* pio0-4 */
 225                 .mwdma_mask     = 0x07, /* mwdma0-2 */
 226                 .udma_mask      = 0x7f, /* udma0-6 ; FIXME */
 227                 .port_ops       = &pdc_20621_ops,
 228         },
 229
 230 };
 231
 232 static const struct pci_device_id pdc_sata_pci_tbl[] = {
 233         { PCI_VENDOR_ID_PROMISE, 0x6622, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
 234           board_20621 },
 235         { }     /* terminate list */
 236 };
 237
 238
 239 static struct pci_driver pdc_sata_pci_driver = {
 240         .name                   = DRV_NAME,
 241         .id_table               = pdc_sata_pci_tbl,
 242         .probe                  = pdc_sata_init_one,
 243         .remove                 = ata_pci_remove_one,
 244 };
 245
 246
 247 static void pdc20621_host_stop(struct ata_host_set *host_set)
 248 {
 249         struct pci_dev *pdev = to_pci_dev(host_set->dev);
 250         struct pdc_host_priv *hpriv = host_set->private_data;
 251         void __iomem *dimm_mmio = hpriv->dimm_mmio;
 252
 253         pci_iounmap(pdev, dimm_mmio);
 254         kfree(hpriv);
 255
 256         pci_iounmap(pdev, host_set->mmio_base);
 257 }
 258
 259 static int pdc_port_start(struct ata_port *ap)
 260 {
 261         struct device *dev = ap->host_set->dev;
 262         struct pdc_port_priv *pp;
 263         int rc;
 264
 265         rc = ata_port_start(ap);
 266         if (rc)
 267                 return rc;
 268
 269         pp = kmalloc(sizeof(*pp), GFP_KERNEL);
 270         if (!pp) {
 271                 rc = -ENOMEM;
 272                 goto err_out;
 273         }
 274         memset(pp, 0, sizeof(*pp));
 275
 276         pp->pkt = dma_alloc_coherent(dev, 128, &pp->pkt_dma, GFP_KERNEL);
 277         if (!pp->pkt) {
 278                 rc = -ENOMEM;
 279                 goto err_out_kfree;
 280         }
 281
 282         ap->private_data = pp;
 283
 284         return 0;
 285
 286 err_out_kfree:
 287         kfree(pp);
 288 err_out:
 289         ata_port_stop(ap);
 290         return rc;
 291 }
 292
 293
 294 static void pdc_port_stop(struct ata_port *ap)
 295 {
 296         struct device *dev = ap->host_set->dev;
 297         struct pdc_port_priv *pp = ap->private_data;
 298
 299         ap->private_data = NULL;
 300         dma_free_coherent(dev, 128, pp->pkt, pp->pkt_dma);
 301         kfree(pp);
 302         ata_port_stop(ap);
 303 }
 304
 305
 306 static void pdc_20621_phy_reset (struct ata_port *ap)
 307 {
 308         VPRINTK("ENTER\n");
 309         ap->cbl = ATA_CBL_SATA;
 310         ata_port_probe(ap);
 311         ata_bus_reset(ap);
 312 }
 313
 314 static inline void pdc20621_ata_sg(struct ata_taskfile *tf, u8 *buf,
 315                                            unsigned int portno,
 316                                            unsigned int total_len)
 317 {
 318         u32 addr;
 319         unsigned int dw = PDC_DIMM_APKT_PRD >> 2;
 320         u32 *buf32 = (u32 *) buf;
 321
 322         /* output ATA packet S/G table */
 323         addr = PDC_20621_DIMM_BASE + PDC_20621_DIMM_DATA +
 324                (PDC_DIMM_DATA_STEP * portno);
 325         VPRINTK("ATA sg addr 0x%x, %d\n", addr, addr);
 326         buf32[dw] = cpu_to_le32(addr);
 327         buf32[dw + 1] = cpu_to_le32(total_len | ATA_PRD_EOT);
 328
 329         VPRINTK("ATA PSG @ %x == (0x%x, 0x%x)\n",
 330                 PDC_20621_DIMM_BASE +
 331                        (PDC_DIMM_WINDOW_STEP * portno) +
 332                        PDC_DIMM_APKT_PRD,
 333                 buf32[dw], buf32[dw + 1]);
 334 }
 335
 336 static inline void pdc20621_host_sg(struct ata_taskfile *tf, u8 *buf,
 337                                             unsigned int portno,
 338                                             unsigned int total_len)
 339 {
 340         u32 addr;
 341         unsigned int dw = PDC_DIMM_HPKT_PRD >> 2;
 342         u32 *buf32 = (u32 *) buf;
 343
 344         /* output Host DMA packet S/G table */
 345         addr = PDC_20621_DIMM_BASE + PDC_20621_DIMM_DATA +
 346                (PDC_DIMM_DATA_STEP * portno);
 347
 348         buf32[dw] = cpu_to_le32(addr);
 349         buf32[dw + 1] = cpu_to_le32(total_len | ATA_PRD_EOT);
 350
 351         VPRINTK("HOST PSG @ %x == (0x%x, 0x%x)\n",
 352                 PDC_20621_DIMM_BASE +
 353                        (PDC_DIMM_WINDOW_STEP * portno) +
 354                        PDC_DIMM_HPKT_PRD,
 355                 buf32[dw], buf32[dw + 1]);
 356 }
 357
 358 static inline unsigned int pdc20621_ata_pkt(struct ata_taskfile *tf,
 359                                             unsigned int devno, u8 *buf,
 360                                             unsigned int portno)
 361 {
 362         unsigned int i, dw;
 363         u32 *buf32 = (u32 *) buf;
 364         u8 dev_reg;
 365
 366         unsigned int dimm_sg = PDC_20621_DIMM_BASE +
 367                                (PDC_DIMM_WINDOW_STEP * portno) +
 368                                PDC_DIMM_APKT_PRD;
 369         VPRINTK("ENTER, dimm_sg == 0x%x, %d\n", dimm_sg, dimm_sg);
 370
 371         i = PDC_DIMM_ATA_PKT;
 372
 373         /*
 374          * Set up ATA packet
 375          */
 376         if ((tf->protocol == ATA_PROT_DMA) && (!(tf->flags & ATA_TFLAG_WRITE)))
 377                 buf[i++] = PDC_PKT_READ;
 378         else if (tf->protocol == ATA_PROT_NODATA)
 379                 buf[i++] = PDC_PKT_NODATA;
 380         else
 381                 buf[i++] = 0;
 382         buf[i++] = 0;                   /* reserved */
 383         buf[i++] = portno + 1;          /* seq. id */
 384         buf[i++] = 0xff;                /* delay seq. id */
 385
 386         /* dimm dma S/G, and next-pkt */
 387         dw = i >> 2;
 388         if (tf->protocol == ATA_PROT_NODATA)
 389                 buf32[dw] = 0;
 390         else
 391                 buf32[dw] = cpu_to_le32(dimm_sg);
 392         buf32[dw + 1] = 0;
 393         i += 8;
 394
 395         if (devno == 0)
 396                 dev_reg = ATA_DEVICE_OBS;
 397         else
 398                 dev_reg = ATA_DEVICE_OBS | ATA_DEV1;
 399
 400         /* select device */
 401         buf[i++] = (1 << 5) | PDC_PKT_CLEAR_BSY | ATA_REG_DEVICE;
 402         buf[i++] = dev_reg;
 403
 404         /* device control register */
 405         buf[i++] = (1 << 5) | PDC_REG_DEVCTL;
 406         buf[i++] = tf->ctl;
 407
 408         return i;
 409 }
 410
 411 static inline void pdc20621_host_pkt(struct ata_taskfile *tf, u8 *buf,
 412                                      unsigned int portno)
 413 {
 414         unsigned int dw;
 415         u32 tmp, *buf32 = (u32 *) buf;
 416
 417         unsigned int host_sg = PDC_20621_DIMM_BASE +
 418                                (PDC_DIMM_WINDOW_STEP * portno) +
 419                                PDC_DIMM_HOST_PRD;
 420         unsigned int dimm_sg = PDC_20621_DIMM_BASE +
 421                                (PDC_DIMM_WINDOW_STEP * portno) +
 422                                PDC_DIMM_HPKT_PRD;
 423         VPRINTK("ENTER, dimm_sg == 0x%x, %d\n", dimm_sg, dimm_sg);
 424         VPRINTK("host_sg == 0x%x, %d\n", host_sg, host_sg);
 425
 426         dw = PDC_DIMM_HOST_PKT >> 2;
 427
 428         /*
 429          * Set up Host DMA packet
 430          */
 431         if ((tf->protocol == ATA_PROT_DMA) && (!(tf->flags & ATA_TFLAG_WRITE)))
 432                 tmp = PDC_PKT_READ;
 433         else
 434                 tmp = 0;
 435         tmp |= ((portno + 1 + 4) << 16);        /* seq. id */
 436         tmp |= (0xff << 24);                    /* delay seq. id */
 437         buf32[dw + 0] = cpu_to_le32(tmp);
 438         buf32[dw + 1] = cpu_to_le32(host_sg);
 439         buf32[dw + 2] = cpu_to_le32(dimm_sg);
 440         buf32[dw + 3] = 0;
 441
 442         VPRINTK("HOST PKT @ %x == (0x%x 0x%x 0x%x 0x%x)\n",
 443                 PDC_20621_DIMM_BASE + (PDC_DIMM_WINDOW_STEP * portno) +
 444                         PDC_DIMM_HOST_PKT,
 445                 buf32[dw + 0],
 446                 buf32[dw + 1],
 447                 buf32[dw + 2],
 448                 buf32[dw + 3]);
 449 }
 450
 451 static void pdc20621_dma_prep(struct ata_queued_cmd *qc)
 452 {
 453         struct scatterlist *sg;
 454         struct ata_port *ap = qc->ap;
 455         struct pdc_port_priv *pp = ap->private_data;
 456         void __iomem *mmio = ap->host_set->mmio_base;
 457         struct pdc_host_priv *hpriv = ap->host_set->private_data;
 458         void __iomem *dimm_mmio = hpriv->dimm_mmio;
 459         unsigned int portno = ap->port_no;
 460         unsigned int i, idx, total_len = 0, sgt_len;
 461         u32 *buf = (u32 *) &pp->dimm_buf[PDC_DIMM_HEADER_SZ];
 462
 463         assert(qc->flags & ATA_QCFLAG_DMAMAP);
 464
 465         VPRINTK("ata%u: ENTER\n", ap->id);
 466
 467         /* hard-code chip #0 */
 468         mmio += PDC_CHIP0_OFS;
 469
 470         /*
 471          * Build S/G table
 472          */
 473         idx = 0;
 474         ata_for_each_sg(sg, qc) {
 475                 buf[idx++] = cpu_to_le32(sg_dma_address(sg));
 476                 buf[idx++] = cpu_to_le32(sg_dma_len(sg));
 477                 total_len += sg_dma_len(sg);
 478         }
 479         buf[idx - 1] |= cpu_to_le32(ATA_PRD_EOT);
 480         sgt_len = idx * 4;
 481
 482         /*
 483          * Build ATA, host DMA packets
 484          */
 485         pdc20621_host_sg(&qc->tf, &pp->dimm_buf[0], portno, total_len);
 486         pdc20621_host_pkt(&qc->tf, &pp->dimm_buf[0], portno);
 487
 488         pdc20621_ata_sg(&qc->tf, &pp->dimm_buf[0], portno, total_len);
 489         i = pdc20621_ata_pkt(&qc->tf, qc->dev->devno, &pp->dimm_buf[0], portno);
 490
 491         if (qc->tf.flags & ATA_TFLAG_LBA48)
 492                 i = pdc_prep_lba48(&qc->tf, &pp->dimm_buf[0], i);
 493         else
 494                 i = pdc_prep_lba28(&qc->tf, &pp->dimm_buf[0], i);
 495
 496         pdc_pkt_footer(&qc->tf, &pp->dimm_buf[0], i);
 497
 498         /* copy three S/G tables and two packets to DIMM MMIO window */
 499         memcpy_toio(dimm_mmio + (portno * PDC_DIMM_WINDOW_STEP),
 500                     &pp->dimm_buf, PDC_DIMM_HEADER_SZ);
 501         memcpy_toio(dimm_mmio + (portno * PDC_DIMM_WINDOW_STEP) +
 502                     PDC_DIMM_HOST_PRD,
 503                     &pp->dimm_buf[PDC_DIMM_HEADER_SZ], sgt_len);
 504
 505         /* force host FIFO dump */
 506         writel(0x00000001, mmio + PDC_20621_GENERAL_CTL);
 507
 508         readl(dimm_mmio);       /* MMIO PCI posting flush */
 509
 510         VPRINTK("ata pkt buf ofs %u, prd size %u, mmio copied\n", i, sgt_len);
 511 }
 512
 513 static void pdc20621_nodata_prep(struct ata_queued_cmd *qc)
 514 {
 515         struct ata_port *ap = qc->ap;
 516         struct pdc_port_priv *pp = ap->private_data;
 517         void __iomem *mmio = ap->host_set->mmio_base;
 518         struct pdc_host_priv *hpriv = ap->host_set->private_data;
 519         void __iomem *dimm_mmio = hpriv->dimm_mmio;
 520         unsigned int portno = ap->port_no;
 521         unsigned int i;
 522
 523         VPRINTK("ata%u: ENTER\n", ap->id);
 524
 525         /* hard-code chip #0 */
 526         mmio += PDC_CHIP0_OFS;
 527
 528         i = pdc20621_ata_pkt(&qc->tf, qc->dev->devno, &pp->dimm_buf[0], portno);
 529
 530         if (qc->tf.flags & ATA_TFLAG_LBA48)
 531                 i = pdc_prep_lba48(&qc->tf, &pp->dimm_buf[0], i);
 532         else
 533                 i = pdc_prep_lba28(&qc->tf, &pp->dimm_buf[0], i);
 534
 535         pdc_pkt_footer(&qc->tf, &pp->dimm_buf[0], i);
 536
 537         /* copy three S/G tables and two packets to DIMM MMIO window */
 538         memcpy_toio(dimm_mmio + (portno * PDC_DIMM_WINDOW_STEP),
 539                     &pp->dimm_buf, PDC_DIMM_HEADER_SZ);
 540
 541         /* force host FIFO dump */
 542         writel(0x00000001, mmio + PDC_20621_GENERAL_CTL);
 543
 544         readl(dimm_mmio);       /* MMIO PCI posting flush */
 545
 546         VPRINTK("ata pkt buf ofs %u, mmio copied\n", i);
 547 }
 548
 549 static void pdc20621_qc_prep(struct ata_queued_cmd *qc)
 550 {
 551         switch (qc->tf.protocol) {
 552         case ATA_PROT_DMA:
 553                 pdc20621_dma_prep(qc);
 554                 break;
 555         case ATA_PROT_NODATA:
 556                 pdc20621_nodata_prep(qc);
 557                 break;
 558         default:
 559                 break;
 560         }
 561 }
 562
 563 static void __pdc20621_push_hdma(struct ata_queued_cmd *qc,
 564                                  unsigned int seq,
 565                                  u32 pkt_ofs)
 566 {
 567         struct ata_port *ap = qc->ap;
 568         struct ata_host_set *host_set = ap->host_set;
 569         void __iomem *mmio = host_set->mmio_base;
 570
 571         /* hard-code chip #0 */
 572         mmio += PDC_CHIP0_OFS;
 573
 574         writel(0x00000001, mmio + PDC_20621_SEQCTL + (seq * 4));
 575         readl(mmio + PDC_20621_SEQCTL + (seq * 4));     /* flush */
 576
 577         writel(pkt_ofs, mmio + PDC_HDMA_PKT_SUBMIT);
 578         readl(mmio + PDC_HDMA_PKT_SUBMIT);      /* flush */
 579 }
 580
 581 static void pdc20621_push_hdma(struct ata_queued_cmd *qc,
 582                                 unsigned int seq,
 583                                 u32 pkt_ofs)
 584 {
 585         struct ata_port *ap = qc->ap;
 586         struct pdc_host_priv *pp = ap->host_set->private_data;
 587         unsigned int idx = pp->hdma_prod & PDC_HDMA_Q_MASK;
 588
 589         if (!pp->doing_hdma) {
 590                 __pdc20621_push_hdma(qc, seq, pkt_ofs);
 591                 pp->doing_hdma = 1;
 592                 return;
 593         }
 594
 595         pp->hdma[idx].qc = qc;
 596         pp->hdma[idx].seq = seq;
 597         pp->hdma[idx].pkt_ofs = pkt_ofs;
 598         pp->hdma_prod++;
 599 }
 600
 601 static void pdc20621_pop_hdma(struct ata_queued_cmd *qc)
 602 {
 603         struct ata_port *ap = qc->ap;
 604         struct pdc_host_priv *pp = ap->host_set->private_data;
 605         unsigned int idx = pp->hdma_cons & PDC_HDMA_Q_MASK;
 606
 607         /* if nothing on queue, we're done */
 608         if (pp->hdma_prod == pp->hdma_cons) {
 609                 pp->doing_hdma = 0;
 610                 return;
 611         }
 612
 613         __pdc20621_push_hdma(pp->hdma[idx].qc, pp->hdma[idx].seq,
 614                              pp->hdma[idx].pkt_ofs);
 615         pp->hdma_cons++;
 616 }
 617
 618 #ifdef ATA_VERBOSE_DEBUG
 619 static void pdc20621_dump_hdma(struct ata_queued_cmd *qc)
 620 {
 621         struct ata_port *ap = qc->ap;
 622         unsigned int port_no = ap->port_no;
 623         struct pdc_host_priv *hpriv = ap->host_set->private_data;
 624         void *dimm_mmio = hpriv->dimm_mmio;
 625
 626         dimm_mmio += (port_no * PDC_DIMM_WINDOW_STEP);
 627         dimm_mmio += PDC_DIMM_HOST_PKT;
 628
 629         printk(KERN_ERR "HDMA[0] == 0x%08X\n", readl(dimm_mmio));
 630         printk(KERN_ERR "HDMA[1] == 0x%08X\n", readl(dimm_mmio + 4));
 631         printk(KERN_ERR "HDMA[2] == 0x%08X\n", readl(dimm_mmio + 8));
 632         printk(KERN_ERR "HDMA[3] == 0x%08X\n", readl(dimm_mmio + 12));
 633 }
 634 #else
 635 static inline void pdc20621_dump_hdma(struct ata_queued_cmd *qc) { }
 636 #endif /* ATA_VERBOSE_DEBUG */
 637
 638 static void pdc20621_packet_start(struct ata_queued_cmd *qc)
 639 {
 640         struct ata_port *ap = qc->ap;
 641         struct ata_host_set *host_set = ap->host_set;
 642         unsigned int port_no = ap->port_no;
 643         void __iomem *mmio = host_set->mmio_base;
 644         unsigned int rw = (qc->tf.flags & ATA_TFLAG_WRITE);
 645         u8 seq = (u8) (port_no + 1);
 646         unsigned int port_ofs;
 647
 648         /* hard-code chip #0 */
 649         mmio += PDC_CHIP0_OFS;
 650
 651         VPRINTK("ata%u: ENTER\n", ap->id);
 652
 653         wmb();                  /* flush PRD, pkt writes */
 654
 655         port_ofs = PDC_20621_DIMM_BASE + (PDC_DIMM_WINDOW_STEP * port_no);
 656
 657         /* if writing, we (1) DMA to DIMM, then (2) do ATA command */
 658         if (rw && qc->tf.protocol == ATA_PROT_DMA) {
 659                 seq += 4;
 660
 661                 pdc20621_dump_hdma(qc);
 662                 pdc20621_push_hdma(qc, seq, port_ofs + PDC_DIMM_HOST_PKT);
 663                 VPRINTK("queued ofs 0x%x (%u), seq %u\n",
 664                         port_ofs + PDC_DIMM_HOST_PKT,
 665                         port_ofs + PDC_DIMM_HOST_PKT,
 666                         seq);
 667         } else {
 668                 writel(0x00000001, mmio + PDC_20621_SEQCTL + (seq * 4));
 669                 readl(mmio + PDC_20621_SEQCTL + (seq * 4));     /* flush */
 670
 671                 writel(port_ofs + PDC_DIMM_ATA_PKT,
 672                        (void __iomem *) ap->ioaddr.cmd_addr + PDC_PKT_SUBMIT);
 673                 readl((void __iomem *) ap->ioaddr.cmd_addr + PDC_PKT_SUBMIT);
 674                 VPRINTK("submitted ofs 0x%x (%u), seq %u\n",
 675                         port_ofs + PDC_DIMM_ATA_PKT,
 676                         port_ofs + PDC_DIMM_ATA_PKT,
 677                         seq);
 678         }
 679 }
 680
 681 static unsigned int pdc20621_qc_issue_prot(struct ata_queued_cmd *qc)
 682 {
 683         switch (qc->tf.protocol) {
 684         case ATA_PROT_DMA:
 685         case ATA_PROT_NODATA:
 686                 pdc20621_packet_start(qc);
 687                 return 0;
 688
 689         case ATA_PROT_ATAPI_DMA:
 690                 BUG();
 691                 break;
 692
 693         default:
 694                 break;
 695         }
 696
 697         return ata_qc_issue_prot(qc);
 698 }
 699
 700 static inline unsigned int pdc20621_host_intr( struct ata_port *ap,
 701                                           struct ata_queued_cmd *qc,
 702                                           unsigned int doing_hdma,
 703                                           void __iomem *mmio)
 704 {
 705         unsigned int port_no = ap->port_no;
 706         unsigned int port_ofs =
 707                 PDC_20621_DIMM_BASE + (PDC_DIMM_WINDOW_STEP * port_no);
 708         u8 status;
 709         unsigned int handled = 0;
 710
 711         VPRINTK("ENTER\n");
 712
 713         if ((qc->tf.protocol == ATA_PROT_DMA) &&        /* read */
 714             (!(qc->tf.flags & ATA_TFLAG_WRITE))) {
 715
 716                 /* step two - DMA from DIMM to host */
 717                 if (doing_hdma) {
 718                         VPRINTK("ata%u: read hdma, 0x%x 0x%x\n", ap->id,
 719                                 readl(mmio + 0x104), readl(mmio + PDC_HDMA_CTLSTAT));
 720                         /* get drive status; clear intr; complete txn */
 721                         qc->err_mask |= ac_err_mask(ata_wait_idle(ap));
 722                         ata_qc_complete(qc);
 723                         pdc20621_pop_hdma(qc);
 724                 }
 725
 726                 /* step one - exec ATA command */
 727                 else {
 728                         u8 seq = (u8) (port_no + 1 + 4);
 729                         VPRINTK("ata%u: read ata, 0x%x 0x%x\n", ap->id,
 730                                 readl(mmio + 0x104), readl(mmio + PDC_HDMA_CTLSTAT));
 731
 732                         /* submit hdma pkt */
 733                         pdc20621_dump_hdma(qc);
 734                         pdc20621_push_hdma(qc, seq,
 735                                            port_ofs + PDC_DIMM_HOST_PKT);
 736                 }
 737                 handled = 1;
 738
 739         } else if (qc->tf.protocol == ATA_PROT_DMA) {   /* write */
 740
 741                 /* step one - DMA from host to DIMM */
 742                 if (doing_hdma) {
 743                         u8 seq = (u8) (port_no + 1);
 744                         VPRINTK("ata%u: write hdma, 0x%x 0x%x\n", ap->id,
 745                                 readl(mmio + 0x104), readl(mmio + PDC_HDMA_CTLSTAT));
 746
 747                         /* submit ata pkt */
 748                         writel(0x00000001, mmio + PDC_20621_SEQCTL + (seq * 4));
 749                         readl(mmio + PDC_20621_SEQCTL + (seq * 4));
 750                         writel(port_ofs + PDC_DIMM_ATA_PKT,
 751                                (void __iomem *) ap->ioaddr.cmd_addr + PDC_PKT_SUBMIT);
 752                         readl((void __iomem *) ap->ioaddr.cmd_addr + PDC_PKT_SUBMIT);
 753                 }
 754
 755                 /* step two - execute ATA command */
 756                 else {
 757                         VPRINTK("ata%u: write ata, 0x%x 0x%x\n", ap->id,
 758                                 readl(mmio + 0x104), readl(mmio + PDC_HDMA_CTLSTAT));
 759                         /* get drive status; clear intr; complete txn */
 760                         qc->err_mask |= ac_err_mask(ata_wait_idle(ap));
 761                         ata_qc_complete(qc);
 762                         pdc20621_pop_hdma(qc);
 763                 }
 764                 handled = 1;
 765
 766         /* command completion, but no data xfer */
 767         } else if (qc->tf.protocol == ATA_PROT_NODATA) {
 768
 769                 status = ata_busy_wait(ap, ATA_BUSY | ATA_DRQ, 1000);
 770                 DPRINTK("BUS_NODATA (drv_stat 0x%X)\n", status);
 771                 qc->err_mask |= ac_err_mask(status);
 772                 ata_qc_complete(qc);
 773                 handled = 1;
 774
 775         } else {
 776                 ap->stats.idle_irq++;
 777         }
 778
 779         return handled;
 780 }
 781
 782 static void pdc20621_irq_clear(struct ata_port *ap)
 783 {
 784         struct ata_host_set *host_set = ap->host_set;
 785         void __iomem *mmio = host_set->mmio_base;
 786
 787         mmio += PDC_CHIP0_OFS;
 788
 789         readl(mmio + PDC_20621_SEQMASK);
 790 }
 791
 792 static irqreturn_t pdc20621_interrupt (int irq, void *dev_instance, struct pt_regs *regs)
 793 {
 794         struct ata_host_set *host_set = dev_instance;
 795         struct ata_port *ap;
 796         u32 mask = 0;
 797         unsigned int i, tmp, port_no;
 798         unsigned int handled = 0;
 799         void __iomem *mmio_base;
 800
 801         VPRINTK("ENTER\n");
 802
 803         if (!host_set || !host_set->mmio_base) {
 804                 VPRINTK("QUICK EXIT\n");
 805                 return IRQ_NONE;
 806         }
 807
 808         mmio_base = host_set->mmio_base;
 809
 810         /* reading should also clear interrupts */
 811         mmio_base += PDC_CHIP0_OFS;
 812         mask = readl(mmio_base + PDC_20621_SEQMASK);
 813         VPRINTK("mask == 0x%x\n", mask);
 814
 815         if (mask == 0xffffffff) {
 816                 VPRINTK("QUICK EXIT 2\n");
 817                 return IRQ_NONE;
 818         }
 819         mask &= 0xffff;         /* only 16 tags possible */
 820         if (!mask) {
 821                 VPRINTK("QUICK EXIT 3\n");
 822                 return IRQ_NONE;
 823         }
 824
 825         spin_lock(&host_set->lock);
 826
 827         for (i = 1; i < 9; i++) {
 828                 port_no = i - 1;
 829                 if (port_no > 3)
 830                         port_no -= 4;
 831                 if (port_no >= host_set->n_ports)
 832                         ap = NULL;
 833                 else
 834                         ap = host_set->ports[port_no];
 835                 tmp = mask & (1 << i);
 836                 VPRINTK("seq %u, port_no %u, ap %p, tmp %x\n", i, port_no, ap, tmp);
 837                 if (tmp && ap &&
 838                     !(ap->flags & (ATA_FLAG_PORT_DISABLED | ATA_FLAG_NOINTR))) {
 839                         struct ata_queued_cmd *qc;
 840
 841                         qc = ata_qc_from_tag(ap, ap->active_tag);
 842                         if (qc && (!(qc->tf.ctl & ATA_NIEN)))
 843                                 handled += pdc20621_host_intr(ap, qc, (i > 4),
 844                                                               mmio_base);
 845                 }
 846         }
 847
 848         spin_unlock(&host_set->lock);
 849
 850         VPRINTK("mask == 0x%x\n", mask);
 851
 852         VPRINTK("EXIT\n");
 853
 854         return IRQ_RETVAL(handled);
 855 }
 856
 857 static void pdc_eng_timeout(struct ata_port *ap)
 858 {
 859         u8 drv_stat;
 860         struct ata_host_set *host_set = ap->host_set;
 861         struct ata_queued_cmd *qc;
 862         unsigned long flags;
 863
 864         DPRINTK("ENTER\n");
 865
 866         spin_lock_irqsave(&host_set->lock, flags);
 867
 868         qc = ata_qc_from_tag(ap, ap->active_tag);
 869         if (!qc) {
 870                 printk(KERN_ERR "ata%u: BUG: timeout without command\n",
 871                        ap->id);
 872                 goto out;
 873         }
 874
 875         switch (qc->tf.protocol) {
 876         case ATA_PROT_DMA:
 877         case ATA_PROT_NODATA:
 878                 printk(KERN_ERR "ata%u: command timeout\n", ap->id);
 879                 qc->err_mask |= __ac_err_mask(ata_wait_idle(ap));
 880                 break;
 881
 882         default:
 883                 drv_stat = ata_busy_wait(ap, ATA_BUSY | ATA_DRQ, 1000);
 884
 885                 printk(KERN_ERR "ata%u: unknown timeout, cmd 0x%x stat 0x%x\n",
 886                        ap->id, qc->tf.command, drv_stat);
 887
 888                 qc->err_mask |= ac_err_mask(drv_stat);
 889                 break;
 890         }
 891
 892 out:
 893         spin_unlock_irqrestore(&host_set->lock, flags);
 894         if (qc)
 895                 ata_eh_qc_complete(qc);
 896         DPRINTK("EXIT\n");
 897 }
 898
 899 static void pdc_tf_load_mmio(struct ata_port *ap, const struct ata_taskfile *tf)
 900 {
 901         WARN_ON (tf->protocol == ATA_PROT_DMA ||
 902                  tf->protocol == ATA_PROT_NODATA);
 903         ata_tf_load(ap, tf);
 904 }
 905
 906
 907 static void pdc_exec_command_mmio(struct ata_port *ap, const struct ata_taskfile *tf)
 908 {
 909         WARN_ON (tf->protocol == ATA_PROT_DMA ||
 910                  tf->protocol == ATA_PROT_NODATA);
 911         ata_exec_command(ap, tf);
 912 }
 913
 914
 915 static void pdc_sata_setup_port(struct ata_ioports *port, unsigned long base)
 916 {
 917         port->cmd_addr          = base;
 918         port->data_addr         = base;
 919         port->feature_addr      =
 920         port->error_addr        = base + 0x4;
 921         port->nsect_addr        = base + 0x8;
 922         port->lbal_addr         = base + 0xc;
 923         port->lbam_addr         = base + 0x10;
 924         port->lbah_addr         = base + 0x14;
 925         port->device_addr       = base + 0x18;
 926         port->command_addr      =
 927         port->status_addr       = base + 0x1c;
 928         port->altstatus_addr    =
 929         port->ctl_addr          = base + 0x38;
 930 }
 931
 932
 933 #ifdef ATA_VERBOSE_DEBUG
 934 static void pdc20621_get_from_dimm(struct ata_probe_ent *pe, void *psource,
 935                                    u32 offset, u32 size)
 936 {
 937         u32 window_size;
 938         u16 idx;
 939         u8 page_mask;
 940         long dist;
 941         void __iomem *mmio = pe->mmio_base;
 942         struct pdc_host_priv *hpriv = pe->private_data;
 943         void __iomem *dimm_mmio = hpriv->dimm_mmio;
 944
 945         /* hard-code chip #0 */
 946         mmio += PDC_CHIP0_OFS;
 947
 948         page_mask = 0x00;
 949         window_size = 0x2000 * 4; /* 32K byte uchar size */
 950         idx = (u16) (offset / window_size);
 951
 952         writel(0x01, mmio + PDC_GENERAL_CTLR);
 953         readl(mmio + PDC_GENERAL_CTLR);
 954         writel(((idx) << page_mask), mmio + PDC_DIMM_WINDOW_CTLR);
 955         readl(mmio + PDC_DIMM_WINDOW_CTLR);
 956
 957         offset -= (idx * window_size);
 958         idx++;
 959         dist = ((long) (window_size - (offset + size))) >= 0 ? size :
 960                 (long) (window_size - offset);
 961         memcpy_fromio((char *) psource, (char *) (dimm_mmio + offset / 4),
 962                       dist);
 963
 964         psource += dist;
 965         size -= dist;
 966         for (; (long) size >= (long) window_size ;) {
 967                 writel(0x01, mmio + PDC_GENERAL_CTLR);
 968                 readl(mmio + PDC_GENERAL_CTLR);
 969                 writel(((idx) << page_mask), mmio + PDC_DIMM_WINDOW_CTLR);
 970                 readl(mmio + PDC_DIMM_WINDOW_CTLR);
 971                 memcpy_fromio((char *) psource, (char *) (dimm_mmio),
 972                               window_size / 4);
 973                 psource += window_size;
 974                 size -= window_size;
 975                 idx ++;
 976         }
 977
 978         if (size) {
 979                 writel(0x01, mmio + PDC_GENERAL_CTLR);
 980                 readl(mmio + PDC_GENERAL_CTLR);
 981                 writel(((idx) << page_mask), mmio + PDC_DIMM_WINDOW_CTLR);
 982                 readl(mmio + PDC_DIMM_WINDOW_CTLR);
 983                 memcpy_fromio((char *) psource, (char *) (dimm_mmio),
 984                               size / 4);
 985         }
 986 }
 987 #endif
 988
 989
 990 static void pdc20621_put_to_dimm(struct ata_probe_ent *pe, void *psource,
 991                                  u32 offset, u32 size)
 992 {
 993         u32 window_size;
 994         u16 idx;
 995         u8 page_mask;
 996         long dist;
 997         void __iomem *mmio = pe->mmio_base;
 998         struct pdc_host_priv *hpriv = pe->private_data;
 999         void __iomem *dimm_mmio = hpriv->dimm_mmio;
1000
1001         /* hard-code chip #0 */
1002         mmio += PDC_CHIP0_OFS;
1003
1004         page_mask = 0x00;
1005         window_size = 0x2000 * 4;       /* 32K byte uchar size */
1006         idx = (u16) (offset / window_size);
1007
1008         writel(((idx) << page_mask), mmio + PDC_DIMM_WINDOW_CTLR);
1009         readl(mmio + PDC_DIMM_WINDOW_CTLR);
1010         offset -= (idx * window_size);
1011         idx++;
1012         dist = ((long)(s32)(window_size - (offset + size))) >= 0 ? size :
1013                 (long) (window_size - offset);
1014         memcpy_toio(dimm_mmio + offset / 4, psource, dist);
1015         writel(0x01, mmio + PDC_GENERAL_CTLR);
1016         readl(mmio + PDC_GENERAL_CTLR);
1017
1018         psource += dist;
1019         size -= dist;
1020         for (; (long) size >= (long) window_size ;) {
1021                 writel(((idx) << page_mask), mmio + PDC_DIMM_WINDOW_CTLR);
1022                 readl(mmio + PDC_DIMM_WINDOW_CTLR);
1023                 memcpy_toio(dimm_mmio, psource, window_size / 4);
1024                 writel(0x01, mmio + PDC_GENERAL_CTLR);
1025                 readl(mmio + PDC_GENERAL_CTLR);
1026                 psource += window_size;
1027                 size -= window_size;
1028                 idx ++;
1029         }
1030
1031         if (size) {
1032                 writel(((idx) << page_mask), mmio + PDC_DIMM_WINDOW_CTLR);
1033                 readl(mmio + PDC_DIMM_WINDOW_CTLR);
1034                 memcpy_toio(dimm_mmio, psource, size / 4);
1035                 writel(0x01, mmio + PDC_GENERAL_CTLR);
1036                 readl(mmio + PDC_GENERAL_CTLR);
1037         }
1038 }
1039
1040
1041 static unsigned int pdc20621_i2c_read(struct ata_probe_ent *pe, u32 device,
1042                                       u32 subaddr, u32 *pdata)
1043 {
1044         void __iomem *mmio = pe->mmio_base;
1045         u32 i2creg  = 0;
1046         u32 status;
1047         u32 count =0;
1048
1049         /* hard-code chip #0 */
1050         mmio += PDC_CHIP0_OFS;
1051
1052         i2creg |= device << 24;
1053         i2creg |= subaddr << 16;
1054
1055         /* Set the device and subaddress */
1056         writel(i2creg, mmio + PDC_I2C_ADDR_DATA_OFFSET);
1057         readl(mmio + PDC_I2C_ADDR_DATA_OFFSET);
1058
1059         /* Write Control to perform read operation, mask int */
1060         writel(PDC_I2C_READ | PDC_I2C_START | PDC_I2C_MASK_INT,
1061                mmio + PDC_I2C_CONTROL_OFFSET);
1062
1063         for (count = 0; count <= 1000; count ++) {
1064                 status = readl(mmio + PDC_I2C_CONTROL_OFFSET);
1065                 if (status & PDC_I2C_COMPLETE) {
1066                         status = readl(mmio + PDC_I2C_ADDR_DATA_OFFSET);
1067                         break;
1068                 } else if (count == 1000)
1069                         return 0;
1070         }
1071
1072         *pdata = (status >> 8) & 0x000000ff;
1073         return 1;
1074 }
1075
1076
1077 static int pdc20621_detect_dimm(struct ata_probe_ent *pe)
1078 {
1079         u32 data=0 ;
1080         if (pdc20621_i2c_read(pe, PDC_DIMM0_SPD_DEV_ADDRESS,
1081                              PDC_DIMM_SPD_SYSTEM_FREQ, &data)) {
1082                 if (data == 100)
1083                         return 100;
1084         } else
1085                 return 0;
1086
1087         if (pdc20621_i2c_read(pe, PDC_DIMM0_SPD_DEV_ADDRESS, 9, &data)) {
1088                 if(data <= 0x75)
1089                         return 133;
1090         } else
1091                 return 0;
1092
1093         return 0;
1094 }
1095
1096
1097 static int pdc20621_prog_dimm0(struct ata_probe_ent *pe)
1098 {
1099         u32 spd0[50];
1100         u32 data = 0;
1101         int size, i;
1102         u8 bdimmsize;
1103         void __iomem *mmio = pe->mmio_base;
1104         static const struct {
1105                 unsigned int reg;
1106                 unsigned int ofs;
1107         } pdc_i2c_read_data [] = {
1108                 { PDC_DIMM_SPD_TYPE, 11 },
1109                 { PDC_DIMM_SPD_FRESH_RATE, 12 },
1110                 { PDC_DIMM_SPD_COLUMN_NUM, 4 },
1111                 { PDC_DIMM_SPD_ATTRIBUTE, 21 },
1112                 { PDC_DIMM_SPD_ROW_NUM, 3 },
1113                 { PDC_DIMM_SPD_BANK_NUM, 17 },
1114                 { PDC_DIMM_SPD_MODULE_ROW, 5 },
1115                 { PDC_DIMM_SPD_ROW_PRE_CHARGE, 27 },
1116                 { PDC_DIMM_SPD_ROW_ACTIVE_DELAY, 28 },
1117                 { PDC_DIMM_SPD_RAS_CAS_DELAY, 29 },
1118                 { PDC_DIMM_SPD_ACTIVE_PRECHARGE, 30 },
1119                 { PDC_DIMM_SPD_CAS_LATENCY, 18 },
1120         };
1121
1122         /* hard-code chip #0 */
1123         mmio += PDC_CHIP0_OFS;
1124
1125         for(i=0; i<ARRAY_SIZE(pdc_i2c_read_data); i++)
1126                 pdc20621_i2c_read(pe, PDC_DIMM0_SPD_DEV_ADDRESS,
1127                                   pdc_i2c_read_data[i].reg,
1128                                   &spd0[pdc_i2c_read_data[i].ofs]);
1129
1130         data |= (spd0[4] - 8) | ((spd0[21] != 0) << 3) | ((spd0[3]-11) << 4);
1131         data |= ((spd0[17] / 4) << 6) | ((spd0[5] / 2) << 7) |
1132                 ((((spd0[27] + 9) / 10) - 1) << 8) ;
1133         data |= (((((spd0[29] > spd0[28])
1134                     ? spd0[29] : spd0[28]) + 9) / 10) - 1) << 10;
1135         data |= ((spd0[30] - spd0[29] + 9) / 10 - 2) << 12;
1136
1137         if (spd0[18] & 0x08)
1138                 data |= ((0x03) << 14);
1139         else if (spd0[18] & 0x04)
1140                 data |= ((0x02) << 14);
1141         else if (spd0[18] & 0x01)
1142                 data |= ((0x01) << 14);
1143         else
1144                 data |= (0 << 14);
1145
1146         /*
1147            Calculate the size of bDIMMSize (power of 2) and
1148            merge the DIMM size by program start/end address.
1149         */
1150
1151         bdimmsize = spd0[4] + (spd0[5] / 2) + spd0[3] + (spd0[17] / 2) + 3;
1152         size = (1 << bdimmsize) >> 20;  /* size = xxx(MB) */
1153         data |= (((size / 16) - 1) << 16);
1154         data |= (0 << 23);
1155         data |= 8;
1156         writel(data, mmio + PDC_DIMM0_CONTROL_OFFSET);
1157         readl(mmio + PDC_DIMM0_CONTROL_OFFSET);
1158         return size;
1159 }
1160
1161
1162 static unsigned int pdc20621_prog_dimm_global(struct ata_probe_ent *pe)
1163 {
1164         u32 data, spd0;
1165         int error, i;
1166         void __iomem *mmio = pe->mmio_base;
1167
1168         /* hard-code chip #0 */
1169         mmio += PDC_CHIP0_OFS;
1170
1171         /*
1172           Set To Default : DIMM Module Global Control Register (0x022259F1)
1173           DIMM Arbitration Disable (bit 20)
1174           DIMM Data/Control Output Driving Selection (bit12 - bit15)
1175           Refresh Enable (bit 17)
1176         */
1177
1178         data = 0x022259F1;
1179         writel(data, mmio + PDC_SDRAM_CONTROL_OFFSET);
1180         readl(mmio + PDC_SDRAM_CONTROL_OFFSET);
1181
1182         /* Turn on for ECC */
1183         pdc20621_i2c_read(pe, PDC_DIMM0_SPD_DEV_ADDRESS,
1184                           PDC_DIMM_SPD_TYPE, &spd0);
1185         if (spd0 == 0x02) {
1186                 data |= (0x01 << 16);
1187                 writel(data, mmio + PDC_SDRAM_CONTROL_OFFSET);
1188                 readl(mmio + PDC_SDRAM_CONTROL_OFFSET);
1189                 printk(KERN_ERR "Local DIMM ECC Enabled\n");
1190         }
1191
1192         /* DIMM Initialization Select/Enable (bit 18/19) */
1193         data &= (~(1<<18));
1194         data |= (1<<19);
1195         writel(data, mmio + PDC_SDRAM_CONTROL_OFFSET);
1196
1197         error = 1;
1198         for (i = 1; i <= 10; i++) {   /* polling ~5 secs */
1199                 data = readl(mmio + PDC_SDRAM_CONTROL_OFFSET);
1200                 if (!(data & (1<<19))) {
1201                         error = 0;
1202                         break;
1203                 }
1204                 msleep(i*100);
1205         }
1206         return error;
1207 }
1208
1209
1210 static unsigned int pdc20621_dimm_init(struct ata_probe_ent *pe)
1211 {
1212         int speed, size, length;
1213         u32 addr,spd0,pci_status;
1214         u32 tmp=0;
1215         u32 time_period=0;
1216         u32 tcount=0;
1217         u32 ticks=0;
1218         u32 clock=0;
1219         u32 fparam=0;
1220         void __iomem *mmio = pe->mmio_base;
1221
1222         /* hard-code chip #0 */
1223         mmio += PDC_CHIP0_OFS;
1224
1225         /* Initialize PLL based upon PCI Bus Frequency */
1226
1227         /* Initialize Time Period Register */
1228         writel(0xffffffff, mmio + PDC_TIME_PERIOD);
1229         time_period = readl(mmio + PDC_TIME_PERIOD);
1230         VPRINTK("Time Period Register (0x40): 0x%x\n", time_period);
1231
1232         /* Enable timer */
1233         writel(0x00001a0, mmio + PDC_TIME_CONTROL);
1234         readl(mmio + PDC_TIME_CONTROL);
1235
1236         /* Wait 3 seconds */
1237         msleep(3000);
1238
1239         /*
1240            When timer is enabled, counter is decreased every internal
1241            clock cycle.
1242         */
1243
1244         tcount = readl(mmio + PDC_TIME_COUNTER);
1245         VPRINTK("Time Counter Register (0x44): 0x%x\n", tcount);
1246
1247         /*
1248            If SX4 is on PCI-X bus, after 3 seconds, the timer counter
1249            register should be >= (0xffffffff - 3x10^8).
1250         */
1251         if(tcount >= PCI_X_TCOUNT) {
1252                 ticks = (time_period - tcount);
1253                 VPRINTK("Num counters 0x%x (%d)\n", ticks, ticks);
1254
1255                 clock = (ticks / 300000);
1256                 VPRINTK("10 * Internal clk = 0x%x (%d)\n", clock, clock);
1257
1258                 clock = (clock * 33);
1259                 VPRINTK("10 * Internal clk * 33 = 0x%x (%d)\n", clock, clock);
1260
1261                 /* PLL F Param (bit 22:16) */
1262                 fparam = (1400000 / clock) - 2;
1263                 VPRINTK("PLL F Param: 0x%x (%d)\n", fparam, fparam);
1264
1265                 /* OD param = 0x2 (bit 31:30), R param = 0x5 (bit 29:25) */
1266                 pci_status = (0x8a001824 | (fparam << 16));
1267         } else
1268                 pci_status = PCI_PLL_INIT;
1269
1270         /* Initialize PLL. */
1271         VPRINTK("pci_status: 0x%x\n", pci_status);
1272         writel(pci_status, mmio + PDC_CTL_STATUS);
1273         readl(mmio + PDC_CTL_STATUS);
1274
1275         /*
1276            Read SPD of DIMM by I2C interface,
1277            and program the DIMM Module Controller.
1278         */
1279         if (!(speed = pdc20621_detect_dimm(pe))) {
1280                 printk(KERN_ERR "Detect Local DIMM Fail\n");
1281                 return 1;       /* DIMM error */
1282         }
1283         VPRINTK("Local DIMM Speed = %d\n", speed);
1284
1285         /* Programming DIMM0 Module Control Register (index_CID0:80h) */
1286         size = pdc20621_prog_dimm0(pe);
1287         VPRINTK("Local DIMM Size = %dMB\n",size);
1288
1289         /* Programming DIMM Module Global Control Register (index_CID0:88h) */
1290         if (pdc20621_prog_dimm_global(pe)) {
1291                 printk(KERN_ERR "Programming DIMM Module Global Control Register Fail\n");
1292                 return 1;
1293         }
1294
1295 #ifdef ATA_VERBOSE_DEBUG
1296         {
1297                 u8 test_parttern1[40] = {0x55,0xAA,'P','r','o','m','i','s','e',' ',
1298                                 'N','o','t',' ','Y','e','t',' ','D','e','f','i','n','e','d',' ',
1299                                  '1','.','1','0',
1300                                 '9','8','0','3','1','6','1','2',0,0};
1301                 u8 test_parttern2[40] = {0};
1302
1303                 pdc20621_put_to_dimm(pe, (void *) test_parttern2, 0x10040, 40);
1304                 pdc20621_put_to_dimm(pe, (void *) test_parttern2, 0x40, 40);
1305
1306                 pdc20621_put_to_dimm(pe, (void *) test_parttern1, 0x10040, 40);
1307                 pdc20621_get_from_dimm(pe, (void *) test_parttern2, 0x40, 40);
1308                 printk(KERN_ERR "%x, %x, %s\n", test_parttern2[0],
1309                        test_parttern2[1], &(test_parttern2[2]));
1310                 pdc20621_get_from_dimm(pe, (void *) test_parttern2, 0x10040,
1311                                        40);
1312                 printk(KERN_ERR "%x, %x, %s\n", test_parttern2[0],
1313                        test_parttern2[1], &(test_parttern2[2]));
1314
1315                 pdc20621_put_to_dimm(pe, (void *) test_parttern1, 0x40, 40);
1316                 pdc20621_get_from_dimm(pe, (void *) test_parttern2, 0x40, 40);
1317                 printk(KERN_ERR "%x, %x, %s\n", test_parttern2[0],
1318                        test_parttern2[1], &(test_parttern2[2]));
1319         }
1320 #endif
1321
1322         /* ECC initiliazation. */
1323
1324         pdc20621_i2c_read(pe, PDC_DIMM0_SPD_DEV_ADDRESS,
1325                           PDC_DIMM_SPD_TYPE, &spd0);
1326         if (spd0 == 0x02) {
1327                 VPRINTK("Start ECC initialization\n");
1328                 addr = 0;
1329                 length = size * 1024 * 1024;
1330                 while (addr < length) {
1331                         pdc20621_put_to_dimm(pe, (void *) &tmp, addr,
1332                                              sizeof(u32));
1333                         addr += sizeof(u32);
1334                 }
1335                 VPRINTK("Finish ECC initialization\n");
1336         }
1337         return 0;
1338 }
1339
1340
1341 static void pdc_20621_init(struct ata_probe_ent *pe)
1342 {
1343         u32 tmp;
1344         void __iomem *mmio = pe->mmio_base;
1345
1346         /* hard-code chip #0 */
1347         mmio += PDC_CHIP0_OFS;
1348
1349         /*
1350          * Select page 0x40 for our 32k DIMM window
1351          */
1352         tmp = readl(mmio + PDC_20621_DIMM_WINDOW) & 0xffff0000;
1353         tmp |= PDC_PAGE_WINDOW; /* page 40h; arbitrarily selected */
1354         writel(tmp, mmio + PDC_20621_DIMM_WINDOW);
1355
1356         /*
1357          * Reset Host DMA
1358          */
1359         tmp = readl(mmio + PDC_HDMA_CTLSTAT);
1360         tmp |= PDC_RESET;
1361         writel(tmp, mmio + PDC_HDMA_CTLSTAT);
1362         readl(mmio + PDC_HDMA_CTLSTAT);         /* flush */
1363
1364         udelay(10);
1365
1366         tmp = readl(mmio + PDC_HDMA_CTLSTAT);
1367         tmp &= ~PDC_RESET;
1368         writel(tmp, mmio + PDC_HDMA_CTLSTAT);
1369         readl(mmio + PDC_HDMA_CTLSTAT);         /* flush */
1370 }
1371
1372 static int pdc_sata_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
1373 {
1374         static int printed_version;
1375         struct ata_probe_ent *probe_ent = NULL;
1376         unsigned long base;
1377         void __iomem *mmio_base;
1378         void __iomem *dimm_mmio = NULL;
1379         struct pdc_host_priv *hpriv = NULL;
1380         unsigned int board_idx = (unsigned int) ent->driver_data;
1381         int pci_dev_busy = 0;
1382         int rc;
1383
1384         if (!printed_version++)
1385                 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
1386
1387         /*
1388          * If this driver happens to only be useful on Apple's K2, then
1389          * we should check that here as it has a normal Serverworks ID
1390          */
1391         rc = pci_enable_device(pdev);
1392         if (rc)
1393                 return rc;
1394
1395         rc = pci_request_regions(pdev, DRV_NAME);
1396         if (rc) {
1397                 pci_dev_busy = 1;
1398                 goto err_out;
1399         }
1400
1401         rc = pci_set_dma_mask(pdev, ATA_DMA_MASK);
1402         if (rc)
1403                 goto err_out_regions;
1404         rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK);
1405         if (rc)
1406                 goto err_out_regions;
1407
1408         probe_ent = kmalloc(sizeof(*probe_ent), GFP_KERNEL);
1409         if (probe_ent == NULL) {
1410                 rc = -ENOMEM;
1411                 goto err_out_regions;
1412         }
1413
1414         memset(probe_ent, 0, sizeof(*probe_ent));
1415         probe_ent->dev = pci_dev_to_dev(pdev);
1416         INIT_LIST_HEAD(&probe_ent->node);
1417
1418         mmio_base = pci_iomap(pdev, 3, 0);
1419         if (mmio_base == NULL) {
1420                 rc = -ENOMEM;
1421                 goto err_out_free_ent;
1422         }
1423         base = (unsigned long) mmio_base;
1424
1425         hpriv = kmalloc(sizeof(*hpriv), GFP_KERNEL);
1426         if (!hpriv) {
1427                 rc = -ENOMEM;
1428                 goto err_out_iounmap;
1429         }
1430         memset(hpriv, 0, sizeof(*hpriv));
1431
1432         dimm_mmio = pci_iomap(pdev, 4, 0);
1433         if (!dimm_mmio) {
1434                 kfree(hpriv);
1435                 rc = -ENOMEM;
1436                 goto err_out_iounmap;
1437         }
1438
1439         hpriv->dimm_mmio = dimm_mmio;
1440
1441         probe_ent->sht          = pdc_port_info[board_idx].sht;
1442         probe_ent->host_flags   = pdc_port_info[board_idx].host_flags;
1443         probe_ent->pio_mask     = pdc_port_info[board_idx].pio_mask;
1444         probe_ent->mwdma_mask   = pdc_port_info[board_idx].mwdma_mask;
1445         probe_ent->udma_mask    = pdc_port_info[board_idx].udma_mask;
1446         probe_ent->port_ops     = pdc_port_info[board_idx].port_ops;
1447
1448         probe_ent->irq = pdev->irq;
1449         probe_ent->irq_flags = SA_SHIRQ;
1450         probe_ent->mmio_base = mmio_base;
1451
1452         probe_ent->private_data = hpriv;
1453         base += PDC_CHIP0_OFS;
1454
1455         probe_ent->n_ports = 4;
1456         pdc_sata_setup_port(&probe_ent->port[0], base + 0x200);
1457         pdc_sata_setup_port(&probe_ent->port[1], base + 0x280);
1458         pdc_sata_setup_port(&probe_ent->port[2], base + 0x300);
1459         pdc_sata_setup_port(&probe_ent->port[3], base + 0x380);
1460
1461         pci_set_master(pdev);
1462
1463         /* initialize adapter */
1464         /* initialize local dimm */
1465         if (pdc20621_dimm_init(probe_ent)) {
1466                 rc = -ENOMEM;
1467                 goto err_out_iounmap_dimm;
1468         }
1469         pdc_20621_init(probe_ent);
1470
1471         /* FIXME: check ata_device_add return value */
1472         ata_device_add(probe_ent);
1473         kfree(probe_ent);
1474
1475         return 0;
1476
1477 err_out_iounmap_dimm:           /* only get to this label if 20621 */
1478         kfree(hpriv);
1479         pci_iounmap(pdev, dimm_mmio);
1480 err_out_iounmap:
1481         pci_iounmap(pdev, mmio_base);
1482 err_out_free_ent:
1483         kfree(probe_ent);
1484 err_out_regions:
1485         pci_release_regions(pdev);
1486 err_out:
1487         if (!pci_dev_busy)
1488                 pci_disable_device(pdev);
1489         return rc;
1490 }
1491
1492
1493 static int __init pdc_sata_init(void)
1494 {
1495         return pci_module_init(&pdc_sata_pci_driver);
1496 }
1497
1498
1499 static void __exit pdc_sata_exit(void)
1500 {
1501         pci_unregister_driver(&pdc_sata_pci_driver);
1502 }
1503
1504
1505 MODULE_AUTHOR("Jeff Garzik");
1506 MODULE_DESCRIPTION("Promise SATA low-level driver");
1507 MODULE_LICENSE("GPL");
1508 MODULE_DEVICE_TABLE(pci, pdc_sata_pci_tbl);
1509 MODULE_VERSION(DRV_VERSION);
1510
1511 module_init(pdc_sata_init);
1512 module_exit(pdc_sata_exit);