2 * linux/drivers/char/8250.c
4 * Driver for 8250/16550-type serial ports
6 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
8 * Copyright (C) 2001 Russell King.
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
15 * $Id: 8250.c,v 1.90 2002/07/28 10:03:27 rmk Exp $
17 * A note about mapbase / membase
19 * mapbase is the physical address of the IO port.
20 * membase is an 'ioremapped' cookie.
23 #if defined(CONFIG_SERIAL_8250_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
27 #include <linux/module.h>
28 #include <linux/moduleparam.h>
29 #include <linux/ioport.h>
30 #include <linux/init.h>
31 #include <linux/console.h>
32 #include <linux/sysrq.h>
33 #include <linux/delay.h>
34 #include <linux/platform_device.h>
35 #include <linux/tty.h>
36 #include <linux/tty_flip.h>
37 #include <linux/serial_reg.h>
38 #include <linux/serial_core.h>
39 #include <linux/serial.h>
40 #include <linux/serial_8250.h>
41 #include <linux/nmi.h>
42 #include <linux/mutex.h>
51 * share_irqs - whether we pass IRQF_SHARED to request_irq(). This option
52 * is unsafe when used on edge-triggered interrupts.
54 static unsigned int share_irqs = SERIAL8250_SHARE_IRQS;
56 static unsigned int nr_uarts = CONFIG_SERIAL_8250_RUNTIME_UARTS;
62 #define DEBUG_AUTOCONF(fmt...) printk(fmt)
64 #define DEBUG_AUTOCONF(fmt...) do { } while (0)
68 #define DEBUG_INTR(fmt...) printk(fmt)
70 #define DEBUG_INTR(fmt...) do { } while (0)
73 #define PASS_LIMIT 256
76 * We default to IRQ0 for the "no irq" hack. Some
77 * machine types want others as well - they're free
78 * to redefine this in their header file.
80 #define is_real_interrupt(irq) ((irq) != 0)
82 #ifdef CONFIG_SERIAL_8250_DETECT_IRQ
83 #define CONFIG_SERIAL_DETECT_IRQ 1
85 #ifdef CONFIG_SERIAL_8250_MANY_PORTS
86 #define CONFIG_SERIAL_MANY_PORTS 1
90 * HUB6 is always on. This will be removed once the header
91 * files have been cleaned.
95 #include <asm/serial.h>
98 * SERIAL_PORT_DFNS tells us about built-in ports that have no
99 * standard enumeration mechanism. Platforms that can find all
100 * serial ports via mechanisms like ACPI or PCI need not supply it.
102 #ifndef SERIAL_PORT_DFNS
103 #define SERIAL_PORT_DFNS
106 static const struct old_serial_port old_serial_port[] = {
107 SERIAL_PORT_DFNS /* defined in asm/serial.h */
110 #define UART_NR CONFIG_SERIAL_8250_NR_UARTS
112 #ifdef CONFIG_SERIAL_8250_RSA
114 #define PORT_RSA_MAX 4
115 static unsigned long probe_rsa[PORT_RSA_MAX];
116 static unsigned int probe_rsa_count;
117 #endif /* CONFIG_SERIAL_8250_RSA */
119 struct uart_8250_port {
120 struct uart_port port;
121 struct timer_list timer; /* "no irq" timer */
122 struct list_head list; /* ports on this IRQ */
123 unsigned short capabilities; /* port capabilities */
124 unsigned short bugs; /* port bugs */
125 unsigned int tx_loadsz; /* transmit fifo load size */
130 unsigned char mcr_mask; /* mask of user bits */
131 unsigned char mcr_force; /* mask of forced bits */
134 * Some bits in registers are cleared on a read, so they must
135 * be saved whenever the register is read but the bits will not
136 * be immediately processed.
138 #define LSR_SAVE_FLAGS UART_LSR_BRK_ERROR_BITS
139 unsigned char lsr_saved_flags;
140 #define MSR_SAVE_FLAGS UART_MSR_ANY_DELTA
141 unsigned char msr_saved_flags;
144 * We provide a per-port pm hook.
146 void (*pm)(struct uart_port *port,
147 unsigned int state, unsigned int old);
152 struct list_head *head;
155 static struct irq_info irq_lists[NR_IRQS];
158 * Here we define the default xmit fifo size used for each type of UART.
160 static const struct serial8250_config uart_config[] = {
185 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
186 .flags = UART_CAP_FIFO,
197 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
203 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
205 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
211 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10 |
213 .flags = UART_CAP_FIFO | UART_CAP_SLEEP | UART_CAP_AFE,
221 .name = "16C950/954",
224 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
225 .flags = UART_CAP_FIFO,
231 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
233 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
239 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
240 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
246 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_11,
247 .flags = UART_CAP_FIFO,
253 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
254 .flags = UART_CAP_FIFO | UART_NATSEMI,
260 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
261 .flags = UART_CAP_FIFO | UART_CAP_UUE,
267 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
268 .flags = UART_CAP_FIFO,
272 #if defined (CONFIG_SERIAL_8250_AU1X00)
274 /* Au1x00 UART hardware has a weird register layout */
275 static const u8 au_io_in_map[] = {
285 static const u8 au_io_out_map[] = {
293 /* sane hardware needs no mapping */
294 static inline int map_8250_in_reg(struct uart_8250_port *up, int offset)
296 if (up->port.iotype != UPIO_AU)
298 return au_io_in_map[offset];
301 static inline int map_8250_out_reg(struct uart_8250_port *up, int offset)
303 if (up->port.iotype != UPIO_AU)
305 return au_io_out_map[offset];
308 #elif defined (CONFIG_SERIAL_8250_RM9K)
332 static inline int map_8250_in_reg(struct uart_8250_port *up, int offset)
334 if (up->port.iotype != UPIO_RM9000)
336 return regmap_in[offset];
339 static inline int map_8250_out_reg(struct uart_8250_port *up, int offset)
341 if (up->port.iotype != UPIO_RM9000)
343 return regmap_out[offset];
348 /* sane hardware needs no mapping */
349 #define map_8250_in_reg(up, offset) (offset)
350 #define map_8250_out_reg(up, offset) (offset)
354 static unsigned int serial_in(struct uart_8250_port *up, int offset)
357 offset = map_8250_in_reg(up, offset) << up->port.regshift;
359 switch (up->port.iotype) {
361 outb(up->port.hub6 - 1 + offset, up->port.iobase);
362 return inb(up->port.iobase + 1);
366 return readb(up->port.membase + offset);
370 return readl(up->port.membase + offset);
372 #ifdef CONFIG_SERIAL_8250_AU1X00
374 return __raw_readl(up->port.membase + offset);
378 if (offset == UART_IIR) {
379 tmp = readl(up->port.membase + (UART_IIR & ~3));
380 return (tmp >> 16) & 0xff; /* UART_IIR % 4 == 2 */
382 return readb(up->port.membase + offset);
385 return inb(up->port.iobase + offset);
390 serial_out(struct uart_8250_port *up, int offset, int value)
392 /* Save the offset before it's remapped */
393 int save_offset = offset;
394 offset = map_8250_out_reg(up, offset) << up->port.regshift;
396 switch (up->port.iotype) {
398 outb(up->port.hub6 - 1 + offset, up->port.iobase);
399 outb(value, up->port.iobase + 1);
403 writeb(value, up->port.membase + offset);
408 writel(value, up->port.membase + offset);
411 #ifdef CONFIG_SERIAL_8250_AU1X00
413 __raw_writel(value, up->port.membase + offset);
417 if (!((offset == UART_IER) && (value & UART_IER_UUE)))
418 writeb(value, up->port.membase + offset);
422 /* Save the LCR value so it can be re-written when a
423 * Busy Detect interrupt occurs. */
424 if (save_offset == UART_LCR)
426 writeb(value, up->port.membase + offset);
427 /* Read the IER to ensure any interrupt is cleared before
428 * returning from ISR. */
429 if (save_offset == UART_TX || save_offset == UART_IER)
430 value = serial_in(up, UART_IER);
434 outb(value, up->port.iobase + offset);
439 serial_out_sync(struct uart_8250_port *up, int offset, int value)
441 switch (up->port.iotype) {
444 #ifdef CONFIG_SERIAL_8250_AU1X00
448 serial_out(up, offset, value);
449 serial_in(up, UART_LCR); /* safe, no side-effects */
452 serial_out(up, offset, value);
457 * We used to support using pause I/O for certain machines. We
458 * haven't supported this for a while, but just in case it's badly
459 * needed for certain old 386 machines, I've left these #define's
462 #define serial_inp(up, offset) serial_in(up, offset)
463 #define serial_outp(up, offset, value) serial_out(up, offset, value)
465 /* Uart divisor latch read */
466 static inline int _serial_dl_read(struct uart_8250_port *up)
468 return serial_inp(up, UART_DLL) | serial_inp(up, UART_DLM) << 8;
471 /* Uart divisor latch write */
472 static inline void _serial_dl_write(struct uart_8250_port *up, int value)
474 serial_outp(up, UART_DLL, value & 0xff);
475 serial_outp(up, UART_DLM, value >> 8 & 0xff);
478 #if defined (CONFIG_SERIAL_8250_AU1X00)
479 /* Au1x00 haven't got a standard divisor latch */
480 static int serial_dl_read(struct uart_8250_port *up)
482 if (up->port.iotype == UPIO_AU)
483 return __raw_readl(up->port.membase + 0x28);
485 return _serial_dl_read(up);
488 static void serial_dl_write(struct uart_8250_port *up, int value)
490 if (up->port.iotype == UPIO_AU)
491 __raw_writel(value, up->port.membase + 0x28);
493 _serial_dl_write(up, value);
495 #elif defined (CONFIG_SERIAL_8250_RM9K)
496 static int serial_dl_read(struct uart_8250_port *up)
498 return (up->port.iotype == UPIO_RM9000) ?
499 (((__raw_readl(up->port.membase + 0x10) << 8) |
500 (__raw_readl(up->port.membase + 0x08) & 0xff)) & 0xffff) :
504 static void serial_dl_write(struct uart_8250_port *up, int value)
506 if (up->port.iotype == UPIO_RM9000) {
507 __raw_writel(value, up->port.membase + 0x08);
508 __raw_writel(value >> 8, up->port.membase + 0x10);
510 _serial_dl_write(up, value);
514 #define serial_dl_read(up) _serial_dl_read(up)
515 #define serial_dl_write(up, value) _serial_dl_write(up, value)
521 static void serial_icr_write(struct uart_8250_port *up, int offset, int value)
523 serial_out(up, UART_SCR, offset);
524 serial_out(up, UART_ICR, value);
527 static unsigned int serial_icr_read(struct uart_8250_port *up, int offset)
531 serial_icr_write(up, UART_ACR, up->acr | UART_ACR_ICRRD);
532 serial_out(up, UART_SCR, offset);
533 value = serial_in(up, UART_ICR);
534 serial_icr_write(up, UART_ACR, up->acr);
542 static inline void serial8250_clear_fifos(struct uart_8250_port *p)
544 if (p->capabilities & UART_CAP_FIFO) {
545 serial_outp(p, UART_FCR, UART_FCR_ENABLE_FIFO);
546 serial_outp(p, UART_FCR, UART_FCR_ENABLE_FIFO |
547 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
548 serial_outp(p, UART_FCR, 0);
553 * IER sleep support. UARTs which have EFRs need the "extended
554 * capability" bit enabled. Note that on XR16C850s, we need to
555 * reset LCR to write to IER.
557 static inline void serial8250_set_sleep(struct uart_8250_port *p, int sleep)
559 if (p->capabilities & UART_CAP_SLEEP) {
560 if (p->capabilities & UART_CAP_EFR) {
561 serial_outp(p, UART_LCR, 0xBF);
562 serial_outp(p, UART_EFR, UART_EFR_ECB);
563 serial_outp(p, UART_LCR, 0);
565 serial_outp(p, UART_IER, sleep ? UART_IERX_SLEEP : 0);
566 if (p->capabilities & UART_CAP_EFR) {
567 serial_outp(p, UART_LCR, 0xBF);
568 serial_outp(p, UART_EFR, 0);
569 serial_outp(p, UART_LCR, 0);
574 #ifdef CONFIG_SERIAL_8250_RSA
576 * Attempts to turn on the RSA FIFO. Returns zero on failure.
577 * We set the port uart clock rate if we succeed.
579 static int __enable_rsa(struct uart_8250_port *up)
584 mode = serial_inp(up, UART_RSA_MSR);
585 result = mode & UART_RSA_MSR_FIFO;
588 serial_outp(up, UART_RSA_MSR, mode | UART_RSA_MSR_FIFO);
589 mode = serial_inp(up, UART_RSA_MSR);
590 result = mode & UART_RSA_MSR_FIFO;
594 up->port.uartclk = SERIAL_RSA_BAUD_BASE * 16;
599 static void enable_rsa(struct uart_8250_port *up)
601 if (up->port.type == PORT_RSA) {
602 if (up->port.uartclk != SERIAL_RSA_BAUD_BASE * 16) {
603 spin_lock_irq(&up->port.lock);
605 spin_unlock_irq(&up->port.lock);
607 if (up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16)
608 serial_outp(up, UART_RSA_FRR, 0);
613 * Attempts to turn off the RSA FIFO. Returns zero on failure.
614 * It is unknown why interrupts were disabled in here. However,
615 * the caller is expected to preserve this behaviour by grabbing
616 * the spinlock before calling this function.
618 static void disable_rsa(struct uart_8250_port *up)
623 if (up->port.type == PORT_RSA &&
624 up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16) {
625 spin_lock_irq(&up->port.lock);
627 mode = serial_inp(up, UART_RSA_MSR);
628 result = !(mode & UART_RSA_MSR_FIFO);
631 serial_outp(up, UART_RSA_MSR, mode & ~UART_RSA_MSR_FIFO);
632 mode = serial_inp(up, UART_RSA_MSR);
633 result = !(mode & UART_RSA_MSR_FIFO);
637 up->port.uartclk = SERIAL_RSA_BAUD_BASE_LO * 16;
638 spin_unlock_irq(&up->port.lock);
641 #endif /* CONFIG_SERIAL_8250_RSA */
644 * This is a quickie test to see how big the FIFO is.
645 * It doesn't work at all the time, more's the pity.
647 static int size_fifo(struct uart_8250_port *up)
649 unsigned char old_fcr, old_mcr, old_lcr;
650 unsigned short old_dl;
653 old_lcr = serial_inp(up, UART_LCR);
654 serial_outp(up, UART_LCR, 0);
655 old_fcr = serial_inp(up, UART_FCR);
656 old_mcr = serial_inp(up, UART_MCR);
657 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO |
658 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
659 serial_outp(up, UART_MCR, UART_MCR_LOOP);
660 serial_outp(up, UART_LCR, UART_LCR_DLAB);
661 old_dl = serial_dl_read(up);
662 serial_dl_write(up, 0x0001);
663 serial_outp(up, UART_LCR, 0x03);
664 for (count = 0; count < 256; count++)
665 serial_outp(up, UART_TX, count);
666 mdelay(20);/* FIXME - schedule_timeout */
667 for (count = 0; (serial_inp(up, UART_LSR) & UART_LSR_DR) &&
668 (count < 256); count++)
669 serial_inp(up, UART_RX);
670 serial_outp(up, UART_FCR, old_fcr);
671 serial_outp(up, UART_MCR, old_mcr);
672 serial_outp(up, UART_LCR, UART_LCR_DLAB);
673 serial_dl_write(up, old_dl);
674 serial_outp(up, UART_LCR, old_lcr);
680 * Read UART ID using the divisor method - set DLL and DLM to zero
681 * and the revision will be in DLL and device type in DLM. We
682 * preserve the device state across this.
684 static unsigned int autoconfig_read_divisor_id(struct uart_8250_port *p)
686 unsigned char old_dll, old_dlm, old_lcr;
689 old_lcr = serial_inp(p, UART_LCR);
690 serial_outp(p, UART_LCR, UART_LCR_DLAB);
692 old_dll = serial_inp(p, UART_DLL);
693 old_dlm = serial_inp(p, UART_DLM);
695 serial_outp(p, UART_DLL, 0);
696 serial_outp(p, UART_DLM, 0);
698 id = serial_inp(p, UART_DLL) | serial_inp(p, UART_DLM) << 8;
700 serial_outp(p, UART_DLL, old_dll);
701 serial_outp(p, UART_DLM, old_dlm);
702 serial_outp(p, UART_LCR, old_lcr);
708 * This is a helper routine to autodetect StarTech/Exar/Oxsemi UART's.
709 * When this function is called we know it is at least a StarTech
710 * 16650 V2, but it might be one of several StarTech UARTs, or one of
711 * its clones. (We treat the broken original StarTech 16650 V1 as a
712 * 16550, and why not? Startech doesn't seem to even acknowledge its
715 * What evil have men's minds wrought...
717 static void autoconfig_has_efr(struct uart_8250_port *up)
719 unsigned int id1, id2, id3, rev;
722 * Everything with an EFR has SLEEP
724 up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP;
727 * First we check to see if it's an Oxford Semiconductor UART.
729 * If we have to do this here because some non-National
730 * Semiconductor clone chips lock up if you try writing to the
731 * LSR register (which serial_icr_read does)
735 * Check for Oxford Semiconductor 16C950.
737 * EFR [4] must be set else this test fails.
739 * This shouldn't be necessary, but Mike Hudson (Exoray@isys.ca)
740 * claims that it's needed for 952 dual UART's (which are not
741 * recommended for new designs).
744 serial_out(up, UART_LCR, 0xBF);
745 serial_out(up, UART_EFR, UART_EFR_ECB);
746 serial_out(up, UART_LCR, 0x00);
747 id1 = serial_icr_read(up, UART_ID1);
748 id2 = serial_icr_read(up, UART_ID2);
749 id3 = serial_icr_read(up, UART_ID3);
750 rev = serial_icr_read(up, UART_REV);
752 DEBUG_AUTOCONF("950id=%02x:%02x:%02x:%02x ", id1, id2, id3, rev);
754 if (id1 == 0x16 && id2 == 0xC9 &&
755 (id3 == 0x50 || id3 == 0x52 || id3 == 0x54)) {
756 up->port.type = PORT_16C950;
759 * Enable work around for the Oxford Semiconductor 952 rev B
760 * chip which causes it to seriously miscalculate baud rates
763 if (id3 == 0x52 && rev == 0x01)
764 up->bugs |= UART_BUG_QUOT;
769 * We check for a XR16C850 by setting DLL and DLM to 0, and then
770 * reading back DLL and DLM. The chip type depends on the DLM
772 * 0x10 - XR16C850 and the DLL contains the chip revision.
776 id1 = autoconfig_read_divisor_id(up);
777 DEBUG_AUTOCONF("850id=%04x ", id1);
780 if (id2 == 0x10 || id2 == 0x12 || id2 == 0x14) {
781 up->port.type = PORT_16850;
786 * It wasn't an XR16C850.
788 * We distinguish between the '654 and the '650 by counting
789 * how many bytes are in the FIFO. I'm using this for now,
790 * since that's the technique that was sent to me in the
791 * serial driver update, but I'm not convinced this works.
792 * I've had problems doing this in the past. -TYT
794 if (size_fifo(up) == 64)
795 up->port.type = PORT_16654;
797 up->port.type = PORT_16650V2;
801 * We detected a chip without a FIFO. Only two fall into
802 * this category - the original 8250 and the 16450. The
803 * 16450 has a scratch register (accessible with LCR=0)
805 static void autoconfig_8250(struct uart_8250_port *up)
807 unsigned char scratch, status1, status2;
809 up->port.type = PORT_8250;
811 scratch = serial_in(up, UART_SCR);
812 serial_outp(up, UART_SCR, 0xa5);
813 status1 = serial_in(up, UART_SCR);
814 serial_outp(up, UART_SCR, 0x5a);
815 status2 = serial_in(up, UART_SCR);
816 serial_outp(up, UART_SCR, scratch);
818 if (status1 == 0xa5 && status2 == 0x5a)
819 up->port.type = PORT_16450;
822 static int broken_efr(struct uart_8250_port *up)
825 * Exar ST16C2550 "A2" devices incorrectly detect as
826 * having an EFR, and report an ID of 0x0201. See
827 * http://www.exar.com/info.php?pdf=dan180_oct2004.pdf
829 if (autoconfig_read_divisor_id(up) == 0x0201 && size_fifo(up) == 16)
836 * We know that the chip has FIFOs. Does it have an EFR? The
837 * EFR is located in the same register position as the IIR and
838 * we know the top two bits of the IIR are currently set. The
839 * EFR should contain zero. Try to read the EFR.
841 static void autoconfig_16550a(struct uart_8250_port *up)
843 unsigned char status1, status2;
844 unsigned int iersave;
846 up->port.type = PORT_16550A;
847 up->capabilities |= UART_CAP_FIFO;
850 * Check for presence of the EFR when DLAB is set.
851 * Only ST16C650V1 UARTs pass this test.
853 serial_outp(up, UART_LCR, UART_LCR_DLAB);
854 if (serial_in(up, UART_EFR) == 0) {
855 serial_outp(up, UART_EFR, 0xA8);
856 if (serial_in(up, UART_EFR) != 0) {
857 DEBUG_AUTOCONF("EFRv1 ");
858 up->port.type = PORT_16650;
859 up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP;
861 DEBUG_AUTOCONF("Motorola 8xxx DUART ");
863 serial_outp(up, UART_EFR, 0);
868 * Maybe it requires 0xbf to be written to the LCR.
869 * (other ST16C650V2 UARTs, TI16C752A, etc)
871 serial_outp(up, UART_LCR, 0xBF);
872 if (serial_in(up, UART_EFR) == 0 && !broken_efr(up)) {
873 DEBUG_AUTOCONF("EFRv2 ");
874 autoconfig_has_efr(up);
879 * Check for a National Semiconductor SuperIO chip.
880 * Attempt to switch to bank 2, read the value of the LOOP bit
881 * from EXCR1. Switch back to bank 0, change it in MCR. Then
882 * switch back to bank 2, read it from EXCR1 again and check
883 * it's changed. If so, set baud_base in EXCR2 to 921600. -- dwmw2
885 serial_outp(up, UART_LCR, 0);
886 status1 = serial_in(up, UART_MCR);
887 serial_outp(up, UART_LCR, 0xE0);
888 status2 = serial_in(up, 0x02); /* EXCR1 */
890 if (!((status2 ^ status1) & UART_MCR_LOOP)) {
891 serial_outp(up, UART_LCR, 0);
892 serial_outp(up, UART_MCR, status1 ^ UART_MCR_LOOP);
893 serial_outp(up, UART_LCR, 0xE0);
894 status2 = serial_in(up, 0x02); /* EXCR1 */
895 serial_outp(up, UART_LCR, 0);
896 serial_outp(up, UART_MCR, status1);
898 if ((status2 ^ status1) & UART_MCR_LOOP) {
901 serial_outp(up, UART_LCR, 0xE0);
903 quot = serial_dl_read(up);
906 status1 = serial_in(up, 0x04); /* EXCR2 */
907 status1 &= ~0xB0; /* Disable LOCK, mask out PRESL[01] */
908 status1 |= 0x10; /* 1.625 divisor for baud_base --> 921600 */
909 serial_outp(up, 0x04, status1);
911 serial_dl_write(up, quot);
913 serial_outp(up, UART_LCR, 0);
915 up->port.uartclk = 921600*16;
916 up->port.type = PORT_NS16550A;
917 up->capabilities |= UART_NATSEMI;
923 * No EFR. Try to detect a TI16750, which only sets bit 5 of
924 * the IIR when 64 byte FIFO mode is enabled when DLAB is set.
925 * Try setting it with and without DLAB set. Cheap clones
926 * set bit 5 without DLAB set.
928 serial_outp(up, UART_LCR, 0);
929 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE);
930 status1 = serial_in(up, UART_IIR) >> 5;
931 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
932 serial_outp(up, UART_LCR, UART_LCR_DLAB);
933 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE);
934 status2 = serial_in(up, UART_IIR) >> 5;
935 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
936 serial_outp(up, UART_LCR, 0);
938 DEBUG_AUTOCONF("iir1=%d iir2=%d ", status1, status2);
940 if (status1 == 6 && status2 == 7) {
941 up->port.type = PORT_16750;
942 up->capabilities |= UART_CAP_AFE | UART_CAP_SLEEP;
947 * Try writing and reading the UART_IER_UUE bit (b6).
948 * If it works, this is probably one of the Xscale platform's
950 * We're going to explicitly set the UUE bit to 0 before
951 * trying to write and read a 1 just to make sure it's not
952 * already a 1 and maybe locked there before we even start start.
954 iersave = serial_in(up, UART_IER);
955 serial_outp(up, UART_IER, iersave & ~UART_IER_UUE);
956 if (!(serial_in(up, UART_IER) & UART_IER_UUE)) {
958 * OK it's in a known zero state, try writing and reading
959 * without disturbing the current state of the other bits.
961 serial_outp(up, UART_IER, iersave | UART_IER_UUE);
962 if (serial_in(up, UART_IER) & UART_IER_UUE) {
965 * We'll leave the UART_IER_UUE bit set to 1 (enabled).
967 DEBUG_AUTOCONF("Xscale ");
968 up->port.type = PORT_XSCALE;
969 up->capabilities |= UART_CAP_UUE;
974 * If we got here we couldn't force the IER_UUE bit to 0.
975 * Log it and continue.
977 DEBUG_AUTOCONF("Couldn't force IER_UUE to 0 ");
979 serial_outp(up, UART_IER, iersave);
983 * This routine is called by rs_init() to initialize a specific serial
984 * port. It determines what type of UART chip this serial port is
985 * using: 8250, 16450, 16550, 16550A. The important question is
986 * whether or not this UART is a 16550A or not, since this will
987 * determine whether or not we can use its FIFO features or not.
989 static void autoconfig(struct uart_8250_port *up, unsigned int probeflags)
991 unsigned char status1, scratch, scratch2, scratch3;
992 unsigned char save_lcr, save_mcr;
995 if (!up->port.iobase && !up->port.mapbase && !up->port.membase)
998 DEBUG_AUTOCONF("ttyS%d: autoconf (0x%04x, 0x%p): ",
999 up->port.line, up->port.iobase, up->port.membase);
1002 * We really do need global IRQs disabled here - we're going to
1003 * be frobbing the chips IRQ enable register to see if it exists.
1005 spin_lock_irqsave(&up->port.lock, flags);
1007 up->capabilities = 0;
1010 if (!(up->port.flags & UPF_BUGGY_UART)) {
1012 * Do a simple existence test first; if we fail this,
1013 * there's no point trying anything else.
1015 * 0x80 is used as a nonsense port to prevent against
1016 * false positives due to ISA bus float. The
1017 * assumption is that 0x80 is a non-existent port;
1018 * which should be safe since include/asm/io.h also
1019 * makes this assumption.
1021 * Note: this is safe as long as MCR bit 4 is clear
1022 * and the device is in "PC" mode.
1024 scratch = serial_inp(up, UART_IER);
1025 serial_outp(up, UART_IER, 0);
1030 * Mask out IER[7:4] bits for test as some UARTs (e.g. TL
1031 * 16C754B) allow only to modify them if an EFR bit is set.
1033 scratch2 = serial_inp(up, UART_IER) & 0x0f;
1034 serial_outp(up, UART_IER, 0x0F);
1038 scratch3 = serial_inp(up, UART_IER) & 0x0f;
1039 serial_outp(up, UART_IER, scratch);
1040 if (scratch2 != 0 || scratch3 != 0x0F) {
1042 * We failed; there's nothing here
1044 DEBUG_AUTOCONF("IER test failed (%02x, %02x) ",
1045 scratch2, scratch3);
1050 save_mcr = serial_in(up, UART_MCR);
1051 save_lcr = serial_in(up, UART_LCR);
1054 * Check to see if a UART is really there. Certain broken
1055 * internal modems based on the Rockwell chipset fail this
1056 * test, because they apparently don't implement the loopback
1057 * test mode. So this test is skipped on the COM 1 through
1058 * COM 4 ports. This *should* be safe, since no board
1059 * manufacturer would be stupid enough to design a board
1060 * that conflicts with COM 1-4 --- we hope!
1062 if (!(up->port.flags & UPF_SKIP_TEST)) {
1063 serial_outp(up, UART_MCR, UART_MCR_LOOP | 0x0A);
1064 status1 = serial_inp(up, UART_MSR) & 0xF0;
1065 serial_outp(up, UART_MCR, save_mcr);
1066 if (status1 != 0x90) {
1067 DEBUG_AUTOCONF("LOOP test failed (%02x) ",
1074 * We're pretty sure there's a port here. Lets find out what
1075 * type of port it is. The IIR top two bits allows us to find
1076 * out if it's 8250 or 16450, 16550, 16550A or later. This
1077 * determines what we test for next.
1079 * We also initialise the EFR (if any) to zero for later. The
1080 * EFR occupies the same register location as the FCR and IIR.
1082 serial_outp(up, UART_LCR, 0xBF);
1083 serial_outp(up, UART_EFR, 0);
1084 serial_outp(up, UART_LCR, 0);
1086 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1087 scratch = serial_in(up, UART_IIR) >> 6;
1089 DEBUG_AUTOCONF("iir=%d ", scratch);
1093 autoconfig_8250(up);
1096 up->port.type = PORT_UNKNOWN;
1099 up->port.type = PORT_16550;
1102 autoconfig_16550a(up);
1106 #ifdef CONFIG_SERIAL_8250_RSA
1108 * Only probe for RSA ports if we got the region.
1110 if (up->port.type == PORT_16550A && probeflags & PROBE_RSA) {
1113 for (i = 0 ; i < probe_rsa_count; ++i) {
1114 if (probe_rsa[i] == up->port.iobase &&
1116 up->port.type = PORT_RSA;
1123 #ifdef CONFIG_SERIAL_8250_AU1X00
1124 /* if access method is AU, it is a 16550 with a quirk */
1125 if (up->port.type == PORT_16550A && up->port.iotype == UPIO_AU)
1126 up->bugs |= UART_BUG_NOMSR;
1129 serial_outp(up, UART_LCR, save_lcr);
1131 if (up->capabilities != uart_config[up->port.type].flags) {
1133 "ttyS%d: detected caps %08x should be %08x\n",
1134 up->port.line, up->capabilities,
1135 uart_config[up->port.type].flags);
1138 up->port.fifosize = uart_config[up->port.type].fifo_size;
1139 up->capabilities = uart_config[up->port.type].flags;
1140 up->tx_loadsz = uart_config[up->port.type].tx_loadsz;
1142 if (up->port.type == PORT_UNKNOWN)
1148 #ifdef CONFIG_SERIAL_8250_RSA
1149 if (up->port.type == PORT_RSA)
1150 serial_outp(up, UART_RSA_FRR, 0);
1152 serial_outp(up, UART_MCR, save_mcr);
1153 serial8250_clear_fifos(up);
1154 serial_in(up, UART_RX);
1155 if (up->capabilities & UART_CAP_UUE)
1156 serial_outp(up, UART_IER, UART_IER_UUE);
1158 serial_outp(up, UART_IER, 0);
1161 spin_unlock_irqrestore(&up->port.lock, flags);
1162 DEBUG_AUTOCONF("type=%s\n", uart_config[up->port.type].name);
1165 static void autoconfig_irq(struct uart_8250_port *up)
1167 unsigned char save_mcr, save_ier;
1168 unsigned char save_ICP = 0;
1169 unsigned int ICP = 0;
1173 if (up->port.flags & UPF_FOURPORT) {
1174 ICP = (up->port.iobase & 0xfe0) | 0x1f;
1175 save_ICP = inb_p(ICP);
1180 /* forget possible initially masked and pending IRQ */
1181 probe_irq_off(probe_irq_on());
1182 save_mcr = serial_inp(up, UART_MCR);
1183 save_ier = serial_inp(up, UART_IER);
1184 serial_outp(up, UART_MCR, UART_MCR_OUT1 | UART_MCR_OUT2);
1186 irqs = probe_irq_on();
1187 serial_outp(up, UART_MCR, 0);
1189 if (up->port.flags & UPF_FOURPORT) {
1190 serial_outp(up, UART_MCR,
1191 UART_MCR_DTR | UART_MCR_RTS);
1193 serial_outp(up, UART_MCR,
1194 UART_MCR_DTR | UART_MCR_RTS | UART_MCR_OUT2);
1196 serial_outp(up, UART_IER, 0x0f); /* enable all intrs */
1197 (void)serial_inp(up, UART_LSR);
1198 (void)serial_inp(up, UART_RX);
1199 (void)serial_inp(up, UART_IIR);
1200 (void)serial_inp(up, UART_MSR);
1201 serial_outp(up, UART_TX, 0xFF);
1203 irq = probe_irq_off(irqs);
1205 serial_outp(up, UART_MCR, save_mcr);
1206 serial_outp(up, UART_IER, save_ier);
1208 if (up->port.flags & UPF_FOURPORT)
1209 outb_p(save_ICP, ICP);
1211 up->port.irq = (irq > 0) ? irq : 0;
1214 static inline void __stop_tx(struct uart_8250_port *p)
1216 if (p->ier & UART_IER_THRI) {
1217 p->ier &= ~UART_IER_THRI;
1218 serial_out(p, UART_IER, p->ier);
1222 static void serial8250_stop_tx(struct uart_port *port)
1224 struct uart_8250_port *up = (struct uart_8250_port *)port;
1229 * We really want to stop the transmitter from sending.
1231 if (up->port.type == PORT_16C950) {
1232 up->acr |= UART_ACR_TXDIS;
1233 serial_icr_write(up, UART_ACR, up->acr);
1237 static void transmit_chars(struct uart_8250_port *up);
1239 static void serial8250_start_tx(struct uart_port *port)
1241 struct uart_8250_port *up = (struct uart_8250_port *)port;
1243 if (!(up->ier & UART_IER_THRI)) {
1244 up->ier |= UART_IER_THRI;
1245 serial_out(up, UART_IER, up->ier);
1247 if (up->bugs & UART_BUG_TXEN) {
1248 unsigned char lsr, iir;
1249 lsr = serial_in(up, UART_LSR);
1250 up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS;
1251 iir = serial_in(up, UART_IIR) & 0x0f;
1252 if ((up->port.type == PORT_RM9000) ?
1253 (lsr & UART_LSR_THRE &&
1254 (iir == UART_IIR_NO_INT || iir == UART_IIR_THRI)) :
1255 (lsr & UART_LSR_TEMT && iir & UART_IIR_NO_INT))
1261 * Re-enable the transmitter if we disabled it.
1263 if (up->port.type == PORT_16C950 && up->acr & UART_ACR_TXDIS) {
1264 up->acr &= ~UART_ACR_TXDIS;
1265 serial_icr_write(up, UART_ACR, up->acr);
1269 static void serial8250_stop_rx(struct uart_port *port)
1271 struct uart_8250_port *up = (struct uart_8250_port *)port;
1273 up->ier &= ~UART_IER_RLSI;
1274 up->port.read_status_mask &= ~UART_LSR_DR;
1275 serial_out(up, UART_IER, up->ier);
1278 static void serial8250_enable_ms(struct uart_port *port)
1280 struct uart_8250_port *up = (struct uart_8250_port *)port;
1282 /* no MSR capabilities */
1283 if (up->bugs & UART_BUG_NOMSR)
1286 up->ier |= UART_IER_MSI;
1287 serial_out(up, UART_IER, up->ier);
1291 receive_chars(struct uart_8250_port *up, unsigned int *status)
1293 struct tty_struct *tty = up->port.info->tty;
1294 unsigned char ch, lsr = *status;
1295 int max_count = 256;
1299 ch = serial_inp(up, UART_RX);
1301 up->port.icount.rx++;
1303 lsr |= up->lsr_saved_flags;
1304 up->lsr_saved_flags = 0;
1306 if (unlikely(lsr & UART_LSR_BRK_ERROR_BITS)) {
1308 * For statistics only
1310 if (lsr & UART_LSR_BI) {
1311 lsr &= ~(UART_LSR_FE | UART_LSR_PE);
1312 up->port.icount.brk++;
1314 * We do the SysRQ and SAK checking
1315 * here because otherwise the break
1316 * may get masked by ignore_status_mask
1317 * or read_status_mask.
1319 if (uart_handle_break(&up->port))
1321 } else if (lsr & UART_LSR_PE)
1322 up->port.icount.parity++;
1323 else if (lsr & UART_LSR_FE)
1324 up->port.icount.frame++;
1325 if (lsr & UART_LSR_OE)
1326 up->port.icount.overrun++;
1329 * Mask off conditions which should be ignored.
1331 lsr &= up->port.read_status_mask;
1333 if (lsr & UART_LSR_BI) {
1334 DEBUG_INTR("handling break....");
1336 } else if (lsr & UART_LSR_PE)
1338 else if (lsr & UART_LSR_FE)
1341 if (uart_handle_sysrq_char(&up->port, ch))
1344 uart_insert_char(&up->port, lsr, UART_LSR_OE, ch, flag);
1347 lsr = serial_inp(up, UART_LSR);
1348 } while ((lsr & UART_LSR_DR) && (max_count-- > 0));
1349 spin_unlock(&up->port.lock);
1350 tty_flip_buffer_push(tty);
1351 spin_lock(&up->port.lock);
1355 static void transmit_chars(struct uart_8250_port *up)
1357 struct circ_buf *xmit = &up->port.info->xmit;
1360 if (up->port.x_char) {
1361 serial_outp(up, UART_TX, up->port.x_char);
1362 up->port.icount.tx++;
1363 up->port.x_char = 0;
1366 if (uart_tx_stopped(&up->port)) {
1367 serial8250_stop_tx(&up->port);
1370 if (uart_circ_empty(xmit)) {
1375 count = up->tx_loadsz;
1377 serial_out(up, UART_TX, xmit->buf[xmit->tail]);
1378 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
1379 up->port.icount.tx++;
1380 if (uart_circ_empty(xmit))
1382 } while (--count > 0);
1384 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1385 uart_write_wakeup(&up->port);
1387 DEBUG_INTR("THRE...");
1389 if (uart_circ_empty(xmit))
1393 static unsigned int check_modem_status(struct uart_8250_port *up)
1395 unsigned int status = serial_in(up, UART_MSR);
1397 status |= up->msr_saved_flags;
1398 up->msr_saved_flags = 0;
1399 if (status & UART_MSR_ANY_DELTA && up->ier & UART_IER_MSI &&
1400 up->port.info != NULL) {
1401 if (status & UART_MSR_TERI)
1402 up->port.icount.rng++;
1403 if (status & UART_MSR_DDSR)
1404 up->port.icount.dsr++;
1405 if (status & UART_MSR_DDCD)
1406 uart_handle_dcd_change(&up->port, status & UART_MSR_DCD);
1407 if (status & UART_MSR_DCTS)
1408 uart_handle_cts_change(&up->port, status & UART_MSR_CTS);
1410 wake_up_interruptible(&up->port.info->delta_msr_wait);
1417 * This handles the interrupt from one port.
1420 serial8250_handle_port(struct uart_8250_port *up)
1422 unsigned int status;
1423 unsigned long flags;
1425 spin_lock_irqsave(&up->port.lock, flags);
1427 status = serial_inp(up, UART_LSR);
1429 DEBUG_INTR("status = %x...", status);
1431 if (status & UART_LSR_DR)
1432 receive_chars(up, &status);
1433 check_modem_status(up);
1434 if (status & UART_LSR_THRE)
1437 spin_unlock_irqrestore(&up->port.lock, flags);
1441 * This is the serial driver's interrupt routine.
1443 * Arjan thinks the old way was overly complex, so it got simplified.
1444 * Alan disagrees, saying that need the complexity to handle the weird
1445 * nature of ISA shared interrupts. (This is a special exception.)
1447 * In order to handle ISA shared interrupts properly, we need to check
1448 * that all ports have been serviced, and therefore the ISA interrupt
1449 * line has been de-asserted.
1451 * This means we need to loop through all ports. checking that they
1452 * don't have an interrupt pending.
1454 static irqreturn_t serial8250_interrupt(int irq, void *dev_id)
1456 struct irq_info *i = dev_id;
1457 struct list_head *l, *end = NULL;
1458 int pass_counter = 0, handled = 0;
1460 DEBUG_INTR("serial8250_interrupt(%d)...", irq);
1462 spin_lock(&i->lock);
1466 struct uart_8250_port *up;
1469 up = list_entry(l, struct uart_8250_port, list);
1471 iir = serial_in(up, UART_IIR);
1472 if (!(iir & UART_IIR_NO_INT)) {
1473 serial8250_handle_port(up);
1478 } else if (up->port.iotype == UPIO_DWAPB &&
1479 (iir & UART_IIR_BUSY) == UART_IIR_BUSY) {
1480 /* The DesignWare APB UART has an Busy Detect (0x07)
1481 * interrupt meaning an LCR write attempt occured while the
1482 * UART was busy. The interrupt must be cleared by reading
1483 * the UART status register (USR) and the LCR re-written. */
1484 unsigned int status;
1485 status = *(volatile u32 *)up->port.private_data;
1486 serial_out(up, UART_LCR, up->lcr);
1491 } else if (end == NULL)
1496 if (l == i->head && pass_counter++ > PASS_LIMIT) {
1497 /* If we hit this, we're dead. */
1498 printk(KERN_ERR "serial8250: too much work for "
1504 spin_unlock(&i->lock);
1506 DEBUG_INTR("end.\n");
1508 #ifdef CONFIG_ARCH_OMAP15XX
1509 return IRQ_HANDLED; /* FIXME: iir status not ready on 1510 */
1511 return IRQ_RETVAL(handled);
1516 * To support ISA shared interrupts, we need to have one interrupt
1517 * handler that ensures that the IRQ line has been deasserted
1518 * before returning. Failing to do this will result in the IRQ
1519 * line being stuck active, and, since ISA irqs are edge triggered,
1520 * no more IRQs will be seen.
1522 static void serial_do_unlink(struct irq_info *i, struct uart_8250_port *up)
1524 spin_lock_irq(&i->lock);
1526 if (!list_empty(i->head)) {
1527 if (i->head == &up->list)
1528 i->head = i->head->next;
1529 list_del(&up->list);
1531 BUG_ON(i->head != &up->list);
1535 spin_unlock_irq(&i->lock);
1538 static int serial_link_irq_chain(struct uart_8250_port *up)
1540 struct irq_info *i = irq_lists + up->port.irq;
1541 int ret, irq_flags = up->port.flags & UPF_SHARE_IRQ ? IRQF_SHARED : 0;
1543 spin_lock_irq(&i->lock);
1546 list_add(&up->list, i->head);
1547 spin_unlock_irq(&i->lock);
1551 INIT_LIST_HEAD(&up->list);
1552 i->head = &up->list;
1553 spin_unlock_irq(&i->lock);
1555 ret = request_irq(up->port.irq, serial8250_interrupt,
1556 irq_flags, "serial", i);
1558 serial_do_unlink(i, up);
1564 static void serial_unlink_irq_chain(struct uart_8250_port *up)
1566 struct irq_info *i = irq_lists + up->port.irq;
1568 BUG_ON(i->head == NULL);
1570 if (list_empty(i->head))
1571 free_irq(up->port.irq, i);
1573 serial_do_unlink(i, up);
1576 /* Base timer interval for polling */
1577 static inline int poll_timeout(int timeout)
1579 return timeout > 6 ? (timeout / 2 - 2) : 1;
1583 * This function is used to handle ports that do not have an
1584 * interrupt. This doesn't work very well for 16450's, but gives
1585 * barely passable results for a 16550A. (Although at the expense
1586 * of much CPU overhead).
1588 static void serial8250_timeout(unsigned long data)
1590 struct uart_8250_port *up = (struct uart_8250_port *)data;
1593 iir = serial_in(up, UART_IIR);
1594 if (!(iir & UART_IIR_NO_INT))
1595 serial8250_handle_port(up);
1596 mod_timer(&up->timer, jiffies + poll_timeout(up->port.timeout));
1599 static void serial8250_backup_timeout(unsigned long data)
1601 struct uart_8250_port *up = (struct uart_8250_port *)data;
1602 unsigned int iir, ier = 0, lsr;
1603 unsigned long flags;
1606 * Must disable interrupts or else we risk racing with the interrupt
1609 if (is_real_interrupt(up->port.irq)) {
1610 ier = serial_in(up, UART_IER);
1611 serial_out(up, UART_IER, 0);
1614 iir = serial_in(up, UART_IIR);
1617 * This should be a safe test for anyone who doesn't trust the
1618 * IIR bits on their UART, but it's specifically designed for
1619 * the "Diva" UART used on the management processor on many HP
1620 * ia64 and parisc boxes.
1622 spin_lock_irqsave(&up->port.lock, flags);
1623 lsr = serial_in(up, UART_LSR);
1624 up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS;
1625 spin_unlock_irqrestore(&up->port.lock, flags);
1626 if ((iir & UART_IIR_NO_INT) && (up->ier & UART_IER_THRI) &&
1627 (!uart_circ_empty(&up->port.info->xmit) || up->port.x_char) &&
1628 (lsr & UART_LSR_THRE)) {
1629 iir &= ~(UART_IIR_ID | UART_IIR_NO_INT);
1630 iir |= UART_IIR_THRI;
1633 if (!(iir & UART_IIR_NO_INT))
1634 serial8250_handle_port(up);
1636 if (is_real_interrupt(up->port.irq))
1637 serial_out(up, UART_IER, ier);
1639 /* Standard timer interval plus 0.2s to keep the port running */
1640 mod_timer(&up->timer, jiffies + poll_timeout(up->port.timeout) + HZ/5);
1643 static unsigned int serial8250_tx_empty(struct uart_port *port)
1645 struct uart_8250_port *up = (struct uart_8250_port *)port;
1646 unsigned long flags;
1649 spin_lock_irqsave(&up->port.lock, flags);
1650 lsr = serial_in(up, UART_LSR);
1651 up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS;
1652 spin_unlock_irqrestore(&up->port.lock, flags);
1654 return lsr & UART_LSR_TEMT ? TIOCSER_TEMT : 0;
1657 static unsigned int serial8250_get_mctrl(struct uart_port *port)
1659 struct uart_8250_port *up = (struct uart_8250_port *)port;
1660 unsigned int status;
1663 status = check_modem_status(up);
1666 if (status & UART_MSR_DCD)
1668 if (status & UART_MSR_RI)
1670 if (status & UART_MSR_DSR)
1672 if (status & UART_MSR_CTS)
1677 static void serial8250_set_mctrl(struct uart_port *port, unsigned int mctrl)
1679 struct uart_8250_port *up = (struct uart_8250_port *)port;
1680 unsigned char mcr = 0;
1682 if (mctrl & TIOCM_RTS)
1683 mcr |= UART_MCR_RTS;
1684 if (mctrl & TIOCM_DTR)
1685 mcr |= UART_MCR_DTR;
1686 if (mctrl & TIOCM_OUT1)
1687 mcr |= UART_MCR_OUT1;
1688 if (mctrl & TIOCM_OUT2)
1689 mcr |= UART_MCR_OUT2;
1690 if (mctrl & TIOCM_LOOP)
1691 mcr |= UART_MCR_LOOP;
1693 mcr = (mcr & up->mcr_mask) | up->mcr_force | up->mcr;
1695 serial_out(up, UART_MCR, mcr);
1698 static void serial8250_break_ctl(struct uart_port *port, int break_state)
1700 struct uart_8250_port *up = (struct uart_8250_port *)port;
1701 unsigned long flags;
1703 spin_lock_irqsave(&up->port.lock, flags);
1704 if (break_state == -1)
1705 up->lcr |= UART_LCR_SBC;
1707 up->lcr &= ~UART_LCR_SBC;
1708 serial_out(up, UART_LCR, up->lcr);
1709 spin_unlock_irqrestore(&up->port.lock, flags);
1712 #define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
1715 * Wait for transmitter & holding register to empty
1717 static inline void wait_for_xmitr(struct uart_8250_port *up, int bits)
1719 unsigned int status, tmout = 10000;
1721 /* Wait up to 10ms for the character(s) to be sent. */
1723 status = serial_in(up, UART_LSR);
1725 up->lsr_saved_flags |= status & LSR_SAVE_FLAGS;
1730 } while ((status & bits) != bits);
1732 /* Wait up to 1s for flow control if necessary */
1733 if (up->port.flags & UPF_CONS_FLOW) {
1735 for (tmout = 1000000; tmout; tmout--) {
1736 unsigned int msr = serial_in(up, UART_MSR);
1737 up->msr_saved_flags |= msr & MSR_SAVE_FLAGS;
1738 if (msr & UART_MSR_CTS)
1741 touch_nmi_watchdog();
1746 static int serial8250_startup(struct uart_port *port)
1748 struct uart_8250_port *up = (struct uart_8250_port *)port;
1749 unsigned long flags;
1750 unsigned char lsr, iir;
1753 up->capabilities = uart_config[up->port.type].flags;
1756 if (up->port.type == PORT_16C950) {
1757 /* Wake up and initialize UART */
1759 serial_outp(up, UART_LCR, 0xBF);
1760 serial_outp(up, UART_EFR, UART_EFR_ECB);
1761 serial_outp(up, UART_IER, 0);
1762 serial_outp(up, UART_LCR, 0);
1763 serial_icr_write(up, UART_CSR, 0); /* Reset the UART */
1764 serial_outp(up, UART_LCR, 0xBF);
1765 serial_outp(up, UART_EFR, UART_EFR_ECB);
1766 serial_outp(up, UART_LCR, 0);
1769 #ifdef CONFIG_SERIAL_8250_RSA
1771 * If this is an RSA port, see if we can kick it up to the
1772 * higher speed clock.
1778 * Clear the FIFO buffers and disable them.
1779 * (they will be reenabled in set_termios())
1781 serial8250_clear_fifos(up);
1784 * Clear the interrupt registers.
1786 (void) serial_inp(up, UART_LSR);
1787 (void) serial_inp(up, UART_RX);
1788 (void) serial_inp(up, UART_IIR);
1789 (void) serial_inp(up, UART_MSR);
1792 * At this point, there's no way the LSR could still be 0xff;
1793 * if it is, then bail out, because there's likely no UART
1796 if (!(up->port.flags & UPF_BUGGY_UART) &&
1797 (serial_inp(up, UART_LSR) == 0xff)) {
1798 printk("ttyS%d: LSR safety check engaged!\n", up->port.line);
1803 * For a XR16C850, we need to set the trigger levels
1805 if (up->port.type == PORT_16850) {
1808 serial_outp(up, UART_LCR, 0xbf);
1810 fctr = serial_inp(up, UART_FCTR) & ~(UART_FCTR_RX|UART_FCTR_TX);
1811 serial_outp(up, UART_FCTR, fctr | UART_FCTR_TRGD | UART_FCTR_RX);
1812 serial_outp(up, UART_TRG, UART_TRG_96);
1813 serial_outp(up, UART_FCTR, fctr | UART_FCTR_TRGD | UART_FCTR_TX);
1814 serial_outp(up, UART_TRG, UART_TRG_96);
1816 serial_outp(up, UART_LCR, 0);
1819 if (is_real_interrupt(up->port.irq)) {
1821 * Test for UARTs that do not reassert THRE when the
1822 * transmitter is idle and the interrupt has already
1823 * been cleared. Real 16550s should always reassert
1824 * this interrupt whenever the transmitter is idle and
1825 * the interrupt is enabled. Delays are necessary to
1826 * allow register changes to become visible.
1828 spin_lock_irqsave(&up->port.lock, flags);
1830 wait_for_xmitr(up, UART_LSR_THRE);
1831 serial_out_sync(up, UART_IER, UART_IER_THRI);
1832 udelay(1); /* allow THRE to set */
1833 serial_in(up, UART_IIR);
1834 serial_out(up, UART_IER, 0);
1835 serial_out_sync(up, UART_IER, UART_IER_THRI);
1836 udelay(1); /* allow a working UART time to re-assert THRE */
1837 iir = serial_in(up, UART_IIR);
1838 serial_out(up, UART_IER, 0);
1840 spin_unlock_irqrestore(&up->port.lock, flags);
1843 * If the interrupt is not reasserted, setup a timer to
1844 * kick the UART on a regular basis.
1846 if (iir & UART_IIR_NO_INT) {
1847 pr_debug("ttyS%d - using backup timer\n", port->line);
1848 up->timer.function = serial8250_backup_timeout;
1849 up->timer.data = (unsigned long)up;
1850 mod_timer(&up->timer, jiffies +
1851 poll_timeout(up->port.timeout) + HZ/5);
1856 * If the "interrupt" for this port doesn't correspond with any
1857 * hardware interrupt, we use a timer-based system. The original
1858 * driver used to do this with IRQ0.
1860 if (!is_real_interrupt(up->port.irq)) {
1861 up->timer.data = (unsigned long)up;
1862 mod_timer(&up->timer, jiffies + poll_timeout(up->port.timeout));
1864 retval = serial_link_irq_chain(up);
1870 * Now, initialize the UART
1872 serial_outp(up, UART_LCR, UART_LCR_WLEN8);
1874 spin_lock_irqsave(&up->port.lock, flags);
1875 if (up->port.flags & UPF_FOURPORT) {
1876 if (!is_real_interrupt(up->port.irq))
1877 up->port.mctrl |= TIOCM_OUT1;
1880 * Most PC uarts need OUT2 raised to enable interrupts.
1882 if (is_real_interrupt(up->port.irq))
1883 up->port.mctrl |= TIOCM_OUT2;
1885 serial8250_set_mctrl(&up->port, up->port.mctrl);
1888 * Do a quick test to see if we receive an
1889 * interrupt when we enable the TX irq.
1891 serial_outp(up, UART_IER, UART_IER_THRI);
1892 lsr = serial_in(up, UART_LSR);
1893 iir = serial_in(up, UART_IIR);
1894 serial_outp(up, UART_IER, 0);
1896 if (lsr & UART_LSR_TEMT && iir & UART_IIR_NO_INT) {
1897 if (!(up->bugs & UART_BUG_TXEN)) {
1898 up->bugs |= UART_BUG_TXEN;
1899 pr_debug("ttyS%d - enabling bad tx status workarounds\n",
1903 up->bugs &= ~UART_BUG_TXEN;
1906 spin_unlock_irqrestore(&up->port.lock, flags);
1909 * Clear the interrupt registers again for luck, and clear the
1910 * saved flags to avoid getting false values from polling
1911 * routines or the previous session.
1913 serial_inp(up, UART_LSR);
1914 serial_inp(up, UART_RX);
1915 serial_inp(up, UART_IIR);
1916 serial_inp(up, UART_MSR);
1917 up->lsr_saved_flags = 0;
1918 up->msr_saved_flags = 0;
1921 * Finally, enable interrupts. Note: Modem status interrupts
1922 * are set via set_termios(), which will be occurring imminently
1923 * anyway, so we don't enable them here.
1925 up->ier = UART_IER_RLSI | UART_IER_RDI;
1926 serial_outp(up, UART_IER, up->ier);
1928 if (up->port.flags & UPF_FOURPORT) {
1931 * Enable interrupts on the AST Fourport board
1933 icp = (up->port.iobase & 0xfe0) | 0x01f;
1941 static void serial8250_shutdown(struct uart_port *port)
1943 struct uart_8250_port *up = (struct uart_8250_port *)port;
1944 unsigned long flags;
1947 * Disable interrupts from this port
1950 serial_outp(up, UART_IER, 0);
1952 spin_lock_irqsave(&up->port.lock, flags);
1953 if (up->port.flags & UPF_FOURPORT) {
1954 /* reset interrupts on the AST Fourport board */
1955 inb((up->port.iobase & 0xfe0) | 0x1f);
1956 up->port.mctrl |= TIOCM_OUT1;
1958 up->port.mctrl &= ~TIOCM_OUT2;
1960 serial8250_set_mctrl(&up->port, up->port.mctrl);
1961 spin_unlock_irqrestore(&up->port.lock, flags);
1964 * Disable break condition and FIFOs
1966 serial_out(up, UART_LCR, serial_inp(up, UART_LCR) & ~UART_LCR_SBC);
1967 serial8250_clear_fifos(up);
1969 #ifdef CONFIG_SERIAL_8250_RSA
1971 * Reset the RSA board back to 115kbps compat mode.
1977 * Read data port to reset things, and then unlink from
1980 (void) serial_in(up, UART_RX);
1982 del_timer_sync(&up->timer);
1983 up->timer.function = serial8250_timeout;
1984 if (is_real_interrupt(up->port.irq))
1985 serial_unlink_irq_chain(up);
1988 static unsigned int serial8250_get_divisor(struct uart_port *port, unsigned int baud)
1993 * Handle magic divisors for baud rates above baud_base on
1994 * SMSC SuperIO chips.
1996 if ((port->flags & UPF_MAGIC_MULTIPLIER) &&
1997 baud == (port->uartclk/4))
1999 else if ((port->flags & UPF_MAGIC_MULTIPLIER) &&
2000 baud == (port->uartclk/8))
2003 quot = uart_get_divisor(port, baud);
2009 serial8250_set_termios(struct uart_port *port, struct ktermios *termios,
2010 struct ktermios *old)
2012 struct uart_8250_port *up = (struct uart_8250_port *)port;
2013 unsigned char cval, fcr = 0;
2014 unsigned long flags;
2015 unsigned int baud, quot;
2017 switch (termios->c_cflag & CSIZE) {
2019 cval = UART_LCR_WLEN5;
2022 cval = UART_LCR_WLEN6;
2025 cval = UART_LCR_WLEN7;
2029 cval = UART_LCR_WLEN8;
2033 if (termios->c_cflag & CSTOPB)
2034 cval |= UART_LCR_STOP;
2035 if (termios->c_cflag & PARENB)
2036 cval |= UART_LCR_PARITY;
2037 if (!(termios->c_cflag & PARODD))
2038 cval |= UART_LCR_EPAR;
2040 if (termios->c_cflag & CMSPAR)
2041 cval |= UART_LCR_SPAR;
2045 * Ask the core to calculate the divisor for us.
2047 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16);
2048 quot = serial8250_get_divisor(port, baud);
2051 * Oxford Semi 952 rev B workaround
2053 if (up->bugs & UART_BUG_QUOT && (quot & 0xff) == 0)
2056 if (up->capabilities & UART_CAP_FIFO && up->port.fifosize > 1) {
2058 fcr = UART_FCR_ENABLE_FIFO | UART_FCR_TRIGGER_1;
2060 fcr = uart_config[up->port.type].fcr;
2064 * MCR-based auto flow control. When AFE is enabled, RTS will be
2065 * deasserted when the receive FIFO contains more characters than
2066 * the trigger, or the MCR RTS bit is cleared. In the case where
2067 * the remote UART is not using CTS auto flow control, we must
2068 * have sufficient FIFO entries for the latency of the remote
2069 * UART to respond. IOW, at least 32 bytes of FIFO.
2071 if (up->capabilities & UART_CAP_AFE && up->port.fifosize >= 32) {
2072 up->mcr &= ~UART_MCR_AFE;
2073 if (termios->c_cflag & CRTSCTS)
2074 up->mcr |= UART_MCR_AFE;
2078 * Ok, we're now changing the port state. Do it with
2079 * interrupts disabled.
2081 spin_lock_irqsave(&up->port.lock, flags);
2084 * Update the per-port timeout.
2086 uart_update_timeout(port, termios->c_cflag, baud);
2088 up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
2089 if (termios->c_iflag & INPCK)
2090 up->port.read_status_mask |= UART_LSR_FE | UART_LSR_PE;
2091 if (termios->c_iflag & (BRKINT | PARMRK))
2092 up->port.read_status_mask |= UART_LSR_BI;
2095 * Characteres to ignore
2097 up->port.ignore_status_mask = 0;
2098 if (termios->c_iflag & IGNPAR)
2099 up->port.ignore_status_mask |= UART_LSR_PE | UART_LSR_FE;
2100 if (termios->c_iflag & IGNBRK) {
2101 up->port.ignore_status_mask |= UART_LSR_BI;
2103 * If we're ignoring parity and break indicators,
2104 * ignore overruns too (for real raw support).
2106 if (termios->c_iflag & IGNPAR)
2107 up->port.ignore_status_mask |= UART_LSR_OE;
2111 * ignore all characters if CREAD is not set
2113 if ((termios->c_cflag & CREAD) == 0)
2114 up->port.ignore_status_mask |= UART_LSR_DR;
2117 * CTS flow control flag and modem status interrupts
2119 up->ier &= ~UART_IER_MSI;
2120 if (!(up->bugs & UART_BUG_NOMSR) &&
2121 UART_ENABLE_MS(&up->port, termios->c_cflag))
2122 up->ier |= UART_IER_MSI;
2123 if (up->capabilities & UART_CAP_UUE)
2124 up->ier |= UART_IER_UUE | UART_IER_RTOIE;
2126 serial_out(up, UART_IER, up->ier);
2128 if (up->capabilities & UART_CAP_EFR) {
2129 unsigned char efr = 0;
2131 * TI16C752/Startech hardware flow control. FIXME:
2132 * - TI16C752 requires control thresholds to be set.
2133 * - UART_MCR_RTS is ineffective if auto-RTS mode is enabled.
2135 if (termios->c_cflag & CRTSCTS)
2136 efr |= UART_EFR_CTS;
2138 serial_outp(up, UART_LCR, 0xBF);
2139 serial_outp(up, UART_EFR, efr);
2142 #ifdef CONFIG_ARCH_OMAP15XX
2143 /* Workaround to enable 115200 baud on OMAP1510 internal ports */
2144 if (cpu_is_omap1510() && is_omap_port((unsigned int)up->port.membase)) {
2145 if (baud == 115200) {
2147 serial_out(up, UART_OMAP_OSC_12M_SEL, 1);
2149 serial_out(up, UART_OMAP_OSC_12M_SEL, 0);
2153 if (up->capabilities & UART_NATSEMI) {
2154 /* Switch to bank 2 not bank 1, to avoid resetting EXCR2 */
2155 serial_outp(up, UART_LCR, 0xe0);
2157 serial_outp(up, UART_LCR, cval | UART_LCR_DLAB);/* set DLAB */
2160 serial_dl_write(up, quot);
2163 * LCR DLAB must be set to enable 64-byte FIFO mode. If the FCR
2164 * is written without DLAB set, this mode will be disabled.
2166 if (up->port.type == PORT_16750)
2167 serial_outp(up, UART_FCR, fcr);
2169 serial_outp(up, UART_LCR, cval); /* reset DLAB */
2170 up->lcr = cval; /* Save LCR */
2171 if (up->port.type != PORT_16750) {
2172 if (fcr & UART_FCR_ENABLE_FIFO) {
2173 /* emulated UARTs (Lucent Venus 167x) need two steps */
2174 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
2177 /* Note that we need to set ECB to access write water mark
2178 * bits. First allow FCR tx fifo write, then set fcr with
2179 * possible TX fifo settings. */
2180 if (uart_config[up->port.type].flags & UART_CAP_EFR) {
2181 serial_outp(up, UART_LCR, 0xbf); /* Access EFR */
2182 serial_outp(up, UART_EFR, UART_EFR_ECB);
2183 serial_outp(up, UART_LCR, 0x0); /* Access FCR */
2184 serial_outp(up, UART_FCR, fcr);
2185 serial_outp(up, UART_LCR, 0xbf); /* Access EFR */
2186 serial_outp(up, UART_EFR, 0);
2187 serial_outp(up, UART_LCR, cval); /* Access FCR */
2189 serial_outp(up, UART_FCR, fcr); /* set fcr */
2191 serial8250_set_mctrl(&up->port, up->port.mctrl);
2192 spin_unlock_irqrestore(&up->port.lock, flags);
2196 serial8250_pm(struct uart_port *port, unsigned int state,
2197 unsigned int oldstate)
2199 struct uart_8250_port *p = (struct uart_8250_port *)port;
2201 serial8250_set_sleep(p, state != 0);
2204 p->pm(port, state, oldstate);
2208 * Resource handling.
2210 static int serial8250_request_std_resource(struct uart_8250_port *up)
2212 unsigned int size = 8 << up->port.regshift;
2215 #ifdef CONFIG_ARCH_OMAP
2216 if (is_omap_port((unsigned int)up->port.membase))
2217 size = 0x16 << up->port.regshift;
2220 switch (up->port.iotype) {
2228 if (!up->port.mapbase)
2231 if (!request_mem_region(up->port.mapbase, size, "serial")) {
2236 if (up->port.flags & UPF_IOREMAP) {
2237 up->port.membase = ioremap(up->port.mapbase, size);
2238 if (!up->port.membase) {
2239 release_mem_region(up->port.mapbase, size);
2247 if (!request_region(up->port.iobase, size, "serial"))
2254 static void serial8250_release_std_resource(struct uart_8250_port *up)
2256 unsigned int size = 8 << up->port.regshift;
2258 switch (up->port.iotype) {
2266 if (!up->port.mapbase)
2269 if (up->port.flags & UPF_IOREMAP) {
2270 iounmap(up->port.membase);
2271 up->port.membase = NULL;
2274 release_mem_region(up->port.mapbase, size);
2279 release_region(up->port.iobase, size);
2284 static int serial8250_request_rsa_resource(struct uart_8250_port *up)
2286 unsigned long start = UART_RSA_BASE << up->port.regshift;
2287 unsigned int size = 8 << up->port.regshift;
2290 switch (up->port.iotype) {
2293 start += up->port.iobase;
2294 if (request_region(start, size, "serial-rsa"))
2304 static void serial8250_release_rsa_resource(struct uart_8250_port *up)
2306 unsigned long offset = UART_RSA_BASE << up->port.regshift;
2307 unsigned int size = 8 << up->port.regshift;
2309 switch (up->port.iotype) {
2312 release_region(up->port.iobase + offset, size);
2317 static void serial8250_release_port(struct uart_port *port)
2319 struct uart_8250_port *up = (struct uart_8250_port *)port;
2321 serial8250_release_std_resource(up);
2322 if (up->port.type == PORT_RSA)
2323 serial8250_release_rsa_resource(up);
2326 static int serial8250_request_port(struct uart_port *port)
2328 struct uart_8250_port *up = (struct uart_8250_port *)port;
2331 ret = serial8250_request_std_resource(up);
2332 if (ret == 0 && up->port.type == PORT_RSA) {
2333 ret = serial8250_request_rsa_resource(up);
2335 serial8250_release_std_resource(up);
2341 static void serial8250_config_port(struct uart_port *port, int flags)
2343 struct uart_8250_port *up = (struct uart_8250_port *)port;
2344 int probeflags = PROBE_ANY;
2348 * Find the region that we can probe for. This in turn
2349 * tells us whether we can probe for the type of port.
2351 ret = serial8250_request_std_resource(up);
2355 ret = serial8250_request_rsa_resource(up);
2357 probeflags &= ~PROBE_RSA;
2359 if (flags & UART_CONFIG_TYPE)
2360 autoconfig(up, probeflags);
2361 if (up->port.type != PORT_UNKNOWN && flags & UART_CONFIG_IRQ)
2364 if (up->port.type != PORT_RSA && probeflags & PROBE_RSA)
2365 serial8250_release_rsa_resource(up);
2366 if (up->port.type == PORT_UNKNOWN)
2367 serial8250_release_std_resource(up);
2371 serial8250_verify_port(struct uart_port *port, struct serial_struct *ser)
2373 if (ser->irq >= NR_IRQS || ser->irq < 0 ||
2374 ser->baud_base < 9600 || ser->type < PORT_UNKNOWN ||
2375 ser->type >= ARRAY_SIZE(uart_config) || ser->type == PORT_CIRRUS ||
2376 ser->type == PORT_STARTECH)
2382 serial8250_type(struct uart_port *port)
2384 int type = port->type;
2386 if (type >= ARRAY_SIZE(uart_config))
2388 return uart_config[type].name;
2391 static struct uart_ops serial8250_pops = {
2392 .tx_empty = serial8250_tx_empty,
2393 .set_mctrl = serial8250_set_mctrl,
2394 .get_mctrl = serial8250_get_mctrl,
2395 .stop_tx = serial8250_stop_tx,
2396 .start_tx = serial8250_start_tx,
2397 .stop_rx = serial8250_stop_rx,
2398 .enable_ms = serial8250_enable_ms,
2399 .break_ctl = serial8250_break_ctl,
2400 .startup = serial8250_startup,
2401 .shutdown = serial8250_shutdown,
2402 .set_termios = serial8250_set_termios,
2403 .pm = serial8250_pm,
2404 .type = serial8250_type,
2405 .release_port = serial8250_release_port,
2406 .request_port = serial8250_request_port,
2407 .config_port = serial8250_config_port,
2408 .verify_port = serial8250_verify_port,
2411 static struct uart_8250_port serial8250_ports[UART_NR];
2413 static void __init serial8250_isa_init_ports(void)
2415 struct uart_8250_port *up;
2416 static int first = 1;
2423 for (i = 0; i < nr_uarts; i++) {
2424 struct uart_8250_port *up = &serial8250_ports[i];
2427 spin_lock_init(&up->port.lock);
2429 init_timer(&up->timer);
2430 up->timer.function = serial8250_timeout;
2433 * ALPHA_KLUDGE_MCR needs to be killed.
2435 up->mcr_mask = ~ALPHA_KLUDGE_MCR;
2436 up->mcr_force = ALPHA_KLUDGE_MCR;
2438 up->port.ops = &serial8250_pops;
2441 for (i = 0, up = serial8250_ports;
2442 i < ARRAY_SIZE(old_serial_port) && i < nr_uarts;
2444 up->port.iobase = old_serial_port[i].port;
2445 up->port.irq = irq_canonicalize(old_serial_port[i].irq);
2446 up->port.uartclk = old_serial_port[i].baud_base * 16;
2447 up->port.flags = old_serial_port[i].flags;
2448 up->port.hub6 = old_serial_port[i].hub6;
2449 up->port.membase = old_serial_port[i].iomem_base;
2450 up->port.iotype = old_serial_port[i].io_type;
2451 up->port.regshift = old_serial_port[i].iomem_reg_shift;
2453 up->port.flags |= UPF_SHARE_IRQ;
2458 serial8250_register_ports(struct uart_driver *drv, struct device *dev)
2462 serial8250_isa_init_ports();
2464 for (i = 0; i < nr_uarts; i++) {
2465 struct uart_8250_port *up = &serial8250_ports[i];
2468 uart_add_one_port(drv, &up->port);
2472 #ifdef CONFIG_SERIAL_8250_CONSOLE
2474 static void serial8250_console_putchar(struct uart_port *port, int ch)
2476 struct uart_8250_port *up = (struct uart_8250_port *)port;
2478 wait_for_xmitr(up, UART_LSR_THRE);
2479 serial_out(up, UART_TX, ch);
2483 * Print a string to the serial port trying not to disturb
2484 * any possible real use of the port...
2486 * The console_lock must be held when we get here.
2489 serial8250_console_write(struct console *co, const char *s, unsigned int count)
2491 struct uart_8250_port *up = &serial8250_ports[co->index];
2492 unsigned long flags;
2496 touch_nmi_watchdog();
2498 local_irq_save(flags);
2499 if (up->port.sysrq) {
2500 /* serial8250_handle_port() already took the lock */
2502 } else if (oops_in_progress) {
2503 locked = spin_trylock(&up->port.lock);
2505 spin_lock(&up->port.lock);
2508 * First save the IER then disable the interrupts
2510 ier = serial_in(up, UART_IER);
2512 if (up->capabilities & UART_CAP_UUE)
2513 serial_out(up, UART_IER, UART_IER_UUE);
2515 serial_out(up, UART_IER, 0);
2517 uart_console_write(&up->port, s, count, serial8250_console_putchar);
2520 * Finally, wait for transmitter to become empty
2521 * and restore the IER
2523 wait_for_xmitr(up, BOTH_EMPTY);
2524 serial_out(up, UART_IER, ier);
2527 * The receive handling will happen properly because the
2528 * receive ready bit will still be set; it is not cleared
2529 * on read. However, modem control will not, we must
2530 * call it if we have saved something in the saved flags
2531 * while processing with interrupts off.
2533 if (up->msr_saved_flags)
2534 check_modem_status(up);
2537 spin_unlock(&up->port.lock);
2538 local_irq_restore(flags);
2541 static int __init serial8250_console_setup(struct console *co, char *options)
2543 struct uart_port *port;
2550 * Check whether an invalid uart number has been specified, and
2551 * if so, search for the first available port that does have
2554 if (co->index >= nr_uarts)
2556 port = &serial8250_ports[co->index].port;
2557 if (!port->iobase && !port->membase)
2561 uart_parse_options(options, &baud, &parity, &bits, &flow);
2563 return uart_set_options(port, co, baud, parity, bits, flow);
2566 static int serial8250_console_early_setup(void)
2568 return serial8250_find_port_for_earlycon();
2571 static struct uart_driver serial8250_reg;
2572 static struct console serial8250_console = {
2574 .write = serial8250_console_write,
2575 .device = uart_console_device,
2576 .setup = serial8250_console_setup,
2577 .early_setup = serial8250_console_early_setup,
2578 .flags = CON_PRINTBUFFER,
2580 .data = &serial8250_reg,
2583 static int __init serial8250_console_init(void)
2585 serial8250_isa_init_ports();
2586 register_console(&serial8250_console);
2589 console_initcall(serial8250_console_init);
2591 int serial8250_find_port(struct uart_port *p)
2594 struct uart_port *port;
2596 for (line = 0; line < nr_uarts; line++) {
2597 port = &serial8250_ports[line].port;
2598 if (uart_match_port(p, port))
2604 #define SERIAL8250_CONSOLE &serial8250_console
2606 #define SERIAL8250_CONSOLE NULL
2609 static struct uart_driver serial8250_reg = {
2610 .owner = THIS_MODULE,
2611 .driver_name = "serial",
2616 .cons = SERIAL8250_CONSOLE,
2620 * early_serial_setup - early registration for 8250 ports
2622 * Setup an 8250 port structure prior to console initialisation. Use
2623 * after console initialisation will cause undefined behaviour.
2625 int __init early_serial_setup(struct uart_port *port)
2627 if (port->line >= ARRAY_SIZE(serial8250_ports))
2630 serial8250_isa_init_ports();
2631 serial8250_ports[port->line].port = *port;
2632 serial8250_ports[port->line].port.ops = &serial8250_pops;
2637 * serial8250_suspend_port - suspend one serial port
2638 * @line: serial line number
2640 * Suspend one serial port.
2642 void serial8250_suspend_port(int line)
2644 uart_suspend_port(&serial8250_reg, &serial8250_ports[line].port);
2648 * serial8250_resume_port - resume one serial port
2649 * @line: serial line number
2651 * Resume one serial port.
2653 void serial8250_resume_port(int line)
2655 struct uart_8250_port *up = &serial8250_ports[line];
2657 if (up->capabilities & UART_NATSEMI) {
2660 /* Ensure it's still in high speed mode */
2661 serial_outp(up, UART_LCR, 0xE0);
2663 tmp = serial_in(up, 0x04); /* EXCR2 */
2664 tmp &= ~0xB0; /* Disable LOCK, mask out PRESL[01] */
2665 tmp |= 0x10; /* 1.625 divisor for baud_base --> 921600 */
2666 serial_outp(up, 0x04, tmp);
2668 serial_outp(up, UART_LCR, 0);
2670 uart_resume_port(&serial8250_reg, &up->port);
2674 * Register a set of serial devices attached to a platform device. The
2675 * list is terminated with a zero flags entry, which means we expect
2676 * all entries to have at least UPF_BOOT_AUTOCONF set.
2678 static int __devinit serial8250_probe(struct platform_device *dev)
2680 struct plat_serial8250_port *p = dev->dev.platform_data;
2681 struct uart_port port;
2684 memset(&port, 0, sizeof(struct uart_port));
2686 for (i = 0; p && p->flags != 0; p++, i++) {
2687 port.iobase = p->iobase;
2688 port.membase = p->membase;
2690 port.uartclk = p->uartclk;
2691 port.regshift = p->regshift;
2692 port.iotype = p->iotype;
2693 port.flags = p->flags;
2694 port.mapbase = p->mapbase;
2695 port.hub6 = p->hub6;
2696 port.dev = &dev->dev;
2698 port.flags |= UPF_SHARE_IRQ;
2699 ret = serial8250_register_port(&port);
2701 dev_err(&dev->dev, "unable to register port at index %d "
2702 "(IO%lx MEM%llx IRQ%d): %d\n", i,
2703 p->iobase, (unsigned long long)p->mapbase,
2711 * Remove serial ports registered against a platform device.
2713 static int __devexit serial8250_remove(struct platform_device *dev)
2717 for (i = 0; i < nr_uarts; i++) {
2718 struct uart_8250_port *up = &serial8250_ports[i];
2720 if (up->port.dev == &dev->dev)
2721 serial8250_unregister_port(i);
2726 static int serial8250_suspend(struct platform_device *dev, pm_message_t state)
2730 for (i = 0; i < UART_NR; i++) {
2731 struct uart_8250_port *up = &serial8250_ports[i];
2733 if (up->port.type != PORT_UNKNOWN && up->port.dev == &dev->dev)
2734 uart_suspend_port(&serial8250_reg, &up->port);
2740 static int serial8250_resume(struct platform_device *dev)
2744 for (i = 0; i < UART_NR; i++) {
2745 struct uart_8250_port *up = &serial8250_ports[i];
2747 if (up->port.type != PORT_UNKNOWN && up->port.dev == &dev->dev)
2748 serial8250_resume_port(i);
2754 static struct platform_driver serial8250_isa_driver = {
2755 .probe = serial8250_probe,
2756 .remove = __devexit_p(serial8250_remove),
2757 .suspend = serial8250_suspend,
2758 .resume = serial8250_resume,
2760 .name = "serial8250",
2761 .owner = THIS_MODULE,
2766 * This "device" covers _all_ ISA 8250-compatible serial devices listed
2767 * in the table in include/asm/serial.h
2769 static struct platform_device *serial8250_isa_devs;
2772 * serial8250_register_port and serial8250_unregister_port allows for
2773 * 16x50 serial ports to be configured at run-time, to support PCMCIA
2774 * modems and PCI multiport cards.
2776 static DEFINE_MUTEX(serial_mutex);
2778 static struct uart_8250_port *serial8250_find_match_or_unused(struct uart_port *port)
2783 * First, find a port entry which matches.
2785 for (i = 0; i < nr_uarts; i++)
2786 if (uart_match_port(&serial8250_ports[i].port, port))
2787 return &serial8250_ports[i];
2790 * We didn't find a matching entry, so look for the first
2791 * free entry. We look for one which hasn't been previously
2792 * used (indicated by zero iobase).
2794 for (i = 0; i < nr_uarts; i++)
2795 if (serial8250_ports[i].port.type == PORT_UNKNOWN &&
2796 serial8250_ports[i].port.iobase == 0)
2797 return &serial8250_ports[i];
2800 * That also failed. Last resort is to find any entry which
2801 * doesn't have a real port associated with it.
2803 for (i = 0; i < nr_uarts; i++)
2804 if (serial8250_ports[i].port.type == PORT_UNKNOWN)
2805 return &serial8250_ports[i];
2811 * serial8250_register_port - register a serial port
2812 * @port: serial port template
2814 * Configure the serial port specified by the request. If the
2815 * port exists and is in use, it is hung up and unregistered
2818 * The port is then probed and if necessary the IRQ is autodetected
2819 * If this fails an error is returned.
2821 * On success the port is ready to use and the line number is returned.
2823 int serial8250_register_port(struct uart_port *port)
2825 struct uart_8250_port *uart;
2828 if (port->uartclk == 0)
2831 mutex_lock(&serial_mutex);
2833 uart = serial8250_find_match_or_unused(port);
2835 uart_remove_one_port(&serial8250_reg, &uart->port);
2837 uart->port.iobase = port->iobase;
2838 uart->port.membase = port->membase;
2839 uart->port.irq = port->irq;
2840 uart->port.uartclk = port->uartclk;
2841 uart->port.fifosize = port->fifosize;
2842 uart->port.regshift = port->regshift;
2843 uart->port.iotype = port->iotype;
2844 uart->port.flags = port->flags | UPF_BOOT_AUTOCONF;
2845 uart->port.mapbase = port->mapbase;
2847 uart->port.dev = port->dev;
2849 ret = uart_add_one_port(&serial8250_reg, &uart->port);
2851 ret = uart->port.line;
2853 mutex_unlock(&serial_mutex);
2857 EXPORT_SYMBOL(serial8250_register_port);
2860 * serial8250_unregister_port - remove a 16x50 serial port at runtime
2861 * @line: serial line number
2863 * Remove one serial port. This may not be called from interrupt
2864 * context. We hand the port back to the our control.
2866 void serial8250_unregister_port(int line)
2868 struct uart_8250_port *uart = &serial8250_ports[line];
2870 mutex_lock(&serial_mutex);
2871 uart_remove_one_port(&serial8250_reg, &uart->port);
2872 if (serial8250_isa_devs) {
2873 uart->port.flags &= ~UPF_BOOT_AUTOCONF;
2874 uart->port.type = PORT_UNKNOWN;
2875 uart->port.dev = &serial8250_isa_devs->dev;
2876 uart_add_one_port(&serial8250_reg, &uart->port);
2878 uart->port.dev = NULL;
2880 mutex_unlock(&serial_mutex);
2882 EXPORT_SYMBOL(serial8250_unregister_port);
2884 static int __init serial8250_init(void)
2888 if (nr_uarts > UART_NR)
2891 printk(KERN_INFO "Serial: 8250/16550 driver $Revision: 1.90 $ "
2892 "%d ports, IRQ sharing %sabled\n", nr_uarts,
2893 share_irqs ? "en" : "dis");
2895 for (i = 0; i < NR_IRQS; i++)
2896 spin_lock_init(&irq_lists[i].lock);
2898 ret = uart_register_driver(&serial8250_reg);
2902 serial8250_isa_devs = platform_device_alloc("serial8250",
2903 PLAT8250_DEV_LEGACY);
2904 if (!serial8250_isa_devs) {
2906 goto unreg_uart_drv;
2909 ret = platform_device_add(serial8250_isa_devs);
2913 serial8250_register_ports(&serial8250_reg, &serial8250_isa_devs->dev);
2915 ret = platform_driver_register(&serial8250_isa_driver);
2919 platform_device_del(serial8250_isa_devs);
2921 platform_device_put(serial8250_isa_devs);
2923 uart_unregister_driver(&serial8250_reg);
2928 static void __exit serial8250_exit(void)
2930 struct platform_device *isa_dev = serial8250_isa_devs;
2933 * This tells serial8250_unregister_port() not to re-register
2934 * the ports (thereby making serial8250_isa_driver permanently
2937 serial8250_isa_devs = NULL;
2939 platform_driver_unregister(&serial8250_isa_driver);
2940 platform_device_unregister(isa_dev);
2942 uart_unregister_driver(&serial8250_reg);
2945 module_init(serial8250_init);
2946 module_exit(serial8250_exit);
2948 EXPORT_SYMBOL(serial8250_suspend_port);
2949 EXPORT_SYMBOL(serial8250_resume_port);
2951 MODULE_LICENSE("GPL");
2952 MODULE_DESCRIPTION("Generic 8250/16x50 serial driver $Revision: 1.90 $");
2954 module_param(share_irqs, uint, 0644);
2955 MODULE_PARM_DESC(share_irqs, "Share IRQs with other non-8250/16x50 devices"
2958 module_param(nr_uarts, uint, 0644);
2959 MODULE_PARM_DESC(nr_uarts, "Maximum number of UARTs supported. (1-" __MODULE_STRING(CONFIG_SERIAL_8250_NR_UARTS) ")");
2961 #ifdef CONFIG_SERIAL_8250_RSA
2962 module_param_array(probe_rsa, ulong, &probe_rsa_count, 0444);
2963 MODULE_PARM_DESC(probe_rsa, "Probe I/O ports for RSA");
2965 MODULE_ALIAS_CHARDEV_MAJOR(TTY_MAJOR);