2 * linux/drivers/serial/imx.c
4 * Driver for Motorola IMX serial ports
6 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
8 * Author: Sascha Hauer <sascha@saschahauer.de>
9 * Copyright (C) 2004 Pengutronix
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
25 * [29-Mar-2005] Mike Lee
26 * Added hardware handshake
29 #if defined(CONFIG_SERIAL_IMX_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
33 #include <linux/module.h>
34 #include <linux/ioport.h>
35 #include <linux/init.h>
36 #include <linux/console.h>
37 #include <linux/sysrq.h>
38 #include <linux/platform_device.h>
39 #include <linux/tty.h>
40 #include <linux/tty_flip.h>
41 #include <linux/serial_core.h>
42 #include <linux/serial.h>
46 #include <asm/hardware.h>
47 #include <asm/arch/imx-uart.h>
49 /* Register definitions */
50 #define URXD0 0x0 /* Receiver Register */
51 #define URTX0 0x40 /* Transmitter Register */
52 #define UCR1 0x80 /* Control Register 1 */
53 #define UCR2 0x84 /* Control Register 2 */
54 #define UCR3 0x88 /* Control Register 3 */
55 #define UCR4 0x8c /* Control Register 4 */
56 #define UFCR 0x90 /* FIFO Control Register */
57 #define USR1 0x94 /* Status Register 1 */
58 #define USR2 0x98 /* Status Register 2 */
59 #define UESC 0x9c /* Escape Character Register */
60 #define UTIM 0xa0 /* Escape Timer Register */
61 #define UBIR 0xa4 /* BRM Incremental Register */
62 #define UBMR 0xa8 /* BRM Modulator Register */
63 #define UBRC 0xac /* Baud Rate Count Register */
64 #define BIPR1 0xb0 /* Incremental Preset Register 1 */
65 #define BIPR2 0xb4 /* Incremental Preset Register 2 */
66 #define BIPR3 0xb8 /* Incremental Preset Register 3 */
67 #define BIPR4 0xbc /* Incremental Preset Register 4 */
68 #define BMPR1 0xc0 /* BRM Modulator Register 1 */
69 #define BMPR2 0xc4 /* BRM Modulator Register 2 */
70 #define BMPR3 0xc8 /* BRM Modulator Register 3 */
71 #define BMPR4 0xcc /* BRM Modulator Register 4 */
72 #define UTS 0xd0 /* UART Test Register */
74 /* UART Control Register Bit Fields.*/
75 #define URXD_CHARRDY (1<<15)
76 #define URXD_ERR (1<<14)
77 #define URXD_OVRRUN (1<<13)
78 #define URXD_FRMERR (1<<12)
79 #define URXD_BRK (1<<11)
80 #define URXD_PRERR (1<<10)
81 #define UCR1_ADEN (1<<15) /* Auto dectect interrupt */
82 #define UCR1_ADBR (1<<14) /* Auto detect baud rate */
83 #define UCR1_TRDYEN (1<<13) /* Transmitter ready interrupt enable */
84 #define UCR1_IDEN (1<<12) /* Idle condition interrupt */
85 #define UCR1_RRDYEN (1<<9) /* Recv ready interrupt enable */
86 #define UCR1_RDMAEN (1<<8) /* Recv ready DMA enable */
87 #define UCR1_IREN (1<<7) /* Infrared interface enable */
88 #define UCR1_TXMPTYEN (1<<6) /* Transimitter empty interrupt enable */
89 #define UCR1_RTSDEN (1<<5) /* RTS delta interrupt enable */
90 #define UCR1_SNDBRK (1<<4) /* Send break */
91 #define UCR1_TDMAEN (1<<3) /* Transmitter ready DMA enable */
92 #define UCR1_UARTCLKEN (1<<2) /* UART clock enabled */
93 #define UCR1_DOZE (1<<1) /* Doze */
94 #define UCR1_UARTEN (1<<0) /* UART enabled */
95 #define UCR2_ESCI (1<<15) /* Escape seq interrupt enable */
96 #define UCR2_IRTS (1<<14) /* Ignore RTS pin */
97 #define UCR2_CTSC (1<<13) /* CTS pin control */
98 #define UCR2_CTS (1<<12) /* Clear to send */
99 #define UCR2_ESCEN (1<<11) /* Escape enable */
100 #define UCR2_PREN (1<<8) /* Parity enable */
101 #define UCR2_PROE (1<<7) /* Parity odd/even */
102 #define UCR2_STPB (1<<6) /* Stop */
103 #define UCR2_WS (1<<5) /* Word size */
104 #define UCR2_RTSEN (1<<4) /* Request to send interrupt enable */
105 #define UCR2_TXEN (1<<2) /* Transmitter enabled */
106 #define UCR2_RXEN (1<<1) /* Receiver enabled */
107 #define UCR2_SRST (1<<0) /* SW reset */
108 #define UCR3_DTREN (1<<13) /* DTR interrupt enable */
109 #define UCR3_PARERREN (1<<12) /* Parity enable */
110 #define UCR3_FRAERREN (1<<11) /* Frame error interrupt enable */
111 #define UCR3_DSR (1<<10) /* Data set ready */
112 #define UCR3_DCD (1<<9) /* Data carrier detect */
113 #define UCR3_RI (1<<8) /* Ring indicator */
114 #define UCR3_TIMEOUTEN (1<<7) /* Timeout interrupt enable */
115 #define UCR3_RXDSEN (1<<6) /* Receive status interrupt enable */
116 #define UCR3_AIRINTEN (1<<5) /* Async IR wake interrupt enable */
117 #define UCR3_AWAKEN (1<<4) /* Async wake interrupt enable */
118 #define UCR3_REF25 (1<<3) /* Ref freq 25 MHz */
119 #define UCR3_REF30 (1<<2) /* Ref Freq 30 MHz */
120 #define UCR3_INVT (1<<1) /* Inverted Infrared transmission */
121 #define UCR3_BPEN (1<<0) /* Preset registers enable */
122 #define UCR4_CTSTL_32 (32<<10) /* CTS trigger level (32 chars) */
123 #define UCR4_INVR (1<<9) /* Inverted infrared reception */
124 #define UCR4_ENIRI (1<<8) /* Serial infrared interrupt enable */
125 #define UCR4_WKEN (1<<7) /* Wake interrupt enable */
126 #define UCR4_REF16 (1<<6) /* Ref freq 16 MHz */
127 #define UCR4_IRSC (1<<5) /* IR special case */
128 #define UCR4_TCEN (1<<3) /* Transmit complete interrupt enable */
129 #define UCR4_BKEN (1<<2) /* Break condition interrupt enable */
130 #define UCR4_OREN (1<<1) /* Receiver overrun interrupt enable */
131 #define UCR4_DREN (1<<0) /* Recv data ready interrupt enable */
132 #define UFCR_RXTL_SHF 0 /* Receiver trigger level shift */
133 #define UFCR_RFDIV (7<<7) /* Reference freq divider mask */
134 #define UFCR_TXTL_SHF 10 /* Transmitter trigger level shift */
135 #define USR1_PARITYERR (1<<15) /* Parity error interrupt flag */
136 #define USR1_RTSS (1<<14) /* RTS pin status */
137 #define USR1_TRDY (1<<13) /* Transmitter ready interrupt/dma flag */
138 #define USR1_RTSD (1<<12) /* RTS delta */
139 #define USR1_ESCF (1<<11) /* Escape seq interrupt flag */
140 #define USR1_FRAMERR (1<<10) /* Frame error interrupt flag */
141 #define USR1_RRDY (1<<9) /* Receiver ready interrupt/dma flag */
142 #define USR1_TIMEOUT (1<<7) /* Receive timeout interrupt status */
143 #define USR1_RXDS (1<<6) /* Receiver idle interrupt flag */
144 #define USR1_AIRINT (1<<5) /* Async IR wake interrupt flag */
145 #define USR1_AWAKE (1<<4) /* Aysnc wake interrupt flag */
146 #define USR2_ADET (1<<15) /* Auto baud rate detect complete */
147 #define USR2_TXFE (1<<14) /* Transmit buffer FIFO empty */
148 #define USR2_DTRF (1<<13) /* DTR edge interrupt flag */
149 #define USR2_IDLE (1<<12) /* Idle condition */
150 #define USR2_IRINT (1<<8) /* Serial infrared interrupt flag */
151 #define USR2_WAKE (1<<7) /* Wake */
152 #define USR2_RTSF (1<<4) /* RTS edge interrupt flag */
153 #define USR2_TXDC (1<<3) /* Transmitter complete */
154 #define USR2_BRCD (1<<2) /* Break condition */
155 #define USR2_ORE (1<<1) /* Overrun error */
156 #define USR2_RDR (1<<0) /* Recv data ready */
157 #define UTS_FRCPERR (1<<13) /* Force parity error */
158 #define UTS_LOOP (1<<12) /* Loop tx and rx */
159 #define UTS_TXEMPTY (1<<6) /* TxFIFO empty */
160 #define UTS_RXEMPTY (1<<5) /* RxFIFO empty */
161 #define UTS_TXFULL (1<<4) /* TxFIFO full */
162 #define UTS_RXFULL (1<<3) /* RxFIFO full */
163 #define UTS_SOFTRST (1<<0) /* Software reset */
165 /* We've been assigned a range on the "Low-density serial ports" major */
166 #define SERIAL_IMX_MAJOR 204
167 #define MINOR_START 41
170 * This is the size of our serial port register set.
172 #define UART_PORT_SIZE 0x100
175 * This determines how often we check the modem status signals
176 * for any change. They generally aren't connected to an IRQ
177 * so we have to poll them. We also check immediately before
178 * filling the TX fifo incase CTS has been dropped.
180 #define MCTRL_TIMEOUT (250*HZ/1000)
182 #define DRIVER_NAME "IMX-uart"
185 struct uart_port port;
186 struct timer_list timer;
187 unsigned int old_status;
188 int txirq,rxirq,rtsirq;
193 * Handle any change of modem status signal since we were last called.
195 static void imx_mctrl_check(struct imx_port *sport)
197 unsigned int status, changed;
199 status = sport->port.ops->get_mctrl(&sport->port);
200 changed = status ^ sport->old_status;
205 sport->old_status = status;
207 if (changed & TIOCM_RI)
208 sport->port.icount.rng++;
209 if (changed & TIOCM_DSR)
210 sport->port.icount.dsr++;
211 if (changed & TIOCM_CAR)
212 uart_handle_dcd_change(&sport->port, status & TIOCM_CAR);
213 if (changed & TIOCM_CTS)
214 uart_handle_cts_change(&sport->port, status & TIOCM_CTS);
216 wake_up_interruptible(&sport->port.info->delta_msr_wait);
220 * This is our per-port timeout handler, for checking the
221 * modem status signals.
223 static void imx_timeout(unsigned long data)
225 struct imx_port *sport = (struct imx_port *)data;
228 if (sport->port.info) {
229 spin_lock_irqsave(&sport->port.lock, flags);
230 imx_mctrl_check(sport);
231 spin_unlock_irqrestore(&sport->port.lock, flags);
233 mod_timer(&sport->timer, jiffies + MCTRL_TIMEOUT);
238 * interrupts disabled on entry
240 static void imx_stop_tx(struct uart_port *port)
242 struct imx_port *sport = (struct imx_port *)port;
245 temp = readl(sport->port.membase + UCR1);
246 writel(temp & ~UCR1_TXMPTYEN, sport->port.membase + UCR1);
250 * interrupts disabled on entry
252 static void imx_stop_rx(struct uart_port *port)
254 struct imx_port *sport = (struct imx_port *)port;
257 temp = readl(sport->port.membase + UCR2);
258 writel(temp &~ UCR2_RXEN, sport->port.membase + UCR2);
262 * Set the modem control timer to fire immediately.
264 static void imx_enable_ms(struct uart_port *port)
266 struct imx_port *sport = (struct imx_port *)port;
268 mod_timer(&sport->timer, jiffies);
271 static inline void imx_transmit_buffer(struct imx_port *sport)
273 struct circ_buf *xmit = &sport->port.info->xmit;
275 while (!(readl(sport->port.membase + UTS) & UTS_TXFULL)) {
276 /* send xmit->buf[xmit->tail]
277 * out the port here */
278 writel(xmit->buf[xmit->tail], sport->port.membase + URTX0);
279 xmit->tail = (xmit->tail + 1) &
280 (UART_XMIT_SIZE - 1);
281 sport->port.icount.tx++;
282 if (uart_circ_empty(xmit))
286 if (uart_circ_empty(xmit))
287 imx_stop_tx(&sport->port);
291 * interrupts disabled on entry
293 static void imx_start_tx(struct uart_port *port)
295 struct imx_port *sport = (struct imx_port *)port;
298 temp = readl(sport->port.membase + UCR1);
299 writel(temp | UCR1_TXMPTYEN, sport->port.membase + UCR1);
301 if (readl(sport->port.membase + UTS) & UTS_TXEMPTY)
302 imx_transmit_buffer(sport);
305 static irqreturn_t imx_rtsint(int irq, void *dev_id)
307 struct imx_port *sport = dev_id;
308 unsigned int val = readl(sport->port.membase + USR1) & USR1_RTSS;
311 spin_lock_irqsave(&sport->port.lock, flags);
313 writel(USR1_RTSD, sport->port.membase + USR1);
314 uart_handle_cts_change(&sport->port, !!val);
315 wake_up_interruptible(&sport->port.info->delta_msr_wait);
317 spin_unlock_irqrestore(&sport->port.lock, flags);
321 static irqreturn_t imx_txint(int irq, void *dev_id)
323 struct imx_port *sport = dev_id;
324 struct circ_buf *xmit = &sport->port.info->xmit;
327 spin_lock_irqsave(&sport->port.lock,flags);
328 if (sport->port.x_char)
331 writel(sport->port.x_char, sport->port.membase + URTX0);
335 if (uart_circ_empty(xmit) || uart_tx_stopped(&sport->port)) {
336 imx_stop_tx(&sport->port);
340 imx_transmit_buffer(sport);
342 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
343 uart_write_wakeup(&sport->port);
346 spin_unlock_irqrestore(&sport->port.lock,flags);
350 static irqreturn_t imx_rxint(int irq, void *dev_id)
352 struct imx_port *sport = dev_id;
353 unsigned int rx,flg,ignored = 0;
354 struct tty_struct *tty = sport->port.info->tty;
355 unsigned long flags, temp;
357 spin_lock_irqsave(&sport->port.lock,flags);
359 while ((rx = readl(sport->port.membase + URXD0)) & URXD_CHARRDY) {
361 sport->port.icount.rx++;
363 temp = readl(sport->port.membase + USR2);
364 if (temp & USR2_BRCD) {
365 writel(temp | USR2_BRCD, sport->port.membase + USR2);
366 if (uart_handle_break(&sport->port))
370 if (uart_handle_sysrq_char
371 (&sport->port, (unsigned char)rx))
374 if (rx & (URXD_PRERR | URXD_OVRRUN | URXD_FRMERR) ) {
376 sport->port.icount.parity++;
377 else if (rx & URXD_FRMERR)
378 sport->port.icount.frame++;
379 if (rx & URXD_OVRRUN)
380 sport->port.icount.overrun++;
382 if (rx & sport->port.ignore_status_mask) {
388 rx &= sport->port.read_status_mask;
392 else if (rx & URXD_FRMERR)
394 if (rx & URXD_OVRRUN)
398 sport->port.sysrq = 0;
402 tty_insert_flip_char(tty, rx, flg);
406 spin_unlock_irqrestore(&sport->port.lock,flags);
407 tty_flip_buffer_push(tty);
412 * Return TIOCSER_TEMT when transmitter is not busy.
414 static unsigned int imx_tx_empty(struct uart_port *port)
416 struct imx_port *sport = (struct imx_port *)port;
418 return (readl(sport->port.membase + USR2) & USR2_TXDC) ? TIOCSER_TEMT : 0;
422 * We have a modem side uart, so the meanings of RTS and CTS are inverted.
424 static unsigned int imx_get_mctrl(struct uart_port *port)
426 struct imx_port *sport = (struct imx_port *)port;
427 unsigned int tmp = TIOCM_DSR | TIOCM_CAR;
429 if (readl(sport->port.membase + USR1) & USR1_RTSS)
432 if (readl(sport->port.membase + UCR2) & UCR2_CTS)
438 static void imx_set_mctrl(struct uart_port *port, unsigned int mctrl)
440 struct imx_port *sport = (struct imx_port *)port;
443 temp = readl(sport->port.membase + UCR2) & ~UCR2_CTS;
445 if (mctrl & TIOCM_RTS)
448 writel(temp, sport->port.membase + UCR2);
452 * Interrupts always disabled.
454 static void imx_break_ctl(struct uart_port *port, int break_state)
456 struct imx_port *sport = (struct imx_port *)port;
457 unsigned long flags, temp;
459 spin_lock_irqsave(&sport->port.lock, flags);
461 temp = readl(sport->port.membase + UCR1) & ~UCR1_SNDBRK;
463 if ( break_state != 0 )
466 writel(temp, sport->port.membase + UCR1);
468 spin_unlock_irqrestore(&sport->port.lock, flags);
471 #define TXTL 2 /* reset default */
472 #define RXTL 1 /* reset default */
474 static int imx_setup_ufcr(struct imx_port *sport, unsigned int mode)
477 unsigned int ufcr_rfdiv;
479 /* set receiver / transmitter trigger level.
480 * RFDIV is set such way to satisfy requested uartclk value
482 val = TXTL << 10 | RXTL;
483 ufcr_rfdiv = (imx_get_perclk1() + sport->port.uartclk / 2) / sport->port.uartclk;
491 ufcr_rfdiv = 6 - ufcr_rfdiv;
493 val |= UFCR_RFDIV & (ufcr_rfdiv << 7);
495 writel(val, sport->port.membase + UFCR);
500 static int imx_startup(struct uart_port *port)
502 struct imx_port *sport = (struct imx_port *)port;
504 unsigned long flags, temp;
506 imx_setup_ufcr(sport, 0);
508 /* disable the DREN bit (Data Ready interrupt enable) before
511 temp = readl(sport->port.membase + UCR4);
512 writel(temp & ~UCR4_DREN, sport->port.membase + UCR4);
517 retval = request_irq(sport->rxirq, imx_rxint, 0,
519 if (retval) goto error_out1;
521 retval = request_irq(sport->txirq, imx_txint, 0,
523 if (retval) goto error_out2;
525 retval = request_irq(sport->rtsirq, imx_rtsint,
526 (sport->rtsirq < IMX_IRQS) ? 0 :
527 IRQF_TRIGGER_FALLING | IRQF_TRIGGER_RISING,
529 if (retval) goto error_out3;
532 * Finally, clear and enable interrupts
534 writel(USR1_RTSD, sport->port.membase + USR1);
536 temp = readl(sport->port.membase + UCR1);
537 temp |= (UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN | UCR1_UARTEN);
538 writel(temp, sport->port.membase + UCR1);
540 temp = readl(sport->port.membase + UCR2);
541 temp |= (UCR2_RXEN | UCR2_TXEN);
542 writel(temp, sport->port.membase + UCR2);
545 * Enable modem status interrupts
547 spin_lock_irqsave(&sport->port.lock,flags);
548 imx_enable_ms(&sport->port);
549 spin_unlock_irqrestore(&sport->port.lock,flags);
554 free_irq(sport->txirq, sport);
556 free_irq(sport->rxirq, sport);
561 static void imx_shutdown(struct uart_port *port)
563 struct imx_port *sport = (struct imx_port *)port;
569 del_timer_sync(&sport->timer);
572 * Free the interrupts
574 free_irq(sport->rtsirq, sport);
575 free_irq(sport->txirq, sport);
576 free_irq(sport->rxirq, sport);
579 * Disable all interrupts, port and break condition.
582 temp = readl(sport->port.membase + UCR1);
583 temp &= ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN | UCR1_UARTEN);
584 writel(temp, sport->port.membase + UCR1);
588 imx_set_termios(struct uart_port *port, struct ktermios *termios,
589 struct ktermios *old)
591 struct imx_port *sport = (struct imx_port *)port;
593 unsigned int ucr2, old_ucr1, old_txrxen, baud, quot;
594 unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8;
597 * If we don't support modem control lines, don't allow
601 termios->c_cflag &= ~(HUPCL | CRTSCTS | CMSPAR);
602 termios->c_cflag |= CLOCAL;
606 * We only support CS7 and CS8.
608 while ((termios->c_cflag & CSIZE) != CS7 &&
609 (termios->c_cflag & CSIZE) != CS8) {
610 termios->c_cflag &= ~CSIZE;
611 termios->c_cflag |= old_csize;
615 if ((termios->c_cflag & CSIZE) == CS8)
616 ucr2 = UCR2_WS | UCR2_SRST | UCR2_IRTS;
618 ucr2 = UCR2_SRST | UCR2_IRTS;
620 if (termios->c_cflag & CRTSCTS) {
621 if( sport->have_rtscts ) {
625 termios->c_cflag &= ~CRTSCTS;
629 if (termios->c_cflag & CSTOPB)
631 if (termios->c_cflag & PARENB) {
633 if (termios->c_cflag & PARODD)
638 * Ask the core to calculate the divisor for us.
640 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16);
641 quot = uart_get_divisor(port, baud);
643 spin_lock_irqsave(&sport->port.lock, flags);
645 sport->port.read_status_mask = 0;
646 if (termios->c_iflag & INPCK)
647 sport->port.read_status_mask |= (URXD_FRMERR | URXD_PRERR);
648 if (termios->c_iflag & (BRKINT | PARMRK))
649 sport->port.read_status_mask |= URXD_BRK;
652 * Characters to ignore
654 sport->port.ignore_status_mask = 0;
655 if (termios->c_iflag & IGNPAR)
656 sport->port.ignore_status_mask |= URXD_PRERR;
657 if (termios->c_iflag & IGNBRK) {
658 sport->port.ignore_status_mask |= URXD_BRK;
660 * If we're ignoring parity and break indicators,
661 * ignore overruns too (for real raw support).
663 if (termios->c_iflag & IGNPAR)
664 sport->port.ignore_status_mask |= URXD_OVRRUN;
667 del_timer_sync(&sport->timer);
670 * Update the per-port timeout.
672 uart_update_timeout(port, termios->c_cflag, baud);
675 * disable interrupts and drain transmitter
677 old_ucr1 = readl(sport->port.membase + UCR1);
678 writel(old_ucr1 & ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN),
679 sport->port.membase + UCR1);
681 while ( !(readl(sport->port.membase + USR2) & USR2_TXDC))
684 /* then, disable everything */
685 old_txrxen = readl(sport->port.membase + UCR2);
686 writel(old_txrxen & ~( UCR2_TXEN | UCR2_RXEN),
687 sport->port.membase + UCR2);
688 old_txrxen &= (UCR2_TXEN | UCR2_RXEN);
690 /* set the baud rate. We assume uartclk = 16 MHz
693 * --------- = --------
696 writel((baud / 100) - 1, sport->port.membase + UBIR);
697 writel(10000 - 1, sport->port.membase + UBMR);
699 writel(old_ucr1, sport->port.membase + UCR1);
701 /* set the parity, stop bits and data size */
702 writel(ucr2 | old_txrxen, sport->port.membase + UCR2);
704 if (UART_ENABLE_MS(&sport->port, termios->c_cflag))
705 imx_enable_ms(&sport->port);
707 spin_unlock_irqrestore(&sport->port.lock, flags);
710 static const char *imx_type(struct uart_port *port)
712 struct imx_port *sport = (struct imx_port *)port;
714 return sport->port.type == PORT_IMX ? "IMX" : NULL;
718 * Release the memory region(s) being used by 'port'.
720 static void imx_release_port(struct uart_port *port)
722 struct imx_port *sport = (struct imx_port *)port;
724 release_mem_region(sport->port.mapbase, UART_PORT_SIZE);
728 * Request the memory region(s) being used by 'port'.
730 static int imx_request_port(struct uart_port *port)
732 struct imx_port *sport = (struct imx_port *)port;
734 return request_mem_region(sport->port.mapbase, UART_PORT_SIZE,
735 "imx-uart") != NULL ? 0 : -EBUSY;
739 * Configure/autoconfigure the port.
741 static void imx_config_port(struct uart_port *port, int flags)
743 struct imx_port *sport = (struct imx_port *)port;
745 if (flags & UART_CONFIG_TYPE &&
746 imx_request_port(&sport->port) == 0)
747 sport->port.type = PORT_IMX;
751 * Verify the new serial_struct (for TIOCSSERIAL).
752 * The only change we allow are to the flags and type, and
753 * even then only between PORT_IMX and PORT_UNKNOWN
756 imx_verify_port(struct uart_port *port, struct serial_struct *ser)
758 struct imx_port *sport = (struct imx_port *)port;
761 if (ser->type != PORT_UNKNOWN && ser->type != PORT_IMX)
763 if (sport->port.irq != ser->irq)
765 if (ser->io_type != UPIO_MEM)
767 if (sport->port.uartclk / 16 != ser->baud_base)
769 if ((void *)sport->port.mapbase != ser->iomem_base)
771 if (sport->port.iobase != ser->port)
778 static struct uart_ops imx_pops = {
779 .tx_empty = imx_tx_empty,
780 .set_mctrl = imx_set_mctrl,
781 .get_mctrl = imx_get_mctrl,
782 .stop_tx = imx_stop_tx,
783 .start_tx = imx_start_tx,
784 .stop_rx = imx_stop_rx,
785 .enable_ms = imx_enable_ms,
786 .break_ctl = imx_break_ctl,
787 .startup = imx_startup,
788 .shutdown = imx_shutdown,
789 .set_termios = imx_set_termios,
791 .release_port = imx_release_port,
792 .request_port = imx_request_port,
793 .config_port = imx_config_port,
794 .verify_port = imx_verify_port,
797 static struct imx_port imx_ports[] = {
799 .txirq = UART1_MINT_TX,
800 .rxirq = UART1_MINT_RX,
801 .rtsirq = UART1_MINT_RTS,
805 .membase = (void *)IMX_UART1_BASE,
806 .mapbase = IMX_UART1_BASE, /* FIXME */
807 .irq = UART1_MINT_RX,
810 .flags = UPF_BOOT_AUTOCONF,
815 .txirq = UART2_MINT_TX,
816 .rxirq = UART2_MINT_RX,
817 .rtsirq = UART2_MINT_RTS,
821 .membase = (void *)IMX_UART2_BASE,
822 .mapbase = IMX_UART2_BASE, /* FIXME */
823 .irq = UART2_MINT_RX,
826 .flags = UPF_BOOT_AUTOCONF,
834 * Setup the IMX serial ports.
835 * Note also that we support "console=ttySMXx" where "x" is either 0 or 1.
836 * Which serial port this ends up being depends on the machine you're
837 * running this kernel on. I'm not convinced that this is a good idea,
838 * but that's the way it traditionally works.
841 static void __init imx_init_ports(void)
843 static int first = 1;
850 for (i = 0; i < ARRAY_SIZE(imx_ports); i++) {
851 init_timer(&imx_ports[i].timer);
852 imx_ports[i].timer.function = imx_timeout;
853 imx_ports[i].timer.data = (unsigned long)&imx_ports[i];
857 #ifdef CONFIG_SERIAL_IMX_CONSOLE
858 static void imx_console_putchar(struct uart_port *port, int ch)
860 struct imx_port *sport = (struct imx_port *)port;
862 while (readl(sport->port.membase + UTS) & UTS_TXFULL)
865 writel(ch, sport->port.membase + URTX0);
869 * Interrupts are disabled on entering
872 imx_console_write(struct console *co, const char *s, unsigned int count)
874 struct imx_port *sport = &imx_ports[co->index];
875 unsigned int old_ucr1, old_ucr2;
878 * First, save UCR1/2 and then disable interrupts
880 old_ucr1 = readl(sport->port.membase + UCR1);
881 old_ucr2 = readl(sport->port.membase + UCR2);
883 writel((old_ucr1 | UCR1_UARTCLKEN | UCR1_UARTEN) &
884 ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN),
885 sport->port.membase + UCR1);
887 writel(old_ucr2 | UCR2_TXEN, sport->port.membase + UCR2);
889 uart_console_write(&sport->port, s, count, imx_console_putchar);
892 * Finally, wait for transmitter to become empty
895 while (!(readl(sport->port.membase + USR2) & USR2_TXDC));
897 writel(old_ucr1, sport->port.membase + UCR1);
898 writel(old_ucr2, sport->port.membase + UCR2);
902 * If the port was already initialised (eg, by a boot loader),
903 * try to determine the current setup.
906 imx_console_get_options(struct imx_port *sport, int *baud,
907 int *parity, int *bits)
910 if ( readl(sport->port.membase + UCR1) | UCR1_UARTEN ) {
911 /* ok, the port was enabled */
912 unsigned int ucr2, ubir,ubmr, uartclk;
913 unsigned int baud_raw;
914 unsigned int ucfr_rfdiv;
916 ucr2 = readl(sport->port.membase + UCR2);
919 if (ucr2 & UCR2_PREN) {
920 if (ucr2 & UCR2_PROE)
931 ubir = readl(sport->port.membase + UBIR) & 0xffff;
932 ubmr = readl(sport->port.membase + UBMR) & 0xffff;
934 ucfr_rfdiv = (readl(sport->port.membase + UFCR) & UFCR_RFDIV) >> 7;
938 ucfr_rfdiv = 6 - ucfr_rfdiv;
940 uartclk = imx_get_perclk1();
941 uartclk /= ucfr_rfdiv;
944 * The next code provides exact computation of
945 * baud_raw = round(((uartclk/16) * (ubir + 1)) / (ubmr + 1))
946 * without need of float support or long long division,
947 * which would be required to prevent 32bit arithmetic overflow
949 unsigned int mul = ubir + 1;
950 unsigned int div = 16 * (ubmr + 1);
951 unsigned int rem = uartclk % div;
953 baud_raw = (uartclk / div) * mul;
954 baud_raw += (rem * mul + div / 2) / div;
955 *baud = (baud_raw + 50) / 100 * 100;
958 if(*baud != baud_raw)
959 printk(KERN_INFO "Serial: Console IMX rounded baud rate from %d to %d\n",
965 imx_console_setup(struct console *co, char *options)
967 struct imx_port *sport;
974 * Check whether an invalid uart number has been specified, and
975 * if so, search for the first available port that does have
978 if (co->index == -1 || co->index >= ARRAY_SIZE(imx_ports))
980 sport = &imx_ports[co->index];
983 uart_parse_options(options, &baud, &parity, &bits, &flow);
985 imx_console_get_options(sport, &baud, &parity, &bits);
987 imx_setup_ufcr(sport, 0);
989 return uart_set_options(&sport->port, co, baud, parity, bits, flow);
992 static struct uart_driver imx_reg;
993 static struct console imx_console = {
995 .write = imx_console_write,
996 .device = uart_console_device,
997 .setup = imx_console_setup,
998 .flags = CON_PRINTBUFFER,
1003 static int __init imx_rs_console_init(void)
1006 register_console(&imx_console);
1009 console_initcall(imx_rs_console_init);
1011 #define IMX_CONSOLE &imx_console
1013 #define IMX_CONSOLE NULL
1016 static struct uart_driver imx_reg = {
1017 .owner = THIS_MODULE,
1018 .driver_name = DRIVER_NAME,
1019 .dev_name = "ttySMX",
1020 .major = SERIAL_IMX_MAJOR,
1021 .minor = MINOR_START,
1022 .nr = ARRAY_SIZE(imx_ports),
1023 .cons = IMX_CONSOLE,
1026 static int serial_imx_suspend(struct platform_device *dev, pm_message_t state)
1028 struct imx_port *sport = platform_get_drvdata(dev);
1031 uart_suspend_port(&imx_reg, &sport->port);
1036 static int serial_imx_resume(struct platform_device *dev)
1038 struct imx_port *sport = platform_get_drvdata(dev);
1041 uart_resume_port(&imx_reg, &sport->port);
1046 static int serial_imx_probe(struct platform_device *dev)
1048 struct imxuart_platform_data *pdata;
1050 imx_ports[dev->id].port.dev = &dev->dev;
1052 pdata = (struct imxuart_platform_data *)dev->dev.platform_data;
1053 if(pdata && (pdata->flags & IMXUART_HAVE_RTSCTS))
1054 imx_ports[dev->id].have_rtscts = 1;
1056 uart_add_one_port(&imx_reg, &imx_ports[dev->id].port);
1057 platform_set_drvdata(dev, &imx_ports[dev->id]);
1061 static int serial_imx_remove(struct platform_device *dev)
1063 struct imx_port *sport = platform_get_drvdata(dev);
1065 platform_set_drvdata(dev, NULL);
1068 uart_remove_one_port(&imx_reg, &sport->port);
1073 static struct platform_driver serial_imx_driver = {
1074 .probe = serial_imx_probe,
1075 .remove = serial_imx_remove,
1077 .suspend = serial_imx_suspend,
1078 .resume = serial_imx_resume,
1084 static int __init imx_serial_init(void)
1088 printk(KERN_INFO "Serial: IMX driver\n");
1092 ret = uart_register_driver(&imx_reg);
1096 ret = platform_driver_register(&serial_imx_driver);
1098 uart_unregister_driver(&imx_reg);
1103 static void __exit imx_serial_exit(void)
1105 platform_driver_unregister(&serial_imx_driver);
1106 uart_unregister_driver(&imx_reg);
1109 module_init(imx_serial_init);
1110 module_exit(imx_serial_exit);
1112 MODULE_AUTHOR("Sascha Hauer");
1113 MODULE_DESCRIPTION("IMX generic serial port driver");
1114 MODULE_LICENSE("GPL");