2 * OMAP2 McSPI controller driver
4 * Copyright (C) 2005, 2006 Nokia Corporation
5 * Author: Samuel Ortiz <samuel.ortiz@nokia.com> and
6 * Juha Yrjölä <juha.yrjola@nokia.com>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
24 #include <linux/kernel.h>
25 #include <linux/init.h>
26 #include <linux/interrupt.h>
27 #include <linux/module.h>
28 #include <linux/device.h>
29 #include <linux/delay.h>
30 #include <linux/dma-mapping.h>
31 #include <linux/platform_device.h>
32 #include <linux/err.h>
33 #include <linux/clk.h>
35 #include <linux/spi/spi.h>
38 #include <asm/arch/dma.h>
39 #include <asm/arch/mcspi.h>
40 #include <asm/arch/clock.h>
42 #define OMAP2_MCSPI_MAX_FREQ 48000000
44 #define OMAP2_MCSPI_REVISION 0x00
45 #define OMAP2_MCSPI_SYSCONFIG 0x10
46 #define OMAP2_MCSPI_SYSSTATUS 0x14
47 #define OMAP2_MCSPI_IRQSTATUS 0x18
48 #define OMAP2_MCSPI_IRQENABLE 0x1c
49 #define OMAP2_MCSPI_WAKEUPENABLE 0x20
50 #define OMAP2_MCSPI_SYST 0x24
51 #define OMAP2_MCSPI_MODULCTRL 0x28
52 #define OMAP2_MCSPI_CHCONF0 0x2c
53 #define OMAP2_MCSPI_CHSTAT0 0x30
54 #define OMAP2_MCSPI_CHCTRL0 0x34
55 #define OMAP2_MCSPI_TX0 0x38
56 #define OMAP2_MCSPI_RX0 0x3c
58 #define OMAP2_MCSPI_SYSCONFIG_SOFTRESET (1 << 1)
60 #define OMAP2_MCSPI_SYSSTATUS_RESETDONE (1 << 0)
62 #define OMAP2_MCSPI_MODULCTRL_SINGLE (1 << 0)
63 #define OMAP2_MCSPI_MODULCTRL_MS (1 << 2)
64 #define OMAP2_MCSPI_MODULCTRL_STEST (1 << 3)
66 #define OMAP2_MCSPI_CHCONF_PHA (1 << 0)
67 #define OMAP2_MCSPI_CHCONF_POL (1 << 1)
68 #define OMAP2_MCSPI_CHCONF_CLKD_MASK (0x0f << 2)
69 #define OMAP2_MCSPI_CHCONF_EPOL (1 << 6)
70 #define OMAP2_MCSPI_CHCONF_WL_MASK (0x1f << 7)
71 #define OMAP2_MCSPI_CHCONF_TRM_RX_ONLY (0x01 << 12)
72 #define OMAP2_MCSPI_CHCONF_TRM_TX_ONLY (0x02 << 12)
73 #define OMAP2_MCSPI_CHCONF_TRM_MASK (0x03 << 12)
74 #define OMAP2_MCSPI_CHCONF_DMAW (1 << 14)
75 #define OMAP2_MCSPI_CHCONF_DMAR (1 << 15)
76 #define OMAP2_MCSPI_CHCONF_DPE0 (1 << 16)
77 #define OMAP2_MCSPI_CHCONF_DPE1 (1 << 17)
78 #define OMAP2_MCSPI_CHCONF_IS (1 << 18)
79 #define OMAP2_MCSPI_CHCONF_TURBO (1 << 19)
80 #define OMAP2_MCSPI_CHCONF_FORCE (1 << 20)
83 #define OMAP2_MCSPI_CHSTAT_RXS (1 << 0)
84 #define OMAP2_MCSPI_CHSTAT_TXS (1 << 1)
85 #define OMAP2_MCSPI_CHSTAT_EOT (1 << 2)
87 #define OMAP2_MCSPI_CHCTRL_EN (1 << 0)
89 /* We have 2 DMA channels per CS, one for RX and one for TX */
90 struct omap2_mcspi_dma {
97 struct completion dma_tx_completion;
98 struct completion dma_rx_completion;
102 struct work_struct work;
104 struct list_head msg_queue;
105 struct spi_master *master;
108 /* Virtual base address of the controller */
110 /* SPI1 has 4 channels, while SPI2 has 2 */
111 struct omap2_mcspi_dma *dma_channels;
114 struct omap2_mcspi_cs {
119 static struct workqueue_struct * omap2_mcspi_wq;
121 #define MOD_REG_BIT(val, mask, set) do { \
128 static inline void mcspi_write_reg(struct spi_master *master,
131 struct omap2_mcspi * mcspi = class_get_devdata(&master->cdev);
133 __raw_writel(val, mcspi->base + idx);
136 static inline u32 mcspi_read_reg(struct spi_master *master,
139 struct omap2_mcspi * mcspi = class_get_devdata(&master->cdev);
141 return __raw_readl(mcspi->base + idx);
144 static inline void mcspi_write_cs_reg(const struct spi_device *spi,
147 struct omap2_mcspi * mcspi = class_get_devdata(&spi->master->cdev);
149 __raw_writel(val, mcspi->base + spi->chip_select * 0x14 + idx);
152 static inline u32 mcspi_read_cs_reg(const struct spi_device *spi,
155 struct omap2_mcspi * mcspi = class_get_devdata(&spi->master->cdev);
157 return __raw_readl(mcspi->base + spi->chip_select * 0x14 + idx);
160 static void omap2_mcspi_set_dma_req(const struct spi_device *spi,
161 int is_read, int enable)
165 l = mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHCONF0);
167 if (is_read) /* 1 is read, 0 write */
168 rw = OMAP2_MCSPI_CHCONF_DMAR;
170 rw = OMAP2_MCSPI_CHCONF_DMAW;
172 MOD_REG_BIT(l, rw, enable);
173 mcspi_write_cs_reg(spi, OMAP2_MCSPI_CHCONF0, l);
176 static void omap2_mcspi_set_enable(const struct spi_device *spi, int enable)
180 l = mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHCTRL0);
181 MOD_REG_BIT(l, OMAP2_MCSPI_CHCTRL_EN, enable);
182 mcspi_write_cs_reg(spi, OMAP2_MCSPI_CHCTRL0, l);
185 static void omap2_mcspi_force_cs(struct spi_device *spi, int cs_active)
189 l = mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHCONF0);
190 MOD_REG_BIT(l, OMAP2_MCSPI_CHCONF_FORCE, cs_active);
191 mcspi_write_cs_reg(spi, OMAP2_MCSPI_CHCONF0, l);
194 static void omap2_mcspi_set_master_mode(struct spi_device *spi, int single_channel)
198 /* Need reset when switching from slave mode */
199 l = mcspi_read_reg(spi->master, OMAP2_MCSPI_MODULCTRL);
200 MOD_REG_BIT(l, OMAP2_MCSPI_MODULCTRL_STEST, 0);
201 MOD_REG_BIT(l, OMAP2_MCSPI_MODULCTRL_MS, 0);
202 MOD_REG_BIT(l, OMAP2_MCSPI_MODULCTRL_SINGLE, single_channel);
203 mcspi_write_reg(spi->master, OMAP2_MCSPI_MODULCTRL, l);
206 static void omap2_mcspi_txrx_dma(struct spi_device *spi,
207 struct spi_transfer *xfer)
209 struct omap2_mcspi * mcspi;
210 struct omap2_mcspi_cs * cs = spi->controller_state;
211 struct omap2_mcspi_dma * mcspi_dma;
212 unsigned int count, c;
213 unsigned long base, tx_reg, rx_reg;
214 int word_len, data_type, element_count;
219 mcspi = class_get_devdata(&spi->master->cdev);
220 mcspi_dma = &mcspi->dma_channels[spi->chip_select];
224 word_len = cs->word_len;
226 l = mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHCONF0);
227 l &= ~OMAP2_MCSPI_CHCONF_TRM_MASK;
228 if (xfer->tx_buf == NULL)
229 l |= OMAP2_MCSPI_CHCONF_TRM_RX_ONLY;
230 else if (xfer->rx_buf == NULL)
231 l |= OMAP2_MCSPI_CHCONF_TRM_TX_ONLY;
232 mcspi_write_cs_reg(spi, OMAP2_MCSPI_CHCONF0, l);
234 omap2_mcspi_set_enable(spi, 1);
236 base = io_v2p(mcspi->base) + spi->chip_select * 0x14;
237 tx_reg = base + OMAP2_MCSPI_TX0;
238 rx_reg = base + OMAP2_MCSPI_RX0;
243 data_type = OMAP_DMA_DATA_TYPE_S8;
244 element_count = count;
245 } else if (word_len <= 16) {
246 data_type = OMAP_DMA_DATA_TYPE_S16;
247 element_count = count >> 1;
248 } else if (word_len <= 32) {
249 data_type = OMAP_DMA_DATA_TYPE_S32;
250 element_count = count >> 2;
254 /* RX_ONLY mode needs dummy data in TX reg */
256 __raw_writel(0, mcspi->base +
257 spi->chip_select * 0x14 + OMAP2_MCSPI_TX0);
260 xfer->tx_dma = dma_map_single(&spi->dev, (void *) tx, count,
262 if (dma_mapping_error(xfer->tx_dma)) {
263 printk(KERN_ERR "%s(): Couldn't DMA map a %d bytes TX buffer\n",
264 __FUNCTION__, count);
268 omap_set_dma_transfer_params(mcspi_dma->dma_tx_channel,
269 data_type, element_count, 1,
270 OMAP_DMA_SYNC_ELEMENT,
271 mcspi_dma->dma_tx_sync_dev, 0);
273 omap_set_dma_dest_params(mcspi_dma->dma_tx_channel, 0,
274 OMAP_DMA_AMODE_CONSTANT,
277 omap_set_dma_src_params(mcspi_dma->dma_tx_channel, 0,
278 OMAP_DMA_AMODE_POST_INC,
283 xfer->rx_dma = dma_map_single(&spi->dev, rx, count,
285 if (dma_mapping_error(xfer->rx_dma)) {
286 printk(KERN_ERR "%s(): Couldn't DMA map a %d bytes RX buffer\n",
287 __FUNCTION__, count);
289 dma_unmap_single(NULL, xfer->tx_dma,
290 count, DMA_TO_DEVICE);
294 omap_set_dma_transfer_params(mcspi_dma->dma_rx_channel,
295 data_type, element_count, 1,
296 OMAP_DMA_SYNC_ELEMENT,
297 mcspi_dma->dma_rx_sync_dev, 1);
299 omap_set_dma_src_params(mcspi_dma->dma_rx_channel, 0,
300 OMAP_DMA_AMODE_CONSTANT,
303 omap_set_dma_dest_params(mcspi_dma->dma_rx_channel, 0,
304 OMAP_DMA_AMODE_POST_INC,
309 omap_start_dma(mcspi_dma->dma_tx_channel);
310 omap2_mcspi_set_dma_req(spi, 0, 1);
314 omap_start_dma(mcspi_dma->dma_rx_channel);
315 omap2_mcspi_set_dma_req(spi, 1, 1);
319 wait_for_completion(&mcspi_dma->dma_tx_completion);
320 dma_unmap_single(NULL, xfer->tx_dma, count, DMA_TO_DEVICE);
324 wait_for_completion(&mcspi_dma->dma_rx_completion);
325 dma_unmap_single(NULL, xfer->rx_dma, count, DMA_FROM_DEVICE);
328 omap2_mcspi_set_enable(spi, 0);
331 static int mcspi_wait_for_reg_bit(unsigned long reg, unsigned long bit)
333 unsigned long timeout;
335 timeout = jiffies + msecs_to_jiffies(1000);
336 while (!(__raw_readl(reg) & bit)) {
337 if (time_after(jiffies, timeout))
343 static void omap2_mcspi_txrx_pio(struct spi_device *spi, struct spi_transfer *xfer)
345 struct omap2_mcspi * mcspi;
346 struct omap2_mcspi_cs *cs = spi->controller_state;
347 unsigned int count, c;
349 unsigned long base, tx_reg, rx_reg, chstat_reg;
352 mcspi = class_get_devdata(&spi->master->cdev);
355 word_len = cs->word_len;
357 l = mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHCONF0);
358 l &= ~OMAP2_MCSPI_CHCONF_TRM_MASK;
359 if (xfer->tx_buf == NULL)
360 l |= OMAP2_MCSPI_CHCONF_TRM_RX_ONLY;
361 else if (xfer->rx_buf == NULL)
362 l |= OMAP2_MCSPI_CHCONF_TRM_TX_ONLY;
363 mcspi_write_cs_reg(spi, OMAP2_MCSPI_CHCONF0, l);
365 omap2_mcspi_set_enable(spi, 1);
367 /* We store the pre-calculated register addresses on stack to speed
368 * up the transfer loop. */
369 base = mcspi->base + spi->chip_select * 0x14;
370 tx_reg = base + OMAP2_MCSPI_TX0;
371 rx_reg = base + OMAP2_MCSPI_RX0;
372 chstat_reg = base + OMAP2_MCSPI_CHSTAT0;
374 /* RX_ONLY mode needs dummy data in TX reg */
375 if (xfer->tx_buf == NULL)
376 __raw_writel(0, tx_reg);
387 if (mcspi_wait_for_reg_bit(chstat_reg, OMAP2_MCSPI_CHSTAT_TXS) < 0) {
388 dev_err(&spi->dev, "TXS timed out\n");
392 dev_dbg(&spi->dev, "write-%d %02x\n",
395 __raw_writel(*tx, tx_reg);
398 if (mcspi_wait_for_reg_bit(chstat_reg, OMAP2_MCSPI_CHSTAT_RXS) < 0) {
399 dev_err(&spi->dev, "RXS timed out\n");
402 if (c == 0 && tx == NULL)
403 omap2_mcspi_set_enable(spi, 0);
404 *rx++ = __raw_readl(rx_reg);
406 dev_dbg(&spi->dev, "read-%d %02x\n",
407 word_len, *(rx - 1));
411 } else if (word_len <= 16) {
420 if (mcspi_wait_for_reg_bit(chstat_reg, OMAP2_MCSPI_CHSTAT_TXS) < 0) {
421 dev_err(&spi->dev, "TXS timed out\n");
425 dev_dbg(&spi->dev, "write-%d %04x\n",
428 __raw_writel(*tx++, tx_reg);
431 if (mcspi_wait_for_reg_bit(chstat_reg, OMAP2_MCSPI_CHSTAT_RXS) < 0) {
432 dev_err(&spi->dev, "RXS timed out\n");
435 if (c == 0 && tx == NULL)
436 omap2_mcspi_set_enable(spi, 0);
437 *rx++ = __raw_readl(rx_reg);
439 dev_dbg(&spi->dev, "read-%d %04x\n",
440 word_len, *(rx - 1));
444 } else if (word_len <= 32) {
453 if (mcspi_wait_for_reg_bit(chstat_reg, OMAP2_MCSPI_CHSTAT_TXS) < 0) {
454 dev_err(&spi->dev, "TXS timed out\n");
458 dev_dbg(&spi->dev, "write-%d %04x\n",
461 __raw_writel(*tx++, tx_reg);
464 if (mcspi_wait_for_reg_bit(chstat_reg, OMAP2_MCSPI_CHSTAT_RXS) < 0) {
465 dev_err(&spi->dev, "RXS timed out\n");
468 if (c == 0 && tx == NULL)
469 omap2_mcspi_set_enable(spi, 0);
470 *rx++ = __raw_readl(rx_reg);
472 dev_dbg(&spi->dev, "read-%d %04x\n",
473 word_len, *(rx - 1));
479 if (xfer->tx_buf != NULL) {
480 if (mcspi_wait_for_reg_bit(chstat_reg, OMAP2_MCSPI_CHSTAT_TXS) < 0) {
481 dev_err(&spi->dev, "TXS timed out\n");
484 if (mcspi_wait_for_reg_bit(chstat_reg, OMAP2_MCSPI_CHSTAT_EOT) < 0)
485 dev_err(&spi->dev, "EOT timed out\n");
487 omap2_mcspi_set_enable(spi, 0);
491 static int omap2_mcspi_setup_transfer(struct spi_device *spi,
492 struct spi_transfer *t)
494 struct omap2_mcspi_cs *cs = spi->controller_state;
495 struct omap2_mcspi_device_config *conf;
496 struct omap2_mcspi * mcspi;
498 u8 word_len = spi->bits_per_word;
500 mcspi = class_get_devdata(&spi->master->cdev);
502 if (t != NULL && t->bits_per_word)
503 word_len = t->bits_per_word;
507 if (spi->bits_per_word > 32)
509 cs->word_len = word_len;
511 conf = (struct omap2_mcspi_device_config *) spi->controller_data;
513 clk_enable(mcspi->ick);
514 clk_enable(mcspi->fck);
516 if (conf->single_channel == 1)
517 omap2_mcspi_set_master_mode(spi, 1);
519 omap2_mcspi_set_master_mode(spi, 0);
521 if (spi->max_speed_hz) {
522 while (div <= 15 && (OMAP2_MCSPI_MAX_FREQ / (1 << div)) > spi->max_speed_hz)
527 if (spi->chip_select > 3 ||
528 word_len < 4 || word_len > 32 ||
530 dev_err(&spi->dev, "Invalid McSPI channel setting\n");
531 clk_disable(mcspi->fck);
532 clk_disable(mcspi->ick);
536 l = mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHCONF0);
537 l &= ~OMAP2_MCSPI_CHCONF_IS;
538 l &= ~OMAP2_MCSPI_CHCONF_DPE1;
539 l |= OMAP2_MCSPI_CHCONF_DPE0;
540 l &= ~OMAP2_MCSPI_CHCONF_WL_MASK;
541 l |= (word_len - 1) << 7;
542 if (!(spi->mode & SPI_CS_HIGH))
543 l |= OMAP2_MCSPI_CHCONF_EPOL;
545 l &= ~OMAP2_MCSPI_CHCONF_EPOL;
546 l &= ~OMAP2_MCSPI_CHCONF_CLKD_MASK;
548 if (spi->mode & SPI_CPOL)
549 l |= OMAP2_MCSPI_CHCONF_POL;
551 l &= ~OMAP2_MCSPI_CHCONF_POL;
552 if (spi->mode & SPI_CPHA)
553 l &= ~OMAP2_MCSPI_CHCONF_PHA;
555 l |= OMAP2_MCSPI_CHCONF_PHA;
556 mcspi_write_cs_reg(spi, OMAP2_MCSPI_CHCONF0, l);
558 dev_dbg(&spi->dev, "setup: speed %d, sample %s edge, clk %s inverted\n",
559 OMAP2_MCSPI_MAX_FREQ / (1 << div),
560 (spi->mode & SPI_CPHA) ? "odd" : "even",
561 (spi->mode & SPI_CPOL) ? "" : "not");
563 clk_disable(mcspi->fck);
564 clk_disable(mcspi->ick);
569 static void omap2_mcspi_dma_rx_callback(int lch, u16 ch_status, void *data)
571 struct spi_device * spi = (struct spi_device *)data;
572 struct omap2_mcspi * mcspi;
573 struct omap2_mcspi_dma * mcspi_dma;
575 mcspi = class_get_devdata(&spi->master->cdev);
576 mcspi_dma = &(mcspi->dma_channels[spi->chip_select]);
578 complete(&mcspi_dma->dma_rx_completion);
580 /* We must disable the DMA RX request */
581 omap2_mcspi_set_dma_req(spi, 1, 0);
584 static void omap2_mcspi_dma_tx_callback(int lch, u16 ch_status, void *data)
586 struct spi_device * spi = (struct spi_device *)data;
587 struct omap2_mcspi * mcspi;
588 struct omap2_mcspi_dma * mcspi_dma;
590 mcspi = class_get_devdata(&spi->master->cdev);
591 mcspi_dma = &(mcspi->dma_channels[spi->chip_select]);
593 complete(&mcspi_dma->dma_tx_completion);
595 /* We must disable the DMA TX request */
596 omap2_mcspi_set_dma_req(spi, 0, 0);
599 static int omap2_mcspi_request_dma(struct spi_device *spi)
601 int rx_dev_id, tx_dev_id;
602 struct spi_master *master = spi->master;
603 struct omap2_mcspi * mcspi;
604 struct omap2_mcspi_dma * mcspi_dma;
606 mcspi = class_get_devdata(&master->cdev);
607 mcspi_dma = &(mcspi->dma_channels[spi->chip_select]);
609 if (master->bus_num == 1) {
610 switch (spi->chip_select) {
612 rx_dev_id = OMAP24XX_DMA_SPI1_RX0;
613 tx_dev_id = OMAP24XX_DMA_SPI1_TX0;
616 rx_dev_id = OMAP24XX_DMA_SPI1_RX1;
617 tx_dev_id = OMAP24XX_DMA_SPI1_TX1;
620 rx_dev_id = OMAP24XX_DMA_SPI1_RX2;
621 tx_dev_id = OMAP24XX_DMA_SPI1_TX2;
624 rx_dev_id = OMAP24XX_DMA_SPI1_RX3;
625 tx_dev_id = OMAP24XX_DMA_SPI1_TX3;
630 } else if (master->bus_num == 2) {
631 /* McSPI 2 has 1 chipselect */
632 switch (spi->chip_select) {
634 rx_dev_id = OMAP24XX_DMA_SPI2_RX0;
635 tx_dev_id = OMAP24XX_DMA_SPI2_TX0;
638 rx_dev_id = OMAP24XX_DMA_SPI2_RX1;
639 tx_dev_id = OMAP24XX_DMA_SPI2_TX1;
648 if (omap_request_dma(rx_dev_id, "McSPI RX",
649 omap2_mcspi_dma_rx_callback, spi,
650 &mcspi_dma->dma_rx_channel)) {
651 printk(KERN_ERR "Unable to request DMA channel for McSPI RX\n");
655 if (omap_request_dma(tx_dev_id, "McSPI TX",
656 omap2_mcspi_dma_tx_callback, spi,
657 &mcspi_dma->dma_tx_channel)) {
658 omap_free_dma(mcspi_dma->dma_rx_channel);
659 mcspi_dma->dma_rx_channel = -1;
660 printk(KERN_ERR "Unable to request DMA channel for McSPI TX\n");
664 mcspi_dma->dma_rx_sync_dev = rx_dev_id;
665 mcspi_dma->dma_tx_sync_dev = tx_dev_id;
667 init_completion(&mcspi_dma->dma_rx_completion);
668 init_completion(&mcspi_dma->dma_tx_completion);
673 static int omap2_mcspi_setup(struct spi_device *spi)
676 struct omap2_mcspi * mcspi;
677 struct omap2_mcspi_dma * mcspi_dma;
678 struct omap2_mcspi_cs *cs = spi->controller_state;
680 mcspi = class_get_devdata(&spi->master->cdev);
681 mcspi_dma = &mcspi->dma_channels[spi->chip_select];
684 cs = kzalloc(sizeof *cs, GFP_KERNEL);
687 spi->controller_state = cs;
690 if (mcspi_dma->dma_rx_channel == -1 ||
691 mcspi_dma->dma_tx_channel == -1) {
692 ret = omap2_mcspi_request_dma(spi);
697 return omap2_mcspi_setup_transfer(spi, NULL);
700 static void omap2_mcspi_cleanup(struct spi_device *spi)
702 struct omap2_mcspi * mcspi;
703 struct omap2_mcspi_dma * mcspi_dma;
705 mcspi = class_get_devdata(&spi->master->cdev);
706 mcspi_dma = &mcspi->dma_channels[spi->chip_select];
708 if (spi->controller_state != NULL)
709 kfree(spi->controller_state);
711 if (mcspi_dma->dma_rx_channel != -1 &&
712 mcspi_dma->dma_tx_channel != -1) {
713 omap_free_dma(mcspi_dma->dma_tx_channel);
714 omap_free_dma(mcspi_dma->dma_rx_channel);
718 static void omap2_mcspi_work(struct work_struct *work)
720 struct omap2_mcspi *mcspi = container_of(work, struct omap2_mcspi, work);
723 spin_lock_irqsave(&mcspi->lock, flags);
724 while (!list_empty(&mcspi->msg_queue)) {
725 struct spi_message *m;
726 struct spi_device *spi;
727 struct spi_transfer *t = NULL;
729 struct omap2_mcspi_device_config *conf;
730 struct omap2_mcspi_cs *cs;
731 int par_override = 0;
734 m = container_of(mcspi->msg_queue.next, struct spi_message,
737 list_del_init(&m->queue);
738 spin_unlock_irqrestore(&mcspi->lock, flags);
741 conf = (struct omap2_mcspi_device_config *) spi->controller_data;
742 cs = (struct omap2_mcspi_cs *) spi->controller_state;
744 list_for_each_entry(t, &m->transfers, transfer_list) {
745 if (t->tx_buf == NULL && t->rx_buf == NULL && t->len) {
749 if (par_override || t->speed_hz || t->bits_per_word) {
751 status = omap2_mcspi_setup_transfer(spi, t);
754 if (!t->speed_hz && !t->bits_per_word)
758 clk_enable(mcspi->ick);
759 clk_enable(mcspi->fck);
762 omap2_mcspi_force_cs(spi, 1);
766 if (m->is_dma_mapped &&
767 (t->tx_dma != 0 || t->rx_dma != 0))
768 omap2_mcspi_txrx_dma(spi, t);
770 omap2_mcspi_txrx_pio(spi, t);
773 /* In the last transfer entry the flag means
775 if (t->transfer_list.next != &m->transfers)
776 omap2_mcspi_force_cs(spi, 0);
779 clk_disable(mcspi->ick);
780 clk_disable(mcspi->fck);
783 clk_enable(mcspi->ick);
784 clk_enable(mcspi->fck);
785 /* Restore defaults they are overriden */
788 status = omap2_mcspi_setup_transfer(spi, NULL);
792 omap2_mcspi_force_cs(spi, 0);
793 clk_disable(mcspi->ick);
794 clk_disable(mcspi->fck);
797 m->complete(m->context);
799 spin_lock_irqsave(&mcspi->lock, flags);
801 spin_unlock_irqrestore(&mcspi->lock, flags);
804 static int omap2_mcspi_transfer(struct spi_device *spi, struct spi_message *m)
806 struct omap2_mcspi *mcspi;
809 m->actual_length = 0;
812 mcspi = class_get_devdata(&spi->master->cdev);
814 spin_lock_irqsave(&mcspi->lock, flags);
815 list_add_tail(&m->queue, &mcspi->msg_queue);
816 spin_unlock_irqrestore(&mcspi->lock, flags);
818 queue_work(omap2_mcspi_wq, &mcspi->work);
823 static int __devinit omap2_mcspi_reset(struct spi_master *master)
826 mcspi_write_reg(master, OMAP2_MCSPI_SYSCONFIG,
827 OMAP2_MCSPI_SYSCONFIG_SOFTRESET);
828 while (!(mcspi_read_reg(master, OMAP2_MCSPI_SYSSTATUS) & OMAP2_MCSPI_SYSSTATUS_RESETDONE));
834 static int __devinit omap2_mcspi_probe(struct platform_device *pdev)
836 struct spi_master *master;
837 struct omap2_mcspi_platform_config *pdata = pdev->dev.platform_data;
838 struct omap2_mcspi *mcspi;
845 master = spi_alloc_master(&pdev->dev, sizeof *mcspi);
846 if (master == NULL) {
847 dev_err(&pdev->dev, "master allocation failed\n");
852 master->bus_num = pdev->id;
854 master->setup = omap2_mcspi_setup;
855 master->transfer = omap2_mcspi_transfer;
856 master->cleanup = omap2_mcspi_cleanup;
857 master->num_chipselect = pdata->num_cs;
859 if (class_device_get(&master->cdev) == NULL) {
860 dev_err(&pdev->dev, "no master->cdev");
865 dev_set_drvdata(&pdev->dev, master);
867 mcspi = class_get_devdata(&master->cdev);
868 mcspi->master = master;
870 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
876 mcspi->base = io_p2v(r->start);
878 INIT_WORK(&mcspi->work, omap2_mcspi_work);
880 spin_lock_init(&mcspi->lock);
881 INIT_LIST_HEAD(&mcspi->msg_queue);
883 mcspi->ick = clk_get(&pdev->dev, "mcspi_ick");
884 if (IS_ERR(mcspi->ick)) {
885 dev_err(&pdev->dev, "can't get mcspi_ick\n");
886 status = PTR_ERR(mcspi->ick);
889 mcspi->fck = clk_get(&pdev->dev, "mcspi_fck");
890 if (IS_ERR(mcspi->fck)) {
891 dev_err(&pdev->dev, "can't get mcspi_fck\n");
892 status = PTR_ERR(mcspi->fck);
896 mcspi->dma_channels =
897 (struct omap2_mcspi_dma *)kzalloc(master->num_chipselect *
898 sizeof(struct omap2_mcspi_dma),
901 if (mcspi->dma_channels == NULL)
904 for (i = 0; i < master->num_chipselect; i++) {
905 mcspi->dma_channels[i].dma_rx_channel = -1;
906 mcspi->dma_channels[i].dma_tx_channel = -1;
909 if (omap2_mcspi_reset(master) < 0)
912 status = spi_register_master(master);
919 kfree(mcspi->dma_channels);
925 class_device_put(&master->cdev);
930 static int __devexit omap2_mcspi_remove(struct platform_device *pdev)
932 struct spi_master *master;
933 struct omap2_mcspi *mcspi;
935 master = dev_get_drvdata(&pdev->dev);
937 spi_unregister_master(master);
938 mcspi = class_get_devdata(&master->cdev);
941 class_device_put(&master->cdev);
942 kfree(mcspi->dma_channels);
947 struct platform_driver omap2_mcspi_driver = {
949 .name = "omap2_mcspi",
950 .owner = THIS_MODULE,
952 .probe = omap2_mcspi_probe,
953 .remove = __devexit_p(omap2_mcspi_remove),
955 EXPORT_SYMBOL_GPL(omap2_mcspi_driver);
958 static int __init omap2_mcspi_init(void)
960 printk(KERN_INFO "OMAP24xx McSPI driver initializing\n");
961 omap2_mcspi_wq = create_workqueue("OMAP McSPI");
962 if (omap2_mcspi_wq == NULL)
964 return platform_driver_register(&omap2_mcspi_driver);
966 subsys_initcall(omap2_mcspi_init);
968 static void __exit omap2_mcspi_exit(void)
970 platform_driver_unregister(&omap2_mcspi_driver);
972 module_exit(omap2_mcspi_exit);
974 MODULE_LICENSE("GPL");