2 * Copyright (C) 2005 Stephen Street / StreetFire Sound Labs
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
19 #include <linux/init.h>
20 #include <linux/module.h>
21 #include <linux/device.h>
22 #include <linux/ioport.h>
23 #include <linux/errno.h>
24 #include <linux/interrupt.h>
25 #include <linux/platform_device.h>
26 #include <linux/dma-mapping.h>
27 #include <linux/spi/spi.h>
28 #include <linux/workqueue.h>
29 #include <linux/delay.h>
30 #include <linux/clk.h>
31 #include <linux/gpio.h>
35 #include <asm/delay.h>
38 #include <mach/regs-ssp.h>
40 #include <mach/pxa2xx_spi.h>
42 MODULE_AUTHOR("Stephen Street");
43 MODULE_DESCRIPTION("PXA2xx SSP SPI Controller");
44 MODULE_LICENSE("GPL");
45 MODULE_ALIAS("platform:pxa2xx-spi");
49 #define RX_THRESH_DFLT 8
50 #define TX_THRESH_DFLT 8
51 #define TIMOUT_DFLT 1000
53 #define DMA_INT_MASK (DCSR_ENDINTR | DCSR_STARTINTR | DCSR_BUSERR)
54 #define RESET_DMA_CHANNEL (DCSR_NODESC | DMA_INT_MASK)
55 #define IS_DMA_ALIGNED(x) ((((u32)(x)) & 0x07) == 0)
56 #define MAX_DMA_LEN 8191
59 * for testing SSCR1 changes that require SSP restart, basically
60 * everything except the service and interrupt enables, the pxa270 developer
61 * manual says only SSCR1_SCFR, SSCR1_SPH, SSCR1_SPO need to be in this
62 * list, but the PXA255 dev man says all bits without really meaning the
63 * service and interrupt enables
65 #define SSCR1_CHANGE_MASK (SSCR1_TTELP | SSCR1_TTE | SSCR1_SCFR \
66 | SSCR1_ECRA | SSCR1_ECRB | SSCR1_SCLKDIR \
67 | SSCR1_SFRMDIR | SSCR1_RWOT | SSCR1_TRAIL \
68 | SSCR1_IFS | SSCR1_STRF | SSCR1_EFWR \
69 | SSCR1_RFT | SSCR1_TFT | SSCR1_MWDS \
70 | SSCR1_SPH | SSCR1_SPO | SSCR1_LBM)
72 #define DEFINE_SSP_REG(reg, off) \
73 static inline u32 read_##reg(void const __iomem *p) \
74 { return __raw_readl(p + (off)); } \
76 static inline void write_##reg(u32 v, void __iomem *p) \
77 { __raw_writel(v, p + (off)); }
79 DEFINE_SSP_REG(SSCR0, 0x00)
80 DEFINE_SSP_REG(SSCR1, 0x04)
81 DEFINE_SSP_REG(SSSR, 0x08)
82 DEFINE_SSP_REG(SSITR, 0x0c)
83 DEFINE_SSP_REG(SSDR, 0x10)
84 DEFINE_SSP_REG(SSTO, 0x28)
85 DEFINE_SSP_REG(SSPSP, 0x2c)
87 #define START_STATE ((void*)0)
88 #define RUNNING_STATE ((void*)1)
89 #define DONE_STATE ((void*)2)
90 #define ERROR_STATE ((void*)-1)
92 #define QUEUE_RUNNING 0
93 #define QUEUE_STOPPED 1
96 /* Driver model hookup */
97 struct platform_device *pdev;
100 struct ssp_device *ssp;
102 /* SPI framework hookup */
103 enum pxa_ssp_type ssp_type;
104 struct spi_master *master;
107 struct pxa2xx_spi_master *master_info;
109 /* DMA setup stuff */
114 /* SSP register addresses */
115 void __iomem *ioaddr;
124 /* Driver message queue */
125 struct workqueue_struct *workqueue;
126 struct work_struct pump_messages;
128 struct list_head queue;
132 /* Message Transfer pump */
133 struct tasklet_struct pump_transfers;
135 /* Current message transfer state info */
136 struct spi_message* cur_msg;
137 struct spi_transfer* cur_transfer;
138 struct chip_data *cur_chip;
151 int (*write)(struct driver_data *drv_data);
152 int (*read)(struct driver_data *drv_data);
153 irqreturn_t (*transfer_handler)(struct driver_data *drv_data);
154 void (*cs_control)(u32 command);
171 int gpio_cs_inverted;
172 int (*write)(struct driver_data *drv_data);
173 int (*read)(struct driver_data *drv_data);
174 void (*cs_control)(u32 command);
177 static void pump_messages(struct work_struct *work);
179 static void cs_assert(struct driver_data *drv_data)
181 struct chip_data *chip = drv_data->cur_chip;
183 if (chip->cs_control) {
184 chip->cs_control(PXA2XX_CS_ASSERT);
188 if (gpio_is_valid(chip->gpio_cs))
189 gpio_set_value(chip->gpio_cs, chip->gpio_cs_inverted);
192 static void cs_deassert(struct driver_data *drv_data)
194 struct chip_data *chip = drv_data->cur_chip;
196 if (chip->cs_control) {
197 chip->cs_control(PXA2XX_CS_ASSERT);
201 if (gpio_is_valid(chip->gpio_cs))
202 gpio_set_value(chip->gpio_cs, !chip->gpio_cs_inverted);
205 static int flush(struct driver_data *drv_data)
207 unsigned long limit = loops_per_jiffy << 1;
209 void __iomem *reg = drv_data->ioaddr;
212 while (read_SSSR(reg) & SSSR_RNE) {
215 } while ((read_SSSR(reg) & SSSR_BSY) && limit--);
216 write_SSSR(SSSR_ROR, reg);
221 static int null_writer(struct driver_data *drv_data)
223 void __iomem *reg = drv_data->ioaddr;
224 u8 n_bytes = drv_data->n_bytes;
226 if (((read_SSSR(reg) & 0x00000f00) == 0x00000f00)
227 || (drv_data->tx == drv_data->tx_end))
231 drv_data->tx += n_bytes;
236 static int null_reader(struct driver_data *drv_data)
238 void __iomem *reg = drv_data->ioaddr;
239 u8 n_bytes = drv_data->n_bytes;
241 while ((read_SSSR(reg) & SSSR_RNE)
242 && (drv_data->rx < drv_data->rx_end)) {
244 drv_data->rx += n_bytes;
247 return drv_data->rx == drv_data->rx_end;
250 static int u8_writer(struct driver_data *drv_data)
252 void __iomem *reg = drv_data->ioaddr;
254 if (((read_SSSR(reg) & 0x00000f00) == 0x00000f00)
255 || (drv_data->tx == drv_data->tx_end))
258 write_SSDR(*(u8 *)(drv_data->tx), reg);
264 static int u8_reader(struct driver_data *drv_data)
266 void __iomem *reg = drv_data->ioaddr;
268 while ((read_SSSR(reg) & SSSR_RNE)
269 && (drv_data->rx < drv_data->rx_end)) {
270 *(u8 *)(drv_data->rx) = read_SSDR(reg);
274 return drv_data->rx == drv_data->rx_end;
277 static int u16_writer(struct driver_data *drv_data)
279 void __iomem *reg = drv_data->ioaddr;
281 if (((read_SSSR(reg) & 0x00000f00) == 0x00000f00)
282 || (drv_data->tx == drv_data->tx_end))
285 write_SSDR(*(u16 *)(drv_data->tx), reg);
291 static int u16_reader(struct driver_data *drv_data)
293 void __iomem *reg = drv_data->ioaddr;
295 while ((read_SSSR(reg) & SSSR_RNE)
296 && (drv_data->rx < drv_data->rx_end)) {
297 *(u16 *)(drv_data->rx) = read_SSDR(reg);
301 return drv_data->rx == drv_data->rx_end;
304 static int u32_writer(struct driver_data *drv_data)
306 void __iomem *reg = drv_data->ioaddr;
308 if (((read_SSSR(reg) & 0x00000f00) == 0x00000f00)
309 || (drv_data->tx == drv_data->tx_end))
312 write_SSDR(*(u32 *)(drv_data->tx), reg);
318 static int u32_reader(struct driver_data *drv_data)
320 void __iomem *reg = drv_data->ioaddr;
322 while ((read_SSSR(reg) & SSSR_RNE)
323 && (drv_data->rx < drv_data->rx_end)) {
324 *(u32 *)(drv_data->rx) = read_SSDR(reg);
328 return drv_data->rx == drv_data->rx_end;
331 static void *next_transfer(struct driver_data *drv_data)
333 struct spi_message *msg = drv_data->cur_msg;
334 struct spi_transfer *trans = drv_data->cur_transfer;
336 /* Move to next transfer */
337 if (trans->transfer_list.next != &msg->transfers) {
338 drv_data->cur_transfer =
339 list_entry(trans->transfer_list.next,
342 return RUNNING_STATE;
347 static int map_dma_buffers(struct driver_data *drv_data)
349 struct spi_message *msg = drv_data->cur_msg;
350 struct device *dev = &msg->spi->dev;
352 if (!drv_data->cur_chip->enable_dma)
355 if (msg->is_dma_mapped)
356 return drv_data->rx_dma && drv_data->tx_dma;
358 if (!IS_DMA_ALIGNED(drv_data->rx) || !IS_DMA_ALIGNED(drv_data->tx))
361 /* Modify setup if rx buffer is null */
362 if (drv_data->rx == NULL) {
363 *drv_data->null_dma_buf = 0;
364 drv_data->rx = drv_data->null_dma_buf;
365 drv_data->rx_map_len = 4;
367 drv_data->rx_map_len = drv_data->len;
370 /* Modify setup if tx buffer is null */
371 if (drv_data->tx == NULL) {
372 *drv_data->null_dma_buf = 0;
373 drv_data->tx = drv_data->null_dma_buf;
374 drv_data->tx_map_len = 4;
376 drv_data->tx_map_len = drv_data->len;
378 /* Stream map the tx buffer. Always do DMA_TO_DEVICE first
379 * so we flush the cache *before* invalidating it, in case
380 * the tx and rx buffers overlap.
382 drv_data->tx_dma = dma_map_single(dev, drv_data->tx,
383 drv_data->tx_map_len, DMA_TO_DEVICE);
384 if (dma_mapping_error(dev, drv_data->tx_dma))
387 /* Stream map the rx buffer */
388 drv_data->rx_dma = dma_map_single(dev, drv_data->rx,
389 drv_data->rx_map_len, DMA_FROM_DEVICE);
390 if (dma_mapping_error(dev, drv_data->rx_dma)) {
391 dma_unmap_single(dev, drv_data->tx_dma,
392 drv_data->tx_map_len, DMA_TO_DEVICE);
399 static void unmap_dma_buffers(struct driver_data *drv_data)
403 if (!drv_data->dma_mapped)
406 if (!drv_data->cur_msg->is_dma_mapped) {
407 dev = &drv_data->cur_msg->spi->dev;
408 dma_unmap_single(dev, drv_data->rx_dma,
409 drv_data->rx_map_len, DMA_FROM_DEVICE);
410 dma_unmap_single(dev, drv_data->tx_dma,
411 drv_data->tx_map_len, DMA_TO_DEVICE);
414 drv_data->dma_mapped = 0;
417 /* caller already set message->status; dma and pio irqs are blocked */
418 static void giveback(struct driver_data *drv_data)
420 struct spi_transfer* last_transfer;
422 struct spi_message *msg;
424 spin_lock_irqsave(&drv_data->lock, flags);
425 msg = drv_data->cur_msg;
426 drv_data->cur_msg = NULL;
427 drv_data->cur_transfer = NULL;
428 queue_work(drv_data->workqueue, &drv_data->pump_messages);
429 spin_unlock_irqrestore(&drv_data->lock, flags);
431 last_transfer = list_entry(msg->transfers.prev,
435 /* Delay if requested before any change in chip select */
436 if (last_transfer->delay_usecs)
437 udelay(last_transfer->delay_usecs);
439 /* Drop chip select UNLESS cs_change is true or we are returning
440 * a message with an error, or next message is for another chip
442 if (!last_transfer->cs_change)
443 cs_deassert(drv_data);
445 struct spi_message *next_msg;
447 /* Holding of cs was hinted, but we need to make sure
448 * the next message is for the same chip. Don't waste
449 * time with the following tests unless this was hinted.
451 * We cannot postpone this until pump_messages, because
452 * after calling msg->complete (below) the driver that
453 * sent the current message could be unloaded, which
454 * could invalidate the cs_control() callback...
457 /* get a pointer to the next message, if any */
458 spin_lock_irqsave(&drv_data->lock, flags);
459 if (list_empty(&drv_data->queue))
462 next_msg = list_entry(drv_data->queue.next,
463 struct spi_message, queue);
464 spin_unlock_irqrestore(&drv_data->lock, flags);
466 /* see if the next and current messages point
469 if (next_msg && next_msg->spi != msg->spi)
471 if (!next_msg || msg->state == ERROR_STATE)
472 cs_deassert(drv_data);
477 msg->complete(msg->context);
479 drv_data->cur_chip = NULL;
482 static int wait_ssp_rx_stall(void const __iomem *ioaddr)
484 unsigned long limit = loops_per_jiffy << 1;
486 while ((read_SSSR(ioaddr) & SSSR_BSY) && limit--)
492 static int wait_dma_channel_stop(int channel)
494 unsigned long limit = loops_per_jiffy << 1;
496 while (!(DCSR(channel) & DCSR_STOPSTATE) && limit--)
502 static void dma_error_stop(struct driver_data *drv_data, const char *msg)
504 void __iomem *reg = drv_data->ioaddr;
507 DCSR(drv_data->rx_channel) = RESET_DMA_CHANNEL;
508 DCSR(drv_data->tx_channel) = RESET_DMA_CHANNEL;
509 write_SSSR(drv_data->clear_sr, reg);
510 write_SSCR1(read_SSCR1(reg) & ~drv_data->dma_cr1, reg);
511 if (drv_data->ssp_type != PXA25x_SSP)
514 write_SSCR0(read_SSCR0(reg) & ~SSCR0_SSE, reg);
516 unmap_dma_buffers(drv_data);
518 dev_err(&drv_data->pdev->dev, "%s\n", msg);
520 drv_data->cur_msg->state = ERROR_STATE;
521 tasklet_schedule(&drv_data->pump_transfers);
524 static void dma_transfer_complete(struct driver_data *drv_data)
526 void __iomem *reg = drv_data->ioaddr;
527 struct spi_message *msg = drv_data->cur_msg;
529 /* Clear and disable interrupts on SSP and DMA channels*/
530 write_SSCR1(read_SSCR1(reg) & ~drv_data->dma_cr1, reg);
531 write_SSSR(drv_data->clear_sr, reg);
532 DCSR(drv_data->tx_channel) = RESET_DMA_CHANNEL;
533 DCSR(drv_data->rx_channel) = RESET_DMA_CHANNEL;
535 if (wait_dma_channel_stop(drv_data->rx_channel) == 0)
536 dev_err(&drv_data->pdev->dev,
537 "dma_handler: dma rx channel stop failed\n");
539 if (wait_ssp_rx_stall(drv_data->ioaddr) == 0)
540 dev_err(&drv_data->pdev->dev,
541 "dma_transfer: ssp rx stall failed\n");
543 unmap_dma_buffers(drv_data);
545 /* update the buffer pointer for the amount completed in dma */
546 drv_data->rx += drv_data->len -
547 (DCMD(drv_data->rx_channel) & DCMD_LENGTH);
549 /* read trailing data from fifo, it does not matter how many
550 * bytes are in the fifo just read until buffer is full
551 * or fifo is empty, which ever occurs first */
552 drv_data->read(drv_data);
554 /* return count of what was actually read */
555 msg->actual_length += drv_data->len -
556 (drv_data->rx_end - drv_data->rx);
558 /* Transfer delays and chip select release are
559 * handled in pump_transfers or giveback
562 /* Move to next transfer */
563 msg->state = next_transfer(drv_data);
565 /* Schedule transfer tasklet */
566 tasklet_schedule(&drv_data->pump_transfers);
569 static void dma_handler(int channel, void *data)
571 struct driver_data *drv_data = data;
572 u32 irq_status = DCSR(channel) & DMA_INT_MASK;
574 if (irq_status & DCSR_BUSERR) {
576 if (channel == drv_data->tx_channel)
577 dma_error_stop(drv_data,
579 "bad bus address on tx channel");
581 dma_error_stop(drv_data,
583 "bad bus address on rx channel");
587 /* PXA255x_SSP has no timeout interrupt, wait for tailing bytes */
588 if ((channel == drv_data->tx_channel)
589 && (irq_status & DCSR_ENDINTR)
590 && (drv_data->ssp_type == PXA25x_SSP)) {
592 /* Wait for rx to stall */
593 if (wait_ssp_rx_stall(drv_data->ioaddr) == 0)
594 dev_err(&drv_data->pdev->dev,
595 "dma_handler: ssp rx stall failed\n");
597 /* finish this transfer, start the next */
598 dma_transfer_complete(drv_data);
602 static irqreturn_t dma_transfer(struct driver_data *drv_data)
605 void __iomem *reg = drv_data->ioaddr;
607 irq_status = read_SSSR(reg) & drv_data->mask_sr;
608 if (irq_status & SSSR_ROR) {
609 dma_error_stop(drv_data, "dma_transfer: fifo overrun");
613 /* Check for false positive timeout */
614 if ((irq_status & SSSR_TINT)
615 && (DCSR(drv_data->tx_channel) & DCSR_RUN)) {
616 write_SSSR(SSSR_TINT, reg);
620 if (irq_status & SSSR_TINT || drv_data->rx == drv_data->rx_end) {
622 /* Clear and disable timeout interrupt, do the rest in
623 * dma_transfer_complete */
624 if (drv_data->ssp_type != PXA25x_SSP)
627 /* finish this transfer, start the next */
628 dma_transfer_complete(drv_data);
633 /* Opps problem detected */
637 static void int_error_stop(struct driver_data *drv_data, const char* msg)
639 void __iomem *reg = drv_data->ioaddr;
641 /* Stop and reset SSP */
642 write_SSSR(drv_data->clear_sr, reg);
643 write_SSCR1(read_SSCR1(reg) & ~drv_data->int_cr1, reg);
644 if (drv_data->ssp_type != PXA25x_SSP)
647 write_SSCR0(read_SSCR0(reg) & ~SSCR0_SSE, reg);
649 dev_err(&drv_data->pdev->dev, "%s\n", msg);
651 drv_data->cur_msg->state = ERROR_STATE;
652 tasklet_schedule(&drv_data->pump_transfers);
655 static void int_transfer_complete(struct driver_data *drv_data)
657 void __iomem *reg = drv_data->ioaddr;
660 write_SSSR(drv_data->clear_sr, reg);
661 write_SSCR1(read_SSCR1(reg) & ~drv_data->int_cr1, reg);
662 if (drv_data->ssp_type != PXA25x_SSP)
665 /* Update total byte transfered return count actual bytes read */
666 drv_data->cur_msg->actual_length += drv_data->len -
667 (drv_data->rx_end - drv_data->rx);
669 /* Transfer delays and chip select release are
670 * handled in pump_transfers or giveback
673 /* Move to next transfer */
674 drv_data->cur_msg->state = next_transfer(drv_data);
676 /* Schedule transfer tasklet */
677 tasklet_schedule(&drv_data->pump_transfers);
680 static irqreturn_t interrupt_transfer(struct driver_data *drv_data)
682 void __iomem *reg = drv_data->ioaddr;
684 u32 irq_mask = (read_SSCR1(reg) & SSCR1_TIE) ?
685 drv_data->mask_sr : drv_data->mask_sr & ~SSSR_TFS;
687 u32 irq_status = read_SSSR(reg) & irq_mask;
689 if (irq_status & SSSR_ROR) {
690 int_error_stop(drv_data, "interrupt_transfer: fifo overrun");
694 if (irq_status & SSSR_TINT) {
695 write_SSSR(SSSR_TINT, reg);
696 if (drv_data->read(drv_data)) {
697 int_transfer_complete(drv_data);
702 /* Drain rx fifo, Fill tx fifo and prevent overruns */
704 if (drv_data->read(drv_data)) {
705 int_transfer_complete(drv_data);
708 } while (drv_data->write(drv_data));
710 if (drv_data->read(drv_data)) {
711 int_transfer_complete(drv_data);
715 if (drv_data->tx == drv_data->tx_end) {
716 write_SSCR1(read_SSCR1(reg) & ~SSCR1_TIE, reg);
717 /* PXA25x_SSP has no timeout, read trailing bytes */
718 if (drv_data->ssp_type == PXA25x_SSP) {
719 if (!wait_ssp_rx_stall(reg))
721 int_error_stop(drv_data, "interrupt_transfer: "
725 if (!drv_data->read(drv_data))
727 int_error_stop(drv_data,
728 "interrupt_transfer: "
729 "trailing byte read failed");
732 int_transfer_complete(drv_data);
736 /* We did something */
740 static irqreturn_t ssp_int(int irq, void *dev_id)
742 struct driver_data *drv_data = dev_id;
743 void __iomem *reg = drv_data->ioaddr;
745 if (!drv_data->cur_msg) {
747 write_SSCR0(read_SSCR0(reg) & ~SSCR0_SSE, reg);
748 write_SSCR1(read_SSCR1(reg) & ~drv_data->int_cr1, reg);
749 if (drv_data->ssp_type != PXA25x_SSP)
751 write_SSSR(drv_data->clear_sr, reg);
753 dev_err(&drv_data->pdev->dev, "bad message state "
754 "in interrupt handler\n");
760 return drv_data->transfer_handler(drv_data);
763 static int set_dma_burst_and_threshold(struct chip_data *chip,
764 struct spi_device *spi,
765 u8 bits_per_word, u32 *burst_code,
768 struct pxa2xx_spi_chip *chip_info =
769 (struct pxa2xx_spi_chip *)spi->controller_data;
776 /* Set the threshold (in registers) to equal the same amount of data
777 * as represented by burst size (in bytes). The computation below
778 * is (burst_size rounded up to nearest 8 byte, word or long word)
779 * divided by (bytes/register); the tx threshold is the inverse of
780 * the rx, so that there will always be enough data in the rx fifo
781 * to satisfy a burst, and there will always be enough space in the
782 * tx fifo to accept a burst (a tx burst will overwrite the fifo if
783 * there is not enough space), there must always remain enough empty
784 * space in the rx fifo for any data loaded to the tx fifo.
785 * Whenever burst_size (in bytes) equals bits/word, the fifo threshold
786 * will be 8, or half the fifo;
787 * The threshold can only be set to 2, 4 or 8, but not 16, because
788 * to burst 16 to the tx fifo, the fifo would have to be empty;
789 * however, the minimum fifo trigger level is 1, and the tx will
790 * request service when the fifo is at this level, with only 15 spaces.
793 /* find bytes/word */
794 if (bits_per_word <= 8)
796 else if (bits_per_word <= 16)
801 /* use struct pxa2xx_spi_chip->dma_burst_size if available */
803 req_burst_size = chip_info->dma_burst_size;
805 switch (chip->dma_burst_size) {
807 /* if the default burst size is not set,
809 chip->dma_burst_size = DCMD_BURST8;
821 if (req_burst_size <= 8) {
822 *burst_code = DCMD_BURST8;
824 } else if (req_burst_size <= 16) {
825 if (bytes_per_word == 1) {
826 /* don't burst more than 1/2 the fifo */
827 *burst_code = DCMD_BURST8;
831 *burst_code = DCMD_BURST16;
835 if (bytes_per_word == 1) {
836 /* don't burst more than 1/2 the fifo */
837 *burst_code = DCMD_BURST8;
840 } else if (bytes_per_word == 2) {
841 /* don't burst more than 1/2 the fifo */
842 *burst_code = DCMD_BURST16;
846 *burst_code = DCMD_BURST32;
851 thresh_words = burst_bytes / bytes_per_word;
853 /* thresh_words will be between 2 and 8 */
854 *threshold = (SSCR1_RxTresh(thresh_words) & SSCR1_RFT)
855 | (SSCR1_TxTresh(16-thresh_words) & SSCR1_TFT);
860 static unsigned int ssp_get_clk_div(struct ssp_device *ssp, int rate)
862 unsigned long ssp_clk = clk_get_rate(ssp->clk);
864 if (ssp->type == PXA25x_SSP)
865 return ((ssp_clk / (2 * rate) - 1) & 0xff) << 8;
867 return ((ssp_clk / rate - 1) & 0xfff) << 8;
870 static void pump_transfers(unsigned long data)
872 struct driver_data *drv_data = (struct driver_data *)data;
873 struct spi_message *message = NULL;
874 struct spi_transfer *transfer = NULL;
875 struct spi_transfer *previous = NULL;
876 struct chip_data *chip = NULL;
877 struct ssp_device *ssp = drv_data->ssp;
878 void __iomem *reg = drv_data->ioaddr;
884 u32 dma_thresh = drv_data->cur_chip->dma_threshold;
885 u32 dma_burst = drv_data->cur_chip->dma_burst_size;
887 /* Get current state information */
888 message = drv_data->cur_msg;
889 transfer = drv_data->cur_transfer;
890 chip = drv_data->cur_chip;
892 /* Handle for abort */
893 if (message->state == ERROR_STATE) {
894 message->status = -EIO;
899 /* Handle end of message */
900 if (message->state == DONE_STATE) {
906 /* Delay if requested at end of transfer before CS change */
907 if (message->state == RUNNING_STATE) {
908 previous = list_entry(transfer->transfer_list.prev,
911 if (previous->delay_usecs)
912 udelay(previous->delay_usecs);
914 /* Drop chip select only if cs_change is requested */
915 if (previous->cs_change)
916 cs_deassert(drv_data);
919 /* Check for transfers that need multiple DMA segments */
920 if (transfer->len > MAX_DMA_LEN && chip->enable_dma) {
922 /* reject already-mapped transfers; PIO won't always work */
923 if (message->is_dma_mapped
924 || transfer->rx_dma || transfer->tx_dma) {
925 dev_err(&drv_data->pdev->dev,
926 "pump_transfers: mapped transfer length "
927 "of %u is greater than %d\n",
928 transfer->len, MAX_DMA_LEN);
929 message->status = -EINVAL;
934 /* warn ... we force this to PIO mode */
935 if (printk_ratelimit())
936 dev_warn(&message->spi->dev, "pump_transfers: "
937 "DMA disabled for transfer length %ld "
939 (long)drv_data->len, MAX_DMA_LEN);
942 /* Setup the transfer state based on the type of transfer */
943 if (flush(drv_data) == 0) {
944 dev_err(&drv_data->pdev->dev, "pump_transfers: flush failed\n");
945 message->status = -EIO;
949 drv_data->n_bytes = chip->n_bytes;
950 drv_data->dma_width = chip->dma_width;
951 drv_data->tx = (void *)transfer->tx_buf;
952 drv_data->tx_end = drv_data->tx + transfer->len;
953 drv_data->rx = transfer->rx_buf;
954 drv_data->rx_end = drv_data->rx + transfer->len;
955 drv_data->rx_dma = transfer->rx_dma;
956 drv_data->tx_dma = transfer->tx_dma;
957 drv_data->len = transfer->len & DCMD_LENGTH;
958 drv_data->write = drv_data->tx ? chip->write : null_writer;
959 drv_data->read = drv_data->rx ? chip->read : null_reader;
961 /* Change speed and bit per word on a per transfer */
963 if (transfer->speed_hz || transfer->bits_per_word) {
965 bits = chip->bits_per_word;
966 speed = chip->speed_hz;
968 if (transfer->speed_hz)
969 speed = transfer->speed_hz;
971 if (transfer->bits_per_word)
972 bits = transfer->bits_per_word;
974 clk_div = ssp_get_clk_div(ssp, speed);
977 drv_data->n_bytes = 1;
978 drv_data->dma_width = DCMD_WIDTH1;
979 drv_data->read = drv_data->read != null_reader ?
980 u8_reader : null_reader;
981 drv_data->write = drv_data->write != null_writer ?
982 u8_writer : null_writer;
983 } else if (bits <= 16) {
984 drv_data->n_bytes = 2;
985 drv_data->dma_width = DCMD_WIDTH2;
986 drv_data->read = drv_data->read != null_reader ?
987 u16_reader : null_reader;
988 drv_data->write = drv_data->write != null_writer ?
989 u16_writer : null_writer;
990 } else if (bits <= 32) {
991 drv_data->n_bytes = 4;
992 drv_data->dma_width = DCMD_WIDTH4;
993 drv_data->read = drv_data->read != null_reader ?
994 u32_reader : null_reader;
995 drv_data->write = drv_data->write != null_writer ?
996 u32_writer : null_writer;
998 /* if bits/word is changed in dma mode, then must check the
999 * thresholds and burst also */
1000 if (chip->enable_dma) {
1001 if (set_dma_burst_and_threshold(chip, message->spi,
1004 if (printk_ratelimit())
1005 dev_warn(&message->spi->dev,
1007 "DMA burst size reduced to "
1008 "match bits_per_word\n");
1013 | SSCR0_DataSize(bits > 16 ? bits - 16 : bits)
1015 | (bits > 16 ? SSCR0_EDSS : 0);
1018 message->state = RUNNING_STATE;
1020 /* Try to map dma buffer and do a dma transfer if successful, but
1021 * only if the length is non-zero and less than MAX_DMA_LEN.
1023 * Zero-length non-descriptor DMA is illegal on PXA2xx; force use
1024 * of PIO instead. Care is needed above because the transfer may
1025 * have have been passed with buffers that are already dma mapped.
1026 * A zero-length transfer in PIO mode will not try to write/read
1027 * to/from the buffers
1029 * REVISIT large transfers are exactly where we most want to be
1030 * using DMA. If this happens much, split those transfers into
1031 * multiple DMA segments rather than forcing PIO.
1033 drv_data->dma_mapped = 0;
1034 if (drv_data->len > 0 && drv_data->len <= MAX_DMA_LEN)
1035 drv_data->dma_mapped = map_dma_buffers(drv_data);
1036 if (drv_data->dma_mapped) {
1038 /* Ensure we have the correct interrupt handler */
1039 drv_data->transfer_handler = dma_transfer;
1041 /* Setup rx DMA Channel */
1042 DCSR(drv_data->rx_channel) = RESET_DMA_CHANNEL;
1043 DSADR(drv_data->rx_channel) = drv_data->ssdr_physical;
1044 DTADR(drv_data->rx_channel) = drv_data->rx_dma;
1045 if (drv_data->rx == drv_data->null_dma_buf)
1046 /* No target address increment */
1047 DCMD(drv_data->rx_channel) = DCMD_FLOWSRC
1048 | drv_data->dma_width
1052 DCMD(drv_data->rx_channel) = DCMD_INCTRGADDR
1054 | drv_data->dma_width
1058 /* Setup tx DMA Channel */
1059 DCSR(drv_data->tx_channel) = RESET_DMA_CHANNEL;
1060 DSADR(drv_data->tx_channel) = drv_data->tx_dma;
1061 DTADR(drv_data->tx_channel) = drv_data->ssdr_physical;
1062 if (drv_data->tx == drv_data->null_dma_buf)
1063 /* No source address increment */
1064 DCMD(drv_data->tx_channel) = DCMD_FLOWTRG
1065 | drv_data->dma_width
1069 DCMD(drv_data->tx_channel) = DCMD_INCSRCADDR
1071 | drv_data->dma_width
1075 /* Enable dma end irqs on SSP to detect end of transfer */
1076 if (drv_data->ssp_type == PXA25x_SSP)
1077 DCMD(drv_data->tx_channel) |= DCMD_ENDIRQEN;
1079 /* Clear status and start DMA engine */
1080 cr1 = chip->cr1 | dma_thresh | drv_data->dma_cr1;
1081 write_SSSR(drv_data->clear_sr, reg);
1082 DCSR(drv_data->rx_channel) |= DCSR_RUN;
1083 DCSR(drv_data->tx_channel) |= DCSR_RUN;
1085 /* Ensure we have the correct interrupt handler */
1086 drv_data->transfer_handler = interrupt_transfer;
1089 cr1 = chip->cr1 | chip->threshold | drv_data->int_cr1;
1090 write_SSSR(drv_data->clear_sr, reg);
1093 /* see if we need to reload the config registers */
1094 if ((read_SSCR0(reg) != cr0)
1095 || (read_SSCR1(reg) & SSCR1_CHANGE_MASK) !=
1096 (cr1 & SSCR1_CHANGE_MASK)) {
1098 /* stop the SSP, and update the other bits */
1099 write_SSCR0(cr0 & ~SSCR0_SSE, reg);
1100 if (drv_data->ssp_type != PXA25x_SSP)
1101 write_SSTO(chip->timeout, reg);
1102 /* first set CR1 without interrupt and service enables */
1103 write_SSCR1(cr1 & SSCR1_CHANGE_MASK, reg);
1104 /* restart the SSP */
1105 write_SSCR0(cr0, reg);
1108 if (drv_data->ssp_type != PXA25x_SSP)
1109 write_SSTO(chip->timeout, reg);
1112 cs_assert(drv_data);
1114 /* after chip select, release the data by enabling service
1115 * requests and interrupts, without changing any mode bits */
1116 write_SSCR1(cr1, reg);
1119 static void pump_messages(struct work_struct *work)
1121 struct driver_data *drv_data =
1122 container_of(work, struct driver_data, pump_messages);
1123 unsigned long flags;
1125 /* Lock queue and check for queue work */
1126 spin_lock_irqsave(&drv_data->lock, flags);
1127 if (list_empty(&drv_data->queue) || drv_data->run == QUEUE_STOPPED) {
1129 spin_unlock_irqrestore(&drv_data->lock, flags);
1133 /* Make sure we are not already running a message */
1134 if (drv_data->cur_msg) {
1135 spin_unlock_irqrestore(&drv_data->lock, flags);
1139 /* Extract head of queue */
1140 drv_data->cur_msg = list_entry(drv_data->queue.next,
1141 struct spi_message, queue);
1142 list_del_init(&drv_data->cur_msg->queue);
1144 /* Initial message state*/
1145 drv_data->cur_msg->state = START_STATE;
1146 drv_data->cur_transfer = list_entry(drv_data->cur_msg->transfers.next,
1147 struct spi_transfer,
1150 /* prepare to setup the SSP, in pump_transfers, using the per
1151 * chip configuration */
1152 drv_data->cur_chip = spi_get_ctldata(drv_data->cur_msg->spi);
1154 /* Mark as busy and launch transfers */
1155 tasklet_schedule(&drv_data->pump_transfers);
1158 spin_unlock_irqrestore(&drv_data->lock, flags);
1161 static int transfer(struct spi_device *spi, struct spi_message *msg)
1163 struct driver_data *drv_data = spi_master_get_devdata(spi->master);
1164 unsigned long flags;
1166 spin_lock_irqsave(&drv_data->lock, flags);
1168 if (drv_data->run == QUEUE_STOPPED) {
1169 spin_unlock_irqrestore(&drv_data->lock, flags);
1173 msg->actual_length = 0;
1174 msg->status = -EINPROGRESS;
1175 msg->state = START_STATE;
1177 list_add_tail(&msg->queue, &drv_data->queue);
1179 if (drv_data->run == QUEUE_RUNNING && !drv_data->busy)
1180 queue_work(drv_data->workqueue, &drv_data->pump_messages);
1182 spin_unlock_irqrestore(&drv_data->lock, flags);
1187 /* the spi->mode bits understood by this driver: */
1188 #define MODEBITS (SPI_CPOL | SPI_CPHA)
1190 static int setup_cs(struct spi_device *spi, struct chip_data *chip,
1191 struct pxa2xx_spi_chip *chip_info)
1195 if (chip == NULL || chip_info == NULL)
1198 /* NOTE: setup() can be called multiple times, possibly with
1199 * different chip_info, release previously requested GPIO
1201 if (gpio_is_valid(chip->gpio_cs))
1202 gpio_free(chip->gpio_cs);
1204 /* If (*cs_control) is provided, ignore GPIO chip select */
1205 if (chip_info->cs_control) {
1206 chip->cs_control = chip_info->cs_control;
1210 if (gpio_is_valid(chip_info->gpio_cs)) {
1211 err = gpio_request(chip_info->gpio_cs, "SPI_CS");
1213 dev_err(&spi->dev, "failed to request chip select "
1214 "GPIO%d\n", chip_info->gpio_cs);
1218 chip->gpio_cs = chip_info->gpio_cs;
1219 chip->gpio_cs_inverted = spi->mode & SPI_CS_HIGH;
1221 err = gpio_direction_output(chip->gpio_cs,
1222 !chip->gpio_cs_inverted);
1228 static int setup(struct spi_device *spi)
1230 struct pxa2xx_spi_chip *chip_info = NULL;
1231 struct chip_data *chip;
1232 struct driver_data *drv_data = spi_master_get_devdata(spi->master);
1233 struct ssp_device *ssp = drv_data->ssp;
1234 unsigned int clk_div;
1235 uint tx_thres = TX_THRESH_DFLT;
1236 uint rx_thres = RX_THRESH_DFLT;
1238 if (!spi->bits_per_word)
1239 spi->bits_per_word = 8;
1241 if (drv_data->ssp_type != PXA25x_SSP
1242 && (spi->bits_per_word < 4 || spi->bits_per_word > 32)) {
1243 dev_err(&spi->dev, "failed setup: ssp_type=%d, bits/wrd=%d "
1244 "b/w not 4-32 for type non-PXA25x_SSP\n",
1245 drv_data->ssp_type, spi->bits_per_word);
1248 else if (drv_data->ssp_type == PXA25x_SSP
1249 && (spi->bits_per_word < 4
1250 || spi->bits_per_word > 16)) {
1251 dev_err(&spi->dev, "failed setup: ssp_type=%d, bits/wrd=%d "
1252 "b/w not 4-16 for type PXA25x_SSP\n",
1253 drv_data->ssp_type, spi->bits_per_word);
1257 if (spi->mode & ~MODEBITS) {
1258 dev_dbg(&spi->dev, "setup: unsupported mode bits %x\n",
1259 spi->mode & ~MODEBITS);
1263 /* Only alloc on first setup */
1264 chip = spi_get_ctldata(spi);
1266 chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL);
1269 "failed setup: can't allocate chip data\n");
1274 chip->enable_dma = 0;
1275 chip->timeout = TIMOUT_DFLT;
1276 chip->dma_burst_size = drv_data->master_info->enable_dma ?
1280 /* protocol drivers may change the chip settings, so...
1281 * if chip_info exists, use it */
1282 chip_info = spi->controller_data;
1284 /* chip_info isn't always needed */
1287 if (chip_info->timeout)
1288 chip->timeout = chip_info->timeout;
1289 if (chip_info->tx_threshold)
1290 tx_thres = chip_info->tx_threshold;
1291 if (chip_info->rx_threshold)
1292 rx_thres = chip_info->rx_threshold;
1293 chip->enable_dma = drv_data->master_info->enable_dma;
1294 chip->dma_threshold = 0;
1295 if (chip_info->enable_loopback)
1296 chip->cr1 = SSCR1_LBM;
1299 chip->threshold = (SSCR1_RxTresh(rx_thres) & SSCR1_RFT) |
1300 (SSCR1_TxTresh(tx_thres) & SSCR1_TFT);
1302 /* set dma burst and threshold outside of chip_info path so that if
1303 * chip_info goes away after setting chip->enable_dma, the
1304 * burst and threshold can still respond to changes in bits_per_word */
1305 if (chip->enable_dma) {
1306 /* set up legal burst and threshold for dma */
1307 if (set_dma_burst_and_threshold(chip, spi, spi->bits_per_word,
1308 &chip->dma_burst_size,
1309 &chip->dma_threshold)) {
1310 dev_warn(&spi->dev, "in setup: DMA burst size reduced "
1311 "to match bits_per_word\n");
1315 clk_div = ssp_get_clk_div(ssp, spi->max_speed_hz);
1316 chip->speed_hz = spi->max_speed_hz;
1320 | SSCR0_DataSize(spi->bits_per_word > 16 ?
1321 spi->bits_per_word - 16 : spi->bits_per_word)
1323 | (spi->bits_per_word > 16 ? SSCR0_EDSS : 0);
1324 chip->cr1 &= ~(SSCR1_SPO | SSCR1_SPH);
1325 chip->cr1 |= (((spi->mode & SPI_CPHA) != 0) ? SSCR1_SPH : 0)
1326 | (((spi->mode & SPI_CPOL) != 0) ? SSCR1_SPO : 0);
1328 /* NOTE: PXA25x_SSP _could_ use external clocking ... */
1329 if (drv_data->ssp_type != PXA25x_SSP)
1330 dev_dbg(&spi->dev, "%d bits/word, %ld Hz, mode %d, %s\n",
1332 clk_get_rate(ssp->clk)
1333 / (1 + ((chip->cr0 & SSCR0_SCR) >> 8)),
1335 chip->enable_dma ? "DMA" : "PIO");
1337 dev_dbg(&spi->dev, "%d bits/word, %ld Hz, mode %d, %s\n",
1339 clk_get_rate(ssp->clk) / 2
1340 / (1 + ((chip->cr0 & SSCR0_SCR) >> 8)),
1342 chip->enable_dma ? "DMA" : "PIO");
1344 if (spi->bits_per_word <= 8) {
1346 chip->dma_width = DCMD_WIDTH1;
1347 chip->read = u8_reader;
1348 chip->write = u8_writer;
1349 } else if (spi->bits_per_word <= 16) {
1351 chip->dma_width = DCMD_WIDTH2;
1352 chip->read = u16_reader;
1353 chip->write = u16_writer;
1354 } else if (spi->bits_per_word <= 32) {
1355 chip->cr0 |= SSCR0_EDSS;
1357 chip->dma_width = DCMD_WIDTH4;
1358 chip->read = u32_reader;
1359 chip->write = u32_writer;
1361 dev_err(&spi->dev, "invalid wordsize\n");
1364 chip->bits_per_word = spi->bits_per_word;
1366 spi_set_ctldata(spi, chip);
1368 return setup_cs(spi, chip, chip_info);
1371 static void cleanup(struct spi_device *spi)
1373 struct chip_data *chip = spi_get_ctldata(spi);
1375 if (gpio_is_valid(chip->gpio_cs))
1376 gpio_free(chip->gpio_cs);
1381 static int __init init_queue(struct driver_data *drv_data)
1383 INIT_LIST_HEAD(&drv_data->queue);
1384 spin_lock_init(&drv_data->lock);
1386 drv_data->run = QUEUE_STOPPED;
1389 tasklet_init(&drv_data->pump_transfers,
1390 pump_transfers, (unsigned long)drv_data);
1392 INIT_WORK(&drv_data->pump_messages, pump_messages);
1393 drv_data->workqueue = create_singlethread_workqueue(
1394 dev_name(drv_data->master->dev.parent));
1395 if (drv_data->workqueue == NULL)
1401 static int start_queue(struct driver_data *drv_data)
1403 unsigned long flags;
1405 spin_lock_irqsave(&drv_data->lock, flags);
1407 if (drv_data->run == QUEUE_RUNNING || drv_data->busy) {
1408 spin_unlock_irqrestore(&drv_data->lock, flags);
1412 drv_data->run = QUEUE_RUNNING;
1413 drv_data->cur_msg = NULL;
1414 drv_data->cur_transfer = NULL;
1415 drv_data->cur_chip = NULL;
1416 spin_unlock_irqrestore(&drv_data->lock, flags);
1418 queue_work(drv_data->workqueue, &drv_data->pump_messages);
1423 static int stop_queue(struct driver_data *drv_data)
1425 unsigned long flags;
1426 unsigned limit = 500;
1429 spin_lock_irqsave(&drv_data->lock, flags);
1431 /* This is a bit lame, but is optimized for the common execution path.
1432 * A wait_queue on the drv_data->busy could be used, but then the common
1433 * execution path (pump_messages) would be required to call wake_up or
1434 * friends on every SPI message. Do this instead */
1435 drv_data->run = QUEUE_STOPPED;
1436 while (!list_empty(&drv_data->queue) && drv_data->busy && limit--) {
1437 spin_unlock_irqrestore(&drv_data->lock, flags);
1439 spin_lock_irqsave(&drv_data->lock, flags);
1442 if (!list_empty(&drv_data->queue) || drv_data->busy)
1445 spin_unlock_irqrestore(&drv_data->lock, flags);
1450 static int destroy_queue(struct driver_data *drv_data)
1454 status = stop_queue(drv_data);
1455 /* we are unloading the module or failing to load (only two calls
1456 * to this routine), and neither call can handle a return value.
1457 * However, destroy_workqueue calls flush_workqueue, and that will
1458 * block until all work is done. If the reason that stop_queue
1459 * timed out is that the work will never finish, then it does no
1460 * good to call destroy_workqueue, so return anyway. */
1464 destroy_workqueue(drv_data->workqueue);
1469 static int __init pxa2xx_spi_probe(struct platform_device *pdev)
1471 struct device *dev = &pdev->dev;
1472 struct pxa2xx_spi_master *platform_info;
1473 struct spi_master *master;
1474 struct driver_data *drv_data;
1475 struct ssp_device *ssp;
1478 platform_info = dev->platform_data;
1480 ssp = ssp_request(pdev->id, pdev->name);
1482 dev_err(&pdev->dev, "failed to request SSP%d\n", pdev->id);
1486 /* Allocate master with space for drv_data and null dma buffer */
1487 master = spi_alloc_master(dev, sizeof(struct driver_data) + 16);
1489 dev_err(&pdev->dev, "cannot alloc spi_master\n");
1493 drv_data = spi_master_get_devdata(master);
1494 drv_data->master = master;
1495 drv_data->master_info = platform_info;
1496 drv_data->pdev = pdev;
1497 drv_data->ssp = ssp;
1499 master->bus_num = pdev->id;
1500 master->num_chipselect = platform_info->num_chipselect;
1501 master->cleanup = cleanup;
1502 master->setup = setup;
1503 master->transfer = transfer;
1505 drv_data->ssp_type = ssp->type;
1506 drv_data->null_dma_buf = (u32 *)ALIGN((u32)(drv_data +
1507 sizeof(struct driver_data)), 8);
1509 drv_data->ioaddr = ssp->mmio_base;
1510 drv_data->ssdr_physical = ssp->phys_base + SSDR;
1511 if (ssp->type == PXA25x_SSP) {
1512 drv_data->int_cr1 = SSCR1_TIE | SSCR1_RIE;
1513 drv_data->dma_cr1 = 0;
1514 drv_data->clear_sr = SSSR_ROR;
1515 drv_data->mask_sr = SSSR_RFS | SSSR_TFS | SSSR_ROR;
1517 drv_data->int_cr1 = SSCR1_TIE | SSCR1_RIE | SSCR1_TINTE;
1518 drv_data->dma_cr1 = SSCR1_TSRE | SSCR1_RSRE | SSCR1_TINTE;
1519 drv_data->clear_sr = SSSR_ROR | SSSR_TINT;
1520 drv_data->mask_sr = SSSR_TINT | SSSR_RFS | SSSR_TFS | SSSR_ROR;
1523 status = request_irq(ssp->irq, ssp_int, 0, dev_name(dev), drv_data);
1525 dev_err(&pdev->dev, "cannot get IRQ %d\n", ssp->irq);
1526 goto out_error_master_alloc;
1529 /* Setup DMA if requested */
1530 drv_data->tx_channel = -1;
1531 drv_data->rx_channel = -1;
1532 if (platform_info->enable_dma) {
1534 /* Get two DMA channels (rx and tx) */
1535 drv_data->rx_channel = pxa_request_dma("pxa2xx_spi_ssp_rx",
1539 if (drv_data->rx_channel < 0) {
1540 dev_err(dev, "problem (%d) requesting rx channel\n",
1541 drv_data->rx_channel);
1543 goto out_error_irq_alloc;
1545 drv_data->tx_channel = pxa_request_dma("pxa2xx_spi_ssp_tx",
1549 if (drv_data->tx_channel < 0) {
1550 dev_err(dev, "problem (%d) requesting tx channel\n",
1551 drv_data->tx_channel);
1553 goto out_error_dma_alloc;
1556 DRCMR(ssp->drcmr_rx) = DRCMR_MAPVLD | drv_data->rx_channel;
1557 DRCMR(ssp->drcmr_tx) = DRCMR_MAPVLD | drv_data->tx_channel;
1560 /* Enable SOC clock */
1561 clk_enable(ssp->clk);
1563 /* Load default SSP configuration */
1564 write_SSCR0(0, drv_data->ioaddr);
1565 write_SSCR1(SSCR1_RxTresh(RX_THRESH_DFLT) |
1566 SSCR1_TxTresh(TX_THRESH_DFLT),
1568 write_SSCR0(SSCR0_SerClkDiv(2)
1570 | SSCR0_DataSize(8),
1572 if (drv_data->ssp_type != PXA25x_SSP)
1573 write_SSTO(0, drv_data->ioaddr);
1574 write_SSPSP(0, drv_data->ioaddr);
1576 /* Initial and start queue */
1577 status = init_queue(drv_data);
1579 dev_err(&pdev->dev, "problem initializing queue\n");
1580 goto out_error_clock_enabled;
1582 status = start_queue(drv_data);
1584 dev_err(&pdev->dev, "problem starting queue\n");
1585 goto out_error_clock_enabled;
1588 /* Register with the SPI framework */
1589 platform_set_drvdata(pdev, drv_data);
1590 status = spi_register_master(master);
1592 dev_err(&pdev->dev, "problem registering spi master\n");
1593 goto out_error_queue_alloc;
1598 out_error_queue_alloc:
1599 destroy_queue(drv_data);
1601 out_error_clock_enabled:
1602 clk_disable(ssp->clk);
1604 out_error_dma_alloc:
1605 if (drv_data->tx_channel != -1)
1606 pxa_free_dma(drv_data->tx_channel);
1607 if (drv_data->rx_channel != -1)
1608 pxa_free_dma(drv_data->rx_channel);
1610 out_error_irq_alloc:
1611 free_irq(ssp->irq, drv_data);
1613 out_error_master_alloc:
1614 spi_master_put(master);
1619 static int pxa2xx_spi_remove(struct platform_device *pdev)
1621 struct driver_data *drv_data = platform_get_drvdata(pdev);
1622 struct ssp_device *ssp;
1627 ssp = drv_data->ssp;
1629 /* Remove the queue */
1630 status = destroy_queue(drv_data);
1632 /* the kernel does not check the return status of this
1633 * this routine (mod->exit, within the kernel). Therefore
1634 * nothing is gained by returning from here, the module is
1635 * going away regardless, and we should not leave any more
1636 * resources allocated than necessary. We cannot free the
1637 * message memory in drv_data->queue, but we can release the
1638 * resources below. I think the kernel should honor -EBUSY
1640 dev_err(&pdev->dev, "pxa2xx_spi_remove: workqueue will not "
1641 "complete, message memory not freed\n");
1643 /* Disable the SSP at the peripheral and SOC level */
1644 write_SSCR0(0, drv_data->ioaddr);
1645 clk_disable(ssp->clk);
1648 if (drv_data->master_info->enable_dma) {
1649 DRCMR(ssp->drcmr_rx) = 0;
1650 DRCMR(ssp->drcmr_tx) = 0;
1651 pxa_free_dma(drv_data->tx_channel);
1652 pxa_free_dma(drv_data->rx_channel);
1656 free_irq(ssp->irq, drv_data);
1661 /* Disconnect from the SPI framework */
1662 spi_unregister_master(drv_data->master);
1664 /* Prevent double remove */
1665 platform_set_drvdata(pdev, NULL);
1670 static void pxa2xx_spi_shutdown(struct platform_device *pdev)
1674 if ((status = pxa2xx_spi_remove(pdev)) != 0)
1675 dev_err(&pdev->dev, "shutdown failed with %d\n", status);
1680 static int pxa2xx_spi_suspend(struct platform_device *pdev, pm_message_t state)
1682 struct driver_data *drv_data = platform_get_drvdata(pdev);
1683 struct ssp_device *ssp = drv_data->ssp;
1686 status = stop_queue(drv_data);
1689 write_SSCR0(0, drv_data->ioaddr);
1690 clk_disable(ssp->clk);
1695 static int pxa2xx_spi_resume(struct platform_device *pdev)
1697 struct driver_data *drv_data = platform_get_drvdata(pdev);
1698 struct ssp_device *ssp = drv_data->ssp;
1701 /* Enable the SSP clock */
1702 clk_enable(ssp->clk);
1704 /* Start the queue running */
1705 status = start_queue(drv_data);
1707 dev_err(&pdev->dev, "problem starting queue (%d)\n", status);
1714 #define pxa2xx_spi_suspend NULL
1715 #define pxa2xx_spi_resume NULL
1716 #endif /* CONFIG_PM */
1718 static struct platform_driver driver = {
1720 .name = "pxa2xx-spi",
1721 .owner = THIS_MODULE,
1723 .remove = pxa2xx_spi_remove,
1724 .shutdown = pxa2xx_spi_shutdown,
1725 .suspend = pxa2xx_spi_suspend,
1726 .resume = pxa2xx_spi_resume,
1729 static int __init pxa2xx_spi_init(void)
1731 return platform_driver_probe(&driver, pxa2xx_spi_probe);
1733 module_init(pxa2xx_spi_init);
1735 static void __exit pxa2xx_spi_exit(void)
1737 platform_driver_unregister(&driver);
1739 module_exit(pxa2xx_spi_exit);