2 * File: drivers/spi/bfin5xx_spi.c
4 * Bryan Wu <bryan.wu@analog.com>
6 * Luke Yang (Analog Devices Inc.)
8 * Created: March. 10th 2006
9 * Description: SPI controller driver for Blackfin BF5xx
10 * Bugs: Enter bugs at http://blackfin.uclinux.org/
13 * March 10, 2006 bfin5xx_spi.c Created. (Luke Yang)
14 * August 7, 2006 added full duplex mode (Axel Weiss & Luke Yang)
15 * July 17, 2007 add support for BF54x SPI0 controller (Bryan Wu)
16 * July 30, 2007 add platfrom_resource interface to support multi-port
17 * SPI controller (Bryan Wu)
19 * Copyright 2004-2007 Analog Devices Inc.
21 * This program is free software ; you can redistribute it and/or modify
22 * it under the terms of the GNU General Public License as published by
23 * the Free Software Foundation ; either version 2, or (at your option)
26 * This program is distributed in the hope that it will be useful,
27 * but WITHOUT ANY WARRANTY ; without even the implied warranty of
28 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
29 * GNU General Public License for more details.
31 * You should have received a copy of the GNU General Public License
32 * along with this program ; see the file COPYING.
33 * If not, write to the Free Software Foundation,
34 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
37 #include <linux/init.h>
38 #include <linux/module.h>
39 #include <linux/delay.h>
40 #include <linux/device.h>
42 #include <linux/ioport.h>
43 #include <linux/irq.h>
44 #include <linux/errno.h>
45 #include <linux/interrupt.h>
46 #include <linux/platform_device.h>
47 #include <linux/dma-mapping.h>
48 #include <linux/spi/spi.h>
49 #include <linux/workqueue.h>
52 #include <asm/portmux.h>
53 #include <asm/bfin5xx_spi.h>
55 #define DRV_NAME "bfin-spi"
56 #define DRV_AUTHOR "Bryan Wu, Luke Yang"
57 #define DRV_DESC "Blackfin BF5xx on-chip SPI Contoller Driver"
58 #define DRV_VERSION "1.0"
60 MODULE_AUTHOR(DRV_AUTHOR);
61 MODULE_DESCRIPTION(DRV_DESC);
62 MODULE_LICENSE("GPL");
64 #define IS_DMA_ALIGNED(x) (((u32)(x)&0x07)==0)
66 static u32 spi_dma_ch;
67 static u32 spi_regs_base;
69 #define DEFINE_SPI_REG(reg, off) \
70 static inline u16 read_##reg(void) \
71 { return bfin_read16(spi_regs_base + off); } \
72 static inline void write_##reg(u16 v) \
73 {bfin_write16(spi_regs_base + off, v); }
75 DEFINE_SPI_REG(CTRL, 0x00)
76 DEFINE_SPI_REG(FLAG, 0x04)
77 DEFINE_SPI_REG(STAT, 0x08)
78 DEFINE_SPI_REG(TDBR, 0x0C)
79 DEFINE_SPI_REG(RDBR, 0x10)
80 DEFINE_SPI_REG(BAUD, 0x14)
81 DEFINE_SPI_REG(SHAW, 0x18)
82 #define START_STATE ((void*)0)
83 #define RUNNING_STATE ((void*)1)
84 #define DONE_STATE ((void*)2)
85 #define ERROR_STATE ((void*)-1)
86 #define QUEUE_RUNNING 0
87 #define QUEUE_STOPPED 1
91 /* Driver model hookup */
92 struct platform_device *pdev;
94 /* SPI framework hookup */
95 struct spi_master *master;
98 struct bfin5xx_spi_master *master_info;
100 /* Driver message queue */
101 struct workqueue_struct *workqueue;
102 struct work_struct pump_messages;
104 struct list_head queue;
108 /* Message Transfer pump */
109 struct tasklet_struct pump_transfers;
111 /* Current message transfer state info */
112 struct spi_message *cur_msg;
113 struct spi_transfer *cur_transfer;
114 struct chip_data *cur_chip;
128 void (*write) (struct driver_data *);
129 void (*read) (struct driver_data *);
130 void (*duplex) (struct driver_data *);
140 u8 width; /* 0 or 1 */
142 u8 bits_per_word; /* 8 or 16 */
143 u8 cs_change_per_word;
145 void (*write) (struct driver_data *);
146 void (*read) (struct driver_data *);
147 void (*duplex) (struct driver_data *);
150 static void bfin_spi_enable(struct driver_data *drv_data)
155 write_CTRL(cr | BIT_CTL_ENABLE);
158 static void bfin_spi_disable(struct driver_data *drv_data)
163 write_CTRL(cr & (~BIT_CTL_ENABLE));
166 /* Caculate the SPI_BAUD register value based on input HZ */
167 static u16 hz_to_spi_baud(u32 speed_hz)
169 u_long sclk = get_sclk();
170 u16 spi_baud = (sclk / (2 * speed_hz));
172 if ((sclk % (2 * speed_hz)) > 0)
178 static int flush(struct driver_data *drv_data)
180 unsigned long limit = loops_per_jiffy << 1;
182 /* wait for stop and clear stat */
183 while (!(read_STAT() & BIT_STAT_SPIF) && limit--)
186 write_STAT(BIT_STAT_CLR);
191 /* Chip select operation functions for cs_change flag */
192 static void cs_active(struct chip_data *chip)
194 u16 flag = read_FLAG();
197 flag &= ~(chip->flag << 8);
202 static void cs_deactive(struct chip_data *chip)
204 u16 flag = read_FLAG();
206 flag |= (chip->flag << 8);
211 #define MAX_SPI_SSEL 7
213 /* stop controller and re-config current chip*/
214 static int restore_state(struct driver_data *drv_data)
216 struct chip_data *chip = drv_data->cur_chip;
219 /* Clear status and disable clock */
220 write_STAT(BIT_STAT_CLR);
221 bfin_spi_disable(drv_data);
222 dev_dbg(&drv_data->pdev->dev, "restoring spi ctl state\n");
224 /* Load the registers */
226 write_BAUD(chip->baud);
227 chip->ctl_reg &= (~BIT_CTL_TIMOD);
228 chip->ctl_reg |= (chip->width << 8);
229 write_CTRL(chip->ctl_reg);
231 bfin_spi_enable(drv_data);
234 dev_dbg(&drv_data->pdev->dev,
235 ": request chip select number %d failed\n",
236 chip->chip_select_num);
241 /* used to kick off transfer in rx mode */
242 static unsigned short dummy_read(void)
249 static void null_writer(struct driver_data *drv_data)
251 u8 n_bytes = drv_data->n_bytes;
253 while (drv_data->tx < drv_data->tx_end) {
255 while ((read_STAT() & BIT_STAT_TXS))
257 drv_data->tx += n_bytes;
261 static void null_reader(struct driver_data *drv_data)
263 u8 n_bytes = drv_data->n_bytes;
266 while (drv_data->rx < drv_data->rx_end) {
267 while (!(read_STAT() & BIT_STAT_RXS))
270 drv_data->rx += n_bytes;
274 static void u8_writer(struct driver_data *drv_data)
276 dev_dbg(&drv_data->pdev->dev,
277 "cr8-s is 0x%x\n", read_STAT());
279 while (drv_data->tx < drv_data->tx_end) {
280 write_TDBR(*(u8 *) (drv_data->tx));
281 while (read_STAT() & BIT_STAT_TXS)
286 /* poll for SPI completion before returning */
287 while (!(read_STAT() & BIT_STAT_SPIF))
291 static void u8_cs_chg_writer(struct driver_data *drv_data)
293 struct chip_data *chip = drv_data->cur_chip;
295 while (drv_data->tx < drv_data->tx_end) {
298 write_TDBR(*(u8 *) (drv_data->tx));
299 while (read_STAT() & BIT_STAT_TXS)
303 if (chip->cs_chg_udelay)
304 udelay(chip->cs_chg_udelay);
308 /* poll for SPI completion before returning */
309 while (!(read_STAT() & BIT_STAT_SPIF))
313 static void u8_reader(struct driver_data *drv_data)
315 dev_dbg(&drv_data->pdev->dev,
316 "cr-8 is 0x%x\n", read_STAT());
318 /* clear TDBR buffer before read(else it will be shifted out) */
323 while (drv_data->rx < drv_data->rx_end - 1) {
324 while (!(read_STAT() & BIT_STAT_RXS))
326 *(u8 *) (drv_data->rx) = read_RDBR();
330 while (!(read_STAT() & BIT_STAT_RXS))
332 *(u8 *) (drv_data->rx) = read_SHAW();
336 static void u8_cs_chg_reader(struct driver_data *drv_data)
338 struct chip_data *chip = drv_data->cur_chip;
340 /* clear TDBR buffer before read(else it will be shifted out) */
346 while (drv_data->rx < drv_data->rx_end - 1) {
349 if (chip->cs_chg_udelay)
350 udelay(chip->cs_chg_udelay);
352 while (!(read_STAT() & BIT_STAT_RXS))
355 *(u8 *) (drv_data->rx) = read_RDBR();
360 while (!(read_STAT() & BIT_STAT_RXS))
362 *(u8 *) (drv_data->rx) = read_SHAW();
366 static void u8_duplex(struct driver_data *drv_data)
368 /* in duplex mode, clk is triggered by writing of TDBR */
369 while (drv_data->rx < drv_data->rx_end) {
370 write_TDBR(*(u8 *) (drv_data->tx));
371 while (read_STAT() & BIT_STAT_TXS)
373 while (!(read_STAT() & BIT_STAT_RXS))
375 *(u8 *) (drv_data->rx) = read_RDBR();
380 /* poll for SPI completion before returning */
381 while (!(read_STAT() & BIT_STAT_SPIF))
385 static void u8_cs_chg_duplex(struct driver_data *drv_data)
387 struct chip_data *chip = drv_data->cur_chip;
389 while (drv_data->rx < drv_data->rx_end) {
392 write_TDBR(*(u8 *) (drv_data->tx));
393 while (read_STAT() & BIT_STAT_TXS)
395 while (!(read_STAT() & BIT_STAT_RXS))
397 *(u8 *) (drv_data->rx) = read_RDBR();
400 if (chip->cs_chg_udelay)
401 udelay(chip->cs_chg_udelay);
406 /* poll for SPI completion before returning */
407 while (!(read_STAT() & BIT_STAT_SPIF))
411 static void u16_writer(struct driver_data *drv_data)
413 dev_dbg(&drv_data->pdev->dev,
414 "cr16 is 0x%x\n", read_STAT());
416 while (drv_data->tx < drv_data->tx_end) {
417 write_TDBR(*(u16 *) (drv_data->tx));
418 while ((read_STAT() & BIT_STAT_TXS))
423 /* poll for SPI completion before returning */
424 while (!(read_STAT() & BIT_STAT_SPIF))
428 static void u16_cs_chg_writer(struct driver_data *drv_data)
430 struct chip_data *chip = drv_data->cur_chip;
432 while (drv_data->tx < drv_data->tx_end) {
435 write_TDBR(*(u16 *) (drv_data->tx));
436 while ((read_STAT() & BIT_STAT_TXS))
440 if (chip->cs_chg_udelay)
441 udelay(chip->cs_chg_udelay);
445 /* poll for SPI completion before returning */
446 while (!(read_STAT() & BIT_STAT_SPIF))
450 static void u16_reader(struct driver_data *drv_data)
452 dev_dbg(&drv_data->pdev->dev,
453 "cr-16 is 0x%x\n", read_STAT());
455 /* clear TDBR buffer before read(else it will be shifted out) */
460 while (drv_data->rx < (drv_data->rx_end - 2)) {
461 while (!(read_STAT() & BIT_STAT_RXS))
463 *(u16 *) (drv_data->rx) = read_RDBR();
467 while (!(read_STAT() & BIT_STAT_RXS))
469 *(u16 *) (drv_data->rx) = read_SHAW();
473 static void u16_cs_chg_reader(struct driver_data *drv_data)
475 struct chip_data *chip = drv_data->cur_chip;
477 /* clear TDBR buffer before read(else it will be shifted out) */
483 while (drv_data->rx < drv_data->rx_end) {
486 if (chip->cs_chg_udelay)
487 udelay(chip->cs_chg_udelay);
489 while (!(read_STAT() & BIT_STAT_RXS))
492 *(u16 *) (drv_data->rx) = read_RDBR();
497 while (!(read_STAT() & BIT_STAT_RXS))
499 *(u16 *) (drv_data->rx) = read_SHAW();
503 static void u16_duplex(struct driver_data *drv_data)
505 /* in duplex mode, clk is triggered by writing of TDBR */
506 while (drv_data->tx < drv_data->tx_end) {
507 write_TDBR(*(u16 *) (drv_data->tx));
508 while (read_STAT() & BIT_STAT_TXS)
510 while (!(read_STAT() & BIT_STAT_RXS))
512 *(u16 *) (drv_data->rx) = read_RDBR();
517 /* poll for SPI completion before returning */
518 while (!(read_STAT() & BIT_STAT_SPIF))
522 static void u16_cs_chg_duplex(struct driver_data *drv_data)
524 struct chip_data *chip = drv_data->cur_chip;
526 while (drv_data->tx < drv_data->tx_end) {
529 write_TDBR(*(u16 *) (drv_data->tx));
530 while (read_STAT() & BIT_STAT_TXS)
532 while (!(read_STAT() & BIT_STAT_RXS))
534 *(u16 *) (drv_data->rx) = read_RDBR();
537 if (chip->cs_chg_udelay)
538 udelay(chip->cs_chg_udelay);
543 /* poll for SPI completion before returning */
544 while (!(read_STAT() & BIT_STAT_SPIF))
548 /* test if ther is more transfer to be done */
549 static void *next_transfer(struct driver_data *drv_data)
551 struct spi_message *msg = drv_data->cur_msg;
552 struct spi_transfer *trans = drv_data->cur_transfer;
554 /* Move to next transfer */
555 if (trans->transfer_list.next != &msg->transfers) {
556 drv_data->cur_transfer =
557 list_entry(trans->transfer_list.next,
558 struct spi_transfer, transfer_list);
559 return RUNNING_STATE;
565 * caller already set message->status;
566 * dma and pio irqs are blocked give finished message back
568 static void giveback(struct driver_data *drv_data)
570 struct chip_data *chip = drv_data->cur_chip;
571 struct spi_transfer *last_transfer;
573 struct spi_message *msg;
575 spin_lock_irqsave(&drv_data->lock, flags);
576 msg = drv_data->cur_msg;
577 drv_data->cur_msg = NULL;
578 drv_data->cur_transfer = NULL;
579 drv_data->cur_chip = NULL;
580 queue_work(drv_data->workqueue, &drv_data->pump_messages);
581 spin_unlock_irqrestore(&drv_data->lock, flags);
583 last_transfer = list_entry(msg->transfers.prev,
584 struct spi_transfer, transfer_list);
588 /* disable chip select signal. And not stop spi in autobuffer mode */
589 if (drv_data->tx_dma != 0xFFFF) {
591 bfin_spi_disable(drv_data);
594 if (!drv_data->cs_change)
598 msg->complete(msg->context);
601 static irqreturn_t dma_irq_handler(int irq, void *dev_id)
603 struct driver_data *drv_data = (struct driver_data *)dev_id;
604 struct spi_message *msg = drv_data->cur_msg;
605 struct chip_data *chip = drv_data->cur_chip;
607 dev_dbg(&drv_data->pdev->dev, "in dma_irq_handler\n");
608 clear_dma_irqstat(spi_dma_ch);
610 /* Wait for DMA to complete */
611 while (get_dma_curr_irqstat(spi_dma_ch) & DMA_RUN)
615 * wait for the last transaction shifted out. HRM states:
616 * at this point there may still be data in the SPI DMA FIFO waiting
617 * to be transmitted ... software needs to poll TXS in the SPI_STAT
618 * register until it goes low for 2 successive reads
620 if (drv_data->tx != NULL) {
621 while ((read_STAT() & TXS) ||
626 while (!(read_STAT() & SPIF))
629 msg->actual_length += drv_data->len_in_bytes;
631 if (drv_data->cs_change)
634 /* Move to next transfer */
635 msg->state = next_transfer(drv_data);
637 /* Schedule transfer tasklet */
638 tasklet_schedule(&drv_data->pump_transfers);
640 /* free the irq handler before next transfer */
641 dev_dbg(&drv_data->pdev->dev,
642 "disable dma channel irq%d\n",
644 dma_disable_irq(spi_dma_ch);
649 static void pump_transfers(unsigned long data)
651 struct driver_data *drv_data = (struct driver_data *)data;
652 struct spi_message *message = NULL;
653 struct spi_transfer *transfer = NULL;
654 struct spi_transfer *previous = NULL;
655 struct chip_data *chip = NULL;
657 u16 cr, dma_width, dma_config;
658 u32 tranf_success = 1;
660 /* Get current state information */
661 message = drv_data->cur_msg;
662 transfer = drv_data->cur_transfer;
663 chip = drv_data->cur_chip;
665 * if msg is error or done, report it back using complete() callback
668 /* Handle for abort */
669 if (message->state == ERROR_STATE) {
670 message->status = -EIO;
675 /* Handle end of message */
676 if (message->state == DONE_STATE) {
682 /* Delay if requested at end of transfer */
683 if (message->state == RUNNING_STATE) {
684 previous = list_entry(transfer->transfer_list.prev,
685 struct spi_transfer, transfer_list);
686 if (previous->delay_usecs)
687 udelay(previous->delay_usecs);
690 /* Setup the transfer state based on the type of transfer */
691 if (flush(drv_data) == 0) {
692 dev_err(&drv_data->pdev->dev, "pump_transfers: flush failed\n");
693 message->status = -EIO;
698 if (transfer->tx_buf != NULL) {
699 drv_data->tx = (void *)transfer->tx_buf;
700 drv_data->tx_end = drv_data->tx + transfer->len;
701 dev_dbg(&drv_data->pdev->dev, "tx_buf is %p, tx_end is %p\n",
702 transfer->tx_buf, drv_data->tx_end);
707 if (transfer->rx_buf != NULL) {
708 drv_data->rx = transfer->rx_buf;
709 drv_data->rx_end = drv_data->rx + transfer->len;
710 dev_dbg(&drv_data->pdev->dev, "rx_buf is %p, rx_end is %p\n",
711 transfer->rx_buf, drv_data->rx_end);
716 drv_data->rx_dma = transfer->rx_dma;
717 drv_data->tx_dma = transfer->tx_dma;
718 drv_data->len_in_bytes = transfer->len;
719 drv_data->cs_change = transfer->cs_change;
722 if (width == CFG_SPI_WORDSIZE16) {
723 drv_data->len = (transfer->len) >> 1;
725 drv_data->len = transfer->len;
727 drv_data->write = drv_data->tx ? chip->write : null_writer;
728 drv_data->read = drv_data->rx ? chip->read : null_reader;
729 drv_data->duplex = chip->duplex ? chip->duplex : null_writer;
730 dev_dbg(&drv_data->pdev->dev, "transfer: ",
731 "drv_data->write is %p, chip->write is %p, null_wr is %p\n",
732 drv_data->write, chip->write, null_writer);
734 /* speed and width has been set on per message */
735 message->state = RUNNING_STATE;
738 write_STAT(BIT_STAT_CLR);
739 cr = (read_CTRL() & (~BIT_CTL_TIMOD));
742 dev_dbg(&drv_data->pdev->dev,
743 "now pumping a transfer: width is %d, len is %d\n",
744 width, transfer->len);
747 * Try to map dma buffer and do a dma transfer if
748 * successful use different way to r/w according to
749 * drv_data->cur_chip->enable_dma
751 if (drv_data->cur_chip->enable_dma && drv_data->len > 6) {
753 disable_dma(spi_dma_ch);
754 clear_dma_irqstat(spi_dma_ch);
756 /* config dma channel */
757 dev_dbg(&drv_data->pdev->dev, "doing dma transfer\n");
758 if (width == CFG_SPI_WORDSIZE16) {
759 set_dma_x_count(spi_dma_ch, drv_data->len);
760 set_dma_x_modify(spi_dma_ch, 2);
761 dma_width = WDSIZE_16;
763 set_dma_x_count(spi_dma_ch, drv_data->len);
764 set_dma_x_modify(spi_dma_ch, 1);
765 dma_width = WDSIZE_8;
768 /* dirty hack for autobuffer DMA mode */
769 if (drv_data->tx_dma == 0xFFFF) {
770 dev_dbg(&drv_data->pdev->dev,
771 "doing autobuffer DMA out.\n");
773 /* set SPI transfer mode */
774 write_CTRL(cr | CFG_SPI_DMAWRITE);
776 /* no irq in autobuffer mode */
778 (DMAFLOW_AUTO | RESTART | dma_width | DI_EN);
779 set_dma_config(spi_dma_ch, dma_config);
780 set_dma_start_addr(spi_dma_ch,
781 (unsigned long)drv_data->tx);
782 enable_dma(spi_dma_ch);
784 /* just return here, there can only be one transfer in this mode */
790 /* In dma mode, rx or tx must be NULL in one transfer */
791 if (drv_data->rx != NULL) {
792 /* set transfer mode, and enable SPI */
793 dev_dbg(&drv_data->pdev->dev, "doing DMA in.\n");
795 /* set SPI transfer mode */
796 write_CTRL(cr | CFG_SPI_DMAREAD);
798 /* clear tx reg soformer data is not shifted out */
801 set_dma_x_count(spi_dma_ch, drv_data->len);
804 dma_enable_irq(spi_dma_ch);
805 dma_config = (WNR | RESTART | dma_width | DI_EN);
806 set_dma_config(spi_dma_ch, dma_config);
807 set_dma_start_addr(spi_dma_ch,
808 (unsigned long)drv_data->rx);
809 enable_dma(spi_dma_ch);
811 } else if (drv_data->tx != NULL) {
812 dev_dbg(&drv_data->pdev->dev, "doing DMA out.\n");
814 /* set SPI transfer mode */
815 write_CTRL(cr | CFG_SPI_DMAWRITE);
818 dma_enable_irq(spi_dma_ch);
819 dma_config = (RESTART | dma_width | DI_EN);
820 set_dma_config(spi_dma_ch, dma_config);
821 set_dma_start_addr(spi_dma_ch,
822 (unsigned long)drv_data->tx);
823 enable_dma(spi_dma_ch);
826 /* IO mode write then read */
827 dev_dbg(&drv_data->pdev->dev, "doing IO transfer\n");
829 if (drv_data->tx != NULL && drv_data->rx != NULL) {
830 /* full duplex mode */
831 BUG_ON((drv_data->tx_end - drv_data->tx) !=
832 (drv_data->rx_end - drv_data->rx));
833 dev_dbg(&drv_data->pdev->dev,
834 "IO duplex: cr is 0x%x\n", cr);
836 /* set SPI transfer mode */
837 write_CTRL(cr | CFG_SPI_WRITE);
839 drv_data->duplex(drv_data);
841 if (drv_data->tx != drv_data->tx_end)
843 } else if (drv_data->tx != NULL) {
844 /* write only half duplex */
845 dev_dbg(&drv_data->pdev->dev,
846 "IO write: cr is 0x%x\n", cr);
848 /* set SPI transfer mode */
849 write_CTRL(cr | CFG_SPI_WRITE);
851 drv_data->write(drv_data);
853 if (drv_data->tx != drv_data->tx_end)
855 } else if (drv_data->rx != NULL) {
856 /* read only half duplex */
857 dev_dbg(&drv_data->pdev->dev,
858 "IO read: cr is 0x%x\n", cr);
860 /* set SPI transfer mode */
861 write_CTRL(cr | CFG_SPI_READ);
863 drv_data->read(drv_data);
864 if (drv_data->rx != drv_data->rx_end)
868 if (!tranf_success) {
869 dev_dbg(&drv_data->pdev->dev,
870 "IO write error!\n");
871 message->state = ERROR_STATE;
873 /* Update total byte transfered */
874 message->actual_length += drv_data->len;
876 /* Move to next transfer of this msg */
877 message->state = next_transfer(drv_data);
880 /* Schedule next transfer tasklet */
881 tasklet_schedule(&drv_data->pump_transfers);
886 /* pop a msg from queue and kick off real transfer */
887 static void pump_messages(struct work_struct *work)
889 struct driver_data *drv_data;
892 drv_data = container_of(work, struct driver_data, pump_messages);
894 /* Lock queue and check for queue work */
895 spin_lock_irqsave(&drv_data->lock, flags);
896 if (list_empty(&drv_data->queue) || drv_data->run == QUEUE_STOPPED) {
897 /* pumper kicked off but no work to do */
899 spin_unlock_irqrestore(&drv_data->lock, flags);
903 /* Make sure we are not already running a message */
904 if (drv_data->cur_msg) {
905 spin_unlock_irqrestore(&drv_data->lock, flags);
909 /* Extract head of queue */
910 drv_data->cur_msg = list_entry(drv_data->queue.next,
911 struct spi_message, queue);
913 /* Setup the SSP using the per chip configuration */
914 drv_data->cur_chip = spi_get_ctldata(drv_data->cur_msg->spi);
915 if (restore_state(drv_data)) {
916 spin_unlock_irqrestore(&drv_data->lock, flags);
920 list_del_init(&drv_data->cur_msg->queue);
922 /* Initial message state */
923 drv_data->cur_msg->state = START_STATE;
924 drv_data->cur_transfer = list_entry(drv_data->cur_msg->transfers.next,
925 struct spi_transfer, transfer_list);
927 dev_dbg(&drv_data->pdev->dev, "got a message to pump, "
928 "state is set to: baud %d, flag 0x%x, ctl 0x%x\n",
929 drv_data->cur_chip->baud, drv_data->cur_chip->flag,
930 drv_data->cur_chip->ctl_reg);
932 dev_dbg(&drv_data->pdev->dev,
933 "the first transfer len is %d\n",
934 drv_data->cur_transfer->len);
936 /* Mark as busy and launch transfers */
937 tasklet_schedule(&drv_data->pump_transfers);
940 spin_unlock_irqrestore(&drv_data->lock, flags);
944 * got a msg to transfer, queue it in drv_data->queue.
945 * And kick off message pumper
947 static int transfer(struct spi_device *spi, struct spi_message *msg)
949 struct driver_data *drv_data = spi_master_get_devdata(spi->master);
952 spin_lock_irqsave(&drv_data->lock, flags);
954 if (drv_data->run == QUEUE_STOPPED) {
955 spin_unlock_irqrestore(&drv_data->lock, flags);
959 msg->actual_length = 0;
960 msg->status = -EINPROGRESS;
961 msg->state = START_STATE;
963 dev_dbg(&spi->dev, "adding an msg in transfer() \n");
964 list_add_tail(&msg->queue, &drv_data->queue);
966 if (drv_data->run == QUEUE_RUNNING && !drv_data->busy)
967 queue_work(drv_data->workqueue, &drv_data->pump_messages);
969 spin_unlock_irqrestore(&drv_data->lock, flags);
974 #define MAX_SPI_SSEL 7
976 static u16 ssel[3][MAX_SPI_SSEL] = {
977 {P_SPI0_SSEL1, P_SPI0_SSEL2, P_SPI0_SSEL3,
978 P_SPI0_SSEL4, P_SPI0_SSEL5,
979 P_SPI0_SSEL6, P_SPI0_SSEL7},
981 {P_SPI1_SSEL1, P_SPI1_SSEL2, P_SPI1_SSEL3,
982 P_SPI1_SSEL4, P_SPI1_SSEL5,
983 P_SPI1_SSEL6, P_SPI1_SSEL7},
985 {P_SPI2_SSEL1, P_SPI2_SSEL2, P_SPI2_SSEL3,
986 P_SPI2_SSEL4, P_SPI2_SSEL5,
987 P_SPI2_SSEL6, P_SPI2_SSEL7},
990 /* first setup for new devices */
991 static int setup(struct spi_device *spi)
993 struct bfin5xx_spi_chip *chip_info = NULL;
994 struct chip_data *chip;
995 struct driver_data *drv_data = spi_master_get_devdata(spi->master);
998 /* Abort device setup if requested features are not supported */
999 if (spi->mode & ~(SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST)) {
1000 dev_err(&spi->dev, "requested mode not fully supported\n");
1004 /* Zero (the default) here means 8 bits */
1005 if (!spi->bits_per_word)
1006 spi->bits_per_word = 8;
1008 if (spi->bits_per_word != 8 && spi->bits_per_word != 16)
1011 /* Only alloc (or use chip_info) on first setup */
1012 chip = spi_get_ctldata(spi);
1014 chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL);
1018 chip->enable_dma = 0;
1019 chip_info = spi->controller_data;
1022 /* chip_info isn't always needed */
1024 /* Make sure people stop trying to set fields via ctl_reg
1025 * when they should actually be using common SPI framework.
1026 * Currently we let through: WOM EMISO PSSE GM SZ TIMOD.
1027 * Not sure if a user actually needs/uses any of these,
1028 * but let's assume (for now) they do.
1030 if (chip_info->ctl_reg & (SPE|MSTR|CPOL|CPHA|LSBF|SIZE)) {
1031 dev_err(&spi->dev, "do not set bits in ctl_reg "
1032 "that the SPI framework manages\n");
1036 chip->enable_dma = chip_info->enable_dma != 0
1037 && drv_data->master_info->enable_dma;
1038 chip->ctl_reg = chip_info->ctl_reg;
1039 chip->bits_per_word = chip_info->bits_per_word;
1040 chip->cs_change_per_word = chip_info->cs_change_per_word;
1041 chip->cs_chg_udelay = chip_info->cs_chg_udelay;
1044 /* translate common spi framework into our register */
1045 if (spi->mode & SPI_CPOL)
1046 chip->ctl_reg |= CPOL;
1047 if (spi->mode & SPI_CPHA)
1048 chip->ctl_reg |= CPHA;
1049 if (spi->mode & SPI_LSB_FIRST)
1050 chip->ctl_reg |= LSBF;
1051 /* we dont support running in slave mode (yet?) */
1052 chip->ctl_reg |= MSTR;
1055 * if any one SPI chip is registered and wants DMA, request the
1056 * DMA channel for it
1058 if (chip->enable_dma && !dma_requested) {
1059 /* register dma irq handler */
1060 if (request_dma(spi_dma_ch, "BF53x_SPI_DMA") < 0) {
1062 "Unable to request BlackFin SPI DMA channel\n");
1065 if (set_dma_callback(spi_dma_ch, (void *)dma_irq_handler,
1067 dev_dbg(&spi->dev, "Unable to set dma callback\n");
1070 dma_disable_irq(spi_dma_ch);
1075 * Notice: for blackfin, the speed_hz is the value of register
1076 * SPI_BAUD, not the real baudrate
1078 chip->baud = hz_to_spi_baud(spi->max_speed_hz);
1079 spi_flg = ~(1 << (spi->chip_select));
1080 chip->flag = ((u16) spi_flg << 8) | (1 << (spi->chip_select));
1081 chip->chip_select_num = spi->chip_select;
1083 switch (chip->bits_per_word) {
1086 chip->width = CFG_SPI_WORDSIZE8;
1087 chip->read = chip->cs_change_per_word ?
1088 u8_cs_chg_reader : u8_reader;
1089 chip->write = chip->cs_change_per_word ?
1090 u8_cs_chg_writer : u8_writer;
1091 chip->duplex = chip->cs_change_per_word ?
1092 u8_cs_chg_duplex : u8_duplex;
1097 chip->width = CFG_SPI_WORDSIZE16;
1098 chip->read = chip->cs_change_per_word ?
1099 u16_cs_chg_reader : u16_reader;
1100 chip->write = chip->cs_change_per_word ?
1101 u16_cs_chg_writer : u16_writer;
1102 chip->duplex = chip->cs_change_per_word ?
1103 u16_cs_chg_duplex : u16_duplex;
1107 dev_err(&spi->dev, "%d bits_per_word is not supported\n",
1108 chip->bits_per_word);
1113 dev_dbg(&spi->dev, "setup spi chip %s, width is %d, dma is %d\n",
1114 spi->modalias, chip->width, chip->enable_dma);
1115 dev_dbg(&spi->dev, "ctl_reg is 0x%x, flag_reg is 0x%x\n",
1116 chip->ctl_reg, chip->flag);
1118 spi_set_ctldata(spi, chip);
1120 dev_dbg(&spi->dev, "chip select number is %d\n", chip->chip_select_num);
1121 if ((chip->chip_select_num > 0)
1122 && (chip->chip_select_num <= spi->master->num_chipselect))
1123 peripheral_request(ssel[spi->master->bus_num]
1124 [chip->chip_select_num-1], DRV_NAME);
1130 * callback for spi framework.
1131 * clean driver specific data
1133 static void cleanup(struct spi_device *spi)
1135 struct chip_data *chip = spi_get_ctldata(spi);
1137 if ((chip->chip_select_num > 0)
1138 && (chip->chip_select_num <= spi->master->num_chipselect))
1139 peripheral_free(ssel[spi->master->bus_num]
1140 [chip->chip_select_num-1]);
1145 static inline int init_queue(struct driver_data *drv_data)
1147 INIT_LIST_HEAD(&drv_data->queue);
1148 spin_lock_init(&drv_data->lock);
1150 drv_data->run = QUEUE_STOPPED;
1153 /* init transfer tasklet */
1154 tasklet_init(&drv_data->pump_transfers,
1155 pump_transfers, (unsigned long)drv_data);
1157 /* init messages workqueue */
1158 INIT_WORK(&drv_data->pump_messages, pump_messages);
1159 drv_data->workqueue =
1160 create_singlethread_workqueue(drv_data->master->dev.parent->bus_id);
1161 if (drv_data->workqueue == NULL)
1167 static inline int start_queue(struct driver_data *drv_data)
1169 unsigned long flags;
1171 spin_lock_irqsave(&drv_data->lock, flags);
1173 if (drv_data->run == QUEUE_RUNNING || drv_data->busy) {
1174 spin_unlock_irqrestore(&drv_data->lock, flags);
1178 drv_data->run = QUEUE_RUNNING;
1179 drv_data->cur_msg = NULL;
1180 drv_data->cur_transfer = NULL;
1181 drv_data->cur_chip = NULL;
1182 spin_unlock_irqrestore(&drv_data->lock, flags);
1184 queue_work(drv_data->workqueue, &drv_data->pump_messages);
1189 static inline int stop_queue(struct driver_data *drv_data)
1191 unsigned long flags;
1192 unsigned limit = 500;
1195 spin_lock_irqsave(&drv_data->lock, flags);
1198 * This is a bit lame, but is optimized for the common execution path.
1199 * A wait_queue on the drv_data->busy could be used, but then the common
1200 * execution path (pump_messages) would be required to call wake_up or
1201 * friends on every SPI message. Do this instead
1203 drv_data->run = QUEUE_STOPPED;
1204 while (!list_empty(&drv_data->queue) && drv_data->busy && limit--) {
1205 spin_unlock_irqrestore(&drv_data->lock, flags);
1207 spin_lock_irqsave(&drv_data->lock, flags);
1210 if (!list_empty(&drv_data->queue) || drv_data->busy)
1213 spin_unlock_irqrestore(&drv_data->lock, flags);
1218 static inline int destroy_queue(struct driver_data *drv_data)
1222 status = stop_queue(drv_data);
1226 destroy_workqueue(drv_data->workqueue);
1231 static int setup_pin_mux(int action, int bus_num)
1234 u16 pin_req[3][4] = {
1235 {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0},
1236 {P_SPI1_SCK, P_SPI1_MISO, P_SPI1_MOSI, 0},
1237 {P_SPI2_SCK, P_SPI2_MISO, P_SPI2_MOSI, 0},
1241 if (peripheral_request_list(pin_req[bus_num], DRV_NAME))
1244 peripheral_free_list(pin_req[bus_num]);
1250 static int __init bfin5xx_spi_probe(struct platform_device *pdev)
1252 struct device *dev = &pdev->dev;
1253 struct bfin5xx_spi_master *platform_info;
1254 struct spi_master *master;
1255 struct driver_data *drv_data = 0;
1256 struct resource *res;
1259 platform_info = dev->platform_data;
1261 /* Allocate master with space for drv_data */
1262 master = spi_alloc_master(dev, sizeof(struct driver_data) + 16);
1264 dev_err(&pdev->dev, "can not alloc spi_master\n");
1268 drv_data = spi_master_get_devdata(master);
1269 drv_data->master = master;
1270 drv_data->master_info = platform_info;
1271 drv_data->pdev = pdev;
1273 master->bus_num = pdev->id;
1274 master->num_chipselect = platform_info->num_chipselect;
1275 master->cleanup = cleanup;
1276 master->setup = setup;
1277 master->transfer = transfer;
1279 /* Find and map our resources */
1280 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1282 dev_err(dev, "Cannot get IORESOURCE_MEM\n");
1284 goto out_error_get_res;
1287 spi_regs_base = (u32) ioremap(res->start, (res->end - res->start)+1);
1288 if (!spi_regs_base) {
1289 dev_err(dev, "Cannot map IO\n");
1291 goto out_error_ioremap;
1294 spi_dma_ch = platform_get_irq(pdev, 0);
1295 if (spi_dma_ch < 0) {
1296 dev_err(dev, "No DMA channel specified\n");
1298 goto out_error_no_dma_ch;
1301 /* Initial and start queue */
1302 status = init_queue(drv_data);
1304 dev_err(dev, "problem initializing queue\n");
1305 goto out_error_queue_alloc;
1308 status = start_queue(drv_data);
1310 dev_err(dev, "problem starting queue\n");
1311 goto out_error_queue_alloc;
1314 /* Register with the SPI framework */
1315 platform_set_drvdata(pdev, drv_data);
1316 status = spi_register_master(master);
1318 dev_err(dev, "problem registering spi master\n");
1319 goto out_error_queue_alloc;
1322 if (setup_pin_mux(1, master->bus_num)) {
1323 dev_err(&pdev->dev, ": Requesting Peripherals failed\n");
1327 dev_info(dev, "%s, Version %s, regs_base @ 0x%08x\n",
1328 DRV_DESC, DRV_VERSION, spi_regs_base);
1331 out_error_queue_alloc:
1332 destroy_queue(drv_data);
1333 out_error_no_dma_ch:
1334 iounmap((void *) spi_regs_base);
1338 spi_master_put(master);
1343 /* stop hardware and remove the driver */
1344 static int __devexit bfin5xx_spi_remove(struct platform_device *pdev)
1346 struct driver_data *drv_data = platform_get_drvdata(pdev);
1352 /* Remove the queue */
1353 status = destroy_queue(drv_data);
1357 /* Disable the SSP at the peripheral and SOC level */
1358 bfin_spi_disable(drv_data);
1361 if (drv_data->master_info->enable_dma) {
1362 if (dma_channel_active(spi_dma_ch))
1363 free_dma(spi_dma_ch);
1366 /* Disconnect from the SPI framework */
1367 spi_unregister_master(drv_data->master);
1369 setup_pin_mux(0, drv_data->master->bus_num);
1371 /* Prevent double remove */
1372 platform_set_drvdata(pdev, NULL);
1378 static int bfin5xx_spi_suspend(struct platform_device *pdev, pm_message_t state)
1380 struct driver_data *drv_data = platform_get_drvdata(pdev);
1383 status = stop_queue(drv_data);
1388 bfin_spi_disable(drv_data);
1393 static int bfin5xx_spi_resume(struct platform_device *pdev)
1395 struct driver_data *drv_data = platform_get_drvdata(pdev);
1398 /* Enable the SPI interface */
1399 bfin_spi_enable(drv_data);
1401 /* Start the queue running */
1402 status = start_queue(drv_data);
1404 dev_err(&pdev->dev, "problem starting queue (%d)\n", status);
1411 #define bfin5xx_spi_suspend NULL
1412 #define bfin5xx_spi_resume NULL
1413 #endif /* CONFIG_PM */
1415 MODULE_ALIAS("bfin-spi-master"); /* for platform bus hotplug */
1416 static struct platform_driver bfin5xx_spi_driver = {
1419 .owner = THIS_MODULE,
1421 .suspend = bfin5xx_spi_suspend,
1422 .resume = bfin5xx_spi_resume,
1423 .remove = __devexit_p(bfin5xx_spi_remove),
1426 static int __init bfin5xx_spi_init(void)
1428 return platform_driver_probe(&bfin5xx_spi_driver, bfin5xx_spi_probe);
1430 module_init(bfin5xx_spi_init);
1432 static void __exit bfin5xx_spi_exit(void)
1434 platform_driver_unregister(&bfin5xx_spi_driver);
1436 module_exit(bfin5xx_spi_exit);