2 * Copyright (c) 2001-2002 by David Brownell
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License as published by the
6 * Free Software Foundation; either version 2 of the License, or (at your
7 * option) any later version.
9 * This program is distributed in the hope that it will be useful, but
10 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
11 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software Foundation,
16 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
19 #ifndef __LINUX_EHCI_HCD_H
20 #define __LINUX_EHCI_HCD_H
22 /* definitions used for the EHCI driver */
25 * __hc32 and __hc16 are "Host Controller" types, they may be equivalent to
26 * __leXX (normally) or __beXX (given EHCI_BIG_ENDIAN_DESC), depending on
27 * the host controller implementation.
29 * To facilitate the strongest possible byte-order checking from "sparse"
30 * and so on, we use __leXX unless that's not practical.
32 #ifdef CONFIG_USB_EHCI_BIG_ENDIAN_DESC
33 typedef __u32 __bitwise __hc32;
34 typedef __u16 __bitwise __hc16;
40 /* statistics can be kept for for tuning/monitoring */
45 unsigned long reclaim;
46 unsigned long lost_iaa;
48 /* termination of urbs from core */
49 unsigned long complete;
53 /* ehci_hcd->lock guards shared data against other CPUs:
54 * ehci_hcd: async, reclaim, periodic (and shadow), ...
55 * usb_host_endpoint: hcpriv
56 * ehci_qh: qh_next, qtd_list
59 * Also, hold this lock when talking to HC registers or
60 * when updating hw_* fields in shared qh/qtd/... structures.
63 #define EHCI_MAX_ROOT_PORTS 15 /* see HCS_N_PORTS */
65 struct ehci_hcd { /* one per controller */
66 /* glue to PCI and HCD framework */
67 struct ehci_caps __iomem *caps;
68 struct ehci_regs __iomem *regs;
69 struct ehci_dbg_port __iomem *debug;
71 __u32 hcs_params; /* cached register copy */
74 /* async schedule support */
75 struct ehci_qh *async;
76 struct ehci_qh *reclaim;
77 unsigned scanning : 1;
79 /* periodic schedule support */
80 #define DEFAULT_I_TDPS 1024 /* some HCs can do less */
81 unsigned periodic_size;
82 __hc32 *periodic; /* hw periodic table */
83 dma_addr_t periodic_dma;
84 unsigned i_thresh; /* uframes HC might cache */
86 union ehci_shadow *pshadow; /* mirror hw periodic table */
87 int next_uframe; /* scan periodic, start here */
88 unsigned periodic_sched; /* periodic activity count */
90 /* per root hub port */
91 unsigned long reset_done [EHCI_MAX_ROOT_PORTS];
93 /* bit vectors (one bit per port) */
94 unsigned long bus_suspended; /* which ports were
95 already suspended at the start of a bus suspend */
96 unsigned long companion_ports; /* which ports are
97 dedicated to the companion controller */
98 unsigned long owned_ports; /* which ports are
99 owned by the companion during a bus suspend */
100 unsigned long port_c_suspend; /* which ports have
101 the change-suspend feature turned on */
103 /* per-HC memory pools (could be per-bus, but ...) */
104 struct dma_pool *qh_pool; /* qh per active urb */
105 struct dma_pool *qtd_pool; /* one or more per qh */
106 struct dma_pool *itd_pool; /* itd per iso urb */
107 struct dma_pool *sitd_pool; /* sitd per split iso urb */
109 struct timer_list iaa_watchdog;
110 struct timer_list watchdog;
111 unsigned long actions;
113 unsigned long next_statechange;
117 unsigned no_selective_suspend:1;
118 unsigned has_fsl_port_bug:1; /* FreeScale */
119 unsigned big_endian_mmio:1;
120 unsigned big_endian_desc:1;
122 u8 sbrn; /* packed release number */
126 struct ehci_stats stats;
127 # define COUNT(x) do { (x)++; } while (0)
129 # define COUNT(x) do {} while (0)
134 struct dentry *debug_dir;
135 struct dentry *debug_async;
136 struct dentry *debug_periodic;
137 struct dentry *debug_registers;
141 /* convert between an HCD pointer and the corresponding EHCI_HCD */
142 static inline struct ehci_hcd *hcd_to_ehci (struct usb_hcd *hcd)
144 return (struct ehci_hcd *) (hcd->hcd_priv);
146 static inline struct usb_hcd *ehci_to_hcd (struct ehci_hcd *ehci)
148 return container_of ((void *) ehci, struct usb_hcd, hcd_priv);
153 iaa_watchdog_start(struct ehci_hcd *ehci)
155 WARN_ON(timer_pending(&ehci->iaa_watchdog));
156 mod_timer(&ehci->iaa_watchdog,
157 jiffies + msecs_to_jiffies(EHCI_IAA_MSECS));
160 static inline void iaa_watchdog_done(struct ehci_hcd *ehci)
162 del_timer(&ehci->iaa_watchdog);
165 enum ehci_timer_action {
172 timer_action_done (struct ehci_hcd *ehci, enum ehci_timer_action action)
174 clear_bit (action, &ehci->actions);
178 timer_action (struct ehci_hcd *ehci, enum ehci_timer_action action)
180 /* Don't override timeouts which shrink or (later) disable
181 * the async ring; just the I/O watchdog. Note that if a
182 * SHRINK were pending, OFF would never be requested.
184 if (timer_pending(&ehci->watchdog)
185 && ((BIT(TIMER_ASYNC_SHRINK) | BIT(TIMER_ASYNC_OFF))
189 if (!test_and_set_bit (action, &ehci->actions)) {
193 case TIMER_IO_WATCHDOG:
196 case TIMER_ASYNC_OFF:
197 t = EHCI_ASYNC_JIFFIES;
199 // case TIMER_ASYNC_SHRINK:
201 /* add a jiffie since we synch against the
202 * 8 KHz uframe counter.
204 t = DIV_ROUND_UP(EHCI_SHRINK_FRAMES * HZ, 1000) + 1;
207 mod_timer(&ehci->watchdog, t + jiffies);
211 /*-------------------------------------------------------------------------*/
213 #include <linux/usb/ehci_def.h>
215 /*-------------------------------------------------------------------------*/
217 #define QTD_NEXT(ehci, dma) cpu_to_hc32(ehci, (u32)dma)
220 * EHCI Specification 0.95 Section 3.5
221 * QTD: describe data transfer components (buffer, direction, ...)
222 * See Fig 3-6 "Queue Element Transfer Descriptor Block Diagram".
224 * These are associated only with "QH" (Queue Head) structures,
225 * used with control, bulk, and interrupt transfers.
228 /* first part defined by EHCI spec */
229 __hc32 hw_next; /* see EHCI 3.5.1 */
230 __hc32 hw_alt_next; /* see EHCI 3.5.2 */
231 __hc32 hw_token; /* see EHCI 3.5.3 */
232 #define QTD_TOGGLE (1 << 31) /* data toggle */
233 #define QTD_LENGTH(tok) (((tok)>>16) & 0x7fff)
234 #define QTD_IOC (1 << 15) /* interrupt on complete */
235 #define QTD_CERR(tok) (((tok)>>10) & 0x3)
236 #define QTD_PID(tok) (((tok)>>8) & 0x3)
237 #define QTD_STS_ACTIVE (1 << 7) /* HC may execute this */
238 #define QTD_STS_HALT (1 << 6) /* halted on error */
239 #define QTD_STS_DBE (1 << 5) /* data buffer error (in HC) */
240 #define QTD_STS_BABBLE (1 << 4) /* device was babbling (qtd halted) */
241 #define QTD_STS_XACT (1 << 3) /* device gave illegal response */
242 #define QTD_STS_MMF (1 << 2) /* incomplete split transaction */
243 #define QTD_STS_STS (1 << 1) /* split transaction state */
244 #define QTD_STS_PING (1 << 0) /* issue PING? */
246 #define ACTIVE_BIT(ehci) cpu_to_hc32(ehci, QTD_STS_ACTIVE)
247 #define HALT_BIT(ehci) cpu_to_hc32(ehci, QTD_STS_HALT)
248 #define STATUS_BIT(ehci) cpu_to_hc32(ehci, QTD_STS_STS)
250 __hc32 hw_buf [5]; /* see EHCI 3.5.4 */
251 __hc32 hw_buf_hi [5]; /* Appendix B */
253 /* the rest is HCD-private */
254 dma_addr_t qtd_dma; /* qtd address */
255 struct list_head qtd_list; /* sw qtd list */
256 struct urb *urb; /* qtd's urb */
257 size_t length; /* length of buffer */
258 } __attribute__ ((aligned (32)));
260 /* mask NakCnt+T in qh->hw_alt_next */
261 #define QTD_MASK(ehci) cpu_to_hc32 (ehci, ~0x1f)
263 #define IS_SHORT_READ(token) (QTD_LENGTH (token) != 0 && QTD_PID (token) == 1)
265 /*-------------------------------------------------------------------------*/
267 /* type tag from {qh,itd,sitd,fstn}->hw_next */
268 #define Q_NEXT_TYPE(ehci,dma) ((dma) & cpu_to_hc32(ehci, 3 << 1))
271 * Now the following defines are not converted using the
272 * __constant_cpu_to_le32() macro anymore, since we have to support
273 * "dynamic" switching between be and le support, so that the driver
274 * can be used on one system with SoC EHCI controller using big-endian
275 * descriptors as well as a normal little-endian PCI EHCI controller.
277 /* values for that type tag */
278 #define Q_TYPE_ITD (0 << 1)
279 #define Q_TYPE_QH (1 << 1)
280 #define Q_TYPE_SITD (2 << 1)
281 #define Q_TYPE_FSTN (3 << 1)
283 /* next async queue entry, or pointer to interrupt/periodic QH */
284 #define QH_NEXT(ehci,dma) (cpu_to_hc32(ehci, (((u32)dma)&~0x01f)|Q_TYPE_QH))
286 /* for periodic/async schedules and qtd lists, mark end of list */
287 #define EHCI_LIST_END(ehci) cpu_to_hc32(ehci, 1) /* "null pointer" to hw */
290 * Entries in periodic shadow table are pointers to one of four kinds
291 * of data structure. That's dictated by the hardware; a type tag is
292 * encoded in the low bits of the hardware's periodic schedule. Use
293 * Q_NEXT_TYPE to get the tag.
295 * For entries in the async schedule, the type tag always says "qh".
298 struct ehci_qh *qh; /* Q_TYPE_QH */
299 struct ehci_itd *itd; /* Q_TYPE_ITD */
300 struct ehci_sitd *sitd; /* Q_TYPE_SITD */
301 struct ehci_fstn *fstn; /* Q_TYPE_FSTN */
302 __hc32 *hw_next; /* (all types) */
306 /*-------------------------------------------------------------------------*/
309 * EHCI Specification 0.95 Section 3.6
310 * QH: describes control/bulk/interrupt endpoints
311 * See Fig 3-7 "Queue Head Structure Layout".
313 * These appear in both the async and (for interrupt) periodic schedules.
317 /* first part defined by EHCI spec */
318 __hc32 hw_next; /* see EHCI 3.6.1 */
319 __hc32 hw_info1; /* see EHCI 3.6.2 */
320 #define QH_HEAD 0x00008000
321 __hc32 hw_info2; /* see EHCI 3.6.2 */
322 #define QH_SMASK 0x000000ff
323 #define QH_CMASK 0x0000ff00
324 #define QH_HUBADDR 0x007f0000
325 #define QH_HUBPORT 0x3f800000
326 #define QH_MULT 0xc0000000
327 __hc32 hw_current; /* qtd list - see EHCI 3.6.4 */
329 /* qtd overlay (hardware parts of a struct ehci_qtd) */
334 __hc32 hw_buf_hi [5];
336 /* the rest is HCD-private */
337 dma_addr_t qh_dma; /* address of qh */
338 union ehci_shadow qh_next; /* ptr to qh; or periodic */
339 struct list_head qtd_list; /* sw qtd list */
340 struct ehci_qtd *dummy;
341 struct ehci_qh *reclaim; /* next to reclaim */
343 struct ehci_hcd *ehci;
346 * Do NOT use atomic operations for QH refcounting. On some CPUs
347 * (PPC7448 for example), atomic operations cannot be performed on
348 * memory that is cache-inhibited (i.e. being used for DMA).
349 * Spinlocks are used to protect all QH fields.
355 #define QH_STATE_LINKED 1 /* HC sees this */
356 #define QH_STATE_UNLINK 2 /* HC may still see this */
357 #define QH_STATE_IDLE 3 /* HC doesn't see this */
358 #define QH_STATE_UNLINK_WAIT 4 /* LINKED and on reclaim q */
359 #define QH_STATE_COMPLETING 5 /* don't touch token.HALT */
361 /* periodic schedule info */
362 u8 usecs; /* intr bandwidth */
363 u8 gap_uf; /* uframes split/csplit gap */
364 u8 c_usecs; /* ... split completion bw */
365 u16 tt_usecs; /* tt downstream bandwidth */
366 unsigned short period; /* polling interval */
367 unsigned short start; /* where polling starts */
368 #define NO_FRAME ((unsigned short)~0) /* pick new start */
369 struct usb_device *dev; /* access to TT */
370 } __attribute__ ((aligned (32)));
372 /*-------------------------------------------------------------------------*/
374 /* description of one iso transaction (up to 3 KB data if highspeed) */
375 struct ehci_iso_packet {
376 /* These will be copied to iTD when scheduling */
377 u64 bufp; /* itd->hw_bufp{,_hi}[pg] |= */
378 __hc32 transaction; /* itd->hw_transaction[i] |= */
379 u8 cross; /* buf crosses pages */
380 /* for full speed OUT splits */
384 /* temporary schedule data for packets from iso urbs (both speeds)
385 * each packet is one logical usb transaction to the device (not TT),
386 * beginning at stream->next_uframe
388 struct ehci_iso_sched {
389 struct list_head td_list;
391 struct ehci_iso_packet packet [0];
395 * ehci_iso_stream - groups all (s)itds for this endpoint.
396 * acts like a qh would, if EHCI had them for ISO.
398 struct ehci_iso_stream {
399 /* first two fields match QH, but info1 == 0 */
406 u16 depth; /* depth in uframes */
407 struct list_head td_list; /* queued itds/sitds */
408 struct list_head free_list; /* list of unused itds/sitds */
409 struct usb_device *udev;
410 struct usb_host_endpoint *ep;
412 /* output of (re)scheduling */
413 unsigned long start; /* jiffies */
414 unsigned long rescheduled;
418 /* the rest is derived from the endpoint descriptor,
419 * trusting urb->interval == f(epdesc->bInterval) and
420 * including the extra info for hw_bufp[0..2]
429 /* This is used to initialize iTD's hw_bufp fields */
434 /* this is used to initialize sITD's tt info */
438 /*-------------------------------------------------------------------------*/
441 * EHCI Specification 0.95 Section 3.3
442 * Fig 3-4 "Isochronous Transaction Descriptor (iTD)"
444 * Schedule records for high speed iso xfers
447 /* first part defined by EHCI spec */
448 __hc32 hw_next; /* see EHCI 3.3.1 */
449 __hc32 hw_transaction [8]; /* see EHCI 3.3.2 */
450 #define EHCI_ISOC_ACTIVE (1<<31) /* activate transfer this slot */
451 #define EHCI_ISOC_BUF_ERR (1<<30) /* Data buffer error */
452 #define EHCI_ISOC_BABBLE (1<<29) /* babble detected */
453 #define EHCI_ISOC_XACTERR (1<<28) /* XactErr - transaction error */
454 #define EHCI_ITD_LENGTH(tok) (((tok)>>16) & 0x0fff)
455 #define EHCI_ITD_IOC (1 << 15) /* interrupt on complete */
457 #define ITD_ACTIVE(ehci) cpu_to_hc32(ehci, EHCI_ISOC_ACTIVE)
459 __hc32 hw_bufp [7]; /* see EHCI 3.3.3 */
460 __hc32 hw_bufp_hi [7]; /* Appendix B */
462 /* the rest is HCD-private */
463 dma_addr_t itd_dma; /* for this itd */
464 union ehci_shadow itd_next; /* ptr to periodic q entry */
467 struct ehci_iso_stream *stream; /* endpoint's queue */
468 struct list_head itd_list; /* list of stream's itds */
470 /* any/all hw_transactions here may be used by that urb */
471 unsigned frame; /* where scheduled */
473 unsigned index[8]; /* in urb->iso_frame_desc */
474 } __attribute__ ((aligned (32)));
476 /*-------------------------------------------------------------------------*/
479 * EHCI Specification 0.95 Section 3.4
480 * siTD, aka split-transaction isochronous Transfer Descriptor
481 * ... describe full speed iso xfers through TT in hubs
482 * see Figure 3-5 "Split-transaction Isochronous Transaction Descriptor (siTD)
485 /* first part defined by EHCI spec */
487 /* uses bit field macros above - see EHCI 0.95 Table 3-8 */
488 __hc32 hw_fullspeed_ep; /* EHCI table 3-9 */
489 __hc32 hw_uframe; /* EHCI table 3-10 */
490 __hc32 hw_results; /* EHCI table 3-11 */
491 #define SITD_IOC (1 << 31) /* interrupt on completion */
492 #define SITD_PAGE (1 << 30) /* buffer 0/1 */
493 #define SITD_LENGTH(x) (0x3ff & ((x)>>16))
494 #define SITD_STS_ACTIVE (1 << 7) /* HC may execute this */
495 #define SITD_STS_ERR (1 << 6) /* error from TT */
496 #define SITD_STS_DBE (1 << 5) /* data buffer error (in HC) */
497 #define SITD_STS_BABBLE (1 << 4) /* device was babbling */
498 #define SITD_STS_XACT (1 << 3) /* illegal IN response */
499 #define SITD_STS_MMF (1 << 2) /* incomplete split transaction */
500 #define SITD_STS_STS (1 << 1) /* split transaction state */
502 #define SITD_ACTIVE(ehci) cpu_to_hc32(ehci, SITD_STS_ACTIVE)
504 __hc32 hw_buf [2]; /* EHCI table 3-12 */
505 __hc32 hw_backpointer; /* EHCI table 3-13 */
506 __hc32 hw_buf_hi [2]; /* Appendix B */
508 /* the rest is HCD-private */
510 union ehci_shadow sitd_next; /* ptr to periodic q entry */
513 struct ehci_iso_stream *stream; /* endpoint's queue */
514 struct list_head sitd_list; /* list of stream's sitds */
517 } __attribute__ ((aligned (32)));
519 /*-------------------------------------------------------------------------*/
522 * EHCI Specification 0.96 Section 3.7
523 * Periodic Frame Span Traversal Node (FSTN)
525 * Manages split interrupt transactions (using TT) that span frame boundaries
526 * into uframes 0/1; see 4.12.2.2. In those uframes, a "save place" FSTN
527 * makes the HC jump (back) to a QH to scan for fs/ls QH completions until
528 * it hits a "restore" FSTN; then it returns to finish other uframe 0/1 work.
531 __hc32 hw_next; /* any periodic q entry */
532 __hc32 hw_prev; /* qh or EHCI_LIST_END */
534 /* the rest is HCD-private */
536 union ehci_shadow fstn_next; /* ptr to periodic q entry */
537 } __attribute__ ((aligned (32)));
539 /*-------------------------------------------------------------------------*/
541 #ifdef CONFIG_USB_EHCI_ROOT_HUB_TT
544 * Some EHCI controllers have a Transaction Translator built into the
545 * root hub. This is a non-standard feature. Each controller will need
546 * to add code to the following inline functions, and call them as
547 * needed (mostly in root hub code).
550 #define ehci_is_TDI(e) (ehci_to_hcd(e)->has_tt)
552 /* Returns the speed of a device attached to a port on the root hub. */
553 static inline unsigned int
554 ehci_port_speed(struct ehci_hcd *ehci, unsigned int portsc)
556 if (ehci_is_TDI(ehci)) {
557 switch ((portsc>>26)&3) {
561 return (1<<USB_PORT_FEAT_LOWSPEED);
564 return (1<<USB_PORT_FEAT_HIGHSPEED);
567 return (1<<USB_PORT_FEAT_HIGHSPEED);
572 #define ehci_is_TDI(e) (0)
574 #define ehci_port_speed(ehci, portsc) (1<<USB_PORT_FEAT_HIGHSPEED)
577 /*-------------------------------------------------------------------------*/
579 #ifdef CONFIG_PPC_83xx
580 /* Some Freescale processors have an erratum in which the TT
581 * port number in the queue head was 0..N-1 instead of 1..N.
583 #define ehci_has_fsl_portno_bug(e) ((e)->has_fsl_port_bug)
585 #define ehci_has_fsl_portno_bug(e) (0)
589 * While most USB host controllers implement their registers in
590 * little-endian format, a minority (celleb companion chip) implement
591 * them in big endian format.
593 * This attempts to support either format at compile time without a
594 * runtime penalty, or both formats with the additional overhead
595 * of checking a flag bit.
598 #ifdef CONFIG_USB_EHCI_BIG_ENDIAN_MMIO
599 #define ehci_big_endian_mmio(e) ((e)->big_endian_mmio)
601 #define ehci_big_endian_mmio(e) 0
605 * Big-endian read/write functions are arch-specific.
606 * Other arches can be added if/when they're needed.
608 * REVISIT: arch/powerpc now has readl/writel_be, so the
609 * definition below can die once the 4xx support is
610 * finally ported over.
612 #if defined(CONFIG_PPC) && !defined(CONFIG_PPC_MERGE)
613 #define readl_be(addr) in_be32((__force unsigned *)addr)
614 #define writel_be(val, addr) out_be32((__force unsigned *)addr, val)
617 #if defined(CONFIG_ARM) && defined(CONFIG_ARCH_IXP4XX)
618 #define readl_be(addr) __raw_readl((__force unsigned *)addr)
619 #define writel_be(val, addr) __raw_writel(val, (__force unsigned *)addr)
622 static inline unsigned int ehci_readl(const struct ehci_hcd *ehci,
623 __u32 __iomem * regs)
625 #ifdef CONFIG_USB_EHCI_BIG_ENDIAN_MMIO
626 return ehci_big_endian_mmio(ehci) ?
634 static inline void ehci_writel(const struct ehci_hcd *ehci,
635 const unsigned int val, __u32 __iomem *regs)
637 #ifdef CONFIG_USB_EHCI_BIG_ENDIAN_MMIO
638 ehci_big_endian_mmio(ehci) ?
639 writel_be(val, regs) :
646 /*-------------------------------------------------------------------------*/
649 * The AMCC 440EPx not only implements its EHCI registers in big-endian
650 * format, but also its DMA data structures (descriptors).
652 * EHCI controllers accessed through PCI work normally (little-endian
653 * everywhere), so we won't bother supporting a BE-only mode for now.
655 #ifdef CONFIG_USB_EHCI_BIG_ENDIAN_DESC
656 #define ehci_big_endian_desc(e) ((e)->big_endian_desc)
659 static inline __hc32 cpu_to_hc32 (const struct ehci_hcd *ehci, const u32 x)
661 return ehci_big_endian_desc(ehci)
662 ? (__force __hc32)cpu_to_be32(x)
663 : (__force __hc32)cpu_to_le32(x);
667 static inline u32 hc32_to_cpu (const struct ehci_hcd *ehci, const __hc32 x)
669 return ehci_big_endian_desc(ehci)
670 ? be32_to_cpu((__force __be32)x)
671 : le32_to_cpu((__force __le32)x);
674 static inline u32 hc32_to_cpup (const struct ehci_hcd *ehci, const __hc32 *x)
676 return ehci_big_endian_desc(ehci)
677 ? be32_to_cpup((__force __be32 *)x)
678 : le32_to_cpup((__force __le32 *)x);
684 static inline __hc32 cpu_to_hc32 (const struct ehci_hcd *ehci, const u32 x)
686 return cpu_to_le32(x);
690 static inline u32 hc32_to_cpu (const struct ehci_hcd *ehci, const __hc32 x)
692 return le32_to_cpu(x);
695 static inline u32 hc32_to_cpup (const struct ehci_hcd *ehci, const __hc32 *x)
697 return le32_to_cpup(x);
702 /*-------------------------------------------------------------------------*/
705 #define STUB_DEBUG_FILES
708 /*-------------------------------------------------------------------------*/
710 #endif /* __LINUX_EHCI_HCD_H */