2 * OHCI HCD (Host Controller Driver) for USB.
4 * (C) Copyright 1999 Roman Weissgaerber <weissg@vienna.at>
5 * (C) Copyright 2000-2002 David Brownell <dbrownell@users.sourceforge.net>
7 * [ Initialisation is based on Linus' ]
8 * [ uhci code and gregs ohci fragments ]
9 * [ (C) Copyright 1999 Linus Torvalds ]
10 * [ (C) Copyright 1999 Gregory P. Smith]
14 * This file is licenced under the GPL.
18 #error "This file is PCI bus glue. CONFIG_PCI must be defined."
21 /*-------------------------------------------------------------------------*/
23 static int broken_suspend(struct usb_hcd *hcd)
25 device_init_wakeup(&hcd->self.root_hub->dev, 0);
29 /* AMD 756, for most chips (early revs), corrupts register
30 * values on read ... so enable the vendor workaround.
32 static int ohci_quirk_amd756(struct usb_hcd *hcd)
34 struct ohci_hcd *ohci = hcd_to_ohci (hcd);
36 ohci->flags = OHCI_QUIRK_AMD756;
37 ohci_dbg (ohci, "AMD756 erratum 4 workaround\n");
39 /* also erratum 10 (suspend/resume issues) */
40 return broken_suspend(hcd);
43 /* Apple's OHCI driver has a lot of bizarre workarounds
44 * for this chip. Evidently control and bulk lists
45 * can get confused. (B&W G3 models, and ...)
47 static int ohci_quirk_opti(struct usb_hcd *hcd)
49 struct ohci_hcd *ohci = hcd_to_ohci (hcd);
51 ohci_dbg (ohci, "WARNING: OPTi workarounds unavailable\n");
56 /* Check for NSC87560. We have to look at the bridge (fn1) to
57 * identify the USB (fn2). This quirk might apply to more or
60 static int ohci_quirk_ns(struct usb_hcd *hcd)
62 struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
65 b = pci_get_slot (pdev->bus, PCI_DEVFN (PCI_SLOT (pdev->devfn), 1));
66 if (b && b->device == PCI_DEVICE_ID_NS_87560_LIO
67 && b->vendor == PCI_VENDOR_ID_NS) {
68 struct ohci_hcd *ohci = hcd_to_ohci (hcd);
70 ohci->flags |= OHCI_QUIRK_SUPERIO;
71 ohci_dbg (ohci, "Using NSC SuperIO setup\n");
78 /* Check for Compaq's ZFMicro chipset, which needs short
79 * delays before control or bulk queues get re-activated
82 static int ohci_quirk_zfmicro(struct usb_hcd *hcd)
84 struct ohci_hcd *ohci = hcd_to_ohci (hcd);
86 ohci->flags |= OHCI_QUIRK_ZFMICRO;
87 ohci_dbg (ohci, "enabled Compaq ZFMicro chipset quirk\n");
92 /* Check for Toshiba SCC OHCI which has big endian registers
93 * and little endian in memory data structures
95 static int ohci_quirk_toshiba_scc(struct usb_hcd *hcd)
97 struct ohci_hcd *ohci = hcd_to_ohci (hcd);
99 /* That chip is only present in the southbridge of some
100 * cell based platforms which are supposed to select
101 * CONFIG_USB_OHCI_BIG_ENDIAN_MMIO. We verify here if
102 * that was the case though.
104 #ifdef CONFIG_USB_OHCI_BIG_ENDIAN_MMIO
105 ohci->flags |= OHCI_QUIRK_BE_MMIO;
106 ohci_dbg (ohci, "enabled big endian Toshiba quirk\n");
109 ohci_err (ohci, "unsupported big endian Toshiba quirk\n");
114 /* List of quirks for OHCI */
115 static const struct pci_device_id ohci_pci_quirks[] = {
117 PCI_DEVICE(PCI_VENDOR_ID_AMD, 0x740c),
118 .driver_data = (unsigned long)ohci_quirk_amd756,
121 PCI_DEVICE(PCI_VENDOR_ID_OPTI, 0xc861),
122 .driver_data = (unsigned long)ohci_quirk_opti,
125 PCI_DEVICE(PCI_VENDOR_ID_NS, PCI_ANY_ID),
126 .driver_data = (unsigned long)ohci_quirk_ns,
129 PCI_DEVICE(PCI_VENDOR_ID_COMPAQ, 0xa0f8),
130 .driver_data = (unsigned long)ohci_quirk_zfmicro,
133 PCI_DEVICE(PCI_VENDOR_ID_TOSHIBA_2, 0x01b6),
134 .driver_data = (unsigned long)ohci_quirk_toshiba_scc,
137 /* Toshiba portege 4000 */
138 .vendor = PCI_VENDOR_ID_AL,
140 .subvendor = PCI_VENDOR_ID_TOSHIBA,
142 .driver_data = (unsigned long) broken_suspend,
145 PCI_DEVICE(PCI_VENDOR_ID_ITE, 0x8152),
146 .driver_data = (unsigned long) broken_suspend,
148 /* FIXME for some of the early AMD 760 southbridges, OHCI
149 * won't work at all. blacklist them.
155 static int ohci_pci_reset (struct usb_hcd *hcd)
157 struct ohci_hcd *ohci = hcd_to_ohci (hcd);
160 if (hcd->self.controller) {
161 struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
162 const struct pci_device_id *quirk_id;
164 quirk_id = pci_match_id(ohci_pci_quirks, pdev);
165 if (quirk_id != NULL) {
166 int (*quirk)(struct usb_hcd *ohci);
167 quirk = (void *)quirk_id->driver_data;
172 ohci_hcd_init (ohci);
173 return ohci_init (ohci);
179 static int __devinit ohci_pci_start (struct usb_hcd *hcd)
181 struct ohci_hcd *ohci = hcd_to_ohci (hcd);
184 #ifdef CONFIG_PM /* avoid warnings about unused pdev */
185 if (hcd->self.controller) {
186 struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
188 /* RWC may not be set for add-in PCI cards, since boot
189 * firmware probably ignored them. This transfers PCI
190 * PM wakeup capabilities (once the PCI layer is fixed).
192 if (device_may_wakeup(&pdev->dev))
193 ohci->hc_control |= OHCI_CTRL_RWC;
195 #endif /* CONFIG_PM */
197 ret = ohci_run (ohci);
199 ohci_err (ohci, "can't start\n");
205 #if defined(CONFIG_USB_PERSIST) && (defined(CONFIG_USB_EHCI_HCD) || \
206 defined(CONFIG_USB_EHCI_HCD_MODULE))
208 /* Following a power loss, we must prepare to regain control of the ports
209 * we used to own. This means turning on the port power before ehci-hcd
210 * tries to switch ownership.
212 * This isn't a 100% perfect solution. On most systems the OHCI controllers
213 * lie at lower PCI addresses than the EHCI controller, so they will be
214 * discovered (and hence resumed) first. But there is no guarantee things
215 * will always work this way. If the EHCI controller is resumed first and
216 * the OHCI ports are unpowered, then the handover will fail.
218 static void prepare_for_handover(struct usb_hcd *hcd)
220 struct ohci_hcd *ohci = hcd_to_ohci(hcd);
223 /* Here we "know" root ports should always stay powered */
224 ohci_dbg(ohci, "powerup ports\n");
225 for (port = 0; port < ohci->num_ports; port++)
226 ohci_writel(ohci, RH_PS_PPS,
227 &ohci->regs->roothub.portstatus[port]);
229 /* Flush those writes */
230 ohci_readl(ohci, &ohci->regs->control);
236 static inline void prepare_for_handover(struct usb_hcd *hcd)
239 #endif /* CONFIG_USB_PERSIST etc. */
243 static int ohci_pci_suspend (struct usb_hcd *hcd, pm_message_t message)
245 struct ohci_hcd *ohci = hcd_to_ohci (hcd);
249 /* Root hub was already suspended. Disable irq emission and
250 * mark HW unaccessible, bail out if RH has been resumed. Use
251 * the spinlock to properly synchronize with possible pending
252 * RH suspend or resume activity.
254 * This is still racy as hcd->state is manipulated outside of
255 * any locks =P But that will be a different fix.
257 spin_lock_irqsave (&ohci->lock, flags);
258 if (hcd->state != HC_STATE_SUSPENDED) {
262 ohci_writel(ohci, OHCI_INTR_MIE, &ohci->regs->intrdisable);
263 (void)ohci_readl(ohci, &ohci->regs->intrdisable);
265 /* make sure snapshot being resumed re-enumerates everything */
266 if (message.event == PM_EVENT_PRETHAW)
267 ohci_usb_reset(ohci);
269 clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
271 spin_unlock_irqrestore (&ohci->lock, flags);
277 static int ohci_pci_resume (struct usb_hcd *hcd)
279 set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
281 /* FIXME: we should try to detect loss of VBUS power here */
282 prepare_for_handover(hcd);
287 #endif /* CONFIG_PM */
290 /*-------------------------------------------------------------------------*/
292 static const struct hc_driver ohci_pci_hc_driver = {
293 .description = hcd_name,
294 .product_desc = "OHCI Host Controller",
295 .hcd_priv_size = sizeof(struct ohci_hcd),
298 * generic hardware linkage
301 .flags = HCD_MEMORY | HCD_USB11,
304 * basic lifecycle operations
306 .reset = ohci_pci_reset,
307 .start = ohci_pci_start,
309 .shutdown = ohci_shutdown,
312 /* these suspend/resume entries are for upstream PCI glue ONLY */
313 .suspend = ohci_pci_suspend,
314 .resume = ohci_pci_resume,
318 * managing i/o requests and associated device resources
320 .urb_enqueue = ohci_urb_enqueue,
321 .urb_dequeue = ohci_urb_dequeue,
322 .endpoint_disable = ohci_endpoint_disable,
327 .get_frame_number = ohci_get_frame,
332 .hub_status_data = ohci_hub_status_data,
333 .hub_control = ohci_hub_control,
334 .hub_irq_enable = ohci_rhsc_enable,
336 .bus_suspend = ohci_bus_suspend,
337 .bus_resume = ohci_bus_resume,
339 .start_port_reset = ohci_start_port_reset,
342 /*-------------------------------------------------------------------------*/
345 static const struct pci_device_id pci_ids [] = { {
346 /* handle any USB OHCI controller */
347 PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_USB_OHCI, ~0),
348 .driver_data = (unsigned long) &ohci_pci_hc_driver,
349 }, { /* end: all zeroes */ }
351 MODULE_DEVICE_TABLE (pci, pci_ids);
353 /* pci driver glue; this is a "new style" PCI driver module */
354 static struct pci_driver ohci_pci_driver = {
355 .name = (char *) hcd_name,
358 .probe = usb_hcd_pci_probe,
359 .remove = usb_hcd_pci_remove,
362 .suspend = usb_hcd_pci_suspend,
363 .resume = usb_hcd_pci_resume,
366 .shutdown = usb_hcd_pci_shutdown,