2 * Universal Host Controller Interface driver for USB.
4 * Maintainer: Alan Stern <stern@rowland.harvard.edu>
6 * (C) Copyright 1999 Linus Torvalds
7 * (C) Copyright 1999-2002 Johannes Erdfelt, johannes@erdfelt.com
8 * (C) Copyright 1999 Randy Dunlap
9 * (C) Copyright 1999 Georg Acher, acher@in.tum.de
10 * (C) Copyright 1999 Deti Fliegl, deti@fliegl.de
11 * (C) Copyright 1999 Thomas Sailer, sailer@ife.ee.ethz.ch
12 * (C) Copyright 1999 Roman Weissgaerber, weissg@vienna.at
13 * (C) Copyright 2000 Yggdrasil Computing, Inc. (port of new PCI interface
14 * support from usb-ohci.c by Adam Richter, adam@yggdrasil.com).
15 * (C) Copyright 1999 Gregory P. Smith (from usb-ohci.c)
16 * (C) Copyright 2004-2005 Alan Stern, stern@rowland.harvard.edu
18 * Intel documents this fairly well, and as far as I know there
19 * are no royalties or anything like that, but even so there are
20 * people who decided that they want to do the same thing in a
21 * completely different way.
25 #include <linux/config.h>
26 #include <linux/module.h>
27 #include <linux/pci.h>
28 #include <linux/kernel.h>
29 #include <linux/init.h>
30 #include <linux/delay.h>
31 #include <linux/ioport.h>
32 #include <linux/sched.h>
33 #include <linux/slab.h>
34 #include <linux/smp_lock.h>
35 #include <linux/errno.h>
36 #include <linux/unistd.h>
37 #include <linux/interrupt.h>
38 #include <linux/spinlock.h>
39 #include <linux/debugfs.h>
41 #include <linux/dmapool.h>
42 #include <linux/dma-mapping.h>
43 #include <linux/usb.h>
44 #include <linux/bitops.h>
46 #include <asm/uaccess.h>
49 #include <asm/system.h>
51 #include "../core/hcd.h"
53 #include "pci-quirks.h"
58 #define DRIVER_VERSION "v3.0"
59 #define DRIVER_AUTHOR "Linus 'Frodo Rabbit' Torvalds, Johannes Erdfelt, \
60 Randy Dunlap, Georg Acher, Deti Fliegl, Thomas Sailer, Roman Weissgaerber, \
62 #define DRIVER_DESC "USB Universal Host Controller Interface driver"
65 * debug = 0, no debugging messages
66 * debug = 1, dump failed URBs except for stalls
67 * debug = 2, dump all failed URBs (including stalls)
68 * show all queues in /debug/uhci/[pci_addr]
69 * debug = 3, show all TDs in URBs when dumping
72 #define DEBUG_CONFIGURED 1
74 module_param(debug, int, S_IRUGO | S_IWUSR);
75 MODULE_PARM_DESC(debug, "Debug level");
78 #define DEBUG_CONFIGURED 0
83 #define ERRBUF_LEN (32 * 1024)
85 static kmem_cache_t *uhci_up_cachep; /* urb_priv */
87 static void suspend_rh(struct uhci_hcd *uhci, enum uhci_rh_state new_state);
88 static void wakeup_rh(struct uhci_hcd *uhci);
89 static void uhci_get_current_frame_number(struct uhci_hcd *uhci);
91 /* If a transfer is still active after this much time, turn off FSBR */
92 #define IDLE_TIMEOUT msecs_to_jiffies(50)
93 #define FSBR_DELAY msecs_to_jiffies(50)
95 /* When we timeout an idle transfer for FSBR, we'll switch it over to */
96 /* depth first traversal. We'll do it in groups of this number of TDs */
97 /* to make sure it doesn't hog all of the bandwidth */
98 #define DEPTH_INTERVAL 5
100 #include "uhci-debug.c"
102 #include "uhci-hub.c"
105 * Finish up a host controller reset and update the recorded state.
107 static void finish_reset(struct uhci_hcd *uhci)
111 /* HCRESET doesn't affect the Suspend, Reset, and Resume Detect
112 * bits in the port status and control registers.
113 * We have to clear them by hand.
115 for (port = 0; port < uhci->rh_numports; ++port)
116 outw(0, uhci->io_addr + USBPORTSC1 + (port * 2));
118 uhci->port_c_suspend = uhci->suspended_ports =
119 uhci->resuming_ports = 0;
120 uhci->rh_state = UHCI_RH_RESET;
121 uhci->is_stopped = UHCI_IS_STOPPED;
122 uhci_to_hcd(uhci)->state = HC_STATE_HALT;
123 uhci_to_hcd(uhci)->poll_rh = 0;
127 * Last rites for a defunct/nonfunctional controller
128 * or one we don't want to use any more.
130 static void hc_died(struct uhci_hcd *uhci)
132 uhci_reset_hc(to_pci_dev(uhci_dev(uhci)), uhci->io_addr);
134 uhci->hc_inaccessible = 1;
138 * Initialize a controller that was newly discovered or has just been
139 * resumed. In either case we can't be sure of its previous state.
141 static void check_and_reset_hc(struct uhci_hcd *uhci)
143 if (uhci_check_and_reset_hc(to_pci_dev(uhci_dev(uhci)), uhci->io_addr))
148 * Store the basic register settings needed by the controller.
150 static void configure_hc(struct uhci_hcd *uhci)
152 /* Set the frame length to the default: 1 ms exactly */
153 outb(USBSOF_DEFAULT, uhci->io_addr + USBSOF);
155 /* Store the frame list base address */
156 outl(uhci->frame_dma_handle, uhci->io_addr + USBFLBASEADD);
158 /* Set the current frame number */
159 outw(uhci->frame_number, uhci->io_addr + USBFRNUM);
161 /* Mark controller as not halted before we enable interrupts */
162 uhci_to_hcd(uhci)->state = HC_STATE_SUSPENDED;
166 pci_write_config_word(to_pci_dev(uhci_dev(uhci)), USBLEGSUP,
171 static int resume_detect_interrupts_are_broken(struct uhci_hcd *uhci)
175 switch (to_pci_dev(uhci_dev(uhci))->vendor) {
179 case PCI_VENDOR_ID_GENESYS:
180 /* Genesys Logic's GL880S controllers don't generate
181 * resume-detect interrupts.
185 case PCI_VENDOR_ID_INTEL:
186 /* Some of Intel's USB controllers have a bug that causes
187 * resume-detect interrupts if any port has an over-current
188 * condition. To make matters worse, some motherboards
189 * hardwire unused USB ports' over-current inputs active!
190 * To prevent problems, we will not enable resume-detect
191 * interrupts if any ports are OC.
193 for (port = 0; port < uhci->rh_numports; ++port) {
194 if (inw(uhci->io_addr + USBPORTSC1 + port * 2) &
203 static void suspend_rh(struct uhci_hcd *uhci, enum uhci_rh_state new_state)
204 __releases(uhci->lock)
205 __acquires(uhci->lock)
210 auto_stop = (new_state == UHCI_RH_AUTO_STOPPED);
211 dev_dbg(uhci_dev(uhci), "%s%s\n", __FUNCTION__,
212 (auto_stop ? " (auto-stop)" : ""));
214 /* If we get a suspend request when we're already auto-stopped
215 * then there's nothing to do.
217 if (uhci->rh_state == UHCI_RH_AUTO_STOPPED) {
218 uhci->rh_state = new_state;
222 /* Enable resume-detect interrupts if they work.
223 * Then enter Global Suspend mode, still configured.
225 uhci->working_RD = 1;
226 int_enable = USBINTR_RESUME;
227 if (resume_detect_interrupts_are_broken(uhci)) {
228 uhci->working_RD = int_enable = 0;
230 outw(int_enable, uhci->io_addr + USBINTR);
231 outw(USBCMD_EGSM | USBCMD_CF, uhci->io_addr + USBCMD);
235 /* If we're auto-stopping then no devices have been attached
236 * for a while, so there shouldn't be any active URBs and the
237 * controller should stop after a few microseconds. Otherwise
238 * we will give the controller one frame to stop.
240 if (!auto_stop && !(inw(uhci->io_addr + USBSTS) & USBSTS_HCH)) {
241 uhci->rh_state = UHCI_RH_SUSPENDING;
242 spin_unlock_irq(&uhci->lock);
244 spin_lock_irq(&uhci->lock);
245 if (uhci->hc_inaccessible) /* Died */
248 if (!(inw(uhci->io_addr + USBSTS) & USBSTS_HCH))
249 dev_warn(uhci_dev(uhci), "Controller not stopped yet!\n");
251 uhci_get_current_frame_number(uhci);
254 uhci->rh_state = new_state;
255 uhci->is_stopped = UHCI_IS_STOPPED;
256 uhci_to_hcd(uhci)->poll_rh = !int_enable;
258 uhci_scan_schedule(uhci, NULL);
261 static void start_rh(struct uhci_hcd *uhci)
263 uhci_to_hcd(uhci)->state = HC_STATE_RUNNING;
264 uhci->is_stopped = 0;
267 /* Mark it configured and running with a 64-byte max packet.
268 * All interrupts are enabled, even though RESUME won't do anything.
270 outw(USBCMD_RS | USBCMD_CF | USBCMD_MAXP, uhci->io_addr + USBCMD);
271 outw(USBINTR_TIMEOUT | USBINTR_RESUME | USBINTR_IOC | USBINTR_SP,
272 uhci->io_addr + USBINTR);
274 uhci->rh_state = UHCI_RH_RUNNING;
275 uhci_to_hcd(uhci)->poll_rh = 1;
278 static void wakeup_rh(struct uhci_hcd *uhci)
279 __releases(uhci->lock)
280 __acquires(uhci->lock)
282 dev_dbg(uhci_dev(uhci), "%s%s\n", __FUNCTION__,
283 uhci->rh_state == UHCI_RH_AUTO_STOPPED ?
284 " (auto-start)" : "");
286 /* If we are auto-stopped then no devices are attached so there's
287 * no need for wakeup signals. Otherwise we send Global Resume
290 if (uhci->rh_state == UHCI_RH_SUSPENDED) {
291 uhci->rh_state = UHCI_RH_RESUMING;
292 outw(USBCMD_FGR | USBCMD_EGSM | USBCMD_CF,
293 uhci->io_addr + USBCMD);
294 spin_unlock_irq(&uhci->lock);
296 spin_lock_irq(&uhci->lock);
297 if (uhci->hc_inaccessible) /* Died */
300 /* End Global Resume and wait for EOP to be sent */
301 outw(USBCMD_CF, uhci->io_addr + USBCMD);
304 if (inw(uhci->io_addr + USBCMD) & USBCMD_FGR)
305 dev_warn(uhci_dev(uhci), "FGR not stopped yet!\n");
310 /* Restart root hub polling */
311 mod_timer(&uhci_to_hcd(uhci)->rh_timer, jiffies);
314 static irqreturn_t uhci_irq(struct usb_hcd *hcd, struct pt_regs *regs)
316 struct uhci_hcd *uhci = hcd_to_uhci(hcd);
317 unsigned short status;
321 * Read the interrupt status, and write it back to clear the
322 * interrupt cause. Contrary to the UHCI specification, the
323 * "HC Halted" status bit is persistent: it is RO, not R/WC.
325 status = inw(uhci->io_addr + USBSTS);
326 if (!(status & ~USBSTS_HCH)) /* shared interrupt, not mine */
328 outw(status, uhci->io_addr + USBSTS); /* Clear it */
330 if (status & ~(USBSTS_USBINT | USBSTS_ERROR | USBSTS_RD)) {
331 if (status & USBSTS_HSE)
332 dev_err(uhci_dev(uhci), "host system error, "
334 if (status & USBSTS_HCPE)
335 dev_err(uhci_dev(uhci), "host controller process "
336 "error, something bad happened!\n");
337 if (status & USBSTS_HCH) {
338 spin_lock_irqsave(&uhci->lock, flags);
339 if (uhci->rh_state >= UHCI_RH_RUNNING) {
340 dev_err(uhci_dev(uhci),
341 "host controller halted, "
343 if (debug > 1 && errbuf) {
344 /* Print the schedule for debugging */
345 uhci_sprint_schedule(uhci,
351 /* Force a callback in case there are
353 mod_timer(&hcd->rh_timer, jiffies);
355 spin_unlock_irqrestore(&uhci->lock, flags);
359 if (status & USBSTS_RD)
360 usb_hcd_poll_rh_status(hcd);
362 spin_lock_irqsave(&uhci->lock, flags);
363 uhci_scan_schedule(uhci, regs);
364 spin_unlock_irqrestore(&uhci->lock, flags);
371 * Store the current frame number in uhci->frame_number if the controller
374 static void uhci_get_current_frame_number(struct uhci_hcd *uhci)
376 if (!uhci->is_stopped)
377 uhci->frame_number = inw(uhci->io_addr + USBFRNUM);
381 * De-allocate all resources
383 static void release_uhci(struct uhci_hcd *uhci)
387 if (DEBUG_CONFIGURED) {
388 spin_lock_irq(&uhci->lock);
389 uhci->is_initialized = 0;
390 spin_unlock_irq(&uhci->lock);
392 debugfs_remove(uhci->dentry);
395 for (i = 0; i < UHCI_NUM_SKELQH; i++)
396 uhci_free_qh(uhci, uhci->skelqh[i]);
398 uhci_free_td(uhci, uhci->term_td);
400 dma_pool_destroy(uhci->qh_pool);
402 dma_pool_destroy(uhci->td_pool);
404 kfree(uhci->frame_cpu);
406 dma_free_coherent(uhci_dev(uhci),
407 UHCI_NUMFRAMES * sizeof(*uhci->frame),
408 uhci->frame, uhci->frame_dma_handle);
411 static int uhci_reset(struct usb_hcd *hcd)
413 struct uhci_hcd *uhci = hcd_to_uhci(hcd);
414 unsigned io_size = (unsigned) hcd->rsrc_len;
417 uhci->io_addr = (unsigned long) hcd->rsrc_start;
419 /* The UHCI spec says devices must have 2 ports, and goes on to say
420 * they may have more but gives no way to determine how many there
421 * are. However according to the UHCI spec, Bit 7 of the port
422 * status and control register is always set to 1. So we try to
423 * use this to our advantage. Another common failure mode when
424 * a nonexistent register is addressed is to return all ones, so
425 * we test for that also.
427 for (port = 0; port < (io_size - USBPORTSC1) / 2; port++) {
428 unsigned int portstatus;
430 portstatus = inw(uhci->io_addr + USBPORTSC1 + (port * 2));
431 if (!(portstatus & 0x0080) || portstatus == 0xffff)
435 dev_info(uhci_dev(uhci), "detected %d ports\n", port);
437 /* Anything greater than 7 is weird so we'll ignore it. */
438 if (port > UHCI_RH_MAXCHILD) {
439 dev_info(uhci_dev(uhci), "port count misdetected? "
440 "forcing to 2 ports\n");
443 uhci->rh_numports = port;
445 /* Kick BIOS off this hardware and reset if the controller
446 * isn't already safely quiescent.
448 check_and_reset_hc(uhci);
452 /* Make sure the controller is quiescent and that we're not using it
453 * any more. This is mainly for the benefit of programs which, like kexec,
454 * expect the hardware to be idle: not doing DMA or generating IRQs.
456 * This routine may be called in a damaged or failing kernel. Hence we
457 * do not acquire the spinlock before shutting down the controller.
459 static void uhci_shutdown(struct pci_dev *pdev)
461 struct usb_hcd *hcd = (struct usb_hcd *) pci_get_drvdata(pdev);
463 hc_died(hcd_to_uhci(hcd));
467 * Allocate a frame list, and then setup the skeleton
469 * The hardware doesn't really know any difference
470 * in the queues, but the order does matter for the
471 * protocols higher up. The order is:
473 * - any isochronous events handled before any
474 * of the queues. We don't do that here, because
475 * we'll create the actual TD entries on demand.
476 * - The first queue is the interrupt queue.
477 * - The second queue is the control queue, split into low- and full-speed
478 * - The third queue is bulk queue.
479 * - The fourth queue is the bandwidth reclamation queue, which loops back
480 * to the full-speed control queue.
482 static int uhci_start(struct usb_hcd *hcd)
484 struct uhci_hcd *uhci = hcd_to_uhci(hcd);
487 struct dentry *dentry;
489 hcd->uses_new_polling = 1;
492 uhci->fsbrtimeout = 0;
494 spin_lock_init(&uhci->lock);
496 INIT_LIST_HEAD(&uhci->td_remove_list);
497 INIT_LIST_HEAD(&uhci->idle_qh_list);
499 init_waitqueue_head(&uhci->waitqh);
501 if (DEBUG_CONFIGURED) {
502 dentry = debugfs_create_file(hcd->self.bus_name,
503 S_IFREG|S_IRUGO|S_IWUSR, uhci_debugfs_root,
504 uhci, &uhci_debug_operations);
506 dev_err(uhci_dev(uhci), "couldn't create uhci "
509 goto err_create_debug_entry;
511 uhci->dentry = dentry;
514 uhci->frame = dma_alloc_coherent(uhci_dev(uhci),
515 UHCI_NUMFRAMES * sizeof(*uhci->frame),
516 &uhci->frame_dma_handle, 0);
518 dev_err(uhci_dev(uhci), "unable to allocate "
519 "consistent memory for frame list\n");
520 goto err_alloc_frame;
522 memset(uhci->frame, 0, UHCI_NUMFRAMES * sizeof(*uhci->frame));
524 uhci->frame_cpu = kcalloc(UHCI_NUMFRAMES, sizeof(*uhci->frame_cpu),
526 if (!uhci->frame_cpu) {
527 dev_err(uhci_dev(uhci), "unable to allocate "
528 "memory for frame pointers\n");
529 goto err_alloc_frame_cpu;
532 uhci->td_pool = dma_pool_create("uhci_td", uhci_dev(uhci),
533 sizeof(struct uhci_td), 16, 0);
534 if (!uhci->td_pool) {
535 dev_err(uhci_dev(uhci), "unable to create td dma_pool\n");
536 goto err_create_td_pool;
539 uhci->qh_pool = dma_pool_create("uhci_qh", uhci_dev(uhci),
540 sizeof(struct uhci_qh), 16, 0);
541 if (!uhci->qh_pool) {
542 dev_err(uhci_dev(uhci), "unable to create qh dma_pool\n");
543 goto err_create_qh_pool;
546 uhci->term_td = uhci_alloc_td(uhci);
547 if (!uhci->term_td) {
548 dev_err(uhci_dev(uhci), "unable to allocate terminating TD\n");
549 goto err_alloc_term_td;
552 for (i = 0; i < UHCI_NUM_SKELQH; i++) {
553 uhci->skelqh[i] = uhci_alloc_qh(uhci, NULL, NULL);
554 if (!uhci->skelqh[i]) {
555 dev_err(uhci_dev(uhci), "unable to allocate QH\n");
556 goto err_alloc_skelqh;
561 * 8 Interrupt queues; link all higher int queues to int1,
562 * then link int1 to control and control to bulk
564 uhci->skel_int128_qh->link =
565 uhci->skel_int64_qh->link =
566 uhci->skel_int32_qh->link =
567 uhci->skel_int16_qh->link =
568 uhci->skel_int8_qh->link =
569 uhci->skel_int4_qh->link =
570 uhci->skel_int2_qh->link = UHCI_PTR_QH |
571 cpu_to_le32(uhci->skel_int1_qh->dma_handle);
573 uhci->skel_int1_qh->link = UHCI_PTR_QH |
574 cpu_to_le32(uhci->skel_ls_control_qh->dma_handle);
575 uhci->skel_ls_control_qh->link = UHCI_PTR_QH |
576 cpu_to_le32(uhci->skel_fs_control_qh->dma_handle);
577 uhci->skel_fs_control_qh->link = UHCI_PTR_QH |
578 cpu_to_le32(uhci->skel_bulk_qh->dma_handle);
579 uhci->skel_bulk_qh->link = UHCI_PTR_QH |
580 cpu_to_le32(uhci->skel_term_qh->dma_handle);
582 /* This dummy TD is to work around a bug in Intel PIIX controllers */
583 uhci_fill_td(uhci->term_td, 0, uhci_explen(0) |
584 (0x7f << TD_TOKEN_DEVADDR_SHIFT) | USB_PID_IN, 0);
585 uhci->term_td->link = cpu_to_le32(uhci->term_td->dma_handle);
587 uhci->skel_term_qh->link = UHCI_PTR_TERM;
588 uhci->skel_term_qh->element = cpu_to_le32(uhci->term_td->dma_handle);
591 * Fill the frame list: make all entries point to the proper
594 * The interrupt queues will be interleaved as evenly as possible.
595 * There's not much to be done about period-1 interrupts; they have
596 * to occur in every frame. But we can schedule period-2 interrupts
597 * in odd-numbered frames, period-4 interrupts in frames congruent
598 * to 2 (mod 4), and so on. This way each frame only has two
599 * interrupt QHs, which will help spread out bandwidth utilization.
601 for (i = 0; i < UHCI_NUMFRAMES; i++) {
605 * ffs (Find First bit Set) does exactly what we need:
606 * 1,3,5,... => ffs = 0 => use skel_int2_qh = skelqh[8],
607 * 2,6,10,... => ffs = 1 => use skel_int4_qh = skelqh[7], etc.
608 * ffs >= 7 => not on any high-period queue, so use
609 * skel_int1_qh = skelqh[9].
610 * Add UHCI_NUMFRAMES to insure at least one bit is set.
612 irq = 8 - (int) __ffs(i + UHCI_NUMFRAMES);
616 /* Only place we don't use the frame list routines */
617 uhci->frame[i] = UHCI_PTR_QH |
618 cpu_to_le32(uhci->skelqh[irq]->dma_handle);
622 * Some architectures require a full mb() to enforce completion of
623 * the memory writes above before the I/O transfers in configure_hc().
628 uhci->is_initialized = 1;
636 for (i = 0; i < UHCI_NUM_SKELQH; i++) {
638 uhci_free_qh(uhci, uhci->skelqh[i]);
641 uhci_free_td(uhci, uhci->term_td);
644 dma_pool_destroy(uhci->qh_pool);
647 dma_pool_destroy(uhci->td_pool);
650 kfree(uhci->frame_cpu);
653 dma_free_coherent(uhci_dev(uhci),
654 UHCI_NUMFRAMES * sizeof(*uhci->frame),
655 uhci->frame, uhci->frame_dma_handle);
658 debugfs_remove(uhci->dentry);
660 err_create_debug_entry:
664 static void uhci_stop(struct usb_hcd *hcd)
666 struct uhci_hcd *uhci = hcd_to_uhci(hcd);
668 spin_lock_irq(&uhci->lock);
669 if (!uhci->hc_inaccessible)
671 uhci_scan_schedule(uhci, NULL);
672 spin_unlock_irq(&uhci->lock);
678 static int uhci_rh_suspend(struct usb_hcd *hcd)
680 struct uhci_hcd *uhci = hcd_to_uhci(hcd);
682 spin_lock_irq(&uhci->lock);
683 if (!uhci->hc_inaccessible) /* Not dead */
684 suspend_rh(uhci, UHCI_RH_SUSPENDED);
685 spin_unlock_irq(&uhci->lock);
689 static int uhci_rh_resume(struct usb_hcd *hcd)
691 struct uhci_hcd *uhci = hcd_to_uhci(hcd);
694 spin_lock_irq(&uhci->lock);
695 if (uhci->hc_inaccessible) {
696 if (uhci->rh_state == UHCI_RH_SUSPENDED) {
697 dev_warn(uhci_dev(uhci), "HC isn't running!\n");
700 /* Otherwise the HC is dead */
703 spin_unlock_irq(&uhci->lock);
707 static int uhci_suspend(struct usb_hcd *hcd, pm_message_t message)
709 struct uhci_hcd *uhci = hcd_to_uhci(hcd);
712 dev_dbg(uhci_dev(uhci), "%s\n", __FUNCTION__);
714 spin_lock_irq(&uhci->lock);
715 if (uhci->hc_inaccessible) /* Dead or already suspended */
718 if (uhci->rh_state > UHCI_RH_SUSPENDED) {
719 dev_warn(uhci_dev(uhci), "Root hub isn't suspended!\n");
724 /* All PCI host controllers are required to disable IRQ generation
725 * at the source, so we must turn off PIRQ.
727 pci_write_config_word(to_pci_dev(uhci_dev(uhci)), USBLEGSUP, 0);
729 clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
730 uhci->hc_inaccessible = 1;
733 /* FIXME: Enable non-PME# remote wakeup? */
736 spin_unlock_irq(&uhci->lock);
740 static int uhci_resume(struct usb_hcd *hcd)
742 struct uhci_hcd *uhci = hcd_to_uhci(hcd);
744 dev_dbg(uhci_dev(uhci), "%s\n", __FUNCTION__);
746 /* Since we aren't in D3 any more, it's safe to set this flag
747 * even if the controller was dead. It might not even be dead
748 * any more, if the firmware or quirks code has reset it.
750 set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
753 if (uhci->rh_state == UHCI_RH_RESET) /* Dead */
755 spin_lock_irq(&uhci->lock);
757 /* FIXME: Disable non-PME# remote wakeup? */
759 uhci->hc_inaccessible = 0;
761 /* The BIOS may have changed the controller settings during a
762 * system wakeup. Check it and reconfigure to avoid problems.
764 check_and_reset_hc(uhci);
767 if (uhci->rh_state == UHCI_RH_RESET) {
769 /* The controller had to be reset */
770 usb_root_hub_lost_power(hcd->self.root_hub);
771 suspend_rh(uhci, UHCI_RH_SUSPENDED);
774 spin_unlock_irq(&uhci->lock);
776 if (!uhci->working_RD) {
777 /* Suspended root hub needs to be polled */
779 usb_hcd_poll_rh_status(hcd);
785 /* Wait until a particular device/endpoint's QH is idle, and free it */
786 static void uhci_hcd_endpoint_disable(struct usb_hcd *hcd,
787 struct usb_host_endpoint *hep)
789 struct uhci_hcd *uhci = hcd_to_uhci(hcd);
792 spin_lock_irq(&uhci->lock);
793 qh = (struct uhci_qh *) hep->hcpriv;
797 while (qh->state != QH_STATE_IDLE) {
799 spin_unlock_irq(&uhci->lock);
800 wait_event_interruptible(uhci->waitqh,
801 qh->state == QH_STATE_IDLE);
802 spin_lock_irq(&uhci->lock);
806 uhci_free_qh(uhci, qh);
808 spin_unlock_irq(&uhci->lock);
811 static int uhci_hcd_get_frame_number(struct usb_hcd *hcd)
813 struct uhci_hcd *uhci = hcd_to_uhci(hcd);
818 /* Minimize latency by avoiding the spinlock */
819 local_irq_save(flags);
820 is_stopped = uhci->is_stopped;
822 frame_number = (is_stopped ? uhci->frame_number :
823 inw(uhci->io_addr + USBFRNUM));
824 local_irq_restore(flags);
828 static const char hcd_name[] = "uhci_hcd";
830 static const struct hc_driver uhci_driver = {
831 .description = hcd_name,
832 .product_desc = "UHCI Host Controller",
833 .hcd_priv_size = sizeof(struct uhci_hcd),
835 /* Generic hardware linkage */
839 /* Basic lifecycle operations */
843 .suspend = uhci_suspend,
844 .resume = uhci_resume,
845 .bus_suspend = uhci_rh_suspend,
846 .bus_resume = uhci_rh_resume,
850 .urb_enqueue = uhci_urb_enqueue,
851 .urb_dequeue = uhci_urb_dequeue,
853 .endpoint_disable = uhci_hcd_endpoint_disable,
854 .get_frame_number = uhci_hcd_get_frame_number,
856 .hub_status_data = uhci_hub_status_data,
857 .hub_control = uhci_hub_control,
860 static const struct pci_device_id uhci_pci_ids[] = { {
861 /* handle any USB UHCI controller */
862 PCI_DEVICE_CLASS(((PCI_CLASS_SERIAL_USB << 8) | 0x00), ~0),
863 .driver_data = (unsigned long) &uhci_driver,
864 }, { /* end: all zeroes */ }
867 MODULE_DEVICE_TABLE(pci, uhci_pci_ids);
869 static struct pci_driver uhci_pci_driver = {
870 .name = (char *)hcd_name,
871 .id_table = uhci_pci_ids,
873 .probe = usb_hcd_pci_probe,
874 .remove = usb_hcd_pci_remove,
875 .shutdown = uhci_shutdown,
878 .suspend = usb_hcd_pci_suspend,
879 .resume = usb_hcd_pci_resume,
883 static int __init uhci_hcd_init(void)
885 int retval = -ENOMEM;
887 printk(KERN_INFO DRIVER_DESC " " DRIVER_VERSION "\n");
892 if (DEBUG_CONFIGURED) {
893 errbuf = kmalloc(ERRBUF_LEN, GFP_KERNEL);
896 uhci_debugfs_root = debugfs_create_dir("uhci", NULL);
897 if (!uhci_debugfs_root)
901 uhci_up_cachep = kmem_cache_create("uhci_urb_priv",
902 sizeof(struct urb_priv), 0, 0, NULL, NULL);
906 retval = pci_register_driver(&uhci_pci_driver);
913 if (kmem_cache_destroy(uhci_up_cachep))
914 warn("not all urb_privs were freed!");
917 debugfs_remove(uhci_debugfs_root);
927 static void __exit uhci_hcd_cleanup(void)
929 pci_unregister_driver(&uhci_pci_driver);
931 if (kmem_cache_destroy(uhci_up_cachep))
932 warn("not all urb_privs were freed!");
934 debugfs_remove(uhci_debugfs_root);
938 module_init(uhci_hcd_init);
939 module_exit(uhci_hcd_cleanup);
941 MODULE_AUTHOR(DRIVER_AUTHOR);
942 MODULE_DESCRIPTION(DRIVER_DESC);
943 MODULE_LICENSE("GPL");