1 /******************************************************************
2 * Copyright 2005 Mentor Graphics Corporation
3 * Copyright (C) 2005-2006 by Texas Instruments
5 * This file is part of the Inventra Controller Driver for Linux.
7 * The Inventra Controller Driver for Linux is free software; you
8 * can redistribute it and/or modify it under the terms of the GNU
9 * General Public License version 2 as published by the Free Software
12 * The Inventra Controller Driver for Linux is distributed in
13 * the hope that it will be useful, but WITHOUT ANY WARRANTY;
14 * without even the implied warranty of MERCHANTABILITY or
15 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
16 * License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with The Inventra Controller Driver for Linux ; if not,
20 * write to the Free Software Foundation, Inc., 59 Temple Place,
21 * Suite 330, Boston, MA 02111-1307 USA
23 * ANY DOWNLOAD, USE, REPRODUCTION, MODIFICATION OR DISTRIBUTION
24 * OF THIS DRIVER INDICATES YOUR COMPLETE AND UNCONDITIONAL ACCEPTANCE
25 * OF THOSE TERMS.THIS DRIVER IS PROVIDED "AS IS" AND MENTOR GRAPHICS
26 * MAKES NO WARRANTIES, EXPRESS OR IMPLIED, RELATED TO THIS DRIVER.
27 * MENTOR GRAPHICS SPECIFICALLY DISCLAIMS ALL IMPLIED WARRANTIES
28 * OF MERCHANTABILITY; FITNESS FOR A PARTICULAR PURPOSE AND
29 * NON-INFRINGEMENT. MENTOR GRAPHICS DOES NOT PROVIDE SUPPORT
30 * SERVICES OR UPDATES FOR THIS DRIVER, EVEN IF YOU ARE A MENTOR
31 * GRAPHICS SUPPORT CUSTOMER.
32 ******************************************************************/
34 #include <linux/kernel.h>
35 #include <linux/list.h>
36 #include <linux/timer.h>
37 #include <linux/spinlock.h>
38 #include <linux/init.h>
39 #include <linux/device.h>
40 #include <linux/interrupt.h>
44 /* ep0 is always musb->aLocalEnd[0].ep_in */
45 #define next_ep0_request(musb) next_in_request(&(musb)->aLocalEnd[0])
48 * Locking note: we use only the controller lock, for simpler correctness.
49 * It's always held with IRQs blocked.
51 * It protects the ep0 request queue as well as ep0_state, not just the
52 * controller and indexed registers. And that lock stays held unless it
53 * needs to be dropped to allow reentering this driver ... like upcalls to
54 * the gadget driver, or adjusting endpoint halt status.
57 static char *decode_ep0stage(u8 stage)
60 case MGC_END0_STAGE_SETUP: return "idle";
61 case MGC_END0_STAGE_TX: return "in";
62 case MGC_END0_STAGE_RX: return "out";
63 case MGC_END0_STAGE_ACKWAIT: return "wait";
64 case MGC_END0_STAGE_STATUSIN: return "in/status";
65 case MGC_END0_STAGE_STATUSOUT: return "out/status";
70 /* handle a standard GET_STATUS request
71 * Context: caller holds controller lock
73 static int service_tx_status_request(
75 const struct usb_ctrlrequest *pControlRequest)
77 void __iomem *pBase = pThis->pRegs;
79 u8 bResult[2], bEnd = 0;
80 const u8 bRecip = pControlRequest->bRequestType & USB_RECIP_MASK;
85 case USB_RECIP_DEVICE:
86 bResult[0] = pThis->bIsSelfPowered << USB_DEVICE_SELF_POWERED;
87 bResult[0] |= pThis->bMayWakeup << USB_DEVICE_REMOTE_WAKEUP;
88 #ifdef CONFIG_USB_MUSB_OTG
89 if (pThis->g.is_otg) {
90 bResult[0] |= pThis->g.b_hnp_enable
91 << USB_DEVICE_B_HNP_ENABLE;
92 bResult[0] |= pThis->g.a_alt_hnp_support
93 << USB_DEVICE_A_ALT_HNP_SUPPORT;
94 bResult[0] |= pThis->g.a_hnp_support
95 << USB_DEVICE_A_HNP_SUPPORT;
100 case USB_RECIP_INTERFACE:
104 case USB_RECIP_ENDPOINT: {
110 bEnd = (u8) pControlRequest->wIndex;
116 is_in = bEnd & USB_DIR_IN;
119 ep = &pThis->aLocalEnd[bEnd].ep_in;
121 ep = &pThis->aLocalEnd[bEnd].ep_out;
123 regs = pThis->aLocalEnd[bEnd].regs;
125 if (bEnd >= MUSB_C_NUM_EPS || !ep->desc) {
130 MGC_SelectEnd(pBase, bEnd);
132 tmp = musb_readw(regs, MGC_O_HDRC_TXCSR)
133 & MGC_M_TXCSR_P_SENDSTALL;
135 tmp = musb_readw(regs, MGC_O_HDRC_RXCSR)
136 & MGC_M_RXCSR_P_SENDSTALL;
137 MGC_SelectEnd(pBase, 0);
139 bResult[0] = tmp ? 1 : 0;
143 /* class, vendor, etc ... delegate */
148 /* fill up the fifo; caller updates csr0 */
150 u16 len = le16_to_cpu(pControlRequest->wLength);
154 musb_write_fifo(&pThis->aLocalEnd[0], len, bResult);
161 * handle a control-IN request, the end0 buffer contains the current request
162 * that is supposed to be a standard control request. Assumes the fifo to
163 * be at least 2 bytes long.
165 * @return 0 if the request was NOT HANDLED,
167 * > 0 when the request is processed
169 * Context: caller holds controller lock
172 service_in_request(struct musb *pThis,
173 const struct usb_ctrlrequest *pControlRequest)
175 int handled = 0; /* not handled */
177 if ((pControlRequest->bRequestType & USB_TYPE_MASK)
178 == USB_TYPE_STANDARD) {
179 switch (pControlRequest->bRequest) {
180 case USB_REQ_GET_STATUS:
181 handled = service_tx_status_request(pThis,
185 /* case USB_REQ_SYNC_FRAME: */
195 * Context: caller holds controller lock
197 static void musb_g_ep0_giveback(struct musb *pThis, struct usb_request *req)
199 pThis->ep0_state = MGC_END0_STAGE_SETUP;
200 musb_g_giveback(&pThis->aLocalEnd[0].ep_in, req, 0);
204 * Handle all control requests with no DATA stage, including standard
206 * USB_REQ_SET_CONFIGURATION, USB_REQ_SET_INTERFACE, unrecognized
207 * always delegated to the gadget driver
208 * USB_REQ_SET_ADDRESS, USB_REQ_CLEAR_FEATURE, USB_REQ_SET_FEATURE
209 * always handled here, except for class/vendor/... features
211 * Context: caller holds controller lock
214 service_zero_data_request(struct musb *pThis,
215 struct usb_ctrlrequest *pControlRequest)
216 __releases(pThis->Lock)
217 __acquires(pThis->Lock)
219 int handled = -EINVAL;
220 void __iomem *pBase = pThis->pRegs;
221 const u8 bRecip = pControlRequest->bRequestType & USB_RECIP_MASK;
223 /* the gadget driver handles everything except what we MUST handle */
224 if ((pControlRequest->bRequestType & USB_TYPE_MASK)
225 == USB_TYPE_STANDARD) {
226 switch (pControlRequest->bRequest) {
227 case USB_REQ_SET_ADDRESS:
228 /* change it after the status stage */
229 pThis->bSetAddress = TRUE;
230 pThis->bAddress = (u8) (pControlRequest->wValue & 0x7f);
234 case USB_REQ_CLEAR_FEATURE:
236 case USB_RECIP_DEVICE:
237 if (pControlRequest->wValue
238 != USB_DEVICE_REMOTE_WAKEUP)
240 pThis->bMayWakeup = 0;
243 case USB_RECIP_INTERFACE:
245 case USB_RECIP_ENDPOINT:{
246 const u8 bEnd = pControlRequest->wIndex & 0x0f;
247 struct musb_ep *pEnd;
250 || bEnd >= MUSB_C_NUM_EPS
251 || pControlRequest->wValue
252 != USB_ENDPOINT_HALT)
255 if (pControlRequest->wIndex & USB_DIR_IN)
256 pEnd = &pThis->aLocalEnd[bEnd].ep_in;
258 pEnd = &pThis->aLocalEnd[bEnd].ep_out;
262 /* REVISIT do it directly, no locking games */
263 spin_unlock(&pThis->Lock);
264 musb_gadget_set_halt(&pEnd->end_point, 0);
265 spin_lock(&pThis->Lock);
267 /* select ep0 again */
268 MGC_SelectEnd(pBase, 0);
272 /* class, vendor, etc ... delegate */
278 case USB_REQ_SET_FEATURE:
280 case USB_RECIP_DEVICE:
282 switch (pControlRequest->wValue) {
283 case USB_DEVICE_REMOTE_WAKEUP:
284 pThis->bMayWakeup = 1;
286 case USB_DEVICE_TEST_MODE:
287 if (pThis->g.speed != USB_SPEED_HIGH)
289 if (pControlRequest->wIndex & 0xff)
292 switch (pControlRequest->wIndex >> 8) {
294 pr_debug("TEST_J\n");
296 pThis->bTestModeValue =
301 pr_debug("TEST_K\n");
302 pThis->bTestModeValue =
307 pr_debug("TEST_SE0_NAK\n");
308 pThis->bTestModeValue =
313 pr_debug("TEST_PACKET\n");
314 pThis->bTestModeValue =
321 /* enter test mode after irq */
323 pThis->bTestMode = TRUE;
325 #ifdef CONFIG_USB_MUSB_OTG
326 case USB_DEVICE_B_HNP_ENABLE:
327 if (!pThis->g.is_otg)
330 pThis->g.b_hnp_enable = 1;
331 devctl = musb_readb(pBase,
333 /* REVISIT after roleswitch, HR will
334 * have been cleared ... reset it
336 musb_writeb(pBase, MGC_O_HDRC_DEVCTL,
337 devctl | MGC_M_DEVCTL_HR);
340 case USB_DEVICE_A_HNP_SUPPORT:
341 if (!pThis->g.is_otg)
343 pThis->g.a_hnp_support = 1;
345 case USB_DEVICE_A_ALT_HNP_SUPPORT:
346 if (!pThis->g.is_otg)
348 pThis->g.a_alt_hnp_support = 1;
358 case USB_RECIP_INTERFACE:
361 case USB_RECIP_ENDPOINT:{
363 pControlRequest->wIndex & 0x0f;
364 struct musb_ep *pEnd;
365 struct musb_hw_ep *ep;
371 || bEnd >= MUSB_C_NUM_EPS
372 || pControlRequest->wValue
373 != USB_ENDPOINT_HALT)
376 ep = pThis->aLocalEnd + bEnd;
378 is_in = pControlRequest->wIndex & USB_DIR_IN;
386 MGC_SelectEnd(pBase, bEnd);
388 csr = musb_readw(regs,
390 if (csr & MGC_M_TXCSR_FIFONOTEMPTY)
391 csr |= MGC_M_TXCSR_FLUSHFIFO;
392 csr |= MGC_M_TXCSR_P_SENDSTALL
393 | MGC_M_TXCSR_CLRDATATOG
394 | MGC_M_TXCSR_P_WZC_BITS;
395 musb_writew(regs, MGC_O_HDRC_TXCSR,
398 csr = musb_readw(regs,
400 csr |= MGC_M_RXCSR_P_SENDSTALL
401 | MGC_M_RXCSR_FLUSHFIFO
402 | MGC_M_RXCSR_CLRDATATOG
403 | MGC_M_TXCSR_P_WZC_BITS;
404 musb_writew(regs, MGC_O_HDRC_RXCSR,
408 /* select ep0 again */
409 MGC_SelectEnd(pBase, 0);
414 /* class, vendor, etc ... delegate */
420 /* delegate SET_CONFIGURATION, etc */
428 /* we have an ep0out data packet
429 * Context: caller holds controller lock
431 static void ep0_rxstate(struct musb *this)
433 void __iomem *regs = this->control_ep->regs;
434 struct usb_request *req;
437 req = next_ep0_request(this);
439 /* read packet and ack; or stall because of gadget driver bug:
440 * should have provided the rx buffer before setup() returned.
443 void *buf = req->buf + req->actual;
444 unsigned len = req->length - req->actual;
446 /* read the buffer */
447 tmp = musb_readb(regs, MGC_O_HDRC_COUNT0);
449 req->status = -EOVERFLOW;
452 musb_read_fifo(&this->aLocalEnd[0], tmp, buf);
454 tmp = MGC_M_CSR0_P_SVDRXPKTRDY;
455 if (tmp < 64 || req->actual == req->length) {
456 this->ep0_state = MGC_END0_STAGE_STATUSIN;
457 tmp |= MGC_M_CSR0_P_DATAEND;
461 tmp = MGC_M_CSR0_P_SVDRXPKTRDY | MGC_M_CSR0_P_SENDSTALL;
462 musb_writew(regs, MGC_O_HDRC_CSR0, tmp);
465 /* NOTE: we "should" hold off reporting DATAEND and going to
466 * STATUSIN until after the completion handler decides whether
467 * to issue a stall instead, since this hardware can do that.
470 musb_g_ep0_giveback(this, req);
474 * transmitting to the host (IN), this code might be called from IRQ
475 * and from kernel thread.
477 * Context: caller holds controller lock
479 static void ep0_txstate(struct musb *pThis)
481 void __iomem *regs = pThis->control_ep->regs;
482 struct usb_request *pRequest = next_ep0_request(pThis);
483 u16 wCsrVal = MGC_M_CSR0_TXPKTRDY;
489 DBG(2, "odd; csr0 %04x\n", musb_readw(regs, MGC_O_HDRC_CSR0));
494 pFifoSource = (u8 *) pRequest->buf + pRequest->actual;
495 wFifoCount = min((unsigned) MGC_END0_FIFOSIZE,
496 pRequest->length - pRequest->actual);
497 musb_write_fifo(&pThis->aLocalEnd[0], wFifoCount, pFifoSource);
498 pRequest->actual += wFifoCount;
500 /* update the flags */
501 if (wFifoCount < MUSB_MAX_END0_PACKET
502 || pRequest->actual == pRequest->length) {
503 pThis->ep0_state = MGC_END0_STAGE_STATUSOUT;
504 wCsrVal |= MGC_M_CSR0_P_DATAEND;
508 /* send it out, triggering a "txpktrdy cleared" irq */
509 musb_writew(regs, MGC_O_HDRC_CSR0, wCsrVal);
511 /* report completions as soon as the fifo's loaded; there's no
512 * win in waiting till this last packet gets acked. (other than
513 * very precise fault reporting, needed by USB TMC; possible with
514 * this hardware, but not usable from portable gadget drivers.)
517 musb_g_ep0_giveback(pThis, pRequest);
521 * Read a SETUP packet (struct usb_ctrlrequest) from the hardware.
522 * Fields are left in USB byte-order.
524 * Context: caller holds controller lock.
527 musb_read_setup(struct musb *pThis, struct usb_ctrlrequest *req)
529 struct usb_request *r;
530 void __iomem *regs = pThis->control_ep->regs;
532 musb_read_fifo(&pThis->aLocalEnd[0], sizeof *req, (u8 *)req);
534 /* NOTE: earlier 2.6 versions changed setup packets to host
535 * order, but now USB packets always stay in USB byte order.
537 DBG(3, "SETUP req%02x.%02x v%04x i%04x l%d\n",
540 le16_to_cpu(req->wValue),
541 le16_to_cpu(req->wIndex),
542 le16_to_cpu(req->wLength));
544 /* clean up any leftover transfers */
545 r = next_ep0_request(pThis);
547 musb_g_ep0_giveback(pThis, r);
549 /* For zero-data requests we want to delay the STATUS stage to
550 * avoid SETUPEND errors. If we read data (OUT), delay accepting
551 * packets until there's a buffer to store them in.
553 * If we write data, the controller acts happier if we enable
554 * the TX FIFO right away, and give the controller a moment
557 pThis->bSetAddress = FALSE;
558 pThis->ackpend = MGC_M_CSR0_P_SVDRXPKTRDY;
559 if (req->wLength == 0)
560 pThis->ep0_state = MGC_END0_STAGE_ACKWAIT;
561 else if (req->bRequestType & USB_DIR_IN) {
562 pThis->ep0_state = MGC_END0_STAGE_TX;
563 musb_writew(regs, MGC_O_HDRC_CSR0, MGC_M_CSR0_P_SVDRXPKTRDY);
564 while ((musb_readw(regs, MGC_O_HDRC_CSR0)
565 & MGC_M_CSR0_RXPKTRDY) != 0)
569 pThis->ep0_state = MGC_END0_STAGE_RX;
573 forward_to_driver(struct musb *musb,
574 const struct usb_ctrlrequest *pControlRequest)
575 __releases(musb->Lock)
576 __acquires(musb->Lock)
579 if (!musb->pGadgetDriver)
581 spin_unlock(&musb->Lock);
582 retval = musb->pGadgetDriver->setup(&musb->g, pControlRequest);
583 spin_lock(&musb->Lock);
588 * Handle peripheral ep0 interrupt
591 * Context: irq handler; we won't re-enter the driver that way.
593 irqreturn_t musb_g_ep0_irq(struct musb *pThis)
597 void __iomem *pBase = pThis->pRegs;
598 void __iomem *regs = pThis->aLocalEnd[0].regs;
599 irqreturn_t retval = IRQ_NONE;
601 MGC_SelectEnd(pBase, 0); /* select ep0 */
602 wCsrVal = musb_readw(regs, MGC_O_HDRC_CSR0);
603 wCount = musb_readb(regs, MGC_O_HDRC_COUNT0);
605 DBG(4, "csr %04x, count %d, myaddr %d, ep0stage %s\n",
607 musb_readb(pBase, MGC_O_HDRC_FADDR),
608 decode_ep0stage(pThis->ep0_state));
610 /* I sent a stall.. need to acknowledge it now.. */
611 if (wCsrVal & MGC_M_CSR0_P_SENTSTALL) {
612 musb_writew(regs, MGC_O_HDRC_CSR0,
613 wCsrVal & ~MGC_M_CSR0_P_SENTSTALL);
614 retval = IRQ_HANDLED;
615 pThis->ep0_state = MGC_END0_STAGE_SETUP;
616 wCsrVal = musb_readw(regs, MGC_O_HDRC_CSR0);
619 /* request ended "early" */
620 if (wCsrVal & MGC_M_CSR0_P_SETUPEND) {
621 musb_writew(regs, MGC_O_HDRC_CSR0, MGC_M_CSR0_P_SVDSETUPEND);
622 retval = IRQ_HANDLED;
623 pThis->ep0_state = MGC_END0_STAGE_SETUP;
624 wCsrVal = musb_readw(regs, MGC_O_HDRC_CSR0);
625 /* NOTE: request may need completion */
628 /* docs from Mentor only describe tx, rx, and idle/setup states.
629 * we need to handle nuances around status stages, and also the
630 * case where status and setup stages come back-to-back ...
632 switch (pThis->ep0_state) {
634 case MGC_END0_STAGE_TX:
635 /* irq on clearing txpktrdy */
636 if ((wCsrVal & MGC_M_CSR0_TXPKTRDY) == 0) {
638 retval = IRQ_HANDLED;
642 case MGC_END0_STAGE_RX:
643 /* irq on set rxpktrdy */
644 if (wCsrVal & MGC_M_CSR0_RXPKTRDY) {
646 retval = IRQ_HANDLED;
650 case MGC_END0_STAGE_STATUSIN:
651 /* end of sequence #2 (OUT/RX state) or #3 (no data) */
653 /* update address (if needed) only @ the end of the
654 * status phase per usb spec, which also guarantees
655 * we get 10 msec to receive this irq... until this
656 * is done we won't see the next packet.
658 if (pThis->bSetAddress) {
659 pThis->bSetAddress = FALSE;
660 musb_writeb(pBase, MGC_O_HDRC_FADDR, pThis->bAddress);
663 /* enter test mode if needed (exit by reset) */
664 else if (pThis->bTestMode) {
665 DBG(1, "entering TESTMODE\n");
667 if (MGC_M_TEST_PACKET == pThis->bTestModeValue)
668 musb_load_testpacket(pThis);
670 musb_writeb(pBase, MGC_O_HDRC_TESTMODE,
671 pThis->bTestModeValue);
675 case MGC_END0_STAGE_STATUSOUT:
676 /* end of sequence #1: write to host (TX state) */
678 struct usb_request *req;
680 req = next_ep0_request(pThis);
682 musb_g_ep0_giveback(pThis, req);
684 retval = IRQ_HANDLED;
685 pThis->ep0_state = MGC_END0_STAGE_SETUP;
688 case MGC_END0_STAGE_SETUP:
689 if (wCsrVal & MGC_M_CSR0_RXPKTRDY) {
690 struct usb_ctrlrequest setup;
694 ERR("SETUP packet len %d != 8 ?\n", wCount);
697 musb_read_setup(pThis, &setup);
698 retval = IRQ_HANDLED;
700 /* sometimes the RESET won't be reported */
701 if (unlikely(pThis->g.speed == USB_SPEED_UNKNOWN)) {
704 printk(KERN_NOTICE "%s: peripheral reset "
707 power = musb_readb(pBase, MGC_O_HDRC_POWER);
708 pThis->g.speed = (power & MGC_M_POWER_HSMODE)
709 ? USB_SPEED_HIGH : USB_SPEED_FULL;
713 switch (pThis->ep0_state) {
715 /* sequence #3 (no data stage), includes requests
716 * we can't forward (notably SET_ADDRESS and the
717 * device/endpoint feature set/clear operations)
718 * plus SET_CONFIGURATION and others we must
720 case MGC_END0_STAGE_ACKWAIT:
721 handled = service_zero_data_request(
724 /* status stage might be immediate */
726 pThis->ackpend |= MGC_M_CSR0_P_DATAEND;
728 MGC_END0_STAGE_STATUSIN;
732 /* sequence #1 (IN to host), includes GET_STATUS
733 * requests that we can't forward, GET_DESCRIPTOR
734 * and others that we must
736 case MGC_END0_STAGE_TX:
737 handled = service_in_request(pThis, &setup);
739 pThis->ackpend = MGC_M_CSR0_TXPKTRDY
740 | MGC_M_CSR0_P_DATAEND;
742 MGC_END0_STAGE_STATUSOUT;
746 /* sequence #2 (OUT from host), always forward */
747 default: /* MGC_END0_STAGE_RX */
751 DBG(3, "handled %d, csr %04x, ep0stage %s\n",
753 decode_ep0stage(pThis->ep0_state));
755 /* unless we need to delegate this to the gadget
756 * driver, we know how to wrap this up: csr0 has
757 * not yet been written.
761 else if (handled > 0)
764 handled = forward_to_driver(pThis, &setup);
766 MGC_SelectEnd(pBase, 0);
768 DBG(3, "stall (%d)\n", handled);
769 pThis->ackpend |= MGC_M_CSR0_P_SENDSTALL;
770 pThis->ep0_state = MGC_END0_STAGE_SETUP;
772 musb_writew(regs, MGC_O_HDRC_CSR0,
779 case MGC_END0_STAGE_ACKWAIT:
780 /* This should not happen. But happens with tusb6010 with
781 * g_file_storage and high speed. Do nothing.
783 retval = IRQ_HANDLED;
789 musb_writew(regs, MGC_O_HDRC_CSR0, MGC_M_CSR0_P_SENDSTALL);
790 pThis->ep0_state = MGC_END0_STAGE_SETUP;
799 musb_g_ep0_enable(struct usb_ep *ep, const struct usb_endpoint_descriptor *desc)
805 static int musb_g_ep0_disable(struct usb_ep *e)
811 static void *musb_g_ep0_alloc_buffer(struct usb_ep *ep, unsigned bytes,
812 dma_addr_t * dma, gfp_t gfp_flags)
814 *dma = DMA_ADDR_INVALID;
815 return kmalloc(bytes, gfp_flags);
818 static void musb_g_ep0_free_buffer(struct usb_ep *ep, void *address,
819 dma_addr_t dma, unsigned bytes)
825 musb_g_ep0_queue(struct usb_ep *e, struct usb_request *r, gfp_t gfp_flags)
828 struct musb_request *req;
831 unsigned long lockflags;
839 regs = musb->control_ep->regs;
841 req = to_musb_request(r);
843 req->request.actual = 0;
844 req->request.status = -EINPROGRESS;
845 req->bTx = ep->is_in;
847 spin_lock_irqsave(&musb->Lock, lockflags);
849 if (!list_empty(&ep->req_list)) {
854 switch (musb->ep0_state) {
855 case MGC_END0_STAGE_RX: /* control-OUT data */
856 case MGC_END0_STAGE_TX: /* control-IN data */
857 case MGC_END0_STAGE_ACKWAIT: /* zero-length data */
861 DBG(1, "ep0 request queued in state %d\n",
867 /* add request to the list */
868 list_add_tail(&(req->request.list), &(ep->req_list));
870 DBG(3, "queue to %s (%s), length=%d\n",
871 ep->name, ep->is_in ? "IN/TX" : "OUT/RX",
872 req->request.length);
874 MGC_SelectEnd(musb->pRegs, 0);
876 /* sequence #1, IN ... start writing the data */
877 if (musb->ep0_state == MGC_END0_STAGE_TX)
880 /* sequence #3, no-data ... issue IN status */
881 else if (musb->ep0_state == MGC_END0_STAGE_ACKWAIT) {
882 if (req->request.length)
885 musb->ep0_state = MGC_END0_STAGE_STATUSIN;
886 musb_writew(regs, MGC_O_HDRC_CSR0,
887 musb->ackpend | MGC_M_CSR0_P_DATAEND);
889 musb_g_ep0_giveback(ep->pThis, r);
892 /* else for sequence #2 (OUT), caller provides a buffer
893 * before the next packet arrives. deferred responses
894 * (after SETUP is acked) are racey.
896 } else if (musb->ackpend) {
897 musb_writew(regs, MGC_O_HDRC_CSR0, musb->ackpend);
902 spin_unlock_irqrestore(&musb->Lock, lockflags);
907 musb_g_ep0_dequeue(struct usb_ep *ep, struct usb_request *req)
909 /* we just won't support this */
913 static int musb_g_ep0_halt(struct usb_ep *e, int value)
917 void __iomem *base, *regs;
928 regs = musb->control_ep->regs;
930 spin_lock_irqsave(&musb->Lock, flags);
932 if (!list_empty(&ep->req_list)) {
937 switch (musb->ep0_state) {
938 case MGC_END0_STAGE_TX: /* control-IN data */
939 case MGC_END0_STAGE_ACKWAIT: /* STALL for zero-length data */
940 case MGC_END0_STAGE_RX: /* control-OUT data */
943 MGC_SelectEnd(base, 0);
944 csr = musb_readw(regs, MGC_O_HDRC_CSR0);
945 csr |= MGC_M_CSR0_P_SENDSTALL;
946 musb_writew(regs, MGC_O_HDRC_CSR0, csr);
947 musb->ep0_state = MGC_END0_STAGE_SETUP;
950 DBG(1, "ep0 can't halt in state %d\n", musb->ep0_state);
955 spin_unlock_irqrestore(&musb->Lock, flags);
959 const struct usb_ep_ops musb_g_ep0_ops = {
960 .enable = musb_g_ep0_enable,
961 .disable = musb_g_ep0_disable,
962 .alloc_request = musb_alloc_request,
963 .free_request = musb_free_request,
964 .alloc_buffer = musb_g_ep0_alloc_buffer,
965 .free_buffer = musb_g_ep0_free_buffer,
966 .queue = musb_g_ep0_queue,
967 .dequeue = musb_g_ep0_dequeue,
968 .set_halt = musb_g_ep0_halt,