drivers/usb/musb/g_ep0.c

   1 /******************************************************************
   2  * Copyright 2005 Mentor Graphics Corporation
   3  * Copyright (C) 2005-2006 by Texas Instruments
   4  *
   5  * This file is part of the Inventra Controller Driver for Linux.
   6  *
   7  * The Inventra Controller Driver for Linux is free software; you
   8  * can redistribute it and/or modify it under the terms of the GNU
   9  * General Public License version 2 as published by the Free Software
  10  * Foundation.
  11  *
  12  * The Inventra Controller Driver for Linux is distributed in
  13  * the hope that it will be useful, but WITHOUT ANY WARRANTY;
  14  * without even the implied warranty of MERCHANTABILITY or
  15  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  16  * License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with The Inventra Controller Driver for Linux ; if not,
  20  * write to the Free Software Foundation, Inc., 59 Temple Place,
  21  * Suite 330, Boston, MA  02111-1307  USA
  22  *
  23  * ANY DOWNLOAD, USE, REPRODUCTION, MODIFICATION OR DISTRIBUTION
  24  * OF THIS DRIVER INDICATES YOUR COMPLETE AND UNCONDITIONAL ACCEPTANCE
  25  * OF THOSE TERMS.THIS DRIVER IS PROVIDED "AS IS" AND MENTOR GRAPHICS
  26  * MAKES NO WARRANTIES, EXPRESS OR IMPLIED, RELATED TO THIS DRIVER.
  27  * MENTOR GRAPHICS SPECIFICALLY DISCLAIMS ALL IMPLIED WARRANTIES
  28  * OF MERCHANTABILITY; FITNESS FOR A PARTICULAR PURPOSE AND
  29  * NON-INFRINGEMENT.  MENTOR GRAPHICS DOES NOT PROVIDE SUPPORT
  30  * SERVICES OR UPDATES FOR THIS DRIVER, EVEN IF YOU ARE A MENTOR
  31  * GRAPHICS SUPPORT CUSTOMER.
  32  ******************************************************************/
  33
  34 #include <linux/kernel.h>
  35 #include <linux/list.h>
  36 #include <linux/timer.h>
  37 #include <linux/spinlock.h>
  38 #include <linux/init.h>
  39 #include <linux/device.h>
  40 #include <linux/interrupt.h>
  41
  42 #include "musbdefs.h"
  43
  44 /* ep0 is always musb->aLocalEnd[0].ep_in */
  45 #define next_ep0_request(musb)  next_in_request(&(musb)->aLocalEnd[0])
  46
  47 /*
  48  * Locking note:  we use only the controller lock, for simpler correctness.
  49  * It's always held with IRQs blocked.
  50  *
  51  * It protects the ep0 request queue as well as ep0_state, not just the
  52  * controller and indexed registers.  And that lock stays held unless it
  53  * needs to be dropped to allow reentering this driver ... like upcalls to
  54  * the gadget driver, or adjusting endpoint halt status.
  55  */
  56
  57 static char *decode_ep0stage(u8 stage)
  58 {
  59         switch(stage) {
  60         case MGC_END0_STAGE_SETUP:      return "idle";
  61         case MGC_END0_STAGE_TX:         return "in";
  62         case MGC_END0_STAGE_RX:         return "out";
  63         case MGC_END0_STAGE_ACKWAIT:    return "wait";
  64         case MGC_END0_STAGE_STATUSIN:   return "in/status";
  65         case MGC_END0_STAGE_STATUSOUT:  return "out/status";
  66         default:                        return "?";
  67         }
  68 }
  69
  70 /* handle a standard GET_STATUS request
  71  * Context:  caller holds controller lock
  72  */
  73 static int service_tx_status_request(
  74         struct musb *pThis,
  75         const struct usb_ctrlrequest *pControlRequest)
  76 {
  77         void __iomem    *pBase = pThis->pRegs;
  78         int handled = 1;
  79         u8 bResult[2], bEnd = 0;
  80         const u8 bRecip = pControlRequest->bRequestType & USB_RECIP_MASK;
  81
  82         bResult[1] = 0;
  83
  84         switch (bRecip) {
  85         case USB_RECIP_DEVICE:
  86                 bResult[0] = pThis->bIsSelfPowered << USB_DEVICE_SELF_POWERED;
  87                 bResult[0] |= pThis->bMayWakeup << USB_DEVICE_REMOTE_WAKEUP;
  88 #ifdef CONFIG_USB_MUSB_OTG
  89                 if (pThis->g.is_otg) {
  90                         bResult[0] |= pThis->g.b_hnp_enable
  91                                 << USB_DEVICE_B_HNP_ENABLE;
  92                         bResult[0] |= pThis->g.a_alt_hnp_support
  93                                 << USB_DEVICE_A_ALT_HNP_SUPPORT;
  94                         bResult[0] |= pThis->g.a_hnp_support
  95                                 << USB_DEVICE_A_HNP_SUPPORT;
  96                 }
  97 #endif
  98                 break;
  99
 100         case USB_RECIP_INTERFACE:
 101                 bResult[0] = 0;
 102                 break;
 103
 104         case USB_RECIP_ENDPOINT: {
 105                 int             is_in;
 106                 struct musb_ep  *ep;
 107                 u16             tmp;
 108                 void __iomem    *regs;
 109
 110                 bEnd = (u8) pControlRequest->wIndex;
 111                 if (!bEnd) {
 112                         bResult[0] = 0;
 113                         break;
 114                 }
 115
 116                 is_in = bEnd & USB_DIR_IN;
 117                 if (is_in) {
 118                         bEnd &= 0x0f;
 119                         ep = &pThis->aLocalEnd[bEnd].ep_in;
 120                 } else {
 121                         ep = &pThis->aLocalEnd[bEnd].ep_out;
 122                 }
 123                 regs = pThis->aLocalEnd[bEnd].regs;
 124
 125                 if (bEnd >= MUSB_C_NUM_EPS || !ep->desc) {
 126                         handled = -EINVAL;
 127                         break;
 128                 }
 129
 130                 MGC_SelectEnd(pBase, bEnd);
 131                 if (is_in)
 132                         tmp = musb_readw(regs, MGC_O_HDRC_TXCSR)
 133                                                 & MGC_M_TXCSR_P_SENDSTALL;
 134                 else
 135                         tmp = musb_readw(regs, MGC_O_HDRC_RXCSR)
 136                                                 & MGC_M_RXCSR_P_SENDSTALL;
 137                 MGC_SelectEnd(pBase, 0);
 138
 139                 bResult[0] = tmp ? 1 : 0;
 140                 } break;
 141
 142         default:
 143                 /* class, vendor, etc ... delegate */
 144                 handled = 0;
 145                 break;
 146         }
 147
 148         /* fill up the fifo; caller updates csr0 */
 149         if (handled > 0) {
 150                 u16     len = le16_to_cpu(pControlRequest->wLength);
 151
 152                 if (len > 2)
 153                         len = 2;
 154                 musb_write_fifo(&pThis->aLocalEnd[0], len, bResult);
 155         }
 156
 157         return handled;
 158 }
 159
 160 /*
 161  * handle a control-IN request, the end0 buffer contains the current request
 162  * that is supposed to be a standard control request. Assumes the fifo to
 163  * be at least 2 bytes long.
 164  *
 165  * @return 0 if the request was NOT HANDLED,
 166  * < 0 when error
 167  * > 0 when the request is processed
 168  *
 169  * Context:  caller holds controller lock
 170  */
 171 static int
 172 service_in_request(struct musb *pThis,
 173                 const struct usb_ctrlrequest *pControlRequest)
 174 {
 175         int handled = 0;        /* not handled */
 176
 177         if ((pControlRequest->bRequestType & USB_TYPE_MASK)
 178                         == USB_TYPE_STANDARD) {
 179                 switch (pControlRequest->bRequest) {
 180                 case USB_REQ_GET_STATUS:
 181                         handled = service_tx_status_request(pThis,
 182                                         pControlRequest);
 183                         break;
 184
 185                 /* case USB_REQ_SYNC_FRAME: */
 186
 187                 default:
 188                         break;
 189                 }
 190         }
 191         return handled;
 192 }
 193
 194 /*
 195  * Context:  caller holds controller lock
 196  */
 197 static void musb_g_ep0_giveback(struct musb *pThis, struct usb_request *req)
 198 {
 199         pThis->ep0_state = MGC_END0_STAGE_SETUP;
 200         musb_g_giveback(&pThis->aLocalEnd[0].ep_in, req, 0);
 201 }
 202
 203 /*
 204  * Handle all control requests with no DATA stage, including standard
 205  * requests such as:
 206  * USB_REQ_SET_CONFIGURATION, USB_REQ_SET_INTERFACE, unrecognized
 207  *      always delegated to the gadget driver
 208  * USB_REQ_SET_ADDRESS, USB_REQ_CLEAR_FEATURE, USB_REQ_SET_FEATURE
 209  *      always handled here, except for class/vendor/... features
 210  *
 211  * Context:  caller holds controller lock
 212  */
 213 static int
 214 service_zero_data_request(struct musb *pThis,
 215                 struct usb_ctrlrequest *pControlRequest)
 216 __releases(pThis->Lock)
 217 __acquires(pThis->Lock)
 218 {
 219         int handled = -EINVAL;
 220         void __iomem *pBase = pThis->pRegs;
 221         const u8 bRecip = pControlRequest->bRequestType & USB_RECIP_MASK;
 222
 223         /* the gadget driver handles everything except what we MUST handle */
 224         if ((pControlRequest->bRequestType & USB_TYPE_MASK)
 225                         == USB_TYPE_STANDARD) {
 226                 switch (pControlRequest->bRequest) {
 227                 case USB_REQ_SET_ADDRESS:
 228                         /* change it after the status stage */
 229                         pThis->bSetAddress = TRUE;
 230                         pThis->bAddress = (u8) (pControlRequest->wValue & 0x7f);
 231                         handled = 1;
 232                         break;
 233
 234                 case USB_REQ_CLEAR_FEATURE:
 235                         switch (bRecip) {
 236                         case USB_RECIP_DEVICE:
 237                                 if (pControlRequest->wValue
 238                                                 != USB_DEVICE_REMOTE_WAKEUP)
 239                                         break;
 240                                 pThis->bMayWakeup = 0;
 241                                 handled = 1;
 242                                 break;
 243                         case USB_RECIP_INTERFACE:
 244                                 break;
 245                         case USB_RECIP_ENDPOINT:{
 246                                 const u8 bEnd = pControlRequest->wIndex & 0x0f;
 247                                 struct musb_ep *pEnd;
 248
 249                                 if (bEnd == 0
 250                                                 || bEnd >= MUSB_C_NUM_EPS
 251                                                 || pControlRequest->wValue
 252                                                         != USB_ENDPOINT_HALT)
 253                                         break;
 254
 255                                 if (pControlRequest->wIndex & USB_DIR_IN)
 256                                         pEnd = &pThis->aLocalEnd[bEnd].ep_in;
 257                                 else
 258                                         pEnd = &pThis->aLocalEnd[bEnd].ep_out;
 259                                 if (!pEnd->desc)
 260                                         break;
 261
 262                                 /* REVISIT do it directly, no locking games */
 263                                 spin_unlock(&pThis->Lock);
 264                                 musb_gadget_set_halt(&pEnd->end_point, 0);
 265                                 spin_lock(&pThis->Lock);
 266
 267                                 /* select ep0 again */
 268                                 MGC_SelectEnd(pBase, 0);
 269                                 handled = 1;
 270                                 } break;
 271                         default:
 272                                 /* class, vendor, etc ... delegate */
 273                                 handled = 0;
 274                                 break;
 275                         }
 276                         break;
 277
 278                 case USB_REQ_SET_FEATURE:
 279                         switch (bRecip) {
 280                         case USB_RECIP_DEVICE:
 281                                 handled = 1;
 282                                 switch (pControlRequest->wValue) {
 283                                 case USB_DEVICE_REMOTE_WAKEUP:
 284                                         pThis->bMayWakeup = 1;
 285                                         break;
 286                                 case USB_DEVICE_TEST_MODE:
 287                                         if (pThis->g.speed != USB_SPEED_HIGH)
 288                                                 goto stall;
 289                                         if (pControlRequest->wIndex & 0xff)
 290                                                 goto stall;
 291
 292                                         switch (pControlRequest->wIndex >> 8) {
 293                                         case 1:
 294                                                 pr_debug("TEST_J\n");
 295                                                 /* TEST_J */
 296                                                 pThis->bTestModeValue =
 297                                                         MGC_M_TEST_J;
 298                                                 break;
 299                                         case 2:
 300                                                 /* TEST_K */
 301                                                 pr_debug("TEST_K\n");
 302                                                 pThis->bTestModeValue =
 303                                                         MGC_M_TEST_K;
 304                                                 break;
 305                                         case 3:
 306                                                 /* TEST_SE0_NAK */
 307                                                 pr_debug("TEST_SE0_NAK\n");
 308                                                 pThis->bTestModeValue =
 309                                                         MGC_M_TEST_SE0_NAK;
 310                                                 break;
 311                                         case 4:
 312                                                 /* TEST_PACKET */
 313                                                 pr_debug("TEST_PACKET\n");
 314                                                 pThis->bTestModeValue =
 315                                                         MGC_M_TEST_PACKET;
 316                                                 break;
 317                                         default:
 318                                                 goto stall;
 319                                         }
 320
 321                                         /* enter test mode after irq */
 322                                         if (handled > 0)
 323                                                 pThis->bTestMode = TRUE;
 324                                         break;
 325 #ifdef CONFIG_USB_MUSB_OTG
 326                                 case USB_DEVICE_B_HNP_ENABLE:
 327                                         if (!pThis->g.is_otg)
 328                                                 goto stall;
 329                                         { u8 devctl;
 330                                         pThis->g.b_hnp_enable = 1;
 331                                         devctl = musb_readb(pBase,
 332                                                         MGC_O_HDRC_DEVCTL);
 333                                         musb_writeb(pBase, MGC_O_HDRC_DEVCTL,
 334                                                 devctl | MGC_M_DEVCTL_HR);
 335                                         }
 336                                         break;
 337                                 case USB_DEVICE_A_HNP_SUPPORT:
 338                                         if (!pThis->g.is_otg)
 339                                                 goto stall;
 340                                         pThis->g.a_hnp_support = 1;
 341                                         break;
 342                                 case USB_DEVICE_A_ALT_HNP_SUPPORT:
 343                                         if (!pThis->g.is_otg)
 344                                                 goto stall;
 345                                         pThis->g.a_alt_hnp_support = 1;
 346                                         break;
 347 #endif
 348 stall:
 349                                 default:
 350                                         handled = -EINVAL;
 351                                         break;
 352                                 }
 353                                 break;
 354
 355                         case USB_RECIP_INTERFACE:
 356                                 break;
 357
 358                         case USB_RECIP_ENDPOINT:{
 359                                 const u8                bEnd =
 360                                         pControlRequest->wIndex & 0x0f;
 361                                 struct musb_ep          *pEnd;
 362                                 struct musb_hw_ep       *ep;
 363                                 void __iomem            *regs;
 364                                 int                     is_in;
 365                                 u16                     csr;
 366
 367                                 if (bEnd == 0
 368                                                 || bEnd >= MUSB_C_NUM_EPS
 369                                                 || pControlRequest->wValue
 370                                                         != USB_ENDPOINT_HALT)
 371                                         break;
 372
 373                                 ep = pThis->aLocalEnd + bEnd;
 374                                 regs = ep->regs;
 375                                 is_in = pControlRequest->wIndex & USB_DIR_IN;
 376                                 if (is_in)
 377                                         pEnd = &ep->ep_in;
 378                                 else
 379                                         pEnd = &ep->ep_out;
 380                                 if (!pEnd->desc)
 381                                         break;
 382
 383                                 MGC_SelectEnd(pBase, bEnd);
 384                                 if (is_in) {
 385                                         csr = musb_readw(regs,
 386                                                         MGC_O_HDRC_TXCSR);
 387                                         if (csr & MGC_M_TXCSR_FIFONOTEMPTY)
 388                                                 csr |= MGC_M_TXCSR_FLUSHFIFO;
 389                                         csr |= MGC_M_TXCSR_P_SENDSTALL
 390                                                 | MGC_M_TXCSR_CLRDATATOG
 391                                                 | MGC_M_TXCSR_P_WZC_BITS;
 392                                         musb_writew(regs, MGC_O_HDRC_TXCSR,
 393                                                         csr);
 394                                 } else {
 395                                         csr = musb_readw(regs,
 396                                                         MGC_O_HDRC_RXCSR);
 397                                         csr |= MGC_M_RXCSR_P_SENDSTALL
 398                                                 | MGC_M_RXCSR_FLUSHFIFO
 399                                                 | MGC_M_RXCSR_CLRDATATOG
 400                                                 | MGC_M_TXCSR_P_WZC_BITS;
 401                                         musb_writew(regs, MGC_O_HDRC_RXCSR,
 402                                                         csr);
 403                                 }
 404
 405                                 /* select ep0 again */
 406                                 MGC_SelectEnd(pBase, 0);
 407                                 handled = 1;
 408                                 } break;
 409
 410                         default:
 411                                 /* class, vendor, etc ... delegate */
 412                                 handled = 0;
 413                                 break;
 414                         }
 415                         break;
 416                 default:
 417                         /* delegate SET_CONFIGURATION, etc */
 418                         handled = 0;
 419                 }
 420         } else
 421                 handled = 0;
 422         return handled;
 423 }
 424
 425 /* we have an ep0out data packet
 426  * Context:  caller holds controller lock
 427  */
 428 static void ep0_rxstate(struct musb *this)
 429 {
 430         void __iomem            *regs = this->control_ep->regs;
 431         struct usb_request      *req;
 432         u16                     tmp;
 433
 434         req = next_ep0_request(this);
 435
 436         /* read packet and ack; or stall because of gadget driver bug:
 437          * should have provided the rx buffer before setup() returned.
 438          */
 439         if (req) {
 440                 void            *buf = req->buf + req->actual;
 441                 unsigned        len = req->length - req->actual;
 442
 443                 /* read the buffer */
 444                 tmp = musb_readb(regs, MGC_O_HDRC_COUNT0);
 445                 if (tmp > len) {
 446                         req->status = -EOVERFLOW;
 447                         tmp = len;
 448                 }
 449                 musb_read_fifo(&this->aLocalEnd[0], tmp, buf);
 450                 req->actual += tmp;
 451                 tmp = MGC_M_CSR0_P_SVDRXPKTRDY;
 452                 if (tmp < 64 || req->actual == req->length) {
 453                         this->ep0_state = MGC_END0_STAGE_STATUSIN;
 454                         tmp |= MGC_M_CSR0_P_DATAEND;
 455                 } else
 456                         req = NULL;
 457         } else
 458                 tmp = MGC_M_CSR0_P_SVDRXPKTRDY | MGC_M_CSR0_P_SENDSTALL;
 459         musb_writew(regs, MGC_O_HDRC_CSR0, tmp);
 460
 461
 462         /* NOTE:  we "should" hold off reporting DATAEND and going to
 463          * STATUSIN until after the completion handler decides whether
 464          * to issue a stall instead, since this hardware can do that.
 465          */
 466         if (req)
 467                 musb_g_ep0_giveback(this, req);
 468 }
 469
 470 /*
 471  * transmitting to the host (IN), this code might be called from IRQ
 472  * and from kernel thread.
 473  *
 474  * Context:  caller holds controller lock
 475  */
 476 static void ep0_txstate(struct musb *pThis)
 477 {
 478         void __iomem            *regs = pThis->control_ep->regs;
 479         struct usb_request      *pRequest = next_ep0_request(pThis);
 480         u16                     wCsrVal = MGC_M_CSR0_TXPKTRDY;
 481         u8                      *pFifoSource;
 482         u8                      wFifoCount;
 483
 484         if (!pRequest) {
 485                 // WARN_ON(1);
 486                 DBG(2, "odd; csr0 %04x\n", musb_readw(regs, MGC_O_HDRC_CSR0));
 487                 return;
 488         }
 489
 490         /* load the data */
 491         pFifoSource = (u8 *) pRequest->buf + pRequest->actual;
 492         wFifoCount = min((unsigned) MGC_END0_FIFOSIZE,
 493                 pRequest->length - pRequest->actual);
 494         musb_write_fifo(&pThis->aLocalEnd[0], wFifoCount, pFifoSource);
 495         pRequest->actual += wFifoCount;
 496
 497         /* update the flags */
 498         if (wFifoCount < MUSB_MAX_END0_PACKET
 499                         || pRequest->actual == pRequest->length) {
 500                 pThis->ep0_state = MGC_END0_STAGE_STATUSOUT;
 501                 wCsrVal |= MGC_M_CSR0_P_DATAEND;
 502         } else
 503                 pRequest = NULL;
 504
 505         /* send it out, triggering a "txpktrdy cleared" irq */
 506         musb_writew(regs, MGC_O_HDRC_CSR0, wCsrVal);
 507
 508         /* report completions as soon as the fifo's loaded; there's no
 509          * win in waiting till this last packet gets acked.  (other than
 510          * very precise fault reporting, needed by USB TMC; possible with
 511          * this hardware, but not usable from portable gadget drivers.)
 512          */
 513         if (pRequest)
 514                 musb_g_ep0_giveback(pThis, pRequest);
 515 }
 516
 517 /*
 518  * Read a SETUP packet (struct usb_ctrlrequest) from the hardware.
 519  * Fields are left in USB byte-order.
 520  *
 521  * Context:  caller holds controller lock.
 522  */
 523 static void
 524 musb_read_setup(struct musb *pThis, struct usb_ctrlrequest *req)
 525 {
 526         struct usb_request      *r;
 527         void __iomem            *regs = pThis->control_ep->regs;
 528
 529         musb_read_fifo(&pThis->aLocalEnd[0], sizeof *req, (u8 *)req);
 530
 531         /* NOTE:  earlier 2.6 versions changed setup packets to host
 532          * order, but now USB packets always stay in USB byte order.
 533          */
 534         DBG(3, "SETUP req%02x.%02x v%04x i%04x l%d\n",
 535                 req->bRequestType,
 536                 req->bRequest,
 537                 le16_to_cpu(req->wValue),
 538                 le16_to_cpu(req->wIndex),
 539                 le16_to_cpu(req->wLength));
 540
 541         /* clean up any leftover transfers */
 542         r = next_ep0_request(pThis);
 543         if (r)
 544                 musb_g_ep0_giveback(pThis, r);
 545
 546         /* For zero-data requests we want to delay the STATUS stage to
 547          * avoid SETUPEND errors.  If we read data (OUT), delay accepting
 548          * packets until there's a buffer to store them in.
 549          *
 550          * If we write data, the controller acts happier if we enable
 551          * the TX FIFO right away, and give the controller a moment
 552          * to switch modes...
 553          */
 554         pThis->bSetAddress = FALSE;
 555         pThis->ackpend = MGC_M_CSR0_P_SVDRXPKTRDY;
 556         if (req->wLength == 0) {
 557                 if (req->bRequestType & USB_DIR_IN)
 558                         pThis->ackpend |= MGC_M_CSR0_TXPKTRDY;
 559                 pThis->ep0_state = MGC_END0_STAGE_ACKWAIT;
 560         } else if (req->bRequestType & USB_DIR_IN) {
 561                 pThis->ep0_state = MGC_END0_STAGE_TX;
 562                 musb_writew(regs, MGC_O_HDRC_CSR0, MGC_M_CSR0_P_SVDRXPKTRDY);
 563                 while ((musb_readw(regs, MGC_O_HDRC_CSR0)
 564                                 & MGC_M_CSR0_RXPKTRDY) != 0)
 565                         cpu_relax();
 566                 pThis->ackpend = 0;
 567         } else
 568                 pThis->ep0_state = MGC_END0_STAGE_RX;
 569 }
 570
 571 static int
 572 forward_to_driver(struct musb *musb,
 573                 const struct usb_ctrlrequest *pControlRequest)
 574 __releases(musb->Lock)
 575 __acquires(musb->Lock)
 576 {
 577         int retval;
 578         if (!musb->pGadgetDriver)
 579                 return -EOPNOTSUPP;
 580         spin_unlock(&musb->Lock);
 581         retval = musb->pGadgetDriver->setup(&musb->g, pControlRequest);
 582         spin_lock(&musb->Lock);
 583         return retval;
 584 }
 585
 586 /*
 587  * Handle peripheral ep0 interrupt
 588  * @param pThis this
 589  *
 590  * Context: irq handler; we won't re-enter the driver that way.
 591  */
 592 irqreturn_t musb_g_ep0_irq(struct musb *pThis)
 593 {
 594         u16             wCsrVal;
 595         u16             wCount;
 596         void __iomem    *pBase = pThis->pRegs;
 597         void __iomem    *regs = pThis->aLocalEnd[0].regs;
 598         irqreturn_t     retval = IRQ_NONE;
 599
 600         MGC_SelectEnd(pBase, 0);        /* select ep0 */
 601         wCsrVal = musb_readw(regs, MGC_O_HDRC_CSR0);
 602         wCount = musb_readb(regs, MGC_O_HDRC_COUNT0);
 603
 604         DBG(4, "csr %04x, count %d, myaddr %d, ep0stage %s\n",
 605                         wCsrVal, wCount,
 606                         musb_readb(pBase, MGC_O_HDRC_FADDR),
 607                         decode_ep0stage(pThis->ep0_state));
 608
 609         /* I sent a stall.. need to acknowledge it now.. */
 610         if (wCsrVal & MGC_M_CSR0_P_SENTSTALL) {
 611                 musb_writew(regs, MGC_O_HDRC_CSR0,
 612                                 wCsrVal & ~MGC_M_CSR0_P_SENTSTALL);
 613                 retval = IRQ_HANDLED;
 614                 pThis->ep0_state = MGC_END0_STAGE_SETUP;
 615                 wCsrVal = musb_readw(regs, MGC_O_HDRC_CSR0);
 616         }
 617
 618         /* request ended "early" */
 619         if (wCsrVal & MGC_M_CSR0_P_SETUPEND) {
 620                 musb_writew(regs, MGC_O_HDRC_CSR0, MGC_M_CSR0_P_SVDSETUPEND);
 621                 retval = IRQ_HANDLED;
 622                 pThis->ep0_state = MGC_END0_STAGE_SETUP;
 623                 wCsrVal = musb_readw(regs, MGC_O_HDRC_CSR0);
 624                 /* NOTE:  request may need completion */
 625         }
 626
 627         /* docs from Mentor only describe tx, rx, and idle/setup states.
 628          * we need to handle nuances around status stages, and also the
 629          * case where status and setup stages come back-to-back ...
 630          */
 631         switch (pThis->ep0_state) {
 632
 633         case MGC_END0_STAGE_TX:
 634                 /* irq on clearing txpktrdy */
 635                 if ((wCsrVal & MGC_M_CSR0_TXPKTRDY) == 0) {
 636                         ep0_txstate(pThis);
 637                         retval = IRQ_HANDLED;
 638                 }
 639                 break;
 640
 641         case MGC_END0_STAGE_RX:
 642                 /* irq on set rxpktrdy */
 643                 if (wCsrVal & MGC_M_CSR0_RXPKTRDY) {
 644                         ep0_rxstate(pThis);
 645                         retval = IRQ_HANDLED;
 646                 }
 647                 break;
 648
 649         case MGC_END0_STAGE_STATUSIN:
 650                 /* end of sequence #2 (OUT/RX state) or #3 (no data) */
 651
 652                 /* update address (if needed) only @ the end of the
 653                  * status phase per usb spec, which also guarantees
 654                  * we get 10 msec to receive this irq... until this
 655                  * is done we won't see the next packet.
 656                  */
 657                 if (pThis->bSetAddress) {
 658                         pThis->bSetAddress = FALSE;
 659                         musb_writeb(pBase, MGC_O_HDRC_FADDR, pThis->bAddress);
 660                 }
 661
 662                 /* enter test mode if needed (exit by reset) */
 663                 else if (pThis->bTestMode) {
 664                         DBG(1, "entering TESTMODE\n");
 665
 666                         if (MGC_M_TEST_PACKET == pThis->bTestModeValue)
 667                                 musb_load_testpacket(pThis);
 668
 669                         musb_writeb(pBase, MGC_O_HDRC_TESTMODE,
 670                                         pThis->bTestModeValue);
 671                 }
 672                 /* FALLTHROUGH */
 673
 674         case MGC_END0_STAGE_STATUSOUT:
 675                 /* end of sequence #1: write to host (TX state) */
 676                 {
 677                         struct usb_request      *req;
 678
 679                         req = next_ep0_request(pThis);
 680                         if (req)
 681                                 musb_g_ep0_giveback(pThis, req);
 682                 }
 683                 retval = IRQ_HANDLED;
 684                 pThis->ep0_state = MGC_END0_STAGE_SETUP;
 685                 /* FALLTHROUGH */
 686
 687         case MGC_END0_STAGE_SETUP:
 688                 if (wCsrVal & MGC_M_CSR0_RXPKTRDY) {
 689                         struct usb_ctrlrequest  setup;
 690                         int                     handled = 0;
 691
 692                         if (wCount != 8) {
 693                                 ERR("SETUP packet len %d != 8 ?\n", wCount);
 694                                 break;
 695                         }
 696                         musb_read_setup(pThis, &setup);
 697                         retval = IRQ_HANDLED;
 698
 699                         /* sometimes the RESET won't be reported */
 700                         if (unlikely(pThis->g.speed == USB_SPEED_UNKNOWN)) {
 701                                 u8      power;
 702
 703                                 printk(KERN_NOTICE "%s: peripheral reset "
 704                                                 "irq lost!\n",
 705                                                 musb_driver_name);
 706                                 power = musb_readb(pBase, MGC_O_HDRC_POWER);
 707                                 pThis->g.speed = (power & MGC_M_POWER_HSMODE)
 708                                         ? USB_SPEED_HIGH : USB_SPEED_FULL;
 709
 710                         }
 711
 712                         switch (pThis->ep0_state) {
 713
 714                         /* sequence #3 (no data stage), includes requests
 715                          * we can't forward (notably SET_ADDRESS and the
 716                          * device/endpoint feature set/clear operations)
 717                          * plus SET_CONFIGURATION and others we must
 718                          */
 719                         case MGC_END0_STAGE_ACKWAIT:
 720                                 handled = service_zero_data_request(
 721                                                 pThis, &setup);
 722
 723                                 /* status stage might be immediate */
 724                                 if (handled > 0) {
 725                                         pThis->ackpend |= MGC_M_CSR0_P_DATAEND;
 726                                         pThis->ep0_state =
 727                                                 MGC_END0_STAGE_STATUSIN;
 728                                 }
 729                                 break;
 730
 731                         /* sequence #1 (IN to host), includes GET_STATUS
 732                          * requests that we can't forward, GET_DESCRIPTOR
 733                          * and others that we must
 734                          */
 735                         case MGC_END0_STAGE_TX:
 736                                 handled = service_in_request(pThis, &setup);
 737                                 if (handled > 0) {
 738                                         pThis->ackpend = MGC_M_CSR0_TXPKTRDY
 739                                                 | MGC_M_CSR0_P_DATAEND;
 740                                         pThis->ep0_state =
 741                                                 MGC_END0_STAGE_STATUSOUT;
 742                                 }
 743                                 break;
 744
 745                         /* sequence #2 (OUT from host), always forward */
 746                         default:                /* MGC_END0_STAGE_RX */
 747                                 break;
 748                         }
 749
 750                         DBG(3, "handled %d, csr %04x, ep0stage %s\n",
 751                                 handled, wCsrVal,
 752                                 decode_ep0stage(pThis->ep0_state));
 753
 754                         /* unless we need to delegate this to the gadget
 755                          * driver, we know how to wrap this up:  csr0 has
 756                          * not yet been written.
 757                          */
 758                         if (handled < 0)
 759                                 goto stall;
 760                         else if (handled > 0)
 761                                 goto finish;
 762
 763                         handled = forward_to_driver(pThis, &setup);
 764                         if (handled < 0) {
 765                                 MGC_SelectEnd(pBase, 0);
 766 stall:
 767                                 DBG(3, "stall (%d)\n", handled);
 768                                 pThis->ackpend |= MGC_M_CSR0_P_SENDSTALL;
 769                                 pThis->ep0_state = MGC_END0_STAGE_SETUP;
 770 finish:
 771                                 musb_writew(regs, MGC_O_HDRC_CSR0,
 772                                                 pThis->ackpend);
 773                                 pThis->ackpend = 0;
 774                         }
 775                 }
 776                 break;
 777
 778         case MGC_END0_STAGE_ACKWAIT:
 779                 /* This should not happen. But happens with tusb6010 with
 780                  * g_file_storage and high speed. Do nothing.
 781                  */
 782                 retval = IRQ_HANDLED;
 783                 break;
 784
 785         default:
 786                 /* "can't happen" */
 787                 WARN_ON(1);
 788                 musb_writew(regs, MGC_O_HDRC_CSR0, MGC_M_CSR0_P_SENDSTALL);
 789                 pThis->ep0_state = MGC_END0_STAGE_SETUP;
 790                 break;
 791         }
 792
 793         return retval;
 794 }
 795
 796
 797 static int
 798 musb_g_ep0_enable(struct usb_ep *ep, const struct usb_endpoint_descriptor *desc)
 799 {
 800         /* always enabled */
 801         return -EINVAL;
 802 }
 803
 804 static int musb_g_ep0_disable(struct usb_ep *e)
 805 {
 806         /* always enabled */
 807         return -EINVAL;
 808 }
 809
 810 static void *musb_g_ep0_alloc_buffer(struct usb_ep *ep, unsigned bytes,
 811                         dma_addr_t * dma, gfp_t gfp_flags)
 812 {
 813         *dma = DMA_ADDR_INVALID;
 814         return kmalloc(bytes, gfp_flags);
 815 }
 816
 817 static void musb_g_ep0_free_buffer(struct usb_ep *ep, void *address,
 818                         dma_addr_t dma, unsigned bytes)
 819 {
 820         kfree(address);
 821 }
 822
 823 static int
 824 musb_g_ep0_queue(struct usb_ep *e, struct usb_request *r, gfp_t gfp_flags)
 825 {
 826         struct musb_ep          *ep;
 827         struct musb_request     *req;
 828         struct musb             *musb;
 829         int                     status;
 830         unsigned long           lockflags;
 831         void __iomem            *regs;
 832
 833         if (!e || !r)
 834                 return -EINVAL;
 835
 836         ep = to_musb_ep(e);
 837         musb = ep->pThis;
 838         regs = musb->control_ep->regs;
 839
 840         req = to_musb_request(r);
 841         req->musb = musb;
 842         req->request.actual = 0;
 843         req->request.status = -EINPROGRESS;
 844         req->bTx = ep->is_in;
 845
 846         spin_lock_irqsave(&musb->Lock, lockflags);
 847
 848         if (!list_empty(&ep->req_list)) {
 849                 status = -EBUSY;
 850                 goto cleanup;
 851         }
 852
 853         switch (musb->ep0_state) {
 854         case MGC_END0_STAGE_RX:         /* control-OUT data */
 855         case MGC_END0_STAGE_TX:         /* control-IN data */
 856         case MGC_END0_STAGE_ACKWAIT:    /* zero-length data */
 857                 status = 0;
 858                 break;
 859         default:
 860                 DBG(1, "ep0 request queued in state %d\n",
 861                                 musb->ep0_state);
 862                 status = -EINVAL;
 863                 goto cleanup;
 864         }
 865
 866         /* add request to the list */
 867         list_add_tail(&(req->request.list), &(ep->req_list));
 868
 869         DBG(3, "queue to %s (%s), length=%d\n",
 870                         ep->name, ep->is_in ? "IN/TX" : "OUT/RX",
 871                         req->request.length);
 872
 873         MGC_SelectEnd(musb->pRegs, 0);
 874
 875         /* sequence #1, IN ... start writing the data */
 876         if (musb->ep0_state == MGC_END0_STAGE_TX)
 877                 ep0_txstate(musb);
 878
 879         /* sequence #3, no-data ... issue IN status */
 880         else if (musb->ep0_state == MGC_END0_STAGE_ACKWAIT) {
 881                 if (req->request.length)
 882                         status = -EINVAL;
 883                 else {
 884                         musb->ep0_state = MGC_END0_STAGE_STATUSIN;
 885                         musb_writew(regs, MGC_O_HDRC_CSR0,
 886                                         musb->ackpend | MGC_M_CSR0_P_DATAEND);
 887                         musb->ackpend = 0;
 888                         musb_g_ep0_giveback(ep->pThis, r);
 889                 }
 890
 891         /* else for sequence #2 (OUT), caller provides a buffer
 892          * before the next packet arrives.  deferred responses
 893          * (after SETUP is acked) are racey.
 894          */
 895         } else if (musb->ackpend) {
 896                 musb_writew(regs, MGC_O_HDRC_CSR0, musb->ackpend);
 897                 musb->ackpend = 0;
 898         }
 899
 900 cleanup:
 901         spin_unlock_irqrestore(&musb->Lock, lockflags);
 902         return status;
 903 }
 904
 905 static int
 906 musb_g_ep0_dequeue(struct usb_ep *ep, struct usb_request *req)
 907 {
 908         /* we just won't support this */
 909         return -EINVAL;
 910 }
 911
 912 static int musb_g_ep0_halt(struct usb_ep *e, int value)
 913 {
 914         struct musb_ep          *ep;
 915         struct musb             *musb;
 916         void __iomem            *base, *regs;
 917         unsigned long           flags;
 918         int                     status;
 919         u16                     csr;
 920
 921         if (!e || !value)
 922                 return -EINVAL;
 923
 924         ep = to_musb_ep(e);
 925         musb = ep->pThis;
 926         base = musb->pRegs;
 927         regs = musb->control_ep->regs;
 928
 929         spin_lock_irqsave(&musb->Lock, flags);
 930
 931         if (!list_empty(&ep->req_list)) {
 932                 status = -EBUSY;
 933                 goto cleanup;
 934         }
 935
 936         switch (musb->ep0_state) {
 937         case MGC_END0_STAGE_TX:         /* control-IN data */
 938         case MGC_END0_STAGE_ACKWAIT:    /* STALL for zero-length data */
 939         case MGC_END0_STAGE_RX:         /* control-OUT data */
 940                 status = 0;
 941
 942                 MGC_SelectEnd(base, 0);
 943                 csr = musb_readw(regs, MGC_O_HDRC_CSR0);
 944                 csr |= MGC_M_CSR0_P_SENDSTALL;
 945                 musb_writew(regs, MGC_O_HDRC_CSR0, csr);
 946                 musb->ep0_state = MGC_END0_STAGE_SETUP;
 947                 break;
 948         default:
 949                 DBG(1, "ep0 can't halt in state %d\n", musb->ep0_state);
 950                 status = -EINVAL;
 951         }
 952
 953 cleanup:
 954         spin_unlock_irqrestore(&musb->Lock, flags);
 955         return status;
 956 }
 957
 958 const struct usb_ep_ops musb_g_ep0_ops = {
 959         .enable         = musb_g_ep0_enable,
 960         .disable        = musb_g_ep0_disable,
 961         .alloc_request  = musb_alloc_request,
 962         .free_request   = musb_free_request,
 963         .alloc_buffer   = musb_g_ep0_alloc_buffer,
 964         .free_buffer    = musb_g_ep0_free_buffer,
 965         .queue          = musb_g_ep0_queue,
 966         .dequeue        = musb_g_ep0_dequeue,
 967         .set_halt       = musb_g_ep0_halt,
 968         .fifo_status    = NULL,
 969         .fifo_flush     = NULL,
 970 };