1 /******************************************************************
2 * Copyright 2005 Mentor Graphics Corporation
3 * Copyright (C) 2005-2006 by Texas Instruments
5 * This file is part of the Inventra Controller Driver for Linux.
7 * The Inventra Controller Driver for Linux is free software; you
8 * can redistribute it and/or modify it under the terms of the GNU
9 * General Public License version 2 as published by the Free Software
12 * The Inventra Controller Driver for Linux is distributed in
13 * the hope that it will be useful, but WITHOUT ANY WARRANTY;
14 * without even the implied warranty of MERCHANTABILITY or
15 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
16 * License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with The Inventra Controller Driver for Linux ; if not,
20 * write to the Free Software Foundation, Inc., 59 Temple Place,
21 * Suite 330, Boston, MA 02111-1307 USA
23 * ANY DOWNLOAD, USE, REPRODUCTION, MODIFICATION OR DISTRIBUTION
24 * OF THIS DRIVER INDICATES YOUR COMPLETE AND UNCONDITIONAL ACCEPTANCE
25 * OF THOSE TERMS.THIS DRIVER IS PROVIDED "AS IS" AND MENTOR GRAPHICS
26 * MAKES NO WARRANTIES, EXPRESS OR IMPLIED, RELATED TO THIS DRIVER.
27 * MENTOR GRAPHICS SPECIFICALLY DISCLAIMS ALL IMPLIED WARRANTIES
28 * OF MERCHANTABILITY; FITNESS FOR A PARTICULAR PURPOSE AND
29 * NON-INFRINGEMENT. MENTOR GRAPHICS DOES NOT PROVIDE SUPPORT
30 * SERVICES OR UPDATES FOR THIS DRIVER, EVEN IF YOU ARE A MENTOR
31 * GRAPHICS SUPPORT CUSTOMER.
32 ******************************************************************/
34 #include <linux/kernel.h>
35 #include <linux/list.h>
36 #include <linux/timer.h>
37 #include <linux/spinlock.h>
38 #include <linux/init.h>
39 #include <linux/device.h>
40 #include <linux/interrupt.h>
44 /* ep0 is always musb->aLocalEnd[0].ep_in */
45 #define next_ep0_request(musb) next_in_request(&(musb)->aLocalEnd[0])
48 * Locking note: we use only the controller lock, for simpler correctness.
49 * It's always held with IRQs blocked.
51 * It protects the ep0 request queue as well as ep0_state, not just the
52 * controller and indexed registers. And that lock stays held unless it
53 * needs to be dropped to allow reentering this driver ... like upcalls to
54 * the gadget driver, or adjusting endpoint halt status.
57 static char *decode_ep0stage(u8 stage)
60 case MGC_END0_STAGE_SETUP: return "idle";
61 case MGC_END0_STAGE_TX: return "in";
62 case MGC_END0_STAGE_RX: return "out";
63 case MGC_END0_STAGE_ACKWAIT: return "wait";
64 case MGC_END0_STAGE_STATUSIN: return "in/status";
65 case MGC_END0_STAGE_STATUSOUT: return "out/status";
70 /* handle a standard GET_STATUS request
71 * Context: caller holds controller lock
73 static int service_tx_status_request(
75 const struct usb_ctrlrequest *pControlRequest)
77 void __iomem *pBase = pThis->pRegs;
79 u8 bResult[2], bEnd = 0;
80 const u8 bRecip = pControlRequest->bRequestType & USB_RECIP_MASK;
85 case USB_RECIP_DEVICE:
86 bResult[0] = pThis->bIsSelfPowered << USB_DEVICE_SELF_POWERED;
87 bResult[0] |= pThis->bMayWakeup << USB_DEVICE_REMOTE_WAKEUP;
88 #ifdef CONFIG_USB_MUSB_OTG
89 if (pThis->g.is_otg) {
90 bResult[0] |= pThis->g.b_hnp_enable
91 << USB_DEVICE_B_HNP_ENABLE;
92 bResult[0] |= pThis->g.a_alt_hnp_support
93 << USB_DEVICE_A_ALT_HNP_SUPPORT;
94 bResult[0] |= pThis->g.a_hnp_support
95 << USB_DEVICE_A_HNP_SUPPORT;
100 case USB_RECIP_INTERFACE:
104 case USB_RECIP_ENDPOINT: {
110 bEnd = (u8) pControlRequest->wIndex;
116 is_in = bEnd & USB_DIR_IN;
119 ep = &pThis->aLocalEnd[bEnd].ep_in;
121 ep = &pThis->aLocalEnd[bEnd].ep_out;
123 regs = pThis->aLocalEnd[bEnd].regs;
125 if (bEnd >= MUSB_C_NUM_EPS || !ep->desc) {
130 MGC_SelectEnd(pBase, bEnd);
132 tmp = musb_readw(regs, MGC_O_HDRC_TXCSR)
133 & MGC_M_TXCSR_P_SENDSTALL;
135 tmp = musb_readw(regs, MGC_O_HDRC_RXCSR)
136 & MGC_M_RXCSR_P_SENDSTALL;
137 MGC_SelectEnd(pBase, 0);
139 bResult[0] = tmp ? 1 : 0;
143 /* class, vendor, etc ... delegate */
148 /* fill up the fifo; caller updates csr0 */
150 u16 len = le16_to_cpu(pControlRequest->wLength);
154 musb_write_fifo(&pThis->aLocalEnd[0], len, bResult);
161 * handle a control-IN request, the end0 buffer contains the current request
162 * that is supposed to be a standard control request. Assumes the fifo to
163 * be at least 2 bytes long.
165 * @return 0 if the request was NOT HANDLED,
167 * > 0 when the request is processed
169 * Context: caller holds controller lock
172 service_in_request(struct musb *pThis,
173 const struct usb_ctrlrequest *pControlRequest)
175 int handled = 0; /* not handled */
177 if ((pControlRequest->bRequestType & USB_TYPE_MASK)
178 == USB_TYPE_STANDARD) {
179 switch (pControlRequest->bRequest) {
180 case USB_REQ_GET_STATUS:
181 handled = service_tx_status_request(pThis,
185 /* case USB_REQ_SYNC_FRAME: */
195 * Context: caller holds controller lock
197 static void musb_g_ep0_giveback(struct musb *pThis, struct usb_request *req)
199 pThis->ep0_state = MGC_END0_STAGE_SETUP;
200 musb_g_giveback(&pThis->aLocalEnd[0].ep_in, req, 0);
204 * Handle all control requests with no DATA stage, including standard
206 * USB_REQ_SET_CONFIGURATION, USB_REQ_SET_INTERFACE, unrecognized
207 * always delegated to the gadget driver
208 * USB_REQ_SET_ADDRESS, USB_REQ_CLEAR_FEATURE, USB_REQ_SET_FEATURE
209 * always handled here, except for class/vendor/... features
211 * Context: caller holds controller lock
214 service_zero_data_request(struct musb *pThis,
215 struct usb_ctrlrequest *pControlRequest)
216 __releases(pThis->Lock)
217 __acquires(pThis->Lock)
219 int handled = -EINVAL;
220 void __iomem *pBase = pThis->pRegs;
221 const u8 bRecip = pControlRequest->bRequestType & USB_RECIP_MASK;
223 /* the gadget driver handles everything except what we MUST handle */
224 if ((pControlRequest->bRequestType & USB_TYPE_MASK)
225 == USB_TYPE_STANDARD) {
226 switch (pControlRequest->bRequest) {
227 case USB_REQ_SET_ADDRESS:
228 /* change it after the status stage */
229 pThis->bSetAddress = TRUE;
230 pThis->bAddress = (u8) (pControlRequest->wValue & 0x7f);
234 case USB_REQ_CLEAR_FEATURE:
236 case USB_RECIP_DEVICE:
237 if (pControlRequest->wValue
238 != USB_DEVICE_REMOTE_WAKEUP)
240 pThis->bMayWakeup = 0;
243 case USB_RECIP_INTERFACE:
245 case USB_RECIP_ENDPOINT:{
246 const u8 bEnd = pControlRequest->wIndex & 0x0f;
247 struct musb_ep *pEnd;
250 || bEnd >= MUSB_C_NUM_EPS
251 || pControlRequest->wValue
252 != USB_ENDPOINT_HALT)
255 if (pControlRequest->wIndex & USB_DIR_IN)
256 pEnd = &pThis->aLocalEnd[bEnd].ep_in;
258 pEnd = &pThis->aLocalEnd[bEnd].ep_out;
262 /* REVISIT do it directly, no locking games */
263 spin_unlock(&pThis->Lock);
264 musb_gadget_set_halt(&pEnd->end_point, 0);
265 spin_lock(&pThis->Lock);
267 /* select ep0 again */
268 MGC_SelectEnd(pBase, 0);
272 /* class, vendor, etc ... delegate */
278 case USB_REQ_SET_FEATURE:
280 case USB_RECIP_DEVICE:
282 switch (pControlRequest->wValue) {
283 case USB_DEVICE_REMOTE_WAKEUP:
284 pThis->bMayWakeup = 1;
286 case USB_DEVICE_TEST_MODE:
287 if (pThis->g.speed != USB_SPEED_HIGH)
289 if (pControlRequest->wIndex & 0xff)
292 switch (pControlRequest->wIndex >> 8) {
294 pr_debug("TEST_J\n");
296 pThis->bTestModeValue =
301 pr_debug("TEST_K\n");
302 pThis->bTestModeValue =
307 pr_debug("TEST_SE0_NAK\n");
308 pThis->bTestModeValue =
313 pr_debug("TEST_PACKET\n");
314 pThis->bTestModeValue =
321 /* enter test mode after irq */
323 pThis->bTestMode = TRUE;
325 #ifdef CONFIG_USB_MUSB_OTG
326 case USB_DEVICE_B_HNP_ENABLE:
327 if (!pThis->g.is_otg)
330 pThis->g.b_hnp_enable = 1;
331 devctl = musb_readb(pBase,
333 musb_writeb(pBase, MGC_O_HDRC_DEVCTL,
334 devctl | MGC_M_DEVCTL_HR);
337 case USB_DEVICE_A_HNP_SUPPORT:
338 if (!pThis->g.is_otg)
340 pThis->g.a_hnp_support = 1;
342 case USB_DEVICE_A_ALT_HNP_SUPPORT:
343 if (!pThis->g.is_otg)
345 pThis->g.a_alt_hnp_support = 1;
355 case USB_RECIP_INTERFACE:
358 case USB_RECIP_ENDPOINT:{
360 pControlRequest->wIndex & 0x0f;
361 struct musb_ep *pEnd;
362 struct musb_hw_ep *ep;
368 || bEnd >= MUSB_C_NUM_EPS
369 || pControlRequest->wValue
370 != USB_ENDPOINT_HALT)
373 ep = pThis->aLocalEnd + bEnd;
375 is_in = pControlRequest->wIndex & USB_DIR_IN;
383 MGC_SelectEnd(pBase, bEnd);
385 csr = musb_readw(regs,
387 if (csr & MGC_M_TXCSR_FIFONOTEMPTY)
388 csr |= MGC_M_TXCSR_FLUSHFIFO;
389 csr |= MGC_M_TXCSR_P_SENDSTALL
390 | MGC_M_TXCSR_CLRDATATOG
391 | MGC_M_TXCSR_P_WZC_BITS;
392 musb_writew(regs, MGC_O_HDRC_TXCSR,
395 csr = musb_readw(regs,
397 csr |= MGC_M_RXCSR_P_SENDSTALL
398 | MGC_M_RXCSR_FLUSHFIFO
399 | MGC_M_RXCSR_CLRDATATOG
400 | MGC_M_TXCSR_P_WZC_BITS;
401 musb_writew(regs, MGC_O_HDRC_RXCSR,
405 /* select ep0 again */
406 MGC_SelectEnd(pBase, 0);
411 /* class, vendor, etc ... delegate */
417 /* delegate SET_CONFIGURATION, etc */
425 /* we have an ep0out data packet
426 * Context: caller holds controller lock
428 static void ep0_rxstate(struct musb *this)
430 void __iomem *regs = this->control_ep->regs;
431 struct usb_request *req;
434 req = next_ep0_request(this);
436 /* read packet and ack; or stall because of gadget driver bug:
437 * should have provided the rx buffer before setup() returned.
440 void *buf = req->buf + req->actual;
441 unsigned len = req->length - req->actual;
443 /* read the buffer */
444 tmp = musb_readb(regs, MGC_O_HDRC_COUNT0);
446 req->status = -EOVERFLOW;
449 musb_read_fifo(&this->aLocalEnd[0], tmp, buf);
451 tmp = MGC_M_CSR0_P_SVDRXPKTRDY;
452 if (tmp < 64 || req->actual == req->length) {
453 this->ep0_state = MGC_END0_STAGE_STATUSIN;
454 tmp |= MGC_M_CSR0_P_DATAEND;
458 tmp = MGC_M_CSR0_P_SVDRXPKTRDY | MGC_M_CSR0_P_SENDSTALL;
459 musb_writew(regs, MGC_O_HDRC_CSR0, tmp);
462 /* NOTE: we "should" hold off reporting DATAEND and going to
463 * STATUSIN until after the completion handler decides whether
464 * to issue a stall instead, since this hardware can do that.
467 musb_g_ep0_giveback(this, req);
471 * transmitting to the host (IN), this code might be called from IRQ
472 * and from kernel thread.
474 * Context: caller holds controller lock
476 static void ep0_txstate(struct musb *pThis)
478 void __iomem *regs = pThis->control_ep->regs;
479 struct usb_request *pRequest = next_ep0_request(pThis);
480 u16 wCsrVal = MGC_M_CSR0_TXPKTRDY;
486 DBG(2, "odd; csr0 %04x\n", musb_readw(regs, MGC_O_HDRC_CSR0));
491 pFifoSource = (u8 *) pRequest->buf + pRequest->actual;
492 wFifoCount = min((unsigned) MGC_END0_FIFOSIZE,
493 pRequest->length - pRequest->actual);
494 musb_write_fifo(&pThis->aLocalEnd[0], wFifoCount, pFifoSource);
495 pRequest->actual += wFifoCount;
497 /* update the flags */
498 if (wFifoCount < MUSB_MAX_END0_PACKET
499 || pRequest->actual == pRequest->length) {
500 pThis->ep0_state = MGC_END0_STAGE_STATUSOUT;
501 wCsrVal |= MGC_M_CSR0_P_DATAEND;
505 /* send it out, triggering a "txpktrdy cleared" irq */
506 musb_writew(regs, MGC_O_HDRC_CSR0, wCsrVal);
508 /* report completions as soon as the fifo's loaded; there's no
509 * win in waiting till this last packet gets acked. (other than
510 * very precise fault reporting, needed by USB TMC; possible with
511 * this hardware, but not usable from portable gadget drivers.)
514 musb_g_ep0_giveback(pThis, pRequest);
518 * Read a SETUP packet (struct usb_ctrlrequest) from the hardware.
519 * Fields are left in USB byte-order.
521 * Context: caller holds controller lock.
524 musb_read_setup(struct musb *pThis, struct usb_ctrlrequest *req)
526 struct usb_request *r;
527 void __iomem *regs = pThis->control_ep->regs;
529 musb_read_fifo(&pThis->aLocalEnd[0], sizeof *req, (u8 *)req);
531 /* NOTE: earlier 2.6 versions changed setup packets to host
532 * order, but now USB packets always stay in USB byte order.
534 DBG(3, "SETUP req%02x.%02x v%04x i%04x l%d\n",
537 le16_to_cpu(req->wValue),
538 le16_to_cpu(req->wIndex),
539 le16_to_cpu(req->wLength));
541 /* clean up any leftover transfers */
542 r = next_ep0_request(pThis);
544 musb_g_ep0_giveback(pThis, r);
546 /* For zero-data requests we want to delay the STATUS stage to
547 * avoid SETUPEND errors. If we read data (OUT), delay accepting
548 * packets until there's a buffer to store them in.
550 * If we write data, the controller acts happier if we enable
551 * the TX FIFO right away, and give the controller a moment
554 pThis->bSetAddress = FALSE;
555 pThis->ackpend = MGC_M_CSR0_P_SVDRXPKTRDY;
556 if (req->wLength == 0) {
557 if (req->bRequestType & USB_DIR_IN)
558 pThis->ackpend |= MGC_M_CSR0_TXPKTRDY;
559 pThis->ep0_state = MGC_END0_STAGE_ACKWAIT;
560 } else if (req->bRequestType & USB_DIR_IN) {
561 pThis->ep0_state = MGC_END0_STAGE_TX;
562 musb_writew(regs, MGC_O_HDRC_CSR0, MGC_M_CSR0_P_SVDRXPKTRDY);
563 while ((musb_readw(regs, MGC_O_HDRC_CSR0)
564 & MGC_M_CSR0_RXPKTRDY) != 0)
568 pThis->ep0_state = MGC_END0_STAGE_RX;
572 forward_to_driver(struct musb *musb,
573 const struct usb_ctrlrequest *pControlRequest)
574 __releases(musb->Lock)
575 __acquires(musb->Lock)
578 if (!musb->pGadgetDriver)
580 spin_unlock(&musb->Lock);
581 retval = musb->pGadgetDriver->setup(&musb->g, pControlRequest);
582 spin_lock(&musb->Lock);
587 * Handle peripheral ep0 interrupt
590 * Context: irq handler; we won't re-enter the driver that way.
592 irqreturn_t musb_g_ep0_irq(struct musb *pThis)
596 void __iomem *pBase = pThis->pRegs;
597 void __iomem *regs = pThis->aLocalEnd[0].regs;
598 irqreturn_t retval = IRQ_NONE;
600 MGC_SelectEnd(pBase, 0); /* select ep0 */
601 wCsrVal = musb_readw(regs, MGC_O_HDRC_CSR0);
602 wCount = musb_readb(regs, MGC_O_HDRC_COUNT0);
604 DBG(4, "csr %04x, count %d, myaddr %d, ep0stage %s\n",
606 musb_readb(pBase, MGC_O_HDRC_FADDR),
607 decode_ep0stage(pThis->ep0_state));
609 /* I sent a stall.. need to acknowledge it now.. */
610 if (wCsrVal & MGC_M_CSR0_P_SENTSTALL) {
611 musb_writew(regs, MGC_O_HDRC_CSR0,
612 wCsrVal & ~MGC_M_CSR0_P_SENTSTALL);
613 retval = IRQ_HANDLED;
614 pThis->ep0_state = MGC_END0_STAGE_SETUP;
615 wCsrVal = musb_readw(regs, MGC_O_HDRC_CSR0);
618 /* request ended "early" */
619 if (wCsrVal & MGC_M_CSR0_P_SETUPEND) {
620 musb_writew(regs, MGC_O_HDRC_CSR0, MGC_M_CSR0_P_SVDSETUPEND);
621 retval = IRQ_HANDLED;
622 pThis->ep0_state = MGC_END0_STAGE_SETUP;
623 wCsrVal = musb_readw(regs, MGC_O_HDRC_CSR0);
624 /* NOTE: request may need completion */
627 /* docs from Mentor only describe tx, rx, and idle/setup states.
628 * we need to handle nuances around status stages, and also the
629 * case where status and setup stages come back-to-back ...
631 switch (pThis->ep0_state) {
633 case MGC_END0_STAGE_TX:
634 /* irq on clearing txpktrdy */
635 if ((wCsrVal & MGC_M_CSR0_TXPKTRDY) == 0) {
637 retval = IRQ_HANDLED;
641 case MGC_END0_STAGE_RX:
642 /* irq on set rxpktrdy */
643 if (wCsrVal & MGC_M_CSR0_RXPKTRDY) {
645 retval = IRQ_HANDLED;
649 case MGC_END0_STAGE_STATUSIN:
650 /* end of sequence #2 (OUT/RX state) or #3 (no data) */
652 /* update address (if needed) only @ the end of the
653 * status phase per usb spec, which also guarantees
654 * we get 10 msec to receive this irq... until this
655 * is done we won't see the next packet.
657 if (pThis->bSetAddress) {
658 pThis->bSetAddress = FALSE;
659 musb_writeb(pBase, MGC_O_HDRC_FADDR, pThis->bAddress);
662 /* enter test mode if needed (exit by reset) */
663 else if (pThis->bTestMode) {
664 DBG(1, "entering TESTMODE\n");
666 if (MGC_M_TEST_PACKET == pThis->bTestModeValue)
667 musb_load_testpacket(pThis);
669 musb_writeb(pBase, MGC_O_HDRC_TESTMODE,
670 pThis->bTestModeValue);
674 case MGC_END0_STAGE_STATUSOUT:
675 /* end of sequence #1: write to host (TX state) */
677 struct usb_request *req;
679 req = next_ep0_request(pThis);
681 musb_g_ep0_giveback(pThis, req);
683 retval = IRQ_HANDLED;
684 pThis->ep0_state = MGC_END0_STAGE_SETUP;
687 case MGC_END0_STAGE_SETUP:
688 if (wCsrVal & MGC_M_CSR0_RXPKTRDY) {
689 struct usb_ctrlrequest setup;
693 ERR("SETUP packet len %d != 8 ?\n", wCount);
696 musb_read_setup(pThis, &setup);
697 retval = IRQ_HANDLED;
699 /* sometimes the RESET won't be reported */
700 if (unlikely(pThis->g.speed == USB_SPEED_UNKNOWN)) {
703 printk(KERN_NOTICE "%s: peripheral reset "
706 power = musb_readb(pBase, MGC_O_HDRC_POWER);
707 pThis->g.speed = (power & MGC_M_POWER_HSMODE)
708 ? USB_SPEED_HIGH : USB_SPEED_FULL;
712 switch (pThis->ep0_state) {
714 /* sequence #3 (no data stage), includes requests
715 * we can't forward (notably SET_ADDRESS and the
716 * device/endpoint feature set/clear operations)
717 * plus SET_CONFIGURATION and others we must
719 case MGC_END0_STAGE_ACKWAIT:
720 handled = service_zero_data_request(
723 /* status stage might be immediate */
725 pThis->ackpend |= MGC_M_CSR0_P_DATAEND;
727 MGC_END0_STAGE_STATUSIN;
731 /* sequence #1 (IN to host), includes GET_STATUS
732 * requests that we can't forward, GET_DESCRIPTOR
733 * and others that we must
735 case MGC_END0_STAGE_TX:
736 handled = service_in_request(pThis, &setup);
738 pThis->ackpend = MGC_M_CSR0_TXPKTRDY
739 | MGC_M_CSR0_P_DATAEND;
741 MGC_END0_STAGE_STATUSOUT;
745 /* sequence #2 (OUT from host), always forward */
746 default: /* MGC_END0_STAGE_RX */
750 DBG(3, "handled %d, csr %04x, ep0stage %s\n",
752 decode_ep0stage(pThis->ep0_state));
754 /* unless we need to delegate this to the gadget
755 * driver, we know how to wrap this up: csr0 has
756 * not yet been written.
760 else if (handled > 0)
763 handled = forward_to_driver(pThis, &setup);
765 MGC_SelectEnd(pBase, 0);
767 DBG(3, "stall (%d)\n", handled);
768 pThis->ackpend |= MGC_M_CSR0_P_SENDSTALL;
769 pThis->ep0_state = MGC_END0_STAGE_SETUP;
771 musb_writew(regs, MGC_O_HDRC_CSR0,
778 case MGC_END0_STAGE_ACKWAIT:
779 /* This should not happen. But happens with tusb6010 with
780 * g_file_storage and high speed. Do nothing.
782 retval = IRQ_HANDLED;
788 musb_writew(regs, MGC_O_HDRC_CSR0, MGC_M_CSR0_P_SENDSTALL);
789 pThis->ep0_state = MGC_END0_STAGE_SETUP;
798 musb_g_ep0_enable(struct usb_ep *ep, const struct usb_endpoint_descriptor *desc)
804 static int musb_g_ep0_disable(struct usb_ep *e)
810 static void *musb_g_ep0_alloc_buffer(struct usb_ep *ep, unsigned bytes,
811 dma_addr_t * dma, gfp_t gfp_flags)
813 *dma = DMA_ADDR_INVALID;
814 return kmalloc(bytes, gfp_flags);
817 static void musb_g_ep0_free_buffer(struct usb_ep *ep, void *address,
818 dma_addr_t dma, unsigned bytes)
824 musb_g_ep0_queue(struct usb_ep *e, struct usb_request *r, gfp_t gfp_flags)
827 struct musb_request *req;
830 unsigned long lockflags;
838 regs = musb->control_ep->regs;
840 req = to_musb_request(r);
842 req->request.actual = 0;
843 req->request.status = -EINPROGRESS;
844 req->bTx = ep->is_in;
846 spin_lock_irqsave(&musb->Lock, lockflags);
848 if (!list_empty(&ep->req_list)) {
853 switch (musb->ep0_state) {
854 case MGC_END0_STAGE_RX: /* control-OUT data */
855 case MGC_END0_STAGE_TX: /* control-IN data */
856 case MGC_END0_STAGE_ACKWAIT: /* zero-length data */
860 DBG(1, "ep0 request queued in state %d\n",
866 /* add request to the list */
867 list_add_tail(&(req->request.list), &(ep->req_list));
869 DBG(3, "queue to %s (%s), length=%d\n",
870 ep->name, ep->is_in ? "IN/TX" : "OUT/RX",
871 req->request.length);
873 MGC_SelectEnd(musb->pRegs, 0);
875 /* sequence #1, IN ... start writing the data */
876 if (musb->ep0_state == MGC_END0_STAGE_TX)
879 /* sequence #3, no-data ... issue IN status */
880 else if (musb->ep0_state == MGC_END0_STAGE_ACKWAIT) {
881 if (req->request.length)
884 musb->ep0_state = MGC_END0_STAGE_STATUSIN;
885 musb_writew(regs, MGC_O_HDRC_CSR0,
886 musb->ackpend | MGC_M_CSR0_P_DATAEND);
888 musb_g_ep0_giveback(ep->pThis, r);
891 /* else for sequence #2 (OUT), caller provides a buffer
892 * before the next packet arrives. deferred responses
893 * (after SETUP is acked) are racey.
895 } else if (musb->ackpend) {
896 musb_writew(regs, MGC_O_HDRC_CSR0, musb->ackpend);
901 spin_unlock_irqrestore(&musb->Lock, lockflags);
906 musb_g_ep0_dequeue(struct usb_ep *ep, struct usb_request *req)
908 /* we just won't support this */
912 static int musb_g_ep0_halt(struct usb_ep *e, int value)
916 void __iomem *base, *regs;
927 regs = musb->control_ep->regs;
929 spin_lock_irqsave(&musb->Lock, flags);
931 if (!list_empty(&ep->req_list)) {
936 switch (musb->ep0_state) {
937 case MGC_END0_STAGE_TX: /* control-IN data */
938 case MGC_END0_STAGE_ACKWAIT: /* STALL for zero-length data */
939 case MGC_END0_STAGE_RX: /* control-OUT data */
942 MGC_SelectEnd(base, 0);
943 csr = musb_readw(regs, MGC_O_HDRC_CSR0);
944 csr |= MGC_M_CSR0_P_SENDSTALL;
945 musb_writew(regs, MGC_O_HDRC_CSR0, csr);
946 musb->ep0_state = MGC_END0_STAGE_SETUP;
949 DBG(1, "ep0 can't halt in state %d\n", musb->ep0_state);
954 spin_unlock_irqrestore(&musb->Lock, flags);
958 const struct usb_ep_ops musb_g_ep0_ops = {
959 .enable = musb_g_ep0_enable,
960 .disable = musb_g_ep0_disable,
961 .alloc_request = musb_alloc_request,
962 .free_request = musb_free_request,
963 .alloc_buffer = musb_g_ep0_alloc_buffer,
964 .free_buffer = musb_g_ep0_free_buffer,
965 .queue = musb_g_ep0_queue,
966 .dequeue = musb_g_ep0_dequeue,
967 .set_halt = musb_g_ep0_halt,