drivers/usb/musb/g_ep0.c

   1 /******************************************************************
   2  * Copyright 2005 Mentor Graphics Corporation
   3  * Copyright (C) 2005-2006 by Texas Instruments
   4  *
   5  * This file is part of the Inventra Controller Driver for Linux.
   6  *
   7  * The Inventra Controller Driver for Linux is free software; you
   8  * can redistribute it and/or modify it under the terms of the GNU
   9  * General Public License version 2 as published by the Free Software
  10  * Foundation.
  11  *
  12  * The Inventra Controller Driver for Linux is distributed in
  13  * the hope that it will be useful, but WITHOUT ANY WARRANTY;
  14  * without even the implied warranty of MERCHANTABILITY or
  15  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  16  * License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with The Inventra Controller Driver for Linux ; if not,
  20  * write to the Free Software Foundation, Inc., 59 Temple Place,
  21  * Suite 330, Boston, MA  02111-1307  USA
  22  *
  23  * ANY DOWNLOAD, USE, REPRODUCTION, MODIFICATION OR DISTRIBUTION
  24  * OF THIS DRIVER INDICATES YOUR COMPLETE AND UNCONDITIONAL ACCEPTANCE
  25  * OF THOSE TERMS.THIS DRIVER IS PROVIDED "AS IS" AND MENTOR GRAPHICS
  26  * MAKES NO WARRANTIES, EXPRESS OR IMPLIED, RELATED TO THIS DRIVER.
  27  * MENTOR GRAPHICS SPECIFICALLY DISCLAIMS ALL IMPLIED WARRANTIES
  28  * OF MERCHANTABILITY; FITNESS FOR A PARTICULAR PURPOSE AND
  29  * NON-INFRINGEMENT.  MENTOR GRAPHICS DOES NOT PROVIDE SUPPORT
  30  * SERVICES OR UPDATES FOR THIS DRIVER, EVEN IF YOU ARE A MENTOR
  31  * GRAPHICS SUPPORT CUSTOMER.
  32  ******************************************************************/
  33
  34 #include <linux/kernel.h>
  35 #include <linux/list.h>
  36 #include <linux/timer.h>
  37 #include <linux/spinlock.h>
  38 #include <linux/init.h>
  39 #include <linux/device.h>
  40 #include <linux/interrupt.h>
  41
  42 #include "musbdefs.h"
  43
  44 /* ep0 is always musb->aLocalEnd[0].ep_in */
  45 #define next_ep0_request(musb)  next_in_request(&(musb)->aLocalEnd[0])
  46
  47 /*
  48  * Locking note:  we use only the controller lock, for simpler correctness.
  49  * It's always held with IRQs blocked.
  50  *
  51  * It protects the ep0 request queue as well as ep0_state, not just the
  52  * controller and indexed registers.  And that lock stays held unless it
  53  * needs to be dropped to allow reentering this driver ... like upcalls to
  54  * the gadget driver, or adjusting endpoint halt status.
  55  */
  56
  57 static char *decode_ep0stage(u8 stage)
  58 {
  59         switch(stage) {
  60         case MGC_END0_STAGE_SETUP:      return "idle";
  61         case MGC_END0_STAGE_TX:         return "in";
  62         case MGC_END0_STAGE_RX:         return "out";
  63         case MGC_END0_STAGE_ACKWAIT:    return "wait";
  64         case MGC_END0_STAGE_STATUSIN:   return "in/status";
  65         case MGC_END0_STAGE_STATUSOUT:  return "out/status";
  66         default:                        return "?";
  67         }
  68 }
  69
  70 /* handle a standard GET_STATUS request
  71  * Context:  caller holds controller lock
  72  */
  73 static int service_tx_status_request(
  74         struct musb *musb,
  75         const struct usb_ctrlrequest *pControlRequest)
  76 {
  77         void __iomem    *pBase = musb->pRegs;
  78         int handled = 1;
  79         u8 bResult[2], bEnd = 0;
  80         const u8 bRecip = pControlRequest->bRequestType & USB_RECIP_MASK;
  81
  82         bResult[1] = 0;
  83
  84         switch (bRecip) {
  85         case USB_RECIP_DEVICE:
  86                 bResult[0] = musb->is_self_powered << USB_DEVICE_SELF_POWERED;
  87                 bResult[0] |= musb->may_wakeup << USB_DEVICE_REMOTE_WAKEUP;
  88 #ifdef CONFIG_USB_MUSB_OTG
  89                 if (musb->g.is_otg) {
  90                         bResult[0] |= musb->g.b_hnp_enable
  91                                 << USB_DEVICE_B_HNP_ENABLE;
  92                         bResult[0] |= musb->g.a_alt_hnp_support
  93                                 << USB_DEVICE_A_ALT_HNP_SUPPORT;
  94                         bResult[0] |= musb->g.a_hnp_support
  95                                 << USB_DEVICE_A_HNP_SUPPORT;
  96                 }
  97 #endif
  98                 break;
  99
 100         case USB_RECIP_INTERFACE:
 101                 bResult[0] = 0;
 102                 break;
 103
 104         case USB_RECIP_ENDPOINT: {
 105                 int             is_in;
 106                 struct musb_ep  *ep;
 107                 u16             tmp;
 108                 void __iomem    *regs;
 109
 110                 bEnd = (u8) pControlRequest->wIndex;
 111                 if (!bEnd) {
 112                         bResult[0] = 0;
 113                         break;
 114                 }
 115
 116                 is_in = bEnd & USB_DIR_IN;
 117                 if (is_in) {
 118                         bEnd &= 0x0f;
 119                         ep = &musb->aLocalEnd[bEnd].ep_in;
 120                 } else {
 121                         ep = &musb->aLocalEnd[bEnd].ep_out;
 122                 }
 123                 regs = musb->aLocalEnd[bEnd].regs;
 124
 125                 if (bEnd >= MUSB_C_NUM_EPS || !ep->desc) {
 126                         handled = -EINVAL;
 127                         break;
 128                 }
 129
 130                 MGC_SelectEnd(pBase, bEnd);
 131                 if (is_in)
 132                         tmp = musb_readw(regs, MGC_O_HDRC_TXCSR)
 133                                                 & MGC_M_TXCSR_P_SENDSTALL;
 134                 else
 135                         tmp = musb_readw(regs, MGC_O_HDRC_RXCSR)
 136                                                 & MGC_M_RXCSR_P_SENDSTALL;
 137                 MGC_SelectEnd(pBase, 0);
 138
 139                 bResult[0] = tmp ? 1 : 0;
 140                 } break;
 141
 142         default:
 143                 /* class, vendor, etc ... delegate */
 144                 handled = 0;
 145                 break;
 146         }
 147
 148         /* fill up the fifo; caller updates csr0 */
 149         if (handled > 0) {
 150                 u16     len = le16_to_cpu(pControlRequest->wLength);
 151
 152                 if (len > 2)
 153                         len = 2;
 154                 musb_write_fifo(&musb->aLocalEnd[0], len, bResult);
 155         }
 156
 157         return handled;
 158 }
 159
 160 /*
 161  * handle a control-IN request, the end0 buffer contains the current request
 162  * that is supposed to be a standard control request. Assumes the fifo to
 163  * be at least 2 bytes long.
 164  *
 165  * @return 0 if the request was NOT HANDLED,
 166  * < 0 when error
 167  * > 0 when the request is processed
 168  *
 169  * Context:  caller holds controller lock
 170  */
 171 static int
 172 service_in_request(struct musb *musb,
 173                 const struct usb_ctrlrequest *pControlRequest)
 174 {
 175         int handled = 0;        /* not handled */
 176
 177         if ((pControlRequest->bRequestType & USB_TYPE_MASK)
 178                         == USB_TYPE_STANDARD) {
 179                 switch (pControlRequest->bRequest) {
 180                 case USB_REQ_GET_STATUS:
 181                         handled = service_tx_status_request(musb,
 182                                         pControlRequest);
 183                         break;
 184
 185                 /* case USB_REQ_SYNC_FRAME: */
 186
 187                 default:
 188                         break;
 189                 }
 190         }
 191         return handled;
 192 }
 193
 194 /*
 195  * Context:  caller holds controller lock
 196  */
 197 static void musb_g_ep0_giveback(struct musb *musb, struct usb_request *req)
 198 {
 199         musb->ep0_state = MGC_END0_STAGE_SETUP;
 200         musb_g_giveback(&musb->aLocalEnd[0].ep_in, req, 0);
 201 }
 202
 203 /*
 204  * Handle all control requests with no DATA stage, including standard
 205  * requests such as:
 206  * USB_REQ_SET_CONFIGURATION, USB_REQ_SET_INTERFACE, unrecognized
 207  *      always delegated to the gadget driver
 208  * USB_REQ_SET_ADDRESS, USB_REQ_CLEAR_FEATURE, USB_REQ_SET_FEATURE
 209  *      always handled here, except for class/vendor/... features
 210  *
 211  * Context:  caller holds controller lock
 212  */
 213 static int
 214 service_zero_data_request(struct musb *musb,
 215                 struct usb_ctrlrequest *pControlRequest)
 216 __releases(musb->Lock)
 217 __acquires(musb->Lock)
 218 {
 219         int handled = -EINVAL;
 220         void __iomem *pBase = musb->pRegs;
 221         const u8 bRecip = pControlRequest->bRequestType & USB_RECIP_MASK;
 222
 223         /* the gadget driver handles everything except what we MUST handle */
 224         if ((pControlRequest->bRequestType & USB_TYPE_MASK)
 225                         == USB_TYPE_STANDARD) {
 226                 switch (pControlRequest->bRequest) {
 227                 case USB_REQ_SET_ADDRESS:
 228                         /* change it after the status stage */
 229                         musb->bSetAddress = TRUE;
 230                         musb->bAddress = (u8) (pControlRequest->wValue & 0x7f);
 231                         handled = 1;
 232                         break;
 233
 234                 case USB_REQ_CLEAR_FEATURE:
 235                         switch (bRecip) {
 236                         case USB_RECIP_DEVICE:
 237                                 if (pControlRequest->wValue
 238                                                 != USB_DEVICE_REMOTE_WAKEUP)
 239                                         break;
 240                                 musb->may_wakeup = 0;
 241                                 handled = 1;
 242                                 break;
 243                         case USB_RECIP_INTERFACE:
 244                                 break;
 245                         case USB_RECIP_ENDPOINT:{
 246                                 const u8 bEnd = pControlRequest->wIndex & 0x0f;
 247                                 struct musb_ep *pEnd;
 248
 249                                 if (bEnd == 0
 250                                                 || bEnd >= MUSB_C_NUM_EPS
 251                                                 || pControlRequest->wValue
 252                                                         != USB_ENDPOINT_HALT)
 253                                         break;
 254
 255                                 if (pControlRequest->wIndex & USB_DIR_IN)
 256                                         pEnd = &musb->aLocalEnd[bEnd].ep_in;
 257                                 else
 258                                         pEnd = &musb->aLocalEnd[bEnd].ep_out;
 259                                 if (!pEnd->desc)
 260                                         break;
 261
 262                                 /* REVISIT do it directly, no locking games */
 263                                 spin_unlock(&musb->Lock);
 264                                 musb_gadget_set_halt(&pEnd->end_point, 0);
 265                                 spin_lock(&musb->Lock);
 266
 267                                 /* select ep0 again */
 268                                 MGC_SelectEnd(pBase, 0);
 269                                 handled = 1;
 270                                 } break;
 271                         default:
 272                                 /* class, vendor, etc ... delegate */
 273                                 handled = 0;
 274                                 break;
 275                         }
 276                         break;
 277
 278                 case USB_REQ_SET_FEATURE:
 279                         switch (bRecip) {
 280                         case USB_RECIP_DEVICE:
 281                                 handled = 1;
 282                                 switch (pControlRequest->wValue) {
 283                                 case USB_DEVICE_REMOTE_WAKEUP:
 284                                         musb->may_wakeup = 1;
 285                                         break;
 286                                 case USB_DEVICE_TEST_MODE:
 287                                         if (musb->g.speed != USB_SPEED_HIGH)
 288                                                 goto stall;
 289                                         if (pControlRequest->wIndex & 0xff)
 290                                                 goto stall;
 291
 292                                         switch (pControlRequest->wIndex >> 8) {
 293                                         case 1:
 294                                                 pr_debug("TEST_J\n");
 295                                                 /* TEST_J */
 296                                                 musb->bTestModeValue =
 297                                                         MGC_M_TEST_J;
 298                                                 break;
 299                                         case 2:
 300                                                 /* TEST_K */
 301                                                 pr_debug("TEST_K\n");
 302                                                 musb->bTestModeValue =
 303                                                         MGC_M_TEST_K;
 304                                                 break;
 305                                         case 3:
 306                                                 /* TEST_SE0_NAK */
 307                                                 pr_debug("TEST_SE0_NAK\n");
 308                                                 musb->bTestModeValue =
 309                                                         MGC_M_TEST_SE0_NAK;
 310                                                 break;
 311                                         case 4:
 312                                                 /* TEST_PACKET */
 313                                                 pr_debug("TEST_PACKET\n");
 314                                                 musb->bTestModeValue =
 315                                                         MGC_M_TEST_PACKET;
 316                                                 break;
 317                                         default:
 318                                                 goto stall;
 319                                         }
 320
 321                                         /* enter test mode after irq */
 322                                         if (handled > 0)
 323                                                 musb->bTestMode = TRUE;
 324                                         break;
 325 #ifdef CONFIG_USB_MUSB_OTG
 326                                 case USB_DEVICE_B_HNP_ENABLE:
 327                                         if (!musb->g.is_otg)
 328                                                 goto stall;
 329                                         { u8 devctl;
 330                                         musb->g.b_hnp_enable = 1;
 331                                         devctl = musb_readb(pBase,
 332                                                         MGC_O_HDRC_DEVCTL);
 333                                         /* NOTE:  at least DaVinci doesn't
 334                                          * like to set HR ...
 335                                          */
 336                                         DBG(1, "set HR\n");
 337                                         musb_writeb(pBase, MGC_O_HDRC_DEVCTL,
 338                                                 devctl | MGC_M_DEVCTL_HR);
 339                                         }
 340                                         break;
 341                                 case USB_DEVICE_A_HNP_SUPPORT:
 342                                         if (!musb->g.is_otg)
 343                                                 goto stall;
 344                                         musb->g.a_hnp_support = 1;
 345                                         break;
 346                                 case USB_DEVICE_A_ALT_HNP_SUPPORT:
 347                                         if (!musb->g.is_otg)
 348                                                 goto stall;
 349                                         musb->g.a_alt_hnp_support = 1;
 350                                         break;
 351 #endif
 352 stall:
 353                                 default:
 354                                         handled = -EINVAL;
 355                                         break;
 356                                 }
 357                                 break;
 358
 359                         case USB_RECIP_INTERFACE:
 360                                 break;
 361
 362                         case USB_RECIP_ENDPOINT:{
 363                                 const u8                bEnd =
 364                                         pControlRequest->wIndex & 0x0f;
 365                                 struct musb_ep          *pEnd;
 366                                 struct musb_hw_ep       *ep;
 367                                 void __iomem            *regs;
 368                                 int                     is_in;
 369                                 u16                     csr;
 370
 371                                 if (bEnd == 0
 372                                                 || bEnd >= MUSB_C_NUM_EPS
 373                                                 || pControlRequest->wValue
 374                                                         != USB_ENDPOINT_HALT)
 375                                         break;
 376
 377                                 ep = musb->aLocalEnd + bEnd;
 378                                 regs = ep->regs;
 379                                 is_in = pControlRequest->wIndex & USB_DIR_IN;
 380                                 if (is_in)
 381                                         pEnd = &ep->ep_in;
 382                                 else
 383                                         pEnd = &ep->ep_out;
 384                                 if (!pEnd->desc)
 385                                         break;
 386
 387                                 MGC_SelectEnd(pBase, bEnd);
 388                                 if (is_in) {
 389                                         csr = musb_readw(regs,
 390                                                         MGC_O_HDRC_TXCSR);
 391                                         if (csr & MGC_M_TXCSR_FIFONOTEMPTY)
 392                                                 csr |= MGC_M_TXCSR_FLUSHFIFO;
 393                                         csr |= MGC_M_TXCSR_P_SENDSTALL
 394                                                 | MGC_M_TXCSR_CLRDATATOG
 395                                                 | MGC_M_TXCSR_P_WZC_BITS;
 396                                         musb_writew(regs, MGC_O_HDRC_TXCSR,
 397                                                         csr);
 398                                 } else {
 399                                         csr = musb_readw(regs,
 400                                                         MGC_O_HDRC_RXCSR);
 401                                         csr |= MGC_M_RXCSR_P_SENDSTALL
 402                                                 | MGC_M_RXCSR_FLUSHFIFO
 403                                                 | MGC_M_RXCSR_CLRDATATOG
 404                                                 | MGC_M_TXCSR_P_WZC_BITS;
 405                                         musb_writew(regs, MGC_O_HDRC_RXCSR,
 406                                                         csr);
 407                                 }
 408
 409                                 /* select ep0 again */
 410                                 MGC_SelectEnd(pBase, 0);
 411                                 handled = 1;
 412                                 } break;
 413
 414                         default:
 415                                 /* class, vendor, etc ... delegate */
 416                                 handled = 0;
 417                                 break;
 418                         }
 419                         break;
 420                 default:
 421                         /* delegate SET_CONFIGURATION, etc */
 422                         handled = 0;
 423                 }
 424         } else
 425                 handled = 0;
 426         return handled;
 427 }
 428
 429 /* we have an ep0out data packet
 430  * Context:  caller holds controller lock
 431  */
 432 static void ep0_rxstate(struct musb *this)
 433 {
 434         void __iomem            *regs = this->control_ep->regs;
 435         struct usb_request      *req;
 436         u16                     tmp;
 437
 438         req = next_ep0_request(this);
 439
 440         /* read packet and ack; or stall because of gadget driver bug:
 441          * should have provided the rx buffer before setup() returned.
 442          */
 443         if (req) {
 444                 void            *buf = req->buf + req->actual;
 445                 unsigned        len = req->length - req->actual;
 446
 447                 /* read the buffer */
 448                 tmp = musb_readb(regs, MGC_O_HDRC_COUNT0);
 449                 if (tmp > len) {
 450                         req->status = -EOVERFLOW;
 451                         tmp = len;
 452                 }
 453                 musb_read_fifo(&this->aLocalEnd[0], tmp, buf);
 454                 req->actual += tmp;
 455                 tmp = MGC_M_CSR0_P_SVDRXPKTRDY;
 456                 if (tmp < 64 || req->actual == req->length) {
 457                         this->ep0_state = MGC_END0_STAGE_STATUSIN;
 458                         tmp |= MGC_M_CSR0_P_DATAEND;
 459                 } else
 460                         req = NULL;
 461         } else
 462                 tmp = MGC_M_CSR0_P_SVDRXPKTRDY | MGC_M_CSR0_P_SENDSTALL;
 463         musb_writew(regs, MGC_O_HDRC_CSR0, tmp);
 464
 465
 466         /* NOTE:  we "should" hold off reporting DATAEND and going to
 467          * STATUSIN until after the completion handler decides whether
 468          * to issue a stall instead, since this hardware can do that.
 469          */
 470         if (req)
 471                 musb_g_ep0_giveback(this, req);
 472 }
 473
 474 /*
 475  * transmitting to the host (IN), this code might be called from IRQ
 476  * and from kernel thread.
 477  *
 478  * Context:  caller holds controller lock
 479  */
 480 static void ep0_txstate(struct musb *musb)
 481 {
 482         void __iomem            *regs = musb->control_ep->regs;
 483         struct usb_request      *pRequest = next_ep0_request(musb);
 484         u16                     wCsrVal = MGC_M_CSR0_TXPKTRDY;
 485         u8                      *pFifoSource;
 486         u8                      wFifoCount;
 487
 488         if (!pRequest) {
 489                 // WARN_ON(1);
 490                 DBG(2, "odd; csr0 %04x\n", musb_readw(regs, MGC_O_HDRC_CSR0));
 491                 return;
 492         }
 493
 494         /* load the data */
 495         pFifoSource = (u8 *) pRequest->buf + pRequest->actual;
 496         wFifoCount = min((unsigned) MGC_END0_FIFOSIZE,
 497                 pRequest->length - pRequest->actual);
 498         musb_write_fifo(&musb->aLocalEnd[0], wFifoCount, pFifoSource);
 499         pRequest->actual += wFifoCount;
 500
 501         /* update the flags */
 502         if (wFifoCount < MUSB_MAX_END0_PACKET
 503                         || pRequest->actual == pRequest->length) {
 504                 musb->ep0_state = MGC_END0_STAGE_STATUSOUT;
 505                 wCsrVal |= MGC_M_CSR0_P_DATAEND;
 506         } else
 507                 pRequest = NULL;
 508
 509         /* send it out, triggering a "txpktrdy cleared" irq */
 510         musb_writew(regs, MGC_O_HDRC_CSR0, wCsrVal);
 511
 512         /* report completions as soon as the fifo's loaded; there's no
 513          * win in waiting till this last packet gets acked.  (other than
 514          * very precise fault reporting, needed by USB TMC; possible with
 515          * this hardware, but not usable from portable gadget drivers.)
 516          */
 517         if (pRequest)
 518                 musb_g_ep0_giveback(musb, pRequest);
 519 }
 520
 521 /*
 522  * Read a SETUP packet (struct usb_ctrlrequest) from the hardware.
 523  * Fields are left in USB byte-order.
 524  *
 525  * Context:  caller holds controller lock.
 526  */
 527 static void
 528 musb_read_setup(struct musb *musb, struct usb_ctrlrequest *req)
 529 {
 530         struct usb_request      *r;
 531         void __iomem            *regs = musb->control_ep->regs;
 532
 533         musb_read_fifo(&musb->aLocalEnd[0], sizeof *req, (u8 *)req);
 534
 535         /* NOTE:  earlier 2.6 versions changed setup packets to host
 536          * order, but now USB packets always stay in USB byte order.
 537          */
 538         DBG(3, "SETUP req%02x.%02x v%04x i%04x l%d\n",
 539                 req->bRequestType,
 540                 req->bRequest,
 541                 le16_to_cpu(req->wValue),
 542                 le16_to_cpu(req->wIndex),
 543                 le16_to_cpu(req->wLength));
 544
 545         /* clean up any leftover transfers */
 546         r = next_ep0_request(musb);
 547         if (r)
 548                 musb_g_ep0_giveback(musb, r);
 549
 550         /* For zero-data requests we want to delay the STATUS stage to
 551          * avoid SETUPEND errors.  If we read data (OUT), delay accepting
 552          * packets until there's a buffer to store them in.
 553          *
 554          * If we write data, the controller acts happier if we enable
 555          * the TX FIFO right away, and give the controller a moment
 556          * to switch modes...
 557          */
 558         musb->bSetAddress = FALSE;
 559         musb->ackpend = MGC_M_CSR0_P_SVDRXPKTRDY;
 560         if (req->wLength == 0) {
 561                 if (req->bRequestType & USB_DIR_IN)
 562                         musb->ackpend |= MGC_M_CSR0_TXPKTRDY;
 563                 musb->ep0_state = MGC_END0_STAGE_ACKWAIT;
 564         } else if (req->bRequestType & USB_DIR_IN) {
 565                 musb->ep0_state = MGC_END0_STAGE_TX;
 566                 musb_writew(regs, MGC_O_HDRC_CSR0, MGC_M_CSR0_P_SVDRXPKTRDY);
 567                 while ((musb_readw(regs, MGC_O_HDRC_CSR0)
 568                                 & MGC_M_CSR0_RXPKTRDY) != 0)
 569                         cpu_relax();
 570                 musb->ackpend = 0;
 571         } else
 572                 musb->ep0_state = MGC_END0_STAGE_RX;
 573 }
 574
 575 static int
 576 forward_to_driver(struct musb *musb,
 577                 const struct usb_ctrlrequest *pControlRequest)
 578 __releases(musb->Lock)
 579 __acquires(musb->Lock)
 580 {
 581         int retval;
 582         if (!musb->pGadgetDriver)
 583                 return -EOPNOTSUPP;
 584         spin_unlock(&musb->Lock);
 585         retval = musb->pGadgetDriver->setup(&musb->g, pControlRequest);
 586         spin_lock(&musb->Lock);
 587         return retval;
 588 }
 589
 590 /*
 591  * Handle peripheral ep0 interrupt
 592  *
 593  * Context: irq handler; we won't re-enter the driver that way.
 594  */
 595 irqreturn_t musb_g_ep0_irq(struct musb *musb)
 596 {
 597         u16             wCsrVal;
 598         u16             wCount;
 599         void __iomem    *pBase = musb->pRegs;
 600         void __iomem    *regs = musb->aLocalEnd[0].regs;
 601         irqreturn_t     retval = IRQ_NONE;
 602
 603         MGC_SelectEnd(pBase, 0);        /* select ep0 */
 604         wCsrVal = musb_readw(regs, MGC_O_HDRC_CSR0);
 605         wCount = musb_readb(regs, MGC_O_HDRC_COUNT0);
 606
 607         DBG(4, "csr %04x, count %d, myaddr %d, ep0stage %s\n",
 608                         wCsrVal, wCount,
 609                         musb_readb(pBase, MGC_O_HDRC_FADDR),
 610                         decode_ep0stage(musb->ep0_state));
 611
 612         /* I sent a stall.. need to acknowledge it now.. */
 613         if (wCsrVal & MGC_M_CSR0_P_SENTSTALL) {
 614                 musb_writew(regs, MGC_O_HDRC_CSR0,
 615                                 wCsrVal & ~MGC_M_CSR0_P_SENTSTALL);
 616                 retval = IRQ_HANDLED;
 617                 musb->ep0_state = MGC_END0_STAGE_SETUP;
 618                 wCsrVal = musb_readw(regs, MGC_O_HDRC_CSR0);
 619         }
 620
 621         /* request ended "early" */
 622         if (wCsrVal & MGC_M_CSR0_P_SETUPEND) {
 623                 musb_writew(regs, MGC_O_HDRC_CSR0, MGC_M_CSR0_P_SVDSETUPEND);
 624                 retval = IRQ_HANDLED;
 625                 musb->ep0_state = MGC_END0_STAGE_SETUP;
 626                 wCsrVal = musb_readw(regs, MGC_O_HDRC_CSR0);
 627                 /* NOTE:  request may need completion */
 628         }
 629
 630         /* docs from Mentor only describe tx, rx, and idle/setup states.
 631          * we need to handle nuances around status stages, and also the
 632          * case where status and setup stages come back-to-back ...
 633          */
 634         switch (musb->ep0_state) {
 635
 636         case MGC_END0_STAGE_TX:
 637                 /* irq on clearing txpktrdy */
 638                 if ((wCsrVal & MGC_M_CSR0_TXPKTRDY) == 0) {
 639                         ep0_txstate(musb);
 640                         retval = IRQ_HANDLED;
 641                 }
 642                 break;
 643
 644         case MGC_END0_STAGE_RX:
 645                 /* irq on set rxpktrdy */
 646                 if (wCsrVal & MGC_M_CSR0_RXPKTRDY) {
 647                         ep0_rxstate(musb);
 648                         retval = IRQ_HANDLED;
 649                 }
 650                 break;
 651
 652         case MGC_END0_STAGE_STATUSIN:
 653                 /* end of sequence #2 (OUT/RX state) or #3 (no data) */
 654
 655                 /* update address (if needed) only @ the end of the
 656                  * status phase per usb spec, which also guarantees
 657                  * we get 10 msec to receive this irq... until this
 658                  * is done we won't see the next packet.
 659                  */
 660                 if (musb->bSetAddress) {
 661                         musb->bSetAddress = FALSE;
 662                         musb_writeb(pBase, MGC_O_HDRC_FADDR, musb->bAddress);
 663                 }
 664
 665                 /* enter test mode if needed (exit by reset) */
 666                 else if (musb->bTestMode) {
 667                         DBG(1, "entering TESTMODE\n");
 668
 669                         if (MGC_M_TEST_PACKET == musb->bTestModeValue)
 670                                 musb_load_testpacket(musb);
 671
 672                         musb_writeb(pBase, MGC_O_HDRC_TESTMODE,
 673                                         musb->bTestModeValue);
 674                 }
 675                 /* FALLTHROUGH */
 676
 677         case MGC_END0_STAGE_STATUSOUT:
 678                 /* end of sequence #1: write to host (TX state) */
 679                 {
 680                         struct usb_request      *req;
 681
 682                         req = next_ep0_request(musb);
 683                         if (req)
 684                                 musb_g_ep0_giveback(musb, req);
 685                 }
 686                 retval = IRQ_HANDLED;
 687                 musb->ep0_state = MGC_END0_STAGE_SETUP;
 688                 /* FALLTHROUGH */
 689
 690         case MGC_END0_STAGE_SETUP:
 691                 if (wCsrVal & MGC_M_CSR0_RXPKTRDY) {
 692                         struct usb_ctrlrequest  setup;
 693                         int                     handled = 0;
 694
 695                         if (wCount != 8) {
 696                                 ERR("SETUP packet len %d != 8 ?\n", wCount);
 697                                 break;
 698                         }
 699                         musb_read_setup(musb, &setup);
 700                         retval = IRQ_HANDLED;
 701
 702                         /* sometimes the RESET won't be reported */
 703                         if (unlikely(musb->g.speed == USB_SPEED_UNKNOWN)) {
 704                                 u8      power;
 705
 706                                 printk(KERN_NOTICE "%s: peripheral reset "
 707                                                 "irq lost!\n",
 708                                                 musb_driver_name);
 709                                 power = musb_readb(pBase, MGC_O_HDRC_POWER);
 710                                 musb->g.speed = (power & MGC_M_POWER_HSMODE)
 711                                         ? USB_SPEED_HIGH : USB_SPEED_FULL;
 712
 713                         }
 714
 715                         switch (musb->ep0_state) {
 716
 717                         /* sequence #3 (no data stage), includes requests
 718                          * we can't forward (notably SET_ADDRESS and the
 719                          * device/endpoint feature set/clear operations)
 720                          * plus SET_CONFIGURATION and others we must
 721                          */
 722                         case MGC_END0_STAGE_ACKWAIT:
 723                                 handled = service_zero_data_request(
 724                                                 musb, &setup);
 725
 726                                 /* status stage might be immediate */
 727                                 if (handled > 0) {
 728                                         musb->ackpend |= MGC_M_CSR0_P_DATAEND;
 729                                         musb->ep0_state =
 730                                                 MGC_END0_STAGE_STATUSIN;
 731                                 }
 732                                 break;
 733
 734                         /* sequence #1 (IN to host), includes GET_STATUS
 735                          * requests that we can't forward, GET_DESCRIPTOR
 736                          * and others that we must
 737                          */
 738                         case MGC_END0_STAGE_TX:
 739                                 handled = service_in_request(musb, &setup);
 740                                 if (handled > 0) {
 741                                         musb->ackpend = MGC_M_CSR0_TXPKTRDY
 742                                                 | MGC_M_CSR0_P_DATAEND;
 743                                         musb->ep0_state =
 744                                                 MGC_END0_STAGE_STATUSOUT;
 745                                 }
 746                                 break;
 747
 748                         /* sequence #2 (OUT from host), always forward */
 749                         default:                /* MGC_END0_STAGE_RX */
 750                                 break;
 751                         }
 752
 753                         DBG(3, "handled %d, csr %04x, ep0stage %s\n",
 754                                 handled, wCsrVal,
 755                                 decode_ep0stage(musb->ep0_state));
 756
 757                         /* unless we need to delegate this to the gadget
 758                          * driver, we know how to wrap this up:  csr0 has
 759                          * not yet been written.
 760                          */
 761                         if (handled < 0)
 762                                 goto stall;
 763                         else if (handled > 0)
 764                                 goto finish;
 765
 766                         handled = forward_to_driver(musb, &setup);
 767                         if (handled < 0) {
 768                                 MGC_SelectEnd(pBase, 0);
 769 stall:
 770                                 DBG(3, "stall (%d)\n", handled);
 771                                 musb->ackpend |= MGC_M_CSR0_P_SENDSTALL;
 772                                 musb->ep0_state = MGC_END0_STAGE_SETUP;
 773 finish:
 774                                 musb_writew(regs, MGC_O_HDRC_CSR0,
 775                                                 musb->ackpend);
 776                                 musb->ackpend = 0;
 777                         }
 778                 }
 779                 break;
 780
 781         case MGC_END0_STAGE_ACKWAIT:
 782                 /* This should not happen. But happens with tusb6010 with
 783                  * g_file_storage and high speed. Do nothing.
 784                  */
 785                 retval = IRQ_HANDLED;
 786                 break;
 787
 788         default:
 789                 /* "can't happen" */
 790                 WARN_ON(1);
 791                 musb_writew(regs, MGC_O_HDRC_CSR0, MGC_M_CSR0_P_SENDSTALL);
 792                 musb->ep0_state = MGC_END0_STAGE_SETUP;
 793                 break;
 794         }
 795
 796         return retval;
 797 }
 798
 799
 800 static int
 801 musb_g_ep0_enable(struct usb_ep *ep, const struct usb_endpoint_descriptor *desc)
 802 {
 803         /* always enabled */
 804         return -EINVAL;
 805 }
 806
 807 static int musb_g_ep0_disable(struct usb_ep *e)
 808 {
 809         /* always enabled */
 810         return -EINVAL;
 811 }
 812
 813 static void *musb_g_ep0_alloc_buffer(struct usb_ep *ep, unsigned bytes,
 814                         dma_addr_t * dma, gfp_t gfp_flags)
 815 {
 816         *dma = DMA_ADDR_INVALID;
 817         return kmalloc(bytes, gfp_flags);
 818 }
 819
 820 static void musb_g_ep0_free_buffer(struct usb_ep *ep, void *address,
 821                         dma_addr_t dma, unsigned bytes)
 822 {
 823         kfree(address);
 824 }
 825
 826 static int
 827 musb_g_ep0_queue(struct usb_ep *e, struct usb_request *r, gfp_t gfp_flags)
 828 {
 829         struct musb_ep          *ep;
 830         struct musb_request     *req;
 831         struct musb             *musb;
 832         int                     status;
 833         unsigned long           lockflags;
 834         void __iomem            *regs;
 835
 836         if (!e || !r)
 837                 return -EINVAL;
 838
 839         ep = to_musb_ep(e);
 840         musb = ep->pThis;
 841         regs = musb->control_ep->regs;
 842
 843         req = to_musb_request(r);
 844         req->musb = musb;
 845         req->request.actual = 0;
 846         req->request.status = -EINPROGRESS;
 847         req->bTx = ep->is_in;
 848
 849         spin_lock_irqsave(&musb->Lock, lockflags);
 850
 851         if (!list_empty(&ep->req_list)) {
 852                 status = -EBUSY;
 853                 goto cleanup;
 854         }
 855
 856         switch (musb->ep0_state) {
 857         case MGC_END0_STAGE_RX:         /* control-OUT data */
 858         case MGC_END0_STAGE_TX:         /* control-IN data */
 859         case MGC_END0_STAGE_ACKWAIT:    /* zero-length data */
 860                 status = 0;
 861                 break;
 862         default:
 863                 DBG(1, "ep0 request queued in state %d\n",
 864                                 musb->ep0_state);
 865                 status = -EINVAL;
 866                 goto cleanup;
 867         }
 868
 869         /* add request to the list */
 870         list_add_tail(&(req->request.list), &(ep->req_list));
 871
 872         DBG(3, "queue to %s (%s), length=%d\n",
 873                         ep->name, ep->is_in ? "IN/TX" : "OUT/RX",
 874                         req->request.length);
 875
 876         MGC_SelectEnd(musb->pRegs, 0);
 877
 878         /* sequence #1, IN ... start writing the data */
 879         if (musb->ep0_state == MGC_END0_STAGE_TX)
 880                 ep0_txstate(musb);
 881
 882         /* sequence #3, no-data ... issue IN status */
 883         else if (musb->ep0_state == MGC_END0_STAGE_ACKWAIT) {
 884                 if (req->request.length)
 885                         status = -EINVAL;
 886                 else {
 887                         musb->ep0_state = MGC_END0_STAGE_STATUSIN;
 888                         musb_writew(regs, MGC_O_HDRC_CSR0,
 889                                         musb->ackpend | MGC_M_CSR0_P_DATAEND);
 890                         musb->ackpend = 0;
 891                         musb_g_ep0_giveback(ep->pThis, r);
 892                 }
 893
 894         /* else for sequence #2 (OUT), caller provides a buffer
 895          * before the next packet arrives.  deferred responses
 896          * (after SETUP is acked) are racey.
 897          */
 898         } else if (musb->ackpend) {
 899                 musb_writew(regs, MGC_O_HDRC_CSR0, musb->ackpend);
 900                 musb->ackpend = 0;
 901         }
 902
 903 cleanup:
 904         spin_unlock_irqrestore(&musb->Lock, lockflags);
 905         return status;
 906 }
 907
 908 static int
 909 musb_g_ep0_dequeue(struct usb_ep *ep, struct usb_request *req)
 910 {
 911         /* we just won't support this */
 912         return -EINVAL;
 913 }
 914
 915 static int musb_g_ep0_halt(struct usb_ep *e, int value)
 916 {
 917         struct musb_ep          *ep;
 918         struct musb             *musb;
 919         void __iomem            *base, *regs;
 920         unsigned long           flags;
 921         int                     status;
 922         u16                     csr;
 923
 924         if (!e || !value)
 925                 return -EINVAL;
 926
 927         ep = to_musb_ep(e);
 928         musb = ep->pThis;
 929         base = musb->pRegs;
 930         regs = musb->control_ep->regs;
 931
 932         spin_lock_irqsave(&musb->Lock, flags);
 933
 934         if (!list_empty(&ep->req_list)) {
 935                 status = -EBUSY;
 936                 goto cleanup;
 937         }
 938
 939         switch (musb->ep0_state) {
 940         case MGC_END0_STAGE_TX:         /* control-IN data */
 941         case MGC_END0_STAGE_ACKWAIT:    /* STALL for zero-length data */
 942         case MGC_END0_STAGE_RX:         /* control-OUT data */
 943                 status = 0;
 944
 945                 MGC_SelectEnd(base, 0);
 946                 csr = musb_readw(regs, MGC_O_HDRC_CSR0);
 947                 csr |= MGC_M_CSR0_P_SENDSTALL;
 948                 musb_writew(regs, MGC_O_HDRC_CSR0, csr);
 949                 musb->ep0_state = MGC_END0_STAGE_SETUP;
 950                 break;
 951         default:
 952                 DBG(1, "ep0 can't halt in state %d\n", musb->ep0_state);
 953                 status = -EINVAL;
 954         }
 955
 956 cleanup:
 957         spin_unlock_irqrestore(&musb->Lock, flags);
 958         return status;
 959 }
 960
 961 const struct usb_ep_ops musb_g_ep0_ops = {
 962         .enable         = musb_g_ep0_enable,
 963         .disable        = musb_g_ep0_disable,
 964         .alloc_request  = musb_alloc_request,
 965         .free_request   = musb_free_request,
 966         .alloc_buffer   = musb_g_ep0_alloc_buffer,
 967         .free_buffer    = musb_g_ep0_free_buffer,
 968         .queue          = musb_g_ep0_queue,
 969         .dequeue        = musb_g_ep0_dequeue,
 970         .set_halt       = musb_g_ep0_halt,
 971         .fifo_status    = NULL,
 972         .fifo_flush     = NULL,
 973 };