2 * MUSB OTG driver core code
4 * Copyright 2005 Mentor Graphics Corporation
5 * Copyright (C) 2005-2006 by Texas Instruments
6 * Copyright (C) 2006-2007 Nokia Corporation
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * version 2 as published by the Free Software Foundation.
12 * This program is distributed in the hope that it will be useful, but
13 * WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
22 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
23 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
24 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
25 * NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT,
26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
28 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
29 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 * Inventra (Multipoint) Dual-Role Controller Driver for Linux.
38 * This consists of a Host Controller Driver (HCD) and a peripheral
39 * controller driver implementing the "Gadget" API; OTG support is
40 * in the works. These are normal Linux-USB controller drivers which
41 * use IRQs and have no dedicated thread.
43 * This version of the driver has only been used with products from
44 * Texas Instruments. Those products integrate the Inventra logic
45 * with other DMA, IRQ, and bus modules, as well as other logic that
46 * needs to be reflected in this driver.
49 * NOTE: the original Mentor code here was pretty much a collection
50 * of mechanisms that don't seem to have been fully integrated/working
51 * for *any* Linux kernel version. This version aims at Linux 2.6.now,
52 * Key open issues include:
54 * - Lack of host-side transaction scheduling, for all transfer types.
55 * The hardware doesn't do it; instead, software must.
57 * This is not an issue for OTG devices that don't support external
58 * hubs, but for more "normal" USB hosts it's a user issue that the
59 * "multipoint" support doesn't scale in the expected ways. That
60 * includes DaVinci EVM in a common non-OTG mode.
62 * * Control and bulk use dedicated endpoints, and there's as
63 * yet no mechanism to either (a) reclaim the hardware when
64 * peripherals are NAKing, which gets complicated with bulk
65 * endpoints, or (b) use more than a single bulk endpoint in
68 * RESULT: one device may be perceived as blocking another one.
70 * * Interrupt and isochronous will dynamically allocate endpoint
71 * hardware, but (a) there's no record keeping for bandwidth;
72 * (b) in the common case that few endpoints are available, there
73 * is no mechanism to reuse endpoints to talk to multiple devices.
75 * RESULT: At one extreme, bandwidth can be overcommitted in
76 * some hardware configurations, no faults will be reported.
77 * At the other extreme, the bandwidth capabilities which do
78 * exist tend to be severely undercommitted. You can't yet hook
79 * up both a keyboard and a mouse to an external USB hub.
83 * This gets many kinds of configuration information:
84 * - Kconfig for everything user-configurable
85 * - <asm/arch/hdrc_cnf.h> for SOC or family details
86 * - platform_device for addressing, irq, and platform_data
87 * - platform_data is mostly for board-specific informarion
89 * Most of the conditional compilation will (someday) vanish.
92 #include <linux/module.h>
93 #include <linux/kernel.h>
94 #include <linux/sched.h>
95 #include <linux/slab.h>
96 #include <linux/init.h>
97 #include <linux/list.h>
98 #include <linux/kobject.h>
99 #include <linux/platform_device.h>
104 #include <asm/arch/hardware.h>
105 #include <asm/arch/memory.h>
106 #include <asm/mach-types.h>
109 #include "musb_core.h"
112 #ifdef CONFIG_ARCH_DAVINCI
119 unsigned debug = MUSB_DEBUG;
120 module_param(debug, uint, 0);
121 MODULE_PARM_DESC(debug, "initial debug message level");
123 #define MUSB_VERSION_SUFFIX "/dbg"
126 const char *otg_state_string(struct musb *musb)
130 snprintf(buf, sizeof buf, "otg-%d", musb->xceiv.state);
135 #define DRIVER_AUTHOR "Mentor Graphics, Texas Instruments, Nokia"
136 #define DRIVER_DESC "Inventra Dual-Role USB Controller Driver"
138 #define MUSB_VERSION_BASE "6.0"
140 #ifndef MUSB_VERSION_SUFFIX
141 #define MUSB_VERSION_SUFFIX ""
143 #define MUSB_VERSION MUSB_VERSION_BASE MUSB_VERSION_SUFFIX
145 #define DRIVER_INFO DRIVER_DESC ", v" MUSB_VERSION
147 const char musb_driver_name[] = "musb_hdrc";
149 MODULE_DESCRIPTION(DRIVER_INFO);
150 MODULE_AUTHOR(DRIVER_AUTHOR);
151 MODULE_LICENSE("GPL");
154 /*-------------------------------------------------------------------------*/
156 static inline struct musb *dev_to_musb(struct device *dev)
158 #ifdef CONFIG_USB_MUSB_HDRC_HCD
159 /* usbcore insists dev->driver_data is a "struct hcd *" */
160 return hcd_to_musb(dev_get_drvdata(dev));
162 return dev_get_drvdata(dev);
166 /*-------------------------------------------------------------------------*/
168 #ifndef CONFIG_USB_TUSB6010
170 * Load an endpoint's FIFO
172 void musb_write_fifo(struct musb_hw_ep *hw_ep, u16 len, const u8 *src)
174 void __iomem *fifo = hw_ep->fifo;
178 DBG(4, "%cX ep%d fifo %p count %d buf %p\n",
179 'T', hw_ep->epnum, fifo, len, src);
181 /* we can't assume unaligned reads work */
182 if (likely((0x01 & (unsigned long) src) == 0)) {
185 /* best case is 32bit-aligned source address */
186 if ((0x02 & (unsigned long) src) == 0) {
188 writesl(fifo, src + index, len >> 2);
189 index += len & ~0x03;
192 musb_writew(fifo, 0, *(u16*)&src[index]);
197 writesw(fifo, src + index, len >> 1);
198 index += len & ~0x01;
202 musb_writeb(fifo, 0, src[index]);
205 writesb(fifo, src, len);
210 * Unload an endpoint's FIFO
212 void musb_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *dst)
214 void __iomem *fifo = hw_ep->fifo;
216 DBG(4, "%cX ep%d fifo %p count %d buf %p\n",
217 'R', hw_ep->epnum, fifo, len, dst);
219 /* we can't assume unaligned writes work */
220 if (likely((0x01 & (unsigned long) dst) == 0)) {
223 /* best case is 32bit-aligned destination address */
224 if ((0x02 & (unsigned long) dst) == 0) {
226 readsl(fifo, dst, len >> 2);
230 *(u16*)&dst[index] = musb_readw(fifo, 0);
235 readsw(fifo, dst, len >> 1);
240 dst[index] = musb_readb(fifo, 0);
243 readsb(fifo, dst, len);
247 #endif /* normal PIO */
250 /*-------------------------------------------------------------------------*/
252 /* for high speed test mode; see USB 2.0 spec 7.1.20 */
253 static const u8 musb_test_packet[53] = {
254 /* implicit SYNC then DATA0 to start */
257 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
259 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,
261 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0xee,
262 /* JJJJJJJKKKKKKK x8 */
263 0xfe, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
265 0x7f, 0xbf, 0xdf, 0xef, 0xf7, 0xfb, 0xfd,
266 /* JKKKKKKK x10, JK */
267 0xfc, 0x7e, 0xbf, 0xdf, 0xef, 0xf7, 0xfb, 0xfd, 0x7e
269 /* implicit CRC16 then EOP to end */
272 void musb_load_testpacket(struct musb *musb)
274 void __iomem *regs = musb->endpoints[0].regs;
276 musb_ep_select(musb->mregs, 0);
277 musb_write_fifo(musb->control_ep,
278 sizeof(musb_test_packet), musb_test_packet);
279 musb_writew(regs, MUSB_CSR0, MUSB_CSR0_TXPKTRDY);
282 /*-------------------------------------------------------------------------*/
284 #ifdef CONFIG_USB_MUSB_OTG
287 * See also USB_OTG_1-3.pdf 6.6.5 Timers
288 * REVISIT: Are the other timers done in the hardware?
290 #define TB_ASE0_BRST 100 /* Min 3.125 ms */
293 * Handles OTG hnp timeouts, such as b_ase0_brst
295 void musb_otg_timer_func(unsigned long data)
297 struct musb *musb = (struct musb *)data;
300 spin_lock_irqsave(&musb->lock, flags);
301 if (musb->xceiv.state == OTG_STATE_B_WAIT_ACON) {
302 DBG(1, "HNP: B_WAIT_ACON timeout; back to B_PERIPHERAL\n");
303 musb_g_disconnect(musb);
304 musb->xceiv.state = OTG_STATE_B_PERIPHERAL;
307 spin_unlock_irqrestore(&musb->lock, flags);
310 static DEFINE_TIMER(musb_otg_timer, musb_otg_timer_func, 0, 0);
313 * Stops the B-device HNP state. Caller must take care of locking.
315 void musb_hnp_stop(struct musb *musb)
317 struct usb_hcd *hcd = musb_to_hcd(musb);
318 void __iomem *mbase = musb->mregs;
321 switch (musb->xceiv.state) {
322 case OTG_STATE_A_PERIPHERAL:
323 case OTG_STATE_A_WAIT_VFALL:
324 case OTG_STATE_A_WAIT_BCON:
325 DBG(1, "HNP: Switching back to A-host\n");
326 musb_g_disconnect(musb);
327 musb->xceiv.state = OTG_STATE_A_IDLE;
331 case OTG_STATE_B_HOST:
332 DBG(1, "HNP: Disabling HR\n");
333 hcd->self.is_b_host = 0;
334 musb->xceiv.state = OTG_STATE_B_PERIPHERAL;
336 reg = musb_readb(mbase, MUSB_POWER);
337 reg |= MUSB_POWER_SUSPENDM;
338 musb_writeb(mbase, MUSB_POWER, reg);
339 /* REVISIT: Start SESSION_REQUEST here? */
342 DBG(1, "HNP: Stopping in unknown state %s\n",
343 otg_state_string(musb));
347 * When returning to A state after HNP, avoid hub_port_rebounce(),
348 * which cause occasional OPT A "Did not receive reset after connect"
351 musb->port1_status &=
352 ~(1 << USB_PORT_FEAT_C_CONNECTION);
358 * Interrupt Service Routine to record USB "global" interrupts.
359 * Since these do not happen often and signify things of
360 * paramount importance, it seems OK to check them individually;
361 * the order of the tests is specified in the manual
363 * @param musb instance pointer
364 * @param int_usb register contents
369 #define STAGE0_MASK (MUSB_INTR_RESUME | MUSB_INTR_SESSREQ \
370 | MUSB_INTR_VBUSERROR | MUSB_INTR_CONNECT \
373 static irqreturn_t musb_stage0_irq(struct musb * musb, u8 int_usb,
376 irqreturn_t handled = IRQ_NONE;
377 void __iomem *mbase = musb->mregs;
379 DBG(3, "<== Power=%02x, DevCtl=%02x, int_usb=0x%x\n", power, devctl,
382 /* in host mode, the peripheral may issue remote wakeup.
383 * in peripheral mode, the host may resume the link.
384 * spurious RESUME irqs happen too, paired with SUSPEND.
386 if (int_usb & MUSB_INTR_RESUME) {
387 handled = IRQ_HANDLED;
388 DBG(3, "RESUME (%s)\n", otg_state_string(musb));
390 if (devctl & MUSB_DEVCTL_HM) {
391 #ifdef CONFIG_USB_MUSB_HDRC_HCD
392 switch (musb->xceiv.state) {
393 case OTG_STATE_A_SUSPEND:
394 /* remote wakeup? later, GetPortStatus
395 * will stop RESUME signaling
398 if (power & MUSB_POWER_SUSPENDM) {
400 musb->int_usb &= ~MUSB_INTR_SUSPEND;
401 DBG(2, "Spurious SUSPENDM\n");
405 power &= ~MUSB_POWER_SUSPENDM;
406 musb_writeb(mbase, MUSB_POWER,
407 power | MUSB_POWER_RESUME);
409 musb->port1_status |=
410 (USB_PORT_STAT_C_SUSPEND << 16)
411 | MUSB_PORT_STAT_RESUME;
412 musb->rh_timer = jiffies
413 + msecs_to_jiffies(20);
415 musb->xceiv.state = OTG_STATE_A_HOST;
417 usb_hcd_resume_root_hub(musb_to_hcd(musb));
419 case OTG_STATE_B_WAIT_ACON:
420 musb->xceiv.state = OTG_STATE_B_PERIPHERAL;
425 WARN("bogus %s RESUME (%s)\n",
427 otg_state_string(musb));
431 switch (musb->xceiv.state) {
432 #ifdef CONFIG_USB_MUSB_HDRC_HCD
433 case OTG_STATE_A_SUSPEND:
434 /* possibly DISCONNECT is upcoming */
435 musb->xceiv.state = OTG_STATE_A_HOST;
436 usb_hcd_resume_root_hub(musb_to_hcd(musb));
439 #ifdef CONFIG_USB_GADGET_MUSB_HDRC
440 case OTG_STATE_B_WAIT_ACON:
441 case OTG_STATE_B_PERIPHERAL:
442 /* disconnect while suspended? we may
443 * not get a disconnect irq...
445 if ((devctl & MUSB_DEVCTL_VBUS)
446 != (3 << MUSB_DEVCTL_VBUS_SHIFT)
448 musb->int_usb |= MUSB_INTR_DISCONNECT;
449 musb->int_usb &= ~MUSB_INTR_SUSPEND;
454 case OTG_STATE_B_IDLE:
455 musb->int_usb &= ~MUSB_INTR_SUSPEND;
459 WARN("bogus %s RESUME (%s)\n",
461 otg_state_string(musb));
466 #ifdef CONFIG_USB_MUSB_HDRC_HCD
467 /* see manual for the order of the tests */
468 if (int_usb & MUSB_INTR_SESSREQ) {
469 DBG(1, "SESSION_REQUEST (%s)\n", otg_state_string(musb));
471 /* IRQ arrives from ID pin sense or (later, if VBUS power
472 * is removed) SRP. responses are time critical:
473 * - turn on VBUS (with silicon-specific mechanism)
474 * - go through A_WAIT_VRISE
475 * - ... to A_WAIT_BCON.
476 * a_wait_vrise_tmout triggers VBUS_ERROR transitions
478 musb_writeb(mbase, MUSB_DEVCTL, MUSB_DEVCTL_SESSION);
479 musb->ep0_stage = MUSB_EP0_START;
480 musb->xceiv.state = OTG_STATE_A_IDLE;
482 musb_set_vbus(musb, 1);
484 handled = IRQ_HANDLED;
487 if (int_usb & MUSB_INTR_VBUSERROR) {
490 /* During connection as an A-Device, we may see a short
491 * current spikes causing voltage drop, because of cable
492 * and peripheral capacitance combined with vbus draw.
493 * (So: less common with truly self-powered devices, where
494 * vbus doesn't act like a power supply.)
496 * Such spikes are short; usually less than ~500 usec, max
497 * of ~2 msec. That is, they're not sustained overcurrent
498 * errors, though they're reported using VBUSERROR irqs.
500 * Workarounds: (a) hardware: use self powered devices.
501 * (b) software: ignore non-repeated VBUS errors.
503 * REVISIT: do delays from lots of DEBUG_KERNEL checks
504 * make trouble here, keeping VBUS < 4.4V ?
506 switch (musb->xceiv.state) {
507 case OTG_STATE_A_HOST:
508 /* recovery is dicey once we've gotten past the
509 * initial stages of enumeration, but if VBUS
510 * stayed ok at the other end of the link, and
511 * another reset is due (at least for high speed,
512 * to redo the chirp etc), it might work OK...
514 case OTG_STATE_A_WAIT_BCON:
515 case OTG_STATE_A_WAIT_VRISE:
516 if (musb->vbuserr_retry) {
517 musb->vbuserr_retry--;
519 devctl |= MUSB_DEVCTL_SESSION;
520 musb_writeb(mbase, MUSB_DEVCTL, devctl);
522 musb->port1_status |=
523 (1 << USB_PORT_FEAT_OVER_CURRENT)
524 | (1 << USB_PORT_FEAT_C_OVER_CURRENT);
531 DBG(1, "VBUS_ERROR in %s (%02x, %s), retry #%d, port1 %08x\n",
532 otg_state_string(musb),
535 switch (devctl & MUSB_DEVCTL_VBUS) {
536 case 0 << MUSB_DEVCTL_VBUS_SHIFT:
537 s = "<SessEnd"; break;
538 case 1 << MUSB_DEVCTL_VBUS_SHIFT:
539 s = "<AValid"; break;
540 case 2 << MUSB_DEVCTL_VBUS_SHIFT:
541 s = "<VBusValid"; break;
542 /* case 3 << MUSB_DEVCTL_VBUS_SHIFT: */
546 VBUSERR_RETRY_COUNT - musb->vbuserr_retry,
549 /* go through A_WAIT_VFALL then start a new session */
551 musb_set_vbus(musb, 0);
552 handled = IRQ_HANDLED;
555 if (int_usb & MUSB_INTR_CONNECT) {
556 struct usb_hcd *hcd = musb_to_hcd(musb);
558 handled = IRQ_HANDLED;
560 set_bit(HCD_FLAG_SAW_IRQ, &hcd->flags);
562 musb->ep0_stage = MUSB_EP0_START;
564 #ifdef CONFIG_USB_MUSB_OTG
565 /* flush endpoints when transitioning from Device Mode */
566 if (is_peripheral_active(musb)) {
567 /* REVISIT HNP; just force disconnect */
569 musb_writew(mbase, MUSB_INTRTXE, musb->epmask);
570 musb_writew(mbase, MUSB_INTRRXE, musb->epmask & 0xfffe);
571 musb_writeb(mbase, MUSB_INTRUSBE, 0xf7);
573 musb->port1_status &= ~(USB_PORT_STAT_LOW_SPEED
574 |USB_PORT_STAT_HIGH_SPEED
575 |USB_PORT_STAT_ENABLE
577 musb->port1_status |= USB_PORT_STAT_CONNECTION
578 |(USB_PORT_STAT_C_CONNECTION << 16);
580 /* high vs full speed is just a guess until after reset */
581 if (devctl & MUSB_DEVCTL_LSDEV)
582 musb->port1_status |= USB_PORT_STAT_LOW_SPEED;
585 usb_hcd_poll_rh_status(hcd);
587 usb_hcd_resume_root_hub(hcd);
591 /* indicate new connection to OTG machine */
592 switch (musb->xceiv.state) {
593 case OTG_STATE_B_PERIPHERAL:
594 if (int_usb & MUSB_INTR_SUSPEND) {
595 DBG(1, "HNP: SUSPEND+CONNECT, now b_host\n");
596 musb->xceiv.state = OTG_STATE_B_HOST;
597 hcd->self.is_b_host = 1;
598 int_usb &= ~MUSB_INTR_SUSPEND;
600 DBG(1, "CONNECT as b_peripheral???\n");
602 case OTG_STATE_B_WAIT_ACON:
603 DBG(1, "HNP: Waiting to switch to b_host state\n");
604 musb->xceiv.state = OTG_STATE_B_HOST;
605 hcd->self.is_b_host = 1;
608 if ((devctl & MUSB_DEVCTL_VBUS)
609 == (3 << MUSB_DEVCTL_VBUS_SHIFT)) {
610 musb->xceiv.state = OTG_STATE_A_HOST;
611 hcd->self.is_b_host = 0;
615 DBG(1, "CONNECT (%s) devctl %02x\n",
616 otg_state_string(musb), devctl);
618 #endif /* CONFIG_USB_MUSB_HDRC_HCD */
620 /* mentor saves a bit: bus reset and babble share the same irq.
621 * only host sees babble; only peripheral sees bus reset.
623 if (int_usb & MUSB_INTR_RESET) {
624 if (is_host_capable() && (devctl & MUSB_DEVCTL_HM) != 0) {
626 * Looks like non-HS BABBLE can be ignored, but
627 * HS BABBLE is an error condition. For HS the solution
628 * is to avoid babble in the first place and fix what
629 * caused BABBLE. When HS BABBLE happens we can only
632 if (devctl & (MUSB_DEVCTL_FSDEV | MUSB_DEVCTL_LSDEV))
633 DBG(1, "BABBLE devctl: %02x\n", devctl);
635 ERR("Stopping host session -- babble\n");
636 musb_writeb(mbase, MUSB_DEVCTL, 0);
638 } else if (is_peripheral_capable()) {
639 DBG(1, "BUS RESET as %s\n", otg_state_string(musb));
640 switch (musb->xceiv.state) {
641 case OTG_STATE_A_PERIPHERAL:
642 case OTG_STATE_A_WAIT_BCON: /* OPT TD.4.7-900ms */
645 case OTG_STATE_B_IDLE:
646 musb->xceiv.state = OTG_STATE_B_PERIPHERAL;
648 case OTG_STATE_B_PERIPHERAL:
652 DBG(1, "Unhandled BUS RESET as %s\n",
653 otg_state_string(musb));
655 schedule_work(&musb->irq_work);
658 handled = IRQ_HANDLED;
665 * Interrupt Service Routine to record USB "global" interrupts.
666 * Since these do not happen often and signify things of
667 * paramount importance, it seems OK to check them individually;
668 * the order of the tests is specified in the manual
670 * @param musb instance pointer
671 * @param int_usb register contents
675 static irqreturn_t musb_stage2_irq(struct musb * musb, u8 int_usb,
678 irqreturn_t handled = IRQ_NONE;
681 /* REVISIT ... this would be for multiplexing periodic endpoints, or
682 * supporting transfer phasing to prevent exceeding ISO bandwidth
683 * limits of a given frame or microframe.
685 * It's not needed for peripheral side, which dedicates endpoints;
686 * though it _might_ use SOF irqs for other purposes.
688 * And it's not currently needed for host side, which also dedicates
689 * endpoints, relies on TX/RX interval registers, and isn't claimed
690 * to support ISO transfers yet.
692 if (int_usb & MUSB_INTR_SOF) {
693 void __iomem *mbase = musb->mregs;
694 struct musb_hw_ep *ep;
698 DBG(6, "START_OF_FRAME\n");
699 handled = IRQ_HANDLED;
701 /* start any periodic Tx transfers waiting for current frame */
702 frame = musb_readw(mbase, MUSB_FRAME);
703 ep = musb->endpoints;
704 for (epnum = 1; (epnum < musb->nr_endpoints)
705 && (musb->epmask >= (1 << epnum));
708 * FIXME handle framecounter wraps (12 bits)
709 * eliminate duplicated StartUrb logic
711 if (ep->dwWaitFrame >= frame) {
713 printk("SOF --> periodic TX%s on %d\n",
714 ep->tx_channel ? " DMA" : "",
717 musb_h_tx_start(musb, epnum);
719 cppi_hostdma_start(musb, epnum);
721 } /* end of for loop */
725 if ((int_usb & MUSB_INTR_DISCONNECT) && !musb->ignore_disconnect) {
726 DBG(1, "DISCONNECT (%s) as %s, devctl %02x\n",
727 otg_state_string(musb),
728 MUSB_MODE(musb), devctl);
729 handled = IRQ_HANDLED;
731 switch (musb->xceiv.state) {
732 #ifdef CONFIG_USB_MUSB_HDRC_HCD
733 case OTG_STATE_A_HOST:
734 case OTG_STATE_A_SUSPEND:
735 musb_root_disconnect(musb);
736 if (musb->a_wait_bcon != 0)
737 musb_platform_try_idle(musb, jiffies
738 + msecs_to_jiffies(musb->a_wait_bcon));
741 #ifdef CONFIG_USB_MUSB_OTG
742 case OTG_STATE_B_HOST:
745 case OTG_STATE_A_PERIPHERAL:
747 musb_root_disconnect(musb);
749 case OTG_STATE_B_WAIT_ACON:
752 #ifdef CONFIG_USB_GADGET_MUSB_HDRC
753 case OTG_STATE_B_PERIPHERAL:
754 case OTG_STATE_B_IDLE:
755 musb_g_disconnect(musb);
759 WARN("unhandled DISCONNECT transition (%s)\n",
760 otg_state_string(musb));
764 schedule_work(&musb->irq_work);
767 if (int_usb & MUSB_INTR_SUSPEND) {
768 DBG(1, "SUSPEND (%s) devctl %02x power %02x\n",
769 otg_state_string(musb), devctl, power);
770 handled = IRQ_HANDLED;
772 switch (musb->xceiv.state) {
773 #ifdef CONFIG_USB_MUSB_OTG
774 case OTG_STATE_A_PERIPHERAL:
776 * We cannot stop HNP here, devctl BDEVICE might be
781 case OTG_STATE_B_PERIPHERAL:
782 musb_g_suspend(musb);
783 musb->is_active = is_otg_enabled(musb)
784 && musb->xceiv.gadget->b_hnp_enable;
785 if (musb->is_active) {
786 musb->xceiv.state = OTG_STATE_B_WAIT_ACON;
787 #ifdef CONFIG_USB_MUSB_OTG
788 DBG(1, "HNP: Setting timer for b_ase0_brst\n");
789 musb_otg_timer.data = (unsigned long)musb;
790 mod_timer(&musb_otg_timer, jiffies
791 + msecs_to_jiffies(TB_ASE0_BRST));
795 case OTG_STATE_A_WAIT_BCON:
796 if (musb->a_wait_bcon != 0)
797 musb_platform_try_idle(musb, jiffies
798 + msecs_to_jiffies(musb->a_wait_bcon));
800 case OTG_STATE_A_HOST:
801 musb->xceiv.state = OTG_STATE_A_SUSPEND;
802 musb->is_active = is_otg_enabled(musb)
803 && musb->xceiv.host->b_hnp_enable;
805 case OTG_STATE_B_HOST:
806 /* Transition to B_PERIPHERAL, see 6.8.2.6 p 44 */
807 DBG(1, "REVISIT: SUSPEND as B_HOST\n");
810 /* "should not happen" */
820 /*-------------------------------------------------------------------------*/
823 * Program the HDRC to start (enable interrupts, dma, etc.).
825 void musb_start(struct musb *musb)
827 void __iomem *regs = musb->mregs;
828 u8 devctl = musb_readb(regs, MUSB_DEVCTL);
830 DBG(2, "<== devctl %02x\n", devctl);
832 /* Set INT enable registers, enable interrupts */
833 musb_writew(regs, MUSB_INTRTXE, musb->epmask);
834 musb_writew(regs, MUSB_INTRRXE, musb->epmask & 0xfffe);
835 musb_writeb(regs, MUSB_INTRUSBE, 0xf7);
837 musb_writeb(regs, MUSB_TESTMODE, 0);
839 /* put into basic highspeed mode and start session */
840 musb_writeb(regs, MUSB_POWER, MUSB_POWER_ISOUPDATE
841 | MUSB_POWER_SOFTCONN
843 /* ENSUSPEND wedges tusb */
844 /* | MUSB_POWER_ENSUSPEND */
848 devctl = musb_readb(regs, MUSB_DEVCTL);
849 devctl &= ~MUSB_DEVCTL_SESSION;
851 if (is_otg_enabled(musb)) {
852 /* session started after:
853 * (a) ID-grounded irq, host mode;
854 * (b) vbus present/connect IRQ, peripheral mode;
855 * (c) peripheral initiates, using SRP
857 if ((devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS)
860 devctl |= MUSB_DEVCTL_SESSION;
862 } else if (is_host_enabled(musb)) {
863 /* assume ID pin is hard-wired to ground */
864 devctl |= MUSB_DEVCTL_SESSION;
866 } else /* peripheral is enabled */ {
867 if ((devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS)
870 musb_platform_enable(musb);
871 musb_writeb(regs, MUSB_DEVCTL, devctl);
875 static void musb_generic_disable(struct musb *musb)
877 void __iomem *mbase = musb->mregs;
880 /* disable interrupts */
881 musb_writeb(mbase, MUSB_INTRUSBE, 0);
882 musb_writew(mbase, MUSB_INTRTXE, 0);
883 musb_writew(mbase, MUSB_INTRRXE, 0);
886 musb_writeb(mbase, MUSB_DEVCTL, 0);
888 /* flush pending interrupts */
889 temp = musb_readb(mbase, MUSB_INTRUSB);
890 temp = musb_readw(mbase, MUSB_INTRTX);
891 temp = musb_readw(mbase, MUSB_INTRRX);
896 * Make the HDRC stop (disable interrupts, etc.);
897 * reversible by musb_start
898 * called on gadget driver unregister
899 * with controller locked, irqs blocked
900 * acts as a NOP unless some role activated the hardware
902 void musb_stop(struct musb *musb)
904 /* stop IRQs, timers, ... */
905 musb_platform_disable(musb);
906 musb_generic_disable(musb);
907 DBG(3, "HDRC disabled\n");
910 * - mark host and/or peripheral drivers unusable/inactive
911 * - disable DMA (and enable it in HdrcStart)
912 * - make sure we can musb_start() after musb_stop(); with
913 * OTG mode, gadget driver module rmmod/modprobe cycles that
916 musb_platform_try_idle(musb, 0);
919 static void musb_shutdown(struct platform_device *pdev)
921 struct musb *musb = dev_to_musb(&pdev->dev);
924 spin_lock_irqsave(&musb->lock, flags);
925 musb_platform_disable(musb);
926 musb_generic_disable(musb);
928 clk_put(musb->clock);
931 spin_unlock_irqrestore(&musb->lock, flags);
933 /* FIXME power down */
937 /*-------------------------------------------------------------------------*/
940 * The silicon either has hard-wired endpoint configurations, or else
941 * "dynamic fifo" sizing. The driver has support for both, though at this
942 * writing only the dynamic sizing is very well tested. We use normal
943 * idioms to so both modes are compile-tested, but dead code elimination
944 * leaves only the relevant one in the object file.
946 * We don't currently use dynamic fifo setup capability to do anything
947 * more than selecting one of a bunch of predefined configurations.
949 #ifdef MUSB_C_DYNFIFO_DEF
950 #define can_dynfifo() 1
952 #define can_dynfifo() 0
955 #ifdef CONFIG_USB_TUSB6010
956 static ushort __initdata fifo_mode = 4;
958 static ushort __initdata fifo_mode = 2;
961 /* "modprobe ... fifo_mode=1" etc */
962 module_param(fifo_mode, ushort, 0);
963 MODULE_PARM_DESC(fifo_mode, "initial endpoint configuration");
966 #define DYN_FIFO_SIZE (1<<(MUSB_C_RAM_BITS+2))
968 enum fifo_style { FIFO_RXTX, FIFO_TX, FIFO_RX } __attribute__ ((packed));
969 enum buf_mode { BUF_SINGLE, BUF_DOUBLE } __attribute__ ((packed));
973 enum fifo_style style;
979 * tables defining fifo_mode values. define more if you like.
980 * for host side, make sure both halves of ep1 are set up.
983 /* mode 0 - fits in 2KB */
984 static struct fifo_cfg __initdata mode_0_cfg[] = {
985 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
986 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
987 { .hw_ep_num = 2, .style = FIFO_RXTX, .maxpacket = 512, },
988 { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
989 { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
992 /* mode 1 - fits in 4KB */
993 static struct fifo_cfg __initdata mode_1_cfg[] = {
994 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, .mode = BUF_DOUBLE, },
995 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, .mode = BUF_DOUBLE, },
996 { .hw_ep_num = 2, .style = FIFO_RXTX, .maxpacket = 512, .mode = BUF_DOUBLE, },
997 { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
998 { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1001 /* mode 2 - fits in 4KB */
1002 static struct fifo_cfg __initdata mode_2_cfg[] = {
1003 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
1004 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
1005 { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
1006 { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
1007 { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1008 { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1011 /* mode 3 - fits in 4KB */
1012 static struct fifo_cfg __initdata mode_3_cfg[] = {
1013 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1014 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1015 { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
1016 { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
1017 { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1018 { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1021 /* mode 4 - fits in 16KB */
1022 static struct fifo_cfg __initdata mode_4_cfg[] = {
1023 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
1024 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
1025 { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
1026 { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
1027 { .hw_ep_num = 3, .style = FIFO_TX, .maxpacket = 512, },
1028 { .hw_ep_num = 3, .style = FIFO_RX, .maxpacket = 512, },
1029 { .hw_ep_num = 4, .style = FIFO_TX, .maxpacket = 512, },
1030 { .hw_ep_num = 4, .style = FIFO_RX, .maxpacket = 512, },
1031 { .hw_ep_num = 5, .style = FIFO_TX, .maxpacket = 512, },
1032 { .hw_ep_num = 5, .style = FIFO_RX, .maxpacket = 512, },
1033 { .hw_ep_num = 6, .style = FIFO_TX, .maxpacket = 512, },
1034 { .hw_ep_num = 6, .style = FIFO_RX, .maxpacket = 512, },
1035 { .hw_ep_num = 7, .style = FIFO_TX, .maxpacket = 512, },
1036 { .hw_ep_num = 7, .style = FIFO_RX, .maxpacket = 512, },
1037 { .hw_ep_num = 8, .style = FIFO_TX, .maxpacket = 512, },
1038 { .hw_ep_num = 8, .style = FIFO_RX, .maxpacket = 512, },
1039 { .hw_ep_num = 9, .style = FIFO_TX, .maxpacket = 512, },
1040 { .hw_ep_num = 9, .style = FIFO_RX, .maxpacket = 512, },
1041 { .hw_ep_num = 10, .style = FIFO_TX, .maxpacket = 512, },
1042 { .hw_ep_num = 10, .style = FIFO_RX, .maxpacket = 512, },
1043 { .hw_ep_num = 11, .style = FIFO_TX, .maxpacket = 512, },
1044 { .hw_ep_num = 11, .style = FIFO_RX, .maxpacket = 512, },
1045 { .hw_ep_num = 12, .style = FIFO_TX, .maxpacket = 512, },
1046 { .hw_ep_num = 12, .style = FIFO_RX, .maxpacket = 512, },
1047 { .hw_ep_num = 13, .style = FIFO_TX, .maxpacket = 512, },
1048 { .hw_ep_num = 13, .style = FIFO_RX, .maxpacket = 512, },
1049 { .hw_ep_num = 14, .style = FIFO_RXTX, .maxpacket = 1024, },
1050 { .hw_ep_num = 15, .style = FIFO_RXTX, .maxpacket = 1024, },
1055 * configure a fifo; for non-shared endpoints, this may be called
1056 * once for a tx fifo and once for an rx fifo.
1058 * returns negative errno or offset for next fifo.
1061 fifo_setup(struct musb *musb, struct musb_hw_ep *hw_ep,
1062 const struct fifo_cfg *cfg, u16 offset)
1064 void __iomem *mbase = musb->mregs;
1066 u16 maxpacket = cfg->maxpacket;
1067 u16 c_off = offset >> 3;
1070 /* expect hw_ep has already been zero-initialized */
1072 size = ffs(max(maxpacket, (u16) 8)) - 1;
1073 maxpacket = 1 << size;
1076 if (cfg->mode == BUF_DOUBLE) {
1077 if ((offset + (maxpacket << 1)) > DYN_FIFO_SIZE)
1079 c_size |= MUSB_FIFOSZ_DPB;
1081 if ((offset + maxpacket) > DYN_FIFO_SIZE)
1085 /* configure the FIFO */
1086 musb_writeb(mbase, MUSB_INDEX, hw_ep->epnum);
1088 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1089 /* EP0 reserved endpoint for control, bidirectional;
1090 * EP1 reserved for bulk, two unidirection halves.
1092 if (hw_ep->epnum == 1)
1093 musb->bulk_ep = hw_ep;
1094 /* REVISIT error check: be sure ep0 can both rx and tx ... */
1096 switch (cfg->style) {
1098 musb_writeb(mbase, MUSB_TXFIFOSZ, c_size);
1099 musb_writew(mbase, MUSB_TXFIFOADD, c_off);
1100 hw_ep->tx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB);
1101 hw_ep->max_packet_sz_tx = maxpacket;
1104 musb_writeb(mbase, MUSB_RXFIFOSZ, c_size);
1105 musb_writew(mbase, MUSB_RXFIFOADD, c_off);
1106 hw_ep->rx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB);
1107 hw_ep->max_packet_sz_rx = maxpacket;
1110 musb_writeb(mbase, MUSB_TXFIFOSZ, c_size);
1111 musb_writew(mbase, MUSB_TXFIFOADD, c_off);
1112 hw_ep->rx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB);
1113 hw_ep->max_packet_sz_rx = maxpacket;
1115 musb_writeb(mbase, MUSB_RXFIFOSZ, c_size);
1116 musb_writew(mbase, MUSB_RXFIFOADD, c_off);
1117 hw_ep->tx_double_buffered = hw_ep->rx_double_buffered;
1118 hw_ep->max_packet_sz_tx = maxpacket;
1120 hw_ep->is_shared_fifo = true;
1124 /* NOTE rx and tx endpoint irqs aren't managed separately,
1125 * which happens to be ok
1127 musb->epmask |= (1 << hw_ep->epnum);
1129 return offset + (maxpacket << ((c_size & MUSB_FIFOSZ_DPB) ? 1 : 0));
1132 static struct fifo_cfg __initdata ep0_cfg = {
1133 .style = FIFO_RXTX, .maxpacket = 64,
1136 static int __init ep_config_from_table(struct musb *musb)
1138 const struct fifo_cfg *cfg;
1141 struct musb_hw_ep *hw_ep = musb->endpoints;
1143 switch (fifo_mode) {
1149 n = ARRAY_SIZE(mode_0_cfg);
1153 n = ARRAY_SIZE(mode_1_cfg);
1157 n = ARRAY_SIZE(mode_2_cfg);
1161 n = ARRAY_SIZE(mode_3_cfg);
1165 n = ARRAY_SIZE(mode_4_cfg);
1169 printk(KERN_DEBUG "%s: setup fifo_mode %d\n",
1170 musb_driver_name, fifo_mode);
1173 offset = fifo_setup(musb, hw_ep, &ep0_cfg, 0);
1174 /* assert(offset > 0) */
1176 /* NOTE: for RTL versions >= 1.400 EPINFO and RAMINFO would
1177 * be better than static MUSB_C_NUM_EPS and DYN_FIFO_SIZE...
1180 for (i = 0; i < n; i++) {
1181 u8 epn = cfg->hw_ep_num;
1183 if (epn >= MUSB_C_NUM_EPS) {
1184 pr_debug( "%s: invalid ep %d\n",
1185 musb_driver_name, epn);
1188 offset = fifo_setup(musb, hw_ep + epn, cfg++, offset);
1190 pr_debug( "%s: mem overrun, ep %d\n",
1191 musb_driver_name, epn);
1195 musb->nr_endpoints = max(epn, musb->nr_endpoints);
1198 printk(KERN_DEBUG "%s: %d/%d max ep, %d/%d memory\n",
1200 n + 1, MUSB_C_NUM_EPS * 2 - 1,
1201 offset, DYN_FIFO_SIZE);
1203 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1204 if (!musb->bulk_ep) {
1205 pr_debug( "%s: missing bulk\n", musb_driver_name);
1215 * ep_config_from_hw - when MUSB_C_DYNFIFO_DEF is false
1216 * @param musb the controller
1218 static int __init ep_config_from_hw(struct musb *musb)
1221 struct musb_hw_ep *hw_ep;
1222 void *mbase = musb->mregs;
1224 DBG(2, "<== static silicon ep config\n");
1226 /* FIXME pick up ep0 maxpacket size */
1228 for (epnum = 1; epnum < MUSB_C_NUM_EPS; epnum++) {
1229 musb_ep_select(mbase, epnum);
1230 hw_ep = musb->endpoints + epnum;
1232 /* read from core using indexed model */
1233 reg = musb_readb(hw_ep->regs, 0x10 + MUSB_FIFOSIZE);
1235 /* 0's returned when no more endpoints */
1238 musb->nr_endpoints++;
1239 musb->epmask |= (1 << epnum);
1241 hw_ep->max_packet_sz_tx = 1 << (reg & 0x0f);
1243 /* shared TX/RX FIFO? */
1244 if ((reg & 0xf0) == 0xf0) {
1245 hw_ep->max_packet_sz_rx = hw_ep->max_packet_sz_tx;
1246 hw_ep->is_shared_fifo = true;
1249 hw_ep->max_packet_sz_rx = 1 << ((reg & 0xf0) >> 4);
1250 hw_ep->is_shared_fifo = false;
1253 /* FIXME set up hw_ep->{rx,tx}_double_buffered */
1255 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1256 /* pick an RX/TX endpoint for bulk */
1257 if (hw_ep->max_packet_sz_tx < 512
1258 || hw_ep->max_packet_sz_rx < 512)
1261 /* REVISIT: this algorithm is lazy, we should at least
1262 * try to pick a double buffered endpoint.
1266 musb->bulk_ep = hw_ep;
1270 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1271 if (!musb->bulk_ep) {
1272 pr_debug( "%s: missing bulk\n", musb_driver_name);
1280 enum { MUSB_CONTROLLER_MHDRC, MUSB_CONTROLLER_HDRC, };
1282 /* Initialize MUSB (M)HDRC part of the USB hardware subsystem;
1283 * configure endpoints, or take their config from silicon
1285 static int __init musb_core_init(u16 musb_type, struct musb *musb)
1292 u16 hwvers, rev_major, rev_minor;
1293 char aInfo[78], aRevision[32], aDate[12];
1294 void __iomem *mbase = musb->mregs;
1298 /* log core options (read using indexed model) */
1299 musb_ep_select(mbase, 0);
1300 reg = musb_readb(mbase, 0x10 + MUSB_CONFIGDATA);
1302 strcpy(aInfo, (reg & MUSB_CONFIGDATA_UTMIDW) ? "UTMI-16" : "UTMI-8");
1303 if (reg & MUSB_CONFIGDATA_DYNFIFO) {
1304 strcat(aInfo, ", dyn FIFOs");
1306 if (reg & MUSB_CONFIGDATA_MPRXE) {
1307 strcat(aInfo, ", bulk combine");
1309 musb->bulk_combine = true;
1311 strcat(aInfo, " (X)"); /* no driver support */
1314 if (reg & MUSB_CONFIGDATA_MPTXE) {
1315 strcat(aInfo, ", bulk split");
1317 musb->bulk_split = true;
1319 strcat(aInfo, " (X)"); /* no driver support */
1322 if (reg & MUSB_CONFIGDATA_HBRXE) {
1323 strcat(aInfo, ", HB-ISO Rx");
1324 strcat(aInfo, " (X)"); /* no driver support */
1326 if (reg & MUSB_CONFIGDATA_HBTXE) {
1327 strcat(aInfo, ", HB-ISO Tx");
1328 strcat(aInfo, " (X)"); /* no driver support */
1330 if (reg & MUSB_CONFIGDATA_SOFTCONE) {
1331 strcat(aInfo, ", SoftConn");
1334 printk(KERN_DEBUG "%s: ConfigData=0x%02x (%s)\n",
1335 musb_driver_name, reg, aInfo);
1338 data = musb_readl(mbase, 0x404);
1339 sprintf(aDate, "%04d-%02x-%02x", (data & 0xffff),
1340 (data >> 16) & 0xff, (data >> 24) & 0xff);
1341 /* FIXME ID2 and ID3 are unused */
1342 data = musb_readl(mbase, 0x408);
1343 printk("ID2=%lx\n", (long unsigned)data);
1344 data = musb_readl(mbase, 0x40c);
1345 printk("ID3=%lx\n", (long unsigned)data);
1346 reg = musb_readb(mbase, 0x400);
1347 musb_type = ('M' == reg) ? MUSB_CONTROLLER_MHDRC : MUSB_CONTROLLER_HDRC;
1351 if (MUSB_CONTROLLER_MHDRC == musb_type) {
1352 musb->is_multipoint = 1;
1355 musb->is_multipoint = 0;
1357 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1358 #ifndef CONFIG_USB_OTG_BLACKLIST_HUB
1360 "%s: kernel must blacklist external hubs\n",
1366 /* log release info */
1367 hwvers = musb_readw(mbase, MUSB_HWVERS);
1368 rev_major = (hwvers >> 10) & 0x1f;
1369 rev_minor = hwvers & 0x3ff;
1370 snprintf(aRevision, 32, "%d.%d%s", rev_major,
1371 rev_minor, (hwvers & 0x8000) ? "RC" : "");
1372 printk(KERN_DEBUG "%s: %sHDRC RTL version %s %s\n",
1373 musb_driver_name, type, aRevision, aDate);
1376 musb->endpoints[0].max_packet_sz_tx = MUSB_EP0_FIFOSIZE;
1377 musb->endpoints[0].max_packet_sz_rx = MUSB_EP0_FIFOSIZE;
1379 /* discover endpoint configuration */
1380 musb->nr_endpoints = 1;
1383 if (reg & MUSB_CONFIGDATA_DYNFIFO) {
1385 status = ep_config_from_table(musb);
1387 ERR("reconfigure software for Dynamic FIFOs\n");
1392 status = ep_config_from_hw(musb);
1394 ERR("reconfigure software for static FIFOs\n");
1402 /* finish init, and print endpoint config */
1403 for (i = 0; i < musb->nr_endpoints; i++) {
1404 struct musb_hw_ep *hw_ep = musb->endpoints + i;
1406 hw_ep->fifo = MUSB_FIFO_OFFSET(i) + mbase;
1407 #ifdef CONFIG_USB_TUSB6010
1408 hw_ep->fifo_async = musb->async + 0x400 + MUSB_FIFO_OFFSET(i);
1409 hw_ep->fifo_sync = musb->sync + 0x400 + MUSB_FIFO_OFFSET(i);
1410 hw_ep->fifo_sync_va =
1411 musb->sync_va + 0x400 + MUSB_FIFO_OFFSET(i);
1414 hw_ep->conf = mbase - 0x400 + TUSB_EP0_CONF;
1416 hw_ep->conf = mbase + 0x400 + (((i - 1) & 0xf) << 2);
1419 hw_ep->regs = MUSB_EP_OFFSET(i, 0) + mbase;
1420 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1421 hw_ep->target_regs = MUSB_BUSCTL_OFFSET(i, 0) + mbase;
1422 hw_ep->rx_reinit = 1;
1423 hw_ep->tx_reinit = 1;
1426 if (hw_ep->max_packet_sz_tx) {
1428 "%s: hw_ep %d%s, %smax %d\n",
1429 musb_driver_name, i,
1430 hw_ep->is_shared_fifo ? "shared" : "tx",
1431 hw_ep->tx_double_buffered
1432 ? "doublebuffer, " : "",
1433 hw_ep->max_packet_sz_tx);
1435 if (hw_ep->max_packet_sz_rx && !hw_ep->is_shared_fifo) {
1437 "%s: hw_ep %d%s, %smax %d\n",
1438 musb_driver_name, i,
1440 hw_ep->rx_double_buffered
1441 ? "doublebuffer, " : "",
1442 hw_ep->max_packet_sz_rx);
1444 if (!(hw_ep->max_packet_sz_tx || hw_ep->max_packet_sz_rx))
1445 DBG(1, "hw_ep %d not configured\n", i);
1451 /*-------------------------------------------------------------------------*/
1453 #if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3430)
1455 static irqreturn_t generic_interrupt(int irq, void *__hci)
1457 unsigned long flags;
1458 irqreturn_t retval = IRQ_NONE;
1459 struct musb *musb = __hci;
1461 spin_lock_irqsave(&musb->lock, flags);
1463 musb->int_usb = musb_readb(musb->mregs, MUSB_INTRUSB);
1464 musb->int_tx = musb_readw(musb->mregs, MUSB_INTRTX);
1465 musb->int_rx = musb_readw(musb->mregs, MUSB_INTRRX);
1467 if (musb->int_usb || musb->int_tx || musb->int_rx)
1468 retval = musb_interrupt(musb);
1470 spin_unlock_irqrestore(&musb->lock, flags);
1472 /* REVISIT we sometimes get spurious IRQs on g_ep0
1475 if (retval != IRQ_HANDLED)
1476 DBG(5, "spurious?\n");
1482 #define generic_interrupt NULL
1486 * handle all the irqs defined by the HDRC core. for now we expect: other
1487 * irq sources (phy, dma, etc) will be handled first, musb->int_* values
1488 * will be assigned, and the irq will already have been acked.
1490 * called in irq context with spinlock held, irqs blocked
1492 irqreturn_t musb_interrupt(struct musb *musb)
1494 irqreturn_t retval = IRQ_NONE;
1499 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
1500 power = musb_readb(musb->mregs, MUSB_POWER);
1502 DBG(4, "** IRQ %s usb%04x tx%04x rx%04x\n",
1503 (devctl & MUSB_DEVCTL_HM) ? "host" : "peripheral",
1504 musb->int_usb, musb->int_tx, musb->int_rx);
1506 /* the core can interrupt us for multiple reasons; docs have
1507 * a generic interrupt flowchart to follow
1509 if (musb->int_usb & STAGE0_MASK)
1510 retval |= musb_stage0_irq(musb, musb->int_usb,
1513 /* "stage 1" is handling endpoint irqs */
1515 /* handle endpoint 0 first */
1516 if (musb->int_tx & 1) {
1517 if (devctl & MUSB_DEVCTL_HM)
1518 retval |= musb_h_ep0_irq(musb);
1520 retval |= musb_g_ep0_irq(musb);
1523 /* RX on endpoints 1-15 */
1524 reg = musb->int_rx >> 1;
1528 /* musb_ep_select(musb->mregs, ep_num); */
1529 /* REVISIT just retval = ep->rx_irq(...) */
1530 retval = IRQ_HANDLED;
1531 if (devctl & MUSB_DEVCTL_HM) {
1532 if (is_host_capable())
1533 musb_host_rx(musb, ep_num);
1535 if (is_peripheral_capable())
1536 musb_g_rx(musb, ep_num);
1544 /* TX on endpoints 1-15 */
1545 reg = musb->int_tx >> 1;
1549 /* musb_ep_select(musb->mregs, ep_num); */
1550 /* REVISIT just retval |= ep->tx_irq(...) */
1551 retval = IRQ_HANDLED;
1552 if (devctl & MUSB_DEVCTL_HM) {
1553 if (is_host_capable())
1554 musb_host_tx(musb, ep_num);
1556 if (is_peripheral_capable())
1557 musb_g_tx(musb, ep_num);
1564 /* finish handling "global" interrupts after handling fifos */
1566 retval |= musb_stage2_irq(musb,
1567 musb->int_usb, devctl, power);
1573 #ifndef CONFIG_MUSB_PIO_ONLY
1574 static int __initdata use_dma = 1;
1576 /* "modprobe ... use_dma=0" etc */
1577 module_param(use_dma, bool, 0);
1578 MODULE_PARM_DESC(use_dma, "enable/disable use of DMA");
1580 void musb_dma_completion(struct musb *musb, u8 epnum, u8 transmit)
1582 u8 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
1584 /* called with controller lock already held */
1587 #ifndef CONFIG_USB_TUSB_OMAP_DMA
1588 if (!is_cppi_enabled()) {
1590 if (devctl & MUSB_DEVCTL_HM)
1591 musb_h_ep0_irq(musb);
1593 musb_g_ep0_irq(musb);
1597 /* endpoints 1..15 */
1599 if (devctl & MUSB_DEVCTL_HM) {
1600 if (is_host_capable())
1601 musb_host_tx(musb, epnum);
1603 if (is_peripheral_capable())
1604 musb_g_tx(musb, epnum);
1608 if (devctl & MUSB_DEVCTL_HM) {
1609 if (is_host_capable())
1610 musb_host_rx(musb, epnum);
1612 if (is_peripheral_capable())
1613 musb_g_rx(musb, epnum);
1623 /*-------------------------------------------------------------------------*/
1628 musb_mode_show(struct device *dev, struct device_attribute *attr, char *buf)
1630 struct musb *musb = dev_to_musb(dev);
1631 unsigned long flags;
1634 spin_lock_irqsave(&musb->lock, flags);
1635 ret = sprintf(buf, "%s\n", otg_state_string(musb));
1636 spin_unlock_irqrestore(&musb->lock, flags);
1642 musb_mode_store(struct device *dev, struct device_attribute *attr,
1643 const char *buf, size_t n)
1645 struct musb *musb = dev_to_musb(dev);
1646 unsigned long flags;
1648 spin_lock_irqsave(&musb->lock, flags);
1649 if (!strncmp(buf, "host", 4))
1650 musb_platform_set_mode(musb, MUSB_HOST);
1651 if (!strncmp(buf, "peripheral", 10))
1652 musb_platform_set_mode(musb, MUSB_PERIPHERAL);
1653 if (!strncmp(buf, "otg", 3))
1654 musb_platform_set_mode(musb, MUSB_OTG);
1655 spin_unlock_irqrestore(&musb->lock, flags);
1659 static DEVICE_ATTR(mode, 0644, musb_mode_show, musb_mode_store);
1662 musb_cable_show(struct device *dev, struct device_attribute *attr, char *buf)
1664 struct musb *musb = dev_to_musb(dev);
1665 char *v1= "", *v2 = "?";
1666 unsigned long flags;
1669 spin_lock_irqsave(&musb->lock, flags);
1670 #if defined(CONFIG_USB_TUSB6010) && !defined(CONFIG_USB_MUSB_OTG)
1671 /* REVISIT: connect-A != connect-B ... */
1672 vbus = musb_platform_get_vbus_status(musb);
1676 v2 = "disconnected";
1678 /* NOTE: board-specific issues, like too-big capacitors keeping
1679 * VBUS high for a long time after power has been removed, can
1680 * cause temporary false indications of a connection.
1682 vbus = musb_readb(musb->mregs, MUSB_DEVCTL);
1684 /* REVISIT retest on real OTG hardware */
1685 switch (musb->board_mode) {
1689 case MUSB_PERIPHERAL:
1694 v2 = (vbus & MUSB_DEVCTL_BDEVICE) ? "B" : "A";
1697 } else /* VBUS level below A-Valid */
1698 v2 = "disconnected";
1700 musb_platform_try_idle(musb, 0);
1701 spin_unlock_irqrestore(&musb->lock, flags);
1703 return sprintf(buf, "%s%s\n", v1, v2);
1705 static DEVICE_ATTR(cable, S_IRUGO, musb_cable_show, NULL);
1708 musb_vbus_store(struct device *dev, struct device_attribute *attr,
1709 const char *buf, size_t n)
1711 struct musb *musb = dev_to_musb(dev);
1712 unsigned long flags;
1715 if (sscanf(buf, "%lu", &val) < 1) {
1716 printk(KERN_ERR "Invalid VBUS timeout ms value\n");
1720 spin_lock_irqsave(&musb->lock, flags);
1721 musb->a_wait_bcon = val;
1722 if (musb->xceiv.state == OTG_STATE_A_WAIT_BCON)
1723 musb->is_active = 0;
1724 musb_platform_try_idle(musb, jiffies + msecs_to_jiffies(val));
1725 spin_unlock_irqrestore(&musb->lock, flags);
1731 musb_vbus_show(struct device *dev, struct device_attribute *attr, char *buf)
1733 struct musb *musb = dev_to_musb(dev);
1734 unsigned long flags;
1737 spin_lock_irqsave(&musb->lock, flags);
1738 val = musb->a_wait_bcon;
1739 spin_unlock_irqrestore(&musb->lock, flags);
1741 return sprintf(buf, "%lu\n", val);
1743 static DEVICE_ATTR(vbus, 0644, musb_vbus_show, musb_vbus_store);
1745 #ifdef CONFIG_USB_GADGET_MUSB_HDRC
1747 /* Gadget drivers can't know that a host is connected so they might want
1748 * to start SRP, but users can. This allows userspace to trigger SRP.
1751 musb_srp_store(struct device *dev, struct device_attribute *attr,
1752 const char *buf, size_t n)
1754 struct musb *musb=dev_to_musb(dev);
1757 if (sscanf(buf, "%hu", &srp) != 1
1759 printk (KERN_ERR "SRP: Value must be 1\n");
1764 musb_g_wakeup(musb);
1768 static DEVICE_ATTR(srp, 0644, NULL, musb_srp_store);
1770 #endif /* CONFIG_USB_GADGET_MUSB_HDRC */
1774 /* Only used to provide driver mode change events */
1775 static void musb_irq_work(struct work_struct *data)
1777 struct musb *musb = container_of(data, struct musb, irq_work);
1778 static int old_state;
1780 if (musb->xceiv.state != old_state) {
1781 old_state = musb->xceiv.state;
1782 sysfs_notify(&musb->controller->kobj, NULL, "cable");
1783 sysfs_notify(&musb->controller->kobj, NULL, "mode");
1787 /* --------------------------------------------------------------------------
1791 static struct musb *__init
1792 allocate_instance(struct device *dev, void __iomem *mbase)
1795 struct musb_hw_ep *ep;
1797 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1798 struct usb_hcd *hcd;
1800 hcd = usb_create_hcd(&musb_hc_driver, dev, dev->bus_id);
1803 /* usbcore sets dev->driver_data to hcd, and sometimes uses that... */
1805 musb = hcd_to_musb(hcd);
1806 INIT_LIST_HEAD(&musb->control);
1807 INIT_LIST_HEAD(&musb->in_bulk);
1808 INIT_LIST_HEAD(&musb->out_bulk);
1810 hcd->uses_new_polling = 1;
1812 musb->vbuserr_retry = VBUSERR_RETRY_COUNT;
1814 musb = kzalloc(sizeof *musb, GFP_KERNEL);
1817 dev_set_drvdata(dev, musb);
1821 musb->mregs = mbase;
1822 musb->ctrl_base = mbase;
1823 musb->nIrq = -ENODEV;
1824 for (epnum = 0, ep = musb->endpoints;
1825 epnum < MUSB_C_NUM_EPS;
1832 #ifdef CONFIG_USB_MUSB_OTG
1833 otg_set_transceiver(&musb->xceiv);
1835 musb->controller = dev;
1839 static void musb_free(struct musb *musb)
1841 /* this has multiple entry modes. it handles fault cleanup after
1842 * probe(), where things may be partially set up, as well as rmmod
1843 * cleanup after everything's been de-activated.
1847 device_remove_file(musb->controller, &dev_attr_mode);
1848 device_remove_file(musb->controller, &dev_attr_cable);
1849 device_remove_file(musb->controller, &dev_attr_vbus);
1850 #ifdef CONFIG_USB_MUSB_OTG
1851 device_remove_file(musb->controller, &dev_attr_srp);
1855 #ifdef CONFIG_USB_GADGET_MUSB_HDRC
1856 musb_gadget_cleanup(musb);
1859 if (musb->nIrq >= 0) {
1860 disable_irq_wake(musb->nIrq);
1861 free_irq(musb->nIrq, musb);
1863 if (is_dma_capable() && musb->dma_controller) {
1864 struct dma_controller *c = musb->dma_controller;
1866 (void) c->stop(c->private_data);
1867 dma_controller_destroy(c);
1870 musb_writeb(musb->mregs, MUSB_DEVCTL, 0);
1871 musb_platform_exit(musb);
1872 musb_writeb(musb->mregs, MUSB_DEVCTL, 0);
1875 clk_disable(musb->clock);
1876 clk_put(musb->clock);
1879 #ifdef CONFIG_USB_MUSB_OTG
1880 put_device(musb->xceiv.dev);
1883 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1884 usb_put_hcd(musb_to_hcd(musb));
1891 * Perform generic per-controller initialization.
1893 * @pDevice: the controller (already clocked, etc)
1895 * @mregs: virtual address of controller registers,
1896 * not yet corrected for platform-specific offsets
1899 musb_init_controller(struct device *dev, int nIrq, void __iomem *ctrl)
1903 struct musb_hdrc_platform_data *plat = dev->platform_data;
1905 /* The driver might handle more features than the board; OK.
1906 * Fail when the board needs a feature that's not enabled.
1909 dev_dbg(dev, "no platform_data?\n");
1912 switch (plat->mode) {
1914 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1919 case MUSB_PERIPHERAL:
1920 #ifdef CONFIG_USB_GADGET_MUSB_HDRC
1926 #ifdef CONFIG_USB_MUSB_OTG
1932 dev_err(dev, "incompatible Kconfig role setting\n");
1937 musb = allocate_instance(dev, ctrl);
1941 spin_lock_init(&musb->lock);
1942 musb->board_mode = plat->mode;
1943 musb->board_set_power = plat->set_power;
1944 musb->set_clock = plat->set_clock;
1945 musb->min_power = plat->min_power;
1947 /* Clock usage is chip-specific ... functional clock (DaVinci,
1948 * OMAP2430), or PHY ref (some TUSB6010 boards). All this core
1949 * code does is make sure a clock handle is available; platform
1950 * code manages it during start/stop and suspend/resume.
1953 musb->clock = clk_get(dev, plat->clock);
1954 if (IS_ERR(musb->clock)) {
1955 status = PTR_ERR(musb->clock);
1961 /* assume vbus is off */
1963 /* platform adjusts musb->mregs and musb->isr if needed,
1964 * and activates clocks
1966 musb->isr = generic_interrupt;
1967 status = musb_platform_init(musb);
1976 #ifndef CONFIG_MUSB_PIO_ONLY
1977 if (use_dma && dev->dma_mask) {
1978 struct dma_controller *c;
1980 c = dma_controller_create(musb, musb->mregs);
1981 musb->dma_controller = c;
1983 (void) c->start(c->private_data);
1986 /* ideally this would be abstracted in platform setup */
1987 if (!is_dma_capable() || !musb->dma_controller)
1988 dev->dma_mask = NULL;
1990 /* be sure interrupts are disabled before connecting ISR */
1991 musb_platform_disable(musb);
1992 musb_generic_disable(musb);
1994 /* setup musb parts of the core (especially endpoints) */
1995 status = musb_core_init(plat->multipoint
1996 ? MUSB_CONTROLLER_MHDRC
1997 : MUSB_CONTROLLER_HDRC, musb);
2001 /* attach to the IRQ */
2002 if (request_irq (nIrq, musb->isr, 0, dev->bus_id, musb)) {
2003 dev_err(dev, "request_irq %d failed!\n", nIrq);
2008 /* FIXME this handles wakeup irqs wrong */
2009 if (enable_irq_wake(nIrq) == 0)
2010 device_init_wakeup(dev, 1);
2012 pr_info("%s: USB %s mode controller at %p using %s, IRQ %d\n",
2015 switch (musb->board_mode) {
2016 case MUSB_HOST: s = "Host"; break;
2017 case MUSB_PERIPHERAL: s = "Peripheral"; break;
2018 default: s = "OTG"; break;
2021 (is_dma_capable() && musb->dma_controller)
2025 #ifdef CONFIG_USB_MUSB_HDRC_HCD
2026 /* host side needs more setup, except for no-host modes */
2027 if (musb->board_mode != MUSB_PERIPHERAL) {
2028 struct usb_hcd *hcd = musb_to_hcd(musb);
2030 if (musb->board_mode == MUSB_OTG)
2031 hcd->self.otg_port = 1;
2032 musb->xceiv.host = &hcd->self;
2033 hcd->power_budget = 2 * (plat->power ? : 250);
2035 #endif /* CONFIG_USB_MUSB_HDRC_HCD */
2037 /* For the host-only role, we can activate right away.
2038 * (We expect the ID pin to be forcibly grounded!!)
2039 * Otherwise, wait till the gadget driver hooks up.
2041 if (!is_otg_enabled(musb) && is_host_enabled(musb)) {
2042 MUSB_HST_MODE(musb);
2043 musb->xceiv.default_a = 1;
2044 musb->xceiv.state = OTG_STATE_A_IDLE;
2046 status = usb_add_hcd(musb_to_hcd(musb), -1, 0);
2048 DBG(1, "%s mode, status %d, devctl %02x %c\n",
2050 musb_readb(musb->mregs, MUSB_DEVCTL),
2051 (musb_readb(musb->mregs, MUSB_DEVCTL)
2052 & MUSB_DEVCTL_BDEVICE
2055 } else /* peripheral is enabled */ {
2056 MUSB_DEV_MODE(musb);
2057 musb->xceiv.default_a = 0;
2058 musb->xceiv.state = OTG_STATE_B_IDLE;
2060 status = musb_gadget_setup(musb);
2062 DBG(1, "%s mode, status %d, dev%02x\n",
2063 is_otg_enabled(musb) ? "OTG" : "PERIPHERAL",
2065 musb_readb(musb->mregs, MUSB_DEVCTL));
2070 musb_debug_create("driver/musb_hdrc", musb);
2074 clk_put(musb->clock);
2075 device_init_wakeup(dev, 0);
2080 INIT_WORK(&musb->irq_work, musb_irq_work);
2083 status = device_create_file(dev, &dev_attr_mode);
2084 status = device_create_file(dev, &dev_attr_cable);
2085 status = device_create_file(dev, &dev_attr_vbus);
2086 #ifdef CONFIG_USB_GADGET_MUSB_HDRC
2087 status = device_create_file(dev, &dev_attr_srp);
2088 #endif /* CONFIG_USB_GADGET_MUSB_HDRC */
2095 musb_platform_exit(musb);
2099 /*-------------------------------------------------------------------------*/
2101 /* all implementations (PCI bridge to FPGA, VLYNQ, etc) should just
2102 * bridge to a platform device; this driver then suffices.
2105 #ifndef CONFIG_MUSB_PIO_ONLY
2106 static u64 *orig_dma_mask;
2109 static int __init musb_probe(struct platform_device *pdev)
2111 struct device *dev = &pdev->dev;
2112 int irq = platform_get_irq(pdev, 0);
2113 struct resource *iomem;
2116 iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2117 if (!iomem || irq == 0)
2120 base = ioremap(iomem->start, iomem->end - iomem->start + 1);
2122 dev_err(dev, "ioremap failed\n");
2126 #ifndef CONFIG_MUSB_PIO_ONLY
2127 /* clobbered by use_dma=n */
2128 orig_dma_mask = dev->dma_mask;
2130 return musb_init_controller(dev, irq, base);
2133 static int __devexit musb_remove(struct platform_device *pdev)
2135 struct musb *musb = dev_to_musb(&pdev->dev);
2136 void __iomem *ctrl_base = musb->ctrl_base;
2138 /* this gets called on rmmod.
2139 * - Host mode: host may still be active
2140 * - Peripheral mode: peripheral is deactivated (or never-activated)
2141 * - OTG mode: both roles are deactivated (or never-activated)
2143 musb_shutdown(pdev);
2144 musb_debug_delete("driver/musb_hdrc", musb);
2145 #ifdef CONFIG_USB_MUSB_HDRC_HCD
2146 if (musb->board_mode == MUSB_HOST)
2147 usb_remove_hcd(musb_to_hcd(musb));
2151 device_init_wakeup(&pdev->dev, 0);
2152 #ifndef CONFIG_MUSB_PIO_ONLY
2153 pdev->dev.dma_mask = orig_dma_mask;
2160 static int musb_suspend(struct platform_device *pdev, pm_message_t message)
2162 unsigned long flags;
2163 struct musb *musb = dev_to_musb(&pdev->dev);
2168 spin_lock_irqsave(&musb->lock, flags);
2170 if (is_peripheral_active(musb)) {
2171 /* FIXME force disconnect unless we know USB will wake
2172 * the system up quickly enough to respond ...
2174 } else if (is_host_active(musb)) {
2175 /* we know all the children are suspended; sometimes
2176 * they will even be wakeup-enabled.
2180 if (musb->set_clock)
2181 musb->set_clock(musb->clock, 0);
2183 clk_disable(musb->clock);
2184 spin_unlock_irqrestore(&musb->lock, flags);
2188 static int musb_resume(struct platform_device *pdev)
2190 unsigned long flags;
2191 struct musb *musb = dev_to_musb(&pdev->dev);
2196 spin_lock_irqsave(&musb->lock, flags);
2198 if (musb->set_clock)
2199 musb->set_clock(musb->clock, 1);
2201 clk_enable(musb->clock);
2203 /* for static cmos like DaVinci, register values were preserved
2204 * unless for some reason the whole soc powered down and we're
2205 * not treating that as a whole-system restart (e.g. swsusp)
2207 spin_unlock_irqrestore(&musb->lock, flags);
2212 #define musb_suspend NULL
2213 #define musb_resume NULL
2216 static struct platform_driver musb_driver = {
2218 .name = (char *)musb_driver_name,
2219 .bus = &platform_bus_type,
2220 .owner = THIS_MODULE,
2222 .remove = __devexit_p(musb_remove),
2223 .shutdown = musb_shutdown,
2224 .suspend = musb_suspend,
2225 .resume = musb_resume,
2228 /*-------------------------------------------------------------------------*/
2230 static int __init musb_init(void)
2232 #ifdef CONFIG_USB_MUSB_HDRC_HCD
2237 pr_info("%s: version " MUSB_VERSION ", "
2238 #ifdef CONFIG_MUSB_PIO_ONLY
2240 #elif defined(CONFIG_USB_TI_CPPI_DMA)
2242 #elif defined(CONFIG_USB_INVENTRA_DMA)
2244 #elif defined(CONFIG_USB_TUSB_OMAP_DMA)
2250 #ifdef CONFIG_USB_MUSB_OTG
2251 "otg (peripheral+host)"
2252 #elif defined(CONFIG_USB_GADGET_MUSB_HDRC)
2254 #elif defined(CONFIG_USB_MUSB_HDRC_HCD)
2258 musb_driver_name, debug);
2259 return platform_driver_probe(&musb_driver, musb_probe);
2262 /* make us init after usbcore and before usb
2263 * gadget and host-side drivers start to register
2265 subsys_initcall(musb_init);
2267 static void __exit musb_cleanup(void)
2269 platform_driver_unregister(&musb_driver);
2271 module_exit(musb_cleanup);