1 /******************************************************************
2 * Copyright 2005 Mentor Graphics Corporation
3 * Copyright (C) 2005-2006 by Texas Instruments
4 * Copyright (C) 2006 by Nokia Corporation
6 * This file is part of the Inventra Controller Driver for Linux.
8 * The Inventra Controller Driver for Linux is free software; you
9 * can redistribute it and/or modify it under the terms of the GNU
10 * General Public License version 2 as published by the Free Software
13 * The Inventra Controller Driver for Linux is distributed in
14 * the hope that it will be useful, but WITHOUT ANY WARRANTY;
15 * without even the implied warranty of MERCHANTABILITY or
16 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
17 * License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with The Inventra Controller Driver for Linux ; if not,
21 * write to the Free Software Foundation, Inc., 59 Temple Place,
22 * Suite 330, Boston, MA 02111-1307 USA
24 * ANY DOWNLOAD, USE, REPRODUCTION, MODIFICATION OR DISTRIBUTION
25 * OF THIS DRIVER INDICATES YOUR COMPLETE AND UNCONDITIONAL ACCEPTANCE
26 * OF THOSE TERMS.THIS DRIVER IS PROVIDED "AS IS" AND MENTOR GRAPHICS
27 * MAKES NO WARRANTIES, EXPRESS OR IMPLIED, RELATED TO THIS DRIVER.
28 * MENTOR GRAPHICS SPECIFICALLY DISCLAIMS ALL IMPLIED WARRANTIES
29 * OF MERCHANTABILITY; FITNESS FOR A PARTICULAR PURPOSE AND
30 * NON-INFRINGEMENT. MENTOR GRAPHICS DOES NOT PROVIDE SUPPORT
31 * SERVICES OR UPDATES FOR THIS DRIVER, EVEN IF YOU ARE A MENTOR
32 * GRAPHICS SUPPORT CUSTOMER.
33 ******************************************************************/
35 #include <linux/config.h>
36 #include <linux/module.h>
37 #include <linux/pci.h>
38 #include <linux/kernel.h>
39 #include <linux/delay.h>
40 #include <linux/sched.h>
41 #include <linux/slab.h>
42 #include <linux/errno.h>
43 #include <linux/init.h>
44 #include <linux/list.h>
47 #include "musb_host.h"
50 /* MUSB HOST status 22-mar-2006
52 * - There's still lots of partial code duplication for fault paths, so
53 * they aren't handled as consistently as they need to be.
55 * - PIO mostly behaved when last tested.
56 * + including ep0, with all usbtest cases 9, 10
57 * + usbtest 14 (ep0out) doesn't seem to run at all
58 * + double buffered OUT/TX endpoints saw stalls(!) with certain usbtest
59 * configurations, but otherwise double buffering passes basic tests.
60 * + for 2.6.N, for N > ~10, needs API changes for hcd framework.
62 * - DMA (CPPI) ... partially behaves, not currently recommended
63 * + about 1/15 the speed of typical EHCI implementations (PCI)
64 * + RX, all too often reqpkt seems to misbehave after tx
65 * + TX, no known issues (other than evident silicon issue)
67 * - DMA (Mentor/OMAP) ...has at least toggle update problems
69 * - Still no traffic scheduling code to make NAKing for bulk or control
70 * transfers unable to starve other requests; or to make efficient use
71 * of hardware with periodic transfers. (Note that network drivers
72 * commonly post bulk reads that stay pending for a long time; these
73 * would make very visible trouble.)
75 * - Not tested with HNP, but some SRP paths seem to behave.
79 * - Bulk traffic finally uses both sides of hardware ep1, freeing up an
80 * extra endpoint for periodic use enabling hub + keybd + mouse. That
81 * mostly works, except that with "usbnet" it's easy to trigger cases
82 * with "ping" where RX loses. (a) ping to davinci, even "ping -f",
83 * fine; but (b) ping _from_ davinci, even "ping -c 1", ICMP RX loses
84 * although ARP RX wins. (That test was done with a full speed link.)
89 * NOTE on endpoint usage:
91 * CONTROL transfers all go through ep0. BULK ones go through dedicated IN
92 * and OUT endpoints ... hardware is dedicated for those "async" queue(s).
94 * (Yes, bulk _could_ use more of the endpoints than that, and would even
95 * benefit from it ... one remote device may easily be NAKing while others
96 * need to perform transfers in that same direction. The same thing could
97 * be done in software though, assuming dma cooperates.)
99 * INTERUPPT and ISOCHRONOUS transfers are scheduled to the other endpoints.
100 * So far that scheduling is both dumb and optimistic: the endpoint will be
101 * "claimed" until its software queue is no longer refilled. No multiplexing
102 * of transfers between endpoints, or anything clever.
106 /*************************** Forwards ***************************/
108 static void musb_ep_program(struct musb *pThis, u8 bEnd,
109 struct urb *pUrb, unsigned int nOut,
110 u8 * pBuffer, u32 dwLength);
113 * Start transmit. Caller is responsible for locking shared resources.
114 * pThis must be locked.
116 void musb_h_tx_start(struct musb *pThis, u8 bEnd)
119 void __iomem *pBase = pThis->pRegs;
121 /* NOTE: no locks here; caller should lock */
122 MGC_SelectEnd(pBase, bEnd);
124 wCsr = MGC_ReadCsr16(pBase, MGC_O_HDRC_TXCSR, bEnd);
125 wCsr |= MGC_M_TXCSR_TXPKTRDY | MGC_M_TXCSR_H_WZC_BITS;
126 DBG(5, "Writing TXCSR%d = %x\n", bEnd, wCsr);
127 MGC_WriteCsr16(pBase, MGC_O_HDRC_TXCSR, bEnd, wCsr);
129 wCsr = MGC_M_CSR0_H_SETUPPKT | MGC_M_CSR0_TXPKTRDY;
130 MGC_WriteCsr16(pBase, MGC_O_HDRC_CSR0, 0, wCsr);
135 #ifdef CONFIG_USB_TI_CPPI_DMA
137 void cppi_hostdma_start(struct musb *pThis, u8 bEnd)
139 void __iomem *pBase = pThis->pRegs;
142 /* NOTE: no locks here; caller should lock */
143 MGC_SelectEnd(pBase, bEnd);
144 txCsr = MGC_ReadCsr16(pBase, MGC_O_HDRC_TXCSR, bEnd);
145 txCsr |= MGC_M_TXCSR_DMAENAB | MGC_M_TXCSR_H_WZC_BITS;
146 MGC_WriteCsr16(pBase, MGC_O_HDRC_TXCSR, bEnd, txCsr);
152 * Start the URB at the front of an endpoint's queue
153 * end must be claimed from the caller.
155 * Context: controller locked, irqs blocked
158 musb_start_urb(struct musb *musb, int is_in, struct musb_qh *qh)
163 void __iomem *pBase = musb->pRegs;
164 struct urb *urb = next_urb(qh);
165 struct musb_hw_ep *pEnd = qh->hw_ep;
166 unsigned nPipe = urb->pipe;
167 u8 bAddress = usb_pipedevice(nPipe);
168 int bEnd = pEnd->bLocalEnd;
170 /* initialize software qh state */
174 /* gather right source of data */
176 case USB_ENDPOINT_XFER_CONTROL:
177 /* control transfers always start with SETUP */
180 musb->bEnd0Stage = MGC_END0_START;
181 pBuffer = urb->setup_packet;
184 case USB_ENDPOINT_XFER_ISOC:
187 pBuffer = urb->transfer_buffer + urb->iso_frame_desc[0].offset;
188 dwLength = urb->iso_frame_desc[0].length;
190 default: /* bulk, interrupt */
191 pBuffer = urb->transfer_buffer;
192 dwLength = urb->transfer_buffer_length;
195 DBG(4, "qh %p urb %p dev%d ep%d%s%s, hw_ep %d, %p/%d\n",
196 qh, urb, bAddress, qh->epnum,
197 is_in ? "in" : "out",
198 ({char *s; switch (qh->type) {
199 case USB_ENDPOINT_XFER_CONTROL: s = ""; break;
200 case USB_ENDPOINT_XFER_BULK: s = "-bulk"; break;
201 case USB_ENDPOINT_XFER_ISOC: s = "-iso"; break;
202 default: s = "-intr"; break;
204 bEnd, pBuffer, dwLength);
206 /* Configure endpoint */
207 if (is_in || pEnd->bIsSharedFifo)
211 musb_ep_program(musb, bEnd, urb, !is_in, pBuffer, dwLength);
213 /* transmit may have more work: start it when it is time */
217 /* determine if the time is right for a periodic transfer */
219 case USB_ENDPOINT_XFER_ISOC:
220 case USB_ENDPOINT_XFER_INT:
221 DBG(3, "check whether there's still time for periodic Tx\n");
223 wFrame = musb_readw(pBase, MGC_O_HDRC_FRAME);
224 /* FIXME this doesn't implement that scheduling policy ...
225 * or handle framecounter wrapping
227 if ((urb->transfer_flags & URB_ISO_ASAP)
228 || (wFrame >= urb->start_frame)) {
229 /* REVISIT the SOF irq handler shouldn't duplicate
230 * this code... or the branch below...
231 * ... and we don't set urb->start_frame
234 printk("Start --> periodic TX%s on %d\n",
235 pEnd->tx_channel ? " DMA" : "",
237 if (!pEnd->tx_channel)
238 musb_h_tx_start(musb, bEnd);
240 cppi_hostdma_start(musb, bEnd);
242 qh->frame = urb->start_frame;
243 /* enable SOF interrupt so we can count down */
244 DBG(1,"SOF for %d\n", bEnd);
245 #if 1 // ifndef CONFIG_ARCH_DAVINCI
246 musb_writeb(pBase, MGC_O_HDRC_INTRUSBE, 0xff);
251 DBG(4, "Start TX%d %s\n", bEnd,
252 pEnd->tx_channel ? "dma" : "pio");
254 if (!pEnd->tx_channel)
255 musb_h_tx_start(musb, bEnd);
257 cppi_hostdma_start(musb, bEnd);
261 /* caller owns no controller locks, irqs are blocked */
263 __musb_giveback(struct musb_hw_ep *hw_ep, struct urb *urb, int status)
264 __releases(urb->lock)
265 __acquires(urb->lock)
267 struct musb *musb = hw_ep->musb;
269 if ((urb->transfer_flags & URB_SHORT_NOT_OK)
270 && (urb->actual_length < urb->transfer_buffer_length)
272 && usb_pipein(urb->pipe))
275 spin_lock(&urb->lock);
277 if (urb->status == -EINPROGRESS)
278 urb->status = status;
279 spin_unlock(&urb->lock);
281 DBG(({ int level; switch (urb->status) {
285 /* common/boring faults */
295 "complete %p (%d), dev%d ep%d%s, %d/%d\n",
297 usb_pipedevice(urb->pipe),
298 usb_pipeendpoint(urb->pipe),
299 usb_pipein(urb->pipe) ? "in" : "out",
300 urb->actual_length, urb->transfer_buffer_length
303 usb_hcd_giveback_urb(musb_to_hcd(musb), urb, musb->int_regs);
306 /* for bulk/interrupt endpoints only */
307 static inline void musb_save_toggle(struct musb_hw_ep *ep, int is_in, struct urb *urb)
309 struct usb_device *udev = urb->dev;
311 void __iomem *hw = ep->musb->pRegs;
314 /* FIXME: the current Mentor DMA code seems to have
315 * problems getting toggle correct.
318 if (is_in || ep->bIsSharedFifo)
324 csr = MGC_ReadCsr16(hw, MGC_O_HDRC_TXCSR,
326 usb_settoggle(udev, qh->epnum, 1,
327 (csr & MGC_M_TXCSR_H_DATATOGGLE)
330 csr = MGC_ReadCsr16(hw, MGC_O_HDRC_RXCSR,
332 usb_settoggle(udev, qh->epnum, 0,
333 (csr & MGC_M_RXCSR_H_DATATOGGLE)
338 /* caller owns controller lock, irqs are blocked */
339 static struct musb_qh *
340 musb_giveback(struct musb_qh *qh, struct urb *urb, int status)
341 __releases(qh->hw_ep->musb->Lock)
342 __acquires(qh->hw_ep->musb->Lock)
345 struct musb_hw_ep *ep = qh->hw_ep;
346 struct musb *musb = ep->musb;
347 int ready = qh->is_ready;
349 if (ep->bIsSharedFifo)
352 is_in = usb_pipein(urb->pipe);
354 /* save toggle eagerly, for paranoia */
356 case USB_ENDPOINT_XFER_BULK:
357 case USB_ENDPOINT_XFER_INT:
358 musb_save_toggle(ep, is_in, urb);
360 case USB_ENDPOINT_XFER_ISOC:
361 if (status == 0 && urb->error_count)
367 spin_unlock(&musb->Lock);
368 __musb_giveback(ep, urb, status);
369 spin_lock(&musb->Lock);
370 qh->is_ready = ready;
372 /* reclaim resources (and bandwidth) ASAP; deschedule it, and
373 * invalidate qh as soon as list_empty(&hep->urb_list)
375 if (list_empty(&qh->hep->urb_list)) {
376 struct list_head *head;
383 /* clobber old pointers to this qh */
384 if (is_in || ep->bIsSharedFifo)
388 qh->hep->hcpriv = NULL;
392 case USB_ENDPOINT_XFER_ISOC:
393 case USB_ENDPOINT_XFER_INT:
394 /* this is where periodic bandwidth should be
395 * de-allocated if it's tracked and allocated;
396 * and where we'd update the schedule tree...
398 musb->periodic[ep->bLocalEnd] = NULL;
403 case USB_ENDPOINT_XFER_CONTROL:
404 case USB_ENDPOINT_XFER_BULK:
405 /* fifo policy for these lists, except that NAKing
406 * should rotate a qh to the end (for fairness).
408 head = qh->ring.prev;
419 * Advance this hardware endpoint's queue, completing the specified urb and
420 * advancing to either the next urb queued to that qh, or else invalidating
421 * that qh and advancing to the next qh scheduled after the current one.
423 * Context: caller owns controller lock, irqs are blocked
426 musb_advance_schedule(struct musb *pThis, struct urb *urb,
427 struct musb_hw_ep *pEnd, int is_in)
431 if (is_in || pEnd->bIsSharedFifo)
435 qh = musb_giveback(qh, urb, 0);
437 #ifdef CONFIG_USB_INVENTRA_DMA
438 /* REVISIT udelay reportedly works around issues in unmodified
439 * Mentor RTL before v1.5, where it doesn't disable the pull-up
440 * resisters in high speed mode. That causes signal reflection
441 * and errors because inter packet IDLE time vanishes.
443 * Yes, this delay makes DMA-OUT a bit slower than PIO. But
444 * without it, some devices are unusable. But there seem to be
445 * other issues too, at least on DaVinci; the delay improves
446 * some full speed cases, and being DMA-coupled is strange...
448 if (is_dma_capable() && !is_in && pEnd->tx_channel)
449 udelay(15); /* 10 usec ~= 1x 512byte packet */
452 if (qh && qh->is_ready && !list_empty(&qh->hep->urb_list)) {
453 DBG(4, "... next ep%d %cX urb %p\n",
454 pEnd->bLocalEnd, is_in ? 'R' : 'T',
456 musb_start_urb(pThis, is_in, qh);
460 static inline u16 musb_h_flush_rxfifo(struct musb_hw_ep *hw_ep, u16 csr)
462 /* we don't want fifo to fill itself again;
463 * ignore dma (various models),
464 * leave toggle alone (may not have been saved yet)
466 csr |= MGC_M_RXCSR_FLUSHFIFO | MGC_M_RXCSR_RXPKTRDY;
467 csr &= ~( MGC_M_RXCSR_H_REQPKT
468 | MGC_M_RXCSR_H_AUTOREQ
469 | MGC_M_RXCSR_AUTOCLEAR
472 /* write 2x to allow double buffering */
473 musb_writew(hw_ep->regs, MGC_O_HDRC_RXCSR, csr);
474 musb_writew(hw_ep->regs, MGC_O_HDRC_RXCSR, csr);
476 /* flush writebuffer */
477 return musb_readw(hw_ep->regs, MGC_O_HDRC_RXCSR);
481 * PIO RX for a packet (or part of it).
483 static u8 musb_host_packet_rx(struct musb *pThis, struct urb *pUrb,
484 u8 bEnd, u8 bIsochError)
492 void __iomem *pBase = pThis->pRegs;
493 struct musb_hw_ep *pEnd = pThis->aLocalEnd + bEnd;
494 struct musb_qh *qh = pEnd->in_qh;
495 int nPipe = pUrb->pipe;
496 void *buffer = pUrb->transfer_buffer;
498 // MGC_SelectEnd(pBase, bEnd);
499 wRxCount = MGC_ReadCsr16(pBase, MGC_O_HDRC_RXCOUNT, bEnd);
502 if (usb_pipeisoc(nPipe)) {
504 struct usb_iso_packet_descriptor *d;
511 d = pUrb->iso_frame_desc + qh->iso_idx;
512 pBuffer = buffer + d->offset;
514 if (wRxCount > length) {
519 DBG(2, "** OVERFLOW %d into %d\n", wRxCount, length);
523 pUrb->actual_length += length;
524 d->actual_length = length;
528 /* see if we are done */
529 bDone = (++qh->iso_idx >= pUrb->number_of_packets);
532 pBuffer = buffer + qh->offset;
533 length = pUrb->transfer_buffer_length - qh->offset;
534 if (wRxCount > length) {
535 if (pUrb->status == -EINPROGRESS)
536 pUrb->status = -EOVERFLOW;
537 DBG(2, "** OVERFLOW %d into %d\n", wRxCount, length);
541 pUrb->actual_length += length;
542 qh->offset += length;
544 /* see if we are done */
545 bDone = (pUrb->actual_length == pUrb->transfer_buffer_length)
546 || (wRxCount < qh->maxpacket)
547 || (pUrb->status != -EINPROGRESS);
549 && (pUrb->status == -EINPROGRESS)
550 && (pUrb->transfer_flags & URB_SHORT_NOT_OK)
551 && (pUrb->actual_length
552 < pUrb->transfer_buffer_length))
553 pUrb->status = -EREMOTEIO;
556 musb_read_fifo(pEnd, length, pBuffer);
558 wCsr = MGC_ReadCsr16(pBase, MGC_O_HDRC_RXCSR, bEnd);
559 wCsr |= MGC_M_RXCSR_H_WZC_BITS;
560 if (unlikely(do_flush))
561 musb_h_flush_rxfifo(pEnd, wCsr);
563 /* REVISIT this assumes AUTOCLEAR is never set */
564 wCsr &= ~(MGC_M_RXCSR_RXPKTRDY | MGC_M_RXCSR_H_REQPKT);
566 wCsr |= MGC_M_RXCSR_H_REQPKT;
567 MGC_WriteCsr16(pBase, MGC_O_HDRC_RXCSR, bEnd, wCsr);
573 /* we don't always need to reinit a given side of an endpoint...
574 * when we do, use tx/rx reinit routine and then construct a new CSR
575 * to address data toggle, NYET, and DMA or PIO.
577 * it's possible that driver bugs (especially for DMA) or aborting a
578 * transfer might have left the endpoint busier than it should be.
579 * the busy/not-empty tests are basically paranoia.
582 musb_rx_reinit(struct musb *musb, struct musb_qh *qh, struct musb_hw_ep *ep)
586 /* NOTE: we know the "rx" fifo reinit never triggers for ep0.
587 * That always uses tx_reinit since ep0 repurposes TX register
588 * offsets; the initial SETUP packet is also a kind of OUT.
591 /* if programmed for Tx, put it in RX mode */
592 if (ep->bIsSharedFifo) {
593 csr = musb_readw(ep->regs, MGC_O_HDRC_TXCSR);
594 if (csr & MGC_M_TXCSR_MODE) {
595 if (csr & MGC_M_TXCSR_FIFONOTEMPTY) {
596 /* this shouldn't happen; irq?? */
597 ERR("shared fifo not empty?\n");
598 musb_writew(ep->regs, MGC_O_HDRC_TXCSR,
599 MGC_M_TXCSR_FLUSHFIFO);
600 musb_writew(ep->regs, MGC_O_HDRC_TXCSR,
601 MGC_M_TXCSR_FRCDATATOG);
604 /* clear mode (and everything else) to enable Rx */
605 musb_writew(ep->regs, MGC_O_HDRC_TXCSR, 0);
607 /* scrub all previous state, clearing toggle */
609 csr = musb_readw(ep->regs, MGC_O_HDRC_RXCSR);
610 if (csr & MGC_M_RXCSR_RXPKTRDY)
611 WARN("rx%d, packet/%d ready?\n", ep->bLocalEnd,
612 musb_readw(ep->regs, MGC_O_HDRC_RXCOUNT));
614 musb_h_flush_rxfifo(ep, MGC_M_RXCSR_CLRDATATOG);
617 /* target addr and (for multipoint) hub addr/port */
618 if (musb->bIsMultipoint) {
619 musb_writeb(ep->target_regs, MGC_O_HDRC_RXFUNCADDR,
621 musb_writeb(ep->target_regs, MGC_O_HDRC_RXHUBADDR,
623 musb_writeb(ep->target_regs, MGC_O_HDRC_RXHUBPORT,
626 musb_writeb(musb->pRegs, MGC_O_HDRC_FADDR, qh->addr_reg);
628 /* protocol/endpoint, interval/NAKlimit, i/o size */
629 musb_writeb(ep->regs, MGC_O_HDRC_RXTYPE, qh->type_reg);
630 musb_writeb(ep->regs, MGC_O_HDRC_RXINTERVAL, qh->intv_reg);
631 /* NOTE: bulk combining rewrites high bits of maxpacket */
632 musb_writew(ep->regs, MGC_O_HDRC_RXMAXP, qh->maxpacket);
639 * Program an HDRC endpoint as per the given URB
640 * Context: irqs blocked, controller lock held
642 #define MGC_M_TXCSR_ISO 0 /* FIXME */
643 static void musb_ep_program(struct musb *pThis, u8 bEnd,
644 struct urb *pUrb, unsigned int is_out,
645 u8 * pBuffer, u32 dwLength)
647 #ifndef CONFIG_USB_INVENTRA_FIFO
648 struct dma_controller *pDmaController;
649 struct dma_channel *pDmaChannel;
652 void __iomem *pBase = pThis->pRegs;
653 struct musb_hw_ep *pEnd = pThis->aLocalEnd + bEnd;
657 if (!is_out || pEnd->bIsSharedFifo)
662 wPacketSize = qh->maxpacket;
664 DBG(3, "%s hw%d urb %p spd%d dev%d ep%d%s "
665 "h_addr%02x h_port%02x bytes %d\n",
666 is_out ? "-->" : "<--",
667 bEnd, pUrb, pUrb->dev->speed,
668 qh->addr_reg, qh->epnum, is_out ? "out" : "in",
669 qh->h_addr_reg, qh->h_port_reg,
672 MGC_SelectEnd(pBase, bEnd);
674 #ifndef CONFIG_USB_INVENTRA_FIFO
675 pDmaChannel = is_out ? pEnd->tx_channel : pEnd->rx_channel;
676 pDmaController = pThis->pDmaController;
678 /* candidate for DMA */
679 if (is_dma_capable() && bEnd && pDmaController) {
681 if (bDmaOk && !pDmaChannel) {
682 pDmaChannel = pDmaController->channel_alloc(
683 pDmaController, pEnd, is_out);
685 pEnd->tx_channel = pDmaChannel;
687 pEnd->rx_channel = pDmaChannel;
691 #endif /* PIO isn't the only option */
693 /* make sure we clear DMAEnab, autoSet bits from previous run */
695 /* OUT/transmit/EP0 or IN/receive? */
701 wCsr = MGC_ReadCsr16(pBase, MGC_O_HDRC_TXCSR, bEnd);
703 /* disable interrupt in case we flush */
704 wIntrTxE = musb_readw(pBase, MGC_O_HDRC_INTRTXE);
705 musb_writew(pBase, MGC_O_HDRC_INTRTXE, wIntrTxE & ~(1 << bEnd));
707 /* general endpoint setup */
711 /* ASSERT: TXCSR_DMAENAB was already cleared */
713 /* flush all old state, set default */
714 if (csr & MGC_M_TXCSR_FIFONOTEMPTY)
715 csr |= MGC_M_TXCSR_FLUSHFIFO;
716 csr &= ~(MGC_M_TXCSR_H_NAKTIMEOUT
717 | MGC_M_TXCSR_DMAMODE
718 | MGC_M_TXCSR_FRCDATATOG
720 | MGC_M_TXCSR_H_RXSTALL
721 | MGC_M_TXCSR_H_ERROR
722 | MGC_M_TXCSR_FIFONOTEMPTY
723 | MGC_M_TXCSR_TXPKTRDY
725 csr |= MGC_M_TXCSR_MODE;
727 if (qh->type == USB_ENDPOINT_XFER_ISOC)
728 csr |= MGC_M_TXCSR_ISO;
729 else if (usb_gettoggle(pUrb->dev,
731 csr |= MGC_M_TXCSR_H_WR_DATATOGGLE
732 | MGC_M_TXCSR_H_DATATOGGLE;
734 csr |= MGC_M_TXCSR_CLRDATATOG;
736 /* twice in case of double packet buffering */
737 MGC_WriteCsr16(pBase, MGC_O_HDRC_TXCSR, bEnd,
739 /* REVISIT may need to clear FLUSHFIFO ... */
740 MGC_WriteCsr16(pBase, MGC_O_HDRC_TXCSR, bEnd,
742 wCsr = MGC_ReadCsr16(pBase, MGC_O_HDRC_TXCSR,
745 /* endpoint 0: just flush */
746 MGC_WriteCsr16(pBase, MGC_O_HDRC_CSR0, bEnd,
747 wCsr | MGC_M_CSR0_FLUSHFIFO);
748 MGC_WriteCsr16(pBase, MGC_O_HDRC_CSR0, bEnd,
749 wCsr | MGC_M_CSR0_FLUSHFIFO);
752 /* target addr and (for multipoint) hub addr/port */
753 if (pThis->bIsMultipoint) {
755 MGC_BUSCTL_OFFSET(bEnd, MGC_O_HDRC_TXFUNCADDR),
758 MGC_BUSCTL_OFFSET(bEnd, MGC_O_HDRC_TXHUBADDR),
761 MGC_BUSCTL_OFFSET(bEnd, MGC_O_HDRC_TXHUBPORT),
763 /* FIXME if !bEnd, do the same for RX ... */
765 musb_writeb(pBase, MGC_O_HDRC_FADDR, qh->addr_reg);
767 /* protocol/endpoint/interval/NAKlimit */
769 MGC_WriteCsr8(pBase, MGC_O_HDRC_TXTYPE, bEnd,
771 if (can_bulk_split(pThis, qh->type))
772 MGC_WriteCsr16(pBase, MGC_O_HDRC_TXMAXP, bEnd,
774 | ((pEnd->wMaxPacketSizeTx /
775 wPacketSize) - 1) << 11);
777 MGC_WriteCsr16(pBase, MGC_O_HDRC_TXMAXP, bEnd,
779 MGC_WriteCsr8(pBase, MGC_O_HDRC_TXINTERVAL, bEnd,
782 MGC_WriteCsr8(pBase, MGC_O_HDRC_NAKLIMIT0, 0,
784 if (pThis->bIsMultipoint)
785 MGC_WriteCsr8(pBase, MGC_O_HDRC_TYPE0, 0,
789 if (can_bulk_split(pThis, qh->type))
790 wLoadCount = min((u32) pEnd->wMaxPacketSizeTx,
793 wLoadCount = min((u32) wPacketSize, dwLength);
795 #ifdef CONFIG_USB_INVENTRA_DMA
796 if (bDmaOk && pDmaChannel) {
798 /* clear previous state */
799 wCsr = MGC_ReadCsr16(pBase, MGC_O_HDRC_TXCSR, bEnd);
800 wCsr &= ~(MGC_M_TXCSR_AUTOSET
801 | MGC_M_TXCSR_DMAMODE
802 | MGC_M_TXCSR_DMAENAB);
803 wCsr |= MGC_M_TXCSR_MODE;
804 MGC_WriteCsr16(pBase, MGC_O_HDRC_TXCSR, bEnd,
805 wCsr | MGC_M_TXCSR_MODE);
807 qh->segsize = min(dwLength, pDmaChannel->dwMaxLength);
809 if (qh->segsize <= wPacketSize)
810 pDmaChannel->bDesiredMode = 0;
812 pDmaChannel->bDesiredMode = 1;
815 if (pDmaChannel->bDesiredMode == 0) {
816 wCsr &= ~(MGC_M_TXCSR_AUTOSET
817 | MGC_M_TXCSR_DMAMODE);
818 wCsr |= (MGC_M_TXCSR_DMAENAB);
819 // against programming guide
821 wCsr |= (MGC_M_TXCSR_AUTOSET
822 | MGC_M_TXCSR_DMAENAB
823 | MGC_M_TXCSR_DMAMODE);
825 MGC_WriteCsr16(pBase, MGC_O_HDRC_TXCSR, bEnd, wCsr);
827 bDmaOk = pDmaController->channel_program(
828 pDmaChannel, wPacketSize,
829 pDmaChannel->bDesiredMode,
835 pDmaController->channel_release(pDmaChannel);
836 pDmaChannel = pEnd->pDmaChannel = NULL;
839 #elif defined(CONFIG_USB_TI_CPPI_DMA)
841 /* candidate for DMA */
842 if (bDmaOk && pDmaChannel) {
844 /* program endpoint CSRs first, then setup DMA.
845 * assume CPPI setup succeeds.
846 * defer enabling dma.
848 wCsr = MGC_ReadCsr16(pBase, MGC_O_HDRC_TXCSR, bEnd);
849 wCsr &= ~(MGC_M_TXCSR_AUTOSET
850 | MGC_M_TXCSR_DMAMODE
851 | MGC_M_TXCSR_DMAENAB);
852 wCsr |= MGC_M_TXCSR_MODE;
853 MGC_WriteCsr16(pBase, MGC_O_HDRC_TXCSR, bEnd,
854 wCsr | MGC_M_TXCSR_MODE);
856 pDmaChannel->dwActualLength = 0L;
857 qh->segsize = dwLength;
859 /* TX uses "rndis" mode automatically, but needs help
860 * to identify the zero-length-final-packet case.
862 bDmaOk = pDmaController->channel_program(
863 pDmaChannel, wPacketSize,
864 (pUrb->transfer_flags
872 pDmaController->channel_release(pDmaChannel);
873 pDmaChannel = pEnd->tx_channel = NULL;
875 /* REVISIT there's an error path here that
876 * needs handling: can't do dma, but
877 * there's no pio buffer address...
883 /* ASSERT: TXCSR_DMAENAB was already cleared */
885 /* PIO to load FIFO */
886 qh->segsize = wLoadCount;
887 musb_write_fifo(pEnd, wLoadCount, pBuffer);
888 wCsr = MGC_ReadCsr16(pBase, MGC_O_HDRC_TXCSR, bEnd);
889 wCsr &= ~(MGC_M_TXCSR_DMAENAB
890 | MGC_M_TXCSR_DMAMODE
891 | MGC_M_TXCSR_AUTOSET);
893 wCsr |= MGC_M_TXCSR_MODE;
896 MGC_WriteCsr16(pBase, MGC_O_HDRC_TXCSR,
901 /* re-enable interrupt */
902 musb_writew(pBase, MGC_O_HDRC_INTRTXE, wIntrTxE);
908 if (pEnd->rx_reinit) {
909 musb_rx_reinit(pThis, qh, pEnd);
911 /* init new state: toggle and NYET, maybe DMA later */
912 if (usb_gettoggle(pUrb->dev, qh->epnum, 0))
913 csr = MGC_M_RXCSR_H_WR_DATATOGGLE
914 | MGC_M_RXCSR_H_DATATOGGLE;
917 if (qh->type == USB_ENDPOINT_XFER_INT)
918 csr |= MGC_M_RXCSR_DISNYET;
921 csr = musb_readw(pEnd->regs, MGC_O_HDRC_RXCSR);
923 if (csr & (MGC_M_RXCSR_RXPKTRDY
924 | MGC_M_RXCSR_DMAENAB
925 | MGC_M_RXCSR_H_REQPKT))
926 ERR("broken !rx_reinit, ep%d csr %04x\n",
927 pEnd->bLocalEnd, csr);
929 /* scrub any stale state, leaving toggle alone */
930 csr &= MGC_M_RXCSR_DISNYET;
933 /* kick things off */
934 #ifdef CONFIG_USB_TI_CPPI_DMA
935 /* candidate for DMA */
937 pDmaChannel->dwActualLength = 0L;
938 qh->segsize = dwLength;
940 /* AUTOREQ is in a DMA register */
941 musb_writew(pEnd->regs, MGC_O_HDRC_RXCSR, csr);
942 csr = musb_readw(pEnd->regs,
945 /* unless caller treats short rx transfers as
946 * errors, we dare not queue multiple transfers.
948 bDmaOk = pDmaController->channel_program(
949 pDmaChannel, wPacketSize,
950 !(pUrb->transfer_flags
955 pDmaController->channel_release(
957 pDmaChannel = pEnd->rx_channel = NULL;
959 csr |= MGC_M_RXCSR_DMAENAB;
962 csr |= MGC_M_RXCSR_H_REQPKT;
963 DBG(7, "RXCSR%d := %04x\n", bEnd, csr);
964 musb_writew(pEnd->regs, MGC_O_HDRC_RXCSR, csr);
965 csr = musb_readw(pEnd->regs, MGC_O_HDRC_RXCSR);
971 * Service the default endpoint (ep0) as host.
972 * return TRUE if more packets are required for this transaction
974 static u8 musb_h_ep0_continue(struct musb *pThis,
975 u16 wCount, struct urb *pUrb)
978 u8 *pFifoDest = NULL;
980 struct musb_hw_ep *pEnd = pThis->control_ep;
981 struct musb_qh *qh = pEnd->in_qh;
982 struct usb_ctrlrequest *pRequest;
984 pRequest = (struct usb_ctrlrequest *) pUrb->setup_packet;
985 if (MGC_END0_IN == pThis->bEnd0Stage) {
986 /* we are receiving from peripheral */
987 pFifoDest = pUrb->transfer_buffer + pUrb->actual_length;
988 wFifoCount = min(wCount, ((u16) (pUrb->transfer_buffer_length
989 - pUrb->actual_length)));
990 if (wFifoCount < wCount)
991 pUrb->status = -EOVERFLOW;
993 musb_read_fifo(pEnd, wFifoCount, pFifoDest);
995 pUrb->actual_length += wFifoCount;
996 if (wCount < qh->maxpacket) {
997 /* always terminate on short read; it's
998 * rarely reported as an error.
1000 if ((pUrb->transfer_flags & URB_SHORT_NOT_OK)
1001 && (pUrb->actual_length <
1002 pUrb->transfer_buffer_length))
1003 pUrb->status = -EREMOTEIO;
1004 } else if (pUrb->actual_length <
1005 pUrb->transfer_buffer_length)
1009 DBG(3, "%s hw%d urb %p spd%d dev%d ep%d%s "
1010 "hub%d port%d%s bytes %d\n",
1011 is_out ? "-->" : "<--",
1012 bEnd, pUrb, pUrb->dev->speed,
1013 bAddress, qh->epnum, is_out ? "out" : "in",
1014 bHubAddr, bHubPort + 1,
1015 bIsMulti ? " multi" : "",
1018 if ((MGC_END0_START == pThis->bEnd0Stage)
1019 && (pRequest->bRequestType & USB_DIR_IN)) {
1020 /* this means we just did setup; switch to IN */
1021 DBG(4, "start IN-DATA\n");
1022 pThis->bEnd0Stage = MGC_END0_IN;
1025 } else if (pRequest->wLength
1026 && (MGC_END0_START == pThis->bEnd0Stage)) {
1027 pThis->bEnd0Stage = MGC_END0_OUT;
1028 pFifoDest = (u8 *) (pUrb->transfer_buffer
1029 + pUrb->actual_length);
1030 wFifoCount = min(qh->maxpacket, ((u16)
1031 (pUrb->transfer_buffer_length
1032 - pUrb->actual_length)));
1033 DBG(3, "Sending %d bytes to %p\n",
1034 wFifoCount, pFifoDest);
1035 musb_write_fifo(pEnd, wFifoCount, pFifoDest);
1037 qh->segsize = wFifoCount;
1038 pUrb->actual_length += wFifoCount;
1039 if (pUrb->actual_length
1040 < pUrb->transfer_buffer_length) {
1050 * Handle default endpoint interrupt as host. Only called in IRQ time
1051 * from the LinuxIsr() interrupt service routine.
1053 * called with controller irqlocked
1055 irqreturn_t musb_h_ep0_irq(struct musb *pThis)
1058 u16 wCsrVal, wCount;
1060 void __iomem *pBase = pThis->pRegs;
1061 struct musb_hw_ep *pEnd = pThis->control_ep;
1062 struct musb_qh *qh = pEnd->in_qh;
1063 u8 bComplete = FALSE;
1064 irqreturn_t retval = IRQ_NONE;
1066 /* ep0 only has one queue, "in" */
1067 pUrb = next_urb(qh);
1069 MGC_SelectEnd(pBase, 0);
1070 wCsrVal = MGC_ReadCsr16(pBase, MGC_O_HDRC_CSR0, 0);
1071 wCount = MGC_ReadCsr8(pBase, MGC_O_HDRC_COUNT0, 0);
1073 DBG(4, "<== csr0 %04x, qh %p, count %d, urb %p, stage %d\n",
1074 wCsrVal, qh, wCount, pUrb, pThis->bEnd0Stage);
1076 /* if we just did status stage, we are done */
1077 if (MGC_END0_STATUS == pThis->bEnd0Stage) {
1078 retval = IRQ_HANDLED;
1082 /* prepare status */
1083 if (wCsrVal & MGC_M_CSR0_H_RXSTALL) {
1084 DBG(6, "STALLING ENDPOINT\n");
1087 } else if (wCsrVal & MGC_M_CSR0_H_ERROR) {
1088 DBG(2, "no response, csr0 %04x\n", wCsrVal);
1091 } else if (wCsrVal & MGC_M_CSR0_H_NAKTIMEOUT) {
1092 DBG(2, "control NAK timeout\n");
1094 /* NOTE: this code path would be a good place to PAUSE a
1095 * control transfer, if another one is queued, so that
1096 * ep0 is more likely to stay busy.
1098 * if (qh->ring.next != &musb->control), then
1099 * we have a candidate... NAKing is *NOT* an error
1101 MGC_WriteCsr16(pBase, MGC_O_HDRC_CSR0, 0, 0);
1102 retval = IRQ_HANDLED;
1106 DBG(6, "aborting\n");
1107 retval = IRQ_HANDLED;
1109 pUrb->status = status;
1112 /* use the proper sequence to abort the transfer */
1113 if (wCsrVal & MGC_M_CSR0_H_REQPKT) {
1114 wCsrVal &= ~MGC_M_CSR0_H_REQPKT;
1115 MGC_WriteCsr16(pBase, MGC_O_HDRC_CSR0, 0, wCsrVal);
1116 wCsrVal &= ~MGC_M_CSR0_H_NAKTIMEOUT;
1117 MGC_WriteCsr16(pBase, MGC_O_HDRC_CSR0, 0, wCsrVal);
1119 wCsrVal |= MGC_M_CSR0_FLUSHFIFO;
1120 MGC_WriteCsr16(pBase, MGC_O_HDRC_CSR0, 0, wCsrVal);
1121 MGC_WriteCsr16(pBase, MGC_O_HDRC_CSR0, 0, wCsrVal);
1122 wCsrVal &= ~MGC_M_CSR0_H_NAKTIMEOUT;
1123 MGC_WriteCsr16(pBase, MGC_O_HDRC_CSR0, 0, wCsrVal);
1126 MGC_WriteCsr8(pBase, MGC_O_HDRC_NAKLIMIT0, 0, 0);
1129 MGC_WriteCsr16(pBase, MGC_O_HDRC_CSR0, 0, 0);
1132 if (unlikely(!pUrb)) {
1133 /* stop endpoint since we have no place for its data, this
1134 * SHOULD NEVER HAPPEN! */
1135 ERR("no URB for end 0\n");
1137 MGC_WriteCsr16(pBase, MGC_O_HDRC_CSR0, 0, MGC_M_CSR0_FLUSHFIFO);
1138 MGC_WriteCsr16(pBase, MGC_O_HDRC_CSR0, 0, MGC_M_CSR0_FLUSHFIFO);
1139 MGC_WriteCsr16(pBase, MGC_O_HDRC_CSR0, 0, 0);
1145 /* call common logic and prepare response */
1146 if (musb_h_ep0_continue(pThis, wCount, pUrb)) {
1147 /* more packets required */
1148 wCsrVal = (MGC_END0_IN == pThis->bEnd0Stage)
1149 ? MGC_M_CSR0_H_REQPKT : MGC_M_CSR0_TXPKTRDY;
1151 /* data transfer complete; perform status phase */
1152 wCsrVal = MGC_M_CSR0_H_STATUSPKT
1153 | (usb_pipeout(pUrb->pipe)
1154 ? MGC_M_CSR0_H_REQPKT
1155 : MGC_M_CSR0_TXPKTRDY);
1156 /* flag status stage */
1157 pThis->bEnd0Stage = MGC_END0_STATUS;
1159 DBG(5, "ep0 STATUS, csr %04x\n", wCsrVal);
1162 MGC_WriteCsr16(pBase, MGC_O_HDRC_CSR0, 0, wCsrVal);
1163 retval = IRQ_HANDLED;
1166 /* call completion handler if done */
1168 musb_advance_schedule(pThis, pUrb, pEnd, 1);
1174 #ifdef CONFIG_USB_INVENTRA_DMA
1176 /* Host side TX (OUT) using Mentor DMA works as follows:
1178 - if queue was empty, Program Endpoint
1179 - ... which starts DMA to fifo in mode 1 or 0
1181 DMA Isr (transfer complete) -> TxAvail()
1182 - Stop DMA (~DmaEnab) (<--- Alert ... currently happens
1183 only in musb_cleanup_urb)
1184 - TxPktRdy has to be set in mode 0 or for
1185 short packets in mode 1.
1190 /* Service a Tx-Available or dma completion irq for the endpoint */
1191 void musb_host_tx(struct musb *pThis, u8 bEnd)
1199 struct musb_hw_ep *pEnd = pThis->aLocalEnd + bEnd;
1200 struct musb_qh *qh = pEnd->out_qh;
1202 void __iomem *pBase = pThis->pRegs;
1203 struct dma_channel *dma;
1205 pUrb = next_urb(qh);
1207 MGC_SelectEnd(pBase, bEnd);
1208 wTxCsrVal = MGC_ReadCsr16(pBase, MGC_O_HDRC_TXCSR, bEnd);
1210 /* with CPPI, DMA sometimes triggers "extra" irqs */
1212 DBG(4, "extra TX%d ready, csr %04x\n", bEnd, wTxCsrVal);
1217 dma = is_dma_capable() ? pEnd->tx_channel : NULL;
1218 DBG(4, "OUT/TX%d end, csr %04x%s\n", bEnd, wTxCsrVal,
1219 dma ? ", dma" : "");
1221 /* check for errors */
1222 if (wTxCsrVal & MGC_M_TXCSR_H_RXSTALL) {
1223 /* dma was disabled, fifo flushed */
1224 DBG(3, "TX end %d stall\n", bEnd);
1226 /* stall; record URB status */
1229 } else if (wTxCsrVal & MGC_M_TXCSR_H_ERROR) {
1230 /* (NON-ISO) dma was disabled, fifo flushed */
1231 DBG(3, "TX 3strikes on ep=%d\n", bEnd);
1233 status = -ETIMEDOUT;
1235 } else if (wTxCsrVal & MGC_M_TXCSR_H_NAKTIMEOUT) {
1236 DBG(6, "TX end=%d device not responding\n", bEnd);
1238 /* NOTE: this code path would be a good place to PAUSE a
1239 * transfer, if there's some other (nonperiodic) tx urb
1240 * that could use this fifo. (dma complicates it...)
1242 * if (bulk && qh->ring.next != &musb->out_bulk), then
1243 * we have a candidate... NAKing is *NOT* an error
1245 MGC_SelectEnd(pBase, bEnd);
1246 MGC_WriteCsr16(pBase, MGC_O_HDRC_CSR0, 0,
1247 MGC_M_TXCSR_H_WZC_BITS
1248 | MGC_M_TXCSR_TXPKTRDY);
1253 if (dma_channel_status(dma) == MGC_DMA_STATUS_BUSY) {
1254 dma->bStatus = MGC_DMA_STATUS_CORE_ABORT;
1255 (void) pThis->pDmaController->channel_abort(dma);
1258 /* do the proper sequence to abort the transfer in the
1259 * usb core; the dma engine should already be stopped.
1262 if (wTxCsrVal & MGC_M_TXCSR_FIFONOTEMPTY)
1263 wTxCsrVal |= MGC_M_TXCSR_FLUSHFIFO;
1264 wTxCsrVal &= ~(MGC_M_TXCSR_FIFONOTEMPTY
1265 | MGC_M_TXCSR_AUTOSET
1266 | MGC_M_TXCSR_DMAENAB
1267 | MGC_M_TXCSR_H_ERROR
1268 | MGC_M_TXCSR_H_RXSTALL
1269 | MGC_M_TXCSR_H_NAKTIMEOUT
1272 MGC_SelectEnd(pBase, bEnd);
1273 MGC_WriteCsr16(pBase, MGC_O_HDRC_TXCSR, bEnd, wTxCsrVal);
1274 /* REVISIT may need to clear FLUSHFIFO ... */
1275 MGC_WriteCsr16(pBase, MGC_O_HDRC_TXCSR, bEnd, wTxCsrVal);
1276 MGC_WriteCsr8(pBase, MGC_O_HDRC_TXINTERVAL, bEnd, 0);
1281 /* second cppi case */
1282 if (dma_channel_status(dma) == MGC_DMA_STATUS_BUSY) {
1283 DBG(4, "extra TX%d ready, csr %04x\n", bEnd, wTxCsrVal);
1288 /* REVISIT this looks wrong... */
1289 if (!status || dma || usb_pipeisoc(nPipe)) {
1291 #ifdef CONFIG_USB_INVENTRA_DMA
1292 /* mode 0 or last short packet)
1293 * REVISIT how about ZLP?
1295 if ((dma->bDesiredMode == 0)
1296 || (dma->dwActualLength
1297 & (qh->maxpacket - 1))) {
1298 /* Send out the packet first ... */
1299 MGC_SelectEnd(pBase, bEnd);
1300 MGC_WriteCsr16(pBase, MGC_O_HDRC_TXCSR, bEnd,
1301 MGC_M_TXCSR_TXPKTRDY);
1305 wLength = dma->dwActualLength;
1307 wLength = qh->segsize;
1308 qh->offset += wLength;
1310 if (usb_pipeisoc(nPipe)) {
1311 struct usb_iso_packet_descriptor *d;
1313 d = pUrb->iso_frame_desc + qh->iso_idx;
1314 d->actual_length = qh->segsize;
1315 if (++qh->iso_idx >= pUrb->number_of_packets) {
1319 pBuffer = pUrb->transfer_buffer + d->offset;
1320 wLength = d->length;
1325 /* see if we need to send more data, or ZLP */
1326 if (qh->segsize < qh->maxpacket)
1328 else if (qh->offset == pUrb->transfer_buffer_length
1329 && !(pUrb-> transfer_flags
1333 pBuffer = pUrb->transfer_buffer
1335 wLength = pUrb->transfer_buffer_length
1341 /* urb->status != -EINPROGRESS means request has been faulted,
1342 * so we must abort this transfer after cleanup
1344 if (pUrb->status != -EINPROGRESS) {
1347 status = pUrb->status;
1352 pUrb->status = status;
1353 pUrb->actual_length = qh->offset;
1354 musb_advance_schedule(pThis, pUrb, pEnd, USB_DIR_OUT);
1356 } else if (!(wTxCsrVal & MGC_M_TXCSR_DMAENAB)) {
1357 // WARN_ON(!pBuffer);
1359 /* REVISIT: some docs say that when pEnd->tx_double_buffered,
1360 * (and presumably, fifo is not half-full) we should write TWO
1361 * packets before updating TXCSR ... other docs disagree ...
1363 /* PIO: start next packet in this URB */
1364 wLength = min(qh->maxpacket, (u16) wLength);
1365 musb_write_fifo(pEnd, wLength, pBuffer);
1366 qh->segsize = wLength;
1368 MGC_SelectEnd(pBase, bEnd);
1369 MGC_WriteCsr16(pBase, MGC_O_HDRC_TXCSR, bEnd,
1370 MGC_M_TXCSR_H_WZC_BITS | MGC_M_TXCSR_TXPKTRDY);
1372 DBG(1, "not complete, but dma enabled?\n");
1379 #ifdef CONFIG_USB_INVENTRA_DMA
1381 /* Host side RX (IN) using Mentor DMA works as follows:
1383 - if queue was empty, ProgramEndpoint
1384 - first IN token is sent out (by setting ReqPkt)
1385 LinuxIsr -> RxReady()
1386 /\ => first packet is received
1387 | - Set in mode 0 (DmaEnab, ~ReqPkt)
1388 | -> DMA Isr (transfer complete) -> RxReady()
1389 | - Ack receive (~RxPktRdy), turn off DMA (~DmaEnab)
1390 | - if urb not complete, send next IN token (ReqPkt)
1391 | | else complete urb.
1393 ---------------------------
1395 * Nuances of mode 1:
1396 * For short packets, no ack (+RxPktRdy) is sent automatically
1397 * (even if AutoClear is ON)
1398 * For full packets, ack (~RxPktRdy) and next IN token (+ReqPkt) is sent
1399 * automatically => major problem, as collecting the next packet becomes
1400 * difficult. Hence mode 1 is not used.
1403 * All we care about at this driver level is that
1404 * (a) all URBs terminate with REQPKT cleared and fifo(s) empty;
1405 * (b) termination conditions are: short RX, or buffer full;
1406 * (c) fault modes include
1407 * - iff URB_SHORT_NOT_OK, short RX status is -EREMOTEIO.
1408 * (and that endpoint's dma queue stops immediately)
1409 * - overflow (full, PLUS more bytes in the terminal packet)
1411 * So for example, usb-storage sets URB_SHORT_NOT_OK, and would
1412 * thus be a great candidate for using mode 1 ... for all but the
1413 * last packet of one URB's transfer.
1419 * Service an RX interrupt for the given IN endpoint; docs cover bulk, iso,
1420 * and high-bandwidth IN transfer cases.
1422 void musb_host_rx(struct musb *pThis, u8 bEnd)
1425 struct musb_hw_ep *pEnd = pThis->aLocalEnd + bEnd;
1426 struct musb_qh *qh = pEnd->in_qh;
1428 void __iomem *pBase = pThis->pRegs;
1430 u16 wRxCsrVal, wVal;
1431 u8 bIsochError = FALSE;
1434 struct dma_channel *dma;
1436 MGC_SelectEnd(pBase, bEnd);
1438 pUrb = next_urb(qh);
1439 dma = is_dma_capable() ? pEnd->rx_channel : NULL;
1443 wVal = wRxCsrVal = MGC_ReadCsr16(pBase, MGC_O_HDRC_RXCSR, bEnd);
1445 if (unlikely(!pUrb)) {
1446 /* REVISIT -- THIS SHOULD NEVER HAPPEN ... but, at least
1447 * usbtest #11 (unlinks) triggers it regularly, sometimes
1448 * with fifo full. (Only with DMA??)
1450 DBG(3, "BOGUS RX%d ready, csr %04x, count %d\n", bEnd, wVal,
1451 MGC_ReadCsr16(pBase, MGC_O_HDRC_RXCOUNT, bEnd));
1452 musb_h_flush_rxfifo(pEnd, MGC_M_RXCSR_CLRDATATOG);
1458 DBG(5, "<== hw %d rxcsr %04x, urb actual %d (+dma %zd)\n",
1459 bEnd, wRxCsrVal, pUrb->actual_length,
1460 dma ? dma->dwActualLength : 0);
1462 /* check for errors, concurrent stall & unlink is not really
1464 if (wRxCsrVal & MGC_M_RXCSR_H_RXSTALL) {
1465 DBG(3, "RX end %d STALL\n", bEnd);
1467 /* stall; record URB status */
1470 } else if (wRxCsrVal & MGC_M_RXCSR_H_ERROR) {
1471 DBG(3, "end %d RX proto error\n", bEnd);
1474 MGC_WriteCsr8(pBase, MGC_O_HDRC_RXINTERVAL, bEnd, 0);
1476 } else if (wRxCsrVal & MGC_M_RXCSR_DATAERROR) {
1478 if (USB_ENDPOINT_XFER_ISOC != qh->type) {
1479 /* NOTE this code path would be a good place to PAUSE a
1480 * transfer, if there's some other (nonperiodic) rx urb
1481 * that could use this fifo. (dma complicates it...)
1483 * if (bulk && qh->ring.next != &musb->in_bulk), then
1484 * we have a candidate... NAKing is *NOT* an error
1486 DBG(6, "RX end %d NAK timeout\n", bEnd);
1487 MGC_SelectEnd(pBase, bEnd);
1488 MGC_WriteCsr16(pBase, MGC_O_HDRC_RXCSR, bEnd,
1489 MGC_M_RXCSR_H_WZC_BITS
1490 | MGC_M_RXCSR_H_REQPKT);
1494 DBG(4, "RX end %d ISO data error\n", bEnd);
1495 /* packet error reported later */
1500 /* faults abort the transfer */
1502 /* clean up dma and collect transfer count */
1503 if (dma_channel_status(dma) == MGC_DMA_STATUS_BUSY) {
1504 dma->bStatus = MGC_DMA_STATUS_CORE_ABORT;
1505 (void) pThis->pDmaController->channel_abort(dma);
1506 xfer_len = dma->dwActualLength;
1508 musb_h_flush_rxfifo(pEnd, 0);
1509 MGC_WriteCsr8(pBase, MGC_O_HDRC_RXINTERVAL, bEnd, 0);
1514 if (unlikely(dma_channel_status(dma) == MGC_DMA_STATUS_BUSY)) {
1515 /* SHOULD NEVER HAPPEN */
1516 ERR("RX%d dma busy\n", bEnd);
1520 /* thorough shutdown for now ... given more precise fault handling
1521 * and better queueing support, we might keep a DMA pipeline going
1522 * while processing this irq for earlier completions.
1525 /* FIXME this is _way_ too much in-line logic for Mentor DMA */
1527 #ifndef CONFIG_USB_INVENTRA_DMA
1528 if (wRxCsrVal & MGC_M_RXCSR_H_REQPKT) {
1529 /* REVISIT this happened for a while on some short reads...
1530 * the cleanup still needs investigation... looks bad...
1531 * and also duplicates dma cleanup code above ... plus,
1532 * shouldn't this be the "half full" double buffer case?
1534 if (dma_channel_status(dma) == MGC_DMA_STATUS_BUSY) {
1535 dma->bStatus = MGC_DMA_STATUS_CORE_ABORT;
1536 (void) pThis->pDmaController->channel_abort(dma);
1537 xfer_len = dma->dwActualLength;
1541 DBG(2, "RXCSR%d %04x, reqpkt, len %zd%s\n", bEnd, wRxCsrVal,
1542 xfer_len, dma ? ", dma" : "");
1543 wRxCsrVal &= ~MGC_M_RXCSR_H_REQPKT;
1545 MGC_SelectEnd(pBase, bEnd);
1546 MGC_WriteCsr16(pBase, MGC_O_HDRC_RXCSR, bEnd,
1547 MGC_M_RXCSR_H_WZC_BITS | wRxCsrVal);
1550 if (dma && (wRxCsrVal & MGC_M_RXCSR_DMAENAB)) {
1552 #ifdef CONFIG_USB_INVENTRA_DMA
1553 xfer_len = dma->dwActualLength;
1554 pUrb->actual_length += xfer_len;
1555 qh->offset += xfer_len;
1557 /* bDone if pUrb buffer is full or short packet is recd */
1558 bDone = (pUrb->actual_length >= pUrb->transfer_buffer_length)
1559 || (dma->dwActualLength & (qh->maxpacket - 1));
1561 wVal &= ~(MGC_M_RXCSR_DMAENAB
1562 | MGC_M_RXCSR_H_AUTOREQ
1563 | MGC_M_RXCSR_AUTOCLEAR
1564 | MGC_M_RXCSR_RXPKTRDY);
1566 MGC_WriteCsr16(pBase, MGC_O_HDRC_RXCSR, bEnd, wVal);
1567 MGC_WriteCsr16(pBase, MGC_O_HDRC_RXCSR, bEnd, wVal);
1569 /* send IN token for next packet, without AUTOREQ */
1571 wVal |= MGC_M_RXCSR_H_REQPKT;
1572 MGC_WriteCsr16(pBase, MGC_O_HDRC_RXCSR, bEnd,
1573 MGC_M_RXCSR_H_WZC_BITS | wVal);
1576 DBG(4, "ep %d dma %s, rxcsr %04x, rxcount %d\n", bEnd,
1577 bDone ? "off" : "reset",
1578 MGC_ReadCsr16(pBase, MGC_O_HDRC_RXCSR, bEnd),
1579 MGC_ReadCsr16(pBase, MGC_O_HDRC_RXCOUNT, bEnd));
1582 xfer_len = dma->dwActualLength;
1584 } else if (pUrb->status == -EINPROGRESS) {
1585 /* if no errors, be sure a packet is ready for unloading */
1586 if (unlikely(!(wRxCsrVal & MGC_M_RXCSR_RXPKTRDY))) {
1588 ERR("Rx interrupt with no errors or packet!\n");
1590 // FIXME this is another "SHOULD NEVER HAPPEN"
1593 /* do the proper sequence to abort the transfer */
1594 MGC_SelectEnd(pBase, bEnd);
1595 wVal &= ~MGC_M_RXCSR_H_REQPKT;
1596 MGC_WriteCsr16(pBase, MGC_O_HDRC_RXCSR, bEnd, wVal);
1600 /* we are expecting IN packets */
1601 #ifdef CONFIG_USB_INVENTRA_DMA
1603 struct dma_controller *c;
1607 wRxCount = MGC_ReadCsr16(pBase,
1608 MGC_O_HDRC_RXCOUNT, bEnd);
1610 DBG(2, "RX%d count %d, buffer 0x%x len %d/%d\n",
1613 + pUrb->actual_length,
1615 pUrb->transfer_buffer_length);
1617 c = pThis->pDmaController;
1619 dma->bDesiredMode = 0;
1621 /* because of the issue below, mode 1 will
1622 * only rarely behave with correct semantics.
1624 if ((pUrb->transfer_flags &
1626 && (pUrb->transfer_buffer_length -
1627 pUrb->actual_length)
1629 dma->bDesiredMode = 1;
1632 /* Disadvantage of using mode 1:
1633 * It's basically usable only for mass storage class; essentially all
1634 * other protocols also terminate transfers on short packets.
1637 * An extra IN token is sent at the end of the transfer (due to AUTOREQ)
1638 * If you try to use mode 1 for (transfer_buffer_length - 512), and try
1639 * to use the extra IN token to grab the last packet using mode 0, then
1640 * the problem is that you cannot be sure when the device will send the
1641 * last packet and RxPktRdy set. Sometimes the packet is recd too soon
1642 * such that it gets lost when RxCSR is re-set at the end of the mode 1
1643 * transfer, while sometimes it is recd just a little late so that if you
1644 * try to configure for mode 0 soon after the mode 1 transfer is
1645 * completed, you will find rxcount 0. Okay, so you might think why not
1646 * wait for an interrupt when the pkt is recd. Well, you won't get any!
1649 wVal = MGC_ReadCsr16(pBase, MGC_O_HDRC_RXCSR, bEnd);
1650 wVal &= ~MGC_M_RXCSR_H_REQPKT;
1652 if (dma->bDesiredMode == 0)
1653 wVal &= ~MGC_M_RXCSR_H_AUTOREQ;
1655 wVal |= MGC_M_RXCSR_H_AUTOREQ;
1656 wVal |= MGC_M_RXCSR_AUTOCLEAR | MGC_M_RXCSR_DMAENAB;
1658 MGC_WriteCsr16(pBase, MGC_O_HDRC_RXCSR, bEnd,
1659 MGC_M_RXCSR_H_WZC_BITS | wVal);
1661 /* REVISIT if when actual_length != 0,
1662 * transfer_buffer_length needs to be
1665 status = c->channel_program(
1669 + pUrb->actual_length,
1670 (dma->bDesiredMode == 0)
1672 : pUrb->transfer_buffer_length);
1675 c->channel_release(dma);
1676 dma = pEnd->rx_channel = NULL;
1677 /* REVISIT reset CSR */
1680 #endif /* Mentor DMA */
1683 bDone = musb_host_packet_rx(pThis, pUrb,
1685 DBG(6, "read %spacket\n", bDone ? "last " : "");
1690 pUrb->actual_length += xfer_len;
1691 qh->offset += xfer_len;
1693 if (pUrb->status == -EINPROGRESS)
1694 pUrb->status = status;
1695 musb_advance_schedule(pThis, pUrb, pEnd, USB_DIR_IN);
1699 /* schedule nodes correspond to peripheral endpoints, like an OHCI QH.
1700 * the software schedule associates multiple such nodes with a given
1701 * host side hardware endpoint + direction; scheduling may activate
1702 * that hardware endpoint.
1704 static int musb_schedule(
1712 struct musb_hw_ep *hw_ep;
1713 struct list_head *head = NULL;
1715 /* use fixed hardware for control and bulk */
1717 case USB_ENDPOINT_XFER_CONTROL:
1718 head = &musb->control;
1719 hw_ep = musb->control_ep;
1721 case USB_ENDPOINT_XFER_BULK:
1722 hw_ep = musb->bulk_ep;
1724 head = &musb->in_bulk;
1726 head = &musb->out_bulk;
1730 idle = list_empty(head);
1731 list_add_tail(&qh->ring, head);
1735 /* else, periodic transfers get muxed to other endpoints */
1737 /* FIXME this doesn't consider direction, so it can only
1738 * work for one half of the endpoint hardware, and assumes
1739 * the previous cases handled all non-shared endpoints...
1742 /* we know this qh hasn't been scheduled, so all we need to do
1743 * is choose which hardware endpoint to put it on ...
1745 * REVISIT what we really want here is a regular schedule tree
1746 * like e.g. OHCI uses, but for now musb->periodic is just an
1747 * array of the _single_ logical endpoint associated with a
1748 * given physical one (identity mapping logical->physical).
1750 * that simplistic approach makes TT scheduling a lot simpler;
1751 * there is none, and thus none of its complexity...
1756 for (nEnd = 1; nEnd < musb->bEndCount; nEnd++) {
1759 if (musb->periodic[nEnd])
1761 hw_ep = &musb->aLocalEnd[nEnd];
1762 if (hw_ep == musb->bulk_ep)
1766 diff = hw_ep->wMaxPacketSizeRx - qh->maxpacket;
1768 diff = hw_ep->wMaxPacketSizeTx - qh->maxpacket;
1770 if (wBestDiff > diff) {
1779 hw_ep = musb->aLocalEnd + nBestEnd;
1780 musb->periodic[nBestEnd] = qh;
1781 DBG(4, "qh %p periodic slot %d\n", qh, nBestEnd);
1784 qh->hep->hcpriv = qh;
1786 musb_start_urb(musb, is_in, qh);
1790 static int musb_urb_enqueue(
1791 struct usb_hcd *hcd,
1792 struct usb_host_endpoint *hep,
1796 unsigned long flags;
1797 struct musb *musb = hcd_to_musb(hcd);
1798 struct musb_qh *qh = hep->hcpriv;
1799 struct usb_endpoint_descriptor *epd = &hep->desc;
1804 /* host role must be active */
1805 if (!is_host_active(musb) || !musb->is_active)
1808 /* DMA mapping was already done, if needed, and this urb is on
1809 * hep->urb_list ... so there's little to do unless hep wasn't
1810 * yet scheduled onto a live qh.
1812 * REVISIT best to keep hep->hcpriv valid until the endpoint gets
1813 * disabled, testing for empty qh->ring and avoiding qh setup costs
1814 * except for the first urb queued after a config change.
1821 /* Allocate and initialize qh, minimizing the work done each time
1822 * hw_ep gets reprogrammed, or with irqs blocked. Then schedule it.
1824 * REVISIT consider a dedicated qh kmem_cache, so it's harder
1825 * for bugs in other kernel code to break this driver...
1827 qh = kzalloc(sizeof *qh, mem_flags);
1833 INIT_LIST_HEAD(&qh->ring);
1836 qh->maxpacket = le16_to_cpu(epd->wMaxPacketSize);
1838 /* no high bandwidth support yet */
1839 if (qh->maxpacket & ~0x7ff) {
1844 qh->epnum = epd->bEndpointAddress & USB_ENDPOINT_NUMBER_MASK;
1845 qh->type = epd->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK;
1847 /* NOTE: urb->dev->devnum is wrong during SET_ADDRESS */
1848 qh->addr_reg = (u8) usb_pipedevice(urb->pipe);
1850 /* precompute rxtype/txtype/type0 register */
1851 type_reg = (qh->type << 4) | qh->epnum;
1852 switch (urb->dev->speed) {
1856 case USB_SPEED_FULL:
1862 qh->type_reg = type_reg;
1864 /* precompute rxinterval/txinterval register */
1865 interval = min((u8)16, epd->bInterval); /* log encoding */
1867 case USB_ENDPOINT_XFER_INT:
1868 /* fullspeed uses linear encoding */
1869 if (USB_SPEED_FULL == urb->dev->speed) {
1870 interval = epd->bInterval;
1875 case USB_ENDPOINT_XFER_ISOC:
1876 /* iso always uses log encoding */
1879 /* REVISIT we actually want to use NAK limits, hinting to the
1880 * transfer scheduling logic to try some other qh, e.g. try
1883 * interval = (USB_SPEED_HIGH == pUrb->dev->speed) ? 16 : 2;
1885 * The downside of disabling this is that transfer scheduling
1886 * gets VERY unfair for nonperiodic transfers; a misbehaving
1887 * peripheral could make that hurt. Or for reads, one that's
1888 * perfectly normal: network and other drivers keep reads
1889 * posted at all times, having one pending for a week should
1890 * be perfectly safe.
1892 * The upside of disabling it is avoidng transfer scheduling
1893 * code to put this aside for while.
1897 qh->intv_reg = interval;
1899 /* precompute addressing for external hub/tt ports */
1900 if (musb->bIsMultipoint) {
1901 struct usb_device *parent = urb->dev->parent;
1903 if (parent != hcd->self.root_hub) {
1904 qh->h_addr_reg = (u8) parent->devnum;
1906 /* set up tt info if needed */
1908 qh->h_port_reg = (u8) urb->dev->ttport;
1909 qh->h_addr_reg |= 0x80;
1914 /* invariant: hep->hcpriv is null OR the qh that's already scheduled.
1915 * until we get real dma queues (with an entry for each urb/buffer),
1916 * we only have work to do in the former case.
1918 spin_lock_irqsave(&musb->Lock, flags);
1920 /* some concurrent activity submitted another urb to hep...
1921 * odd, rare, error prone, but legal.
1926 status = musb_schedule(musb, qh,
1927 epd->bEndpointAddress & USB_ENDPOINT_DIR_MASK);
1931 /* FIXME set urb->start_frame for iso/intr, it's tested in
1932 * musb_start_urb(), but otherwise only konicawc cares ...
1935 spin_unlock_irqrestore(&musb->Lock, flags);
1945 * abort a transfer that's at the head of a hardware queue.
1946 * called with controller locked, irqs blocked
1947 * that hardware queue advances to the next transfer, unless prevented
1949 static int musb_cleanup_urb(struct urb *urb, struct musb_qh *qh, int is_in)
1951 struct musb_hw_ep *ep = qh->hw_ep;
1952 unsigned hw_end = ep->bLocalEnd;
1953 void __iomem *regs = ep->musb->pRegs;
1957 MGC_SelectEnd(regs, hw_end);
1959 if (is_dma_capable()) {
1960 struct dma_channel *dma;
1962 dma = is_in ? ep->rx_channel : ep->tx_channel;
1963 status = ep->musb->pDmaController->channel_abort(dma);
1964 DBG(status ? 1 : 3, "abort %cX%d DMA for urb %p --> %d\n",
1965 is_in ? 'R' : 'T', ep->bLocalEnd, urb, status);
1966 urb->actual_length += dma->dwActualLength;
1969 /* turn off DMA requests, discard state, stop polling ... */
1971 /* giveback saves bulk toggle */
1972 csr = musb_h_flush_rxfifo(ep, 0);
1974 /* REVISIT we still get an irq; should likely clear the
1975 * endpoint's irq status here to avoid bogus irqs.
1976 * clearing that status is platform-specific...
1980 csr = MGC_ReadCsr16(regs, MGC_O_HDRC_TXCSR, hw_end);
1981 if (csr & MGC_M_TXCSR_FIFONOTEMPTY)
1982 csr |= MGC_M_TXCSR_FLUSHFIFO;
1983 csr &= ~( MGC_M_TXCSR_AUTOSET
1984 | MGC_M_TXCSR_DMAENAB
1985 | MGC_M_TXCSR_H_RXSTALL
1986 | MGC_M_TXCSR_H_NAKTIMEOUT
1987 | MGC_M_TXCSR_H_ERROR
1988 | MGC_M_TXCSR_FIFONOTEMPTY
1990 MGC_WriteCsr16(regs, MGC_O_HDRC_TXCSR, 0, csr);
1991 /* REVISIT may need to clear FLUSHFIFO ... */
1992 MGC_WriteCsr16(regs, MGC_O_HDRC_TXCSR, 0, csr);
1993 /* flush cpu writebuffer */
1994 csr = MGC_ReadCsr16(regs, MGC_O_HDRC_TXCSR, hw_end);
1997 musb_advance_schedule(ep->musb, urb, ep, is_in);
2001 static int musb_urb_dequeue(struct usb_hcd *hcd, struct urb *urb)
2003 struct musb *musb = hcd_to_musb(hcd);
2005 struct list_head *sched;
2007 unsigned long flags;
2008 int status = -ENOENT;
2010 DBG(4, "urb=%p, dev%d ep%d%s\n", urb,
2011 usb_pipedevice(urb->pipe),
2012 usb_pipeendpoint(urb->pipe),
2013 usb_pipein(urb->pipe) ? "in" : "out");
2015 spin_lock_irqsave(&musb->Lock, flags);
2017 /* make sure the urb is still queued and not completed */
2018 spin_lock(&urb->lock);
2021 struct usb_host_endpoint *hep;
2024 list_for_each_entry(tmp, &hep->urb_list, urb_list) {
2031 spin_unlock(&urb->lock);
2035 /* Any URB not actively programmed into endpoint hardware can be
2036 * immediately given back. Such an URB must be at the head of its
2037 * endpoint queue, unless someday we get real DMA queues. And even
2038 * then, it might not be known to the hardware...
2040 * Otherwise abort current transfer, pending dma, etc.; urb->status
2041 * has already been updated. This is a synchronous abort; it'd be
2042 * OK to hold off until after some IRQ, though.
2044 if (urb->urb_list.prev != &qh->hep->urb_list)
2045 status = -EINPROGRESS;
2048 case USB_ENDPOINT_XFER_CONTROL:
2049 sched = &musb->control;
2051 case USB_ENDPOINT_XFER_BULK:
2052 if (usb_pipein(urb->pipe))
2053 sched = &musb->in_bulk;
2055 sched = &musb->out_bulk;
2058 /* REVISIT when we get a schedule tree, periodic
2059 * transfers won't always be at the head of a
2060 * singleton queue...
2067 /* NOTE: qh is invalid unless !list_empty(&hep->urb_list) */
2068 if (status < 0 || (sched && qh != first_qh(sched))) {
2069 status = -EINPROGRESS;
2070 musb_giveback(qh, urb, 0);
2072 status = musb_cleanup_urb(urb, qh, urb->pipe & USB_DIR_IN);
2074 spin_unlock_irqrestore(&musb->Lock, flags);
2078 /* disable an endpoint */
2080 musb_h_disable(struct usb_hcd *hcd, struct usb_host_endpoint *hep)
2082 u8 epnum = hep->desc.bEndpointAddress;
2083 unsigned long flags;
2084 struct musb *musb = hcd_to_musb(hcd);
2085 u8 is_in = epnum & USB_DIR_IN;
2086 struct musb_qh *qh = hep->hcpriv;
2087 struct urb *urb, *tmp;
2088 struct list_head *sched;
2093 spin_lock_irqsave(&musb->Lock, flags);
2096 case USB_ENDPOINT_XFER_CONTROL:
2097 sched = &musb->control;
2099 case USB_ENDPOINT_XFER_BULK:
2101 sched = &musb->in_bulk;
2103 sched = &musb->out_bulk;
2106 /* REVISIT when we get a schedule tree, periodic transfers
2107 * won't always be at the head of a singleton queue...
2113 /* NOTE: qh is invalid unless !list_empty(&hep->urb_list) */
2115 /* kick first urb off the hardware, if needed */
2117 if (!sched || qh == first_qh(sched)) {
2120 /* make software (then hardware) stop ASAP */
2121 spin_lock(&urb->lock);
2122 if (urb->status == -EINPROGRESS)
2123 urb->status = -ESHUTDOWN;
2124 spin_unlock(&urb->lock);
2127 musb_cleanup_urb(urb, qh, urb->pipe & USB_DIR_IN);
2131 /* then just nuke all the others */
2132 list_for_each_entry_safe_from(urb, tmp, &hep->urb_list, urb_list)
2133 musb_giveback(qh, urb, -ESHUTDOWN);
2135 spin_unlock_irqrestore(&musb->Lock, flags);
2138 static int musb_h_get_frame_number(struct usb_hcd *hcd)
2140 struct musb *musb = hcd_to_musb(hcd);
2142 return musb_readw(musb->pRegs, MGC_O_HDRC_FRAME);
2145 static int musb_h_start(struct usb_hcd *hcd)
2147 /* NOTE: musb_start() is called when the hub driver turns
2148 * on port power, or when (OTG) peripheral starts.
2150 hcd->state = HC_STATE_RUNNING;
2154 static void musb_h_stop(struct usb_hcd *hcd)
2156 musb_stop(hcd_to_musb(hcd));
2157 hcd->state = HC_STATE_HALT;
2160 const struct hc_driver musb_hc_driver = {
2161 .description = "musb-hcd",
2162 .product_desc = "MUSB HDRC host driver",
2163 .hcd_priv_size = sizeof (struct musb),
2164 .flags = HCD_USB2 | HCD_MEMORY,
2166 /* not using irq handler or reset hooks from usbcore, since
2167 * those must be shared with peripheral code for OTG configs
2170 .start = musb_h_start,
2171 .stop = musb_h_stop,
2173 .get_frame_number = musb_h_get_frame_number,
2175 .urb_enqueue = musb_urb_enqueue,
2176 .urb_dequeue = musb_urb_dequeue,
2177 .endpoint_disable = musb_h_disable,
2179 .hub_status_data = musb_hub_status_data,
2180 .hub_control = musb_hub_control,
2181 // .bus_suspend = musb_bus_suspend,
2182 // .bus_resume = musb_bus_resume,
2183 // .start_port_reset = NULL,
2184 // .hub_irq_enable = NULL,