1 /******************************************************************
2 * Copyright 2005 Mentor Graphics Corporation
3 * Copyright (C) 2005-2006 by Texas Instruments
4 * Copyright (C) 2006 by Nokia Corporation
6 * This file is part of the Inventra Controller Driver for Linux.
8 * The Inventra Controller Driver for Linux is free software; you
9 * can redistribute it and/or modify it under the terms of the GNU
10 * General Public License version 2 as published by the Free Software
13 * The Inventra Controller Driver for Linux is distributed in
14 * the hope that it will be useful, but WITHOUT ANY WARRANTY;
15 * without even the implied warranty of MERCHANTABILITY or
16 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
17 * License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with The Inventra Controller Driver for Linux ; if not,
21 * write to the Free Software Foundation, Inc., 59 Temple Place,
22 * Suite 330, Boston, MA 02111-1307 USA
24 * ANY DOWNLOAD, USE, REPRODUCTION, MODIFICATION OR DISTRIBUTION
25 * OF THIS DRIVER INDICATES YOUR COMPLETE AND UNCONDITIONAL ACCEPTANCE
26 * OF THOSE TERMS.THIS DRIVER IS PROVIDED "AS IS" AND MENTOR GRAPHICS
27 * MAKES NO WARRANTIES, EXPRESS OR IMPLIED, RELATED TO THIS DRIVER.
28 * MENTOR GRAPHICS SPECIFICALLY DISCLAIMS ALL IMPLIED WARRANTIES
29 * OF MERCHANTABILITY; FITNESS FOR A PARTICULAR PURPOSE AND
30 * NON-INFRINGEMENT. MENTOR GRAPHICS DOES NOT PROVIDE SUPPORT
31 * SERVICES OR UPDATES FOR THIS DRIVER, EVEN IF YOU ARE A MENTOR
32 * GRAPHICS SUPPORT CUSTOMER.
33 ******************************************************************/
35 #include <linux/module.h>
36 #include <linux/kernel.h>
37 #include <linux/delay.h>
38 #include <linux/sched.h>
39 #include <linux/slab.h>
40 #include <linux/errno.h>
41 #include <linux/init.h>
42 #include <linux/list.h>
45 #include "musb_host.h"
48 /* MUSB HOST status 22-mar-2006
50 * - There's still lots of partial code duplication for fault paths, so
51 * they aren't handled as consistently as they need to be.
53 * - PIO mostly behaved when last tested.
54 * + including ep0, with all usbtest cases 9, 10
55 * + usbtest 14 (ep0out) doesn't seem to run at all
56 * + double buffered OUT/TX endpoints saw stalls(!) with certain usbtest
57 * configurations, but otherwise double buffering passes basic tests.
58 * + for 2.6.N, for N > ~10, needs API changes for hcd framework.
60 * - DMA (CPPI) ... partially behaves, not currently recommended
61 * + about 1/15 the speed of typical EHCI implementations (PCI)
62 * + RX, all too often reqpkt seems to misbehave after tx
63 * + TX, no known issues (other than evident silicon issue)
65 * - DMA (Mentor/OMAP) ...has at least toggle update problems
67 * - Still no traffic scheduling code to make NAKing for bulk or control
68 * transfers unable to starve other requests; or to make efficient use
69 * of hardware with periodic transfers. (Note that network drivers
70 * commonly post bulk reads that stay pending for a long time; these
71 * would make very visible trouble.)
73 * - Not tested with HNP, but some SRP paths seem to behave.
77 * - Bulk traffic finally uses both sides of hardware ep1, freeing up an
78 * extra endpoint for periodic use enabling hub + keybd + mouse. That
79 * mostly works, except that with "usbnet" it's easy to trigger cases
80 * with "ping" where RX loses. (a) ping to davinci, even "ping -f",
81 * fine; but (b) ping _from_ davinci, even "ping -c 1", ICMP RX loses
82 * although ARP RX wins. (That test was done with a full speed link.)
87 * NOTE on endpoint usage:
89 * CONTROL transfers all go through ep0. BULK ones go through dedicated IN
90 * and OUT endpoints ... hardware is dedicated for those "async" queue(s).
92 * (Yes, bulk _could_ use more of the endpoints than that, and would even
93 * benefit from it ... one remote device may easily be NAKing while others
94 * need to perform transfers in that same direction. The same thing could
95 * be done in software though, assuming dma cooperates.)
97 * INTERUPPT and ISOCHRONOUS transfers are scheduled to the other endpoints.
98 * So far that scheduling is both dumb and optimistic: the endpoint will be
99 * "claimed" until its software queue is no longer refilled. No multiplexing
100 * of transfers between endpoints, or anything clever.
104 /*************************** Forwards ***************************/
106 static void musb_ep_program(struct musb *pThis, u8 bEnd,
107 struct urb *pUrb, unsigned int nOut,
108 u8 * pBuffer, u32 dwLength);
111 * Start transmit. Caller is responsible for locking shared resources.
112 * pThis must be locked.
114 static inline void musb_h_tx_start(struct musb_hw_ep *ep)
118 /* NOTE: no locks here; caller should lock and select EP */
120 txcsr = musb_readw(ep->regs, MGC_O_HDRC_TXCSR);
121 txcsr |= MGC_M_TXCSR_TXPKTRDY | MGC_M_TXCSR_H_WZC_BITS;
122 musb_writew(ep->regs, MGC_O_HDRC_TXCSR, txcsr);
124 txcsr = MGC_M_CSR0_H_SETUPPKT | MGC_M_CSR0_TXPKTRDY;
125 musb_writew(ep->regs, MGC_O_HDRC_CSR0, txcsr);
130 static inline void cppi_host_txdma_start(struct musb_hw_ep *ep)
134 /* NOTE: no locks here; caller should lock and select EP */
135 txcsr = musb_readw(ep->regs, MGC_O_HDRC_TXCSR);
136 txcsr |= MGC_M_TXCSR_DMAENAB | MGC_M_TXCSR_H_WZC_BITS;
137 musb_writew(ep->regs, MGC_O_HDRC_TXCSR, txcsr);
141 * Start the URB at the front of an endpoint's queue
142 * end must be claimed from the caller.
144 * Context: controller locked, irqs blocked
147 musb_start_urb(struct musb *musb, int is_in, struct musb_qh *qh)
152 void __iomem *pBase = musb->pRegs;
153 struct urb *urb = next_urb(qh);
154 struct musb_hw_ep *pEnd = qh->hw_ep;
155 unsigned nPipe = urb->pipe;
156 u8 bAddress = usb_pipedevice(nPipe);
157 int bEnd = pEnd->bLocalEnd;
159 /* initialize software qh state */
163 /* gather right source of data */
165 case USB_ENDPOINT_XFER_CONTROL:
166 /* control transfers always start with SETUP */
169 musb->bEnd0Stage = MGC_END0_START;
170 pBuffer = urb->setup_packet;
173 case USB_ENDPOINT_XFER_ISOC:
176 pBuffer = urb->transfer_buffer + urb->iso_frame_desc[0].offset;
177 dwLength = urb->iso_frame_desc[0].length;
179 default: /* bulk, interrupt */
180 pBuffer = urb->transfer_buffer;
181 dwLength = urb->transfer_buffer_length;
184 DBG(4, "qh %p urb %p dev%d ep%d%s%s, hw_ep %d, %p/%d\n",
185 qh, urb, bAddress, qh->epnum,
186 is_in ? "in" : "out",
187 ({char *s; switch (qh->type) {
188 case USB_ENDPOINT_XFER_CONTROL: s = ""; break;
189 case USB_ENDPOINT_XFER_BULK: s = "-bulk"; break;
190 case USB_ENDPOINT_XFER_ISOC: s = "-iso"; break;
191 default: s = "-intr"; break;
193 bEnd, pBuffer, dwLength);
195 /* Configure endpoint */
196 if (is_in || pEnd->bIsSharedFifo)
200 musb_ep_program(musb, bEnd, urb, !is_in, pBuffer, dwLength);
202 /* transmit may have more work: start it when it is time */
206 /* determine if the time is right for a periodic transfer */
208 case USB_ENDPOINT_XFER_ISOC:
209 case USB_ENDPOINT_XFER_INT:
210 DBG(3, "check whether there's still time for periodic Tx\n");
212 wFrame = musb_readw(pBase, MGC_O_HDRC_FRAME);
213 /* FIXME this doesn't implement that scheduling policy ...
214 * or handle framecounter wrapping
216 if ((urb->transfer_flags & URB_ISO_ASAP)
217 || (wFrame >= urb->start_frame)) {
218 /* REVISIT the SOF irq handler shouldn't duplicate
219 * this code; and we don't init urb->start_frame...
224 qh->frame = urb->start_frame;
225 /* enable SOF interrupt so we can count down */
226 DBG(1,"SOF for %d\n", bEnd);
227 #if 1 // ifndef CONFIG_ARCH_DAVINCI
228 musb_writeb(pBase, MGC_O_HDRC_INTRUSBE, 0xff);
234 DBG(4, "Start TX%d %s\n", bEnd,
235 pEnd->tx_channel ? "dma" : "pio");
237 if (!pEnd->tx_channel)
238 musb_h_tx_start(pEnd);
239 else if (is_cppi_enabled())
240 cppi_host_txdma_start(pEnd);
244 /* caller owns controller lock, irqs are blocked */
246 __musb_giveback(struct musb *musb, struct urb *urb, int status)
247 __releases(musb->Lock)
248 __acquires(musb->Lock)
250 if ((urb->transfer_flags & URB_SHORT_NOT_OK)
251 && (urb->actual_length < urb->transfer_buffer_length)
253 && usb_pipein(urb->pipe))
256 spin_lock(&urb->lock);
258 if (urb->status == -EINPROGRESS)
259 urb->status = status;
260 spin_unlock(&urb->lock);
262 DBG(({ int level; switch (urb->status) {
266 /* common/boring faults */
277 "complete %p (%d), dev%d ep%d%s, %d/%d\n",
279 usb_pipedevice(urb->pipe),
280 usb_pipeendpoint(urb->pipe),
281 usb_pipein(urb->pipe) ? "in" : "out",
282 urb->actual_length, urb->transfer_buffer_length
285 spin_unlock(&musb->Lock);
286 usb_hcd_giveback_urb(musb_to_hcd(musb), urb);
287 spin_lock(&musb->Lock);
290 /* for bulk/interrupt endpoints only */
291 static inline void musb_save_toggle(struct musb_hw_ep *ep, int is_in, struct urb *urb)
293 struct usb_device *udev = urb->dev;
295 void __iomem *hw = ep->musb->pRegs;
298 /* FIXME: the current Mentor DMA code seems to have
299 * problems getting toggle correct.
302 if (is_in || ep->bIsSharedFifo)
308 csr = MGC_ReadCsr16(hw, MGC_O_HDRC_TXCSR,
310 usb_settoggle(udev, qh->epnum, 1,
311 (csr & MGC_M_TXCSR_H_DATATOGGLE)
314 csr = MGC_ReadCsr16(hw, MGC_O_HDRC_RXCSR,
316 usb_settoggle(udev, qh->epnum, 0,
317 (csr & MGC_M_RXCSR_H_DATATOGGLE)
322 /* caller owns controller lock, irqs are blocked */
323 static struct musb_qh *
324 musb_giveback(struct musb_qh *qh, struct urb *urb, int status)
327 struct musb_hw_ep *ep = qh->hw_ep;
328 struct musb *musb = ep->musb;
329 int ready = qh->is_ready;
331 if (ep->bIsSharedFifo)
334 is_in = usb_pipein(urb->pipe);
336 /* save toggle eagerly, for paranoia */
338 case USB_ENDPOINT_XFER_BULK:
339 case USB_ENDPOINT_XFER_INT:
340 musb_save_toggle(ep, is_in, urb);
342 case USB_ENDPOINT_XFER_ISOC:
343 if (status == 0 && urb->error_count)
349 __musb_giveback(musb, urb, status);
350 qh->is_ready = ready;
352 /* reclaim resources (and bandwidth) ASAP; deschedule it, and
353 * invalidate qh as soon as list_empty(&hep->urb_list)
355 if (list_empty(&qh->hep->urb_list)) {
356 struct list_head *head;
363 /* clobber old pointers to this qh */
364 if (is_in || ep->bIsSharedFifo)
368 qh->hep->hcpriv = NULL;
372 case USB_ENDPOINT_XFER_ISOC:
373 case USB_ENDPOINT_XFER_INT:
374 /* this is where periodic bandwidth should be
375 * de-allocated if it's tracked and allocated;
376 * and where we'd update the schedule tree...
378 musb->periodic[ep->bLocalEnd] = NULL;
383 case USB_ENDPOINT_XFER_CONTROL:
384 case USB_ENDPOINT_XFER_BULK:
385 /* fifo policy for these lists, except that NAKing
386 * should rotate a qh to the end (for fairness).
388 head = qh->ring.prev;
399 * Advance this hardware endpoint's queue, completing the specified urb and
400 * advancing to either the next urb queued to that qh, or else invalidating
401 * that qh and advancing to the next qh scheduled after the current one.
403 * Context: caller owns controller lock, irqs are blocked
406 musb_advance_schedule(struct musb *pThis, struct urb *urb,
407 struct musb_hw_ep *pEnd, int is_in)
411 if (is_in || pEnd->bIsSharedFifo)
415 qh = musb_giveback(qh, urb, 0);
417 #ifdef CONFIG_USB_INVENTRA_DMA
418 /* REVISIT udelay reportedly works around issues in unmodified
419 * Mentor RTL before v1.5, where it doesn't disable the pull-up
420 * resisters in high speed mode. That causes signal reflection
421 * and errors because inter packet IDLE time vanishes.
423 * Yes, this delay makes DMA-OUT a bit slower than PIO. But
424 * without it, some devices are unusable. But there seem to be
425 * other issues too, at least on DaVinci; the delay improves
426 * some full speed cases, and being DMA-coupled is strange...
428 if (is_dma_capable() && !is_in && pEnd->tx_channel)
429 udelay(15); /* 10 usec ~= 1x 512byte packet */
432 if (qh && qh->is_ready && !list_empty(&qh->hep->urb_list)) {
433 DBG(4, "... next ep%d %cX urb %p\n",
434 pEnd->bLocalEnd, is_in ? 'R' : 'T',
436 musb_start_urb(pThis, is_in, qh);
440 static inline u16 musb_h_flush_rxfifo(struct musb_hw_ep *hw_ep, u16 csr)
442 /* we don't want fifo to fill itself again;
443 * ignore dma (various models),
444 * leave toggle alone (may not have been saved yet)
446 csr |= MGC_M_RXCSR_FLUSHFIFO | MGC_M_RXCSR_RXPKTRDY;
447 csr &= ~( MGC_M_RXCSR_H_REQPKT
448 | MGC_M_RXCSR_H_AUTOREQ
449 | MGC_M_RXCSR_AUTOCLEAR
452 /* write 2x to allow double buffering */
453 musb_writew(hw_ep->regs, MGC_O_HDRC_RXCSR, csr);
454 musb_writew(hw_ep->regs, MGC_O_HDRC_RXCSR, csr);
456 /* flush writebuffer */
457 return musb_readw(hw_ep->regs, MGC_O_HDRC_RXCSR);
461 * PIO RX for a packet (or part of it).
463 static u8 musb_host_packet_rx(struct musb *pThis, struct urb *pUrb,
464 u8 bEnd, u8 bIsochError)
472 void __iomem *pBase = pThis->pRegs;
473 struct musb_hw_ep *pEnd = pThis->aLocalEnd + bEnd;
474 struct musb_qh *qh = pEnd->in_qh;
475 int nPipe = pUrb->pipe;
476 void *buffer = pUrb->transfer_buffer;
478 // MGC_SelectEnd(pBase, bEnd);
479 wRxCount = MGC_ReadCsr16(pBase, MGC_O_HDRC_RXCOUNT, bEnd);
482 if (usb_pipeisoc(nPipe)) {
484 struct usb_iso_packet_descriptor *d;
491 d = pUrb->iso_frame_desc + qh->iso_idx;
492 pBuffer = buffer + d->offset;
494 if (wRxCount > length) {
499 DBG(2, "** OVERFLOW %d into %d\n", wRxCount, length);
503 pUrb->actual_length += length;
504 d->actual_length = length;
508 /* see if we are done */
509 bDone = (++qh->iso_idx >= pUrb->number_of_packets);
512 pBuffer = buffer + qh->offset;
513 length = pUrb->transfer_buffer_length - qh->offset;
514 if (wRxCount > length) {
515 if (pUrb->status == -EINPROGRESS)
516 pUrb->status = -EOVERFLOW;
517 DBG(2, "** OVERFLOW %d into %d\n", wRxCount, length);
521 pUrb->actual_length += length;
522 qh->offset += length;
524 /* see if we are done */
525 bDone = (pUrb->actual_length == pUrb->transfer_buffer_length)
526 || (wRxCount < qh->maxpacket)
527 || (pUrb->status != -EINPROGRESS);
529 && (pUrb->status == -EINPROGRESS)
530 && (pUrb->transfer_flags & URB_SHORT_NOT_OK)
531 && (pUrb->actual_length
532 < pUrb->transfer_buffer_length))
533 pUrb->status = -EREMOTEIO;
536 musb_read_fifo(pEnd, length, pBuffer);
538 wCsr = MGC_ReadCsr16(pBase, MGC_O_HDRC_RXCSR, bEnd);
539 wCsr |= MGC_M_RXCSR_H_WZC_BITS;
540 if (unlikely(do_flush))
541 musb_h_flush_rxfifo(pEnd, wCsr);
543 /* REVISIT this assumes AUTOCLEAR is never set */
544 wCsr &= ~(MGC_M_RXCSR_RXPKTRDY | MGC_M_RXCSR_H_REQPKT);
546 wCsr |= MGC_M_RXCSR_H_REQPKT;
547 MGC_WriteCsr16(pBase, MGC_O_HDRC_RXCSR, bEnd, wCsr);
553 /* we don't always need to reinit a given side of an endpoint...
554 * when we do, use tx/rx reinit routine and then construct a new CSR
555 * to address data toggle, NYET, and DMA or PIO.
557 * it's possible that driver bugs (especially for DMA) or aborting a
558 * transfer might have left the endpoint busier than it should be.
559 * the busy/not-empty tests are basically paranoia.
562 musb_rx_reinit(struct musb *musb, struct musb_qh *qh, struct musb_hw_ep *ep)
566 /* NOTE: we know the "rx" fifo reinit never triggers for ep0.
567 * That always uses tx_reinit since ep0 repurposes TX register
568 * offsets; the initial SETUP packet is also a kind of OUT.
571 /* if programmed for Tx, put it in RX mode */
572 if (ep->bIsSharedFifo) {
573 csr = musb_readw(ep->regs, MGC_O_HDRC_TXCSR);
574 if (csr & MGC_M_TXCSR_MODE) {
575 if (csr & MGC_M_TXCSR_FIFONOTEMPTY) {
576 /* this shouldn't happen; irq?? */
577 ERR("shared fifo not empty?\n");
578 musb_writew(ep->regs, MGC_O_HDRC_TXCSR,
579 MGC_M_TXCSR_FLUSHFIFO);
580 musb_writew(ep->regs, MGC_O_HDRC_TXCSR,
581 MGC_M_TXCSR_FRCDATATOG);
584 /* clear mode (and everything else) to enable Rx */
585 musb_writew(ep->regs, MGC_O_HDRC_TXCSR, 0);
587 /* scrub all previous state, clearing toggle */
589 csr = musb_readw(ep->regs, MGC_O_HDRC_RXCSR);
590 if (csr & MGC_M_RXCSR_RXPKTRDY)
591 WARN("rx%d, packet/%d ready?\n", ep->bLocalEnd,
592 musb_readw(ep->regs, MGC_O_HDRC_RXCOUNT));
594 musb_h_flush_rxfifo(ep, MGC_M_RXCSR_CLRDATATOG);
597 /* target addr and (for multipoint) hub addr/port */
598 if (musb->bIsMultipoint) {
599 musb_writeb(ep->target_regs, MGC_O_HDRC_RXFUNCADDR,
601 musb_writeb(ep->target_regs, MGC_O_HDRC_RXHUBADDR,
603 musb_writeb(ep->target_regs, MGC_O_HDRC_RXHUBPORT,
606 musb_writeb(musb->pRegs, MGC_O_HDRC_FADDR, qh->addr_reg);
608 /* protocol/endpoint, interval/NAKlimit, i/o size */
609 musb_writeb(ep->regs, MGC_O_HDRC_RXTYPE, qh->type_reg);
610 musb_writeb(ep->regs, MGC_O_HDRC_RXINTERVAL, qh->intv_reg);
611 /* NOTE: bulk combining rewrites high bits of maxpacket */
612 musb_writew(ep->regs, MGC_O_HDRC_RXMAXP, qh->maxpacket);
619 * Program an HDRC endpoint as per the given URB
620 * Context: irqs blocked, controller lock held
622 static void musb_ep_program(struct musb *pThis, u8 bEnd,
623 struct urb *pUrb, unsigned int is_out,
624 u8 * pBuffer, u32 dwLength)
626 struct dma_controller *pDmaController;
627 struct dma_channel *pDmaChannel;
629 void __iomem *pBase = pThis->pRegs;
630 struct musb_hw_ep *pEnd = pThis->aLocalEnd + bEnd;
634 if (!is_out || pEnd->bIsSharedFifo)
639 wPacketSize = qh->maxpacket;
641 DBG(3, "%s hw%d urb %p spd%d dev%d ep%d%s "
642 "h_addr%02x h_port%02x bytes %d\n",
643 is_out ? "-->" : "<--",
644 bEnd, pUrb, pUrb->dev->speed,
645 qh->addr_reg, qh->epnum, is_out ? "out" : "in",
646 qh->h_addr_reg, qh->h_port_reg,
649 MGC_SelectEnd(pBase, bEnd);
651 /* candidate for DMA? */
652 pDmaController = pThis->pDmaController;
653 if (is_dma_capable() && bEnd && pDmaController) {
654 pDmaChannel = is_out ? pEnd->tx_channel : pEnd->rx_channel;
656 pDmaChannel = pDmaController->channel_alloc(
657 pDmaController, pEnd, is_out);
659 pEnd->tx_channel = pDmaChannel;
661 pEnd->rx_channel = pDmaChannel;
666 /* make sure we clear DMAEnab, autoSet bits from previous run */
668 /* OUT/transmit/EP0 or IN/receive? */
674 wCsr = MGC_ReadCsr16(pBase, MGC_O_HDRC_TXCSR, bEnd);
676 /* disable interrupt in case we flush */
677 wIntrTxE = musb_readw(pBase, MGC_O_HDRC_INTRTXE);
678 musb_writew(pBase, MGC_O_HDRC_INTRTXE, wIntrTxE & ~(1 << bEnd));
680 /* general endpoint setup */
684 /* ASSERT: TXCSR_DMAENAB was already cleared */
686 /* flush all old state, set default */
687 if (csr & MGC_M_TXCSR_FIFONOTEMPTY)
688 csr |= MGC_M_TXCSR_FLUSHFIFO;
689 csr &= ~(MGC_M_TXCSR_H_NAKTIMEOUT
690 | MGC_M_TXCSR_DMAMODE
691 | MGC_M_TXCSR_FRCDATATOG
692 | MGC_M_TXCSR_H_RXSTALL
693 | MGC_M_TXCSR_H_ERROR
694 | MGC_M_TXCSR_FIFONOTEMPTY
695 | MGC_M_TXCSR_TXPKTRDY
697 csr |= MGC_M_TXCSR_MODE;
699 if (usb_gettoggle(pUrb->dev,
701 csr |= MGC_M_TXCSR_H_WR_DATATOGGLE
702 | MGC_M_TXCSR_H_DATATOGGLE;
704 csr |= MGC_M_TXCSR_CLRDATATOG;
706 /* twice in case of double packet buffering */
707 MGC_WriteCsr16(pBase, MGC_O_HDRC_TXCSR, bEnd,
709 /* REVISIT may need to clear FLUSHFIFO ... */
710 MGC_WriteCsr16(pBase, MGC_O_HDRC_TXCSR, bEnd,
712 wCsr = MGC_ReadCsr16(pBase, MGC_O_HDRC_TXCSR,
715 /* endpoint 0: just flush */
716 MGC_WriteCsr16(pBase, MGC_O_HDRC_CSR0, bEnd,
717 wCsr | MGC_M_CSR0_FLUSHFIFO);
718 MGC_WriteCsr16(pBase, MGC_O_HDRC_CSR0, bEnd,
719 wCsr | MGC_M_CSR0_FLUSHFIFO);
722 /* target addr and (for multipoint) hub addr/port */
723 if (pThis->bIsMultipoint) {
725 MGC_BUSCTL_OFFSET(bEnd, MGC_O_HDRC_TXFUNCADDR),
728 MGC_BUSCTL_OFFSET(bEnd, MGC_O_HDRC_TXHUBADDR),
731 MGC_BUSCTL_OFFSET(bEnd, MGC_O_HDRC_TXHUBPORT),
733 /* FIXME if !bEnd, do the same for RX ... */
735 musb_writeb(pBase, MGC_O_HDRC_FADDR, qh->addr_reg);
737 /* protocol/endpoint/interval/NAKlimit */
739 MGC_WriteCsr8(pBase, MGC_O_HDRC_TXTYPE, bEnd,
741 if (can_bulk_split(pThis, qh->type))
742 MGC_WriteCsr16(pBase, MGC_O_HDRC_TXMAXP, bEnd,
744 | ((pEnd->wMaxPacketSizeTx /
745 wPacketSize) - 1) << 11);
747 MGC_WriteCsr16(pBase, MGC_O_HDRC_TXMAXP, bEnd,
749 MGC_WriteCsr8(pBase, MGC_O_HDRC_TXINTERVAL, bEnd,
752 MGC_WriteCsr8(pBase, MGC_O_HDRC_NAKLIMIT0, 0,
754 if (pThis->bIsMultipoint)
755 MGC_WriteCsr8(pBase, MGC_O_HDRC_TYPE0, 0,
759 if (can_bulk_split(pThis, qh->type))
760 wLoadCount = min((u32) pEnd->wMaxPacketSizeTx,
763 wLoadCount = min((u32) wPacketSize, dwLength);
765 #ifdef CONFIG_USB_INVENTRA_DMA
768 /* clear previous state */
769 wCsr = MGC_ReadCsr16(pBase, MGC_O_HDRC_TXCSR, bEnd);
770 wCsr &= ~(MGC_M_TXCSR_AUTOSET
771 | MGC_M_TXCSR_DMAMODE
772 | MGC_M_TXCSR_DMAENAB);
773 wCsr |= MGC_M_TXCSR_MODE;
774 MGC_WriteCsr16(pBase, MGC_O_HDRC_TXCSR, bEnd,
775 wCsr | MGC_M_TXCSR_MODE);
777 qh->segsize = min(dwLength, pDmaChannel->dwMaxLength);
779 if (qh->segsize <= wPacketSize)
780 pDmaChannel->bDesiredMode = 0;
782 pDmaChannel->bDesiredMode = 1;
785 if (pDmaChannel->bDesiredMode == 0) {
786 wCsr &= ~(MGC_M_TXCSR_AUTOSET
787 | MGC_M_TXCSR_DMAMODE);
788 wCsr |= (MGC_M_TXCSR_DMAENAB);
789 // against programming guide
791 wCsr |= (MGC_M_TXCSR_AUTOSET
792 | MGC_M_TXCSR_DMAENAB
793 | MGC_M_TXCSR_DMAMODE);
795 MGC_WriteCsr16(pBase, MGC_O_HDRC_TXCSR, bEnd, wCsr);
797 bDmaOk = pDmaController->channel_program(
798 pDmaChannel, wPacketSize,
799 pDmaChannel->bDesiredMode,
805 pDmaController->channel_release(pDmaChannel);
806 pDmaChannel = pEnd->pDmaChannel = NULL;
811 /* candidate for DMA */
812 if (is_cppi_enabled() && pDmaChannel) {
814 /* program endpoint CSRs first, then setup DMA.
815 * assume CPPI setup succeeds.
816 * defer enabling dma.
818 wCsr = MGC_ReadCsr16(pBase, MGC_O_HDRC_TXCSR, bEnd);
819 wCsr &= ~(MGC_M_TXCSR_AUTOSET
820 | MGC_M_TXCSR_DMAMODE
821 | MGC_M_TXCSR_DMAENAB);
822 wCsr |= MGC_M_TXCSR_MODE;
823 MGC_WriteCsr16(pBase, MGC_O_HDRC_TXCSR, bEnd,
824 wCsr | MGC_M_TXCSR_MODE);
826 pDmaChannel->dwActualLength = 0L;
827 qh->segsize = dwLength;
829 /* TX uses "rndis" mode automatically, but needs help
830 * to identify the zero-length-final-packet case.
832 bDmaOk = pDmaController->channel_program(
833 pDmaChannel, wPacketSize,
834 (pUrb->transfer_flags
842 pDmaController->channel_release(pDmaChannel);
843 pDmaChannel = pEnd->tx_channel = NULL;
845 /* REVISIT there's an error path here that
846 * needs handling: can't do dma, but
847 * there's no pio buffer address...
853 /* ASSERT: TXCSR_DMAENAB was already cleared */
855 /* PIO to load FIFO */
856 qh->segsize = wLoadCount;
857 musb_write_fifo(pEnd, wLoadCount, pBuffer);
858 wCsr = MGC_ReadCsr16(pBase, MGC_O_HDRC_TXCSR, bEnd);
859 wCsr &= ~(MGC_M_TXCSR_DMAENAB
860 | MGC_M_TXCSR_DMAMODE
861 | MGC_M_TXCSR_AUTOSET);
863 wCsr |= MGC_M_TXCSR_MODE;
866 MGC_WriteCsr16(pBase, MGC_O_HDRC_TXCSR,
871 /* re-enable interrupt */
872 musb_writew(pBase, MGC_O_HDRC_INTRTXE, wIntrTxE);
878 if (pEnd->rx_reinit) {
879 musb_rx_reinit(pThis, qh, pEnd);
881 /* init new state: toggle and NYET, maybe DMA later */
882 if (usb_gettoggle(pUrb->dev, qh->epnum, 0))
883 csr = MGC_M_RXCSR_H_WR_DATATOGGLE
884 | MGC_M_RXCSR_H_DATATOGGLE;
887 if (qh->type == USB_ENDPOINT_XFER_INT)
888 csr |= MGC_M_RXCSR_DISNYET;
891 csr = musb_readw(pEnd->regs, MGC_O_HDRC_RXCSR);
893 if (csr & (MGC_M_RXCSR_RXPKTRDY
894 | MGC_M_RXCSR_DMAENAB
895 | MGC_M_RXCSR_H_REQPKT))
896 ERR("broken !rx_reinit, ep%d csr %04x\n",
897 pEnd->bLocalEnd, csr);
899 /* scrub any stale state, leaving toggle alone */
900 csr &= MGC_M_RXCSR_DISNYET;
903 /* kick things off */
905 if (is_cppi_enabled()) {
906 /* candidate for DMA */
908 pDmaChannel->dwActualLength = 0L;
909 qh->segsize = dwLength;
911 /* AUTOREQ is in a DMA register */
912 musb_writew(pEnd->regs, MGC_O_HDRC_RXCSR, csr);
913 csr = musb_readw(pEnd->regs,
916 /* unless caller treats short rx transfers as
917 * errors, we dare not queue multiple transfers.
919 bDmaOk = pDmaController->channel_program(
920 pDmaChannel, wPacketSize,
921 !(pUrb->transfer_flags
926 pDmaController->channel_release(
928 pDmaChannel = pEnd->rx_channel = NULL;
930 csr |= MGC_M_RXCSR_DMAENAB;
934 csr |= MGC_M_RXCSR_H_REQPKT;
935 DBG(7, "RXCSR%d := %04x\n", bEnd, csr);
936 musb_writew(pEnd->regs, MGC_O_HDRC_RXCSR, csr);
937 csr = musb_readw(pEnd->regs, MGC_O_HDRC_RXCSR);
943 * Service the default endpoint (ep0) as host.
944 * return TRUE if more packets are required for this transaction
946 static u8 musb_h_ep0_continue(struct musb *pThis,
947 u16 wCount, struct urb *pUrb)
950 u8 *pFifoDest = NULL;
952 struct musb_hw_ep *pEnd = pThis->control_ep;
953 struct musb_qh *qh = pEnd->in_qh;
954 struct usb_ctrlrequest *pRequest;
956 pRequest = (struct usb_ctrlrequest *) pUrb->setup_packet;
957 if (MGC_END0_IN == pThis->bEnd0Stage) {
958 /* we are receiving from peripheral */
959 pFifoDest = pUrb->transfer_buffer + pUrb->actual_length;
960 wFifoCount = min(wCount, ((u16) (pUrb->transfer_buffer_length
961 - pUrb->actual_length)));
962 if (wFifoCount < wCount)
963 pUrb->status = -EOVERFLOW;
965 musb_read_fifo(pEnd, wFifoCount, pFifoDest);
967 pUrb->actual_length += wFifoCount;
968 if (wCount < qh->maxpacket) {
969 /* always terminate on short read; it's
970 * rarely reported as an error.
972 if ((pUrb->transfer_flags & URB_SHORT_NOT_OK)
973 && (pUrb->actual_length <
974 pUrb->transfer_buffer_length))
975 pUrb->status = -EREMOTEIO;
976 } else if (pUrb->actual_length <
977 pUrb->transfer_buffer_length)
981 DBG(3, "%s hw%d urb %p spd%d dev%d ep%d%s "
982 "hub%d port%d%s bytes %d\n",
983 is_out ? "-->" : "<--",
984 bEnd, pUrb, pUrb->dev->speed,
985 bAddress, qh->epnum, is_out ? "out" : "in",
986 bHubAddr, bHubPort + 1,
987 bIsMulti ? " multi" : "",
990 if ((MGC_END0_START == pThis->bEnd0Stage)
991 && (pRequest->bRequestType & USB_DIR_IN)) {
992 /* this means we just did setup; switch to IN */
993 DBG(4, "start IN-DATA\n");
994 pThis->bEnd0Stage = MGC_END0_IN;
997 } else if (pRequest->wLength
998 && (MGC_END0_START == pThis->bEnd0Stage)) {
999 pThis->bEnd0Stage = MGC_END0_OUT;
1000 pFifoDest = (u8 *) (pUrb->transfer_buffer
1001 + pUrb->actual_length);
1002 wFifoCount = min(qh->maxpacket, ((u16)
1003 (pUrb->transfer_buffer_length
1004 - pUrb->actual_length)));
1005 DBG(3, "Sending %d bytes to %p\n",
1006 wFifoCount, pFifoDest);
1007 musb_write_fifo(pEnd, wFifoCount, pFifoDest);
1009 qh->segsize = wFifoCount;
1010 pUrb->actual_length += wFifoCount;
1011 if (pUrb->actual_length
1012 < pUrb->transfer_buffer_length) {
1022 * Handle default endpoint interrupt as host. Only called in IRQ time
1023 * from the LinuxIsr() interrupt service routine.
1025 * called with controller irqlocked
1027 irqreturn_t musb_h_ep0_irq(struct musb *pThis)
1030 u16 wCsrVal, wCount;
1032 void __iomem *pBase = pThis->pRegs;
1033 struct musb_hw_ep *pEnd = pThis->control_ep;
1034 struct musb_qh *qh = pEnd->in_qh;
1035 u8 bComplete = FALSE;
1036 irqreturn_t retval = IRQ_NONE;
1038 /* ep0 only has one queue, "in" */
1039 pUrb = next_urb(qh);
1041 MGC_SelectEnd(pBase, 0);
1042 wCsrVal = MGC_ReadCsr16(pBase, MGC_O_HDRC_CSR0, 0);
1043 wCount = MGC_ReadCsr8(pBase, MGC_O_HDRC_COUNT0, 0);
1045 DBG(4, "<== csr0 %04x, qh %p, count %d, urb %p, stage %d\n",
1046 wCsrVal, qh, wCount, pUrb, pThis->bEnd0Stage);
1048 /* if we just did status stage, we are done */
1049 if (MGC_END0_STATUS == pThis->bEnd0Stage) {
1050 retval = IRQ_HANDLED;
1054 /* prepare status */
1055 if (wCsrVal & MGC_M_CSR0_H_RXSTALL) {
1056 DBG(6, "STALLING ENDPOINT\n");
1059 } else if (wCsrVal & MGC_M_CSR0_H_ERROR) {
1060 DBG(2, "no response, csr0 %04x\n", wCsrVal);
1063 } else if (wCsrVal & MGC_M_CSR0_H_NAKTIMEOUT) {
1064 DBG(2, "control NAK timeout\n");
1066 /* NOTE: this code path would be a good place to PAUSE a
1067 * control transfer, if another one is queued, so that
1068 * ep0 is more likely to stay busy.
1070 * if (qh->ring.next != &musb->control), then
1071 * we have a candidate... NAKing is *NOT* an error
1073 MGC_WriteCsr16(pBase, MGC_O_HDRC_CSR0, 0, 0);
1074 retval = IRQ_HANDLED;
1078 DBG(6, "aborting\n");
1079 retval = IRQ_HANDLED;
1081 pUrb->status = status;
1084 /* use the proper sequence to abort the transfer */
1085 if (wCsrVal & MGC_M_CSR0_H_REQPKT) {
1086 wCsrVal &= ~MGC_M_CSR0_H_REQPKT;
1087 MGC_WriteCsr16(pBase, MGC_O_HDRC_CSR0, 0, wCsrVal);
1088 wCsrVal &= ~MGC_M_CSR0_H_NAKTIMEOUT;
1089 MGC_WriteCsr16(pBase, MGC_O_HDRC_CSR0, 0, wCsrVal);
1091 wCsrVal |= MGC_M_CSR0_FLUSHFIFO;
1092 MGC_WriteCsr16(pBase, MGC_O_HDRC_CSR0, 0, wCsrVal);
1093 MGC_WriteCsr16(pBase, MGC_O_HDRC_CSR0, 0, wCsrVal);
1094 wCsrVal &= ~MGC_M_CSR0_H_NAKTIMEOUT;
1095 MGC_WriteCsr16(pBase, MGC_O_HDRC_CSR0, 0, wCsrVal);
1098 MGC_WriteCsr8(pBase, MGC_O_HDRC_NAKLIMIT0, 0, 0);
1101 MGC_WriteCsr16(pBase, MGC_O_HDRC_CSR0, 0, 0);
1104 if (unlikely(!pUrb)) {
1105 /* stop endpoint since we have no place for its data, this
1106 * SHOULD NEVER HAPPEN! */
1107 ERR("no URB for end 0\n");
1109 MGC_WriteCsr16(pBase, MGC_O_HDRC_CSR0, 0, MGC_M_CSR0_FLUSHFIFO);
1110 MGC_WriteCsr16(pBase, MGC_O_HDRC_CSR0, 0, MGC_M_CSR0_FLUSHFIFO);
1111 MGC_WriteCsr16(pBase, MGC_O_HDRC_CSR0, 0, 0);
1117 /* call common logic and prepare response */
1118 if (musb_h_ep0_continue(pThis, wCount, pUrb)) {
1119 /* more packets required */
1120 wCsrVal = (MGC_END0_IN == pThis->bEnd0Stage)
1121 ? MGC_M_CSR0_H_REQPKT : MGC_M_CSR0_TXPKTRDY;
1123 /* data transfer complete; perform status phase */
1124 wCsrVal = MGC_M_CSR0_H_STATUSPKT
1125 | (usb_pipeout(pUrb->pipe)
1126 ? MGC_M_CSR0_H_REQPKT
1127 : MGC_M_CSR0_TXPKTRDY);
1128 /* flag status stage */
1129 pThis->bEnd0Stage = MGC_END0_STATUS;
1131 DBG(5, "ep0 STATUS, csr %04x\n", wCsrVal);
1134 MGC_WriteCsr16(pBase, MGC_O_HDRC_CSR0, 0, wCsrVal);
1135 retval = IRQ_HANDLED;
1138 /* call completion handler if done */
1140 musb_advance_schedule(pThis, pUrb, pEnd, 1);
1146 #ifdef CONFIG_USB_INVENTRA_DMA
1148 /* Host side TX (OUT) using Mentor DMA works as follows:
1150 - if queue was empty, Program Endpoint
1151 - ... which starts DMA to fifo in mode 1 or 0
1153 DMA Isr (transfer complete) -> TxAvail()
1154 - Stop DMA (~DmaEnab) (<--- Alert ... currently happens
1155 only in musb_cleanup_urb)
1156 - TxPktRdy has to be set in mode 0 or for
1157 short packets in mode 1.
1162 /* Service a Tx-Available or dma completion irq for the endpoint */
1163 void musb_host_tx(struct musb *pThis, u8 bEnd)
1171 struct musb_hw_ep *pEnd = pThis->aLocalEnd + bEnd;
1172 struct musb_qh *qh = pEnd->out_qh;
1174 void __iomem *pBase = pThis->pRegs;
1175 struct dma_channel *dma;
1177 pUrb = next_urb(qh);
1179 MGC_SelectEnd(pBase, bEnd);
1180 wTxCsrVal = MGC_ReadCsr16(pBase, MGC_O_HDRC_TXCSR, bEnd);
1182 /* with CPPI, DMA sometimes triggers "extra" irqs */
1184 DBG(4, "extra TX%d ready, csr %04x\n", bEnd, wTxCsrVal);
1189 dma = is_dma_capable() ? pEnd->tx_channel : NULL;
1190 DBG(4, "OUT/TX%d end, csr %04x%s\n", bEnd, wTxCsrVal,
1191 dma ? ", dma" : "");
1193 /* check for errors */
1194 if (wTxCsrVal & MGC_M_TXCSR_H_RXSTALL) {
1195 /* dma was disabled, fifo flushed */
1196 DBG(3, "TX end %d stall\n", bEnd);
1198 /* stall; record URB status */
1201 } else if (wTxCsrVal & MGC_M_TXCSR_H_ERROR) {
1202 /* (NON-ISO) dma was disabled, fifo flushed */
1203 DBG(3, "TX 3strikes on ep=%d\n", bEnd);
1205 status = -ETIMEDOUT;
1207 } else if (wTxCsrVal & MGC_M_TXCSR_H_NAKTIMEOUT) {
1208 DBG(6, "TX end=%d device not responding\n", bEnd);
1210 /* NOTE: this code path would be a good place to PAUSE a
1211 * transfer, if there's some other (nonperiodic) tx urb
1212 * that could use this fifo. (dma complicates it...)
1214 * if (bulk && qh->ring.next != &musb->out_bulk), then
1215 * we have a candidate... NAKing is *NOT* an error
1217 MGC_SelectEnd(pBase, bEnd);
1218 MGC_WriteCsr16(pBase, MGC_O_HDRC_CSR0, 0,
1219 MGC_M_TXCSR_H_WZC_BITS
1220 | MGC_M_TXCSR_TXPKTRDY);
1225 if (dma_channel_status(dma) == MGC_DMA_STATUS_BUSY) {
1226 dma->bStatus = MGC_DMA_STATUS_CORE_ABORT;
1227 (void) pThis->pDmaController->channel_abort(dma);
1230 /* do the proper sequence to abort the transfer in the
1231 * usb core; the dma engine should already be stopped.
1234 if (wTxCsrVal & MGC_M_TXCSR_FIFONOTEMPTY)
1235 wTxCsrVal |= MGC_M_TXCSR_FLUSHFIFO;
1236 wTxCsrVal &= ~(MGC_M_TXCSR_FIFONOTEMPTY
1237 | MGC_M_TXCSR_AUTOSET
1238 | MGC_M_TXCSR_DMAENAB
1239 | MGC_M_TXCSR_H_ERROR
1240 | MGC_M_TXCSR_H_RXSTALL
1241 | MGC_M_TXCSR_H_NAKTIMEOUT
1244 MGC_SelectEnd(pBase, bEnd);
1245 MGC_WriteCsr16(pBase, MGC_O_HDRC_TXCSR, bEnd, wTxCsrVal);
1246 /* REVISIT may need to clear FLUSHFIFO ... */
1247 MGC_WriteCsr16(pBase, MGC_O_HDRC_TXCSR, bEnd, wTxCsrVal);
1248 MGC_WriteCsr8(pBase, MGC_O_HDRC_TXINTERVAL, bEnd, 0);
1253 /* second cppi case */
1254 if (dma_channel_status(dma) == MGC_DMA_STATUS_BUSY) {
1255 DBG(4, "extra TX%d ready, csr %04x\n", bEnd, wTxCsrVal);
1260 /* REVISIT this looks wrong... */
1261 if (!status || dma || usb_pipeisoc(nPipe)) {
1263 #ifdef CONFIG_USB_INVENTRA_DMA
1264 /* mode 0 or last short packet)
1265 * REVISIT how about ZLP?
1267 if ((dma->bDesiredMode == 0)
1268 || (dma->dwActualLength
1269 & (qh->maxpacket - 1))) {
1270 /* Send out the packet first ... */
1271 MGC_SelectEnd(pBase, bEnd);
1272 MGC_WriteCsr16(pBase, MGC_O_HDRC_TXCSR, bEnd,
1273 MGC_M_TXCSR_TXPKTRDY);
1277 wLength = dma->dwActualLength;
1279 wLength = qh->segsize;
1280 qh->offset += wLength;
1282 if (usb_pipeisoc(nPipe)) {
1283 struct usb_iso_packet_descriptor *d;
1285 d = pUrb->iso_frame_desc + qh->iso_idx;
1286 d->actual_length = qh->segsize;
1287 if (++qh->iso_idx >= pUrb->number_of_packets) {
1291 pBuffer = pUrb->transfer_buffer + d->offset;
1292 wLength = d->length;
1297 /* see if we need to send more data, or ZLP */
1298 if (qh->segsize < qh->maxpacket)
1300 else if (qh->offset == pUrb->transfer_buffer_length
1301 && !(pUrb-> transfer_flags
1305 pBuffer = pUrb->transfer_buffer
1307 wLength = pUrb->transfer_buffer_length
1313 /* urb->status != -EINPROGRESS means request has been faulted,
1314 * so we must abort this transfer after cleanup
1316 if (pUrb->status != -EINPROGRESS) {
1319 status = pUrb->status;
1324 pUrb->status = status;
1325 pUrb->actual_length = qh->offset;
1326 musb_advance_schedule(pThis, pUrb, pEnd, USB_DIR_OUT);
1328 } else if (!(wTxCsrVal & MGC_M_TXCSR_DMAENAB)) {
1329 // WARN_ON(!pBuffer);
1331 /* REVISIT: some docs say that when pEnd->tx_double_buffered,
1332 * (and presumably, fifo is not half-full) we should write TWO
1333 * packets before updating TXCSR ... other docs disagree ...
1335 /* PIO: start next packet in this URB */
1336 wLength = min(qh->maxpacket, (u16) wLength);
1337 musb_write_fifo(pEnd, wLength, pBuffer);
1338 qh->segsize = wLength;
1340 MGC_SelectEnd(pBase, bEnd);
1341 MGC_WriteCsr16(pBase, MGC_O_HDRC_TXCSR, bEnd,
1342 MGC_M_TXCSR_H_WZC_BITS | MGC_M_TXCSR_TXPKTRDY);
1344 DBG(1, "not complete, but dma enabled?\n");
1351 #ifdef CONFIG_USB_INVENTRA_DMA
1353 /* Host side RX (IN) using Mentor DMA works as follows:
1355 - if queue was empty, ProgramEndpoint
1356 - first IN token is sent out (by setting ReqPkt)
1357 LinuxIsr -> RxReady()
1358 /\ => first packet is received
1359 | - Set in mode 0 (DmaEnab, ~ReqPkt)
1360 | -> DMA Isr (transfer complete) -> RxReady()
1361 | - Ack receive (~RxPktRdy), turn off DMA (~DmaEnab)
1362 | - if urb not complete, send next IN token (ReqPkt)
1363 | | else complete urb.
1365 ---------------------------
1367 * Nuances of mode 1:
1368 * For short packets, no ack (+RxPktRdy) is sent automatically
1369 * (even if AutoClear is ON)
1370 * For full packets, ack (~RxPktRdy) and next IN token (+ReqPkt) is sent
1371 * automatically => major problem, as collecting the next packet becomes
1372 * difficult. Hence mode 1 is not used.
1375 * All we care about at this driver level is that
1376 * (a) all URBs terminate with REQPKT cleared and fifo(s) empty;
1377 * (b) termination conditions are: short RX, or buffer full;
1378 * (c) fault modes include
1379 * - iff URB_SHORT_NOT_OK, short RX status is -EREMOTEIO.
1380 * (and that endpoint's dma queue stops immediately)
1381 * - overflow (full, PLUS more bytes in the terminal packet)
1383 * So for example, usb-storage sets URB_SHORT_NOT_OK, and would
1384 * thus be a great candidate for using mode 1 ... for all but the
1385 * last packet of one URB's transfer.
1391 * Service an RX interrupt for the given IN endpoint; docs cover bulk, iso,
1392 * and high-bandwidth IN transfer cases.
1394 void musb_host_rx(struct musb *pThis, u8 bEnd)
1397 struct musb_hw_ep *pEnd = pThis->aLocalEnd + bEnd;
1398 struct musb_qh *qh = pEnd->in_qh;
1400 void __iomem *pBase = pThis->pRegs;
1402 u16 wRxCsrVal, wVal;
1403 u8 bIsochError = FALSE;
1406 struct dma_channel *dma;
1408 MGC_SelectEnd(pBase, bEnd);
1410 pUrb = next_urb(qh);
1411 dma = is_dma_capable() ? pEnd->rx_channel : NULL;
1415 wVal = wRxCsrVal = MGC_ReadCsr16(pBase, MGC_O_HDRC_RXCSR, bEnd);
1417 if (unlikely(!pUrb)) {
1418 /* REVISIT -- THIS SHOULD NEVER HAPPEN ... but, at least
1419 * usbtest #11 (unlinks) triggers it regularly, sometimes
1420 * with fifo full. (Only with DMA??)
1422 DBG(3, "BOGUS RX%d ready, csr %04x, count %d\n", bEnd, wVal,
1423 MGC_ReadCsr16(pBase, MGC_O_HDRC_RXCOUNT, bEnd));
1424 musb_h_flush_rxfifo(pEnd, MGC_M_RXCSR_CLRDATATOG);
1430 DBG(5, "<== hw %d rxcsr %04x, urb actual %d (+dma %zd)\n",
1431 bEnd, wRxCsrVal, pUrb->actual_length,
1432 dma ? dma->dwActualLength : 0);
1434 /* check for errors, concurrent stall & unlink is not really
1436 if (wRxCsrVal & MGC_M_RXCSR_H_RXSTALL) {
1437 DBG(3, "RX end %d STALL\n", bEnd);
1439 /* stall; record URB status */
1442 } else if (wRxCsrVal & MGC_M_RXCSR_H_ERROR) {
1443 DBG(3, "end %d RX proto error\n", bEnd);
1446 MGC_WriteCsr8(pBase, MGC_O_HDRC_RXINTERVAL, bEnd, 0);
1448 } else if (wRxCsrVal & MGC_M_RXCSR_DATAERROR) {
1450 if (USB_ENDPOINT_XFER_ISOC != qh->type) {
1451 /* NOTE this code path would be a good place to PAUSE a
1452 * transfer, if there's some other (nonperiodic) rx urb
1453 * that could use this fifo. (dma complicates it...)
1455 * if (bulk && qh->ring.next != &musb->in_bulk), then
1456 * we have a candidate... NAKing is *NOT* an error
1458 DBG(6, "RX end %d NAK timeout\n", bEnd);
1459 MGC_SelectEnd(pBase, bEnd);
1460 MGC_WriteCsr16(pBase, MGC_O_HDRC_RXCSR, bEnd,
1461 MGC_M_RXCSR_H_WZC_BITS
1462 | MGC_M_RXCSR_H_REQPKT);
1466 DBG(4, "RX end %d ISO data error\n", bEnd);
1467 /* packet error reported later */
1472 /* faults abort the transfer */
1474 /* clean up dma and collect transfer count */
1475 if (dma_channel_status(dma) == MGC_DMA_STATUS_BUSY) {
1476 dma->bStatus = MGC_DMA_STATUS_CORE_ABORT;
1477 (void) pThis->pDmaController->channel_abort(dma);
1478 xfer_len = dma->dwActualLength;
1480 musb_h_flush_rxfifo(pEnd, 0);
1481 MGC_WriteCsr8(pBase, MGC_O_HDRC_RXINTERVAL, bEnd, 0);
1486 if (unlikely(dma_channel_status(dma) == MGC_DMA_STATUS_BUSY)) {
1487 /* SHOULD NEVER HAPPEN ... but at least DaVinci has done it */
1488 ERR("RX%d dma busy, csr %04x\n", bEnd, wRxCsrVal);
1492 /* thorough shutdown for now ... given more precise fault handling
1493 * and better queueing support, we might keep a DMA pipeline going
1494 * while processing this irq for earlier completions.
1497 /* FIXME this is _way_ too much in-line logic for Mentor DMA */
1499 #ifndef CONFIG_USB_INVENTRA_DMA
1500 if (wRxCsrVal & MGC_M_RXCSR_H_REQPKT) {
1501 /* REVISIT this happened for a while on some short reads...
1502 * the cleanup still needs investigation... looks bad...
1503 * and also duplicates dma cleanup code above ... plus,
1504 * shouldn't this be the "half full" double buffer case?
1506 if (dma_channel_status(dma) == MGC_DMA_STATUS_BUSY) {
1507 dma->bStatus = MGC_DMA_STATUS_CORE_ABORT;
1508 (void) pThis->pDmaController->channel_abort(dma);
1509 xfer_len = dma->dwActualLength;
1513 DBG(2, "RXCSR%d %04x, reqpkt, len %zd%s\n", bEnd, wRxCsrVal,
1514 xfer_len, dma ? ", dma" : "");
1515 wRxCsrVal &= ~MGC_M_RXCSR_H_REQPKT;
1517 MGC_SelectEnd(pBase, bEnd);
1518 MGC_WriteCsr16(pBase, MGC_O_HDRC_RXCSR, bEnd,
1519 MGC_M_RXCSR_H_WZC_BITS | wRxCsrVal);
1522 if (dma && (wRxCsrVal & MGC_M_RXCSR_DMAENAB)) {
1523 xfer_len = dma->dwActualLength;
1525 wVal &= ~(MGC_M_RXCSR_DMAENAB
1526 | MGC_M_RXCSR_H_AUTOREQ
1527 | MGC_M_RXCSR_AUTOCLEAR
1528 | MGC_M_RXCSR_RXPKTRDY);
1529 musb_writew(pEnd->regs, MGC_O_HDRC_RXCSR, wVal);
1531 #ifdef CONFIG_USB_INVENTRA_DMA
1532 pUrb->actual_length += xfer_len;
1533 qh->offset += xfer_len;
1535 /* bDone if pUrb buffer is full or short packet is recd */
1536 bDone = (pUrb->actual_length >= pUrb->transfer_buffer_length)
1537 || (dma->dwActualLength & (qh->maxpacket - 1));
1539 /* send IN token for next packet, without AUTOREQ */
1541 wVal |= MGC_M_RXCSR_H_REQPKT;
1542 MGC_WriteCsr16(pBase, MGC_O_HDRC_RXCSR, bEnd,
1543 MGC_M_RXCSR_H_WZC_BITS | wVal);
1546 DBG(4, "ep %d dma %s, rxcsr %04x, rxcount %d\n", bEnd,
1547 bDone ? "off" : "reset",
1548 MGC_ReadCsr16(pBase, MGC_O_HDRC_RXCSR, bEnd),
1549 MGC_ReadCsr16(pBase, MGC_O_HDRC_RXCOUNT, bEnd));
1553 } else if (pUrb->status == -EINPROGRESS) {
1554 /* if no errors, be sure a packet is ready for unloading */
1555 if (unlikely(!(wRxCsrVal & MGC_M_RXCSR_RXPKTRDY))) {
1557 ERR("Rx interrupt with no errors or packet!\n");
1559 // FIXME this is another "SHOULD NEVER HAPPEN"
1562 /* do the proper sequence to abort the transfer */
1563 MGC_SelectEnd(pBase, bEnd);
1564 wVal &= ~MGC_M_RXCSR_H_REQPKT;
1565 MGC_WriteCsr16(pBase, MGC_O_HDRC_RXCSR, bEnd, wVal);
1569 /* we are expecting IN packets */
1570 #ifdef CONFIG_USB_INVENTRA_DMA
1572 struct dma_controller *c;
1576 wRxCount = MGC_ReadCsr16(pBase,
1577 MGC_O_HDRC_RXCOUNT, bEnd);
1579 DBG(2, "RX%d count %d, buffer 0x%x len %d/%d\n",
1582 + pUrb->actual_length,
1584 pUrb->transfer_buffer_length);
1586 c = pThis->pDmaController;
1588 dma->bDesiredMode = 0;
1590 /* because of the issue below, mode 1 will
1591 * only rarely behave with correct semantics.
1593 if ((pUrb->transfer_flags &
1595 && (pUrb->transfer_buffer_length -
1596 pUrb->actual_length)
1598 dma->bDesiredMode = 1;
1601 /* Disadvantage of using mode 1:
1602 * It's basically usable only for mass storage class; essentially all
1603 * other protocols also terminate transfers on short packets.
1606 * An extra IN token is sent at the end of the transfer (due to AUTOREQ)
1607 * If you try to use mode 1 for (transfer_buffer_length - 512), and try
1608 * to use the extra IN token to grab the last packet using mode 0, then
1609 * the problem is that you cannot be sure when the device will send the
1610 * last packet and RxPktRdy set. Sometimes the packet is recd too soon
1611 * such that it gets lost when RxCSR is re-set at the end of the mode 1
1612 * transfer, while sometimes it is recd just a little late so that if you
1613 * try to configure for mode 0 soon after the mode 1 transfer is
1614 * completed, you will find rxcount 0. Okay, so you might think why not
1615 * wait for an interrupt when the pkt is recd. Well, you won't get any!
1618 wVal = MGC_ReadCsr16(pBase, MGC_O_HDRC_RXCSR, bEnd);
1619 wVal &= ~MGC_M_RXCSR_H_REQPKT;
1621 if (dma->bDesiredMode == 0)
1622 wVal &= ~MGC_M_RXCSR_H_AUTOREQ;
1624 wVal |= MGC_M_RXCSR_H_AUTOREQ;
1625 wVal |= MGC_M_RXCSR_AUTOCLEAR | MGC_M_RXCSR_DMAENAB;
1627 MGC_WriteCsr16(pBase, MGC_O_HDRC_RXCSR, bEnd,
1628 MGC_M_RXCSR_H_WZC_BITS | wVal);
1630 /* REVISIT if when actual_length != 0,
1631 * transfer_buffer_length needs to be
1634 status = c->channel_program(
1638 + pUrb->actual_length,
1639 (dma->bDesiredMode == 0)
1641 : pUrb->transfer_buffer_length);
1644 c->channel_release(dma);
1645 dma = pEnd->rx_channel = NULL;
1646 /* REVISIT reset CSR */
1649 #endif /* Mentor DMA */
1652 bDone = musb_host_packet_rx(pThis, pUrb,
1654 DBG(6, "read %spacket\n", bDone ? "last " : "");
1659 pUrb->actual_length += xfer_len;
1660 qh->offset += xfer_len;
1662 if (pUrb->status == -EINPROGRESS)
1663 pUrb->status = status;
1664 musb_advance_schedule(pThis, pUrb, pEnd, USB_DIR_IN);
1668 /* schedule nodes correspond to peripheral endpoints, like an OHCI QH.
1669 * the software schedule associates multiple such nodes with a given
1670 * host side hardware endpoint + direction; scheduling may activate
1671 * that hardware endpoint.
1673 static int musb_schedule(
1681 struct musb_hw_ep *hw_ep = NULL;
1682 struct list_head *head = NULL;
1684 /* use fixed hardware for control and bulk */
1686 case USB_ENDPOINT_XFER_CONTROL:
1687 head = &musb->control;
1688 hw_ep = musb->control_ep;
1690 case USB_ENDPOINT_XFER_BULK:
1691 hw_ep = musb->bulk_ep;
1693 head = &musb->in_bulk;
1695 head = &musb->out_bulk;
1699 idle = list_empty(head);
1700 list_add_tail(&qh->ring, head);
1704 /* else, periodic transfers get muxed to other endpoints */
1706 /* FIXME this doesn't consider direction, so it can only
1707 * work for one half of the endpoint hardware, and assumes
1708 * the previous cases handled all non-shared endpoints...
1711 /* we know this qh hasn't been scheduled, so all we need to do
1712 * is choose which hardware endpoint to put it on ...
1714 * REVISIT what we really want here is a regular schedule tree
1715 * like e.g. OHCI uses, but for now musb->periodic is just an
1716 * array of the _single_ logical endpoint associated with a
1717 * given physical one (identity mapping logical->physical).
1719 * that simplistic approach makes TT scheduling a lot simpler;
1720 * there is none, and thus none of its complexity...
1725 for (nEnd = 1; nEnd < musb->bEndCount; nEnd++) {
1728 if (musb->periodic[nEnd])
1730 hw_ep = &musb->aLocalEnd[nEnd];
1731 if (hw_ep == musb->bulk_ep)
1735 diff = hw_ep->wMaxPacketSizeRx - qh->maxpacket;
1737 diff = hw_ep->wMaxPacketSizeTx - qh->maxpacket;
1739 if (diff > 0 && wBestDiff > diff) {
1748 hw_ep = musb->aLocalEnd + nBestEnd;
1749 musb->periodic[nBestEnd] = qh;
1750 DBG(4, "qh %p periodic slot %d\n", qh, nBestEnd);
1753 qh->hep->hcpriv = qh;
1755 musb_start_urb(musb, is_in, qh);
1759 static int musb_urb_enqueue(
1760 struct usb_hcd *hcd,
1761 struct usb_host_endpoint *hep,
1765 unsigned long flags;
1766 struct musb *musb = hcd_to_musb(hcd);
1767 struct musb_qh *qh = hep->hcpriv;
1768 struct usb_endpoint_descriptor *epd = &hep->desc;
1773 /* host role must be active */
1774 if (!is_host_active(musb) || !musb->is_active)
1777 /* DMA mapping was already done, if needed, and this urb is on
1778 * hep->urb_list ... so there's little to do unless hep wasn't
1779 * yet scheduled onto a live qh.
1781 * REVISIT best to keep hep->hcpriv valid until the endpoint gets
1782 * disabled, testing for empty qh->ring and avoiding qh setup costs
1783 * except for the first urb queued after a config change.
1790 /* Allocate and initialize qh, minimizing the work done each time
1791 * hw_ep gets reprogrammed, or with irqs blocked. Then schedule it.
1793 * REVISIT consider a dedicated qh kmem_cache, so it's harder
1794 * for bugs in other kernel code to break this driver...
1796 qh = kzalloc(sizeof *qh, mem_flags);
1802 INIT_LIST_HEAD(&qh->ring);
1805 qh->maxpacket = le16_to_cpu(epd->wMaxPacketSize);
1807 /* no high bandwidth support yet */
1808 if (qh->maxpacket & ~0x7ff) {
1813 qh->epnum = epd->bEndpointAddress & USB_ENDPOINT_NUMBER_MASK;
1814 qh->type = epd->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK;
1816 /* NOTE: urb->dev->devnum is wrong during SET_ADDRESS */
1817 qh->addr_reg = (u8) usb_pipedevice(urb->pipe);
1819 /* precompute rxtype/txtype/type0 register */
1820 type_reg = (qh->type << 4) | qh->epnum;
1821 switch (urb->dev->speed) {
1825 case USB_SPEED_FULL:
1831 qh->type_reg = type_reg;
1833 /* precompute rxinterval/txinterval register */
1834 interval = min((u8)16, epd->bInterval); /* log encoding */
1836 case USB_ENDPOINT_XFER_INT:
1837 /* fullspeed uses linear encoding */
1838 if (USB_SPEED_FULL == urb->dev->speed) {
1839 interval = epd->bInterval;
1844 case USB_ENDPOINT_XFER_ISOC:
1845 /* iso always uses log encoding */
1848 /* REVISIT we actually want to use NAK limits, hinting to the
1849 * transfer scheduling logic to try some other qh, e.g. try
1852 * interval = (USB_SPEED_HIGH == pUrb->dev->speed) ? 16 : 2;
1854 * The downside of disabling this is that transfer scheduling
1855 * gets VERY unfair for nonperiodic transfers; a misbehaving
1856 * peripheral could make that hurt. Or for reads, one that's
1857 * perfectly normal: network and other drivers keep reads
1858 * posted at all times, having one pending for a week should
1859 * be perfectly safe.
1861 * The upside of disabling it is avoidng transfer scheduling
1862 * code to put this aside for while.
1866 qh->intv_reg = interval;
1868 /* precompute addressing for external hub/tt ports */
1869 if (musb->bIsMultipoint) {
1870 struct usb_device *parent = urb->dev->parent;
1872 if (parent != hcd->self.root_hub) {
1873 qh->h_addr_reg = (u8) parent->devnum;
1875 /* set up tt info if needed */
1877 qh->h_port_reg = (u8) urb->dev->ttport;
1878 qh->h_addr_reg |= 0x80;
1883 /* invariant: hep->hcpriv is null OR the qh that's already scheduled.
1884 * until we get real dma queues (with an entry for each urb/buffer),
1885 * we only have work to do in the former case.
1887 spin_lock_irqsave(&musb->Lock, flags);
1889 /* some concurrent activity submitted another urb to hep...
1890 * odd, rare, error prone, but legal.
1895 status = musb_schedule(musb, qh,
1896 epd->bEndpointAddress & USB_ENDPOINT_DIR_MASK);
1900 /* FIXME set urb->start_frame for iso/intr, it's tested in
1901 * musb_start_urb(), but otherwise only konicawc cares ...
1904 spin_unlock_irqrestore(&musb->Lock, flags);
1914 * abort a transfer that's at the head of a hardware queue.
1915 * called with controller locked, irqs blocked
1916 * that hardware queue advances to the next transfer, unless prevented
1918 static int musb_cleanup_urb(struct urb *urb, struct musb_qh *qh, int is_in)
1920 struct musb_hw_ep *ep = qh->hw_ep;
1921 unsigned hw_end = ep->bLocalEnd;
1922 void __iomem *regs = ep->musb->pRegs;
1926 MGC_SelectEnd(regs, hw_end);
1928 if (is_dma_capable()) {
1929 struct dma_channel *dma;
1931 dma = is_in ? ep->rx_channel : ep->tx_channel;
1933 status = ep->musb->pDmaController->channel_abort(dma);
1935 "abort %cX%d DMA for urb %p --> %d\n",
1936 is_in ? 'R' : 'T', ep->bLocalEnd,
1938 urb->actual_length += dma->dwActualLength;
1942 /* turn off DMA requests, discard state, stop polling ... */
1944 /* giveback saves bulk toggle */
1945 csr = musb_h_flush_rxfifo(ep, 0);
1947 /* REVISIT we still get an irq; should likely clear the
1948 * endpoint's irq status here to avoid bogus irqs.
1949 * clearing that status is platform-specific...
1953 csr = MGC_ReadCsr16(regs, MGC_O_HDRC_TXCSR, hw_end);
1954 if (csr & MGC_M_TXCSR_FIFONOTEMPTY)
1955 csr |= MGC_M_TXCSR_FLUSHFIFO;
1956 csr &= ~( MGC_M_TXCSR_AUTOSET
1957 | MGC_M_TXCSR_DMAENAB
1958 | MGC_M_TXCSR_H_RXSTALL
1959 | MGC_M_TXCSR_H_NAKTIMEOUT
1960 | MGC_M_TXCSR_H_ERROR
1961 | MGC_M_TXCSR_FIFONOTEMPTY
1963 MGC_WriteCsr16(regs, MGC_O_HDRC_TXCSR, 0, csr);
1964 /* REVISIT may need to clear FLUSHFIFO ... */
1965 MGC_WriteCsr16(regs, MGC_O_HDRC_TXCSR, 0, csr);
1966 /* flush cpu writebuffer */
1967 csr = MGC_ReadCsr16(regs, MGC_O_HDRC_TXCSR, hw_end);
1970 musb_advance_schedule(ep->musb, urb, ep, is_in);
1974 static int musb_urb_dequeue(struct usb_hcd *hcd, struct urb *urb)
1976 struct musb *musb = hcd_to_musb(hcd);
1978 struct list_head *sched;
1980 unsigned long flags;
1981 int status = -ENOENT;
1983 DBG(4, "urb=%p, dev%d ep%d%s\n", urb,
1984 usb_pipedevice(urb->pipe),
1985 usb_pipeendpoint(urb->pipe),
1986 usb_pipein(urb->pipe) ? "in" : "out");
1988 spin_lock_irqsave(&musb->Lock, flags);
1990 /* make sure the urb is still queued and not completed */
1991 spin_lock(&urb->lock);
1994 struct usb_host_endpoint *hep;
1997 list_for_each_entry(tmp, &hep->urb_list, urb_list) {
2004 spin_unlock(&urb->lock);
2008 /* Any URB not actively programmed into endpoint hardware can be
2009 * immediately given back. Such an URB must be at the head of its
2010 * endpoint queue, unless someday we get real DMA queues. And even
2011 * then, it might not be known to the hardware...
2013 * Otherwise abort current transfer, pending dma, etc.; urb->status
2014 * has already been updated. This is a synchronous abort; it'd be
2015 * OK to hold off until after some IRQ, though.
2017 if (!qh->is_ready || urb->urb_list.prev != &qh->hep->urb_list)
2018 status = -EINPROGRESS;
2021 case USB_ENDPOINT_XFER_CONTROL:
2022 sched = &musb->control;
2024 case USB_ENDPOINT_XFER_BULK:
2025 if (usb_pipein(urb->pipe))
2026 sched = &musb->in_bulk;
2028 sched = &musb->out_bulk;
2031 /* REVISIT when we get a schedule tree, periodic
2032 * transfers won't always be at the head of a
2033 * singleton queue...
2040 /* NOTE: qh is invalid unless !list_empty(&hep->urb_list) */
2041 if (status < 0 || (sched && qh != first_qh(sched))) {
2042 int ready = qh->is_ready;
2046 __musb_giveback(musb, urb, 0);
2047 qh->is_ready = ready;
2049 status = musb_cleanup_urb(urb, qh, urb->pipe & USB_DIR_IN);
2051 spin_unlock_irqrestore(&musb->Lock, flags);
2055 /* disable an endpoint */
2057 musb_h_disable(struct usb_hcd *hcd, struct usb_host_endpoint *hep)
2059 u8 epnum = hep->desc.bEndpointAddress;
2060 unsigned long flags;
2061 struct musb *musb = hcd_to_musb(hcd);
2062 u8 is_in = epnum & USB_DIR_IN;
2063 struct musb_qh *qh = hep->hcpriv;
2064 struct urb *urb, *tmp;
2065 struct list_head *sched;
2070 spin_lock_irqsave(&musb->Lock, flags);
2073 case USB_ENDPOINT_XFER_CONTROL:
2074 sched = &musb->control;
2076 case USB_ENDPOINT_XFER_BULK:
2078 sched = &musb->in_bulk;
2080 sched = &musb->out_bulk;
2083 /* REVISIT when we get a schedule tree, periodic transfers
2084 * won't always be at the head of a singleton queue...
2090 /* NOTE: qh is invalid unless !list_empty(&hep->urb_list) */
2092 /* kick first urb off the hardware, if needed */
2094 if (!sched || qh == first_qh(sched)) {
2097 /* make software (then hardware) stop ASAP */
2098 spin_lock(&urb->lock);
2099 if (urb->status == -EINPROGRESS)
2100 urb->status = -ESHUTDOWN;
2101 spin_unlock(&urb->lock);
2104 musb_cleanup_urb(urb, qh, urb->pipe & USB_DIR_IN);
2108 /* then just nuke all the others */
2109 list_for_each_entry_safe_from(urb, tmp, &hep->urb_list, urb_list)
2110 musb_giveback(qh, urb, -ESHUTDOWN);
2112 spin_unlock_irqrestore(&musb->Lock, flags);
2115 static int musb_h_get_frame_number(struct usb_hcd *hcd)
2117 struct musb *musb = hcd_to_musb(hcd);
2119 return musb_readw(musb->pRegs, MGC_O_HDRC_FRAME);
2122 static int musb_h_start(struct usb_hcd *hcd)
2124 /* NOTE: musb_start() is called when the hub driver turns
2125 * on port power, or when (OTG) peripheral starts.
2127 hcd->state = HC_STATE_RUNNING;
2131 static void musb_h_stop(struct usb_hcd *hcd)
2133 musb_stop(hcd_to_musb(hcd));
2134 hcd->state = HC_STATE_HALT;
2137 static int musb_bus_suspend(struct usb_hcd *hcd)
2139 struct musb *musb = hcd_to_musb(hcd);
2141 return musb->is_active ? -EBUSY : 0;
2144 static int musb_bus_resume(struct usb_hcd *hcd)
2146 /* resuming child port does the work */
2150 const struct hc_driver musb_hc_driver = {
2151 .description = "musb-hcd",
2152 .product_desc = "MUSB HDRC host driver",
2153 .hcd_priv_size = sizeof (struct musb),
2154 .flags = HCD_USB2 | HCD_MEMORY,
2156 /* not using irq handler or reset hooks from usbcore, since
2157 * those must be shared with peripheral code for OTG configs
2160 .start = musb_h_start,
2161 .stop = musb_h_stop,
2163 .get_frame_number = musb_h_get_frame_number,
2165 .urb_enqueue = musb_urb_enqueue,
2166 .urb_dequeue = musb_urb_dequeue,
2167 .endpoint_disable = musb_h_disable,
2169 .hub_status_data = musb_hub_status_data,
2170 .hub_control = musb_hub_control,
2171 .bus_suspend = musb_bus_suspend,
2172 .bus_resume = musb_bus_resume,
2173 // .start_port_reset = NULL,
2174 // .hub_irq_enable = NULL,