1 /******************************************************************
2 * Copyright 2005 Mentor Graphics Corporation
3 * Copyright (C) 2005-2006 by Texas Instruments
4 * Copyright (C) 2006 by Nokia Corporation
6 * This file is part of the Inventra Controller Driver for Linux.
8 * The Inventra Controller Driver for Linux is free software; you
9 * can redistribute it and/or modify it under the terms of the GNU
10 * General Public License version 2 as published by the Free Software
13 * The Inventra Controller Driver for Linux is distributed in
14 * the hope that it will be useful, but WITHOUT ANY WARRANTY;
15 * without even the implied warranty of MERCHANTABILITY or
16 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
17 * License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with The Inventra Controller Driver for Linux ; if not,
21 * write to the Free Software Foundation, Inc., 59 Temple Place,
22 * Suite 330, Boston, MA 02111-1307 USA
24 * ANY DOWNLOAD, USE, REPRODUCTION, MODIFICATION OR DISTRIBUTION
25 * OF THIS DRIVER INDICATES YOUR COMPLETE AND UNCONDITIONAL ACCEPTANCE
26 * OF THOSE TERMS.THIS DRIVER IS PROVIDED "AS IS" AND MENTOR GRAPHICS
27 * MAKES NO WARRANTIES, EXPRESS OR IMPLIED, RELATED TO THIS DRIVER.
28 * MENTOR GRAPHICS SPECIFICALLY DISCLAIMS ALL IMPLIED WARRANTIES
29 * OF MERCHANTABILITY; FITNESS FOR A PARTICULAR PURPOSE AND
30 * NON-INFRINGEMENT. MENTOR GRAPHICS DOES NOT PROVIDE SUPPORT
31 * SERVICES OR UPDATES FOR THIS DRIVER, EVEN IF YOU ARE A MENTOR
32 * GRAPHICS SUPPORT CUSTOMER.
33 ******************************************************************/
35 #include <linux/module.h>
36 #include <linux/kernel.h>
37 #include <linux/delay.h>
38 #include <linux/sched.h>
39 #include <linux/slab.h>
40 #include <linux/errno.h>
41 #include <linux/init.h>
42 #include <linux/list.h>
45 #include "musb_host.h"
48 /* MUSB HOST status 22-mar-2006
50 * - There's still lots of partial code duplication for fault paths, so
51 * they aren't handled as consistently as they need to be.
53 * - PIO mostly behaved when last tested.
54 * + including ep0, with all usbtest cases 9, 10
55 * + usbtest 14 (ep0out) doesn't seem to run at all
56 * + double buffered OUT/TX endpoints saw stalls(!) with certain usbtest
57 * configurations, but otherwise double buffering passes basic tests.
58 * + for 2.6.N, for N > ~10, needs API changes for hcd framework.
60 * - DMA (CPPI) ... partially behaves, not currently recommended
61 * + about 1/15 the speed of typical EHCI implementations (PCI)
62 * + RX, all too often reqpkt seems to misbehave after tx
63 * + TX, no known issues (other than evident silicon issue)
65 * - DMA (Mentor/OMAP) ...has at least toggle update problems
67 * - Still no traffic scheduling code to make NAKing for bulk or control
68 * transfers unable to starve other requests; or to make efficient use
69 * of hardware with periodic transfers. (Note that network drivers
70 * commonly post bulk reads that stay pending for a long time; these
71 * would make very visible trouble.)
73 * - Not tested with HNP, but some SRP paths seem to behave.
77 * - Bulk traffic finally uses both sides of hardware ep1, freeing up an
78 * extra endpoint for periodic use enabling hub + keybd + mouse. That
79 * mostly works, except that with "usbnet" it's easy to trigger cases
80 * with "ping" where RX loses. (a) ping to davinci, even "ping -f",
81 * fine; but (b) ping _from_ davinci, even "ping -c 1", ICMP RX loses
82 * although ARP RX wins. (That test was done with a full speed link.)
87 * NOTE on endpoint usage:
89 * CONTROL transfers all go through ep0. BULK ones go through dedicated IN
90 * and OUT endpoints ... hardware is dedicated for those "async" queue(s).
92 * (Yes, bulk _could_ use more of the endpoints than that, and would even
93 * benefit from it ... one remote device may easily be NAKing while others
94 * need to perform transfers in that same direction. The same thing could
95 * be done in software though, assuming dma cooperates.)
97 * INTERUPPT and ISOCHRONOUS transfers are scheduled to the other endpoints.
98 * So far that scheduling is both dumb and optimistic: the endpoint will be
99 * "claimed" until its software queue is no longer refilled. No multiplexing
100 * of transfers between endpoints, or anything clever.
104 /*************************** Forwards ***************************/
106 static void musb_ep_program(struct musb *pThis, u8 bEnd,
107 struct urb *pUrb, unsigned int nOut,
108 u8 * pBuffer, u32 dwLength);
111 * Start transmit. Caller is responsible for locking shared resources.
112 * pThis must be locked.
114 static inline void musb_h_tx_start(struct musb_hw_ep *ep)
118 /* NOTE: no locks here; caller should lock and select EP */
120 txcsr = musb_readw(ep->regs, MGC_O_HDRC_TXCSR);
121 txcsr |= MGC_M_TXCSR_TXPKTRDY | MGC_M_TXCSR_H_WZC_BITS;
122 musb_writew(ep->regs, MGC_O_HDRC_TXCSR, txcsr);
124 txcsr = MGC_M_CSR0_H_SETUPPKT | MGC_M_CSR0_TXPKTRDY;
125 musb_writew(ep->regs, MGC_O_HDRC_CSR0, txcsr);
130 static inline void cppi_host_txdma_start(struct musb_hw_ep *ep)
134 /* NOTE: no locks here; caller should lock and select EP */
135 txcsr = musb_readw(ep->regs, MGC_O_HDRC_TXCSR);
136 txcsr |= MGC_M_TXCSR_DMAENAB | MGC_M_TXCSR_H_WZC_BITS;
137 musb_writew(ep->regs, MGC_O_HDRC_TXCSR, txcsr);
141 * Start the URB at the front of an endpoint's queue
142 * end must be claimed from the caller.
144 * Context: controller locked, irqs blocked
147 musb_start_urb(struct musb *musb, int is_in, struct musb_qh *qh)
152 void __iomem *pBase = musb->pRegs;
153 struct urb *urb = next_urb(qh);
154 struct musb_hw_ep *pEnd = qh->hw_ep;
155 unsigned nPipe = urb->pipe;
156 u8 bAddress = usb_pipedevice(nPipe);
157 int bEnd = pEnd->bLocalEnd;
159 /* initialize software qh state */
163 /* gather right source of data */
165 case USB_ENDPOINT_XFER_CONTROL:
166 /* control transfers always start with SETUP */
169 musb->bEnd0Stage = MGC_END0_START;
170 pBuffer = urb->setup_packet;
173 case USB_ENDPOINT_XFER_ISOC:
176 pBuffer = urb->transfer_buffer + urb->iso_frame_desc[0].offset;
177 dwLength = urb->iso_frame_desc[0].length;
179 default: /* bulk, interrupt */
180 pBuffer = urb->transfer_buffer;
181 dwLength = urb->transfer_buffer_length;
184 DBG(4, "qh %p urb %p dev%d ep%d%s%s, hw_ep %d, %p/%d\n",
185 qh, urb, bAddress, qh->epnum,
186 is_in ? "in" : "out",
187 ({char *s; switch (qh->type) {
188 case USB_ENDPOINT_XFER_CONTROL: s = ""; break;
189 case USB_ENDPOINT_XFER_BULK: s = "-bulk"; break;
190 case USB_ENDPOINT_XFER_ISOC: s = "-iso"; break;
191 default: s = "-intr"; break;
193 bEnd, pBuffer, dwLength);
195 /* Configure endpoint */
196 if (is_in || pEnd->bIsSharedFifo)
200 musb_ep_program(musb, bEnd, urb, !is_in, pBuffer, dwLength);
202 /* transmit may have more work: start it when it is time */
206 /* determine if the time is right for a periodic transfer */
208 case USB_ENDPOINT_XFER_ISOC:
209 case USB_ENDPOINT_XFER_INT:
210 DBG(3, "check whether there's still time for periodic Tx\n");
212 wFrame = musb_readw(pBase, MGC_O_HDRC_FRAME);
213 /* FIXME this doesn't implement that scheduling policy ...
214 * or handle framecounter wrapping
216 if ((urb->transfer_flags & URB_ISO_ASAP)
217 || (wFrame >= urb->start_frame)) {
218 /* REVISIT the SOF irq handler shouldn't duplicate
219 * this code; and we don't init urb->start_frame...
224 qh->frame = urb->start_frame;
225 /* enable SOF interrupt so we can count down */
226 DBG(1,"SOF for %d\n", bEnd);
227 #if 1 // ifndef CONFIG_ARCH_DAVINCI
228 musb_writeb(pBase, MGC_O_HDRC_INTRUSBE, 0xff);
234 DBG(4, "Start TX%d %s\n", bEnd,
235 pEnd->tx_channel ? "dma" : "pio");
237 if (!pEnd->tx_channel)
238 musb_h_tx_start(pEnd);
239 else if (is_cppi_enabled())
240 cppi_host_txdma_start(pEnd);
244 /* caller owns controller lock, irqs are blocked */
246 __musb_giveback(struct musb *musb, struct urb *urb, int status)
247 __releases(musb->Lock)
248 __acquires(musb->Lock)
250 if ((urb->transfer_flags & URB_SHORT_NOT_OK)
251 && (urb->actual_length < urb->transfer_buffer_length)
253 && usb_pipein(urb->pipe))
256 spin_lock(&urb->lock);
258 if (urb->status == -EINPROGRESS)
259 urb->status = status;
260 spin_unlock(&urb->lock);
262 DBG(({ int level; switch (urb->status) {
266 /* common/boring faults */
277 "complete %p (%d), dev%d ep%d%s, %d/%d\n",
279 usb_pipedevice(urb->pipe),
280 usb_pipeendpoint(urb->pipe),
281 usb_pipein(urb->pipe) ? "in" : "out",
282 urb->actual_length, urb->transfer_buffer_length
285 spin_unlock(&musb->Lock);
286 usb_hcd_giveback_urb(musb_to_hcd(musb), urb);
287 spin_lock(&musb->Lock);
290 /* for bulk/interrupt endpoints only */
291 static inline void musb_save_toggle(struct musb_hw_ep *ep, int is_in, struct urb *urb)
293 struct usb_device *udev = urb->dev;
295 void __iomem *epio = ep->regs;
298 /* FIXME: the current Mentor DMA code seems to have
299 * problems getting toggle correct.
302 if (is_in || ep->bIsSharedFifo)
308 csr = musb_readw(epio, MGC_O_HDRC_TXCSR);
309 usb_settoggle(udev, qh->epnum, 1,
310 (csr & MGC_M_TXCSR_H_DATATOGGLE)
313 csr = musb_readw(epio, MGC_O_HDRC_RXCSR);
314 usb_settoggle(udev, qh->epnum, 0,
315 (csr & MGC_M_RXCSR_H_DATATOGGLE)
320 /* caller owns controller lock, irqs are blocked */
321 static struct musb_qh *
322 musb_giveback(struct musb_qh *qh, struct urb *urb, int status)
325 struct musb_hw_ep *ep = qh->hw_ep;
326 struct musb *musb = ep->musb;
327 int ready = qh->is_ready;
329 if (ep->bIsSharedFifo)
332 is_in = usb_pipein(urb->pipe);
334 /* save toggle eagerly, for paranoia */
336 case USB_ENDPOINT_XFER_BULK:
337 case USB_ENDPOINT_XFER_INT:
338 musb_save_toggle(ep, is_in, urb);
340 case USB_ENDPOINT_XFER_ISOC:
341 if (status == 0 && urb->error_count)
347 __musb_giveback(musb, urb, status);
348 qh->is_ready = ready;
350 /* reclaim resources (and bandwidth) ASAP; deschedule it, and
351 * invalidate qh as soon as list_empty(&hep->urb_list)
353 if (list_empty(&qh->hep->urb_list)) {
354 struct list_head *head;
361 /* clobber old pointers to this qh */
362 if (is_in || ep->bIsSharedFifo)
366 qh->hep->hcpriv = NULL;
370 case USB_ENDPOINT_XFER_ISOC:
371 case USB_ENDPOINT_XFER_INT:
372 /* this is where periodic bandwidth should be
373 * de-allocated if it's tracked and allocated;
374 * and where we'd update the schedule tree...
376 musb->periodic[ep->bLocalEnd] = NULL;
381 case USB_ENDPOINT_XFER_CONTROL:
382 case USB_ENDPOINT_XFER_BULK:
383 /* fifo policy for these lists, except that NAKing
384 * should rotate a qh to the end (for fairness).
386 head = qh->ring.prev;
397 * Advance this hardware endpoint's queue, completing the specified urb and
398 * advancing to either the next urb queued to that qh, or else invalidating
399 * that qh and advancing to the next qh scheduled after the current one.
401 * Context: caller owns controller lock, irqs are blocked
404 musb_advance_schedule(struct musb *pThis, struct urb *urb,
405 struct musb_hw_ep *pEnd, int is_in)
409 if (is_in || pEnd->bIsSharedFifo)
413 qh = musb_giveback(qh, urb, 0);
415 #ifdef CONFIG_USB_INVENTRA_DMA
416 /* REVISIT udelay reportedly works around issues in unmodified
417 * Mentor RTL before v1.5, where it doesn't disable the pull-up
418 * resisters in high speed mode. That causes signal reflection
419 * and errors because inter packet IDLE time vanishes.
421 * Yes, this delay makes DMA-OUT a bit slower than PIO. But
422 * without it, some devices are unusable. But there seem to be
423 * other issues too, at least on DaVinci; the delay improves
424 * some full speed cases, and being DMA-coupled is strange...
426 if (is_dma_capable() && !is_in && pEnd->tx_channel)
427 udelay(15); /* 10 usec ~= 1x 512byte packet */
430 if (qh && qh->is_ready && !list_empty(&qh->hep->urb_list)) {
431 DBG(4, "... next ep%d %cX urb %p\n",
432 pEnd->bLocalEnd, is_in ? 'R' : 'T',
434 musb_start_urb(pThis, is_in, qh);
438 static inline u16 musb_h_flush_rxfifo(struct musb_hw_ep *hw_ep, u16 csr)
440 /* we don't want fifo to fill itself again;
441 * ignore dma (various models),
442 * leave toggle alone (may not have been saved yet)
444 csr |= MGC_M_RXCSR_FLUSHFIFO | MGC_M_RXCSR_RXPKTRDY;
445 csr &= ~( MGC_M_RXCSR_H_REQPKT
446 | MGC_M_RXCSR_H_AUTOREQ
447 | MGC_M_RXCSR_AUTOCLEAR
450 /* write 2x to allow double buffering */
451 musb_writew(hw_ep->regs, MGC_O_HDRC_RXCSR, csr);
452 musb_writew(hw_ep->regs, MGC_O_HDRC_RXCSR, csr);
454 /* flush writebuffer */
455 return musb_readw(hw_ep->regs, MGC_O_HDRC_RXCSR);
459 * PIO RX for a packet (or part of it).
461 static u8 musb_host_packet_rx(struct musb *pThis, struct urb *pUrb,
462 u8 bEnd, u8 bIsochError)
470 struct musb_hw_ep *pEnd = pThis->aLocalEnd + bEnd;
471 void __iomem *epio = pEnd->regs;
472 struct musb_qh *qh = pEnd->in_qh;
473 int nPipe = pUrb->pipe;
474 void *buffer = pUrb->transfer_buffer;
476 // MGC_SelectEnd(pBase, bEnd);
477 wRxCount = musb_readw(epio, MGC_O_HDRC_RXCOUNT);
480 if (usb_pipeisoc(nPipe)) {
482 struct usb_iso_packet_descriptor *d;
489 d = pUrb->iso_frame_desc + qh->iso_idx;
490 pBuffer = buffer + d->offset;
492 if (wRxCount > length) {
497 DBG(2, "** OVERFLOW %d into %d\n", wRxCount, length);
501 pUrb->actual_length += length;
502 d->actual_length = length;
506 /* see if we are done */
507 bDone = (++qh->iso_idx >= pUrb->number_of_packets);
510 pBuffer = buffer + qh->offset;
511 length = pUrb->transfer_buffer_length - qh->offset;
512 if (wRxCount > length) {
513 if (pUrb->status == -EINPROGRESS)
514 pUrb->status = -EOVERFLOW;
515 DBG(2, "** OVERFLOW %d into %d\n", wRxCount, length);
519 pUrb->actual_length += length;
520 qh->offset += length;
522 /* see if we are done */
523 bDone = (pUrb->actual_length == pUrb->transfer_buffer_length)
524 || (wRxCount < qh->maxpacket)
525 || (pUrb->status != -EINPROGRESS);
527 && (pUrb->status == -EINPROGRESS)
528 && (pUrb->transfer_flags & URB_SHORT_NOT_OK)
529 && (pUrb->actual_length
530 < pUrb->transfer_buffer_length))
531 pUrb->status = -EREMOTEIO;
534 musb_read_fifo(pEnd, length, pBuffer);
536 wCsr = musb_readw(epio, MGC_O_HDRC_RXCSR);
537 wCsr |= MGC_M_RXCSR_H_WZC_BITS;
538 if (unlikely(do_flush))
539 musb_h_flush_rxfifo(pEnd, wCsr);
541 /* REVISIT this assumes AUTOCLEAR is never set */
542 wCsr &= ~(MGC_M_RXCSR_RXPKTRDY | MGC_M_RXCSR_H_REQPKT);
544 wCsr |= MGC_M_RXCSR_H_REQPKT;
545 musb_writew(epio, MGC_O_HDRC_RXCSR, wCsr);
551 /* we don't always need to reinit a given side of an endpoint...
552 * when we do, use tx/rx reinit routine and then construct a new CSR
553 * to address data toggle, NYET, and DMA or PIO.
555 * it's possible that driver bugs (especially for DMA) or aborting a
556 * transfer might have left the endpoint busier than it should be.
557 * the busy/not-empty tests are basically paranoia.
560 musb_rx_reinit(struct musb *musb, struct musb_qh *qh, struct musb_hw_ep *ep)
564 /* NOTE: we know the "rx" fifo reinit never triggers for ep0.
565 * That always uses tx_reinit since ep0 repurposes TX register
566 * offsets; the initial SETUP packet is also a kind of OUT.
569 /* if programmed for Tx, put it in RX mode */
570 if (ep->bIsSharedFifo) {
571 csr = musb_readw(ep->regs, MGC_O_HDRC_TXCSR);
572 if (csr & MGC_M_TXCSR_MODE) {
573 if (csr & MGC_M_TXCSR_FIFONOTEMPTY) {
574 /* this shouldn't happen; irq?? */
575 ERR("shared fifo not empty?\n");
576 musb_writew(ep->regs, MGC_O_HDRC_TXCSR,
577 MGC_M_TXCSR_FLUSHFIFO);
578 musb_writew(ep->regs, MGC_O_HDRC_TXCSR,
579 MGC_M_TXCSR_FRCDATATOG);
582 /* clear mode (and everything else) to enable Rx */
583 musb_writew(ep->regs, MGC_O_HDRC_TXCSR, 0);
585 /* scrub all previous state, clearing toggle */
587 csr = musb_readw(ep->regs, MGC_O_HDRC_RXCSR);
588 if (csr & MGC_M_RXCSR_RXPKTRDY)
589 WARN("rx%d, packet/%d ready?\n", ep->bLocalEnd,
590 musb_readw(ep->regs, MGC_O_HDRC_RXCOUNT));
592 musb_h_flush_rxfifo(ep, MGC_M_RXCSR_CLRDATATOG);
595 /* target addr and (for multipoint) hub addr/port */
596 if (musb->bIsMultipoint) {
597 musb_writeb(ep->target_regs, MGC_O_HDRC_RXFUNCADDR,
599 musb_writeb(ep->target_regs, MGC_O_HDRC_RXHUBADDR,
601 musb_writeb(ep->target_regs, MGC_O_HDRC_RXHUBPORT,
604 musb_writeb(musb->pRegs, MGC_O_HDRC_FADDR, qh->addr_reg);
606 /* protocol/endpoint, interval/NAKlimit, i/o size */
607 musb_writeb(ep->regs, MGC_O_HDRC_RXTYPE, qh->type_reg);
608 musb_writeb(ep->regs, MGC_O_HDRC_RXINTERVAL, qh->intv_reg);
609 /* NOTE: bulk combining rewrites high bits of maxpacket */
610 musb_writew(ep->regs, MGC_O_HDRC_RXMAXP, qh->maxpacket);
617 * Program an HDRC endpoint as per the given URB
618 * Context: irqs blocked, controller lock held
620 static void musb_ep_program(struct musb *pThis, u8 bEnd,
621 struct urb *pUrb, unsigned int is_out,
622 u8 * pBuffer, u32 dwLength)
624 struct dma_controller *pDmaController;
625 struct dma_channel *pDmaChannel;
627 void __iomem *pBase = pThis->pRegs;
628 struct musb_hw_ep *pEnd = pThis->aLocalEnd + bEnd;
629 void __iomem *epio = pEnd->regs;
633 if (!is_out || pEnd->bIsSharedFifo)
638 wPacketSize = qh->maxpacket;
640 DBG(3, "%s hw%d urb %p spd%d dev%d ep%d%s "
641 "h_addr%02x h_port%02x bytes %d\n",
642 is_out ? "-->" : "<--",
643 bEnd, pUrb, pUrb->dev->speed,
644 qh->addr_reg, qh->epnum, is_out ? "out" : "in",
645 qh->h_addr_reg, qh->h_port_reg,
648 MGC_SelectEnd(pBase, bEnd);
650 /* candidate for DMA? */
651 pDmaController = pThis->pDmaController;
652 if (is_dma_capable() && bEnd && pDmaController) {
653 pDmaChannel = is_out ? pEnd->tx_channel : pEnd->rx_channel;
655 pDmaChannel = pDmaController->channel_alloc(
656 pDmaController, pEnd, is_out);
658 pEnd->tx_channel = pDmaChannel;
660 pEnd->rx_channel = pDmaChannel;
665 /* make sure we clear DMAEnab, autoSet bits from previous run */
667 /* OUT/transmit/EP0 or IN/receive? */
673 wCsr = musb_readw(epio, MGC_O_HDRC_TXCSR);
675 /* disable interrupt in case we flush */
676 wIntrTxE = musb_readw(pBase, MGC_O_HDRC_INTRTXE);
677 musb_writew(pBase, MGC_O_HDRC_INTRTXE, wIntrTxE & ~(1 << bEnd));
679 /* general endpoint setup */
683 /* ASSERT: TXCSR_DMAENAB was already cleared */
685 /* flush all old state, set default */
686 if (csr & MGC_M_TXCSR_FIFONOTEMPTY)
687 csr |= MGC_M_TXCSR_FLUSHFIFO;
688 csr &= ~(MGC_M_TXCSR_H_NAKTIMEOUT
689 | MGC_M_TXCSR_DMAMODE
690 | MGC_M_TXCSR_FRCDATATOG
691 | MGC_M_TXCSR_H_RXSTALL
692 | MGC_M_TXCSR_H_ERROR
693 | MGC_M_TXCSR_FIFONOTEMPTY
694 | MGC_M_TXCSR_TXPKTRDY
696 csr |= MGC_M_TXCSR_MODE;
698 if (usb_gettoggle(pUrb->dev,
700 csr |= MGC_M_TXCSR_H_WR_DATATOGGLE
701 | MGC_M_TXCSR_H_DATATOGGLE;
703 csr |= MGC_M_TXCSR_CLRDATATOG;
705 /* twice in case of double packet buffering */
706 musb_writew(epio, MGC_O_HDRC_TXCSR, csr);
707 /* REVISIT may need to clear FLUSHFIFO ... */
708 musb_writew(epio, MGC_O_HDRC_TXCSR, csr);
709 wCsr = musb_readw(epio, MGC_O_HDRC_TXCSR);
711 /* endpoint 0: just flush */
712 musb_writew(epio, MGC_O_HDRC_CSR0,
713 wCsr | MGC_M_CSR0_FLUSHFIFO);
714 musb_writew(epio, MGC_O_HDRC_CSR0,
715 wCsr | MGC_M_CSR0_FLUSHFIFO);
718 /* target addr and (for multipoint) hub addr/port */
719 if (pThis->bIsMultipoint) {
721 MGC_BUSCTL_OFFSET(bEnd, MGC_O_HDRC_TXFUNCADDR),
724 MGC_BUSCTL_OFFSET(bEnd, MGC_O_HDRC_TXHUBADDR),
727 MGC_BUSCTL_OFFSET(bEnd, MGC_O_HDRC_TXHUBPORT),
729 /* FIXME if !bEnd, do the same for RX ... */
731 musb_writeb(pBase, MGC_O_HDRC_FADDR, qh->addr_reg);
733 /* protocol/endpoint/interval/NAKlimit */
735 musb_writeb(epio, MGC_O_HDRC_TXTYPE, qh->type_reg);
736 if (can_bulk_split(pThis, qh->type))
737 musb_writew(epio, MGC_O_HDRC_TXMAXP,
739 | ((pEnd->wMaxPacketSizeTx /
740 wPacketSize) - 1) << 11);
742 musb_writew(epio, MGC_O_HDRC_TXMAXP,
744 musb_writeb(epio, MGC_O_HDRC_TXINTERVAL, qh->intv_reg);
746 musb_writeb(epio, MGC_O_HDRC_NAKLIMIT0, qh->intv_reg);
747 if (pThis->bIsMultipoint)
748 musb_writeb(epio, MGC_O_HDRC_TYPE0,
752 if (can_bulk_split(pThis, qh->type))
753 wLoadCount = min((u32) pEnd->wMaxPacketSizeTx,
756 wLoadCount = min((u32) wPacketSize, dwLength);
758 #ifdef CONFIG_USB_INVENTRA_DMA
761 /* clear previous state */
762 wCsr = musb_readw(epio, MGC_O_HDRC_TXCSR);
763 wCsr &= ~(MGC_M_TXCSR_AUTOSET
764 | MGC_M_TXCSR_DMAMODE
765 | MGC_M_TXCSR_DMAENAB);
766 wCsr |= MGC_M_TXCSR_MODE;
767 musb_writew(epio, MGC_O_HDRC_TXCSR,
768 wCsr | MGC_M_TXCSR_MODE);
770 qh->segsize = min(dwLength, pDmaChannel->dwMaxLength);
772 if (qh->segsize <= wPacketSize)
773 pDmaChannel->bDesiredMode = 0;
775 pDmaChannel->bDesiredMode = 1;
778 if (pDmaChannel->bDesiredMode == 0) {
779 wCsr &= ~(MGC_M_TXCSR_AUTOSET
780 | MGC_M_TXCSR_DMAMODE);
781 wCsr |= (MGC_M_TXCSR_DMAENAB);
782 // against programming guide
784 wCsr |= (MGC_M_TXCSR_AUTOSET
785 | MGC_M_TXCSR_DMAENAB
786 | MGC_M_TXCSR_DMAMODE);
788 musb_writew(epio, MGC_O_HDRC_TXCSR, wCsr);
790 bDmaOk = pDmaController->channel_program(
791 pDmaChannel, wPacketSize,
792 pDmaChannel->bDesiredMode,
798 pDmaController->channel_release(pDmaChannel);
800 pEnd->tx_channel = NULL;
802 pEnd->rx_channel = NULL;
808 /* candidate for DMA */
809 if (is_cppi_enabled() && pDmaChannel) {
811 /* program endpoint CSRs first, then setup DMA.
812 * assume CPPI setup succeeds.
813 * defer enabling dma.
815 wCsr = musb_readw(epio, MGC_O_HDRC_TXCSR);
816 wCsr &= ~(MGC_M_TXCSR_AUTOSET
817 | MGC_M_TXCSR_DMAMODE
818 | MGC_M_TXCSR_DMAENAB);
819 wCsr |= MGC_M_TXCSR_MODE;
820 musb_writew(epio, MGC_O_HDRC_TXCSR,
821 wCsr | MGC_M_TXCSR_MODE);
823 pDmaChannel->dwActualLength = 0L;
824 qh->segsize = dwLength;
826 /* TX uses "rndis" mode automatically, but needs help
827 * to identify the zero-length-final-packet case.
829 bDmaOk = pDmaController->channel_program(
830 pDmaChannel, wPacketSize,
831 (pUrb->transfer_flags
839 pDmaController->channel_release(pDmaChannel);
840 pDmaChannel = pEnd->tx_channel = NULL;
842 /* REVISIT there's an error path here that
843 * needs handling: can't do dma, but
844 * there's no pio buffer address...
850 /* ASSERT: TXCSR_DMAENAB was already cleared */
852 /* PIO to load FIFO */
853 qh->segsize = wLoadCount;
854 musb_write_fifo(pEnd, wLoadCount, pBuffer);
855 wCsr = musb_readw(epio, MGC_O_HDRC_TXCSR);
856 wCsr &= ~(MGC_M_TXCSR_DMAENAB
857 | MGC_M_TXCSR_DMAMODE
858 | MGC_M_TXCSR_AUTOSET);
860 wCsr |= MGC_M_TXCSR_MODE;
863 musb_writew(epio, MGC_O_HDRC_TXCSR, wCsr);
866 /* re-enable interrupt */
867 musb_writew(pBase, MGC_O_HDRC_INTRTXE, wIntrTxE);
873 if (pEnd->rx_reinit) {
874 musb_rx_reinit(pThis, qh, pEnd);
876 /* init new state: toggle and NYET, maybe DMA later */
877 if (usb_gettoggle(pUrb->dev, qh->epnum, 0))
878 csr = MGC_M_RXCSR_H_WR_DATATOGGLE
879 | MGC_M_RXCSR_H_DATATOGGLE;
882 if (qh->type == USB_ENDPOINT_XFER_INT)
883 csr |= MGC_M_RXCSR_DISNYET;
886 csr = musb_readw(pEnd->regs, MGC_O_HDRC_RXCSR);
888 if (csr & (MGC_M_RXCSR_RXPKTRDY
889 | MGC_M_RXCSR_DMAENAB
890 | MGC_M_RXCSR_H_REQPKT))
891 ERR("broken !rx_reinit, ep%d csr %04x\n",
892 pEnd->bLocalEnd, csr);
894 /* scrub any stale state, leaving toggle alone */
895 csr &= MGC_M_RXCSR_DISNYET;
898 /* kick things off */
900 if (is_cppi_enabled()) {
901 /* candidate for DMA */
903 pDmaChannel->dwActualLength = 0L;
904 qh->segsize = dwLength;
906 /* AUTOREQ is in a DMA register */
907 musb_writew(pEnd->regs, MGC_O_HDRC_RXCSR, csr);
908 csr = musb_readw(pEnd->regs,
911 /* unless caller treats short rx transfers as
912 * errors, we dare not queue multiple transfers.
914 bDmaOk = pDmaController->channel_program(
915 pDmaChannel, wPacketSize,
916 !(pUrb->transfer_flags
921 pDmaController->channel_release(
923 pDmaChannel = pEnd->rx_channel = NULL;
925 csr |= MGC_M_RXCSR_DMAENAB;
929 csr |= MGC_M_RXCSR_H_REQPKT;
930 DBG(7, "RXCSR%d := %04x\n", bEnd, csr);
931 musb_writew(pEnd->regs, MGC_O_HDRC_RXCSR, csr);
932 csr = musb_readw(pEnd->regs, MGC_O_HDRC_RXCSR);
938 * Service the default endpoint (ep0) as host.
939 * Return TRUE until it's time to start the status stage.
941 static int musb_h_ep0_continue(struct musb *pThis,
942 u16 wCount, struct urb *pUrb)
945 u8 *pFifoDest = NULL;
947 struct musb_hw_ep *pEnd = pThis->control_ep;
948 struct musb_qh *qh = pEnd->in_qh;
949 struct usb_ctrlrequest *pRequest;
951 switch (pThis->bEnd0Stage) {
953 pFifoDest = pUrb->transfer_buffer + pUrb->actual_length;
954 wFifoCount = min(wCount, ((u16) (pUrb->transfer_buffer_length
955 - pUrb->actual_length)));
956 if (wFifoCount < wCount)
957 pUrb->status = -EOVERFLOW;
959 musb_read_fifo(pEnd, wFifoCount, pFifoDest);
961 pUrb->actual_length += wFifoCount;
962 if (wCount < qh->maxpacket) {
963 /* always terminate on short read; it's
964 * rarely reported as an error.
966 } else if (pUrb->actual_length <
967 pUrb->transfer_buffer_length)
971 pRequest = (struct usb_ctrlrequest *) pUrb->setup_packet;
973 if (!pRequest->wLength) {
974 DBG(4, "start no-DATA\n");
976 } else if (pRequest->bRequestType & USB_DIR_IN) {
977 DBG(4, "start IN-DATA\n");
978 pThis->bEnd0Stage = MGC_END0_IN;
982 DBG(4, "start OUT-DATA\n");
983 pThis->bEnd0Stage = MGC_END0_OUT;
988 wFifoCount = min(qh->maxpacket, ((u16)
989 (pUrb->transfer_buffer_length
990 - pUrb->actual_length)));
993 pFifoDest = (u8 *) (pUrb->transfer_buffer
994 + pUrb->actual_length);
995 DBG(3, "Sending %d bytes to %p\n",
996 wFifoCount, pFifoDest);
997 musb_write_fifo(pEnd, wFifoCount, pFifoDest);
999 pUrb->actual_length += wFifoCount;
1004 ERR("bogus ep0 stage %d\n", pThis->bEnd0Stage);
1012 * Handle default endpoint interrupt as host. Only called in IRQ time
1013 * from the LinuxIsr() interrupt service routine.
1015 * called with controller irqlocked
1017 irqreturn_t musb_h_ep0_irq(struct musb *pThis)
1020 u16 wCsrVal, wCount;
1022 void __iomem *pBase = pThis->pRegs;
1023 struct musb_hw_ep *pEnd = pThis->control_ep;
1024 void __iomem *epio = pEnd->regs;
1025 struct musb_qh *qh = pEnd->in_qh;
1026 u8 bComplete = FALSE;
1027 irqreturn_t retval = IRQ_NONE;
1029 /* ep0 only has one queue, "in" */
1030 pUrb = next_urb(qh);
1032 MGC_SelectEnd(pBase, 0);
1033 wCsrVal = musb_readw(epio, MGC_O_HDRC_CSR0);
1034 wCount = (wCsrVal & MGC_M_CSR0_RXPKTRDY)
1035 ? musb_readb(epio, MGC_O_HDRC_COUNT0)
1038 DBG(4, "<== csr0 %04x, qh %p, count %d, urb %p, stage %d\n",
1039 wCsrVal, qh, wCount, pUrb, pThis->bEnd0Stage);
1041 /* if we just did status stage, we are done */
1042 if (MGC_END0_STATUS == pThis->bEnd0Stage) {
1043 retval = IRQ_HANDLED;
1047 /* prepare status */
1048 if (wCsrVal & MGC_M_CSR0_H_RXSTALL) {
1049 DBG(6, "STALLING ENDPOINT\n");
1052 } else if (wCsrVal & MGC_M_CSR0_H_ERROR) {
1053 DBG(2, "no response, csr0 %04x\n", wCsrVal);
1056 } else if (wCsrVal & MGC_M_CSR0_H_NAKTIMEOUT) {
1057 DBG(2, "control NAK timeout\n");
1059 /* NOTE: this code path would be a good place to PAUSE a
1060 * control transfer, if another one is queued, so that
1061 * ep0 is more likely to stay busy.
1063 * if (qh->ring.next != &musb->control), then
1064 * we have a candidate... NAKing is *NOT* an error
1066 musb_writew(epio, MGC_O_HDRC_CSR0, 0);
1067 retval = IRQ_HANDLED;
1071 DBG(6, "aborting\n");
1072 retval = IRQ_HANDLED;
1074 pUrb->status = status;
1077 /* use the proper sequence to abort the transfer */
1078 if (wCsrVal & MGC_M_CSR0_H_REQPKT) {
1079 wCsrVal &= ~MGC_M_CSR0_H_REQPKT;
1080 musb_writew(epio, MGC_O_HDRC_CSR0, wCsrVal);
1081 wCsrVal &= ~MGC_M_CSR0_H_NAKTIMEOUT;
1082 musb_writew(epio, MGC_O_HDRC_CSR0, wCsrVal);
1084 wCsrVal |= MGC_M_CSR0_FLUSHFIFO;
1085 musb_writew(epio, MGC_O_HDRC_CSR0, wCsrVal);
1086 musb_writew(epio, MGC_O_HDRC_CSR0, wCsrVal);
1087 wCsrVal &= ~MGC_M_CSR0_H_NAKTIMEOUT;
1088 musb_writew(epio, MGC_O_HDRC_CSR0, wCsrVal);
1091 musb_writeb(epio, MGC_O_HDRC_NAKLIMIT0, 0);
1094 musb_writew(epio, MGC_O_HDRC_CSR0, 0);
1097 if (unlikely(!pUrb)) {
1098 /* stop endpoint since we have no place for its data, this
1099 * SHOULD NEVER HAPPEN! */
1100 ERR("no URB for end 0\n");
1102 musb_writew(epio, MGC_O_HDRC_CSR0, MGC_M_CSR0_FLUSHFIFO);
1103 musb_writew(epio, MGC_O_HDRC_CSR0, MGC_M_CSR0_FLUSHFIFO);
1104 musb_writew(epio, MGC_O_HDRC_CSR0, 0);
1110 /* call common logic and prepare response */
1111 if (musb_h_ep0_continue(pThis, wCount, pUrb)) {
1112 /* more packets required */
1113 wCsrVal = (MGC_END0_IN == pThis->bEnd0Stage)
1114 ? MGC_M_CSR0_H_REQPKT : MGC_M_CSR0_TXPKTRDY;
1116 /* data transfer complete; perform status phase */
1117 if (usb_pipeout(pUrb->pipe)
1118 || !pUrb->transfer_buffer_length)
1119 wCsrVal = MGC_M_CSR0_H_STATUSPKT
1120 | MGC_M_CSR0_H_REQPKT;
1122 wCsrVal = MGC_M_CSR0_H_STATUSPKT
1123 | MGC_M_CSR0_TXPKTRDY;
1125 /* flag status stage */
1126 pThis->bEnd0Stage = MGC_END0_STATUS;
1128 DBG(5, "ep0 STATUS, csr %04x\n", wCsrVal);
1131 musb_writew(epio, MGC_O_HDRC_CSR0, wCsrVal);
1132 retval = IRQ_HANDLED;
1134 pThis->bEnd0Stage = MGC_END0_IDLE;
1136 /* call completion handler if done */
1138 musb_advance_schedule(pThis, pUrb, pEnd, 1);
1144 #ifdef CONFIG_USB_INVENTRA_DMA
1146 /* Host side TX (OUT) using Mentor DMA works as follows:
1148 - if queue was empty, Program Endpoint
1149 - ... which starts DMA to fifo in mode 1 or 0
1151 DMA Isr (transfer complete) -> TxAvail()
1152 - Stop DMA (~DmaEnab) (<--- Alert ... currently happens
1153 only in musb_cleanup_urb)
1154 - TxPktRdy has to be set in mode 0 or for
1155 short packets in mode 1.
1160 /* Service a Tx-Available or dma completion irq for the endpoint */
1161 void musb_host_tx(struct musb *pThis, u8 bEnd)
1169 struct musb_hw_ep *pEnd = pThis->aLocalEnd + bEnd;
1170 void __iomem *epio = pEnd->regs;
1171 struct musb_qh *qh = pEnd->out_qh;
1173 void __iomem *pBase = pThis->pRegs;
1174 struct dma_channel *dma;
1176 pUrb = next_urb(qh);
1178 MGC_SelectEnd(pBase, bEnd);
1179 wTxCsrVal = musb_readw(epio, MGC_O_HDRC_TXCSR);
1181 /* with CPPI, DMA sometimes triggers "extra" irqs */
1183 DBG(4, "extra TX%d ready, csr %04x\n", bEnd, wTxCsrVal);
1188 dma = is_dma_capable() ? pEnd->tx_channel : NULL;
1189 DBG(4, "OUT/TX%d end, csr %04x%s\n", bEnd, wTxCsrVal,
1190 dma ? ", dma" : "");
1192 /* check for errors */
1193 if (wTxCsrVal & MGC_M_TXCSR_H_RXSTALL) {
1194 /* dma was disabled, fifo flushed */
1195 DBG(3, "TX end %d stall\n", bEnd);
1197 /* stall; record URB status */
1200 } else if (wTxCsrVal & MGC_M_TXCSR_H_ERROR) {
1201 /* (NON-ISO) dma was disabled, fifo flushed */
1202 DBG(3, "TX 3strikes on ep=%d\n", bEnd);
1204 status = -ETIMEDOUT;
1206 } else if (wTxCsrVal & MGC_M_TXCSR_H_NAKTIMEOUT) {
1207 DBG(6, "TX end=%d device not responding\n", bEnd);
1209 /* NOTE: this code path would be a good place to PAUSE a
1210 * transfer, if there's some other (nonperiodic) tx urb
1211 * that could use this fifo. (dma complicates it...)
1213 * if (bulk && qh->ring.next != &musb->out_bulk), then
1214 * we have a candidate... NAKing is *NOT* an error
1216 MGC_SelectEnd(pBase, bEnd);
1217 musb_writew(epio, MGC_O_HDRC_CSR0,
1218 MGC_M_TXCSR_H_WZC_BITS
1219 | MGC_M_TXCSR_TXPKTRDY);
1224 if (dma_channel_status(dma) == MGC_DMA_STATUS_BUSY) {
1225 dma->bStatus = MGC_DMA_STATUS_CORE_ABORT;
1226 (void) pThis->pDmaController->channel_abort(dma);
1229 /* do the proper sequence to abort the transfer in the
1230 * usb core; the dma engine should already be stopped.
1233 if (wTxCsrVal & MGC_M_TXCSR_FIFONOTEMPTY)
1234 wTxCsrVal |= MGC_M_TXCSR_FLUSHFIFO;
1235 wTxCsrVal &= ~(MGC_M_TXCSR_FIFONOTEMPTY
1236 | MGC_M_TXCSR_AUTOSET
1237 | MGC_M_TXCSR_DMAENAB
1238 | MGC_M_TXCSR_H_ERROR
1239 | MGC_M_TXCSR_H_RXSTALL
1240 | MGC_M_TXCSR_H_NAKTIMEOUT
1243 MGC_SelectEnd(pBase, bEnd);
1244 musb_writew(epio, MGC_O_HDRC_TXCSR, wTxCsrVal);
1245 /* REVISIT may need to clear FLUSHFIFO ... */
1246 musb_writew(epio, MGC_O_HDRC_TXCSR, wTxCsrVal);
1247 musb_writeb(epio, MGC_O_HDRC_TXINTERVAL, 0);
1252 /* second cppi case */
1253 if (dma_channel_status(dma) == MGC_DMA_STATUS_BUSY) {
1254 DBG(4, "extra TX%d ready, csr %04x\n", bEnd, wTxCsrVal);
1259 /* REVISIT this looks wrong... */
1260 if (!status || dma || usb_pipeisoc(nPipe)) {
1262 #ifdef CONFIG_USB_INVENTRA_DMA
1263 /* mode 0 or last short packet)
1264 * REVISIT how about ZLP?
1266 if ((dma->bDesiredMode == 0)
1267 || (dma->dwActualLength
1268 & (qh->maxpacket - 1))) {
1269 /* Send out the packet first ... */
1270 MGC_SelectEnd(pBase, bEnd);
1271 musb_writew(epio, MGC_O_HDRC_TXCSR,
1272 MGC_M_TXCSR_TXPKTRDY);
1276 wLength = dma->dwActualLength;
1278 wLength = qh->segsize;
1279 qh->offset += wLength;
1281 if (usb_pipeisoc(nPipe)) {
1282 struct usb_iso_packet_descriptor *d;
1284 d = pUrb->iso_frame_desc + qh->iso_idx;
1285 d->actual_length = qh->segsize;
1286 if (++qh->iso_idx >= pUrb->number_of_packets) {
1290 pBuffer = pUrb->transfer_buffer + d->offset;
1291 wLength = d->length;
1296 /* see if we need to send more data, or ZLP */
1297 if (qh->segsize < qh->maxpacket)
1299 else if (qh->offset == pUrb->transfer_buffer_length
1300 && !(pUrb-> transfer_flags
1304 pBuffer = pUrb->transfer_buffer
1306 wLength = pUrb->transfer_buffer_length
1312 /* urb->status != -EINPROGRESS means request has been faulted,
1313 * so we must abort this transfer after cleanup
1315 if (pUrb->status != -EINPROGRESS) {
1318 status = pUrb->status;
1323 pUrb->status = status;
1324 pUrb->actual_length = qh->offset;
1325 musb_advance_schedule(pThis, pUrb, pEnd, USB_DIR_OUT);
1327 } else if (!(wTxCsrVal & MGC_M_TXCSR_DMAENAB)) {
1328 // WARN_ON(!pBuffer);
1330 /* REVISIT: some docs say that when pEnd->tx_double_buffered,
1331 * (and presumably, fifo is not half-full) we should write TWO
1332 * packets before updating TXCSR ... other docs disagree ...
1334 /* PIO: start next packet in this URB */
1335 wLength = min(qh->maxpacket, (u16) wLength);
1336 musb_write_fifo(pEnd, wLength, pBuffer);
1337 qh->segsize = wLength;
1339 MGC_SelectEnd(pBase, bEnd);
1340 musb_writew(epio, MGC_O_HDRC_TXCSR,
1341 MGC_M_TXCSR_H_WZC_BITS | MGC_M_TXCSR_TXPKTRDY);
1343 DBG(1, "not complete, but dma enabled?\n");
1350 #ifdef CONFIG_USB_INVENTRA_DMA
1352 /* Host side RX (IN) using Mentor DMA works as follows:
1354 - if queue was empty, ProgramEndpoint
1355 - first IN token is sent out (by setting ReqPkt)
1356 LinuxIsr -> RxReady()
1357 /\ => first packet is received
1358 | - Set in mode 0 (DmaEnab, ~ReqPkt)
1359 | -> DMA Isr (transfer complete) -> RxReady()
1360 | - Ack receive (~RxPktRdy), turn off DMA (~DmaEnab)
1361 | - if urb not complete, send next IN token (ReqPkt)
1362 | | else complete urb.
1364 ---------------------------
1366 * Nuances of mode 1:
1367 * For short packets, no ack (+RxPktRdy) is sent automatically
1368 * (even if AutoClear is ON)
1369 * For full packets, ack (~RxPktRdy) and next IN token (+ReqPkt) is sent
1370 * automatically => major problem, as collecting the next packet becomes
1371 * difficult. Hence mode 1 is not used.
1374 * All we care about at this driver level is that
1375 * (a) all URBs terminate with REQPKT cleared and fifo(s) empty;
1376 * (b) termination conditions are: short RX, or buffer full;
1377 * (c) fault modes include
1378 * - iff URB_SHORT_NOT_OK, short RX status is -EREMOTEIO.
1379 * (and that endpoint's dma queue stops immediately)
1380 * - overflow (full, PLUS more bytes in the terminal packet)
1382 * So for example, usb-storage sets URB_SHORT_NOT_OK, and would
1383 * thus be a great candidate for using mode 1 ... for all but the
1384 * last packet of one URB's transfer.
1390 * Service an RX interrupt for the given IN endpoint; docs cover bulk, iso,
1391 * and high-bandwidth IN transfer cases.
1393 void musb_host_rx(struct musb *pThis, u8 bEnd)
1396 struct musb_hw_ep *pEnd = pThis->aLocalEnd + bEnd;
1397 void __iomem *epio = pEnd->regs;
1398 struct musb_qh *qh = pEnd->in_qh;
1400 void __iomem *pBase = pThis->pRegs;
1402 u16 wRxCsrVal, wVal;
1403 u8 bIsochError = FALSE;
1406 struct dma_channel *dma;
1408 MGC_SelectEnd(pBase, bEnd);
1410 pUrb = next_urb(qh);
1411 dma = is_dma_capable() ? pEnd->rx_channel : NULL;
1415 wVal = wRxCsrVal = musb_readw(epio, MGC_O_HDRC_RXCSR);
1417 if (unlikely(!pUrb)) {
1418 /* REVISIT -- THIS SHOULD NEVER HAPPEN ... but, at least
1419 * usbtest #11 (unlinks) triggers it regularly, sometimes
1420 * with fifo full. (Only with DMA??)
1422 DBG(3, "BOGUS RX%d ready, csr %04x, count %d\n", bEnd, wVal,
1423 musb_readw(epio, MGC_O_HDRC_RXCOUNT));
1424 musb_h_flush_rxfifo(pEnd, MGC_M_RXCSR_CLRDATATOG);
1430 DBG(5, "<== hw %d rxcsr %04x, urb actual %d (+dma %zd)\n",
1431 bEnd, wRxCsrVal, pUrb->actual_length,
1432 dma ? dma->dwActualLength : 0);
1434 /* check for errors, concurrent stall & unlink is not really
1436 if (wRxCsrVal & MGC_M_RXCSR_H_RXSTALL) {
1437 DBG(3, "RX end %d STALL\n", bEnd);
1439 /* stall; record URB status */
1442 } else if (wRxCsrVal & MGC_M_RXCSR_H_ERROR) {
1443 DBG(3, "end %d RX proto error\n", bEnd);
1446 musb_writeb(epio, MGC_O_HDRC_RXINTERVAL, 0);
1448 } else if (wRxCsrVal & MGC_M_RXCSR_DATAERROR) {
1450 if (USB_ENDPOINT_XFER_ISOC != qh->type) {
1451 /* NOTE this code path would be a good place to PAUSE a
1452 * transfer, if there's some other (nonperiodic) rx urb
1453 * that could use this fifo. (dma complicates it...)
1455 * if (bulk && qh->ring.next != &musb->in_bulk), then
1456 * we have a candidate... NAKing is *NOT* an error
1458 DBG(6, "RX end %d NAK timeout\n", bEnd);
1459 MGC_SelectEnd(pBase, bEnd);
1460 musb_writew(epio, MGC_O_HDRC_RXCSR,
1461 MGC_M_RXCSR_H_WZC_BITS
1462 | MGC_M_RXCSR_H_REQPKT);
1466 DBG(4, "RX end %d ISO data error\n", bEnd);
1467 /* packet error reported later */
1472 /* faults abort the transfer */
1474 /* clean up dma and collect transfer count */
1475 if (dma_channel_status(dma) == MGC_DMA_STATUS_BUSY) {
1476 dma->bStatus = MGC_DMA_STATUS_CORE_ABORT;
1477 (void) pThis->pDmaController->channel_abort(dma);
1478 xfer_len = dma->dwActualLength;
1480 musb_h_flush_rxfifo(pEnd, 0);
1481 musb_writeb(epio, MGC_O_HDRC_RXINTERVAL, 0);
1486 if (unlikely(dma_channel_status(dma) == MGC_DMA_STATUS_BUSY)) {
1487 /* SHOULD NEVER HAPPEN ... but at least DaVinci has done it */
1488 ERR("RX%d dma busy, csr %04x\n", bEnd, wRxCsrVal);
1492 /* thorough shutdown for now ... given more precise fault handling
1493 * and better queueing support, we might keep a DMA pipeline going
1494 * while processing this irq for earlier completions.
1497 /* FIXME this is _way_ too much in-line logic for Mentor DMA */
1499 #ifndef CONFIG_USB_INVENTRA_DMA
1500 if (wRxCsrVal & MGC_M_RXCSR_H_REQPKT) {
1501 /* REVISIT this happened for a while on some short reads...
1502 * the cleanup still needs investigation... looks bad...
1503 * and also duplicates dma cleanup code above ... plus,
1504 * shouldn't this be the "half full" double buffer case?
1506 if (dma_channel_status(dma) == MGC_DMA_STATUS_BUSY) {
1507 dma->bStatus = MGC_DMA_STATUS_CORE_ABORT;
1508 (void) pThis->pDmaController->channel_abort(dma);
1509 xfer_len = dma->dwActualLength;
1513 DBG(2, "RXCSR%d %04x, reqpkt, len %zd%s\n", bEnd, wRxCsrVal,
1514 xfer_len, dma ? ", dma" : "");
1515 wRxCsrVal &= ~MGC_M_RXCSR_H_REQPKT;
1517 MGC_SelectEnd(pBase, bEnd);
1518 musb_writew(epio, MGC_O_HDRC_RXCSR,
1519 MGC_M_RXCSR_H_WZC_BITS | wRxCsrVal);
1522 if (dma && (wRxCsrVal & MGC_M_RXCSR_DMAENAB)) {
1523 xfer_len = dma->dwActualLength;
1525 wVal &= ~(MGC_M_RXCSR_DMAENAB
1526 | MGC_M_RXCSR_H_AUTOREQ
1527 | MGC_M_RXCSR_AUTOCLEAR
1528 | MGC_M_RXCSR_RXPKTRDY);
1529 musb_writew(pEnd->regs, MGC_O_HDRC_RXCSR, wVal);
1531 #ifdef CONFIG_USB_INVENTRA_DMA
1532 pUrb->actual_length += xfer_len;
1533 qh->offset += xfer_len;
1535 /* bDone if pUrb buffer is full or short packet is recd */
1536 bDone = (pUrb->actual_length >= pUrb->transfer_buffer_length)
1537 || (dma->dwActualLength & (qh->maxpacket - 1));
1539 /* send IN token for next packet, without AUTOREQ */
1541 wVal |= MGC_M_RXCSR_H_REQPKT;
1542 musb_writew(epio, MGC_O_HDRC_RXCSR,
1543 MGC_M_RXCSR_H_WZC_BITS | wVal);
1546 DBG(4, "ep %d dma %s, rxcsr %04x, rxcount %d\n", bEnd,
1547 bDone ? "off" : "reset",
1548 musb_readw(epio, MGC_O_HDRC_RXCSR),
1549 musb_readw(epio, MGC_O_HDRC_RXCOUNT));
1553 } else if (pUrb->status == -EINPROGRESS) {
1554 /* if no errors, be sure a packet is ready for unloading */
1555 if (unlikely(!(wRxCsrVal & MGC_M_RXCSR_RXPKTRDY))) {
1557 ERR("Rx interrupt with no errors or packet!\n");
1559 // FIXME this is another "SHOULD NEVER HAPPEN"
1562 /* do the proper sequence to abort the transfer */
1563 MGC_SelectEnd(pBase, bEnd);
1564 wVal &= ~MGC_M_RXCSR_H_REQPKT;
1565 musb_writew(epio, MGC_O_HDRC_RXCSR, wVal);
1569 /* we are expecting IN packets */
1570 #ifdef CONFIG_USB_INVENTRA_DMA
1572 struct dma_controller *c;
1576 wRxCount = musb_readw(epio, MGC_O_HDRC_RXCOUNT);
1578 DBG(2, "RX%d count %d, buffer 0x%x len %d/%d\n",
1581 + pUrb->actual_length,
1583 pUrb->transfer_buffer_length);
1585 c = pThis->pDmaController;
1587 dma->bDesiredMode = 0;
1589 /* because of the issue below, mode 1 will
1590 * only rarely behave with correct semantics.
1592 if ((pUrb->transfer_flags &
1594 && (pUrb->transfer_buffer_length -
1595 pUrb->actual_length)
1597 dma->bDesiredMode = 1;
1600 /* Disadvantage of using mode 1:
1601 * It's basically usable only for mass storage class; essentially all
1602 * other protocols also terminate transfers on short packets.
1605 * An extra IN token is sent at the end of the transfer (due to AUTOREQ)
1606 * If you try to use mode 1 for (transfer_buffer_length - 512), and try
1607 * to use the extra IN token to grab the last packet using mode 0, then
1608 * the problem is that you cannot be sure when the device will send the
1609 * last packet and RxPktRdy set. Sometimes the packet is recd too soon
1610 * such that it gets lost when RxCSR is re-set at the end of the mode 1
1611 * transfer, while sometimes it is recd just a little late so that if you
1612 * try to configure for mode 0 soon after the mode 1 transfer is
1613 * completed, you will find rxcount 0. Okay, so you might think why not
1614 * wait for an interrupt when the pkt is recd. Well, you won't get any!
1617 wVal = musb_readw(epio, MGC_O_HDRC_RXCSR);
1618 wVal &= ~MGC_M_RXCSR_H_REQPKT;
1620 if (dma->bDesiredMode == 0)
1621 wVal &= ~MGC_M_RXCSR_H_AUTOREQ;
1623 wVal |= MGC_M_RXCSR_H_AUTOREQ;
1624 wVal |= MGC_M_RXCSR_AUTOCLEAR | MGC_M_RXCSR_DMAENAB;
1626 musb_writew(epio, MGC_O_HDRC_RXCSR,
1627 MGC_M_RXCSR_H_WZC_BITS | wVal);
1629 /* REVISIT if when actual_length != 0,
1630 * transfer_buffer_length needs to be
1633 status = c->channel_program(
1637 + pUrb->actual_length,
1638 (dma->bDesiredMode == 0)
1640 : pUrb->transfer_buffer_length);
1643 c->channel_release(dma);
1644 dma = pEnd->rx_channel = NULL;
1645 /* REVISIT reset CSR */
1648 #endif /* Mentor DMA */
1651 bDone = musb_host_packet_rx(pThis, pUrb,
1653 DBG(6, "read %spacket\n", bDone ? "last " : "");
1658 pUrb->actual_length += xfer_len;
1659 qh->offset += xfer_len;
1661 if (pUrb->status == -EINPROGRESS)
1662 pUrb->status = status;
1663 musb_advance_schedule(pThis, pUrb, pEnd, USB_DIR_IN);
1667 /* schedule nodes correspond to peripheral endpoints, like an OHCI QH.
1668 * the software schedule associates multiple such nodes with a given
1669 * host side hardware endpoint + direction; scheduling may activate
1670 * that hardware endpoint.
1672 static int musb_schedule(
1680 struct musb_hw_ep *hw_ep = NULL;
1681 struct list_head *head = NULL;
1683 /* use fixed hardware for control and bulk */
1685 case USB_ENDPOINT_XFER_CONTROL:
1686 head = &musb->control;
1687 hw_ep = musb->control_ep;
1689 case USB_ENDPOINT_XFER_BULK:
1690 hw_ep = musb->bulk_ep;
1692 head = &musb->in_bulk;
1694 head = &musb->out_bulk;
1698 idle = list_empty(head);
1699 list_add_tail(&qh->ring, head);
1703 /* else, periodic transfers get muxed to other endpoints */
1705 /* FIXME this doesn't consider direction, so it can only
1706 * work for one half of the endpoint hardware, and assumes
1707 * the previous cases handled all non-shared endpoints...
1710 /* we know this qh hasn't been scheduled, so all we need to do
1711 * is choose which hardware endpoint to put it on ...
1713 * REVISIT what we really want here is a regular schedule tree
1714 * like e.g. OHCI uses, but for now musb->periodic is just an
1715 * array of the _single_ logical endpoint associated with a
1716 * given physical one (identity mapping logical->physical).
1718 * that simplistic approach makes TT scheduling a lot simpler;
1719 * there is none, and thus none of its complexity...
1724 for (nEnd = 1; nEnd < musb->bEndCount; nEnd++) {
1727 if (musb->periodic[nEnd])
1729 hw_ep = &musb->aLocalEnd[nEnd];
1730 if (hw_ep == musb->bulk_ep)
1734 diff = hw_ep->wMaxPacketSizeRx - qh->maxpacket;
1736 diff = hw_ep->wMaxPacketSizeTx - qh->maxpacket;
1738 if (diff > 0 && wBestDiff > diff) {
1747 hw_ep = musb->aLocalEnd + nBestEnd;
1748 musb->periodic[nBestEnd] = qh;
1749 DBG(4, "qh %p periodic slot %d\n", qh, nBestEnd);
1752 qh->hep->hcpriv = qh;
1754 musb_start_urb(musb, is_in, qh);
1758 static int musb_urb_enqueue(
1759 struct usb_hcd *hcd,
1760 struct usb_host_endpoint *hep,
1764 unsigned long flags;
1765 struct musb *musb = hcd_to_musb(hcd);
1766 struct musb_qh *qh = hep->hcpriv;
1767 struct usb_endpoint_descriptor *epd = &hep->desc;
1772 /* host role must be active */
1773 if (!is_host_active(musb) || !musb->is_active)
1776 /* DMA mapping was already done, if needed, and this urb is on
1777 * hep->urb_list ... so there's little to do unless hep wasn't
1778 * yet scheduled onto a live qh.
1780 * REVISIT best to keep hep->hcpriv valid until the endpoint gets
1781 * disabled, testing for empty qh->ring and avoiding qh setup costs
1782 * except for the first urb queued after a config change.
1789 /* Allocate and initialize qh, minimizing the work done each time
1790 * hw_ep gets reprogrammed, or with irqs blocked. Then schedule it.
1792 * REVISIT consider a dedicated qh kmem_cache, so it's harder
1793 * for bugs in other kernel code to break this driver...
1795 qh = kzalloc(sizeof *qh, mem_flags);
1801 INIT_LIST_HEAD(&qh->ring);
1804 qh->maxpacket = le16_to_cpu(epd->wMaxPacketSize);
1806 /* no high bandwidth support yet */
1807 if (qh->maxpacket & ~0x7ff) {
1812 qh->epnum = epd->bEndpointAddress & USB_ENDPOINT_NUMBER_MASK;
1813 qh->type = epd->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK;
1815 /* NOTE: urb->dev->devnum is wrong during SET_ADDRESS */
1816 qh->addr_reg = (u8) usb_pipedevice(urb->pipe);
1818 /* precompute rxtype/txtype/type0 register */
1819 type_reg = (qh->type << 4) | qh->epnum;
1820 switch (urb->dev->speed) {
1824 case USB_SPEED_FULL:
1830 qh->type_reg = type_reg;
1832 /* precompute rxinterval/txinterval register */
1833 interval = min((u8)16, epd->bInterval); /* log encoding */
1835 case USB_ENDPOINT_XFER_INT:
1836 /* fullspeed uses linear encoding */
1837 if (USB_SPEED_FULL == urb->dev->speed) {
1838 interval = epd->bInterval;
1843 case USB_ENDPOINT_XFER_ISOC:
1844 /* iso always uses log encoding */
1847 /* REVISIT we actually want to use NAK limits, hinting to the
1848 * transfer scheduling logic to try some other qh, e.g. try
1851 * interval = (USB_SPEED_HIGH == pUrb->dev->speed) ? 16 : 2;
1853 * The downside of disabling this is that transfer scheduling
1854 * gets VERY unfair for nonperiodic transfers; a misbehaving
1855 * peripheral could make that hurt. Or for reads, one that's
1856 * perfectly normal: network and other drivers keep reads
1857 * posted at all times, having one pending for a week should
1858 * be perfectly safe.
1860 * The upside of disabling it is avoidng transfer scheduling
1861 * code to put this aside for while.
1865 qh->intv_reg = interval;
1867 /* precompute addressing for external hub/tt ports */
1868 if (musb->bIsMultipoint) {
1869 struct usb_device *parent = urb->dev->parent;
1871 if (parent != hcd->self.root_hub) {
1872 qh->h_addr_reg = (u8) parent->devnum;
1874 /* set up tt info if needed */
1876 qh->h_port_reg = (u8) urb->dev->ttport;
1877 qh->h_addr_reg |= 0x80;
1882 /* invariant: hep->hcpriv is null OR the qh that's already scheduled.
1883 * until we get real dma queues (with an entry for each urb/buffer),
1884 * we only have work to do in the former case.
1886 spin_lock_irqsave(&musb->Lock, flags);
1888 /* some concurrent activity submitted another urb to hep...
1889 * odd, rare, error prone, but legal.
1894 status = musb_schedule(musb, qh,
1895 epd->bEndpointAddress & USB_ENDPOINT_DIR_MASK);
1899 /* FIXME set urb->start_frame for iso/intr, it's tested in
1900 * musb_start_urb(), but otherwise only konicawc cares ...
1903 spin_unlock_irqrestore(&musb->Lock, flags);
1913 * abort a transfer that's at the head of a hardware queue.
1914 * called with controller locked, irqs blocked
1915 * that hardware queue advances to the next transfer, unless prevented
1917 static int musb_cleanup_urb(struct urb *urb, struct musb_qh *qh, int is_in)
1919 struct musb_hw_ep *ep = qh->hw_ep;
1920 void __iomem *epio = ep->regs;
1921 unsigned hw_end = ep->bLocalEnd;
1922 void __iomem *regs = ep->musb->pRegs;
1926 MGC_SelectEnd(regs, hw_end);
1928 if (is_dma_capable()) {
1929 struct dma_channel *dma;
1931 dma = is_in ? ep->rx_channel : ep->tx_channel;
1933 status = ep->musb->pDmaController->channel_abort(dma);
1935 "abort %cX%d DMA for urb %p --> %d\n",
1936 is_in ? 'R' : 'T', ep->bLocalEnd,
1938 urb->actual_length += dma->dwActualLength;
1942 /* turn off DMA requests, discard state, stop polling ... */
1944 /* giveback saves bulk toggle */
1945 csr = musb_h_flush_rxfifo(ep, 0);
1947 /* REVISIT we still get an irq; should likely clear the
1948 * endpoint's irq status here to avoid bogus irqs.
1949 * clearing that status is platform-specific...
1953 csr = musb_readw(epio, MGC_O_HDRC_TXCSR);
1954 if (csr & MGC_M_TXCSR_FIFONOTEMPTY)
1955 csr |= MGC_M_TXCSR_FLUSHFIFO;
1956 csr &= ~( MGC_M_TXCSR_AUTOSET
1957 | MGC_M_TXCSR_DMAENAB
1958 | MGC_M_TXCSR_H_RXSTALL
1959 | MGC_M_TXCSR_H_NAKTIMEOUT
1960 | MGC_M_TXCSR_H_ERROR
1961 | MGC_M_TXCSR_FIFONOTEMPTY
1963 musb_writew(epio, MGC_O_HDRC_TXCSR, csr);
1964 /* REVISIT may need to clear FLUSHFIFO ... */
1965 musb_writew(epio, MGC_O_HDRC_TXCSR, csr);
1966 /* flush cpu writebuffer */
1967 csr = musb_readw(epio, MGC_O_HDRC_TXCSR);
1970 musb_advance_schedule(ep->musb, urb, ep, is_in);
1974 static int musb_urb_dequeue(struct usb_hcd *hcd, struct urb *urb)
1976 struct musb *musb = hcd_to_musb(hcd);
1978 struct list_head *sched;
1980 unsigned long flags;
1981 int status = -ENOENT;
1983 DBG(4, "urb=%p, dev%d ep%d%s\n", urb,
1984 usb_pipedevice(urb->pipe),
1985 usb_pipeendpoint(urb->pipe),
1986 usb_pipein(urb->pipe) ? "in" : "out");
1988 spin_lock_irqsave(&musb->Lock, flags);
1990 /* make sure the urb is still queued and not completed */
1991 spin_lock(&urb->lock);
1994 struct usb_host_endpoint *hep;
1997 list_for_each_entry(tmp, &hep->urb_list, urb_list) {
2004 spin_unlock(&urb->lock);
2008 /* Any URB not actively programmed into endpoint hardware can be
2009 * immediately given back. Such an URB must be at the head of its
2010 * endpoint queue, unless someday we get real DMA queues. And even
2011 * then, it might not be known to the hardware...
2013 * Otherwise abort current transfer, pending dma, etc.; urb->status
2014 * has already been updated. This is a synchronous abort; it'd be
2015 * OK to hold off until after some IRQ, though.
2017 if (!qh->is_ready || urb->urb_list.prev != &qh->hep->urb_list)
2018 status = -EINPROGRESS;
2021 case USB_ENDPOINT_XFER_CONTROL:
2022 sched = &musb->control;
2024 case USB_ENDPOINT_XFER_BULK:
2025 if (usb_pipein(urb->pipe))
2026 sched = &musb->in_bulk;
2028 sched = &musb->out_bulk;
2031 /* REVISIT when we get a schedule tree, periodic
2032 * transfers won't always be at the head of a
2033 * singleton queue...
2040 /* NOTE: qh is invalid unless !list_empty(&hep->urb_list) */
2041 if (status < 0 || (sched && qh != first_qh(sched))) {
2042 int ready = qh->is_ready;
2046 __musb_giveback(musb, urb, 0);
2047 qh->is_ready = ready;
2049 status = musb_cleanup_urb(urb, qh, urb->pipe & USB_DIR_IN);
2051 spin_unlock_irqrestore(&musb->Lock, flags);
2055 /* disable an endpoint */
2057 musb_h_disable(struct usb_hcd *hcd, struct usb_host_endpoint *hep)
2059 u8 epnum = hep->desc.bEndpointAddress;
2060 unsigned long flags;
2061 struct musb *musb = hcd_to_musb(hcd);
2062 u8 is_in = epnum & USB_DIR_IN;
2063 struct musb_qh *qh = hep->hcpriv;
2064 struct urb *urb, *tmp;
2065 struct list_head *sched;
2070 spin_lock_irqsave(&musb->Lock, flags);
2073 case USB_ENDPOINT_XFER_CONTROL:
2074 sched = &musb->control;
2076 case USB_ENDPOINT_XFER_BULK:
2078 sched = &musb->in_bulk;
2080 sched = &musb->out_bulk;
2083 /* REVISIT when we get a schedule tree, periodic transfers
2084 * won't always be at the head of a singleton queue...
2090 /* NOTE: qh is invalid unless !list_empty(&hep->urb_list) */
2092 /* kick first urb off the hardware, if needed */
2094 if (!sched || qh == first_qh(sched)) {
2097 /* make software (then hardware) stop ASAP */
2098 spin_lock(&urb->lock);
2099 if (urb->status == -EINPROGRESS)
2100 urb->status = -ESHUTDOWN;
2101 spin_unlock(&urb->lock);
2104 musb_cleanup_urb(urb, qh, urb->pipe & USB_DIR_IN);
2108 /* then just nuke all the others */
2109 list_for_each_entry_safe_from(urb, tmp, &hep->urb_list, urb_list)
2110 musb_giveback(qh, urb, -ESHUTDOWN);
2112 spin_unlock_irqrestore(&musb->Lock, flags);
2115 static int musb_h_get_frame_number(struct usb_hcd *hcd)
2117 struct musb *musb = hcd_to_musb(hcd);
2119 return musb_readw(musb->pRegs, MGC_O_HDRC_FRAME);
2122 static int musb_h_start(struct usb_hcd *hcd)
2124 struct musb *musb = hcd_to_musb(hcd);
2126 /* NOTE: musb_start() is called when the hub driver turns
2127 * on port power, or when (OTG) peripheral starts.
2129 hcd->state = HC_STATE_RUNNING;
2130 musb->port1_status = 0;
2134 static void musb_h_stop(struct usb_hcd *hcd)
2136 musb_stop(hcd_to_musb(hcd));
2137 hcd->state = HC_STATE_HALT;
2140 static int musb_bus_suspend(struct usb_hcd *hcd)
2142 struct musb *musb = hcd_to_musb(hcd);
2144 if (is_host_active(musb) && musb->is_active)
2150 static int musb_bus_resume(struct usb_hcd *hcd)
2152 /* resuming child port does the work */
2156 const struct hc_driver musb_hc_driver = {
2157 .description = "musb-hcd",
2158 .product_desc = "MUSB HDRC host driver",
2159 .hcd_priv_size = sizeof (struct musb),
2160 .flags = HCD_USB2 | HCD_MEMORY,
2162 /* not using irq handler or reset hooks from usbcore, since
2163 * those must be shared with peripheral code for OTG configs
2166 .start = musb_h_start,
2167 .stop = musb_h_stop,
2169 .get_frame_number = musb_h_get_frame_number,
2171 .urb_enqueue = musb_urb_enqueue,
2172 .urb_dequeue = musb_urb_dequeue,
2173 .endpoint_disable = musb_h_disable,
2175 .hub_status_data = musb_hub_status_data,
2176 .hub_control = musb_hub_control,
2177 .bus_suspend = musb_bus_suspend,
2178 .bus_resume = musb_bus_resume,
2179 // .start_port_reset = NULL,
2180 // .hub_irq_enable = NULL,