1 /******************************************************************
2 * Copyright 2005 Mentor Graphics Corporation
3 * Copyright (C) 2005-2007 by Texas Instruments
5 * This file is part of the Inventra Controller Driver for Linux.
7 * The Inventra Controller Driver for Linux is free software; you
8 * can redistribute it and/or modify it under the terms of the GNU
9 * General Public License version 2 as published by the Free Software
12 * The Inventra Controller Driver for Linux is distributed in
13 * the hope that it will be useful, but WITHOUT ANY WARRANTY;
14 * without even the implied warranty of MERCHANTABILITY or
15 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
16 * License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with The Inventra Controller Driver for Linux ; if not,
20 * write to the Free Software Foundation, Inc., 59 Temple Place,
21 * Suite 330, Boston, MA 02111-1307 USA
23 * ANY DOWNLOAD, USE, REPRODUCTION, MODIFICATION OR DISTRIBUTION
24 * OF THIS DRIVER INDICATES YOUR COMPLETE AND UNCONDITIONAL ACCEPTANCE
25 * OF THOSE TERMS.THIS DRIVER IS PROVIDED "AS IS" AND MENTOR GRAPHICS
26 * MAKES NO WARRANTIES, EXPRESS OR IMPLIED, RELATED TO THIS DRIVER.
27 * MENTOR GRAPHICS SPECIFICALLY DISCLAIMS ALL IMPLIED WARRANTIES
28 * OF MERCHANTABILITY; FITNESS FOR A PARTICULAR PURPOSE AND
29 * NON-INFRINGEMENT. MENTOR GRAPHICS DOES NOT PROVIDE SUPPORT
30 * SERVICES OR UPDATES FOR THIS DRIVER, EVEN IF YOU ARE A MENTOR
31 * GRAPHICS SUPPORT CUSTOMER.
32 ******************************************************************/
35 * Implementation for the DMA controller within the MUSBMHDRC.
38 #include <linux/device.h>
39 #include <linux/interrupt.h>
40 #include <linux/platform_device.h>
43 #if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3430)
47 #define MGC_O_HSDMA_BASE 0x200
48 #define MGC_O_HSDMA_INTR (MGC_O_HSDMA_BASE + 0)
49 #define MGC_O_HSDMA_CONTROL 0x4
50 #define MGC_O_HSDMA_ADDRESS 0x8
51 #define MGC_O_HSDMA_COUNT 0xc
53 #define MGC_HSDMA_CHANNEL_OFFSET(_bChannel, _bOffset) \
54 (MGC_O_HSDMA_BASE + (_bChannel << 4) + _bOffset)
56 /* control register (16-bit): */
57 #define MGC_S_HSDMA_ENABLE 0
58 #define MGC_S_HSDMA_TRANSMIT 1
59 #define MGC_S_HSDMA_MODE1 2
60 #define MGC_S_HSDMA_IRQENABLE 3
61 #define MGC_S_HSDMA_ENDPOINT 4
62 #define MGC_S_HSDMA_BUSERROR 8
63 #define MGC_S_HSDMA_BURSTMODE 9
64 #define MGC_M_HSDMA_BURSTMODE (3 << MGC_S_HSDMA_BURSTMODE)
65 #define MGC_HSDMA_BURSTMODE_UNSPEC 0
66 #define MGC_HSDMA_BURSTMODE_INCR4 1
67 #define MGC_HSDMA_BURSTMODE_INCR8 2
68 #define MGC_HSDMA_BURSTMODE_INCR16 3
70 #define MGC_HSDMA_CHANNELS 8
72 struct musb_dma_controller;
74 struct musb_dma_channel {
75 struct dma_channel Channel;
76 struct musb_dma_controller *pController;
85 struct musb_dma_controller {
86 struct dma_controller Controller;
87 struct musb_dma_channel aChannel[MGC_HSDMA_CHANNELS];
89 void __iomem *pCoreBase;
95 static int dma_controller_start(struct dma_controller *c)
101 static void dma_channel_release(struct dma_channel *pChannel);
103 static int dma_controller_stop(struct dma_controller *c)
105 struct musb_dma_controller *pController =
106 container_of(c, struct musb_dma_controller, Controller);
107 struct musb *pThis = (struct musb *) pController->pDmaPrivate;
108 struct dma_channel *pChannel;
111 if (pController->bmUsedChannels != 0) {
112 dev_err(pThis->controller,
113 "Stopping DMA controller while channel active\n");
115 for (bBit = 0; bBit < MGC_HSDMA_CHANNELS; bBit++) {
116 if (pController->bmUsedChannels & (1 << bBit)) {
117 pChannel = &(pController->aChannel[bBit].Channel);
118 dma_channel_release(pChannel);
120 if (!pController->bmUsedChannels)
128 static struct dma_channel* dma_channel_allocate(struct dma_controller *c,
129 struct musb_hw_ep *hw_ep, u8 bTransmit)
132 struct dma_channel *pChannel = NULL;
133 struct musb_dma_channel *pImplChannel = NULL;
134 struct musb_dma_controller *pController =
135 container_of(c, struct musb_dma_controller, Controller);
137 for (bBit = 0; bBit < MGC_HSDMA_CHANNELS; bBit++) {
138 if (!(pController->bmUsedChannels & (1 << bBit))) {
139 pController->bmUsedChannels |= (1 << bBit);
140 pImplChannel = &(pController->aChannel[bBit]);
141 pImplChannel->pController = pController;
142 pImplChannel->bIndex = bBit;
143 pImplChannel->bEnd = hw_ep->bLocalEnd;
144 pImplChannel->bTransmit = bTransmit;
145 pChannel = &(pImplChannel->Channel);
146 pChannel->pPrivateData = pImplChannel;
147 pChannel->bStatus = MGC_DMA_STATUS_FREE;
148 pChannel->dwMaxLength = 0x10000;
149 /* Tx => mode 1; Rx => mode 0 */
150 pChannel->bDesiredMode = bTransmit;
151 pChannel->dwActualLength = 0;
158 static void dma_channel_release(struct dma_channel *pChannel)
160 struct musb_dma_channel *pImplChannel =
161 (struct musb_dma_channel *) pChannel->pPrivateData;
163 pChannel->dwActualLength = 0;
164 pImplChannel->dwStartAddress = 0;
165 pImplChannel->dwCount = 0;
167 pImplChannel->pController->bmUsedChannels &=
168 ~(1 << pImplChannel->bIndex);
170 pChannel->bStatus = MGC_DMA_STATUS_UNKNOWN;
173 static void configure_channel(struct dma_channel *pChannel,
174 u16 wPacketSize, u8 bMode,
175 dma_addr_t dma_addr, u32 dwLength)
177 struct musb_dma_channel *pImplChannel =
178 (struct musb_dma_channel *) pChannel->pPrivateData;
179 struct musb_dma_controller *pController = pImplChannel->pController;
180 u8 *pBase = pController->pCoreBase;
181 u8 bChannel = pImplChannel->bIndex;
184 DBG(4, "%p, pkt_sz %d, addr 0x%x, len %d, mode %d\n",
185 pChannel, wPacketSize, dma_addr, dwLength, bMode);
188 wCsr |= 1 << MGC_S_HSDMA_MODE1;
189 if (dwLength < wPacketSize) {
192 if (wPacketSize >= 64) {
194 MGC_HSDMA_BURSTMODE_INCR16 << MGC_S_HSDMA_BURSTMODE;
195 } else if (wPacketSize >= 32) {
197 MGC_HSDMA_BURSTMODE_INCR8 << MGC_S_HSDMA_BURSTMODE;
198 } else if (wPacketSize >= 16) {
200 MGC_HSDMA_BURSTMODE_INCR4 << MGC_S_HSDMA_BURSTMODE;
204 wCsr |= (pImplChannel->bEnd << MGC_S_HSDMA_ENDPOINT)
205 | (1 << MGC_S_HSDMA_ENABLE)
206 | (1 << MGC_S_HSDMA_IRQENABLE)
207 | (pImplChannel->bTransmit ? (1 << MGC_S_HSDMA_TRANSMIT) : 0);
211 MGC_HSDMA_CHANNEL_OFFSET(bChannel, MGC_O_HSDMA_ADDRESS),
214 MGC_HSDMA_CHANNEL_OFFSET(bChannel, MGC_O_HSDMA_COUNT),
217 /* control (this should start things) */
219 MGC_HSDMA_CHANNEL_OFFSET(bChannel, MGC_O_HSDMA_CONTROL),
223 static int dma_channel_program(struct dma_channel * pChannel,
224 u16 wPacketSize, u8 bMode,
225 dma_addr_t dma_addr, u32 dwLength)
227 struct musb_dma_channel *pImplChannel =
228 (struct musb_dma_channel *) pChannel->pPrivateData;
230 DBG(2, "ep%d-%s pkt_sz %d, dma_addr 0x%x length %d, mode %d\n",
232 pImplChannel->bTransmit ? "Tx" : "Rx",
233 wPacketSize, dma_addr, dwLength, bMode);
235 BUG_ON(pChannel->bStatus == MGC_DMA_STATUS_UNKNOWN ||
236 pChannel->bStatus == MGC_DMA_STATUS_BUSY);
238 pChannel->dwActualLength = 0;
239 pImplChannel->dwStartAddress = dma_addr;
240 pImplChannel->dwCount = dwLength;
241 pImplChannel->wMaxPacketSize = wPacketSize;
242 pChannel->bStatus = MGC_DMA_STATUS_BUSY;
244 if ((bMode == 1) && (dwLength >= wPacketSize)) {
245 configure_channel(pChannel, wPacketSize, 1, dma_addr,
248 configure_channel(pChannel, wPacketSize, 0, dma_addr,
254 static int dma_channel_abort(struct dma_channel *pChannel)
256 struct musb_dma_channel *pImplChannel =
257 (struct musb_dma_channel *) pChannel->pPrivateData;
258 u8 bChannel = pImplChannel->bIndex;
259 u8 *pBase = pImplChannel->pController->pCoreBase;
262 if (pChannel->bStatus == MGC_DMA_STATUS_BUSY) {
263 if (pImplChannel->bTransmit) {
265 csr = musb_readw(pBase,
266 MGC_END_OFFSET(pImplChannel->bEnd,MGC_O_HDRC_TXCSR));
267 csr &= ~(MGC_M_TXCSR_AUTOSET |
268 MGC_M_TXCSR_DMAENAB |
269 MGC_M_TXCSR_DMAMODE);
271 MGC_END_OFFSET(pImplChannel->bEnd,MGC_O_HDRC_TXCSR),
275 csr = musb_readw(pBase,
276 MGC_END_OFFSET(pImplChannel->bEnd,MGC_O_HDRC_RXCSR));
277 csr &= ~(MGC_M_RXCSR_AUTOCLEAR |
278 MGC_M_RXCSR_DMAENAB |
279 MGC_M_RXCSR_DMAMODE);
281 MGC_END_OFFSET(pImplChannel->bEnd,MGC_O_HDRC_RXCSR),
286 MGC_HSDMA_CHANNEL_OFFSET(bChannel, MGC_O_HSDMA_CONTROL), 0);
288 MGC_HSDMA_CHANNEL_OFFSET(bChannel, MGC_O_HSDMA_ADDRESS), 0);
290 MGC_HSDMA_CHANNEL_OFFSET(bChannel, MGC_O_HSDMA_COUNT), 0);
292 pChannel->bStatus = MGC_DMA_STATUS_FREE;
297 static irqreturn_t dma_controller_irq(int irq, void *pPrivateData)
299 struct musb_dma_controller *pController =
300 (struct musb_dma_controller *)pPrivateData;
301 struct musb_dma_channel *pImplChannel;
302 u8 *pBase = pController->pCoreBase;
303 struct dma_channel *pChannel;
308 irqreturn_t retval = IRQ_NONE;
310 bIntr = musb_readb(pBase, MGC_O_HSDMA_INTR);
314 for (bChannel = 0; bChannel < MGC_HSDMA_CHANNELS; bChannel++) {
315 if (bIntr & (1 << bChannel)) {
316 pImplChannel = (struct musb_dma_channel *)
317 &(pController->aChannel[bChannel]);
318 pChannel = &pImplChannel->Channel;
320 wCsr = musb_readw(pBase,
321 MGC_HSDMA_CHANNEL_OFFSET(bChannel,
322 MGC_O_HSDMA_CONTROL));
324 if (wCsr & (1 << MGC_S_HSDMA_BUSERROR)) {
325 pImplChannel->Channel.bStatus =
326 MGC_DMA_STATUS_BUS_ABORT;
328 dwAddress = musb_readl(pBase,
329 MGC_HSDMA_CHANNEL_OFFSET(
331 MGC_O_HSDMA_ADDRESS));
332 pChannel->dwActualLength =
333 dwAddress - pImplChannel->dwStartAddress;
335 DBG(2, "ch %p, 0x%x -> 0x%x (%d / %d) %s\n",
336 pChannel, pImplChannel->dwStartAddress,
337 dwAddress, pChannel->dwActualLength,
338 pImplChannel->dwCount,
339 (pChannel->dwActualLength <
340 pImplChannel->dwCount) ?
341 "=> reconfig 0": "=> complete");
343 u8 devctl = musb_readb(pBase,
346 pChannel->bStatus = MGC_DMA_STATUS_FREE;
349 if ((devctl & MGC_M_DEVCTL_HM)
350 && (pImplChannel->bTransmit)
351 && ((pChannel->bDesiredMode == 0)
352 || (pChannel->dwActualLength &
353 (pImplChannel->wMaxPacketSize - 1)))
355 /* Send out the packet */
359 MGC_END_OFFSET(pImplChannel->bEnd,MGC_O_HDRC_TXCSR),
360 MGC_M_TXCSR_TXPKTRDY);
363 pController->pDmaPrivate,
365 pImplChannel->bTransmit);
369 retval = IRQ_HANDLED;
374 void dma_controller_destroy(struct dma_controller *c)
376 struct musb_dma_controller *pController =
377 (struct musb_dma_controller *) c->pPrivateData;
382 if (pController->irq)
383 free_irq(pController->irq, c);
386 c->pPrivateData = NULL;
389 struct dma_controller *__init
390 dma_controller_create(struct musb *pThis, void __iomem *pCoreBase)
392 struct musb_dma_controller *pController;
393 struct device *dev = pThis->controller;
394 struct platform_device *pdev = to_platform_device(dev);
395 int irq = platform_get_irq(pdev, 1);
398 dev_err(dev, "No DMA interrupt line!\n");
402 if (!(pController = kzalloc(sizeof(struct musb_dma_controller),
406 pController->bChannelCount = MGC_HSDMA_CHANNELS;
407 pController->pDmaPrivate = pThis;
408 pController->pCoreBase = pCoreBase;
410 pController->Controller.pPrivateData = pController;
411 pController->Controller.start = dma_controller_start;
412 pController->Controller.stop = dma_controller_stop;
413 pController->Controller.channel_alloc = dma_channel_allocate;
414 pController->Controller.channel_release = dma_channel_release;
415 pController->Controller.channel_program = dma_channel_program;
416 pController->Controller.channel_abort = dma_channel_abort;
418 if (request_irq(irq, dma_controller_irq, IRQF_DISABLED,
419 pThis->controller->bus_id, &pController->Controller)) {
420 dev_err(dev, "request_irq %d failed!\n", irq);
421 dma_controller_destroy(&pController->Controller);
425 pController->irq = irq;
427 return &pController->Controller;