1 /*****************************************************************
2 * Copyright 2005 Mentor Graphics Corporation
3 * Copyright (C) 2005-2006 by Texas Instruments
4 * Copyright (C) 2006 by Nokia Corporation
6 * This file is part of the Inventra Controller Driver for Linux.
8 * The Inventra Controller Driver for Linux is free software; you
9 * can redistribute it and/or modify it under the terms of the GNU
10 * General Public License version 2 as published by the Free Software
13 * The Inventra Controller Driver for Linux is distributed in
14 * the hope that it will be useful, but WITHOUT ANY WARRANTY;
15 * without even the implied warranty of MERCHANTABILITY or
16 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
17 * License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with The Inventra Controller Driver for Linux ; if not,
21 * write to the Free Software Foundation, Inc., 59 Temple Place,
22 * Suite 330, Boston, MA 02111-1307 USA
24 * ANY DOWNLOAD, USE, REPRODUCTION, MODIFICATION OR DISTRIBUTION
25 * OF THIS DRIVER INDICATES YOUR COMPLETE AND UNCONDITIONAL ACCEPTANCE
26 * OF THOSE TERMS.THIS DRIVER IS PROVIDED "AS IS" AND MENTOR GRAPHICS
27 * MAKES NO WARRANTIES, EXPRESS OR IMPLIED, RELATED TO THIS DRIVER.
28 * MENTOR GRAPHICS SPECIFICALLY DISCLAIMS ALL IMPLIED WARRANTIES
29 * OF MERCHANTABILITY; FITNESS FOR A PARTICULAR PURPOSE AND
30 * NON-INFRINGEMENT. MENTOR GRAPHICS DOES NOT PROVIDE SUPPORT
31 * SERVICES OR UPDATES FOR THIS DRIVER, EVEN IF YOU ARE A MENTOR
32 * GRAPHICS SUPPORT CUSTOMER.
33 ******************************************************************/
36 * Inventra (Multipoint) Dual-Role Controller Driver for Linux.
38 * This consists of a Host Controller Driver (HCD) and a peripheral
39 * controller driver implementing the "Gadget" API; OTG support is
40 * in the works. These are normal Linux-USB controller drivers which
41 * use IRQs and have no dedicated thread.
43 * This version of the driver has only been used with products from
44 * Texas Instruments. Those products integrate the Inventra logic
45 * with other DMA, IRQ, and bus modules, as well as other logic that
46 * needs to be reflected in this driver.
49 * NOTE: the original Mentor code here was pretty much a collection
50 * of mechanisms that don't seem to have been fully integrated/working
51 * for *any* Linux kernel version. This version aims at Linux 2.6.now,
52 * Key open issues include:
54 * - Lack of host-side transaction scheduling, for all transfer types.
55 * The hardware doesn't do it; instead, software must.
57 * This is not an issue for OTG devices that don't support external
58 * hubs, but for more "normal" USB hosts it's a user issue that the
59 * "multipoint" support doesn't scale in the expected ways. That
60 * includes DaVinci EVM in a common non-OTG mode.
62 * * Control and bulk use dedicated endpoints, and there's as
63 * yet no mechanism to either (a) reclaim the hardware when
64 * peripherals are NAKing, which gets complicated with bulk
65 * endpoints, or (b) use more than a single bulk endpoint in
68 * RESULT: one device may be perceived as blocking another one.
70 * * Interrupt and isochronous will dynamically allocate endpoint
71 * hardware, but (a) there's no record keeping for bandwidth;
72 * (b) in the common case that few endpoints are available, there
73 * is no mechanism to reuse endpoints to talk to multiple devices.
75 * RESULT: At one extreme, bandwidth can be overcommitted in
76 * some hardware configurations, no faults will be reported.
77 * At the other extreme, the bandwidth capabilities which do
78 * exist tend to be severely undercommitted. You can't yet hook
79 * up both a keyboard and a mouse to an external USB hub.
81 * * Host side doesn't understand that hardware endpoints have two
82 * directions, so it uses only half the resources available on
83 * chips like DaVinci or TUSB 6010.
85 * +++ PARTIALLY RESOLVED +++
87 * RESULT: On DaVinci (and TUSB 6010), only one external device may
88 * use periodic transfers, other than the hub used to connect it.
89 * (And if it were to understand, there would still be limitations
90 * because of the lack of periodic endpoint scheduling.)
92 * - Provides its own OTG bits. These are untested, and many of them
93 * seem to be superfluous code bloat given what usbcore does. (They
94 * have now been partially removed.)
98 * This gets many kinds of configuration information:
99 * - Kconfig for everything user-configurable
100 * - <asm/arch/hdrc_cnf.h> for SOC or family details
101 * - platform_device for addressing, irq, and platform_data
102 * - platform_data is mostly for board-specific informarion
104 * Most of the conditional compilation will (someday) vanish.
107 #include <linux/config.h>
108 #include <linux/module.h>
109 #include <linux/pci.h>
110 #include <linux/kernel.h>
111 #include <linux/sched.h>
112 #include <linux/slab.h>
113 #include <linux/init.h>
114 #include <linux/list.h>
115 #include <linux/kobject.h>
116 #include <linux/platform_device.h>
117 #include <linux/clk.h>
122 #include <asm/arch/hardware.h>
123 #include <asm/arch/memory.h>
124 #include <asm/mach-types.h>
127 #include "musbdefs.h"
128 // #ifdef CONFIG_USB_MUSB_HDRC_HCD
129 #define VBUSERR_RETRY_COUNT 2 /* is this too few? */
133 #ifdef CONFIG_ARCH_DAVINCI
140 unsigned debug = MUSB_DEBUG;
141 module_param(debug, uint, 0);
142 MODULE_PARM_DESC(debug, "initial debug message level");
144 #define MUSB_VERSION_SUFFIX "/dbg"
147 #define DRIVER_AUTHOR "Mentor Graphics Corp. and Texas Instruments"
148 #define DRIVER_DESC "Inventra Dual-Role USB Controller Driver"
150 #define MUSB_VERSION_BASE "2.2a/db-0.5.1"
152 #ifndef MUSB_VERSION_SUFFIX
153 #define MUSB_VERSION_SUFFIX ""
155 #define MUSB_VERSION MUSB_VERSION_BASE MUSB_VERSION_SUFFIX
157 #define DRIVER_INFO DRIVER_DESC ", v" MUSB_VERSION
159 const char musb_driver_name[] = "musb_hdrc";
161 MODULE_DESCRIPTION(DRIVER_INFO);
162 MODULE_AUTHOR(DRIVER_AUTHOR);
163 MODULE_LICENSE("GPL");
165 /* time (millseconds) to wait before a restart */
166 #define MUSB_RESTART_TIME 5000
168 /* how many babbles to allow before giving up */
169 #define MUSB_MAX_BABBLE_COUNT 10
172 /*-------------------------------------------------------------------------*/
174 #ifdef CONFIG_USB_MUSB_OTG
176 /* For debugging/prototyping: allow disabling host side support on boards
177 * with Mini-AB (or Mini-A) connectors, making peripheral side support look
178 * like pure peripherals (not reporting OTG capabilities, and able to
179 * draw a full 100mA unit load).
183 module_param(musb_otg, bool, 0600);
184 MODULE_PARM_DESC(musb_otg, "enable/disable OTG capabilities");
187 static inline struct musb *dev_to_musb(struct device *dev)
189 #ifdef CONFIG_USB_MUSB_HDRC_HCD
190 /* usbcore insists dev->driver_data is a "struct hcd *" */
191 return hcd_to_musb(dev_get_drvdata(dev));
193 return dev_get_drvdata(dev);
197 static void otg_input_changed(struct musb * pThis, u8 devctl, u8 reset,
198 u8 connection, u8 suspend)
200 #ifdef CONFIG_USB_MUSB_OTG
201 struct otg_machine *otgm = &pThis->OtgMachine;
202 MGC_OtgMachineInputs Inputs;
204 /* reading suspend state from Power register does NOT work */
205 memset(&Inputs, 0, sizeof(Inputs));
207 Inputs.bSession = (devctl & MGC_M_DEVCTL_SESSION) ? TRUE : FALSE;
208 Inputs.bSuspend = suspend;
209 Inputs.bConnection = connection;
210 Inputs.bReset = reset;
211 Inputs.bConnectorId = (devctl & MGC_M_DEVCTL_BDEVICE) ? TRUE : FALSE;
213 MGC_OtgMachineInputsChanged(otgm, &Inputs);
217 static void otg_input_changed_X(struct musb * pThis, u8 bVbusError, u8 bConnect)
219 #ifdef CONFIG_USB_MUSB_OTG
220 MGC_OtgMachineInputs Inputs;
221 void __iomem *pBase = pThis->pRegs;
222 u8 devctl = musb_readb(pBase, MGC_O_HDRC_DEVCTL);
223 u8 power = musb_readb(pBase, MGC_O_HDRC_POWER);
225 DBG(2, "<== power %02x, devctl %02x%s%s\n", power, devctl,
226 bConnect ? ", bcon" : "",
227 bVbusError ? ", vbus_error" : "");
230 memset(&Inputs, 0, sizeof(Inputs));
231 Inputs.bSession = (devctl & MGC_M_DEVCTL_SESSION) ? TRUE : FALSE;
232 Inputs.bConnectorId = (devctl & MGC_M_DEVCTL_BDEVICE) ? TRUE : FALSE;
233 Inputs.bReset = (power & MGC_M_POWER_RESET) ? TRUE : FALSE;
234 Inputs.bConnection = bConnect;
235 Inputs.bVbusError = bVbusError;
236 Inputs.bSuspend = (power & MGC_M_POWER_SUSPENDM) ? TRUE : FALSE;
237 MGC_OtgMachineInputsChanged(&(pThis->OtgMachine), &Inputs);
238 #endif /* CONFIG_USB_MUSB_OTG */
242 /*-------------------------------------------------------------------------*/
244 #ifndef CONFIG_USB_TUSB6010
246 * Load an endpoint's FIFO
248 void musb_write_fifo(struct musb_hw_ep *hw_ep, u16 wCount, const u8 *pSource)
250 void __iomem *fifo = hw_ep->fifo;
252 prefetch((u8 *)pSource);
254 DBG(4, "%cX ep%d fifo %p count %d buf %p\n",
255 'T', hw_ep->bLocalEnd, fifo, wCount, pSource);
257 /* we can't assume unaligned reads work */
258 if (likely((0x01 & (unsigned long) pSource) == 0)) {
261 /* best case is 32bit-aligned source address */
262 if ((0x02 & (unsigned long) pSource) == 0) {
264 writesl(fifo, pSource + index, wCount >> 2);
265 index += wCount & ~0x03;
268 musb_writew(fifo, 0, *(u16*)&pSource[index]);
273 writesw(fifo, pSource + index, wCount >> 1);
274 index += wCount & ~0x01;
278 musb_writeb(fifo, 0, pSource[index]);
281 writesb(fifo, pSource, wCount);
286 * Unload an endpoint's FIFO
288 void musb_read_fifo(struct musb_hw_ep *hw_ep, u16 wCount, u8 *pDest)
290 void __iomem *fifo = hw_ep->fifo;
292 DBG(4, "%cX ep%d fifo %p count %d buf %p\n",
293 'R', hw_ep->bLocalEnd, fifo, wCount, pDest);
295 /* we can't assume unaligned writes work */
296 if (likely((0x01 & (unsigned long) pDest) == 0)) {
299 /* best case is 32bit-aligned destination address */
300 if ((0x02 & (unsigned long) pDest) == 0) {
302 readsl(fifo, pDest, wCount >> 2);
303 index = wCount & ~0x03;
306 *(u16*)&pDest[index] = musb_readw(fifo, 0);
311 readsw(fifo, pDest, wCount >> 1);
312 index = wCount & ~0x01;
316 pDest[index] = musb_readb(fifo, 0);
319 readsb(fifo, pDest, wCount);
323 #endif /* normal PIO */
326 /*-------------------------------------------------------------------------*/
328 /* for high speed test mode; see USB 2.0 spec 7.1.20 */
329 static const u8 musb_test_packet[53] = {
330 /* implicit SYNC then DATA0 to start */
333 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
335 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,
337 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0xee,
338 /* JJJJJJJKKKKKKK x8 */
339 0xfe, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
341 0x7f, 0xbf, 0xdf, 0xef, 0xf7, 0xfb, 0xfd,
342 /* JKKKKKKK x10, JK */
343 0xfc, 0x7e, 0xbf, 0xdf, 0xef, 0xf7, 0xfb, 0xfd, 0x7e
345 /* implicit CRC16 then EOP to end */
348 void musb_load_testpacket(struct musb *musb)
350 MGC_SelectEnd(musb->pRegs, 0);
351 musb_write_fifo(musb->control_ep,
352 sizeof(musb_test_packet), musb_test_packet);
353 musb_writew(musb->pRegs, MGC_O_HDRC_CSR0, MGC_M_CSR0_TXPKTRDY);
356 /*-------------------------------------------------------------------------*/
359 * Interrupt Service Routine to record USB "global" interrupts.
360 * Since these do not happen often and signify things of
361 * paramount importance, it seems OK to check them individually;
362 * the order of the tests is specified in the manual
364 * @param pThis instance pointer
365 * @param bIntrUSB register contents
370 #define STAGE0_MASK (MGC_M_INTR_RESUME | MGC_M_INTR_SESSREQ \
371 | MGC_M_INTR_VBUSERROR | MGC_M_INTR_CONNECT \
374 static irqreturn_t musb_stage0_irq(struct musb * pThis, u8 bIntrUSB,
377 irqreturn_t handled = IRQ_NONE;
378 #ifdef CONFIG_USB_MUSB_HDRC_HCD
379 void __iomem *pBase = pThis->pRegs;
382 DBG(3, "<== Power=%02x, DevCtl=%02x, bIntrUSB=0x%x\n", power, devctl,
385 /* in host mode when a device resume me (from power save)
386 * in device mode when the host resume me; it shold not change
389 if (bIntrUSB & MGC_M_INTR_RESUME) {
390 handled = IRQ_HANDLED;
392 pThis->is_active = 1;
394 if (devctl & MGC_M_DEVCTL_HM) {
395 #ifdef CONFIG_USB_MUSB_HDRC_HCD
396 /* REVISIT: this is where SRP kicks in, yes?
397 * host responsibility should be to CLEAR the
398 * resume signaling after 50 msec ...
400 MUSB_HST_MODE(pThis); /* unnecessary */
401 power &= ~MGC_M_POWER_SUSPENDM;
402 musb_writeb(pBase, MGC_O_HDRC_POWER,
403 power | MGC_M_POWER_RESUME);
405 /* should now be A_SUSPEND */
406 pThis->xceiv.state = OTG_STATE_A_HOST;
409 #ifdef CONFIG_USB_GADGET_MUSB_HDRC
410 MUSB_DEV_MODE(pThis); /* unnecessary */
412 musb_g_resume(pThis);
416 #ifdef CONFIG_USB_MUSB_HDRC_HCD
417 /* see manual for the order of the tests */
418 if (bIntrUSB & MGC_M_INTR_SESSREQ) {
419 DBG(1, "SESSION_REQUEST (%d)\n", pThis->xceiv.state);
421 /* IRQ arrives from ID pin sense or (later, if VBUS power
422 * is removed) SRP. responses are time critical:
423 * - turn on VBUS (with silicon-specific mechanism)
424 * - go through A_WAIT_VRISE
425 * - ... to A_WAIT_BCON.
426 * a_wait_vrise_tmout triggers VBUS_ERROR transitions
428 musb_writeb(pBase, MGC_O_HDRC_DEVCTL, MGC_M_DEVCTL_SESSION);
429 pThis->bEnd0Stage = MGC_END0_START;
430 pThis->xceiv.state = OTG_STATE_A_IDLE;
431 MUSB_HST_MODE(pThis);
432 musb_set_vbus(pThis, 1);
434 handled = IRQ_HANDLED;
436 #ifdef CONFIG_USB_MUSB_OTG
438 MGC_OtgMachineInputs Inputs;
439 memset(&Inputs, 0, sizeof(Inputs));
440 Inputs.bSession = TRUE;
441 Inputs.bConnectorId = FALSE;
442 Inputs.bReset = FALSE;
443 Inputs.bConnection = FALSE;
444 Inputs.bSuspend = FALSE;
445 MGC_OtgMachineInputsChanged(&(pThis->OtgMachine), &Inputs);
450 if (bIntrUSB & MGC_M_INTR_VBUSERROR) {
452 // MGC_OtgMachineInputsChanged(otgm, &Inputs);
453 // otg_input_changed_X(pThis, TRUE, TRUE);
454 // ... may need to abort otg timer ...
456 DBG(1, "VBUS_ERROR (%02x, %s), retry #%d\n", devctl,
458 switch (devctl & MGC_M_DEVCTL_VBUS) {
459 case 0 << MGC_S_DEVCTL_VBUS:
460 s = "<SessEnd"; break;
461 case 1 << MGC_S_DEVCTL_VBUS:
462 s = "<AValid"; break;
463 case 2 << MGC_S_DEVCTL_VBUS:
464 s = "<VBusValid"; break;
465 //case 3 << MGC_S_DEVCTL_VBUS:
469 pThis->vbuserr_retry);
471 /* go through A_WAIT_VFALL then start a new session */
472 musb_set_vbus(pThis, 0);
473 handled = IRQ_HANDLED;
475 pThis->vbuserr_retry = VBUSERR_RETRY_COUNT;
477 if (bIntrUSB & MGC_M_INTR_CONNECT) {
478 handled = IRQ_HANDLED;
479 pThis->is_active = 1;
480 set_bit(HCD_FLAG_SAW_IRQ, &musb_to_hcd(pThis)->flags);
482 pThis->bEnd0Stage = MGC_END0_START;
484 #ifdef CONFIG_USB_MUSB_OTG
485 /* flush endpoints when transitioning from Device Mode */
486 if (is_peripheral_active(pThis)) {
487 // REVISIT HNP; just force disconnect
489 pThis->bDelayPortPowerOff = FALSE;
491 pThis->port1_status &= ~(USB_PORT_STAT_LOW_SPEED
492 |USB_PORT_STAT_HIGH_SPEED
493 |USB_PORT_STAT_ENABLE
495 pThis->port1_status |= USB_PORT_STAT_CONNECTION
496 |(USB_PORT_STAT_C_CONNECTION << 16);
498 /* high vs full speed is just a guess until after reset */
499 if (devctl & MGC_M_DEVCTL_LSDEV)
500 pThis->port1_status |= USB_PORT_STAT_LOW_SPEED;
502 usb_hcd_poll_rh_status(musb_to_hcd(pThis));
504 MUSB_HST_MODE(pThis);
506 /* indicate new connection to OTG machine */
507 switch (pThis->xceiv.state) {
508 case OTG_STATE_B_WAIT_ACON:
509 pThis->xceiv.state = OTG_STATE_B_HOST;
512 pThis->xceiv.state = OTG_STATE_A_HOST;
515 DBG(1, "CONNECT (%s)\n", otg_state_string(pThis));
516 otg_input_changed(pThis, devctl, FALSE, TRUE, FALSE);
518 #endif /* CONFIG_USB_MUSB_HDRC_HCD */
520 /* saved one bit: bus reset and babble share the same bit;
521 * If I am host is a babble! i must be the only one allowed
522 * to reset the bus; when in otg mode it means that I have
523 * to switch to device
525 if (bIntrUSB & MGC_M_INTR_RESET) {
526 if (devctl & MGC_M_DEVCTL_HM) {
529 /* REVISIT it's unclear how to handle this. Mentor's
530 * code stopped the whole USB host, which is clearly
531 * very wrong. Docs say (15.1) that babble ends the
532 * current sesssion, so shutdown _with restart_ would
533 * be appropriate ... except that seems to be wrong,
534 * at least some lowspeed enumerations trigger the
535 * babbles without aborting the session!
537 * (A "babble" IRQ seems quite pointless...)
541 DBG(1, "BUS RESET\n");
545 /* reading state from Power register doesn't work */
546 otg_input_changed(pThis, devctl, TRUE, FALSE,
547 (power & MGC_M_POWER_SUSPENDM)
550 schedule_work(&pThis->irq_work);
553 handled = IRQ_HANDLED;
560 * Interrupt Service Routine to record USB "global" interrupts.
561 * Since these do not happen often and signify things of
562 * paramount importance, it seems OK to check them individually;
563 * the order of the tests is specified in the manual
565 * @param pThis instance pointer
566 * @param bIntrUSB register contents
570 static irqreturn_t musb_stage2_irq(struct musb * pThis, u8 bIntrUSB,
573 irqreturn_t handled = IRQ_NONE;
576 /* REVISIT ... this would be for multiplexing periodic endpoints, or
577 * supporting transfer phasing to prevent exceeding ISO bandwidth
578 * limits of a given frame or microframe.
580 * It's not needed for peripheral side, which dedicates endpoints;
581 * though it _might_ use SOF irqs for other purposes.
583 * And it's not currently needed for host side, which also dedicates
584 * endpoints, relies on TX/RX interval registers, and isn't claimed
585 * to support ISO transfers yet.
587 if (bIntrUSB & MGC_M_INTR_SOF) {
588 void __iomem *pBase = pThis->pRegs;
589 struct musb_hw_ep *ep;
593 DBG(6, "START_OF_FRAME\n");
594 handled = IRQ_HANDLED;
596 /* start any periodic Tx transfers waiting for current frame */
597 wFrame = musb_readw(pBase, MGC_O_HDRC_FRAME);
598 ep = pThis->aLocalEnd;
599 for (bEnd = 1; (bEnd < pThis->bEndCount)
600 && (pThis->wEndMask >= (1 << bEnd));
602 // FIXME handle framecounter wraps (12 bits)
603 // eliminate duplicated StartUrb logic
604 if (ep->dwWaitFrame >= wFrame) {
606 printk("SOF --> periodic TX%s on %d\n",
607 ep->tx_channel ? " DMA" : "",
610 musb_h_tx_start(pThis, bEnd);
612 cppi_hostdma_start(pThis, bEnd);
614 } /* end of for loop */
618 if ((bIntrUSB & MGC_M_INTR_DISCONNECT) && !pThis->bIgnoreDisconnect) {
619 DBG(1, "DISCONNECT as %s, devctl %02x\n",
620 MUSB_MODE(pThis), devctl);
621 handled = IRQ_HANDLED;
622 pThis->is_active = 0;
624 /* need to check it against pThis, because devctl is going
625 * to report ID low as soon as the device gets disconnected
627 if (is_host_active(pThis))
628 musb_root_disconnect(pThis);
630 musb_g_disconnect(pThis);
632 /* REVISIT all OTG state machine transitions */
633 otg_input_changed_X(pThis, FALSE, FALSE);
635 schedule_work(&pThis->irq_work);
638 if (bIntrUSB & MGC_M_INTR_SUSPEND) {
639 DBG(1, "SUSPEND, devctl %02x\n", devctl);
640 handled = IRQ_HANDLED;
642 /* peripheral suspend, may trigger HNP */
643 if (!(devctl & MGC_M_DEVCTL_HM)) {
644 musb_g_suspend(pThis);
645 pThis->is_active = is_otg_enabled(pThis)
646 && pThis->xceiv.gadget->b_hnp_enable;
647 otg_input_changed(pThis, devctl, FALSE, FALSE, TRUE);
649 pThis->is_active = 0;
655 /*-------------------------------------------------------------------------*/
658 * Program the HDRC to start (enable interrupts, dma, etc.).
660 void musb_start(struct musb *musb)
662 void __iomem *regs = musb->pRegs;
667 /* TODO: always set ISOUPDATE in POWER (periph mode) and leave it on! */
669 /* Set INT enable registers, enable interrupts */
670 musb_writew(regs, MGC_O_HDRC_INTRTXE, musb->wEndMask);
671 musb_writew(regs, MGC_O_HDRC_INTRRXE, musb->wEndMask & 0xfffe);
672 musb_writeb(regs, MGC_O_HDRC_INTRUSBE, 0xf7);
674 musb_writeb(regs, MGC_O_HDRC_TESTMODE, 0);
676 musb_platform_enable(musb);
678 /* enable high-speed/low-power and start session */
679 musb_writeb(regs, MGC_O_HDRC_POWER,
680 MGC_M_POWER_SOFTCONN | MGC_M_POWER_HSENAB);
683 switch (musb->board_mode) {
685 musb_set_vbus(musb, 1);
688 /* session started after:
689 * (a) ID-grounded irq, host mode;
690 * (b) vbus present/connect IRQ, peripheral mode;
691 * (c) peripheral initiates, using SRP
694 case MUSB_PERIPHERAL:
695 devctl = musb_readb(regs, MGC_O_HDRC_DEVCTL);
696 if ((devctl & MGC_M_DEVCTL_VBUS) == MGC_M_DEVCTL_VBUS)
698 musb_writeb(regs, MGC_O_HDRC_DEVCTL,
699 devctl & ~MGC_M_DEVCTL_SESSION);
705 static void musb_generic_disable(struct musb *pThis)
707 void __iomem *pBase = pThis->pRegs;
710 /* disable interrupts */
711 musb_writeb(pBase, MGC_O_HDRC_INTRUSBE, 0);
712 musb_writew(pBase, MGC_O_HDRC_INTRTX, 0);
713 musb_writew(pBase, MGC_O_HDRC_INTRRX, 0);
716 musb_writeb(pBase, MGC_O_HDRC_DEVCTL, 0);
718 /* flush pending interrupts */
719 temp = musb_readb(pBase, MGC_O_HDRC_INTRUSB);
720 temp = musb_readw(pBase, MGC_O_HDRC_INTRTX);
721 temp = musb_readw(pBase, MGC_O_HDRC_INTRRX);
726 * Make the HDRC stop (disable interrupts, etc.);
727 * reversible by musb_start
728 * called on gadget driver unregister
729 * with controller locked, irqs blocked
730 * acts as a NOP unless some role activated the hardware
732 void musb_stop(struct musb * pThis)
734 /* stop IRQs, timers, ... */
735 musb_platform_disable(pThis);
736 musb_generic_disable(pThis);
737 DBG(3, "HDRC disabled\n");
739 #ifdef CONFIG_USB_MUSB_OTG
740 if (is_otg_enabled(pThis))
741 MGC_OtgMachineDestroy(&pThis->OtgMachine);
745 * - mark host and/or peripheral drivers unusable/inactive
746 * - disable DMA (and enable it in HdrcStart)
747 * - make sure we can musb_start() after musb_stop(); with
748 * OTG mode, gadget driver module rmmod/modprobe cycles that
752 #ifdef CONFIG_USB_MUSB_HDRC_HCD
753 if (is_host_enabled(pThis)) {
754 /* REVISIT aren't there some paths where this is wrong? */
755 dev_warn(pThis->controller, "%s, root hub still active\n",
761 static void musb_shutdown(struct platform_device *pdev)
763 struct musb *musb = dev_to_musb(&pdev->dev);
766 spin_lock_irqsave(&musb->Lock, flags);
767 musb_platform_disable(musb);
768 musb_generic_disable(musb);
769 spin_unlock_irqrestore(&musb->Lock, flags);
771 /* FIXME power down */
775 /*-------------------------------------------------------------------------*/
778 * The silicon either has hard-wired endpoint configurations, or else
779 * "dynamic fifo" sizing. The driver has support for both, though at this
780 * writing only the dynamic sizing is very well tested. We use normal
781 * idioms to so both modes are compile-tested, but dead code elimination
782 * leaves only the relevant one in the object file.
784 * We don't currently use dynamic fifo setup capability to do anything
785 * more than selecting one of a bunch of predefined configurations.
787 #ifdef MUSB_C_DYNFIFO_DEF
788 #define can_dynfifo() 1
790 #define can_dynfifo() 0
793 #ifdef CONFIG_USB_TUSB6010
794 static ushort __devinitdata fifo_mode = 4;
796 static ushort __devinitdata fifo_mode = 2;
799 /* "modprobe ... fifo_mode=1" etc */
800 module_param(fifo_mode, ushort, 0);
801 MODULE_PARM_DESC(fifo_mode, "initial endpoint configuration");
804 #define DYN_FIFO_SIZE (1<<(MUSB_C_RAM_BITS+2))
806 enum fifo_style { FIFO_RXTX, FIFO_TX, FIFO_RX } __attribute__ ((packed));
807 enum buf_mode { BUF_SINGLE, BUF_DOUBLE } __attribute__ ((packed));
811 enum fifo_style style;
817 * tables defining fifo_mode values. define more if you like.
818 * for host side, make sure both halves of ep1 are set up.
821 /* mode 0 - fits in 2KB */
822 static const struct fifo_cfg __devinitdata mode_0_cfg[] = {
823 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
824 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
825 { .hw_ep_num = 2, .style = FIFO_RXTX, .maxpacket = 512, },
826 { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
827 { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
830 /* mode 1 - fits in 4KB */
831 static const struct fifo_cfg __devinitdata mode_1_cfg[] = {
832 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, .mode = BUF_DOUBLE, },
833 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, .mode = BUF_DOUBLE, },
834 { .hw_ep_num = 2, .style = FIFO_RXTX, .maxpacket = 512, .mode = BUF_DOUBLE, },
835 { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
836 { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
839 /* mode 2 - fits in 4KB */
840 static const struct fifo_cfg __devinitdata mode_2_cfg[] = {
841 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
842 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
843 { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
844 { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
845 { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
846 { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
849 /* mode 3 - fits in 4KB */
850 static const struct fifo_cfg __devinitdata mode_3_cfg[] = {
851 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, .mode = BUF_DOUBLE, },
852 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, .mode = BUF_DOUBLE, },
853 { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
854 { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
855 { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
856 { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
859 /* mode 4 - fits in 16KB */
860 static const struct fifo_cfg __devinitdata mode_4_cfg[] = {
861 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
862 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
863 { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
864 { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
865 { .hw_ep_num = 3, .style = FIFO_TX, .maxpacket = 512, },
866 { .hw_ep_num = 3, .style = FIFO_RX, .maxpacket = 512, },
867 { .hw_ep_num = 4, .style = FIFO_TX, .maxpacket = 512, },
868 { .hw_ep_num = 4, .style = FIFO_RX, .maxpacket = 512, },
869 { .hw_ep_num = 5, .style = FIFO_TX, .maxpacket = 512, },
870 { .hw_ep_num = 5, .style = FIFO_RX, .maxpacket = 512, },
871 { .hw_ep_num = 6, .style = FIFO_TX, .maxpacket = 512, },
872 { .hw_ep_num = 6, .style = FIFO_RX, .maxpacket = 512, },
873 { .hw_ep_num = 7, .style = FIFO_TX, .maxpacket = 512, },
874 { .hw_ep_num = 7, .style = FIFO_RX, .maxpacket = 512, },
875 { .hw_ep_num = 8, .style = FIFO_TX, .maxpacket = 512, },
876 { .hw_ep_num = 8, .style = FIFO_RX, .maxpacket = 512, },
877 { .hw_ep_num = 9, .style = FIFO_TX, .maxpacket = 512, },
878 { .hw_ep_num = 9, .style = FIFO_RX, .maxpacket = 512, },
879 { .hw_ep_num = 10, .style = FIFO_TX, .maxpacket = 512, },
880 { .hw_ep_num = 10, .style = FIFO_RX, .maxpacket = 512, },
881 { .hw_ep_num = 11, .style = FIFO_TX, .maxpacket = 512, },
882 { .hw_ep_num = 11, .style = FIFO_RX, .maxpacket = 512, },
883 { .hw_ep_num = 12, .style = FIFO_TX, .maxpacket = 512, },
884 { .hw_ep_num = 12, .style = FIFO_RX, .maxpacket = 512, },
885 { .hw_ep_num = 13, .style = FIFO_TX, .maxpacket = 512, },
886 { .hw_ep_num = 13, .style = FIFO_RX, .maxpacket = 512, },
887 { .hw_ep_num = 14, .style = FIFO_RXTX, .maxpacket = 1024, },
888 { .hw_ep_num = 15, .style = FIFO_RXTX, .maxpacket = 1024, },
893 * configure a fifo; for non-shared endpoints, this may be called
894 * once for a tx fifo and once for an rx fifo.
896 * returns negative errno or offset for next fifo.
899 fifo_setup(struct musb *musb, struct musb_hw_ep *hw_ep,
900 const struct fifo_cfg *cfg, u16 offset)
902 void __iomem *mbase = musb->pRegs;
904 u16 maxpacket = cfg->maxpacket;
905 u16 c_off = offset >> 3;
908 /* expect hw_ep has already been zero-initialized */
910 size = ffs(max(maxpacket, (u16) 8)) - 1;
911 maxpacket = 1 << size;
914 if (cfg->mode == BUF_DOUBLE) {
915 if ((offset + (maxpacket << 1)) > DYN_FIFO_SIZE)
917 c_size |= MGC_M_FIFOSZ_DPB;
919 if ((offset + maxpacket) > DYN_FIFO_SIZE)
923 /* configure the FIFO */
924 musb_writeb(mbase, MGC_O_HDRC_INDEX, hw_ep->bLocalEnd);
926 #ifdef CONFIG_USB_MUSB_HDRC_HCD
927 /* EP0 reserved endpoint for control, bidirectional;
928 * EP1 reserved for bulk, two unidirection halves.
930 if (hw_ep->bLocalEnd == 1)
931 musb->bulk_ep = hw_ep;
932 /* REVISIT error check: be sure ep0 can both rx and tx ... */
934 switch (cfg->style) {
936 musb_writeb(mbase, MGC_O_HDRC_TXFIFOSZ, c_size);
937 musb_writew(mbase, MGC_O_HDRC_TXFIFOADD, c_off);
938 hw_ep->tx_double_buffered = !!(c_size & MGC_M_FIFOSZ_DPB);
939 hw_ep->wMaxPacketSizeTx = maxpacket;
942 musb_writeb(mbase, MGC_O_HDRC_RXFIFOSZ, c_size);
943 musb_writew(mbase, MGC_O_HDRC_RXFIFOADD, c_off);
944 hw_ep->rx_double_buffered = !!(c_size & MGC_M_FIFOSZ_DPB);
945 hw_ep->wMaxPacketSizeRx = maxpacket;
948 musb_writeb(mbase, MGC_O_HDRC_TXFIFOSZ, c_size);
949 musb_writew(mbase, MGC_O_HDRC_TXFIFOADD, c_off);
950 hw_ep->rx_double_buffered = !!(c_size & MGC_M_FIFOSZ_DPB);
951 hw_ep->wMaxPacketSizeRx = maxpacket;
953 musb_writeb(mbase, MGC_O_HDRC_RXFIFOSZ, c_size);
954 musb_writew(mbase, MGC_O_HDRC_RXFIFOADD, c_off);
955 hw_ep->tx_double_buffered = hw_ep->rx_double_buffered;
956 hw_ep->wMaxPacketSizeTx = maxpacket;
958 hw_ep->bIsSharedFifo = TRUE;
962 /* NOTE rx and tx endpoint irqs aren't managed separately,
963 * which happens to be ok
965 musb->wEndMask |= (1 << hw_ep->bLocalEnd);
967 return offset + (maxpacket << ((c_size & MGC_M_FIFOSZ_DPB) ? 1 : 0));
970 static const struct fifo_cfg __devinitdata ep0_cfg = {
971 .style = FIFO_RXTX, .maxpacket = 64,
974 static int __devinit ep_config_from_table(struct musb *musb)
976 const struct fifo_cfg *cfg;
979 struct musb_hw_ep *hw_ep = musb->aLocalEnd;
987 n = ARRAY_SIZE(mode_0_cfg);
991 n = ARRAY_SIZE(mode_1_cfg);
995 n = ARRAY_SIZE(mode_2_cfg);
999 n = ARRAY_SIZE(mode_3_cfg);
1003 n = ARRAY_SIZE(mode_4_cfg);
1007 printk(KERN_DEBUG "%s: setup fifo_mode %d\n",
1008 musb_driver_name, fifo_mode);
1011 offset = fifo_setup(musb, hw_ep, &ep0_cfg, 0);
1012 // assert(offset > 0)
1014 for (i = 0; i < n; i++) {
1015 u8 epn = cfg->hw_ep_num;
1017 if (epn >= MUSB_C_NUM_EPS) {
1018 pr_debug( "%s: invalid ep %d\n",
1019 musb_driver_name, epn);
1022 offset = fifo_setup(musb, hw_ep + epn, cfg++, offset);
1024 pr_debug( "%s: mem overrun, ep %d\n",
1025 musb_driver_name, epn);
1029 musb->bEndCount = max(epn, musb->bEndCount);
1032 printk(KERN_DEBUG "%s: %d/%d max ep, %d/%d memory\n",
1034 n + 1, MUSB_C_NUM_EPS * 2 - 1,
1035 offset, DYN_FIFO_SIZE);
1037 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1038 if (!musb->bulk_ep) {
1039 pr_debug( "%s: missing bulk\n", musb_driver_name);
1049 * ep_config_from_hw - when MUSB_C_DYNFIFO_DEF is false
1050 * @param pThis the controller
1052 static int __devinit ep_config_from_hw(struct musb *musb)
1055 struct musb_hw_ep *pEnd;
1056 void *pBase = musb->pRegs;
1058 DBG(2, "<== static silicon ep config\n");
1060 /* FIXME pick up ep0 maxpacket size */
1062 for (bEnd = 1; bEnd < MUSB_C_NUM_EPS; bEnd++) {
1063 MGC_SelectEnd(pBase, bEnd);
1064 pEnd = musb->aLocalEnd + bEnd;
1066 /* read from core using indexed model */
1067 reg = musb_readb(pEnd->regs, 0x10 + MGC_O_HDRC_FIFOSIZE);
1069 /* 0's returned when no more endpoints */
1073 musb->wEndMask |= (1 << bEnd);
1075 pEnd->wMaxPacketSizeTx = 1 << (reg & 0x0f);
1077 /* shared TX/RX FIFO? */
1078 if ((reg & 0xf0) == 0xf0) {
1079 pEnd->wMaxPacketSizeRx = pEnd->wMaxPacketSizeTx;
1080 pEnd->bIsSharedFifo = TRUE;
1083 pEnd->wMaxPacketSizeRx = 1 << ((reg & 0xf0) >> 4);
1084 pEnd->bIsSharedFifo = FALSE;
1087 /* FIXME set up pEnd->{rx,tx}_double_buffered */
1089 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1090 /* pick an RX/TX endpoint for bulk */
1091 if (pEnd->wMaxPacketSizeTx < 512
1092 || pEnd->wMaxPacketSizeRx < 512)
1095 /* REVISIT: this algorithm is lazy, we should at least
1096 * try to pick a double buffered endpoint.
1100 musb->bulk_ep = pEnd;
1104 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1105 if (!musb->bulk_ep) {
1106 pr_debug( "%s: missing bulk\n", musb_driver_name);
1114 enum { MUSB_CONTROLLER_MHDRC, MUSB_CONTROLLER_HDRC, };
1116 /* Initialize MUSB (M)HDRC part of the USB hardware subsystem;
1117 * configure endpoints, or take their config from silicon
1119 static int __devinit musb_core_init(u16 wType, struct musb *pThis)
1126 u16 wRelease, wRelMajor, wRelMinor;
1127 char aInfo[78], aRevision[32], aDate[12];
1128 void __iomem *pBase = pThis->pRegs;
1132 /* log core options (read using indexed model) */
1133 MGC_SelectEnd(pBase, 0);
1134 reg = musb_readb(pBase, 0x10 + MGC_O_HDRC_CONFIGDATA);
1136 strcpy(aInfo, (reg & MGC_M_CONFIGDATA_UTMIDW) ? "UTMI-16" : "UTMI-8");
1137 if (reg & MGC_M_CONFIGDATA_DYNFIFO) {
1138 strcat(aInfo, ", dyn FIFOs");
1140 if (reg & MGC_M_CONFIGDATA_MPRXE) {
1141 strcat(aInfo, ", bulk combine");
1143 pThis->bBulkCombine = TRUE;
1145 strcat(aInfo, " (X)"); /* no driver support */
1148 if (reg & MGC_M_CONFIGDATA_MPTXE) {
1149 strcat(aInfo, ", bulk split");
1151 pThis->bBulkSplit = TRUE;
1153 strcat(aInfo, " (X)"); /* no driver support */
1156 if (reg & MGC_M_CONFIGDATA_HBRXE) {
1157 strcat(aInfo, ", HB-ISO Rx");
1158 strcat(aInfo, " (X)"); /* no driver support */
1160 if (reg & MGC_M_CONFIGDATA_HBTXE) {
1161 strcat(aInfo, ", HB-ISO Tx");
1162 strcat(aInfo, " (X)"); /* no driver support */
1164 if (reg & MGC_M_CONFIGDATA_SOFTCONE) {
1165 strcat(aInfo, ", SoftConn");
1168 printk(KERN_DEBUG "%s: ConfigData=0x%02x (%s)\n",
1169 musb_driver_name, reg, aInfo);
1172 dwData = musb_readl(pBase, 0x404);
1173 sprintf(aDate, "%04d-%02x-%02x", (dwData & 0xffff),
1174 (dwData >> 16) & 0xff, (dwData >> 24) & 0xff);
1175 /* FIXME ID2 and ID3 are unused */
1176 dwData = musb_readl(pBase, 0x408);
1177 printk("ID2=%lx\n", (long unsigned)dwData);
1178 dwData = musb_readl(pBase, 0x40c);
1179 printk("ID3=%lx\n", (long unsigned)dwData);
1180 reg = musb_readb(pBase, 0x400);
1181 wType = ('M' == reg) ? MUSB_CONTROLLER_MHDRC : MUSB_CONTROLLER_HDRC;
1185 if (MUSB_CONTROLLER_MHDRC == wType) {
1186 pThis->bIsMultipoint = 1;
1189 pThis->bIsMultipoint = 0;
1191 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1192 #ifndef CONFIG_USB_OTG_BLACKLIST_HUB
1194 "%s: kernel must blacklist external hubs\n",
1200 /* log release info */
1201 wRelease = musb_readw(pBase, MGC_O_HDRC_HWVERS);
1202 wRelMajor = (wRelease >> 10) & 0x1f;
1203 wRelMinor = wRelease & 0x3ff;
1204 snprintf(aRevision, 32, "%d.%d%s", wRelMajor,
1205 wRelMinor, (wRelease & 0x8000) ? "RC" : "");
1206 printk(KERN_DEBUG "%s: %sHDRC RTL version %s %s\n",
1207 musb_driver_name, type, aRevision, aDate);
1210 pThis->aLocalEnd[0].wMaxPacketSizeTx = MGC_END0_FIFOSIZE;
1211 pThis->aLocalEnd[0].wMaxPacketSizeRx = MGC_END0_FIFOSIZE;
1213 /* discover endpoint configuration */
1214 pThis->bEndCount = 1;
1215 pThis->wEndMask = 1;
1217 if (reg & MGC_M_CONFIGDATA_DYNFIFO) {
1219 status = ep_config_from_table(pThis);
1221 ERR("reconfigure software for Dynamic FIFOs\n");
1226 status = ep_config_from_hw(pThis);
1228 ERR("reconfigure software for static FIFOs\n");
1236 /* finish init, and print endpoint config */
1237 for (i = 0; i < pThis->bEndCount; i++) {
1238 struct musb_hw_ep *hw_ep = pThis->aLocalEnd + i;
1240 hw_ep->fifo = MUSB_FIFO_OFFSET(i) + pBase;
1241 #ifdef CONFIG_USB_TUSB6010
1242 hw_ep->fifo_async = pThis->async + 0x400 + MUSB_FIFO_OFFSET(i);
1243 hw_ep->fifo_sync = pThis->sync + 0x400 + MUSB_FIFO_OFFSET(i);
1245 hw_ep->conf = pBase - 0x400 + TUSB_EP0_CONF;
1247 hw_ep->conf = pBase + 0x400 + (((i - 1) & 0xf) << 2);
1250 hw_ep->regs = MGC_END_OFFSET(i, 0) + pBase;
1251 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1252 hw_ep->target_regs = MGC_BUSCTL_OFFSET(i, 0) + pBase;
1253 hw_ep->rx_reinit = 1;
1254 hw_ep->tx_reinit = 1;
1257 if (hw_ep->wMaxPacketSizeTx) {
1259 "%s: hw_ep %d%s, %smax %d\n",
1260 musb_driver_name, i,
1261 hw_ep->bIsSharedFifo ? "shared" : "tx",
1262 hw_ep->tx_double_buffered
1263 ? "doublebuffer, " : "",
1264 hw_ep->wMaxPacketSizeTx);
1266 if (hw_ep->wMaxPacketSizeRx && !hw_ep->bIsSharedFifo) {
1268 "%s: hw_ep %d%s, %smax %d\n",
1269 musb_driver_name, i,
1271 hw_ep->rx_double_buffered
1272 ? "doublebuffer, " : "",
1273 hw_ep->wMaxPacketSizeRx);
1275 if (!(hw_ep->wMaxPacketSizeTx || hw_ep->wMaxPacketSizeRx))
1276 DBG(1, "hw_ep %d not configured\n", i);
1282 /*-------------------------------------------------------------------------*/
1284 #ifdef CONFIG_ARCH_OMAP243X
1286 static irqreturn_t generic_interrupt(int irq, void *__hci, struct pt_regs *r)
1288 unsigned long flags;
1289 irqreturn_t retval = IRQ_NONE;
1290 struct musb *musb = __hci;
1292 spin_lock_irqsave(&musb->Lock, flags);
1294 musb->int_usb = musb_readb(musb->pRegs, MGC_O_HDRC_INTRUSB);
1295 musb->int_tx = musb_readw(musb->pRegs, MGC_O_HDRC_INTRTX);
1296 musb->int_rx = musb_readw(musb->pRegs, MGC_O_HDRC_INTRRX);
1299 if (musb->int_usb || musb->int_tx || musb->int_rx)
1300 retval = musb_interrupt(musb);
1302 spin_unlock_irqrestore(&musb->Lock, flags);
1304 /* REVISIT we sometimes get spurious IRQs on g_ep0
1307 if (retval != IRQ_HANDLED)
1308 DBG(5, "spurious?\n");
1314 #define generic_interrupt NULL
1318 * handle all the irqs defined by the HDRC core. for now we expect: other
1319 * irq sources (phy, dma, etc) will be handled first, musb->int_* values
1320 * will be assigned, and the irq will already have been acked.
1322 * called in irq context with spinlock held, irqs blocked
1324 irqreturn_t musb_interrupt(struct musb *musb)
1326 irqreturn_t retval = IRQ_NONE;
1331 devctl = musb_readb(musb->pRegs, MGC_O_HDRC_DEVCTL);
1332 power = musb_readb(musb->pRegs, MGC_O_HDRC_POWER);
1334 DBG(4, "** IRQ %s usb%04x tx%04x rx%04x\n",
1335 (devctl & MGC_M_DEVCTL_HM) ? "host" : "peripheral",
1336 musb->int_usb, musb->int_tx, musb->int_rx);
1338 /* the core can interrupt us for multiple reasons; docs have
1339 * a generic interrupt flowchart to follow
1341 if (musb->int_usb & STAGE0_MASK)
1342 retval |= musb_stage0_irq(musb, musb->int_usb,
1345 musb->vbuserr_retry = VBUSERR_RETRY_COUNT;
1347 /* "stage 1" is handling endpoint irqs */
1349 /* handle endpoint 0 first */
1350 if (musb->int_tx & 1) {
1351 if (devctl & MGC_M_DEVCTL_HM)
1352 retval |= musb_h_ep0_irq(musb);
1354 retval |= musb_g_ep0_irq(musb);
1357 /* RX on endpoints 1-15 */
1358 reg = musb->int_rx >> 1;
1362 // MGC_SelectEnd(musb->pRegs, ep_num);
1363 /* REVISIT just retval = ep->rx_irq(...) */
1364 retval = IRQ_HANDLED;
1365 if (devctl & MGC_M_DEVCTL_HM) {
1366 if (is_host_capable())
1367 musb_host_rx(musb, ep_num);
1369 if (is_peripheral_capable())
1370 musb_g_rx(musb, ep_num);
1378 /* TX on endpoints 1-15 */
1379 reg = musb->int_tx >> 1;
1383 // MGC_SelectEnd(musb->pRegs, ep_num);
1384 /* REVISIT just retval |= ep->tx_irq(...) */
1385 retval = IRQ_HANDLED;
1386 if (devctl & MGC_M_DEVCTL_HM) {
1387 if (is_host_capable())
1388 musb_host_tx(musb, ep_num);
1390 if (is_peripheral_capable())
1391 musb_g_tx(musb, ep_num);
1398 /* finish handling "global" interrupts after handling fifos */
1400 retval |= musb_stage2_irq(musb,
1401 musb->int_usb, devctl, power);
1407 #ifndef CONFIG_USB_INVENTRA_FIFO
1408 static int __devinitdata use_dma = is_dma_capable();
1410 /* "modprobe ... use_dma=0" etc */
1411 module_param(use_dma, bool, 0);
1412 MODULE_PARM_DESC(use_dma, "enable/disable use of DMA");
1414 void musb_dma_completion(struct musb *musb, u8 bLocalEnd, u8 bTransmit)
1416 u8 devctl = musb_readb(musb->pRegs, MGC_O_HDRC_DEVCTL);
1418 /* called with controller lock already held */
1421 #if !(defined(CONFIG_USB_TI_CPPI_DMA) || defined(CONFIG_USB_TUSB_OMAP_DMA))
1423 if (devctl & MGC_M_DEVCTL_HM)
1424 musb_h_ep0_irq(musb);
1426 musb_g_ep0_irq(musb);
1429 /* endpoints 1..15 */
1431 if (devctl & MGC_M_DEVCTL_HM) {
1432 if (is_host_capable())
1433 musb_host_tx(musb, bLocalEnd);
1435 if (is_peripheral_capable())
1436 musb_g_tx(musb, bLocalEnd);
1440 if (devctl & MGC_M_DEVCTL_HM) {
1441 if (is_host_capable())
1442 musb_host_rx(musb, bLocalEnd);
1444 if (is_peripheral_capable())
1445 musb_g_rx(musb, bLocalEnd);
1452 #define use_dma is_dma_capable()
1455 /*-------------------------------------------------------------------------*/
1460 musb_mode_show(struct device *dev, struct device_attribute *attr, char *buf)
1462 struct musb *musb = dev_to_musb(dev);
1463 unsigned long flags;
1466 spin_lock_irqsave(&musb->Lock, flags);
1467 switch (musb->board_mode) {
1469 ret = sprintf(buf, "host\n");
1471 case MUSB_PERIPHERAL:
1472 ret = sprintf(buf, "peripheral\n");
1475 ret = sprintf(buf, "otg\n");
1478 spin_unlock_irqrestore(&musb->Lock, flags);
1482 static DEVICE_ATTR(mode, S_IRUGO, musb_mode_show, NULL);
1485 musb_cable_show(struct device *dev, struct device_attribute *attr, char *buf)
1487 struct musb *musb = dev_to_musb(dev);
1488 char *v1= "", *v2 = "?";
1489 unsigned long flags;
1492 spin_lock_irqsave(&musb->Lock, flags);
1493 #ifdef CONFIG_USB_TUSB6010
1494 /* REVISIT: connect-A != connect-B ... */
1495 vbus = musb_platform_get_vbus_status(musb);
1499 v2 = "disconnected";
1501 /* NOTE: board-specific issues, like too-big capacitors keeping
1502 * VBUS high for a long time after power has been removed, can
1503 * cause temporary false indications of a connection.
1505 vbus = musb_readb(musb->pRegs, MGC_O_HDRC_DEVCTL);
1507 /* REVISIT retest on real OTG hardware */
1508 switch (musb->board_mode) {
1512 case MUSB_PERIPHERAL:
1517 v2 = (vbus & MGC_M_DEVCTL_BDEVICE) ? "A" : "B";
1520 } else /* VBUS level below A-Valid */
1521 v2 = "disconnected";
1523 musb_platform_try_idle(musb);
1524 spin_unlock_irqrestore(&musb->Lock, flags);
1526 return sprintf(buf, "%s%s\n", v1, v2);
1528 static DEVICE_ATTR(cable, S_IRUGO, musb_cable_show, NULL);
1532 /* Only used to provide cable state change events */
1533 static void musb_irq_work(void *data)
1535 struct musb *musb = (struct musb *)data;
1537 sysfs_notify(&musb->controller->kobj, NULL, "cable");
1540 /* --------------------------------------------------------------------------
1544 static struct musb *__devinit
1545 allocate_instance(struct device *dev, void __iomem *mbase)
1548 struct musb_hw_ep *ep;
1550 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1551 struct usb_hcd *hcd;
1553 hcd = usb_create_hcd(&musb_hc_driver, dev, dev->bus_id);
1556 /* usbcore sets dev->driver_data to hcd, and sometimes uses that... */
1558 musb = hcd_to_musb(hcd);
1559 INIT_LIST_HEAD(&musb->control);
1560 INIT_LIST_HEAD(&musb->in_bulk);
1561 INIT_LIST_HEAD(&musb->out_bulk);
1563 hcd->uses_new_polling = 1;
1565 musb->vbuserr_retry = VBUSERR_RETRY_COUNT;
1567 musb = kzalloc(sizeof *musb, GFP_KERNEL);
1570 dev_set_drvdata(dev, musb);
1574 musb->pRegs = mbase;
1575 musb->ctrl_base = mbase;
1576 musb->nIrq = -ENODEV;
1577 for (epnum = 0, ep = musb->aLocalEnd;
1578 epnum < MUSB_C_NUM_EPS;
1582 ep->bLocalEnd = epnum;
1585 musb->controller = dev;
1589 static void musb_free(struct musb *musb)
1591 /* this has multiple entry modes. it handles fault cleanup after
1592 * probe(), where things may be partially set up, as well as rmmod
1593 * cleanup after everything's been de-activated.
1597 device_remove_file(musb->controller, &dev_attr_mode);
1598 device_remove_file(musb->controller, &dev_attr_cable);
1601 #ifdef CONFIG_USB_GADGET_MUSB_HDRC
1602 musb_gadget_cleanup(musb);
1605 if (musb->nIrq >= 0) {
1606 disable_irq_wake(musb->nIrq);
1607 free_irq(musb->nIrq, musb);
1609 if (is_dma_capable() && musb->pDmaController) {
1610 struct dma_controller *c = musb->pDmaController;
1613 (void) c->stop(c->pPrivateData);
1614 dma_controller_factory.destroy(c);
1616 musb_platform_exit(musb);
1618 clk_disable(musb->clock);
1619 clk_put(musb->clock);
1622 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1623 usb_put_hcd(musb_to_hcd(musb));
1630 * Perform generic per-controller initialization.
1632 * @pDevice: the controller (already clocked, etc)
1634 * @pRegs: virtual address of controller registers,
1635 * not yet corrected for platform-specific offsets
1637 static int __devinit
1638 musb_init_controller(struct device *dev, int nIrq, void __iomem *ctrl)
1642 struct musb_hdrc_platform_data *plat = dev->platform_data;
1644 /* The driver might handle more features than the board; OK.
1645 * Fail when the board needs a feature that's not enabled.
1648 dev_dbg(dev, "no platform_data?\n");
1651 switch (plat->mode) {
1653 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1658 case MUSB_PERIPHERAL:
1659 #ifdef CONFIG_USB_GADGET_MUSB_HDRC
1665 #ifdef CONFIG_USB_MUSB_OTG
1671 dev_dbg(dev, "incompatible Kconfig role setting\n");
1676 pThis = allocate_instance(dev, ctrl);
1680 spin_lock_init(&pThis->Lock);
1681 pThis->board_mode = plat->mode;
1682 pThis->board_set_power = plat->set_power;
1683 pThis->min_power = plat->min_power;
1685 /* assume vbus is off */
1687 /* platform adjusts pThis->pRegs and pThis->isr if needed,
1688 * and activates clocks
1690 pThis->isr = generic_interrupt;
1691 status = musb_platform_init(pThis);
1700 #ifndef CONFIG_USB_INVENTRA_FIFO
1701 if (use_dma && dev->dma_mask) {
1702 struct dma_controller *c;
1704 c = dma_controller_factory.create(pThis, pThis->pRegs);
1705 pThis->pDmaController = c;
1707 (void) c->start(c->pPrivateData);
1710 /* ideally this would be abstracted in platform setup */
1711 if (!is_dma_capable() || !pThis->pDmaController)
1712 dev->dma_mask = NULL;
1714 /* be sure interrupts are disabled before connecting ISR */
1715 musb_platform_disable(pThis);
1717 /* setup musb parts of the core (especially endpoints) */
1718 status = musb_core_init(plat->multipoint
1719 ? MUSB_CONTROLLER_MHDRC
1720 : MUSB_CONTROLLER_HDRC, pThis);
1724 /* attach to the IRQ */
1725 if (request_irq (nIrq, pThis->isr, 0, dev->bus_id, pThis)) {
1726 dev_err(dev, "request_irq %d failed!\n", nIrq);
1730 (void) enable_irq_wake(nIrq);
1732 device_init_wakeup(dev, 1);
1734 pr_info("%s: USB %s mode controller at %p using %s, IRQ %d\n",
1737 switch (pThis->board_mode) {
1738 case MUSB_HOST: s = "Host"; break;
1739 case MUSB_PERIPHERAL: s = "Peripheral"; break;
1740 default: s = "OTG"; break;
1743 (is_dma_capable() && pThis->pDmaController)
1747 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1748 /* host side needs more setup, except for no-host modes */
1749 if (pThis->board_mode != MUSB_PERIPHERAL) {
1750 struct usb_hcd *hcd = musb_to_hcd(pThis);
1752 if (pThis->board_mode == MUSB_OTG)
1753 hcd->self.otg_port = 1;
1754 pThis->xceiv.host = &hcd->self;
1755 hcd->power_budget = 2 * (plat->power ? : 250);
1757 #endif /* CONFIG_USB_MUSB_HDRC_HCD */
1759 #ifdef CONFIG_USB_MUSB_OTG
1760 /* if present, this gets used even on non-otg boards */
1761 MGC_OtgMachineInit(&pThis->OtgMachine, pThis);
1764 /* For the host-only role, we can activate right away.
1765 * Otherwise, wait till the gadget driver hooks up.
1767 * REVISIT switch to compile-time is_role_host() etc
1768 * to get rid of #ifdeffery
1770 switch (pThis->board_mode) {
1771 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1773 MUSB_HST_MODE(pThis);
1774 pThis->xceiv.state = OTG_STATE_A_IDLE;
1775 status = usb_add_hcd(musb_to_hcd(pThis), -1, 0);
1777 DBG(1, "%s mode, status %d, devctl %02x %c\n",
1779 musb_readb(pThis->pRegs, MGC_O_HDRC_DEVCTL),
1780 (musb_readb(pThis->pRegs, MGC_O_HDRC_DEVCTL)
1781 & MGC_M_DEVCTL_BDEVICE
1785 #ifdef CONFIG_USB_GADGET_MUSB_HDRC
1786 case MUSB_PERIPHERAL:
1787 MUSB_DEV_MODE(pThis);
1788 status = musb_gadget_setup(pThis);
1790 DBG(1, "%s mode, status %d, dev%02x\n",
1791 "PERIPHERAL", status,
1792 musb_readb(pThis->pRegs, MGC_O_HDRC_DEVCTL));
1795 #ifdef CONFIG_USB_MUSB_OTG
1797 MUSB_OTG_MODE(pThis);
1798 status = musb_gadget_setup(pThis);
1800 DBG(1, "%s mode, status %d, dev%02x\n",
1802 musb_readb(pThis->pRegs, MGC_O_HDRC_DEVCTL));
1808 musb_debug_create("driver/musb_hdrc", pThis);
1811 device_init_wakeup(dev, 0);
1816 INIT_WORK(&pThis->irq_work, musb_irq_work, pThis);
1819 device_create_file(dev, &dev_attr_mode);
1820 device_create_file(dev, &dev_attr_cable);
1826 musb_platform_exit(pThis);
1830 /*-------------------------------------------------------------------------*/
1832 /* all implementations (PCI bridge to FPGA, VLYNQ, etc) should just
1833 * bridge to a platform device; this driver then suffices.
1836 static int __devinit musb_probe(struct platform_device *pdev)
1838 struct device *dev = &pdev->dev;
1839 int irq = platform_get_irq(pdev, 0);
1840 struct resource *iomem;
1843 iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1844 if (!iomem || irq == 0)
1847 base = ioremap(iomem->start, iomem->end - iomem->start + 1);
1849 dev_err(dev, "ioremap failed\n");
1853 return musb_init_controller(dev, irq, base);
1856 static int __devexit musb_remove(struct platform_device *pdev)
1858 struct musb *musb = dev_to_musb(&pdev->dev);
1860 /* this gets called on rmmod.
1861 * - Host mode: host may still be active
1862 * - Peripheral mode: peripheral is deactivated (or never-activated)
1863 * - OTG mode: both roles are deactivated (or never-activated)
1865 musb_shutdown(pdev);
1866 musb_debug_delete("driver/musb_hdrc", musb);
1867 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1868 if (musb->board_mode == MUSB_HOST)
1869 usb_remove_hcd(musb_to_hcd(musb));
1872 device_init_wakeup(&pdev->dev, 0);
1878 static int musb_suspend(struct platform_device *pdev, pm_message_t message)
1880 unsigned long flags;
1881 struct musb *musb = dev_to_musb(&pdev->dev);
1886 spin_lock_irqsave(&musb->Lock, flags);
1888 if (is_peripheral_active(musb)) {
1889 /* FIXME force disconnect unless we know USB will wake
1890 * the system up quickly enough to respond ...
1892 } else if (is_host_active(musb)) {
1893 /* we know all the children are suspended; sometimes
1894 * they will even be wakeup-enabled.
1898 clk_disable(musb->clock);
1899 spin_unlock_irqrestore(&musb->Lock, flags);
1903 static int musb_resume(struct platform_device *pdev)
1905 unsigned long flags;
1906 struct musb *musb = dev_to_musb(&pdev->dev);
1911 spin_lock_irqsave(&musb->Lock, flags);
1912 clk_enable(musb->clock);
1913 /* for static cmos like DaVinci, register values were preserved
1914 * unless for some reason the whole soc powered down and we're
1915 * not treating that as a whole-system restart (e.g. swsusp)
1917 spin_unlock_irqrestore(&musb->Lock, flags);
1922 #define musb_suspend NULL
1923 #define musb_resume NULL
1926 static struct platform_driver musb_driver = {
1928 .name = (char *)musb_driver_name,
1929 .bus = &platform_bus_type,
1930 .owner = THIS_MODULE,
1932 .probe = musb_probe,
1933 .remove = __devexit_p(musb_remove),
1934 .shutdown = musb_shutdown,
1935 .suspend = musb_suspend,
1936 .resume = musb_resume,
1939 /*-------------------------------------------------------------------------*/
1941 static int __init musb_init(void)
1943 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1948 pr_info("%s: version " MUSB_VERSION ", "
1949 #ifdef CONFIG_USB_INVENTRA_FIFO
1951 #elif defined(CONFIG_USB_TI_CPPI_DMA)
1953 #elif defined(CONFIG_USB_INVENTRA_DMA)
1955 #elif defined(CONFIG_USB_TUSB_OMAP_DMA)
1961 #ifdef CONFIG_USB_MUSB_OTG
1962 "otg (peripheral+host)"
1963 #elif defined(CONFIG_USB_GADGET_MUSB_HDRC)
1965 #elif defined(CONFIG_USB_MUSB_HDRC_HCD)
1969 musb_driver_name, debug);
1970 return platform_driver_register(&musb_driver);
1973 /* make us init after usbcore and before usb
1974 * gadget and host-side drivers start to register
1976 subsys_initcall(musb_init);
1978 static void __exit musb_cleanup(void)
1980 platform_driver_unregister(&musb_driver);
1982 module_exit(musb_cleanup);