1 /*****************************************************************
2 * Copyright 2005 Mentor Graphics Corporation
3 * Copyright (C) 2005-2006 by Texas Instruments
4 * Copyright (C) 2006 by Nokia Corporation
6 * This file is part of the Inventra Controller Driver for Linux.
8 * The Inventra Controller Driver for Linux is free software; you
9 * can redistribute it and/or modify it under the terms of the GNU
10 * General Public License version 2 as published by the Free Software
13 * The Inventra Controller Driver for Linux is distributed in
14 * the hope that it will be useful, but WITHOUT ANY WARRANTY;
15 * without even the implied warranty of MERCHANTABILITY or
16 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
17 * License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with The Inventra Controller Driver for Linux ; if not,
21 * write to the Free Software Foundation, Inc., 59 Temple Place,
22 * Suite 330, Boston, MA 02111-1307 USA
24 * ANY DOWNLOAD, USE, REPRODUCTION, MODIFICATION OR DISTRIBUTION
25 * OF THIS DRIVER INDICATES YOUR COMPLETE AND UNCONDITIONAL ACCEPTANCE
26 * OF THOSE TERMS.THIS DRIVER IS PROVIDED "AS IS" AND MENTOR GRAPHICS
27 * MAKES NO WARRANTIES, EXPRESS OR IMPLIED, RELATED TO THIS DRIVER.
28 * MENTOR GRAPHICS SPECIFICALLY DISCLAIMS ALL IMPLIED WARRANTIES
29 * OF MERCHANTABILITY; FITNESS FOR A PARTICULAR PURPOSE AND
30 * NON-INFRINGEMENT. MENTOR GRAPHICS DOES NOT PROVIDE SUPPORT
31 * SERVICES OR UPDATES FOR THIS DRIVER, EVEN IF YOU ARE A MENTOR
32 * GRAPHICS SUPPORT CUSTOMER.
33 ******************************************************************/
36 * Inventra (Multipoint) Dual-Role Controller Driver for Linux.
38 * This consists of a Host Controller Driver (HCD) and a peripheral
39 * controller driver implementing the "Gadget" API; OTG support is
40 * in the works. These are normal Linux-USB controller drivers which
41 * use IRQs and have no dedicated thread.
43 * This version of the driver has only been used with products from
44 * Texas Instruments. Those products integrate the Inventra logic
45 * with other DMA, IRQ, and bus modules, as well as other logic that
46 * needs to be reflected in this driver.
49 * NOTE: the original Mentor code here was pretty much a collection
50 * of mechanisms that don't seem to have been fully integrated/working
51 * for *any* Linux kernel version. This version aims at Linux 2.6.now,
52 * Key open issues include:
54 * - Lack of host-side transaction scheduling, for all transfer types.
55 * The hardware doesn't do it; instead, software must.
57 * This is not an issue for OTG devices that don't support external
58 * hubs, but for more "normal" USB hosts it's a user issue that the
59 * "multipoint" support doesn't scale in the expected ways. That
60 * includes DaVinci EVM in a common non-OTG mode.
62 * * Control and bulk use dedicated endpoints, and there's as
63 * yet no mechanism to either (a) reclaim the hardware when
64 * peripherals are NAKing, which gets complicated with bulk
65 * endpoints, or (b) use more than a single bulk endpoint in
68 * RESULT: one device may be perceived as blocking another one.
70 * * Interrupt and isochronous will dynamically allocate endpoint
71 * hardware, but (a) there's no record keeping for bandwidth;
72 * (b) in the common case that few endpoints are available, there
73 * is no mechanism to reuse endpoints to talk to multiple devices.
75 * RESULT: At one extreme, bandwidth can be overcommitted in
76 * some hardware configurations, no faults will be reported.
77 * At the other extreme, the bandwidth capabilities which do
78 * exist tend to be severely undercommitted. You can't yet hook
79 * up both a keyboard and a mouse to an external USB hub.
83 * This gets many kinds of configuration information:
84 * - Kconfig for everything user-configurable
85 * - <asm/arch/hdrc_cnf.h> for SOC or family details
86 * - platform_device for addressing, irq, and platform_data
87 * - platform_data is mostly for board-specific informarion
89 * Most of the conditional compilation will (someday) vanish.
92 #include <linux/module.h>
93 #include <linux/kernel.h>
94 #include <linux/sched.h>
95 #include <linux/slab.h>
96 #include <linux/init.h>
97 #include <linux/list.h>
98 #include <linux/kobject.h>
99 #include <linux/platform_device.h>
104 #include <asm/arch/hardware.h>
105 #include <asm/arch/memory.h>
106 #include <asm/mach-types.h>
109 #include "musbdefs.h"
112 #ifdef CONFIG_ARCH_DAVINCI
119 unsigned debug = MUSB_DEBUG;
120 module_param(debug, uint, 0);
121 MODULE_PARM_DESC(debug, "initial debug message level");
123 #define MUSB_VERSION_SUFFIX "/dbg"
126 const char *otg_state_string(struct musb *musb)
130 snprintf(buf, sizeof buf, "otg-%d", musb->xceiv.state);
135 #define DRIVER_AUTHOR "Mentor Graphics, Texas Instruments, Nokia"
136 #define DRIVER_DESC "Inventra Dual-Role USB Controller Driver"
138 #define MUSB_VERSION_BASE "2.2a/db-0.5.2"
140 #ifndef MUSB_VERSION_SUFFIX
141 #define MUSB_VERSION_SUFFIX ""
143 #define MUSB_VERSION MUSB_VERSION_BASE MUSB_VERSION_SUFFIX
145 #define DRIVER_INFO DRIVER_DESC ", v" MUSB_VERSION
147 const char musb_driver_name[] = "musb_hdrc";
149 MODULE_DESCRIPTION(DRIVER_INFO);
150 MODULE_AUTHOR(DRIVER_AUTHOR);
151 MODULE_LICENSE("GPL");
154 /*-------------------------------------------------------------------------*/
156 static inline struct musb *dev_to_musb(struct device *dev)
158 #ifdef CONFIG_USB_MUSB_HDRC_HCD
159 /* usbcore insists dev->driver_data is a "struct hcd *" */
160 return hcd_to_musb(dev_get_drvdata(dev));
162 return dev_get_drvdata(dev);
166 /*-------------------------------------------------------------------------*/
168 #ifndef CONFIG_USB_TUSB6010
170 * Load an endpoint's FIFO
172 void musb_write_fifo(struct musb_hw_ep *hw_ep, u16 len, const u8 *src)
174 void __iomem *fifo = hw_ep->fifo;
178 DBG(4, "%cX ep%d fifo %p count %d buf %p\n",
179 'T', hw_ep->epnum, fifo, len, src);
181 /* we can't assume unaligned reads work */
182 if (likely((0x01 & (unsigned long) src) == 0)) {
185 /* best case is 32bit-aligned source address */
186 if ((0x02 & (unsigned long) src) == 0) {
188 writesl(fifo, src + index, len >> 2);
189 index += len & ~0x03;
192 musb_writew(fifo, 0, *(u16*)&src[index]);
197 writesw(fifo, src + index, len >> 1);
198 index += len & ~0x01;
202 musb_writeb(fifo, 0, src[index]);
205 writesb(fifo, src, len);
210 * Unload an endpoint's FIFO
212 void musb_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *dst)
214 void __iomem *fifo = hw_ep->fifo;
216 DBG(4, "%cX ep%d fifo %p count %d buf %p\n",
217 'R', hw_ep->epnum, fifo, len, dst);
219 /* we can't assume unaligned writes work */
220 if (likely((0x01 & (unsigned long) dst) == 0)) {
223 /* best case is 32bit-aligned destination address */
224 if ((0x02 & (unsigned long) dst) == 0) {
226 readsl(fifo, dst, len >> 2);
230 *(u16*)&dst[index] = musb_readw(fifo, 0);
235 readsw(fifo, dst, len >> 1);
240 dst[index] = musb_readb(fifo, 0);
243 readsb(fifo, dst, len);
247 #endif /* normal PIO */
250 /*-------------------------------------------------------------------------*/
252 /* for high speed test mode; see USB 2.0 spec 7.1.20 */
253 static const u8 musb_test_packet[53] = {
254 /* implicit SYNC then DATA0 to start */
257 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
259 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,
261 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0xee,
262 /* JJJJJJJKKKKKKK x8 */
263 0xfe, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
265 0x7f, 0xbf, 0xdf, 0xef, 0xf7, 0xfb, 0xfd,
266 /* JKKKKKKK x10, JK */
267 0xfc, 0x7e, 0xbf, 0xdf, 0xef, 0xf7, 0xfb, 0xfd, 0x7e
269 /* implicit CRC16 then EOP to end */
272 void musb_load_testpacket(struct musb *musb)
274 void __iomem *regs = musb->endpoints[0].regs;
276 musb_ep_select(musb->mregs, 0);
277 musb_write_fifo(musb->control_ep,
278 sizeof(musb_test_packet), musb_test_packet);
279 musb_writew(regs, MUSB_CSR0, MGC_M_CSR0_TXPKTRDY);
282 /*-------------------------------------------------------------------------*/
284 #ifdef CONFIG_USB_MUSB_OTG
287 * See also USB_OTG_1-3.pdf 6.6.5 Timers
288 * REVISIT: Are the other timers done in the hardware?
290 #define TB_ASE0_BRST 100 /* Min 3.125 ms */
293 * Handles OTG hnp timeouts, such as b_ase0_brst
295 void musb_otg_timer_func(unsigned long data)
297 struct musb *musb = (struct musb *)data;
300 spin_lock_irqsave(&musb->lock, flags);
301 if (musb->xceiv.state == OTG_STATE_B_WAIT_ACON) {
302 DBG(1, "HNP: B_WAIT_ACON timeout, going back to B_PERIPHERAL\n");
303 musb_g_disconnect(musb);
304 musb->xceiv.state = OTG_STATE_B_PERIPHERAL;
307 spin_unlock_irqrestore(&musb->lock, flags);
310 static DEFINE_TIMER(musb_otg_timer, musb_otg_timer_func, 0, 0);
313 * Stops the B-device HNP state. Caller must take care of locking.
315 void musb_hnp_stop(struct musb *musb)
317 struct usb_hcd *hcd = musb_to_hcd(musb);
318 void __iomem *mbase = musb->mregs;
321 switch (musb->xceiv.state) {
322 case OTG_STATE_A_PERIPHERAL:
323 case OTG_STATE_A_WAIT_VFALL:
324 DBG(1, "HNP: Switching back to A-host\n");
325 musb_g_disconnect(musb);
326 musb_root_disconnect(musb);
327 musb->xceiv.state = OTG_STATE_A_IDLE;
330 case OTG_STATE_B_HOST:
331 DBG(1, "HNP: Disabling HR\n");
332 hcd->self.is_b_host = 0;
333 musb->xceiv.state = OTG_STATE_B_PERIPHERAL;
334 reg = musb_readb(mbase, MUSB_POWER);
335 reg |= MGC_M_POWER_SUSPENDM;
336 musb_writeb(mbase, MUSB_POWER, reg);
337 /* REVISIT: Start SESSION_REQUEST here? */
340 DBG(1, "HNP: Stopping in unknown state %s\n",
341 otg_state_string(musb));
348 * Interrupt Service Routine to record USB "global" interrupts.
349 * Since these do not happen often and signify things of
350 * paramount importance, it seems OK to check them individually;
351 * the order of the tests is specified in the manual
353 * @param musb instance pointer
354 * @param bIntrUSB register contents
359 #define STAGE0_MASK (MGC_M_INTR_RESUME | MGC_M_INTR_SESSREQ \
360 | MGC_M_INTR_VBUSERROR | MGC_M_INTR_CONNECT \
363 static irqreturn_t musb_stage0_irq(struct musb * musb, u8 bIntrUSB,
366 irqreturn_t handled = IRQ_NONE;
367 #ifdef CONFIG_USB_MUSB_HDRC_HCD
368 void __iomem *mbase = musb->mregs;
371 DBG(3, "<== Power=%02x, DevCtl=%02x, bIntrUSB=0x%x\n", power, devctl,
374 /* in host mode, the peripheral may issue remote wakeup.
375 * in peripheral mode, the host may resume the link.
376 * spurious RESUME irqs happen too, paired with SUSPEND.
378 if (bIntrUSB & MGC_M_INTR_RESUME) {
379 handled = IRQ_HANDLED;
380 DBG(3, "RESUME (%s)\n", otg_state_string(musb));
382 if (devctl & MGC_M_DEVCTL_HM) {
383 #ifdef CONFIG_USB_MUSB_HDRC_HCD
384 switch (musb->xceiv.state) {
385 case OTG_STATE_A_SUSPEND:
386 /* remote wakeup? later, GetPortStatus
387 * will stop RESUME signaling
390 if (power & MGC_M_POWER_SUSPENDM) {
392 musb->int_usb &= ~MGC_M_INTR_SUSPEND;
393 DBG(2, "Spurious SUSPENDM\n");
397 power &= ~MGC_M_POWER_SUSPENDM;
398 musb_writeb(mbase, MUSB_POWER,
399 power | MGC_M_POWER_RESUME);
401 musb->port1_status |=
402 (USB_PORT_STAT_C_SUSPEND << 16)
403 | MUSB_PORT_STAT_RESUME;
404 musb->rh_timer = jiffies
405 + msecs_to_jiffies(20);
407 musb->xceiv.state = OTG_STATE_A_HOST;
409 usb_hcd_resume_root_hub(musb_to_hcd(musb));
411 case OTG_STATE_B_WAIT_ACON:
412 musb->xceiv.state = OTG_STATE_B_PERIPHERAL;
417 WARN("bogus %s RESUME (%s)\n",
419 otg_state_string(musb));
423 switch (musb->xceiv.state) {
424 #ifdef CONFIG_USB_MUSB_HDRC_HCD
425 case OTG_STATE_A_SUSPEND:
426 /* possibly DISCONNECT is upcoming */
427 musb->xceiv.state = OTG_STATE_A_HOST;
428 usb_hcd_resume_root_hub(musb_to_hcd(musb));
431 #ifdef CONFIG_USB_GADGET_MUSB_HDRC
432 case OTG_STATE_B_WAIT_ACON:
433 case OTG_STATE_B_PERIPHERAL:
434 /* disconnect while suspended? we may
435 * not get a disconnect irq...
437 if ((devctl & MGC_M_DEVCTL_VBUS)
438 != (3 << MGC_S_DEVCTL_VBUS)) {
439 musb->int_usb |= MGC_M_INTR_DISCONNECT;
440 musb->int_usb &= ~MGC_M_INTR_SUSPEND;
445 case OTG_STATE_B_IDLE:
446 musb->int_usb &= ~MGC_M_INTR_SUSPEND;
450 WARN("bogus %s RESUME (%s)\n",
452 otg_state_string(musb));
457 #ifdef CONFIG_USB_MUSB_HDRC_HCD
458 /* see manual for the order of the tests */
459 if (bIntrUSB & MGC_M_INTR_SESSREQ) {
460 DBG(1, "SESSION_REQUEST (%s)\n", otg_state_string(musb));
462 /* IRQ arrives from ID pin sense or (later, if VBUS power
463 * is removed) SRP. responses are time critical:
464 * - turn on VBUS (with silicon-specific mechanism)
465 * - go through A_WAIT_VRISE
466 * - ... to A_WAIT_BCON.
467 * a_wait_vrise_tmout triggers VBUS_ERROR transitions
469 musb_writeb(mbase, MUSB_DEVCTL, MGC_M_DEVCTL_SESSION);
470 musb->ep0_stage = MGC_END0_START;
471 musb->xceiv.state = OTG_STATE_A_IDLE;
473 musb_set_vbus(musb, 1);
475 handled = IRQ_HANDLED;
478 if (bIntrUSB & MGC_M_INTR_VBUSERROR) {
481 /* During connection as an A-Device, we may see a short
482 * current spikes causing voltage drop, because of cable
483 * and peripheral capacitance combined with vbus draw.
484 * (So: less common with truly self-powered devices, where
485 * vbus doesn't act like a power supply.)
487 * Such spikes are short; usually less than ~500 usec, max
488 * of ~2 msec. That is, they're not sustained overcurrent
489 * errors, though they're reported using VBUSERROR irqs.
491 * Workarounds: (a) hardware: use self powered devices.
492 * (b) software: ignore non-repeated VBUS errors.
494 * REVISIT: do delays from lots of DEBUG_KERNEL checks
495 * make trouble here, keeping VBUS < 4.4V ?
497 switch (musb->xceiv.state) {
498 case OTG_STATE_A_HOST:
499 /* recovery is dicey once we've gotten past the
500 * initial stages of enumeration, but if VBUS
501 * stayed ok at the other end of the link, and
502 * another reset is due (at least for high speed,
503 * to redo the chirp etc), it might work OK...
505 case OTG_STATE_A_WAIT_BCON:
506 case OTG_STATE_A_WAIT_VRISE:
507 if (musb->vbuserr_retry) {
508 musb->vbuserr_retry--;
510 devctl |= MGC_M_DEVCTL_SESSION;
511 musb_writeb(mbase, MUSB_DEVCTL, devctl);
513 musb->port1_status |=
514 (1 << USB_PORT_FEAT_OVER_CURRENT)
515 | (1 << USB_PORT_FEAT_C_OVER_CURRENT);
522 DBG(1, "VBUS_ERROR in %s (%02x, %s), retry #%d, port1 %08x\n",
523 otg_state_string(musb),
526 switch (devctl & MGC_M_DEVCTL_VBUS) {
527 case 0 << MGC_S_DEVCTL_VBUS:
528 s = "<SessEnd"; break;
529 case 1 << MGC_S_DEVCTL_VBUS:
530 s = "<AValid"; break;
531 case 2 << MGC_S_DEVCTL_VBUS:
532 s = "<VBusValid"; break;
533 //case 3 << MGC_S_DEVCTL_VBUS:
537 VBUSERR_RETRY_COUNT - musb->vbuserr_retry,
540 /* go through A_WAIT_VFALL then start a new session */
542 musb_set_vbus(musb, 0);
543 handled = IRQ_HANDLED;
546 if (bIntrUSB & MGC_M_INTR_CONNECT) {
547 struct usb_hcd *hcd = musb_to_hcd(musb);
549 handled = IRQ_HANDLED;
551 set_bit(HCD_FLAG_SAW_IRQ, &hcd->flags);
553 musb->ep0_stage = MGC_END0_START;
555 #ifdef CONFIG_USB_MUSB_OTG
556 /* flush endpoints when transitioning from Device Mode */
557 if (is_peripheral_active(musb)) {
558 // REVISIT HNP; just force disconnect
560 musb->delay_port_power_off = FALSE;
561 musb_writew(mbase, MUSB_INTRTXE, musb->wEndMask);
562 musb_writew(mbase, MUSB_INTRRXE, musb->wEndMask & 0xfffe);
563 musb_writeb(mbase, MUSB_INTRUSBE, 0xf7);
565 musb->port1_status &= ~(USB_PORT_STAT_LOW_SPEED
566 |USB_PORT_STAT_HIGH_SPEED
567 |USB_PORT_STAT_ENABLE
569 musb->port1_status |= USB_PORT_STAT_CONNECTION
570 |(USB_PORT_STAT_C_CONNECTION << 16);
572 /* high vs full speed is just a guess until after reset */
573 if (devctl & MGC_M_DEVCTL_LSDEV)
574 musb->port1_status |= USB_PORT_STAT_LOW_SPEED;
577 usb_hcd_poll_rh_status(hcd);
579 usb_hcd_resume_root_hub(hcd);
583 /* indicate new connection to OTG machine */
584 switch (musb->xceiv.state) {
585 case OTG_STATE_B_WAIT_ACON:
586 DBG(1, "HNP: Waiting to switch to b_host state\n");
587 musb->xceiv.state = OTG_STATE_B_HOST;
588 hcd->self.is_b_host = 1;
591 if ((devctl & MGC_M_DEVCTL_VBUS)
592 == (3 << MGC_S_DEVCTL_VBUS)) {
593 musb->xceiv.state = OTG_STATE_A_HOST;
594 hcd->self.is_b_host = 0;
598 DBG(1, "CONNECT (%s) devctl %02x\n",
599 otg_state_string(musb), devctl);
601 #endif /* CONFIG_USB_MUSB_HDRC_HCD */
603 /* mentor saves a bit: bus reset and babble share the same irq.
604 * only host sees babble; only peripheral sees bus reset.
606 if (bIntrUSB & MGC_M_INTR_RESET) {
607 if (devctl & MGC_M_DEVCTL_HM) {
609 * Looks like non-HS BABBLE can be ignored, but
610 * HS BABBLE is an error condition. For HS the solution
611 * is to avoid babble in the first place and fix whatever
612 * causes BABBLE. When HS BABBLE happens we can only stop
615 if (devctl & (MGC_M_DEVCTL_FSDEV | MGC_M_DEVCTL_LSDEV))
616 DBG(1, "BABBLE devctl: %02x\n", devctl);
618 ERR("Stopping host session because of babble\n");
619 musb_writeb(mbase, MUSB_DEVCTL, 0);
622 DBG(1, "BUS RESET\n");
625 schedule_work(&musb->irq_work);
628 handled = IRQ_HANDLED;
635 * Interrupt Service Routine to record USB "global" interrupts.
636 * Since these do not happen often and signify things of
637 * paramount importance, it seems OK to check them individually;
638 * the order of the tests is specified in the manual
640 * @param musb instance pointer
641 * @param bIntrUSB register contents
645 static irqreturn_t musb_stage2_irq(struct musb * musb, u8 bIntrUSB,
648 irqreturn_t handled = IRQ_NONE;
651 /* REVISIT ... this would be for multiplexing periodic endpoints, or
652 * supporting transfer phasing to prevent exceeding ISO bandwidth
653 * limits of a given frame or microframe.
655 * It's not needed for peripheral side, which dedicates endpoints;
656 * though it _might_ use SOF irqs for other purposes.
658 * And it's not currently needed for host side, which also dedicates
659 * endpoints, relies on TX/RX interval registers, and isn't claimed
660 * to support ISO transfers yet.
662 if (bIntrUSB & MGC_M_INTR_SOF) {
663 void __iomem *mbase = musb->mregs;
664 struct musb_hw_ep *ep;
668 DBG(6, "START_OF_FRAME\n");
669 handled = IRQ_HANDLED;
671 /* start any periodic Tx transfers waiting for current frame */
672 wFrame = musb_readw(mbase, MUSB_FRAME);
673 ep = musb->endpoints;
674 for (epnum = 1; (epnum < musb->nr_endpoints)
675 && (musb->wEndMask >= (1 << epnum));
677 // FIXME handle framecounter wraps (12 bits)
678 // eliminate duplicated StartUrb logic
679 if (ep->dwWaitFrame >= wFrame) {
681 printk("SOF --> periodic TX%s on %d\n",
682 ep->tx_channel ? " DMA" : "",
685 musb_h_tx_start(musb, epnum);
687 cppi_hostdma_start(musb, epnum);
689 } /* end of for loop */
693 if ((bIntrUSB & MGC_M_INTR_DISCONNECT) && !musb->ignore_disconnect) {
694 DBG(1, "DISCONNECT (%s) as %s, devctl %02x\n",
695 otg_state_string(musb),
696 MUSB_MODE(musb), devctl);
697 handled = IRQ_HANDLED;
699 switch (musb->xceiv.state) {
700 #ifdef CONFIG_USB_MUSB_HDRC_HCD
701 case OTG_STATE_A_HOST:
702 case OTG_STATE_A_SUSPEND:
703 musb_root_disconnect(musb);
704 if (musb->a_wait_bcon != 0)
705 musb_platform_try_idle(musb, jiffies
706 + msecs_to_jiffies(musb->a_wait_bcon));
709 #ifdef CONFIG_USB_MUSB_OTG
710 case OTG_STATE_B_HOST:
714 case OTG_STATE_A_PERIPHERAL:
715 musb_root_disconnect(musb);
717 case OTG_STATE_B_WAIT_ACON:
719 #ifdef CONFIG_USB_GADGET_MUSB_HDRC
720 case OTG_STATE_B_PERIPHERAL:
721 case OTG_STATE_B_IDLE:
722 musb_g_disconnect(musb);
726 WARN("unhandled DISCONNECT transition (%s)\n",
727 otg_state_string(musb));
731 schedule_work(&musb->irq_work);
734 if (bIntrUSB & MGC_M_INTR_SUSPEND) {
735 DBG(1, "SUSPEND (%s) devctl %02x power %02x\n",
736 otg_state_string(musb), devctl, power);
737 handled = IRQ_HANDLED;
739 switch (musb->xceiv.state) {
740 case OTG_STATE_A_PERIPHERAL:
743 case OTG_STATE_B_PERIPHERAL:
744 musb_g_suspend(musb);
745 musb->is_active = is_otg_enabled(musb)
746 && musb->xceiv.gadget->b_hnp_enable;
747 if (musb->is_active) {
748 musb->xceiv.state = OTG_STATE_B_WAIT_ACON;
749 #ifdef CONFIG_USB_MUSB_OTG
750 DBG(1, "HNP: Setting timer for b_ase0_brst\n");
751 musb_otg_timer.data = (unsigned long)musb;
752 mod_timer(&musb_otg_timer, jiffies
753 + msecs_to_jiffies(TB_ASE0_BRST));
757 case OTG_STATE_A_WAIT_BCON:
758 if (musb->a_wait_bcon != 0)
759 musb_platform_try_idle(musb, jiffies
760 + msecs_to_jiffies(musb->a_wait_bcon));
762 case OTG_STATE_A_HOST:
763 musb->xceiv.state = OTG_STATE_A_SUSPEND;
764 musb->is_active = is_otg_enabled(musb)
765 && musb->xceiv.host->b_hnp_enable;
767 case OTG_STATE_B_HOST:
768 /* Transition to B_PERIPHERAL, see 6.8.2.6 p 44 */
769 DBG(1, "REVISIT: SUSPEND as B_HOST\n");
772 /* "should not happen" */
782 /*-------------------------------------------------------------------------*/
785 * Program the HDRC to start (enable interrupts, dma, etc.).
787 void musb_start(struct musb *musb)
789 void __iomem *regs = musb->mregs;
790 u8 devctl = musb_readb(regs, MUSB_DEVCTL);
792 DBG(2, "<== devctl %02x\n", devctl);
794 /* Set INT enable registers, enable interrupts */
795 musb_writew(regs, MUSB_INTRTXE, musb->wEndMask);
796 musb_writew(regs, MUSB_INTRRXE, musb->wEndMask & 0xfffe);
797 musb_writeb(regs, MUSB_INTRUSBE, 0xf7);
799 musb_writeb(regs, MUSB_TESTMODE, 0);
801 /* put into basic highspeed mode and start session */
802 musb_writeb(regs, MUSB_POWER, MGC_M_POWER_ISOUPDATE
803 | MGC_M_POWER_SOFTCONN
805 /* ENSUSPEND wedges tusb */
806 // | MGC_M_POWER_ENSUSPEND
810 devctl = musb_readb(regs, MUSB_DEVCTL);
811 devctl &= ~MGC_M_DEVCTL_SESSION;
813 if (is_otg_enabled(musb)) {
814 /* session started after:
815 * (a) ID-grounded irq, host mode;
816 * (b) vbus present/connect IRQ, peripheral mode;
817 * (c) peripheral initiates, using SRP
819 if ((devctl & MGC_M_DEVCTL_VBUS) == MGC_M_DEVCTL_VBUS)
822 devctl |= MGC_M_DEVCTL_SESSION;
824 } else if (is_host_enabled(musb)) {
825 /* assume ID pin is hard-wired to ground */
826 devctl |= MGC_M_DEVCTL_SESSION;
828 } else /* peripheral is enabled */ {
829 if ((devctl & MGC_M_DEVCTL_VBUS) == MGC_M_DEVCTL_VBUS)
832 musb_platform_enable(musb);
833 musb_writeb(regs, MUSB_DEVCTL, devctl);
837 static void musb_generic_disable(struct musb *musb)
839 void __iomem *mbase = musb->mregs;
842 /* disable interrupts */
843 musb_writeb(mbase, MUSB_INTRUSBE, 0);
844 musb_writew(mbase, MUSB_INTRTXE, 0);
845 musb_writew(mbase, MUSB_INTRRXE, 0);
848 musb_writeb(mbase, MUSB_DEVCTL, 0);
850 /* flush pending interrupts */
851 temp = musb_readb(mbase, MUSB_INTRUSB);
852 temp = musb_readw(mbase, MUSB_INTRTX);
853 temp = musb_readw(mbase, MUSB_INTRRX);
858 * Make the HDRC stop (disable interrupts, etc.);
859 * reversible by musb_start
860 * called on gadget driver unregister
861 * with controller locked, irqs blocked
862 * acts as a NOP unless some role activated the hardware
864 void musb_stop(struct musb *musb)
866 /* stop IRQs, timers, ... */
867 musb_platform_disable(musb);
868 musb_generic_disable(musb);
869 DBG(3, "HDRC disabled\n");
872 * - mark host and/or peripheral drivers unusable/inactive
873 * - disable DMA (and enable it in HdrcStart)
874 * - make sure we can musb_start() after musb_stop(); with
875 * OTG mode, gadget driver module rmmod/modprobe cycles that
878 musb_platform_try_idle(musb, 0);
881 static void musb_shutdown(struct platform_device *pdev)
883 struct musb *musb = dev_to_musb(&pdev->dev);
886 spin_lock_irqsave(&musb->lock, flags);
887 musb_platform_disable(musb);
888 musb_generic_disable(musb);
890 clk_put(musb->clock);
893 spin_unlock_irqrestore(&musb->lock, flags);
895 /* FIXME power down */
899 /*-------------------------------------------------------------------------*/
902 * The silicon either has hard-wired endpoint configurations, or else
903 * "dynamic fifo" sizing. The driver has support for both, though at this
904 * writing only the dynamic sizing is very well tested. We use normal
905 * idioms to so both modes are compile-tested, but dead code elimination
906 * leaves only the relevant one in the object file.
908 * We don't currently use dynamic fifo setup capability to do anything
909 * more than selecting one of a bunch of predefined configurations.
911 #ifdef MUSB_C_DYNFIFO_DEF
912 #define can_dynfifo() 1
914 #define can_dynfifo() 0
917 #ifdef CONFIG_USB_TUSB6010
918 static ushort __initdata fifo_mode = 4;
920 static ushort __initdata fifo_mode = 2;
923 /* "modprobe ... fifo_mode=1" etc */
924 module_param(fifo_mode, ushort, 0);
925 MODULE_PARM_DESC(fifo_mode, "initial endpoint configuration");
928 #define DYN_FIFO_SIZE (1<<(MUSB_C_RAM_BITS+2))
930 enum fifo_style { FIFO_RXTX, FIFO_TX, FIFO_RX } __attribute__ ((packed));
931 enum buf_mode { BUF_SINGLE, BUF_DOUBLE } __attribute__ ((packed));
935 enum fifo_style style;
941 * tables defining fifo_mode values. define more if you like.
942 * for host side, make sure both halves of ep1 are set up.
945 /* mode 0 - fits in 2KB */
946 static struct fifo_cfg __initdata mode_0_cfg[] = {
947 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
948 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
949 { .hw_ep_num = 2, .style = FIFO_RXTX, .maxpacket = 512, },
950 { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
951 { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
954 /* mode 1 - fits in 4KB */
955 static struct fifo_cfg __initdata mode_1_cfg[] = {
956 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, .mode = BUF_DOUBLE, },
957 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, .mode = BUF_DOUBLE, },
958 { .hw_ep_num = 2, .style = FIFO_RXTX, .maxpacket = 512, .mode = BUF_DOUBLE, },
959 { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
960 { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
963 /* mode 2 - fits in 4KB */
964 static struct fifo_cfg __initdata mode_2_cfg[] = {
965 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
966 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
967 { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
968 { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
969 { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
970 { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
973 /* mode 3 - fits in 4KB */
974 static struct fifo_cfg __initdata mode_3_cfg[] = {
975 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, .mode = BUF_DOUBLE, },
976 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, .mode = BUF_DOUBLE, },
977 { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
978 { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
979 { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
980 { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
983 /* mode 4 - fits in 16KB */
984 static struct fifo_cfg __initdata mode_4_cfg[] = {
985 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
986 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
987 { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
988 { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
989 { .hw_ep_num = 3, .style = FIFO_TX, .maxpacket = 512, },
990 { .hw_ep_num = 3, .style = FIFO_RX, .maxpacket = 512, },
991 { .hw_ep_num = 4, .style = FIFO_TX, .maxpacket = 512, },
992 { .hw_ep_num = 4, .style = FIFO_RX, .maxpacket = 512, },
993 { .hw_ep_num = 5, .style = FIFO_TX, .maxpacket = 512, },
994 { .hw_ep_num = 5, .style = FIFO_RX, .maxpacket = 512, },
995 { .hw_ep_num = 6, .style = FIFO_TX, .maxpacket = 512, },
996 { .hw_ep_num = 6, .style = FIFO_RX, .maxpacket = 512, },
997 { .hw_ep_num = 7, .style = FIFO_TX, .maxpacket = 512, },
998 { .hw_ep_num = 7, .style = FIFO_RX, .maxpacket = 512, },
999 { .hw_ep_num = 8, .style = FIFO_TX, .maxpacket = 512, },
1000 { .hw_ep_num = 8, .style = FIFO_RX, .maxpacket = 512, },
1001 { .hw_ep_num = 9, .style = FIFO_TX, .maxpacket = 512, },
1002 { .hw_ep_num = 9, .style = FIFO_RX, .maxpacket = 512, },
1003 { .hw_ep_num = 10, .style = FIFO_TX, .maxpacket = 512, },
1004 { .hw_ep_num = 10, .style = FIFO_RX, .maxpacket = 512, },
1005 { .hw_ep_num = 11, .style = FIFO_TX, .maxpacket = 512, },
1006 { .hw_ep_num = 11, .style = FIFO_RX, .maxpacket = 512, },
1007 { .hw_ep_num = 12, .style = FIFO_TX, .maxpacket = 512, },
1008 { .hw_ep_num = 12, .style = FIFO_RX, .maxpacket = 512, },
1009 { .hw_ep_num = 13, .style = FIFO_TX, .maxpacket = 512, },
1010 { .hw_ep_num = 13, .style = FIFO_RX, .maxpacket = 512, },
1011 { .hw_ep_num = 14, .style = FIFO_RXTX, .maxpacket = 1024, },
1012 { .hw_ep_num = 15, .style = FIFO_RXTX, .maxpacket = 1024, },
1017 * configure a fifo; for non-shared endpoints, this may be called
1018 * once for a tx fifo and once for an rx fifo.
1020 * returns negative errno or offset for next fifo.
1023 fifo_setup(struct musb *musb, struct musb_hw_ep *hw_ep,
1024 const struct fifo_cfg *cfg, u16 offset)
1026 void __iomem *mbase = musb->mregs;
1028 u16 maxpacket = cfg->maxpacket;
1029 u16 c_off = offset >> 3;
1032 /* expect hw_ep has already been zero-initialized */
1034 size = ffs(max(maxpacket, (u16) 8)) - 1;
1035 maxpacket = 1 << size;
1038 if (cfg->mode == BUF_DOUBLE) {
1039 if ((offset + (maxpacket << 1)) > DYN_FIFO_SIZE)
1041 c_size |= MGC_M_FIFOSZ_DPB;
1043 if ((offset + maxpacket) > DYN_FIFO_SIZE)
1047 /* configure the FIFO */
1048 musb_writeb(mbase, MUSB_INDEX, hw_ep->epnum);
1050 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1051 /* EP0 reserved endpoint for control, bidirectional;
1052 * EP1 reserved for bulk, two unidirection halves.
1054 if (hw_ep->epnum == 1)
1055 musb->bulk_ep = hw_ep;
1056 /* REVISIT error check: be sure ep0 can both rx and tx ... */
1058 switch (cfg->style) {
1060 musb_writeb(mbase, MUSB_TXFIFOSZ, c_size);
1061 musb_writew(mbase, MUSB_TXFIFOADD, c_off);
1062 hw_ep->tx_double_buffered = !!(c_size & MGC_M_FIFOSZ_DPB);
1063 hw_ep->max_packet_sz_tx = maxpacket;
1066 musb_writeb(mbase, MUSB_RXFIFOSZ, c_size);
1067 musb_writew(mbase, MUSB_RXFIFOADD, c_off);
1068 hw_ep->rx_double_buffered = !!(c_size & MGC_M_FIFOSZ_DPB);
1069 hw_ep->max_packet_sz_rx = maxpacket;
1072 musb_writeb(mbase, MUSB_TXFIFOSZ, c_size);
1073 musb_writew(mbase, MUSB_TXFIFOADD, c_off);
1074 hw_ep->rx_double_buffered = !!(c_size & MGC_M_FIFOSZ_DPB);
1075 hw_ep->max_packet_sz_rx = maxpacket;
1077 musb_writeb(mbase, MUSB_RXFIFOSZ, c_size);
1078 musb_writew(mbase, MUSB_RXFIFOADD, c_off);
1079 hw_ep->tx_double_buffered = hw_ep->rx_double_buffered;
1080 hw_ep->max_packet_sz_tx = maxpacket;
1082 hw_ep->is_shared_fifo = TRUE;
1086 /* NOTE rx and tx endpoint irqs aren't managed separately,
1087 * which happens to be ok
1089 musb->wEndMask |= (1 << hw_ep->epnum);
1091 return offset + (maxpacket << ((c_size & MGC_M_FIFOSZ_DPB) ? 1 : 0));
1094 static struct fifo_cfg __initdata ep0_cfg = {
1095 .style = FIFO_RXTX, .maxpacket = 64,
1098 static int __init ep_config_from_table(struct musb *musb)
1100 const struct fifo_cfg *cfg;
1103 struct musb_hw_ep *hw_ep = musb->endpoints;
1105 switch (fifo_mode) {
1111 n = ARRAY_SIZE(mode_0_cfg);
1115 n = ARRAY_SIZE(mode_1_cfg);
1119 n = ARRAY_SIZE(mode_2_cfg);
1123 n = ARRAY_SIZE(mode_3_cfg);
1127 n = ARRAY_SIZE(mode_4_cfg);
1131 printk(KERN_DEBUG "%s: setup fifo_mode %d\n",
1132 musb_driver_name, fifo_mode);
1135 offset = fifo_setup(musb, hw_ep, &ep0_cfg, 0);
1136 // assert(offset > 0)
1138 /* NOTE: for RTL versions >= 1.400 EPINFO and RAMINFO would
1139 * be better than static MUSB_C_NUM_EPS and DYN_FIFO_SIZE...
1142 for (i = 0; i < n; i++) {
1143 u8 epn = cfg->hw_ep_num;
1145 if (epn >= MUSB_C_NUM_EPS) {
1146 pr_debug( "%s: invalid ep %d\n",
1147 musb_driver_name, epn);
1150 offset = fifo_setup(musb, hw_ep + epn, cfg++, offset);
1152 pr_debug( "%s: mem overrun, ep %d\n",
1153 musb_driver_name, epn);
1157 musb->nr_endpoints = max(epn, musb->nr_endpoints);
1160 printk(KERN_DEBUG "%s: %d/%d max ep, %d/%d memory\n",
1162 n + 1, MUSB_C_NUM_EPS * 2 - 1,
1163 offset, DYN_FIFO_SIZE);
1165 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1166 if (!musb->bulk_ep) {
1167 pr_debug( "%s: missing bulk\n", musb_driver_name);
1177 * ep_config_from_hw - when MUSB_C_DYNFIFO_DEF is false
1178 * @param musb the controller
1180 static int __init ep_config_from_hw(struct musb *musb)
1183 struct musb_hw_ep *hw_ep;
1184 void *mbase = musb->mregs;
1186 DBG(2, "<== static silicon ep config\n");
1188 /* FIXME pick up ep0 maxpacket size */
1190 for (epnum = 1; epnum < MUSB_C_NUM_EPS; epnum++) {
1191 musb_ep_select(mbase, epnum);
1192 hw_ep = musb->endpoints + epnum;
1194 /* read from core using indexed model */
1195 reg = musb_readb(hw_ep->regs, 0x10 + MUSB_FIFOSIZE);
1197 /* 0's returned when no more endpoints */
1200 musb->nr_endpoints++;
1201 musb->wEndMask |= (1 << epnum);
1203 hw_ep->max_packet_sz_tx = 1 << (reg & 0x0f);
1205 /* shared TX/RX FIFO? */
1206 if ((reg & 0xf0) == 0xf0) {
1207 hw_ep->max_packet_sz_rx = hw_ep->max_packet_sz_tx;
1208 hw_ep->is_shared_fifo = TRUE;
1211 hw_ep->max_packet_sz_rx = 1 << ((reg & 0xf0) >> 4);
1212 hw_ep->is_shared_fifo = FALSE;
1215 /* FIXME set up hw_ep->{rx,tx}_double_buffered */
1217 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1218 /* pick an RX/TX endpoint for bulk */
1219 if (hw_ep->max_packet_sz_tx < 512
1220 || hw_ep->max_packet_sz_rx < 512)
1223 /* REVISIT: this algorithm is lazy, we should at least
1224 * try to pick a double buffered endpoint.
1228 musb->bulk_ep = hw_ep;
1232 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1233 if (!musb->bulk_ep) {
1234 pr_debug( "%s: missing bulk\n", musb_driver_name);
1242 enum { MUSB_CONTROLLER_MHDRC, MUSB_CONTROLLER_HDRC, };
1244 /* Initialize MUSB (M)HDRC part of the USB hardware subsystem;
1245 * configure endpoints, or take their config from silicon
1247 static int __init musb_core_init(u16 wType, struct musb *musb)
1254 u16 wRelease, wRelMajor, wRelMinor;
1255 char aInfo[78], aRevision[32], aDate[12];
1256 void __iomem *mbase = musb->mregs;
1260 /* log core options (read using indexed model) */
1261 musb_ep_select(mbase, 0);
1262 reg = musb_readb(mbase, 0x10 + MUSB_CONFIGDATA);
1264 strcpy(aInfo, (reg & MGC_M_CONFIGDATA_UTMIDW) ? "UTMI-16" : "UTMI-8");
1265 if (reg & MGC_M_CONFIGDATA_DYNFIFO) {
1266 strcat(aInfo, ", dyn FIFOs");
1268 if (reg & MGC_M_CONFIGDATA_MPRXE) {
1269 strcat(aInfo, ", bulk combine");
1271 musb->bulk_combine = TRUE;
1273 strcat(aInfo, " (X)"); /* no driver support */
1276 if (reg & MGC_M_CONFIGDATA_MPTXE) {
1277 strcat(aInfo, ", bulk split");
1279 musb->bulk_split = TRUE;
1281 strcat(aInfo, " (X)"); /* no driver support */
1284 if (reg & MGC_M_CONFIGDATA_HBRXE) {
1285 strcat(aInfo, ", HB-ISO Rx");
1286 strcat(aInfo, " (X)"); /* no driver support */
1288 if (reg & MGC_M_CONFIGDATA_HBTXE) {
1289 strcat(aInfo, ", HB-ISO Tx");
1290 strcat(aInfo, " (X)"); /* no driver support */
1292 if (reg & MGC_M_CONFIGDATA_SOFTCONE) {
1293 strcat(aInfo, ", SoftConn");
1296 printk(KERN_DEBUG "%s: ConfigData=0x%02x (%s)\n",
1297 musb_driver_name, reg, aInfo);
1300 dwData = musb_readl(mbase, 0x404);
1301 sprintf(aDate, "%04d-%02x-%02x", (dwData & 0xffff),
1302 (dwData >> 16) & 0xff, (dwData >> 24) & 0xff);
1303 /* FIXME ID2 and ID3 are unused */
1304 dwData = musb_readl(mbase, 0x408);
1305 printk("ID2=%lx\n", (long unsigned)dwData);
1306 dwData = musb_readl(mbase, 0x40c);
1307 printk("ID3=%lx\n", (long unsigned)dwData);
1308 reg = musb_readb(mbase, 0x400);
1309 wType = ('M' == reg) ? MUSB_CONTROLLER_MHDRC : MUSB_CONTROLLER_HDRC;
1313 if (MUSB_CONTROLLER_MHDRC == wType) {
1314 musb->is_multipoint = 1;
1317 musb->is_multipoint = 0;
1319 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1320 #ifndef CONFIG_USB_OTG_BLACKLIST_HUB
1322 "%s: kernel must blacklist external hubs\n",
1328 /* log release info */
1329 wRelease = musb_readw(mbase, MUSB_HWVERS);
1330 wRelMajor = (wRelease >> 10) & 0x1f;
1331 wRelMinor = wRelease & 0x3ff;
1332 snprintf(aRevision, 32, "%d.%d%s", wRelMajor,
1333 wRelMinor, (wRelease & 0x8000) ? "RC" : "");
1334 printk(KERN_DEBUG "%s: %sHDRC RTL version %s %s\n",
1335 musb_driver_name, type, aRevision, aDate);
1338 musb->endpoints[0].max_packet_sz_tx = MGC_END0_FIFOSIZE;
1339 musb->endpoints[0].max_packet_sz_rx = MGC_END0_FIFOSIZE;
1341 /* discover endpoint configuration */
1342 musb->nr_endpoints = 1;
1345 if (reg & MGC_M_CONFIGDATA_DYNFIFO) {
1347 status = ep_config_from_table(musb);
1349 ERR("reconfigure software for Dynamic FIFOs\n");
1354 status = ep_config_from_hw(musb);
1356 ERR("reconfigure software for static FIFOs\n");
1364 /* finish init, and print endpoint config */
1365 for (i = 0; i < musb->nr_endpoints; i++) {
1366 struct musb_hw_ep *hw_ep = musb->endpoints + i;
1368 hw_ep->fifo = MUSB_FIFO_OFFSET(i) + mbase;
1369 #ifdef CONFIG_USB_TUSB6010
1370 hw_ep->fifo_async = musb->async + 0x400 + MUSB_FIFO_OFFSET(i);
1371 hw_ep->fifo_sync = musb->sync + 0x400 + MUSB_FIFO_OFFSET(i);
1372 hw_ep->fifo_sync_va =
1373 musb->sync_va + 0x400 + MUSB_FIFO_OFFSET(i);
1376 hw_ep->conf = mbase - 0x400 + TUSB_EP0_CONF;
1378 hw_ep->conf = mbase + 0x400 + (((i - 1) & 0xf) << 2);
1381 hw_ep->regs = MGC_END_OFFSET(i, 0) + mbase;
1382 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1383 hw_ep->target_regs = MGC_BUSCTL_OFFSET(i, 0) + mbase;
1384 hw_ep->rx_reinit = 1;
1385 hw_ep->tx_reinit = 1;
1388 if (hw_ep->max_packet_sz_tx) {
1390 "%s: hw_ep %d%s, %smax %d\n",
1391 musb_driver_name, i,
1392 hw_ep->is_shared_fifo ? "shared" : "tx",
1393 hw_ep->tx_double_buffered
1394 ? "doublebuffer, " : "",
1395 hw_ep->max_packet_sz_tx);
1397 if (hw_ep->max_packet_sz_rx && !hw_ep->is_shared_fifo) {
1399 "%s: hw_ep %d%s, %smax %d\n",
1400 musb_driver_name, i,
1402 hw_ep->rx_double_buffered
1403 ? "doublebuffer, " : "",
1404 hw_ep->max_packet_sz_rx);
1406 if (!(hw_ep->max_packet_sz_tx || hw_ep->max_packet_sz_rx))
1407 DBG(1, "hw_ep %d not configured\n", i);
1413 /*-------------------------------------------------------------------------*/
1415 #if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3430)
1417 static irqreturn_t generic_interrupt(int irq, void *__hci)
1419 unsigned long flags;
1420 irqreturn_t retval = IRQ_NONE;
1421 struct musb *musb = __hci;
1423 spin_lock_irqsave(&musb->lock, flags);
1425 musb->int_usb = musb_readb(musb->mregs, MUSB_INTRUSB);
1426 musb->int_tx = musb_readw(musb->mregs, MUSB_INTRTX);
1427 musb->int_rx = musb_readw(musb->mregs, MUSB_INTRRX);
1429 if (musb->int_usb || musb->int_tx || musb->int_rx)
1430 retval = musb_interrupt(musb);
1432 spin_unlock_irqrestore(&musb->lock, flags);
1434 /* REVISIT we sometimes get spurious IRQs on g_ep0
1437 if (retval != IRQ_HANDLED)
1438 DBG(5, "spurious?\n");
1444 #define generic_interrupt NULL
1448 * handle all the irqs defined by the HDRC core. for now we expect: other
1449 * irq sources (phy, dma, etc) will be handled first, musb->int_* values
1450 * will be assigned, and the irq will already have been acked.
1452 * called in irq context with spinlock held, irqs blocked
1454 irqreturn_t musb_interrupt(struct musb *musb)
1456 irqreturn_t retval = IRQ_NONE;
1461 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
1462 power = musb_readb(musb->mregs, MUSB_POWER);
1464 DBG(4, "** IRQ %s usb%04x tx%04x rx%04x\n",
1465 (devctl & MGC_M_DEVCTL_HM) ? "host" : "peripheral",
1466 musb->int_usb, musb->int_tx, musb->int_rx);
1468 /* the core can interrupt us for multiple reasons; docs have
1469 * a generic interrupt flowchart to follow
1471 if (musb->int_usb & STAGE0_MASK)
1472 retval |= musb_stage0_irq(musb, musb->int_usb,
1475 /* "stage 1" is handling endpoint irqs */
1477 /* handle endpoint 0 first */
1478 if (musb->int_tx & 1) {
1479 if (devctl & MGC_M_DEVCTL_HM)
1480 retval |= musb_h_ep0_irq(musb);
1482 retval |= musb_g_ep0_irq(musb);
1485 /* RX on endpoints 1-15 */
1486 reg = musb->int_rx >> 1;
1490 // musb_ep_select(musb->mregs, ep_num);
1491 /* REVISIT just retval = ep->rx_irq(...) */
1492 retval = IRQ_HANDLED;
1493 if (devctl & MGC_M_DEVCTL_HM) {
1494 if (is_host_capable())
1495 musb_host_rx(musb, ep_num);
1497 if (is_peripheral_capable())
1498 musb_g_rx(musb, ep_num);
1506 /* TX on endpoints 1-15 */
1507 reg = musb->int_tx >> 1;
1511 // musb_ep_select(musb->mregs, ep_num);
1512 /* REVISIT just retval |= ep->tx_irq(...) */
1513 retval = IRQ_HANDLED;
1514 if (devctl & MGC_M_DEVCTL_HM) {
1515 if (is_host_capable())
1516 musb_host_tx(musb, ep_num);
1518 if (is_peripheral_capable())
1519 musb_g_tx(musb, ep_num);
1526 /* finish handling "global" interrupts after handling fifos */
1528 retval |= musb_stage2_irq(musb,
1529 musb->int_usb, devctl, power);
1535 #ifndef CONFIG_USB_INVENTRA_FIFO
1536 static int __initdata use_dma = 1;
1538 /* "modprobe ... use_dma=0" etc */
1539 module_param(use_dma, bool, 0);
1540 MODULE_PARM_DESC(use_dma, "enable/disable use of DMA");
1542 void musb_dma_completion(struct musb *musb, u8 epnum, u8 bTransmit)
1544 u8 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
1546 /* called with controller lock already held */
1549 #ifndef CONFIG_USB_TUSB_OMAP_DMA
1550 if (!is_cppi_enabled()) {
1552 if (devctl & MGC_M_DEVCTL_HM)
1553 musb_h_ep0_irq(musb);
1555 musb_g_ep0_irq(musb);
1559 /* endpoints 1..15 */
1561 if (devctl & MGC_M_DEVCTL_HM) {
1562 if (is_host_capable())
1563 musb_host_tx(musb, epnum);
1565 if (is_peripheral_capable())
1566 musb_g_tx(musb, epnum);
1570 if (devctl & MGC_M_DEVCTL_HM) {
1571 if (is_host_capable())
1572 musb_host_rx(musb, epnum);
1574 if (is_peripheral_capable())
1575 musb_g_rx(musb, epnum);
1585 /*-------------------------------------------------------------------------*/
1590 musb_mode_show(struct device *dev, struct device_attribute *attr, char *buf)
1592 struct musb *musb = dev_to_musb(dev);
1593 unsigned long flags;
1596 spin_lock_irqsave(&musb->lock, flags);
1597 ret = sprintf(buf, "%s\n", otg_state_string(musb));
1598 spin_unlock_irqrestore(&musb->lock, flags);
1604 musb_mode_store(struct device *dev, struct device_attribute *attr,
1605 const char *buf, size_t n)
1607 struct musb *musb = dev_to_musb(dev);
1608 unsigned long flags;
1610 spin_lock_irqsave(&musb->lock, flags);
1611 if (!strncmp(buf, "host", 4))
1612 musb_platform_set_mode(musb, MUSB_HOST);
1613 if (!strncmp(buf, "peripheral", 10))
1614 musb_platform_set_mode(musb, MUSB_PERIPHERAL);
1615 if (!strncmp(buf, "otg", 3))
1616 musb_platform_set_mode(musb, MUSB_OTG);
1617 spin_unlock_irqrestore(&musb->lock, flags);
1621 static DEVICE_ATTR(mode, 0644, musb_mode_show, musb_mode_store);
1624 musb_cable_show(struct device *dev, struct device_attribute *attr, char *buf)
1626 struct musb *musb = dev_to_musb(dev);
1627 char *v1= "", *v2 = "?";
1628 unsigned long flags;
1631 spin_lock_irqsave(&musb->lock, flags);
1632 #if defined(CONFIG_USB_TUSB6010) && !defined(CONFIG_USB_MUSB_OTG)
1633 /* REVISIT: connect-A != connect-B ... */
1634 vbus = musb_platform_get_vbus_status(musb);
1638 v2 = "disconnected";
1640 /* NOTE: board-specific issues, like too-big capacitors keeping
1641 * VBUS high for a long time after power has been removed, can
1642 * cause temporary false indications of a connection.
1644 vbus = musb_readb(musb->mregs, MUSB_DEVCTL);
1646 /* REVISIT retest on real OTG hardware */
1647 switch (musb->board_mode) {
1651 case MUSB_PERIPHERAL:
1656 v2 = (vbus & MGC_M_DEVCTL_BDEVICE) ? "B" : "A";
1659 } else /* VBUS level below A-Valid */
1660 v2 = "disconnected";
1662 musb_platform_try_idle(musb, 0);
1663 spin_unlock_irqrestore(&musb->lock, flags);
1665 return sprintf(buf, "%s%s\n", v1, v2);
1667 static DEVICE_ATTR(cable, S_IRUGO, musb_cable_show, NULL);
1670 musb_vbus_store(struct device *dev, struct device_attribute *attr,
1671 const char *buf, size_t n)
1673 struct musb *musb = dev_to_musb(dev);
1674 unsigned long flags;
1677 spin_lock_irqsave(&musb->lock, flags);
1678 if (sscanf(buf, "%lu", &val) < 1) {
1679 printk(KERN_ERR "Invalid VBUS timeout ms value\n");
1682 musb->a_wait_bcon = val;
1683 if (musb->xceiv.state == OTG_STATE_A_WAIT_BCON)
1684 musb->is_active = 0;
1685 musb_platform_try_idle(musb, jiffies + msecs_to_jiffies(val));
1686 spin_unlock_irqrestore(&musb->lock, flags);
1692 musb_vbus_show(struct device *dev, struct device_attribute *attr, char *buf)
1694 struct musb *musb = dev_to_musb(dev);
1695 unsigned long flags;
1698 spin_lock_irqsave(&musb->lock, flags);
1699 val = musb->a_wait_bcon;
1700 spin_unlock_irqrestore(&musb->lock, flags);
1702 return sprintf(buf, "%lu\n", val);
1704 static DEVICE_ATTR(vbus, 0644, musb_vbus_show, musb_vbus_store);
1707 musb_srp_store(struct device *dev, struct device_attribute *attr,
1708 const char *buf, size_t n)
1710 struct musb *musb=dev_to_musb(dev);
1711 unsigned long flags;
1714 if (sscanf(buf, "%hu", &srp) != 1
1716 printk (KERN_ERR "SRP: Value must be 1\n");
1720 spin_lock_irqsave(&musb->lock, flags);
1722 musb_g_wakeup(musb);
1723 spin_unlock_irqrestore(&musb->lock, flags);
1727 static DEVICE_ATTR(srp, 0644, NULL, musb_srp_store);
1730 /* Only used to provide cable state change events */
1731 static void musb_irq_work(struct work_struct *data)
1733 struct musb *musb = container_of(data, struct musb, irq_work);
1735 sysfs_notify(&musb->controller->kobj, NULL, "cable");
1738 /* --------------------------------------------------------------------------
1742 static struct musb *__init
1743 allocate_instance(struct device *dev, void __iomem *mbase)
1746 struct musb_hw_ep *ep;
1748 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1749 struct usb_hcd *hcd;
1751 hcd = usb_create_hcd(&musb_hc_driver, dev, dev->bus_id);
1754 /* usbcore sets dev->driver_data to hcd, and sometimes uses that... */
1756 musb = hcd_to_musb(hcd);
1757 INIT_LIST_HEAD(&musb->control);
1758 INIT_LIST_HEAD(&musb->in_bulk);
1759 INIT_LIST_HEAD(&musb->out_bulk);
1761 hcd->uses_new_polling = 1;
1763 musb->vbuserr_retry = VBUSERR_RETRY_COUNT;
1765 musb = kzalloc(sizeof *musb, GFP_KERNEL);
1768 dev_set_drvdata(dev, musb);
1772 musb->mregs = mbase;
1773 musb->ctrl_base = mbase;
1774 musb->nIrq = -ENODEV;
1775 for (epnum = 0, ep = musb->endpoints;
1776 epnum < MUSB_C_NUM_EPS;
1783 musb->controller = dev;
1787 static void musb_free(struct musb *musb)
1789 /* this has multiple entry modes. it handles fault cleanup after
1790 * probe(), where things may be partially set up, as well as rmmod
1791 * cleanup after everything's been de-activated.
1795 device_remove_file(musb->controller, &dev_attr_mode);
1796 device_remove_file(musb->controller, &dev_attr_cable);
1797 device_remove_file(musb->controller, &dev_attr_vbus);
1798 #ifdef CONFIG_USB_MUSB_OTG
1799 device_remove_file(musb->controller, &dev_attr_srp);
1803 #ifdef CONFIG_USB_GADGET_MUSB_HDRC
1804 musb_gadget_cleanup(musb);
1807 if (musb->nIrq >= 0) {
1808 disable_irq_wake(musb->nIrq);
1809 free_irq(musb->nIrq, musb);
1811 if (is_dma_capable() && musb->dma_controller) {
1812 struct dma_controller *c = musb->dma_controller;
1814 (void) c->stop(c->private_data);
1815 dma_controller_destroy(c);
1818 musb_writeb(musb->mregs, MUSB_DEVCTL, 0);
1819 musb_platform_exit(musb);
1820 musb_writeb(musb->mregs, MUSB_DEVCTL, 0);
1823 clk_disable(musb->clock);
1824 clk_put(musb->clock);
1827 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1828 usb_put_hcd(musb_to_hcd(musb));
1835 * Perform generic per-controller initialization.
1837 * @pDevice: the controller (already clocked, etc)
1839 * @mregs: virtual address of controller registers,
1840 * not yet corrected for platform-specific offsets
1843 musb_init_controller(struct device *dev, int nIrq, void __iomem *ctrl)
1847 struct musb_hdrc_platform_data *plat = dev->platform_data;
1849 /* The driver might handle more features than the board; OK.
1850 * Fail when the board needs a feature that's not enabled.
1853 dev_dbg(dev, "no platform_data?\n");
1856 switch (plat->mode) {
1858 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1863 case MUSB_PERIPHERAL:
1864 #ifdef CONFIG_USB_GADGET_MUSB_HDRC
1870 #ifdef CONFIG_USB_MUSB_OTG
1876 dev_err(dev, "incompatible Kconfig role setting\n");
1881 musb = allocate_instance(dev, ctrl);
1885 spin_lock_init(&musb->lock);
1886 musb->board_mode = plat->mode;
1887 musb->board_set_power = plat->set_power;
1888 musb->set_clock = plat->set_clock;
1889 musb->min_power = plat->min_power;
1891 /* Clock usage is chip-specific ... functional clock (DaVinci,
1892 * OMAP2430), or PHY ref (some TUSB6010 boards). All this core
1893 * code does is make sure a clock handle is available; platform
1894 * code manages it during start/stop and suspend/resume.
1897 musb->clock = clk_get(dev, plat->clock);
1898 if (IS_ERR(musb->clock)) {
1899 status = PTR_ERR(musb->clock);
1905 /* assume vbus is off */
1907 /* platform adjusts musb->mregs and musb->isr if needed,
1908 * and activates clocks
1910 musb->isr = generic_interrupt;
1911 status = musb_platform_init(musb);
1920 #ifndef CONFIG_USB_INVENTRA_FIFO
1921 if (use_dma && dev->dma_mask) {
1922 struct dma_controller *c;
1924 c = dma_controller_create(musb, musb->mregs);
1925 musb->dma_controller = c;
1927 (void) c->start(c->private_data);
1930 /* ideally this would be abstracted in platform setup */
1931 if (!is_dma_capable() || !musb->dma_controller)
1932 dev->dma_mask = NULL;
1934 /* be sure interrupts are disabled before connecting ISR */
1935 musb_platform_disable(musb);
1936 musb_generic_disable(musb);
1938 /* setup musb parts of the core (especially endpoints) */
1939 status = musb_core_init(plat->multipoint
1940 ? MUSB_CONTROLLER_MHDRC
1941 : MUSB_CONTROLLER_HDRC, musb);
1945 /* attach to the IRQ */
1946 if (request_irq (nIrq, musb->isr, 0, dev->bus_id, musb)) {
1947 dev_err(dev, "request_irq %d failed!\n", nIrq);
1952 // FIXME this handles wakeup irqs wrong
1953 if (enable_irq_wake(nIrq) == 0)
1954 device_init_wakeup(dev, 1);
1956 pr_info("%s: USB %s mode controller at %p using %s, IRQ %d\n",
1959 switch (musb->board_mode) {
1960 case MUSB_HOST: s = "Host"; break;
1961 case MUSB_PERIPHERAL: s = "Peripheral"; break;
1962 default: s = "OTG"; break;
1965 (is_dma_capable() && musb->dma_controller)
1969 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1970 /* host side needs more setup, except for no-host modes */
1971 if (musb->board_mode != MUSB_PERIPHERAL) {
1972 struct usb_hcd *hcd = musb_to_hcd(musb);
1974 if (musb->board_mode == MUSB_OTG)
1975 hcd->self.otg_port = 1;
1976 musb->xceiv.host = &hcd->self;
1977 hcd->power_budget = 2 * (plat->power ? : 250);
1979 #endif /* CONFIG_USB_MUSB_HDRC_HCD */
1981 /* For the host-only role, we can activate right away.
1982 * (We expect the ID pin to be forcibly grounded!!)
1983 * Otherwise, wait till the gadget driver hooks up.
1985 if (!is_otg_enabled(musb) && is_host_enabled(musb)) {
1986 MUSB_HST_MODE(musb);
1987 musb->xceiv.default_a = 1;
1988 musb->xceiv.state = OTG_STATE_A_IDLE;
1990 status = usb_add_hcd(musb_to_hcd(musb), -1, 0);
1992 DBG(1, "%s mode, status %d, devctl %02x %c\n",
1994 musb_readb(musb->mregs, MUSB_DEVCTL),
1995 (musb_readb(musb->mregs, MUSB_DEVCTL)
1996 & MGC_M_DEVCTL_BDEVICE
1999 } else /* peripheral is enabled */ {
2000 MUSB_DEV_MODE(musb);
2001 musb->xceiv.default_a = 0;
2002 musb->xceiv.state = OTG_STATE_B_IDLE;
2004 status = musb_gadget_setup(musb);
2006 DBG(1, "%s mode, status %d, dev%02x\n",
2007 is_otg_enabled(musb) ? "OTG" : "PERIPHERAL",
2009 musb_readb(musb->mregs, MUSB_DEVCTL));
2014 musb_debug_create("driver/musb_hdrc", musb);
2018 clk_put(musb->clock);
2019 device_init_wakeup(dev, 0);
2024 INIT_WORK(&musb->irq_work, musb_irq_work);
2027 status = device_create_file(dev, &dev_attr_mode);
2028 status = device_create_file(dev, &dev_attr_cable);
2029 status = device_create_file(dev, &dev_attr_vbus);
2030 #ifdef CONFIG_USB_MUSB_OTG
2031 status = device_create_file(dev, &dev_attr_srp);
2032 #endif /* CONFIG_USB_MUSB_OTG */
2039 musb_platform_exit(musb);
2043 /*-------------------------------------------------------------------------*/
2045 /* all implementations (PCI bridge to FPGA, VLYNQ, etc) should just
2046 * bridge to a platform device; this driver then suffices.
2049 #ifndef CONFIG_USB_INVENTRA_FIFO
2050 static u64 *orig_dma_mask;
2053 static int __init musb_probe(struct platform_device *pdev)
2055 struct device *dev = &pdev->dev;
2056 int irq = platform_get_irq(pdev, 0);
2057 struct resource *iomem;
2060 iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2061 if (!iomem || irq == 0)
2064 base = ioremap(iomem->start, iomem->end - iomem->start + 1);
2066 dev_err(dev, "ioremap failed\n");
2070 #ifndef CONFIG_USB_INVENTRA_FIFO
2071 /* clobbered by use_dma=n */
2072 orig_dma_mask = dev->dma_mask;
2074 return musb_init_controller(dev, irq, base);
2077 static int __devexit musb_remove(struct platform_device *pdev)
2079 struct musb *musb = dev_to_musb(&pdev->dev);
2080 void __iomem *ctrl_base = musb->ctrl_base;
2082 /* this gets called on rmmod.
2083 * - Host mode: host may still be active
2084 * - Peripheral mode: peripheral is deactivated (or never-activated)
2085 * - OTG mode: both roles are deactivated (or never-activated)
2087 musb_shutdown(pdev);
2088 musb_debug_delete("driver/musb_hdrc", musb);
2089 #ifdef CONFIG_USB_MUSB_HDRC_HCD
2090 if (musb->board_mode == MUSB_HOST)
2091 usb_remove_hcd(musb_to_hcd(musb));
2095 device_init_wakeup(&pdev->dev, 0);
2096 #ifndef CONFIG_USB_INVENTRA_FIFO
2097 pdev->dev.dma_mask = orig_dma_mask;
2104 static int musb_suspend(struct platform_device *pdev, pm_message_t message)
2106 unsigned long flags;
2107 struct musb *musb = dev_to_musb(&pdev->dev);
2112 spin_lock_irqsave(&musb->lock, flags);
2114 if (is_peripheral_active(musb)) {
2115 /* FIXME force disconnect unless we know USB will wake
2116 * the system up quickly enough to respond ...
2118 } else if (is_host_active(musb)) {
2119 /* we know all the children are suspended; sometimes
2120 * they will even be wakeup-enabled.
2124 if (musb->set_clock)
2125 musb->set_clock(musb->clock, 0);
2127 clk_disable(musb->clock);
2128 spin_unlock_irqrestore(&musb->lock, flags);
2132 static int musb_resume(struct platform_device *pdev)
2134 unsigned long flags;
2135 struct musb *musb = dev_to_musb(&pdev->dev);
2140 spin_lock_irqsave(&musb->lock, flags);
2142 if (musb->set_clock)
2143 musb->set_clock(musb->clock, 1);
2145 clk_enable(musb->clock);
2147 /* for static cmos like DaVinci, register values were preserved
2148 * unless for some reason the whole soc powered down and we're
2149 * not treating that as a whole-system restart (e.g. swsusp)
2151 spin_unlock_irqrestore(&musb->lock, flags);
2156 #define musb_suspend NULL
2157 #define musb_resume NULL
2160 static struct platform_driver musb_driver = {
2162 .name = (char *)musb_driver_name,
2163 .bus = &platform_bus_type,
2164 .owner = THIS_MODULE,
2166 .remove = __devexit_p(musb_remove),
2167 .shutdown = musb_shutdown,
2168 .suspend = musb_suspend,
2169 .resume = musb_resume,
2172 /*-------------------------------------------------------------------------*/
2174 static int __init musb_init(void)
2176 #ifdef CONFIG_USB_MUSB_HDRC_HCD
2181 pr_info("%s: version " MUSB_VERSION ", "
2182 #ifdef CONFIG_USB_INVENTRA_FIFO
2184 #elif defined(CONFIG_USB_TI_CPPI_DMA)
2186 #elif defined(CONFIG_USB_INVENTRA_DMA)
2188 #elif defined(CONFIG_USB_TUSB_OMAP_DMA)
2194 #ifdef CONFIG_USB_MUSB_OTG
2195 "otg (peripheral+host)"
2196 #elif defined(CONFIG_USB_GADGET_MUSB_HDRC)
2198 #elif defined(CONFIG_USB_MUSB_HDRC_HCD)
2202 musb_driver_name, debug);
2203 return platform_driver_probe(&musb_driver, musb_probe);
2206 /* make us init after usbcore and before usb
2207 * gadget and host-side drivers start to register
2209 subsys_initcall(musb_init);
2211 static void __exit musb_cleanup(void)
2213 platform_driver_unregister(&musb_driver);
2215 module_exit(musb_cleanup);