2 * TUSB6010 USB 2.0 OTG Dual Role controller
4 * Copyright (C) 2006 Nokia Corporation
5 * Jarkko Nikula <jarkko.nikula@nokia.com>
6 * Tony Lindgren <tony@atomide.com>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
13 * - Driver assumes that interface to external host (main CPU) is
14 * configured for NOR FLASH interface instead of VLYNQ serial
18 #include <linux/module.h>
19 #include <linux/kernel.h>
20 #include <linux/errno.h>
21 #include <linux/init.h>
22 #include <linux/usb.h>
23 #include <linux/irq.h>
24 #include <linux/platform_device.h>
29 * Checks the revision. We need to use the DMA register as 3.0 does not
30 * have correct versions for TUSB_PRCM_REV or TUSB_INT_CTRL_REV.
32 static u8 tusb_get_revision(struct musb *musb)
34 void __iomem *base = musb->ctrl_base;
36 return musb_readl(base, TUSB_DMA_CTRL_REV) & 0xff;
39 #define TUSB_REV_MAJOR(reg_val) ((reg_val >> 4) & 0xf)
40 #define TUSB_REV_MINOR(reg_val) (reg_val & 0xf)
42 static int __init tusb_print_revision(struct musb *musb)
44 void __iomem *base = musb->ctrl_base;
46 pr_info("tusb: Revisions: %s%i.%i %s%i.%i %s%i.%i %s%i.%i\n",
48 TUSB_REV_MAJOR(musb_readl(base, TUSB_PRCM_REV)),
49 TUSB_REV_MINOR(musb_readl(base, TUSB_PRCM_REV)),
51 TUSB_REV_MAJOR(musb_readl(base, TUSB_INT_CTRL_REV)),
52 TUSB_REV_MINOR(musb_readl(base, TUSB_INT_CTRL_REV)),
54 TUSB_REV_MAJOR(musb_readl(base, TUSB_GPIO_REV)),
55 TUSB_REV_MINOR(musb_readl(base, TUSB_GPIO_REV)),
57 TUSB_REV_MAJOR(musb_readl(base, TUSB_DMA_CTRL_REV)),
58 TUSB_REV_MINOR(musb_readl(base, TUSB_DMA_CTRL_REV)));
60 return TUSB_REV_MAJOR(musb_readl(base, TUSB_INT_CTRL_REV));
63 #define WBUS_QUIRK_MASK (TUSB_PHY_OTG_CTRL_TESTM2 | TUSB_PHY_OTG_CTRL_TESTM1 \
64 | TUSB_PHY_OTG_CTRL_TESTM0)
67 * Workaround for spontaneous WBUS wake-up issue #2 for tusb3.0.
68 * Disables power detection in PHY for the duration of idle.
70 static void tusb_wbus_quirk(struct musb *musb, int enabled)
72 void __iomem *base = musb->ctrl_base;
73 static u32 phy_otg_ena = 0, phy_otg_ctrl = 0;
77 phy_otg_ena = musb_readl(base, TUSB_PHY_OTG_CTRL_ENABLE);
78 phy_otg_ctrl = musb_readl(base, TUSB_PHY_OTG_CTRL);
79 tmp = TUSB_PHY_OTG_CTRL_WRPROTECT
80 | phy_otg_ena | WBUS_QUIRK_MASK;
81 musb_writel(base, TUSB_PHY_OTG_CTRL_ENABLE, tmp);
82 tmp = phy_otg_ctrl & ~WBUS_QUIRK_MASK;
83 tmp |= TUSB_PHY_OTG_CTRL_WRPROTECT | TUSB_PHY_OTG_CTRL_TESTM2;
84 musb_writel(base, TUSB_PHY_OTG_CTRL, tmp);
85 DBG(2, "Enabled tusb wbus quirk ena %08x ctrl %08x\n",
86 musb_readl(base, TUSB_PHY_OTG_CTRL_ENABLE),
87 musb_readl(base, TUSB_PHY_OTG_CTRL));
88 } else if (musb_readl(base, TUSB_PHY_OTG_CTRL_ENABLE)
89 & TUSB_PHY_OTG_CTRL_TESTM2) {
90 tmp = TUSB_PHY_OTG_CTRL_WRPROTECT
91 | phy_otg_ena | WBUS_QUIRK_MASK;
92 musb_writel(base, TUSB_PHY_OTG_CTRL_ENABLE, tmp);
93 tmp = TUSB_PHY_OTG_CTRL_WRPROTECT | phy_otg_ctrl;
94 musb_writel(base, TUSB_PHY_OTG_CTRL, tmp);
95 tmp = TUSB_PHY_OTG_CTRL_WRPROTECT | phy_otg_ena;
96 musb_writel(base, TUSB_PHY_OTG_CTRL_ENABLE, tmp);
97 DBG(2, "Disabled tusb wbus quirk ena %08x ctrl %08x\n",
98 musb_readl(base, TUSB_PHY_OTG_CTRL_ENABLE),
99 musb_readl(base, TUSB_PHY_OTG_CTRL));
104 int_src = musb_readl(base, TUSB_INT_SRC);
105 if (int_src & TUSB_INT_SRC_ID_STATUS_CHNG)
106 musb_writel(base, TUSB_INT_SRC_CLEAR,
107 TUSB_INT_SRC_ID_STATUS_CHNG);
111 * TUSB 6010 may use a parallel bus that doesn't support byte ops;
112 * so both loading and unloading FIFOs need explicit byte counts.
116 tusb_fifo_write_unaligned(void __iomem *fifo, const u8 *buf, u16 len)
122 for (i = 0; i < (len >> 2); i++) {
123 memcpy(&val, buf, 4);
124 musb_writel(fifo, 0, val);
130 /* Write the rest 1 - 3 bytes to FIFO */
131 memcpy(&val, buf, len);
132 musb_writel(fifo, 0, val);
136 static inline void tusb_fifo_read_unaligned(void __iomem *fifo,
137 void __iomem *buf, u16 len)
143 for (i = 0; i < (len >> 2); i++) {
144 val = musb_readl(fifo, 0);
145 memcpy(buf, &val, 4);
151 /* Read the rest 1 - 3 bytes from FIFO */
152 val = musb_readl(fifo, 0);
153 memcpy(buf, &val, len);
157 void musb_write_fifo(struct musb_hw_ep *hw_ep, u16 len, const u8 *buf)
159 void __iomem *ep_conf = hw_ep->conf;
160 void __iomem *fifo = hw_ep->fifo;
161 u8 epnum = hw_ep->bLocalEnd;
165 DBG(4, "%cX ep%d fifo %p count %d buf %p\n",
166 'T', epnum, fifo, len, buf);
169 musb_writel(ep_conf, TUSB_EP_TX_OFFSET,
170 TUSB_EP_CONFIG_XFR_SIZE(len));
172 musb_writel(ep_conf, 0, TUSB_EP0_CONFIG_DIR_TX |
173 TUSB_EP0_CONFIG_XFR_SIZE(len));
175 if (likely((0x01 & (unsigned long) buf) == 0)) {
177 /* Best case is 32bit-aligned destination address */
178 if ((0x02 & (unsigned long) buf) == 0) {
180 writesl(fifo, buf, len >> 2);
181 buf += (len & ~0x03);
189 /* Cannot use writesw, fifo is 32-bit */
190 for (i = 0; i < (len >> 2); i++) {
191 val = (u32)(*(u16 *)buf);
193 val |= (*(u16 *)buf) << 16;
195 musb_writel(fifo, 0, val);
203 tusb_fifo_write_unaligned(fifo, buf, len);
206 void musb_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *buf)
208 void __iomem *ep_conf = hw_ep->conf;
209 void __iomem *fifo = hw_ep->fifo;
210 u8 epnum = hw_ep->bLocalEnd;
212 DBG(4, "%cX ep%d fifo %p count %d buf %p\n",
213 'R', epnum, fifo, len, buf);
216 musb_writel(ep_conf, TUSB_EP_RX_OFFSET,
217 TUSB_EP_CONFIG_XFR_SIZE(len));
219 musb_writel(ep_conf, 0, TUSB_EP0_CONFIG_XFR_SIZE(len));
221 if (likely((0x01 & (unsigned long) buf) == 0)) {
223 /* Best case is 32bit-aligned destination address */
224 if ((0x02 & (unsigned long) buf) == 0) {
226 readsl(fifo, buf, len >> 2);
227 buf += (len & ~0x03);
235 /* Cannot use readsw, fifo is 32-bit */
236 for (i = 0; i < (len >> 2); i++) {
237 val = musb_readl(fifo, 0);
238 *(u16 *)buf = (u16)(val & 0xffff);
240 *(u16 *)buf = (u16)(val >> 16);
249 tusb_fifo_read_unaligned(fifo, buf, len);
252 #ifdef CONFIG_USB_GADGET_MUSB_HDRC
254 /* This is used by gadget drivers, and OTG transceiver logic, allowing
255 * at most mA current to be drawn from VBUS during a Default-B session
256 * (that is, while VBUS exceeds 4.4V). In Default-A (including pure host
257 * mode), or low power Default-B sessions, something else supplies power.
258 * Caller must take care of locking.
260 static int tusb_draw_power(struct otg_transceiver *x, unsigned mA)
262 struct musb *musb = container_of(x, struct musb, xceiv);
263 void __iomem *base = musb->ctrl_base;
266 /* tps65030 seems to consume max 100mA, with maybe 60mA available
267 * (measured on one board) for things other than tps and tusb.
269 * Boards sharing the CPU clock with CLKIN will need to prevent
270 * certain idle sleep states while the USB link is active.
272 * REVISIT we could use VBUS to supply only _one_ of { 1.5V, 3.3V }.
273 * The actual current usage would be very board-specific. For now,
274 * it's simpler to just use an aggregate (also board-specific).
276 if (x->default_a || mA < (musb->min_power << 1))
279 reg = musb_readl(base, TUSB_PRCM_MNGMT);
282 musb->set_clock(musb->clock, 1);
283 musb->is_bus_powered = 1;
284 reg |= TUSB_PRCM_MNGMT_15_SW_EN | TUSB_PRCM_MNGMT_33_SW_EN;
286 musb->is_bus_powered = 0;
287 reg &= ~(TUSB_PRCM_MNGMT_15_SW_EN | TUSB_PRCM_MNGMT_33_SW_EN);
289 musb->set_clock(musb->clock, 0);
291 musb_writel(base, TUSB_PRCM_MNGMT, reg);
293 DBG(2, "draw max %d mA VBUS\n", mA);
298 #define tusb_draw_power NULL
301 /* workaround for issue 13: change clock during chip idle
302 * (to be fixed in rev3 silicon) ... symptoms include disconnect
303 * or looping suspend/resume cycles
305 static void tusb_set_clock_source(struct musb *musb, unsigned mode)
307 void __iomem *base = musb->ctrl_base;
310 reg = musb_readl(base, TUSB_PRCM_CONF);
311 reg &= ~TUSB_PRCM_CONF_SYS_CLKSEL(0x3);
313 /* 0 = refclk (clkin, XI)
314 * 1 = PHY 60 MHz (internal PLL)
319 reg |= TUSB_PRCM_CONF_SYS_CLKSEL(mode & 0x3);
321 musb_writel(base, TUSB_PRCM_CONF, reg);
323 // FIXME tusb6010_platform_retime(mode == 0);
327 * Idle TUSB6010 until next wake-up event; NOR access always wakes.
328 * Other code ensures that we idle unless we're connected _and_ the
329 * USB link is not suspended ... and tells us the relevant wakeup
330 * events. SW_EN for voltage is handled separately.
332 static void tusb_allow_idle(struct musb *musb, u32 wakeup_enables)
334 void __iomem *base = musb->ctrl_base;
337 if ((wakeup_enables & TUSB_PRCM_WBUS)
338 && (tusb_get_revision(musb) == TUSB_REV_30))
339 tusb_wbus_quirk(musb, 1);
341 tusb_set_clock_source(musb, 0);
343 wakeup_enables |= TUSB_PRCM_WNORCS;
344 musb_writel(base, TUSB_PRCM_WAKEUP_MASK, ~wakeup_enables);
346 /* REVISIT writeup of WID implies that if WID set and ID is grounded,
347 * TUSB_PHY_OTG_CTRL.TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP must be cleared.
348 * Presumably that's mostly to save power, hence WID is immaterial ...
351 reg = musb_readl(base, TUSB_PRCM_MNGMT);
352 /* issue 4: when driving vbus, use hipower (vbus_det) comparator */
353 if (is_host_active(musb)) {
354 reg |= TUSB_PRCM_MNGMT_OTG_VBUS_DET_EN;
355 reg &= ~TUSB_PRCM_MNGMT_OTG_SESS_END_EN;
357 reg |= TUSB_PRCM_MNGMT_OTG_SESS_END_EN;
358 reg &= ~TUSB_PRCM_MNGMT_OTG_VBUS_DET_EN;
360 reg |= TUSB_PRCM_MNGMT_PM_IDLE | TUSB_PRCM_MNGMT_DEV_IDLE;
361 musb_writel(base, TUSB_PRCM_MNGMT, reg);
363 DBG(6, "idle, wake on %02x\n", wakeup_enables);
367 * Updates cable VBUS status. Caller must take care of locking.
369 int musb_platform_get_vbus_status(struct musb *musb)
371 void __iomem *base = musb->ctrl_base;
372 u32 otg_stat, prcm_mngmt;
375 otg_stat = musb_readl(base, TUSB_DEV_OTG_STAT);
376 prcm_mngmt = musb_readl(base, TUSB_PRCM_MNGMT);
378 /* Temporarily enable VBUS detection if it was disabled for
379 * suspend mode. Unless it's enabled otg_stat and devctl will
380 * not show correct VBUS state.
382 if (!(prcm_mngmt & TUSB_PRCM_MNGMT_OTG_VBUS_DET_EN)) {
383 u32 tmp = prcm_mngmt;
384 tmp |= TUSB_PRCM_MNGMT_OTG_VBUS_DET_EN;
385 musb_writel(base, TUSB_PRCM_MNGMT, tmp);
386 otg_stat = musb_readl(base, TUSB_DEV_OTG_STAT);
387 musb_writel(base, TUSB_PRCM_MNGMT, prcm_mngmt);
390 if (otg_stat & TUSB_DEV_OTG_STAT_VBUS_VALID)
396 static struct timer_list musb_idle_timer;
398 static void musb_do_idle(unsigned long _musb)
400 struct musb *musb = (void *)_musb;
403 spin_lock_irqsave(&musb->Lock, flags);
404 if (!musb->is_active) {
407 #ifdef CONFIG_USB_MUSB_HDRC_HCD
408 /* wait until khubd handles port change status */
409 if (is_host_active(musb) && (musb->port1_status >> 16))
413 #ifdef CONFIG_USB_GADGET_MUSB_HDRC
414 if (is_peripheral_enabled(musb) && !musb->pGadgetDriver)
417 wakeups = TUSB_PRCM_WHOSTDISCON
420 if (is_otg_enabled(musb))
421 wakeups |= TUSB_PRCM_WID;
424 wakeups = TUSB_PRCM_WHOSTDISCON | TUSB_PRCM_WBUS;
426 tusb_allow_idle(musb, wakeups);
429 spin_unlock_irqrestore(&musb->Lock, flags);
433 * Maybe put TUSB6010 into idle mode mode depending on USB link status,
434 * like "disconnected" or "suspended". We'll be woken out of it by
435 * connect, resume, or disconnect.
437 * Needs to be called as the last function everywhere where there is
438 * register access to TUSB6010 because of NOR flash wake-up.
439 * Caller should own controller spinlock.
441 * Delay because peripheral enables D+ pullup 3msec after SE0, and
442 * we don't want to treat that full speed J as a wakeup event.
443 * ... peripherals must draw only suspend current after 10 msec.
445 void musb_platform_try_idle(struct musb *musb)
448 del_timer(&musb_idle_timer);
450 mod_timer(&musb_idle_timer, jiffies + msecs_to_jiffies(3));
453 /* ticks of 60 MHz clock */
454 #define DEVCLOCK 60000000
455 #define OTG_TIMER_MS(msecs) ((msecs) \
456 ? (TUSB_DEV_OTG_TIMER_VAL((DEVCLOCK/1000)*(msecs)) \
457 | TUSB_DEV_OTG_TIMER_ENABLE) \
460 static void tusb_source_power(struct musb *musb, int is_on)
462 void __iomem *base = musb->ctrl_base;
463 u32 conf, prcm, timer;
466 /* HDRC controls CPEN, but beware current surges during device
467 * connect. They can trigger transient overcurrent conditions
468 * that must be ignored.
471 prcm = musb_readl(base, TUSB_PRCM_MNGMT);
472 conf = musb_readl(base, TUSB_DEV_CONF);
473 devctl = musb_readb(musb->pRegs, MGC_O_HDRC_DEVCTL);
477 timer = OTG_TIMER_MS(OTG_TIME_A_WAIT_VRISE);
479 musb->xceiv.default_a = 1;
480 musb->xceiv.state = OTG_STATE_A_WAIT_VRISE;
481 devctl |= MGC_M_DEVCTL_SESSION;
483 conf |= TUSB_DEV_CONF_USB_HOST_MODE;
489 /* NOTE: we're skipping A_WAIT_VFALL -> A_IDLE and
490 * jumping right to B_IDLE...
493 musb->xceiv.default_a = 0;
494 musb->xceiv.state = OTG_STATE_B_IDLE;
495 devctl &= ~MGC_M_DEVCTL_SESSION;
497 conf &= ~TUSB_DEV_CONF_USB_HOST_MODE;
500 prcm &= ~(TUSB_PRCM_MNGMT_15_SW_EN | TUSB_PRCM_MNGMT_33_SW_EN);
502 musb_writel(base, TUSB_PRCM_MNGMT, prcm);
503 musb_writel(base, TUSB_DEV_OTG_TIMER, timer);
504 musb_writel(base, TUSB_DEV_CONF, conf);
505 musb_writeb(musb->pRegs, MGC_O_HDRC_DEVCTL, devctl);
507 DBG(1, "VBUS %s, devctl %02x otg %3x conf %08x prcm %08x\n",
508 otg_state_string(musb),
509 musb_readb(musb->pRegs, MGC_O_HDRC_DEVCTL),
510 musb_readl(base, TUSB_DEV_OTG_STAT),
515 * Sets the mode to OTG, peripheral or host by changing the ID detection.
516 * Caller must take care of locking.
518 * Note that if a mini-A cable is plugged in the ID line will stay down as
519 * the weak ID pull-up is not able to pull the ID up.
521 * REVISIT: It would be possible to add support for changing between host
522 * and peripheral modes in non-OTG configurations by reconfiguring hardware
523 * and then setting musb->board_mode. For now, only support OTG mode.
525 void musb_platform_set_mode(struct musb *musb, u8 musb_mode)
527 void __iomem *base = musb->ctrl_base;
528 u32 otg_stat, phy_otg_ena, phy_otg_ctrl, dev_conf;
531 if (musb->board_mode != MUSB_OTG) {
532 ERR("Changing mode currently only supported in OTG mode\n");
536 otg_stat = musb_readl(base, TUSB_DEV_OTG_STAT);
537 phy_otg_ena = musb_readl(base, TUSB_PHY_OTG_CTRL_ENABLE);
538 phy_otg_ctrl = musb_readl(base, TUSB_PHY_OTG_CTRL);
539 dev_conf = musb_readl(base, TUSB_DEV_CONF);
543 #ifdef CONFIG_USB_MUSB_HDRC_HCD
544 case MUSB_HOST: /* Disable PHY ID detect, ground ID */
545 if (!(otg_stat & TUSB_DEV_OTG_STAT_ID_STATUS)) {
546 ERR("Already in host mode otg_stat: %08x\n", otg_stat);
549 phy_otg_ena |= TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP;
550 phy_otg_ctrl &= ~TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP;
551 dev_conf |= TUSB_DEV_CONF_ID_SEL;
552 dev_conf &= ~TUSB_DEV_CONF_SOFT_ID;
557 #ifdef CONFIG_USB_GADGET_MUSB_HDRC
558 case MUSB_PERIPHERAL: /* Disable PHY ID detect, keep ID pull-up on */
559 if (otg_stat & TUSB_DEV_OTG_STAT_ID_STATUS) {
560 ERR("Already in peripheral mode otg_stat: %08x\n",
564 phy_otg_ena |= TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP;
565 phy_otg_ctrl |= TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP;
566 dev_conf |= (TUSB_DEV_CONF_ID_SEL | TUSB_DEV_CONF_SOFT_ID);
570 #ifdef CONFIG_USB_MUSB_OTG
571 case MUSB_OTG: /* Use PHY ID detection */
572 phy_otg_ena |= TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP;
573 phy_otg_ctrl |= TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP;
574 dev_conf &= ~(TUSB_DEV_CONF_ID_SEL | TUSB_DEV_CONF_SOFT_ID);
579 DBG(2, "Trying to set unknown mode %i\n", musb_mode);
582 musb_writel(base, TUSB_PHY_OTG_CTRL_ENABLE,
583 TUSB_PHY_OTG_CTRL_WRPROTECT | phy_otg_ena);
584 musb_writel(base, TUSB_PHY_OTG_CTRL,
585 TUSB_PHY_OTG_CTRL_WRPROTECT | phy_otg_ctrl);
586 musb_writel(base, TUSB_DEV_CONF, dev_conf);
588 otg_stat = musb_readl(base, TUSB_DEV_OTG_STAT);
589 if ((musb_mode == MUSB_PERIPHERAL) &&
590 !(otg_stat & TUSB_DEV_OTG_STAT_ID_STATUS))
591 ERR("Cannot be peripheral with mini-A cable "
592 "otg_stat: %08x\n", otg_stat);
596 tusb_otg_ints(struct musb *musb, u32 int_src, void __iomem *base)
598 u32 otg_stat = musb_readl(base, TUSB_DEV_OTG_STAT);
601 if ((int_src & TUSB_INT_SRC_ID_STATUS_CHNG)) {
604 if (is_otg_enabled(musb))
605 default_a = !(otg_stat & TUSB_DEV_OTG_STAT_ID_STATUS);
607 default_a = is_host_enabled(musb);
608 DBG(2, "Default-%c\n", default_a ? 'A' : 'B');
609 musb->xceiv.default_a = default_a;
610 tusb_source_power(musb, default_a);
613 /* VBUS state change */
614 if (int_src & TUSB_INT_SRC_VBUS_SENSE_CHNG) {
616 /* B-dev state machine: no vbus ~= disconnect */
617 if ((is_otg_enabled(musb) && !musb->xceiv.default_a)
618 || !is_host_enabled(musb)) {
619 #ifdef CONFIG_USB_MUSB_HDRC_HCD
620 // ? musb_root_disconnect(musb);
621 musb->port1_status &=
622 ~(USB_PORT_STAT_CONNECTION
623 | USB_PORT_STAT_ENABLE
624 | USB_PORT_STAT_LOW_SPEED
625 | USB_PORT_STAT_HIGH_SPEED
630 if (otg_stat & TUSB_DEV_OTG_STAT_SESS_END) {
631 DBG(1, "Forcing disconnect (no interrupt)\n");
632 if (musb->xceiv.state != OTG_STATE_B_IDLE) {
633 /* INTR_DISCONNECT can hide... */
634 musb->xceiv.state = OTG_STATE_B_IDLE;
635 musb->int_usb |= MGC_M_INTR_DISCONNECT;
639 DBG(2, "vbus change, %s, otg %03x\n",
640 otg_state_string(musb), otg_stat);
641 schedule_work(&musb->irq_work);
643 } else /* A-dev state machine */ {
644 DBG(2, "vbus change, %s, otg %03x\n",
645 otg_state_string(musb), otg_stat);
647 switch (musb->xceiv.state) {
648 case OTG_STATE_A_WAIT_VRISE:
649 /* ignore; A-session-valid < VBUS_VALID/2,
650 * we monitor this with the timer
653 case OTG_STATE_A_WAIT_VFALL:
654 /* REVISIT this irq triggers during short
655 * spikes causet by enumeration ...
657 if (musb->vbuserr_retry) {
658 musb->vbuserr_retry--;
659 tusb_source_power(musb, 1);
668 /* OTG timer expiration */
669 if (int_src & TUSB_INT_SRC_OTG_TIMEOUT) {
672 DBG(4, "%s timer, %03x\n", otg_state_string(musb), otg_stat);
674 switch (musb->xceiv.state) {
675 case OTG_STATE_A_WAIT_VRISE:
676 /* VBUS has probably been valid for a while now,
677 * but may well have bounced out of range a bit
679 devctl = musb_readb(musb->pRegs, MGC_O_HDRC_DEVCTL);
680 if (otg_stat & TUSB_DEV_OTG_STAT_VBUS_VALID) {
683 if ((devctl & MGC_M_DEVCTL_VBUS)
684 != MGC_M_DEVCTL_VBUS) {
685 DBG(2, "devctl %02x\n", devctl);
688 musb->xceiv.state = OTG_STATE_A_WAIT_BCON;
690 /* REVISIT: if nothing is connected yet,
691 * mark controller as inactive so that
692 * we can suspend the TUSB chip.
695 /* timeout 0 == infinite (like non-OTG hosts) */
696 timer = OTG_TIMER_MS(OTG_TIME_A_WAIT_BCON);
698 musb_writel(base, TUSB_DEV_OTG_TIMER,
701 /* REVISIT report overcurrent to hub? */
702 ERR("vbus too slow, devctl %02x\n", devctl);
703 tusb_source_power(musb, 0);
706 case OTG_STATE_A_WAIT_BCON:
707 if (OTG_TIME_A_WAIT_BCON)
708 tusb_source_power(musb, 0);
710 case OTG_STATE_A_SUSPEND:
712 case OTG_STATE_B_WAIT_ACON:
720 static irqreturn_t tusb_interrupt(int irq, void *__hci)
722 struct musb *musb = __hci;
723 void __iomem *base = musb->ctrl_base;
725 u32 int_mask, int_src;
727 spin_lock_irqsave(&musb->Lock, flags);
729 /* Mask all interrupts to allow using both edge and level GPIO irq */
730 int_mask = musb_readl(base, TUSB_INT_MASK);
731 musb_writel(base, TUSB_INT_MASK, ~TUSB_INT_MASK_RESERVED_BITS);
733 int_src = musb_readl(base, TUSB_INT_SRC) & ~TUSB_INT_SRC_RESERVED_BITS;
734 DBG(3, "TUSB IRQ %08x\n", int_src);
736 musb->int_usb = (u8) int_src;
738 /* Acknowledge wake-up source interrupts */
739 if (int_src & TUSB_INT_SRC_DEV_WAKEUP) {
743 if (tusb_get_revision(musb) == TUSB_REV_30)
744 tusb_wbus_quirk(musb, 0);
746 /* there are issues re-locking the PLL on wakeup ... */
748 /* work around issue 8 */
749 for (i = 0xf7f7f7; i > 0xf7f7f7 - 1000; i--) {
750 musb_writel(base, TUSB_SCRATCH_PAD, 0);
751 musb_writel(base, TUSB_SCRATCH_PAD, i);
752 reg = musb_readl(base, TUSB_SCRATCH_PAD);
755 DBG(6, "TUSB NOR not ready\n");
758 /* work around issue 13 (2nd half) */
759 tusb_set_clock_source(musb, 1);
761 reg = musb_readl(base, TUSB_PRCM_WAKEUP_SOURCE);
762 musb_writel(base, TUSB_PRCM_WAKEUP_CLEAR, reg);
763 if (reg & ~TUSB_PRCM_WNORCS) {
765 schedule_work(&musb->irq_work);
767 DBG(3, "wake %sactive %02x\n",
768 musb->is_active ? "" : "in", reg);
770 // REVISIT host side TUSB_PRCM_WHOSTDISCON, TUSB_PRCM_WBUS
773 /* OTG state change reports (annoyingly) not issued by Mentor core */
774 if (int_src & (TUSB_INT_SRC_VBUS_SENSE_CHNG
775 | TUSB_INT_SRC_OTG_TIMEOUT
776 | TUSB_INT_SRC_ID_STATUS_CHNG))
777 tusb_otg_ints(musb, int_src, base);
779 /* TX dma callback must be handled here, RX dma callback is
780 * handled in tusb_omap_dma_cb.
782 if ((int_src & TUSB_INT_SRC_TXRX_DMA_DONE)) {
783 u32 dma_src = musb_readl(base, TUSB_DMA_INT_SRC);
784 u32 real_dma_src = musb_readl(base, TUSB_DMA_INT_MASK);
786 DBG(3, "DMA IRQ %08x\n", dma_src);
787 real_dma_src = ~real_dma_src & dma_src;
788 if (tusb_dma_omap() && real_dma_src) {
789 int tx_source = (real_dma_src & 0xffff);
792 for (i = 1; i <= 15; i++) {
793 if (tx_source & (1 << i)) {
794 DBG(3, "completing ep%i %s\n", i, "tx");
795 musb_dma_completion(musb, i, 1);
799 musb_writel(base, TUSB_DMA_INT_CLEAR, dma_src);
802 /* EP interrupts. In OCP mode tusb6010 mirrors the MUSB * interrupts */
803 if (int_src & (TUSB_INT_SRC_USB_IP_TX | TUSB_INT_SRC_USB_IP_RX)) {
804 u32 musb_src = musb_readl(base, TUSB_USBIP_INT_SRC);
806 musb_writel(base, TUSB_USBIP_INT_CLEAR, musb_src);
807 musb->int_rx = (((musb_src >> 16) & 0xffff) << 1);
808 musb->int_tx = (musb_src & 0xffff);
810 musb->int_rx = musb->int_tx = 0;
812 if (int_src & (TUSB_INT_SRC_USB_IP_TX | TUSB_INT_SRC_USB_IP_RX | 0xff))
813 musb_interrupt(musb);
815 /* Acknowledge TUSB interrupts. Clear only non-reserved bits */
816 musb_writel(base, TUSB_INT_SRC_CLEAR,
817 int_src & ~TUSB_INT_MASK_RESERVED_BITS);
819 musb_platform_try_idle(musb);
821 musb_writel(base, TUSB_INT_MASK, int_mask);
822 spin_unlock_irqrestore(&musb->Lock, flags);
830 * Enables TUSB6010. Caller must take care of locking.
832 * - Check what is unnecessary in MGC_HdrcStart()
834 void musb_platform_enable(struct musb * musb)
836 void __iomem *base = musb->ctrl_base;
838 /* Setup TUSB6010 main interrupt mask. Enable all interrupts except SOF.
839 * REVISIT: Enable and deal with TUSB_INT_SRC_USB_IP_SOF */
840 musb_writel(base, TUSB_INT_MASK, TUSB_INT_SRC_USB_IP_SOF);
842 /* Setup TUSB interrupt, disable DMA and GPIO interrupts */
843 musb_writel(base, TUSB_USBIP_INT_MASK, 0);
844 musb_writel(base, TUSB_DMA_INT_MASK, 0x7fffffff);
845 musb_writel(base, TUSB_GPIO_INT_MASK, 0x1ff);
847 /* Clear all subsystem interrups */
848 musb_writel(base, TUSB_USBIP_INT_CLEAR, 0x7fffffff);
849 musb_writel(base, TUSB_DMA_INT_CLEAR, 0x7fffffff);
850 musb_writel(base, TUSB_GPIO_INT_CLEAR, 0x1ff);
852 /* Acknowledge pending interrupt(s) */
853 musb_writel(base, TUSB_INT_SRC_CLEAR, ~TUSB_INT_MASK_RESERVED_BITS);
855 /* Only 0 clock cycles for minimum interrupt de-assertion time and
856 * interrupt polarity active low seems to work reliably here */
857 musb_writel(base, TUSB_INT_CTRL_CONF,
858 TUSB_INT_CTRL_CONF_INT_RELCYC(0));
860 set_irq_type(musb->nIrq, IRQ_TYPE_LEVEL_LOW);
862 /* maybe force into the Default-A OTG state machine */
863 if (!(musb_readl(base, TUSB_DEV_OTG_STAT)
864 & TUSB_DEV_OTG_STAT_ID_STATUS))
865 musb_writel(base, TUSB_INT_SRC_SET,
866 TUSB_INT_SRC_ID_STATUS_CHNG);
868 if (is_dma_capable() && dma_off)
869 printk(KERN_WARNING "%s %s: dma not reactivated\n",
870 __FILE__, __FUNCTION__);
876 * Disables TUSB6010. Caller must take care of locking.
878 void musb_platform_disable(struct musb *musb)
880 void __iomem *base = musb->ctrl_base;
882 /* FIXME stop DMA, IRQs, timers, ... */
884 /* disable all IRQs */
885 musb_writel(base, TUSB_INT_MASK, ~TUSB_INT_MASK_RESERVED_BITS);
886 musb_writel(base, TUSB_USBIP_INT_MASK, 0);
887 musb_writel(base, TUSB_DMA_INT_MASK, 0x7fffffff);
888 musb_writel(base, TUSB_GPIO_INT_MASK, 0x1ff);
890 del_timer(&musb_idle_timer);
892 if (is_dma_capable() && !dma_off) {
893 printk(KERN_WARNING "%s %s: dma still active\n",
894 __FILE__, __FUNCTION__);
900 * Sets up TUSB6010 CPU interface specific signals and registers
901 * Note: Settings optimized for OMAP24xx
903 static void __init tusb_setup_cpu_interface(struct musb *musb)
905 void __iomem *base = musb->ctrl_base;
908 * Disable GPIO[5:0] pullups (used as output DMA requests)
909 * Don't disable GPIO[7:6] as they are needed for wake-up.
911 musb_writel(base, TUSB_PULLUP_1_CTRL, 0x0000003F);
913 /* Disable all pullups on NOR IF, DMAREQ0 and DMAREQ1 */
914 musb_writel(base, TUSB_PULLUP_2_CTRL, 0x01FFFFFF);
916 /* Turn GPIO[5:0] to DMAREQ[5:0] signals */
917 musb_writel(base, TUSB_GPIO_CONF, TUSB_GPIO_CONF_DMAREQ(0x3f));
919 /* Burst size 16x16 bits, all six DMA requests enabled, DMA request
920 * de-assertion time 2 system clocks p 62 */
921 musb_writel(base, TUSB_DMA_REQ_CONF,
922 TUSB_DMA_REQ_CONF_BURST_SIZE(2) |
923 TUSB_DMA_REQ_CONF_DMA_REQ_EN(0x3f) |
924 TUSB_DMA_REQ_CONF_DMA_REQ_ASSER(2));
926 /* Set 0 wait count for synchronous burst access */
927 musb_writel(base, TUSB_WAIT_COUNT, 1);
930 static int __init tusb_start(struct musb *musb)
932 void __iomem *base = musb->ctrl_base;
937 if (musb->board_set_power)
938 ret = musb->board_set_power(1);
940 printk(KERN_ERR "tusb: Cannot enable TUSB6010\n");
944 spin_lock_irqsave(&musb->Lock, flags);
946 if (musb_readl(base, TUSB_PROD_TEST_RESET) !=
947 TUSB_PROD_TEST_RESET_VAL) {
948 printk(KERN_ERR "tusb: Unable to detect TUSB6010\n");
952 ret = tusb_print_revision(musb);
954 printk(KERN_ERR "tusb: Unsupported TUSB6010 revision %i\n",
959 /* The uint bit for "USB non-PDR interrupt enable" has to be 1 when
960 * NOR FLASH interface is used */
961 musb_writel(base, TUSB_VLYNQ_CTRL, 8);
963 /* Select PHY free running 60MHz as a system clock */
964 tusb_set_clock_source(musb, 1);
966 /* VBus valid timer 1us, disable DFT/Debug and VLYNQ clocks for
967 * power saving, enable VBus detect and session end comparators,
968 * enable IDpullup, enable VBus charging */
969 musb_writel(base, TUSB_PRCM_MNGMT,
970 TUSB_PRCM_MNGMT_VBUS_VALID_TIMER(0xa) |
971 TUSB_PRCM_MNGMT_VBUS_VALID_FLT_EN |
972 TUSB_PRCM_MNGMT_OTG_SESS_END_EN |
973 TUSB_PRCM_MNGMT_OTG_VBUS_DET_EN |
974 TUSB_PRCM_MNGMT_OTG_ID_PULLUP);
975 tusb_setup_cpu_interface(musb);
977 /* simplify: always sense/pullup ID pins, as if in OTG mode */
978 reg = musb_readl(base, TUSB_PHY_OTG_CTRL_ENABLE);
979 reg |= TUSB_PHY_OTG_CTRL_WRPROTECT | TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP;
980 musb_writel(base, TUSB_PHY_OTG_CTRL_ENABLE, reg);
982 reg = musb_readl(base, TUSB_PHY_OTG_CTRL);
983 reg |= TUSB_PHY_OTG_CTRL_WRPROTECT | TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP;
984 musb_writel(base, TUSB_PHY_OTG_CTRL, reg);
986 spin_unlock_irqrestore(&musb->Lock, flags);
991 spin_unlock_irqrestore(&musb->Lock, flags);
993 if (musb->board_set_power)
994 musb->board_set_power(0);
999 int __init musb_platform_init(struct musb *musb)
1001 struct platform_device *pdev;
1002 struct resource *mem;
1006 pdev = to_platform_device(musb->controller);
1008 /* dma address for async dma */
1009 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1010 musb->async = mem->start;
1012 /* dma address for sync dma */
1013 mem = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1015 pr_debug("no sync dma resource?\n");
1018 musb->sync = mem->start;
1020 sync = ioremap(mem->start, mem->end - mem->start + 1);
1022 pr_debug("ioremap for sync failed\n");
1025 musb->sync_va = sync;
1027 /* Offsets from base: VLYNQ at 0x000, MUSB regs at 0x400,
1028 * FIFOs at 0x600, TUSB at 0x800
1030 musb->pRegs += TUSB_BASE_OFFSET;
1032 ret = tusb_start(musb);
1034 printk(KERN_ERR "Could not start tusb6010 (%d)\n",
1038 musb->isr = tusb_interrupt;
1040 if (is_host_enabled(musb))
1041 musb->board_set_vbus = tusb_source_power;
1042 if (is_peripheral_enabled(musb))
1043 musb->xceiv.set_power = tusb_draw_power;
1045 setup_timer(&musb_idle_timer, musb_do_idle, (unsigned long) musb);
1050 int musb_platform_exit(struct musb *musb)
1052 del_timer_sync(&musb_idle_timer);
1054 if (musb->board_set_power)
1055 musb->board_set_power(0);
1057 iounmap(musb->sync_va);