2 * TUSB6010 USB 2.0 OTG Dual Role controller
4 * Copyright (C) 2006 Nokia Corporation
5 * Jarkko Nikula <jarkko.nikula@nokia.com>
6 * Tony Lindgren <tony@atomide.com>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
13 * - Driver assumes that interface to external host (main CPU) is
14 * configured for NOR FLASH interface instead of VLYNQ serial
18 #include <linux/module.h>
19 #include <linux/kernel.h>
20 #include <linux/errno.h>
21 #include <linux/init.h>
22 #include <linux/usb.h>
23 #include <linux/irq.h>
24 #include <linux/platform_device.h>
28 static void tusb_source_power(struct musb *musb, int is_on);
31 * Checks the revision. We need to use the DMA register as 3.0 does not
32 * have correct versions for TUSB_PRCM_REV or TUSB_INT_CTRL_REV.
34 static u8 tusb_get_revision(struct musb *musb)
36 void __iomem *base = musb->ctrl_base;
38 return musb_readl(base, TUSB_DMA_CTRL_REV) & 0xff;
41 #define TUSB_REV_MAJOR(reg_val) ((reg_val >> 4) & 0xf)
42 #define TUSB_REV_MINOR(reg_val) (reg_val & 0xf)
44 static int __init tusb_print_revision(struct musb *musb)
46 void __iomem *base = musb->ctrl_base;
48 pr_info("tusb: Revisions: %s%i.%i %s%i.%i %s%i.%i %s%i.%i\n",
50 TUSB_REV_MAJOR(musb_readl(base, TUSB_PRCM_REV)),
51 TUSB_REV_MINOR(musb_readl(base, TUSB_PRCM_REV)),
53 TUSB_REV_MAJOR(musb_readl(base, TUSB_INT_CTRL_REV)),
54 TUSB_REV_MINOR(musb_readl(base, TUSB_INT_CTRL_REV)),
56 TUSB_REV_MAJOR(musb_readl(base, TUSB_GPIO_REV)),
57 TUSB_REV_MINOR(musb_readl(base, TUSB_GPIO_REV)),
59 TUSB_REV_MAJOR(musb_readl(base, TUSB_DMA_CTRL_REV)),
60 TUSB_REV_MINOR(musb_readl(base, TUSB_DMA_CTRL_REV)));
62 return TUSB_REV_MAJOR(musb_readl(base, TUSB_INT_CTRL_REV));
65 #define WBUS_QUIRK_MASK (TUSB_PHY_OTG_CTRL_TESTM2 | TUSB_PHY_OTG_CTRL_TESTM1 \
66 | TUSB_PHY_OTG_CTRL_TESTM0)
69 * Workaround for spontaneous WBUS wake-up issue #2 for tusb3.0.
70 * Disables power detection in PHY for the duration of idle.
72 static void tusb_wbus_quirk(struct musb *musb, int enabled)
74 void __iomem *base = musb->ctrl_base;
75 static u32 phy_otg_ctrl = 0, phy_otg_ena = 0;
79 phy_otg_ctrl = musb_readl(base, TUSB_PHY_OTG_CTRL);
80 phy_otg_ena = musb_readl(base, TUSB_PHY_OTG_CTRL_ENABLE);
81 tmp = TUSB_PHY_OTG_CTRL_WRPROTECT
82 | phy_otg_ena | WBUS_QUIRK_MASK;
83 musb_writel(base, TUSB_PHY_OTG_CTRL, tmp);
84 tmp = phy_otg_ena & ~WBUS_QUIRK_MASK;
85 tmp |= TUSB_PHY_OTG_CTRL_WRPROTECT | TUSB_PHY_OTG_CTRL_TESTM2;
86 musb_writel(base, TUSB_PHY_OTG_CTRL_ENABLE, tmp);
87 DBG(2, "Enabled tusb wbus quirk ctrl %08x ena %08x\n",
88 musb_readl(base, TUSB_PHY_OTG_CTRL),
89 musb_readl(base, TUSB_PHY_OTG_CTRL_ENABLE));
90 } else if (musb_readl(base, TUSB_PHY_OTG_CTRL_ENABLE)
91 & TUSB_PHY_OTG_CTRL_TESTM2) {
92 tmp = TUSB_PHY_OTG_CTRL_WRPROTECT | phy_otg_ctrl;
93 musb_writel(base, TUSB_PHY_OTG_CTRL, tmp);
94 tmp = TUSB_PHY_OTG_CTRL_WRPROTECT | phy_otg_ena;
95 musb_writel(base, TUSB_PHY_OTG_CTRL_ENABLE, tmp);
96 DBG(2, "Disabled tusb wbus quirk ctrl %08x ena %08x\n",
97 musb_readl(base, TUSB_PHY_OTG_CTRL),
98 musb_readl(base, TUSB_PHY_OTG_CTRL_ENABLE));
105 * TUSB 6010 may use a parallel bus that doesn't support byte ops;
106 * so both loading and unloading FIFOs need explicit byte counts.
110 tusb_fifo_write_unaligned(void __iomem *fifo, const u8 *buf, u16 len)
116 for (i = 0; i < (len >> 2); i++) {
117 memcpy(&val, buf, 4);
118 musb_writel(fifo, 0, val);
124 /* Write the rest 1 - 3 bytes to FIFO */
125 memcpy(&val, buf, len);
126 musb_writel(fifo, 0, val);
130 static inline void tusb_fifo_read_unaligned(void __iomem *fifo,
131 void __iomem *buf, u16 len)
137 for (i = 0; i < (len >> 2); i++) {
138 val = musb_readl(fifo, 0);
139 memcpy(buf, &val, 4);
145 /* Read the rest 1 - 3 bytes from FIFO */
146 val = musb_readl(fifo, 0);
147 memcpy(buf, &val, len);
151 void musb_write_fifo(struct musb_hw_ep *hw_ep, u16 len, const u8 *buf)
153 void __iomem *ep_conf = hw_ep->conf;
154 void __iomem *fifo = hw_ep->fifo;
155 u8 epnum = hw_ep->bLocalEnd;
159 DBG(4, "%cX ep%d fifo %p count %d buf %p\n",
160 'T', epnum, fifo, len, buf);
163 musb_writel(ep_conf, TUSB_EP_TX_OFFSET,
164 TUSB_EP_CONFIG_XFR_SIZE(len));
166 musb_writel(ep_conf, 0, TUSB_EP0_CONFIG_DIR_TX |
167 TUSB_EP0_CONFIG_XFR_SIZE(len));
169 if (likely((0x01 & (unsigned long) buf) == 0)) {
171 /* Best case is 32bit-aligned destination address */
172 if ((0x02 & (unsigned long) buf) == 0) {
174 writesl(fifo, buf, len >> 2);
175 buf += (len & ~0x03);
183 /* Cannot use writesw, fifo is 32-bit */
184 for (i = 0; i < (len >> 2); i++) {
185 val = (u32)(*(u16 *)buf);
187 val |= (*(u16 *)buf) << 16;
189 musb_writel(fifo, 0, val);
197 tusb_fifo_write_unaligned(fifo, buf, len);
200 void musb_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *buf)
202 void __iomem *ep_conf = hw_ep->conf;
203 void __iomem *fifo = hw_ep->fifo;
204 u8 epnum = hw_ep->bLocalEnd;
206 DBG(4, "%cX ep%d fifo %p count %d buf %p\n",
207 'R', epnum, fifo, len, buf);
210 musb_writel(ep_conf, TUSB_EP_RX_OFFSET,
211 TUSB_EP_CONFIG_XFR_SIZE(len));
213 musb_writel(ep_conf, 0, TUSB_EP0_CONFIG_XFR_SIZE(len));
215 if (likely((0x01 & (unsigned long) buf) == 0)) {
217 /* Best case is 32bit-aligned destination address */
218 if ((0x02 & (unsigned long) buf) == 0) {
220 readsl(fifo, buf, len >> 2);
221 buf += (len & ~0x03);
229 /* Cannot use readsw, fifo is 32-bit */
230 for (i = 0; i < (len >> 2); i++) {
231 val = musb_readl(fifo, 0);
232 *(u16 *)buf = (u16)(val & 0xffff);
234 *(u16 *)buf = (u16)(val >> 16);
243 tusb_fifo_read_unaligned(fifo, buf, len);
246 #ifdef CONFIG_USB_GADGET_MUSB_HDRC
248 /* This is used by gadget drivers, and OTG transceiver logic, allowing
249 * at most mA current to be drawn from VBUS during a Default-B session
250 * (that is, while VBUS exceeds 4.4V). In Default-A (including pure host
251 * mode), or low power Default-B sessions, something else supplies power.
252 * Caller must take care of locking.
254 static int tusb_draw_power(struct otg_transceiver *x, unsigned mA)
256 struct musb *musb = container_of(x, struct musb, xceiv);
257 void __iomem *base = musb->ctrl_base;
260 /* tps65030 seems to consume max 100mA, with maybe 60mA available
261 * (measured on one board) for things other than tps and tusb.
263 * Boards sharing the CPU clock with CLKIN will need to prevent
264 * certain idle sleep states while the USB link is active.
266 * REVISIT we could use VBUS to supply only _one_ of { 1.5V, 3.3V }.
267 * The actual current usage would be very board-specific. For now,
268 * it's simpler to just use an aggregate (also board-specific).
270 if (x->default_a || mA < (musb->min_power << 1))
273 reg = musb_readl(base, TUSB_PRCM_MNGMT);
276 musb->set_clock(musb->clock, 1);
277 musb->is_bus_powered = 1;
278 reg |= TUSB_PRCM_MNGMT_15_SW_EN | TUSB_PRCM_MNGMT_33_SW_EN;
280 musb->is_bus_powered = 0;
281 reg &= ~(TUSB_PRCM_MNGMT_15_SW_EN | TUSB_PRCM_MNGMT_33_SW_EN);
283 musb->set_clock(musb->clock, 0);
285 musb_writel(base, TUSB_PRCM_MNGMT, reg);
287 DBG(2, "draw max %d mA VBUS\n", mA);
292 #define tusb_draw_power NULL
295 /* workaround for issue 13: change clock during chip idle
296 * (to be fixed in rev3 silicon) ... symptoms include disconnect
297 * or looping suspend/resume cycles
299 static void tusb_set_clock_source(struct musb *musb, unsigned mode)
301 void __iomem *base = musb->ctrl_base;
304 reg = musb_readl(base, TUSB_PRCM_CONF);
305 reg &= ~TUSB_PRCM_CONF_SYS_CLKSEL(0x3);
307 /* 0 = refclk (clkin, XI)
308 * 1 = PHY 60 MHz (internal PLL)
313 reg |= TUSB_PRCM_CONF_SYS_CLKSEL(mode & 0x3);
315 musb_writel(base, TUSB_PRCM_CONF, reg);
317 // FIXME tusb6010_platform_retime(mode == 0);
321 * Idle TUSB6010 until next wake-up event; NOR access always wakes.
322 * Other code ensures that we idle unless we're connected _and_ the
323 * USB link is not suspended ... and tells us the relevant wakeup
324 * events. SW_EN for voltage is handled separately.
326 void tusb_allow_idle(struct musb *musb, u32 wakeup_enables)
328 void __iomem *base = musb->ctrl_base;
331 if ((wakeup_enables & TUSB_PRCM_WBUS)
332 && (tusb_get_revision(musb) == TUSB_REV_30))
333 tusb_wbus_quirk(musb, 1);
335 tusb_set_clock_source(musb, 0);
337 wakeup_enables |= TUSB_PRCM_WNORCS;
338 musb_writel(base, TUSB_PRCM_WAKEUP_MASK, ~wakeup_enables);
340 /* REVISIT writeup of WID implies that if WID set and ID is grounded,
341 * TUSB_PHY_OTG_CTRL.TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP must be cleared.
342 * Presumably that's mostly to save power, hence WID is immaterial ...
345 reg = musb_readl(base, TUSB_PRCM_MNGMT);
346 /* issue 4: when driving vbus, use hipower (vbus_det) comparator */
347 if (is_host_active(musb)) {
348 reg |= TUSB_PRCM_MNGMT_OTG_VBUS_DET_EN;
349 reg &= ~TUSB_PRCM_MNGMT_OTG_SESS_END_EN;
351 reg |= TUSB_PRCM_MNGMT_OTG_SESS_END_EN;
352 reg &= ~TUSB_PRCM_MNGMT_OTG_VBUS_DET_EN;
354 reg |= TUSB_PRCM_MNGMT_PM_IDLE | TUSB_PRCM_MNGMT_DEV_IDLE;
355 musb_writel(base, TUSB_PRCM_MNGMT, reg);
357 DBG(6, "idle, wake on %02x\n", wakeup_enables);
361 * Updates cable VBUS status. Caller must take care of locking.
363 int musb_platform_get_vbus_status(struct musb *musb)
365 void __iomem *base = musb->ctrl_base;
366 u32 otg_stat, prcm_mngmt;
369 otg_stat = musb_readl(base, TUSB_DEV_OTG_STAT);
370 prcm_mngmt = musb_readl(base, TUSB_PRCM_MNGMT);
372 /* Temporarily enable VBUS detection if it was disabled for
373 * suspend mode. Unless it's enabled otg_stat and devctl will
374 * not show correct VBUS state.
376 if (!(prcm_mngmt & TUSB_PRCM_MNGMT_OTG_VBUS_DET_EN)) {
377 u32 tmp = prcm_mngmt;
378 tmp |= TUSB_PRCM_MNGMT_OTG_VBUS_DET_EN;
379 musb_writel(base, TUSB_PRCM_MNGMT, tmp);
380 otg_stat = musb_readl(base, TUSB_DEV_OTG_STAT);
381 musb_writel(base, TUSB_PRCM_MNGMT, prcm_mngmt);
384 if (otg_stat & TUSB_DEV_OTG_STAT_VBUS_VALID)
390 static struct timer_list musb_idle_timer;
392 static void musb_do_idle(unsigned long _musb)
394 struct musb *musb = (void *)_musb;
397 spin_lock_irqsave(&musb->Lock, flags);
399 switch (musb->xceiv.state) {
400 case OTG_STATE_A_WAIT_BCON:
401 if ((musb->a_wait_bcon != 0)
402 && (musb->idle_timeout == 0
403 || time_after(jiffies, musb->idle_timeout))) {
404 DBG(4, "Nothing connected %s, turning off VBUS\n",
405 otg_state_string(musb));
406 tusb_source_power(musb, 0);
407 musb->xceiv.state = OTG_STATE_A_IDLE;
415 if (!musb->is_active) {
418 #ifdef CONFIG_USB_MUSB_HDRC_HCD
419 /* wait until khubd handles port change status */
420 if (is_host_active(musb) && (musb->port1_status >> 16))
424 #ifdef CONFIG_USB_GADGET_MUSB_HDRC
425 if (is_peripheral_enabled(musb) && !musb->pGadgetDriver)
428 wakeups = TUSB_PRCM_WHOSTDISCON
431 if (is_otg_enabled(musb))
432 wakeups |= TUSB_PRCM_WID;
435 wakeups = TUSB_PRCM_WHOSTDISCON | TUSB_PRCM_WBUS;
437 tusb_allow_idle(musb, wakeups);
440 spin_unlock_irqrestore(&musb->Lock, flags);
444 * Maybe put TUSB6010 into idle mode mode depending on USB link status,
445 * like "disconnected" or "suspended". We'll be woken out of it by
446 * connect, resume, or disconnect.
448 * Needs to be called as the last function everywhere where there is
449 * register access to TUSB6010 because of NOR flash wake-up.
450 * Caller should own controller spinlock.
452 * Delay because peripheral enables D+ pullup 3msec after SE0, and
453 * we don't want to treat that full speed J as a wakeup event.
454 * ... peripherals must draw only suspend current after 10 msec.
456 void musb_platform_try_idle(struct musb *musb, unsigned long timeout)
458 unsigned long default_timeout = jiffies + msecs_to_jiffies(3);
459 static unsigned long last_timer = 0;
462 timeout = default_timeout;
464 if (musb->is_active) {
465 DBG(4, "%s active, deleting timer\n", otg_state_string(musb));
466 del_timer(&musb_idle_timer);
467 last_timer = jiffies;
471 if (time_after(last_timer, timeout)) {
472 if (!timer_pending(&musb_idle_timer))
473 last_timer = timeout;
475 DBG(4, "Longer idle timer already pending, ignoring\n");
479 last_timer = timeout;
481 DBG(4, "%s inactive, for idle timer for %lu ms\n",
482 otg_state_string(musb),
483 (unsigned long)jiffies_to_msecs(timeout - jiffies));
484 mod_timer(&musb_idle_timer, timeout);
487 /* ticks of 60 MHz clock */
488 #define DEVCLOCK 60000000
489 #define OTG_TIMER_MS(msecs) ((msecs) \
490 ? (TUSB_DEV_OTG_TIMER_VAL((DEVCLOCK/1000)*(msecs)) \
491 | TUSB_DEV_OTG_TIMER_ENABLE) \
494 static void tusb_source_power(struct musb *musb, int is_on)
496 void __iomem *base = musb->ctrl_base;
497 u32 conf, prcm, timer;
500 /* HDRC controls CPEN, but beware current surges during device
501 * connect. They can trigger transient overcurrent conditions
502 * that must be ignored.
505 prcm = musb_readl(base, TUSB_PRCM_MNGMT);
506 conf = musb_readl(base, TUSB_DEV_CONF);
507 devctl = musb_readb(musb->pRegs, MGC_O_HDRC_DEVCTL);
511 timer = OTG_TIMER_MS(OTG_TIME_A_WAIT_VRISE);
512 musb->xceiv.default_a = 1;
513 musb->xceiv.state = OTG_STATE_A_WAIT_VRISE;
514 devctl |= MGC_M_DEVCTL_SESSION;
516 conf |= TUSB_DEV_CONF_USB_HOST_MODE;
522 /* NOTE: we're skipping A_WAIT_VFALL -> A_IDLE and
523 * jumping right to B_IDLE...
526 musb->xceiv.default_a = 0;
527 musb->xceiv.state = OTG_STATE_B_IDLE;
528 devctl &= ~MGC_M_DEVCTL_SESSION;
530 conf &= ~TUSB_DEV_CONF_USB_HOST_MODE;
533 prcm &= ~(TUSB_PRCM_MNGMT_15_SW_EN | TUSB_PRCM_MNGMT_33_SW_EN);
535 musb_writel(base, TUSB_PRCM_MNGMT, prcm);
536 musb_writel(base, TUSB_DEV_OTG_TIMER, timer);
537 musb_writel(base, TUSB_DEV_CONF, conf);
538 musb_writeb(musb->pRegs, MGC_O_HDRC_DEVCTL, devctl);
540 DBG(1, "VBUS %s, devctl %02x otg %3x conf %08x prcm %08x\n",
541 otg_state_string(musb),
542 musb_readb(musb->pRegs, MGC_O_HDRC_DEVCTL),
543 musb_readl(base, TUSB_DEV_OTG_STAT),
548 * Sets the mode to OTG, peripheral or host by changing the ID detection.
549 * Caller must take care of locking.
551 * Note that if a mini-A cable is plugged in the ID line will stay down as
552 * the weak ID pull-up is not able to pull the ID up.
554 * REVISIT: It would be possible to add support for changing between host
555 * and peripheral modes in non-OTG configurations by reconfiguring hardware
556 * and then setting musb->board_mode. For now, only support OTG mode.
558 void musb_platform_set_mode(struct musb *musb, u8 musb_mode)
560 void __iomem *base = musb->ctrl_base;
561 u32 otg_stat, phy_otg_ctrl, phy_otg_ena, dev_conf;
564 if (musb->board_mode != MUSB_OTG) {
565 ERR("Changing mode currently only supported in OTG mode\n");
569 otg_stat = musb_readl(base, TUSB_DEV_OTG_STAT);
570 phy_otg_ctrl = musb_readl(base, TUSB_PHY_OTG_CTRL);
571 phy_otg_ena = musb_readl(base, TUSB_PHY_OTG_CTRL_ENABLE);
572 dev_conf = musb_readl(base, TUSB_DEV_CONF);
576 #ifdef CONFIG_USB_MUSB_HDRC_HCD
577 case MUSB_HOST: /* Disable PHY ID detect, ground ID */
578 phy_otg_ctrl &= ~TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP;
579 phy_otg_ena |= TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP;
580 dev_conf |= TUSB_DEV_CONF_ID_SEL;
581 dev_conf &= ~TUSB_DEV_CONF_SOFT_ID;
586 #ifdef CONFIG_USB_GADGET_MUSB_HDRC
587 case MUSB_PERIPHERAL: /* Disable PHY ID detect, keep ID pull-up on */
588 phy_otg_ctrl |= TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP;
589 phy_otg_ena |= TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP;
590 dev_conf |= (TUSB_DEV_CONF_ID_SEL | TUSB_DEV_CONF_SOFT_ID);
594 #ifdef CONFIG_USB_MUSB_OTG
595 case MUSB_OTG: /* Use PHY ID detection */
596 phy_otg_ctrl |= TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP;
597 phy_otg_ena |= TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP;
598 dev_conf &= ~(TUSB_DEV_CONF_ID_SEL | TUSB_DEV_CONF_SOFT_ID);
603 DBG(2, "Trying to set unknown mode %i\n", musb_mode);
606 musb_writel(base, TUSB_PHY_OTG_CTRL,
607 TUSB_PHY_OTG_CTRL_WRPROTECT | phy_otg_ctrl);
608 musb_writel(base, TUSB_PHY_OTG_CTRL_ENABLE,
609 TUSB_PHY_OTG_CTRL_WRPROTECT | phy_otg_ena);
610 musb_writel(base, TUSB_DEV_CONF, dev_conf);
612 otg_stat = musb_readl(base, TUSB_DEV_OTG_STAT);
613 if ((musb_mode == MUSB_PERIPHERAL) &&
614 !(otg_stat & TUSB_DEV_OTG_STAT_ID_STATUS))
615 INFO("Cannot be peripheral with mini-A cable "
616 "otg_stat: %08x\n", otg_stat);
619 static inline unsigned long
620 tusb_otg_ints(struct musb *musb, u32 int_src, void __iomem *base)
622 u32 otg_stat = musb_readl(base, TUSB_DEV_OTG_STAT);
623 unsigned long idle_timeout = 0;
626 if ((int_src & TUSB_INT_SRC_ID_STATUS_CHNG)) {
629 if (is_otg_enabled(musb))
630 default_a = !(otg_stat & TUSB_DEV_OTG_STAT_ID_STATUS);
632 default_a = is_host_enabled(musb);
633 DBG(2, "Default-%c\n", default_a ? 'A' : 'B');
634 musb->xceiv.default_a = default_a;
635 tusb_source_power(musb, default_a);
637 /* Don't allow idling immediately */
639 idle_timeout = jiffies + (HZ * 3);
642 /* VBUS state change */
643 if (int_src & TUSB_INT_SRC_VBUS_SENSE_CHNG) {
645 /* B-dev state machine: no vbus ~= disconnect */
646 if ((is_otg_enabled(musb) && !musb->xceiv.default_a)
647 || !is_host_enabled(musb)) {
648 #ifdef CONFIG_USB_MUSB_HDRC_HCD
649 // ? musb_root_disconnect(musb);
650 musb->port1_status &=
651 ~(USB_PORT_STAT_CONNECTION
652 | USB_PORT_STAT_ENABLE
653 | USB_PORT_STAT_LOW_SPEED
654 | USB_PORT_STAT_HIGH_SPEED
659 if (otg_stat & TUSB_DEV_OTG_STAT_SESS_END) {
660 DBG(1, "Forcing disconnect (no interrupt)\n");
661 if (musb->xceiv.state != OTG_STATE_B_IDLE) {
662 /* INTR_DISCONNECT can hide... */
663 musb->xceiv.state = OTG_STATE_B_IDLE;
664 musb->int_usb |= MGC_M_INTR_DISCONNECT;
668 DBG(2, "vbus change, %s, otg %03x\n",
669 otg_state_string(musb), otg_stat);
670 idle_timeout = jiffies + (1 * HZ);
671 schedule_work(&musb->irq_work);
673 } else /* A-dev state machine */ {
676 DBG(2, "vbus change, %s, otg %03x\n",
677 otg_state_string(musb), otg_stat);
679 switch (musb->xceiv.state) {
680 case OTG_STATE_A_IDLE:
681 DBG(2, "Got SRP, turning on VBUS\n");
682 devctl = musb_readb(musb->pRegs,
684 devctl |= MGC_M_DEVCTL_SESSION;
685 musb_writeb(musb->pRegs, MGC_O_HDRC_DEVCTL,
687 musb->xceiv.state = OTG_STATE_A_WAIT_VRISE;
689 /* CONNECT can wake if a_wait_bcon is set */
690 if (musb->a_wait_bcon != 0)
695 idle_timeout = jiffies
696 + msecs_to_jiffies(musb->a_wait_bcon);
698 case OTG_STATE_A_WAIT_VRISE:
699 /* ignore; A-session-valid < VBUS_VALID/2,
700 * we monitor this with the timer
703 case OTG_STATE_A_WAIT_VFALL:
704 /* REVISIT this irq triggers during short
705 * spikes causet by enumeration ...
707 if (musb->vbuserr_retry) {
708 musb->vbuserr_retry--;
709 tusb_source_power(musb, 1);
718 /* OTG timer expiration */
719 if (int_src & TUSB_INT_SRC_OTG_TIMEOUT) {
722 DBG(4, "%s timer, %03x\n", otg_state_string(musb), otg_stat);
724 switch (musb->xceiv.state) {
725 case OTG_STATE_A_WAIT_VRISE:
726 /* VBUS has probably been valid for a while now,
727 * but may well have bounced out of range a bit
729 devctl = musb_readb(musb->pRegs, MGC_O_HDRC_DEVCTL);
730 if (otg_stat & TUSB_DEV_OTG_STAT_VBUS_VALID) {
731 if ((devctl & MGC_M_DEVCTL_VBUS)
732 != MGC_M_DEVCTL_VBUS) {
733 DBG(2, "devctl %02x\n", devctl);
736 musb->xceiv.state = OTG_STATE_A_WAIT_BCON;
737 /* CONNECT can wake if a_wait_bcon is set */
738 if (musb->a_wait_bcon != 0)
742 idle_timeout = jiffies
743 + msecs_to_jiffies(musb->a_wait_bcon);
745 /* REVISIT report overcurrent to hub? */
746 ERR("vbus too slow, devctl %02x\n", devctl);
747 tusb_source_power(musb, 0);
750 case OTG_STATE_A_WAIT_BCON:
751 if (musb->a_wait_bcon != 0)
752 idle_timeout = jiffies
753 + msecs_to_jiffies(musb->a_wait_bcon);
755 case OTG_STATE_A_SUSPEND:
757 case OTG_STATE_B_WAIT_ACON:
767 static irqreturn_t tusb_interrupt(int irq, void *__hci)
769 struct musb *musb = __hci;
770 void __iomem *base = musb->ctrl_base;
771 unsigned long flags, idle_timeout = 0;
772 u32 int_mask, int_src;
774 spin_lock_irqsave(&musb->Lock, flags);
776 /* Mask all interrupts to allow using both edge and level GPIO irq */
777 int_mask = musb_readl(base, TUSB_INT_MASK);
778 musb_writel(base, TUSB_INT_MASK, ~TUSB_INT_MASK_RESERVED_BITS);
780 int_src = musb_readl(base, TUSB_INT_SRC) & ~TUSB_INT_SRC_RESERVED_BITS;
781 DBG(3, "TUSB IRQ %08x\n", int_src);
783 musb->int_usb = (u8) int_src;
785 /* Acknowledge wake-up source interrupts */
786 if (int_src & TUSB_INT_SRC_DEV_WAKEUP) {
790 if (tusb_get_revision(musb) == TUSB_REV_30)
791 tusb_wbus_quirk(musb, 0);
793 /* there are issues re-locking the PLL on wakeup ... */
795 /* work around issue 8 */
796 for (i = 0xf7f7f7; i > 0xf7f7f7 - 1000; i--) {
797 musb_writel(base, TUSB_SCRATCH_PAD, 0);
798 musb_writel(base, TUSB_SCRATCH_PAD, i);
799 reg = musb_readl(base, TUSB_SCRATCH_PAD);
802 DBG(6, "TUSB NOR not ready\n");
805 /* work around issue 13 (2nd half) */
806 tusb_set_clock_source(musb, 1);
808 reg = musb_readl(base, TUSB_PRCM_WAKEUP_SOURCE);
809 musb_writel(base, TUSB_PRCM_WAKEUP_CLEAR, reg);
810 if (reg & ~TUSB_PRCM_WNORCS) {
812 schedule_work(&musb->irq_work);
814 DBG(3, "wake %sactive %02x\n",
815 musb->is_active ? "" : "in", reg);
817 // REVISIT host side TUSB_PRCM_WHOSTDISCON, TUSB_PRCM_WBUS
820 if (int_src & TUSB_INT_SRC_USB_IP_CONN)
821 del_timer(&musb_idle_timer);
823 /* OTG state change reports (annoyingly) not issued by Mentor core */
824 if (int_src & (TUSB_INT_SRC_VBUS_SENSE_CHNG
825 | TUSB_INT_SRC_OTG_TIMEOUT
826 | TUSB_INT_SRC_ID_STATUS_CHNG))
827 idle_timeout = tusb_otg_ints(musb, int_src, base);
829 /* TX dma callback must be handled here, RX dma callback is
830 * handled in tusb_omap_dma_cb.
832 if ((int_src & TUSB_INT_SRC_TXRX_DMA_DONE)) {
833 u32 dma_src = musb_readl(base, TUSB_DMA_INT_SRC);
834 u32 real_dma_src = musb_readl(base, TUSB_DMA_INT_MASK);
836 DBG(3, "DMA IRQ %08x\n", dma_src);
837 real_dma_src = ~real_dma_src & dma_src;
838 if (tusb_dma_omap() && real_dma_src) {
839 int tx_source = (real_dma_src & 0xffff);
842 for (i = 1; i <= 15; i++) {
843 if (tx_source & (1 << i)) {
844 DBG(3, "completing ep%i %s\n", i, "tx");
845 musb_dma_completion(musb, i, 1);
849 musb_writel(base, TUSB_DMA_INT_CLEAR, dma_src);
852 /* EP interrupts. In OCP mode tusb6010 mirrors the MUSB * interrupts */
853 if (int_src & (TUSB_INT_SRC_USB_IP_TX | TUSB_INT_SRC_USB_IP_RX)) {
854 u32 musb_src = musb_readl(base, TUSB_USBIP_INT_SRC);
856 musb_writel(base, TUSB_USBIP_INT_CLEAR, musb_src);
857 musb->int_rx = (((musb_src >> 16) & 0xffff) << 1);
858 musb->int_tx = (musb_src & 0xffff);
860 musb->int_rx = musb->int_tx = 0;
862 if (int_src & (TUSB_INT_SRC_USB_IP_TX | TUSB_INT_SRC_USB_IP_RX | 0xff))
863 musb_interrupt(musb);
865 /* Acknowledge TUSB interrupts. Clear only non-reserved bits */
866 musb_writel(base, TUSB_INT_SRC_CLEAR,
867 int_src & ~TUSB_INT_MASK_RESERVED_BITS);
869 musb_platform_try_idle(musb, idle_timeout);
871 musb_writel(base, TUSB_INT_MASK, int_mask);
872 spin_unlock_irqrestore(&musb->Lock, flags);
880 * Enables TUSB6010. Caller must take care of locking.
882 * - Check what is unnecessary in MGC_HdrcStart()
884 void musb_platform_enable(struct musb * musb)
886 void __iomem *base = musb->ctrl_base;
888 /* Setup TUSB6010 main interrupt mask. Enable all interrupts except SOF.
889 * REVISIT: Enable and deal with TUSB_INT_SRC_USB_IP_SOF */
890 musb_writel(base, TUSB_INT_MASK, TUSB_INT_SRC_USB_IP_SOF);
892 /* Setup TUSB interrupt, disable DMA and GPIO interrupts */
893 musb_writel(base, TUSB_USBIP_INT_MASK, 0);
894 musb_writel(base, TUSB_DMA_INT_MASK, 0x7fffffff);
895 musb_writel(base, TUSB_GPIO_INT_MASK, 0x1ff);
897 /* Clear all subsystem interrups */
898 musb_writel(base, TUSB_USBIP_INT_CLEAR, 0x7fffffff);
899 musb_writel(base, TUSB_DMA_INT_CLEAR, 0x7fffffff);
900 musb_writel(base, TUSB_GPIO_INT_CLEAR, 0x1ff);
902 /* Acknowledge pending interrupt(s) */
903 musb_writel(base, TUSB_INT_SRC_CLEAR, ~TUSB_INT_MASK_RESERVED_BITS);
905 /* Only 0 clock cycles for minimum interrupt de-assertion time and
906 * interrupt polarity active low seems to work reliably here */
907 musb_writel(base, TUSB_INT_CTRL_CONF,
908 TUSB_INT_CTRL_CONF_INT_RELCYC(0));
910 set_irq_type(musb->nIrq, IRQ_TYPE_LEVEL_LOW);
912 /* maybe force into the Default-A OTG state machine */
913 if (!(musb_readl(base, TUSB_DEV_OTG_STAT)
914 & TUSB_DEV_OTG_STAT_ID_STATUS))
915 musb_writel(base, TUSB_INT_SRC_SET,
916 TUSB_INT_SRC_ID_STATUS_CHNG);
918 if (is_dma_capable() && dma_off)
919 printk(KERN_WARNING "%s %s: dma not reactivated\n",
920 __FILE__, __FUNCTION__);
926 * Disables TUSB6010. Caller must take care of locking.
928 void musb_platform_disable(struct musb *musb)
930 void __iomem *base = musb->ctrl_base;
932 /* FIXME stop DMA, IRQs, timers, ... */
934 /* disable all IRQs */
935 musb_writel(base, TUSB_INT_MASK, ~TUSB_INT_MASK_RESERVED_BITS);
936 musb_writel(base, TUSB_USBIP_INT_MASK, 0);
937 musb_writel(base, TUSB_DMA_INT_MASK, 0x7fffffff);
938 musb_writel(base, TUSB_GPIO_INT_MASK, 0x1ff);
940 del_timer(&musb_idle_timer);
942 if (is_dma_capable() && !dma_off) {
943 printk(KERN_WARNING "%s %s: dma still active\n",
944 __FILE__, __FUNCTION__);
950 * Sets up TUSB6010 CPU interface specific signals and registers
951 * Note: Settings optimized for OMAP24xx
953 static void __init tusb_setup_cpu_interface(struct musb *musb)
955 void __iomem *base = musb->ctrl_base;
958 * Disable GPIO[5:0] pullups (used as output DMA requests)
959 * Don't disable GPIO[7:6] as they are needed for wake-up.
961 musb_writel(base, TUSB_PULLUP_1_CTRL, 0x0000003F);
963 /* Disable all pullups on NOR IF, DMAREQ0 and DMAREQ1 */
964 musb_writel(base, TUSB_PULLUP_2_CTRL, 0x01FFFFFF);
966 /* Turn GPIO[5:0] to DMAREQ[5:0] signals */
967 musb_writel(base, TUSB_GPIO_CONF, TUSB_GPIO_CONF_DMAREQ(0x3f));
969 /* Burst size 16x16 bits, all six DMA requests enabled, DMA request
970 * de-assertion time 2 system clocks p 62 */
971 musb_writel(base, TUSB_DMA_REQ_CONF,
972 TUSB_DMA_REQ_CONF_BURST_SIZE(2) |
973 TUSB_DMA_REQ_CONF_DMA_REQ_EN(0x3f) |
974 TUSB_DMA_REQ_CONF_DMA_REQ_ASSER(2));
976 /* Set 0 wait count for synchronous burst access */
977 musb_writel(base, TUSB_WAIT_COUNT, 1);
980 static int __init tusb_start(struct musb *musb)
982 void __iomem *base = musb->ctrl_base;
987 if (musb->board_set_power)
988 ret = musb->board_set_power(1);
990 printk(KERN_ERR "tusb: Cannot enable TUSB6010\n");
994 spin_lock_irqsave(&musb->Lock, flags);
996 if (musb_readl(base, TUSB_PROD_TEST_RESET) !=
997 TUSB_PROD_TEST_RESET_VAL) {
998 printk(KERN_ERR "tusb: Unable to detect TUSB6010\n");
1002 ret = tusb_print_revision(musb);
1004 printk(KERN_ERR "tusb: Unsupported TUSB6010 revision %i\n",
1009 /* The uint bit for "USB non-PDR interrupt enable" has to be 1 when
1010 * NOR FLASH interface is used */
1011 musb_writel(base, TUSB_VLYNQ_CTRL, 8);
1013 /* Select PHY free running 60MHz as a system clock */
1014 tusb_set_clock_source(musb, 1);
1016 /* VBus valid timer 1us, disable DFT/Debug and VLYNQ clocks for
1017 * power saving, enable VBus detect and session end comparators,
1018 * enable IDpullup, enable VBus charging */
1019 musb_writel(base, TUSB_PRCM_MNGMT,
1020 TUSB_PRCM_MNGMT_VBUS_VALID_TIMER(0xa) |
1021 TUSB_PRCM_MNGMT_VBUS_VALID_FLT_EN |
1022 TUSB_PRCM_MNGMT_OTG_SESS_END_EN |
1023 TUSB_PRCM_MNGMT_OTG_VBUS_DET_EN |
1024 TUSB_PRCM_MNGMT_OTG_ID_PULLUP);
1025 tusb_setup_cpu_interface(musb);
1027 /* simplify: always sense/pullup ID pins, as if in OTG mode */
1028 reg = musb_readl(base, TUSB_PHY_OTG_CTRL_ENABLE);
1029 reg |= TUSB_PHY_OTG_CTRL_WRPROTECT | TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP;
1030 musb_writel(base, TUSB_PHY_OTG_CTRL_ENABLE, reg);
1032 reg = musb_readl(base, TUSB_PHY_OTG_CTRL);
1033 reg |= TUSB_PHY_OTG_CTRL_WRPROTECT | TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP;
1034 musb_writel(base, TUSB_PHY_OTG_CTRL, reg);
1036 spin_unlock_irqrestore(&musb->Lock, flags);
1041 spin_unlock_irqrestore(&musb->Lock, flags);
1043 if (musb->board_set_power)
1044 musb->board_set_power(0);
1049 int __init musb_platform_init(struct musb *musb)
1051 struct platform_device *pdev;
1052 struct resource *mem;
1056 pdev = to_platform_device(musb->controller);
1058 /* dma address for async dma */
1059 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1060 musb->async = mem->start;
1062 /* dma address for sync dma */
1063 mem = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1065 pr_debug("no sync dma resource?\n");
1068 musb->sync = mem->start;
1070 sync = ioremap(mem->start, mem->end - mem->start + 1);
1072 pr_debug("ioremap for sync failed\n");
1075 musb->sync_va = sync;
1077 /* Offsets from base: VLYNQ at 0x000, MUSB regs at 0x400,
1078 * FIFOs at 0x600, TUSB at 0x800
1080 musb->pRegs += TUSB_BASE_OFFSET;
1082 ret = tusb_start(musb);
1084 printk(KERN_ERR "Could not start tusb6010 (%d)\n",
1088 musb->isr = tusb_interrupt;
1090 if (is_host_enabled(musb))
1091 musb->board_set_vbus = tusb_source_power;
1092 if (is_peripheral_enabled(musb))
1093 musb->xceiv.set_power = tusb_draw_power;
1095 setup_timer(&musb_idle_timer, musb_do_idle, (unsigned long) musb);
1100 int musb_platform_exit(struct musb *musb)
1102 del_timer_sync(&musb_idle_timer);
1104 if (musb->board_set_power)
1105 musb->board_set_power(0);
1107 iounmap(musb->sync_va);