4 #include <linux/config.h>
5 #include <linux/module.h>
6 #include <linux/kernel.h>
7 #include <linux/sched.h>
8 #include <linux/delay.h>
13 #ifdef CONFIG_FB_RADEON_I2C
14 #include <linux/i2c.h>
15 #include <linux/i2c-algo-bit.h>
24 #include <video/radeon.h>
26 /***************************************************************
27 * Most of the definitions here are adapted right from XFree86 *
28 ***************************************************************/
32 * Chip families. Must fit in the low 16 bits of a long word
39 CHIP_FAMILY_RS100, /* U1 (IGP320M) or A3 (IGP320)*/
41 CHIP_FAMILY_RS200, /* U2 (IGP330M/340M/350M) or A4 (IGP330/340/345/350),
45 CHIP_FAMILY_RS300, /* Radeon 9000 IGP */
50 CHIP_FAMILY_RV380, /* RV370/RV380/M22/M24 */
51 CHIP_FAMILY_R420, /* R420/R423/M18 */
55 #define IS_RV100_VARIANT(rinfo) (((rinfo)->family == CHIP_FAMILY_RV100) || \
56 ((rinfo)->family == CHIP_FAMILY_RV200) || \
57 ((rinfo)->family == CHIP_FAMILY_RS100) || \
58 ((rinfo)->family == CHIP_FAMILY_RS200) || \
59 ((rinfo)->family == CHIP_FAMILY_RV250) || \
60 ((rinfo)->family == CHIP_FAMILY_RV280) || \
61 ((rinfo)->family == CHIP_FAMILY_RS300))
64 #define IS_R300_VARIANT(rinfo) (((rinfo)->family == CHIP_FAMILY_R300) || \
65 ((rinfo)->family == CHIP_FAMILY_RV350) || \
66 ((rinfo)->family == CHIP_FAMILY_R350) || \
67 ((rinfo)->family == CHIP_FAMILY_RV380) || \
68 ((rinfo)->family == CHIP_FAMILY_R420))
73 enum radeon_chip_flags {
74 CHIP_FAMILY_MASK = 0x0000ffffUL,
75 CHIP_FLAGS_MASK = 0xffff0000UL,
76 CHIP_IS_MOBILITY = 0x00010000UL,
77 CHIP_IS_IGP = 0x00020000UL,
78 CHIP_HAS_CRTC2 = 0x00040000UL,
85 CHIP_ERRATA_R300_CG = 0x00000001,
86 CHIP_ERRATA_PLL_DUMMYREADS = 0x00000002,
87 CHIP_ERRATA_PLL_DELAY = 0x00000004,
99 MT_CTV, /* composite TV */
100 MT_STV /* S-Video out */
139 * This structure contains the various registers manipulated by this
140 * driver for setting or restoring a mode. It's mostly copied from
141 * XFree's RADEONSaveRec structure. A few chip settings might still be
142 * tweaked without beeing reflected or saved in these registers though
145 /* Common registers */
147 u32 ovr_wid_left_right;
148 u32 ovr_wid_top_bottom;
162 /* Other registers to save for VT switches or driver load/unload */
165 u32 clock_cntl_index;
169 /* Surface/tiling registers */
170 u32 surf_lower_bound[8];
171 u32 surf_upper_bound[8];
178 u32 crtc_h_total_disp;
179 u32 crtc_h_sync_strt_wid;
180 u32 crtc_v_total_disp;
181 u32 crtc_v_sync_strt_wid;
183 u32 crtc_offset_cntl;
186 u32 grph_buffer_cntl;
189 /* CRTC2 registers */
192 u32 disp_output_cntl;
194 u32 disp2_merge_cntl;
195 u32 grph2_buffer_cntl;
196 u32 crtc2_h_total_disp;
197 u32 crtc2_h_sync_strt_wid;
198 u32 crtc2_v_total_disp;
199 u32 crtc2_v_sync_strt_wid;
201 u32 crtc2_offset_cntl;
204 /* Flat panel regs */
205 u32 fp_crtc_h_total_disp;
206 u32 fp_crtc_v_total_disp;
209 u32 fp_h_sync_strt_wid;
210 u32 fp2_h_sync_strt_wid;
213 u32 fp_v_sync_strt_wid;
214 u32 fp2_v_sync_strt_wid;
219 u32 tmds_transmitter_cntl;
221 /* Computed values for PLL */
232 /* Computed values for PLL2 */
233 u32 dot_clock_freq_2;
250 int hOver_plus, hSync_width, hblank;
251 int vOver_plus, vSync_width, vblank;
252 int hAct_high, vAct_high, interlaced;
254 int use_bios_dividers;
260 struct radeonfb_info;
262 #ifdef CONFIG_FB_RADEON_I2C
263 struct radeon_i2c_chan {
264 struct radeonfb_info *rinfo;
266 struct i2c_adapter adapter;
267 struct i2c_algo_bit_data algo;
271 enum radeon_pm_mode {
272 radeon_pm_none = 0, /* Nothing supported */
273 radeon_pm_d2 = 0x00000001, /* Can do D2 state */
274 radeon_pm_off = 0x00000002, /* Can resume from D3 cold */
277 struct radeonfb_info {
278 struct fb_info *info;
280 struct radeon_regs state;
281 struct radeon_regs init_state;
283 char name[DEVICE_NAME_SIZE];
285 unsigned long mmio_base_phys;
286 unsigned long fb_base_phys;
288 void __iomem *mmio_base;
289 void __iomem *fb_base;
291 unsigned long fb_local_base;
293 struct pci_dev *pdev;
295 struct device_node *of_node;
298 void __iomem *bios_seg;
301 u32 pseudo_palette[17];
302 struct { u8 red, green, blue, pad; }
309 unsigned long video_ram;
310 unsigned long mapped_vram;
314 int pitch, bpp, depth;
321 struct panel_info panel_info;
324 struct fb_videomode *mon1_modedb;
329 u32 dp_gui_master_cntl;
341 enum radeon_pm_mode pm_mode;
342 void (*reinit_func)(struct radeonfb_info *rinfo);
344 /* Lock on register access */
347 /* Timer used for delayed LVDS operations */
348 struct timer_list lvds_timer;
349 u32 pending_lvds_gen_cntl;
351 #ifdef CONFIG_FB_RADEON_I2C
352 struct radeon_i2c_chan i2c[4];
359 #define PRIMARY_MONITOR(rinfo) (rinfo->mon1_type)
365 #ifdef CONFIG_FB_RADEON_DEBUG
372 #define RTRACE printk
374 #define RTRACE if(0) printk
382 /* Note about this function: we have some rare cases where we must not schedule,
383 * this typically happen with our special "wake up early" hook which allows us to
384 * wake up the graphic chip (and thus get the console back) before everything else
385 * on some machines that support that mecanism. At this point, interrupts are off
386 * and scheduling is not permitted
388 static inline void _radeon_msleep(struct radeonfb_info *rinfo, unsigned long ms)
390 if (rinfo->no_schedule || oops_in_progress)
397 #define INREG8(addr) readb((rinfo->mmio_base)+addr)
398 #define OUTREG8(addr,val) writeb(val, (rinfo->mmio_base)+addr)
399 #define INREG16(addr) readw((rinfo->mmio_base)+addr)
400 #define OUTREG16(addr,val) writew(val, (rinfo->mmio_base)+addr)
401 #define INREG(addr) readl((rinfo->mmio_base)+addr)
402 #define OUTREG(addr,val) writel(val, (rinfo->mmio_base)+addr)
404 static inline void _OUTREGP(struct radeonfb_info *rinfo, u32 addr,
410 spin_lock_irqsave(&rinfo->reg_lock, flags);
415 spin_unlock_irqrestore(&rinfo->reg_lock, flags);
418 #define OUTREGP(addr,val,mask) _OUTREGP(rinfo, addr, val,mask)
421 * Note about PLL register accesses:
423 * I have removed the spinlock on them on purpose. The driver now
424 * expects that it will only manipulate the PLL registers in normal
425 * task environment, where radeon_msleep() will be called, protected
426 * by a semaphore (currently the console semaphore) so that no conflict
427 * will happen on the PLL register index.
429 * With the latest changes to the VT layer, this is guaranteed for all
430 * calls except the actual drawing/blits which aren't supposed to use
431 * the PLL registers anyway
433 * This is very important for the workarounds to work properly. The only
434 * possible exception to this rule is the call to unblank(), which may
435 * be done at irq time if an oops is in progress.
437 static inline void radeon_pll_errata_after_index(struct radeonfb_info *rinfo)
439 if (!(rinfo->errata & CHIP_ERRATA_PLL_DUMMYREADS))
442 (void)INREG(CLOCK_CNTL_DATA);
443 (void)INREG(CRTC_GEN_CNTL);
446 static inline void radeon_pll_errata_after_data(struct radeonfb_info *rinfo)
448 if (rinfo->errata & CHIP_ERRATA_PLL_DELAY) {
449 /* we can't deal with posted writes here ... */
450 _radeon_msleep(rinfo, 5);
452 if (rinfo->errata & CHIP_ERRATA_R300_CG) {
454 save = INREG(CLOCK_CNTL_INDEX);
455 tmp = save & ~(0x3f | PLL_WR_EN);
456 OUTREG(CLOCK_CNTL_INDEX, tmp);
457 tmp = INREG(CLOCK_CNTL_DATA);
458 OUTREG(CLOCK_CNTL_INDEX, save);
462 static inline u32 __INPLL(struct radeonfb_info *rinfo, u32 addr)
466 OUTREG8(CLOCK_CNTL_INDEX, addr & 0x0000003f);
467 radeon_pll_errata_after_index(rinfo);
468 data = INREG(CLOCK_CNTL_DATA);
469 radeon_pll_errata_after_data(rinfo);
473 static inline void __OUTPLL(struct radeonfb_info *rinfo, unsigned int index,
477 OUTREG8(CLOCK_CNTL_INDEX, (index & 0x0000003f) | 0x00000080);
478 radeon_pll_errata_after_index(rinfo);
479 OUTREG(CLOCK_CNTL_DATA, val);
480 radeon_pll_errata_after_data(rinfo);
484 static inline void __OUTPLLP(struct radeonfb_info *rinfo, unsigned int index,
489 tmp = __INPLL(rinfo, index);
492 __OUTPLL(rinfo, index, tmp);
496 #define INPLL(addr) __INPLL(rinfo, addr)
497 #define OUTPLL(index, val) __OUTPLL(rinfo, index, val)
498 #define OUTPLLP(index, val, mask) __OUTPLLP(rinfo, index, val, mask)
501 #define BIOS_IN8(v) (readb(rinfo->bios_seg + (v)))
502 #define BIOS_IN16(v) (readb(rinfo->bios_seg + (v)) | \
503 (readb(rinfo->bios_seg + (v) + 1) << 8))
504 #define BIOS_IN32(v) (readb(rinfo->bios_seg + (v)) | \
505 (readb(rinfo->bios_seg + (v) + 1) << 8) | \
506 (readb(rinfo->bios_seg + (v) + 2) << 16) | \
507 (readb(rinfo->bios_seg + (v) + 3) << 24))
512 static inline int round_div(int num, int den)
514 return (num + (den / 2)) / den;
517 static inline int var_to_depth(const struct fb_var_screeninfo *var)
519 if (var->bits_per_pixel != 16)
520 return var->bits_per_pixel;
521 return (var->green.length == 5) ? 15 : 16;
524 static inline u32 radeon_get_dstbpp(u16 depth)
541 * 2D Engine helper routines
543 static inline void radeon_engine_flush (struct radeonfb_info *rinfo)
548 OUTREGP(RB2D_DSTCACHE_CTLSTAT, RB2D_DC_FLUSH_ALL,
551 for (i=0; i < 2000000; i++) {
552 if (!(INREG(RB2D_DSTCACHE_CTLSTAT) & RB2D_DC_BUSY))
556 printk(KERN_ERR "radeonfb: Flush Timeout !\n");
560 static inline void _radeon_fifo_wait(struct radeonfb_info *rinfo, int entries)
564 for (i=0; i<2000000; i++) {
565 if ((INREG(RBBM_STATUS) & 0x7f) >= entries)
569 printk(KERN_ERR "radeonfb: FIFO Timeout !\n");
573 static inline void _radeon_engine_idle(struct radeonfb_info *rinfo)
577 /* ensure FIFO is empty before waiting for idle */
578 _radeon_fifo_wait (rinfo, 64);
580 for (i=0; i<2000000; i++) {
581 if (((INREG(RBBM_STATUS) & GUI_ACTIVE)) == 0) {
582 radeon_engine_flush (rinfo);
587 printk(KERN_ERR "radeonfb: Idle Timeout !\n");
591 #define radeon_engine_idle() _radeon_engine_idle(rinfo)
592 #define radeon_fifo_wait(entries) _radeon_fifo_wait(rinfo,entries)
593 #define radeon_msleep(ms) _radeon_msleep(rinfo,ms)
597 extern void radeon_create_i2c_busses(struct radeonfb_info *rinfo);
598 extern void radeon_delete_i2c_busses(struct radeonfb_info *rinfo);
599 extern int radeon_probe_i2c_connector(struct radeonfb_info *rinfo, int conn, u8 **out_edid);
602 extern int radeonfb_pci_suspend(struct pci_dev *pdev, pm_message_t state);
603 extern int radeonfb_pci_resume(struct pci_dev *pdev);
604 extern void radeonfb_pm_init(struct radeonfb_info *rinfo, int dynclk);
605 extern void radeonfb_pm_exit(struct radeonfb_info *rinfo);
607 /* Monitor probe functions */
608 extern void radeon_probe_screens(struct radeonfb_info *rinfo,
609 const char *monitor_layout, int ignore_edid);
610 extern void radeon_check_modes(struct radeonfb_info *rinfo, const char *mode_option);
611 extern int radeon_match_mode(struct radeonfb_info *rinfo,
612 struct fb_var_screeninfo *dest,
613 const struct fb_var_screeninfo *src);
615 /* Accel functions */
616 extern void radeonfb_fillrect(struct fb_info *info, const struct fb_fillrect *region);
617 extern void radeonfb_copyarea(struct fb_info *info, const struct fb_copyarea *area);
618 extern void radeonfb_imageblit(struct fb_info *p, const struct fb_image *image);
619 extern int radeonfb_sync(struct fb_info *info);
620 extern void radeonfb_engine_init (struct radeonfb_info *rinfo);
621 extern void radeonfb_engine_reset(struct radeonfb_info *rinfo);
623 /* Other functions */
624 extern int radeon_screen_blank(struct radeonfb_info *rinfo, int blank, int mode_switch);
625 extern void radeon_write_mode (struct radeonfb_info *rinfo, struct radeon_regs *mode,
628 #endif /* __RADEONFB_H__ */