drivers/video/i810/i810_main.c

   1  /*-*- linux-c -*-
   2  *  linux/drivers/video/i810_main.c -- Intel 810 frame buffer device
   3  *
   4  *      Copyright (C) 2001 Antonino Daplas<adaplas@pol.net>
   5  *      All Rights Reserved
   6  *
   7  *      Contributors:
   8  *         Michael Vogt <mvogt@acm.org> - added support for Intel 815 chipsets
   9  *                                        and enabling the power-on state of
  10  *                                        external VGA connectors for
  11  *                                        secondary displays
  12  *
  13  *         Fredrik Andersson <krueger@shell.linux.se> - alpha testing of
  14  *                                        the VESA GTF
  15  *
  16  *         Brad Corrion <bcorrion@web-co.com> - alpha testing of customized
  17  *                                        timings support
  18  *
  19  *      The code framework is a modification of vfb.c by Geert Uytterhoeven.
  20  *      DotClock and PLL calculations are partly based on i810_driver.c
  21  *              in xfree86 v4.0.3 by Precision Insight.
  22  *      Watermark calculation and tables are based on i810_wmark.c
  23  *              in xfre86 v4.0.3 by Precision Insight.  Slight modifications
  24  *              only to allow for integer operations instead of floating point.
  25  *
  26  *  This file is subject to the terms and conditions of the GNU General Public
  27  *  License. See the file COPYING in the main directory of this archive for
  28  *  more details.
  29  */
  30
  31 #include <linux/module.h>
  32 #include <linux/config.h>
  33 #include <linux/kernel.h>
  34 #include <linux/errno.h>
  35 #include <linux/string.h>
  36 #include <linux/mm.h>
  37 #include <linux/tty.h>
  38 #include <linux/slab.h>
  39 #include <linux/fb.h>
  40 #include <linux/init.h>
  41 #include <linux/pci.h>
  42 #include <linux/pci_ids.h>
  43 #include <linux/resource.h>
  44 #include <linux/unistd.h>
  45
  46 #include <asm/io.h>
  47 #include <asm/div64.h>
  48
  49 #ifdef CONFIG_MTRR
  50 #include <asm/mtrr.h>
  51 #endif
  52
  53 #include <asm/page.h>
  54
  55 #include "i810_regs.h"
  56 #include "i810.h"
  57 #include "i810_main.h"
  58
  59 /* PCI */
  60 static const char *i810_pci_list[] __devinitdata = {
  61         "Intel(R) 810 Framebuffer Device"                                 ,
  62         "Intel(R) 810-DC100 Framebuffer Device"                           ,
  63         "Intel(R) 810E Framebuffer Device"                                ,
  64         "Intel(R) 815 (Internal Graphics 100Mhz FSB) Framebuffer Device"  ,
  65         "Intel(R) 815 (Internal Graphics only) Framebuffer Device"        ,
  66         "Intel(R) 815 (Internal Graphics with AGP) Framebuffer Device"
  67 };
  68
  69 static struct pci_device_id i810fb_pci_tbl[] = {
  70         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82810_IG1,
  71           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
  72         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82810_IG3,
  73           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1  },
  74         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82810E_IG,
  75           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 2 },
  76         /* mvo: added i815 PCI-ID */
  77         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82815_100,
  78           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3 },
  79         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82815_NOAGP,
  80           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4 },
  81         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82815_CGC,
  82           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5 },
  83         { 0 },
  84 };
  85
  86 static struct pci_driver i810fb_driver = {
  87         .name     =     "i810fb",
  88         .id_table =     i810fb_pci_tbl,
  89         .probe    =     i810fb_init_pci,
  90         .remove   =     __exit_p(i810fb_remove_pci),
  91         .suspend  =     i810fb_suspend,
  92         .resume   =     i810fb_resume,
  93 };
  94
  95 static char *mode_option __devinitdata = NULL;
  96 static int vram       __devinitdata = 4;
  97 static int bpp        __devinitdata = 8;
  98 static int mtrr       __devinitdata = 0;
  99 static int accel      __devinitdata = 0;
 100 static int hsync1     __devinitdata = 0;
 101 static int hsync2     __devinitdata = 0;
 102 static int vsync1     __devinitdata = 0;
 103 static int vsync2     __devinitdata = 0;
 104 static int xres       __devinitdata = 640;
 105 static int yres       __devinitdata = 480;
 106 static int vyres      __devinitdata = 0;
 107 static int sync       __devinitdata = 0;
 108 static int ext_vga    __devinitdata = 0;
 109 static int dcolor     __devinitdata = 0;
 110
 111 /*------------------------------------------------------------*/
 112
 113 /**************************************************************
 114  *                Hardware Low Level Routines                 *
 115  **************************************************************/
 116
 117 /**
 118  * i810_screen_off - turns off/on display
 119  * @mmio: address of register space
 120  * @mode: on or off
 121  *
 122  * DESCRIPTION:
 123  * Blanks/unblanks the display
 124  */
 125 static void i810_screen_off(u8 __iomem *mmio, u8 mode)
 126 {
 127         u32 count = WAIT_COUNT;
 128         u8 val;
 129
 130         i810_writeb(SR_INDEX, mmio, SR01);
 131         val = i810_readb(SR_DATA, mmio);
 132         val = (mode == OFF) ? val | SCR_OFF :
 133                 val & ~SCR_OFF;
 134
 135         while((i810_readw(DISP_SL, mmio) & 0xFFF) && count--);
 136         i810_writeb(SR_INDEX, mmio, SR01);
 137         i810_writeb(SR_DATA, mmio, val);
 138 }
 139
 140 /**
 141  * i810_dram_off - turns off/on dram refresh
 142  * @mmio: address of register space
 143  * @mode: on or off
 144  *
 145  * DESCRIPTION:
 146  * Turns off DRAM refresh.  Must be off for only 2 vsyncs
 147  * before data becomes corrupt
 148  */
 149 static void i810_dram_off(u8 __iomem *mmio, u8 mode)
 150 {
 151         u8 val;
 152
 153         val = i810_readb(DRAMCH, mmio);
 154         val &= DRAM_OFF;
 155         val = (mode == OFF) ? val : val | DRAM_ON;
 156         i810_writeb(DRAMCH, mmio, val);
 157 }
 158
 159 /**
 160  * i810_protect_regs - allows rw/ro mode of certain VGA registers
 161  * @mmio: address of register space
 162  * @mode: protect/unprotect
 163  *
 164  * DESCRIPTION:
 165  * The IBM VGA standard allows protection of certain VGA registers.
 166  * This will  protect or unprotect them.
 167  */
 168 static void i810_protect_regs(u8 __iomem *mmio, int mode)
 169 {
 170         u8 reg;
 171
 172         i810_writeb(CR_INDEX_CGA, mmio, CR11);
 173         reg = i810_readb(CR_DATA_CGA, mmio);
 174         reg = (mode == OFF) ? reg & ~0x80 :
 175                 reg | 0x80;
 176
 177         i810_writeb(CR_INDEX_CGA, mmio, CR11);
 178         i810_writeb(CR_DATA_CGA, mmio, reg);
 179 }
 180
 181 /**
 182  * i810_load_pll - loads values for the hardware PLL clock
 183  * @par: pointer to i810fb_par structure
 184  *
 185  * DESCRIPTION:
 186  * Loads the P, M, and N registers.
 187  */
 188 static void i810_load_pll(struct i810fb_par *par)
 189 {
 190         u32 tmp1, tmp2;
 191         u8 __iomem *mmio = par->mmio_start_virtual;
 192
 193         tmp1 = par->regs.M | par->regs.N << 16;
 194         tmp2 = i810_readl(DCLK_2D, mmio);
 195         tmp2 &= ~MN_MASK;
 196         i810_writel(DCLK_2D, mmio, tmp1 | tmp2);
 197
 198         tmp1 = par->regs.P;
 199         tmp2 = i810_readl(DCLK_0DS, mmio);
 200         tmp2 &= ~(P_OR << 16);
 201         i810_writel(DCLK_0DS, mmio, (tmp1 << 16) | tmp2);
 202
 203         i810_writeb(MSR_WRITE, mmio, par->regs.msr | 0xC8 | 1);
 204
 205 }
 206
 207 /**
 208  * i810_load_vga - load standard VGA registers
 209  * @par: pointer to i810fb_par structure
 210  *
 211  * DESCRIPTION:
 212  * Load values to VGA registers
 213  */
 214 static void i810_load_vga(struct i810fb_par *par)
 215 {
 216         u8 __iomem *mmio = par->mmio_start_virtual;
 217
 218         /* interlace */
 219         i810_writeb(CR_INDEX_CGA, mmio, CR70);
 220         i810_writeb(CR_DATA_CGA, mmio, par->interlace);
 221
 222         i810_writeb(CR_INDEX_CGA, mmio, CR00);
 223         i810_writeb(CR_DATA_CGA, mmio, par->regs.cr00);
 224         i810_writeb(CR_INDEX_CGA, mmio, CR01);
 225         i810_writeb(CR_DATA_CGA, mmio, par->regs.cr01);
 226         i810_writeb(CR_INDEX_CGA, mmio, CR02);
 227         i810_writeb(CR_DATA_CGA, mmio, par->regs.cr02);
 228         i810_writeb(CR_INDEX_CGA, mmio, CR03);
 229         i810_writeb(CR_DATA_CGA, mmio, par->regs.cr03);
 230         i810_writeb(CR_INDEX_CGA, mmio, CR04);
 231         i810_writeb(CR_DATA_CGA, mmio, par->regs.cr04);
 232         i810_writeb(CR_INDEX_CGA, mmio, CR05);
 233         i810_writeb(CR_DATA_CGA, mmio, par->regs.cr05);
 234         i810_writeb(CR_INDEX_CGA, mmio, CR06);
 235         i810_writeb(CR_DATA_CGA, mmio, par->regs.cr06);
 236         i810_writeb(CR_INDEX_CGA, mmio, CR09);
 237         i810_writeb(CR_DATA_CGA, mmio, par->regs.cr09);
 238         i810_writeb(CR_INDEX_CGA, mmio, CR10);
 239         i810_writeb(CR_DATA_CGA, mmio, par->regs.cr10);
 240         i810_writeb(CR_INDEX_CGA, mmio, CR11);
 241         i810_writeb(CR_DATA_CGA, mmio, par->regs.cr11);
 242         i810_writeb(CR_INDEX_CGA, mmio, CR12);
 243         i810_writeb(CR_DATA_CGA, mmio, par->regs.cr12);
 244         i810_writeb(CR_INDEX_CGA, mmio, CR15);
 245         i810_writeb(CR_DATA_CGA, mmio, par->regs.cr15);
 246         i810_writeb(CR_INDEX_CGA, mmio, CR16);
 247         i810_writeb(CR_DATA_CGA, mmio, par->regs.cr16);
 248 }
 249
 250 /**
 251  * i810_load_vgax - load extended VGA registers
 252  * @par: pointer to i810fb_par structure
 253  *
 254  * DESCRIPTION:
 255  * Load values to extended VGA registers
 256  */
 257 static void i810_load_vgax(struct i810fb_par *par)
 258 {
 259         u8 __iomem *mmio = par->mmio_start_virtual;
 260
 261         i810_writeb(CR_INDEX_CGA, mmio, CR30);
 262         i810_writeb(CR_DATA_CGA, mmio, par->regs.cr30);
 263         i810_writeb(CR_INDEX_CGA, mmio, CR31);
 264         i810_writeb(CR_DATA_CGA, mmio, par->regs.cr31);
 265         i810_writeb(CR_INDEX_CGA, mmio, CR32);
 266         i810_writeb(CR_DATA_CGA, mmio, par->regs.cr32);
 267         i810_writeb(CR_INDEX_CGA, mmio, CR33);
 268         i810_writeb(CR_DATA_CGA, mmio, par->regs.cr33);
 269         i810_writeb(CR_INDEX_CGA, mmio, CR35);
 270         i810_writeb(CR_DATA_CGA, mmio, par->regs.cr35);
 271         i810_writeb(CR_INDEX_CGA, mmio, CR39);
 272         i810_writeb(CR_DATA_CGA, mmio, par->regs.cr39);
 273 }
 274
 275 /**
 276  * i810_load_2d - load grahics registers
 277  * @par: pointer to i810fb_par structure
 278  *
 279  * DESCRIPTION:
 280  * Load values to graphics registers
 281  */
 282 static void i810_load_2d(struct i810fb_par *par)
 283 {
 284         u32 tmp;
 285         u8 tmp8;
 286         u8 __iomem *mmio = par->mmio_start_virtual;
 287
 288         i810_writel(FW_BLC, mmio, par->watermark);
 289         tmp = i810_readl(PIXCONF, mmio);
 290         tmp |= 1 | 1 << 20;
 291         i810_writel(PIXCONF, mmio, tmp);
 292
 293         i810_writel(OVRACT, mmio, par->ovract);
 294
 295         i810_writeb(GR_INDEX, mmio, GR10);
 296         tmp8 = i810_readb(GR_DATA, mmio);
 297         tmp8 |= 2;
 298         i810_writeb(GR_INDEX, mmio, GR10);
 299         i810_writeb(GR_DATA, mmio, tmp8);
 300 }
 301
 302 /**
 303  * i810_hires - enables high resolution mode
 304  * @mmio: address of register space
 305  */
 306 static void i810_hires(u8 __iomem *mmio)
 307 {
 308         u8 val;
 309
 310         i810_writeb(CR_INDEX_CGA, mmio, CR80);
 311         val = i810_readb(CR_DATA_CGA, mmio);
 312         i810_writeb(CR_INDEX_CGA, mmio, CR80);
 313         i810_writeb(CR_DATA_CGA, mmio, val | 1);
 314 }
 315
 316 /**
 317  * i810_load_pitch - loads the characters per line of the display
 318  * @par: pointer to i810fb_par structure
 319  *
 320  * DESCRIPTION:
 321  * Loads the characters per line
 322  */
 323 static void i810_load_pitch(struct i810fb_par *par)
 324 {
 325         u32 tmp, pitch;
 326         u8 val;
 327         u8 __iomem *mmio = par->mmio_start_virtual;
 328
 329         pitch = par->pitch >> 3;
 330         i810_writeb(SR_INDEX, mmio, SR01);
 331         val = i810_readb(SR_DATA, mmio);
 332         val &= 0xE0;
 333         val |= 1 | 1 << 2;
 334         i810_writeb(SR_INDEX, mmio, SR01);
 335         i810_writeb(SR_DATA, mmio, val);
 336
 337         tmp = pitch & 0xFF;
 338         i810_writeb(CR_INDEX_CGA, mmio, CR13);
 339         i810_writeb(CR_DATA_CGA, mmio, (u8) tmp);
 340
 341         tmp = pitch >> 8;
 342         i810_writeb(CR_INDEX_CGA, mmio, CR41);
 343         val = i810_readb(CR_DATA_CGA, mmio) & ~0x0F;
 344         i810_writeb(CR_INDEX_CGA, mmio, CR41);
 345         i810_writeb(CR_DATA_CGA, mmio, (u8) tmp | val);
 346 }
 347
 348 /**
 349  * i810_load_color - loads the color depth of the display
 350  * @par: pointer to i810fb_par structure
 351  *
 352  * DESCRIPTION:
 353  * Loads the color depth of the display and the graphics engine
 354  */
 355 static void i810_load_color(struct i810fb_par *par)
 356 {
 357         u8 __iomem *mmio = par->mmio_start_virtual;
 358         u32 reg1;
 359         u16 reg2;
 360
 361         reg1 = i810_readl(PIXCONF, mmio) & ~(0xF0000 | 1 << 27);
 362         reg2 = i810_readw(BLTCNTL, mmio) & ~0x30;
 363
 364         reg1 |= 0x8000 | par->pixconf;
 365         reg2 |= par->bltcntl;
 366         i810_writel(PIXCONF, mmio, reg1);
 367         i810_writew(BLTCNTL, mmio, reg2);
 368 }
 369
 370 /**
 371  * i810_load_regs - loads all registers for the mode
 372  * @par: pointer to i810fb_par structure
 373  *
 374  * DESCRIPTION:
 375  * Loads registers
 376  */
 377 static void i810_load_regs(struct i810fb_par *par)
 378 {
 379         u8 __iomem *mmio = par->mmio_start_virtual;
 380
 381         i810_screen_off(mmio, OFF);
 382         i810_protect_regs(mmio, OFF);
 383         i810_dram_off(mmio, OFF);
 384         i810_load_pll(par);
 385         i810_load_vga(par);
 386         i810_load_vgax(par);
 387         i810_dram_off(mmio, ON);
 388         i810_load_2d(par);
 389         i810_hires(mmio);
 390         i810_screen_off(mmio, ON);
 391         i810_protect_regs(mmio, ON);
 392         i810_load_color(par);
 393         i810_load_pitch(par);
 394 }
 395
 396 static void i810_write_dac(u8 regno, u8 red, u8 green, u8 blue,
 397                           u8 __iomem *mmio)
 398 {
 399         i810_writeb(CLUT_INDEX_WRITE, mmio, regno);
 400         i810_writeb(CLUT_DATA, mmio, red);
 401         i810_writeb(CLUT_DATA, mmio, green);
 402         i810_writeb(CLUT_DATA, mmio, blue);
 403 }
 404
 405 static void i810_read_dac(u8 regno, u8 *red, u8 *green, u8 *blue,
 406                           u8 __iomem *mmio)
 407 {
 408         i810_writeb(CLUT_INDEX_READ, mmio, regno);
 409         *red = i810_readb(CLUT_DATA, mmio);
 410         *green = i810_readb(CLUT_DATA, mmio);
 411         *blue = i810_readb(CLUT_DATA, mmio);
 412 }
 413
 414 /************************************************************
 415  *                   VGA State Restore                      *
 416  ************************************************************/
 417 static void i810_restore_pll(struct i810fb_par *par)
 418 {
 419         u32 tmp1, tmp2;
 420         u8 __iomem *mmio = par->mmio_start_virtual;
 421
 422         tmp1 = par->hw_state.dclk_2d;
 423         tmp2 = i810_readl(DCLK_2D, mmio);
 424         tmp1 &= ~MN_MASK;
 425         tmp2 &= MN_MASK;
 426         i810_writel(DCLK_2D, mmio, tmp1 | tmp2);
 427
 428         tmp1 = par->hw_state.dclk_1d;
 429         tmp2 = i810_readl(DCLK_1D, mmio);
 430         tmp1 &= ~MN_MASK;
 431         tmp2 &= MN_MASK;
 432         i810_writel(DCLK_1D, mmio, tmp1 | tmp2);
 433
 434         i810_writel(DCLK_0DS, mmio, par->hw_state.dclk_0ds);
 435 }
 436
 437 static void i810_restore_dac(struct i810fb_par *par)
 438 {
 439         u32 tmp1, tmp2;
 440         u8 __iomem *mmio = par->mmio_start_virtual;
 441
 442         tmp1 = par->hw_state.pixconf;
 443         tmp2 = i810_readl(PIXCONF, mmio);
 444         tmp1 &= DAC_BIT;
 445         tmp2 &= ~DAC_BIT;
 446         i810_writel(PIXCONF, mmio, tmp1 | tmp2);
 447 }
 448
 449 static void i810_restore_vgax(struct i810fb_par *par)
 450 {
 451         u8 i, j;
 452         u8 __iomem *mmio = par->mmio_start_virtual;
 453
 454         for (i = 0; i < 4; i++) {
 455                 i810_writeb(CR_INDEX_CGA, mmio, CR30+i);
 456                 i810_writeb(CR_DATA_CGA, mmio, *(&(par->hw_state.cr30) + i));
 457         }
 458         i810_writeb(CR_INDEX_CGA, mmio, CR35);
 459         i810_writeb(CR_DATA_CGA, mmio, par->hw_state.cr35);
 460         i810_writeb(CR_INDEX_CGA, mmio, CR39);
 461         i810_writeb(CR_DATA_CGA, mmio, par->hw_state.cr39);
 462         i810_writeb(CR_INDEX_CGA, mmio, CR41);
 463         i810_writeb(CR_DATA_CGA, mmio, par->hw_state.cr39);
 464
 465         /*restore interlace*/
 466         i810_writeb(CR_INDEX_CGA, mmio, CR70);
 467         i = par->hw_state.cr70;
 468         i &= INTERLACE_BIT;
 469         j = i810_readb(CR_DATA_CGA, mmio);
 470         i810_writeb(CR_INDEX_CGA, mmio, CR70);
 471         i810_writeb(CR_DATA_CGA, mmio, j | i);
 472
 473         i810_writeb(CR_INDEX_CGA, mmio, CR80);
 474         i810_writeb(CR_DATA_CGA, mmio, par->hw_state.cr80);
 475         i810_writeb(MSR_WRITE, mmio, par->hw_state.msr);
 476         i810_writeb(SR_INDEX, mmio, SR01);
 477         i = (par->hw_state.sr01) & ~0xE0 ;
 478         j = i810_readb(SR_DATA, mmio) & 0xE0;
 479         i810_writeb(SR_INDEX, mmio, SR01);
 480         i810_writeb(SR_DATA, mmio, i | j);
 481 }
 482
 483 static void i810_restore_vga(struct i810fb_par *par)
 484 {
 485         u8 i;
 486         u8 __iomem *mmio = par->mmio_start_virtual;
 487
 488         for (i = 0; i < 10; i++) {
 489                 i810_writeb(CR_INDEX_CGA, mmio, CR00 + i);
 490                 i810_writeb(CR_DATA_CGA, mmio, *((&par->hw_state.cr00) + i));
 491         }
 492         for (i = 0; i < 8; i++) {
 493                 i810_writeb(CR_INDEX_CGA, mmio, CR10 + i);
 494                 i810_writeb(CR_DATA_CGA, mmio, *((&par->hw_state.cr10) + i));
 495         }
 496 }
 497
 498 static void i810_restore_addr_map(struct i810fb_par *par)
 499 {
 500         u8 tmp;
 501         u8 __iomem *mmio = par->mmio_start_virtual;
 502
 503         i810_writeb(GR_INDEX, mmio, GR10);
 504         tmp = i810_readb(GR_DATA, mmio);
 505         tmp &= ADDR_MAP_MASK;
 506         tmp |= par->hw_state.gr10;
 507         i810_writeb(GR_INDEX, mmio, GR10);
 508         i810_writeb(GR_DATA, mmio, tmp);
 509 }
 510
 511 static void i810_restore_2d(struct i810fb_par *par)
 512 {
 513         u32 tmp_long;
 514         u16 tmp_word;
 515         u8 __iomem *mmio = par->mmio_start_virtual;
 516
 517         tmp_word = i810_readw(BLTCNTL, mmio);
 518         tmp_word &= ~(3 << 4);
 519         tmp_word |= par->hw_state.bltcntl;
 520         i810_writew(BLTCNTL, mmio, tmp_word);
 521
 522         i810_dram_off(mmio, OFF);
 523         i810_writel(PIXCONF, mmio, par->hw_state.pixconf);
 524         i810_dram_off(mmio, ON);
 525
 526         tmp_word = i810_readw(HWSTAM, mmio);
 527         tmp_word &= 3 << 13;
 528         tmp_word |= par->hw_state.hwstam;
 529         i810_writew(HWSTAM, mmio, tmp_word);
 530
 531         tmp_long = i810_readl(FW_BLC, mmio);
 532         tmp_long &= FW_BLC_MASK;
 533         tmp_long |= par->hw_state.fw_blc;
 534         i810_writel(FW_BLC, mmio, tmp_long);
 535
 536         i810_writel(HWS_PGA, mmio, par->hw_state.hws_pga);
 537         i810_writew(IER, mmio, par->hw_state.ier);
 538         i810_writew(IMR, mmio, par->hw_state.imr);
 539         i810_writel(DPLYSTAS, mmio, par->hw_state.dplystas);
 540 }
 541
 542 static void i810_restore_vga_state(struct i810fb_par *par)
 543 {
 544         u8 __iomem *mmio = par->mmio_start_virtual;
 545
 546         i810_screen_off(mmio, OFF);
 547         i810_protect_regs(mmio, OFF);
 548         i810_dram_off(mmio, OFF);
 549         i810_restore_pll(par);
 550         i810_restore_dac(par);
 551         i810_restore_vga(par);
 552         i810_restore_vgax(par);
 553         i810_restore_addr_map(par);
 554         i810_dram_off(mmio, ON);
 555         i810_restore_2d(par);
 556         i810_screen_off(mmio, ON);
 557         i810_protect_regs(mmio, ON);
 558 }
 559
 560 /***********************************************************************
 561  *                         VGA State Save                              *
 562  ***********************************************************************/
 563
 564 static void i810_save_vgax(struct i810fb_par *par)
 565 {
 566         u8 i;
 567         u8 __iomem *mmio = par->mmio_start_virtual;
 568
 569         for (i = 0; i < 4; i++) {
 570                 i810_writeb(CR_INDEX_CGA, mmio, CR30 + i);
 571                 *(&(par->hw_state.cr30) + i) = i810_readb(CR_DATA_CGA, mmio);
 572         }
 573         i810_writeb(CR_INDEX_CGA, mmio, CR35);
 574         par->hw_state.cr35 = i810_readb(CR_DATA_CGA, mmio);
 575         i810_writeb(CR_INDEX_CGA, mmio, CR39);
 576         par->hw_state.cr39 = i810_readb(CR_DATA_CGA, mmio);
 577         i810_writeb(CR_INDEX_CGA, mmio, CR41);
 578         par->hw_state.cr41 = i810_readb(CR_DATA_CGA, mmio);
 579         i810_writeb(CR_INDEX_CGA, mmio, CR70);
 580         par->hw_state.cr70 = i810_readb(CR_DATA_CGA, mmio);
 581         par->hw_state.msr = i810_readb(MSR_READ, mmio);
 582         i810_writeb(CR_INDEX_CGA, mmio, CR80);
 583         par->hw_state.cr80 = i810_readb(CR_DATA_CGA, mmio);
 584         i810_writeb(SR_INDEX, mmio, SR01);
 585         par->hw_state.sr01 = i810_readb(SR_DATA, mmio);
 586 }
 587
 588 static void i810_save_vga(struct i810fb_par *par)
 589 {
 590         u8 i;
 591         u8 __iomem *mmio = par->mmio_start_virtual;
 592
 593         for (i = 0; i < 10; i++) {
 594                 i810_writeb(CR_INDEX_CGA, mmio, CR00 + i);
 595                 *((&par->hw_state.cr00) + i) = i810_readb(CR_DATA_CGA, mmio);
 596         }
 597         for (i = 0; i < 8; i++) {
 598                 i810_writeb(CR_INDEX_CGA, mmio, CR10 + i);
 599                 *((&par->hw_state.cr10) + i) = i810_readb(CR_DATA_CGA, mmio);
 600         }
 601 }
 602
 603 static void i810_save_2d(struct i810fb_par *par)
 604 {
 605         u8 __iomem *mmio = par->mmio_start_virtual;
 606
 607         par->hw_state.dclk_2d = i810_readl(DCLK_2D, mmio);
 608         par->hw_state.dclk_1d = i810_readl(DCLK_1D, mmio);
 609         par->hw_state.dclk_0ds = i810_readl(DCLK_0DS, mmio);
 610         par->hw_state.pixconf = i810_readl(PIXCONF, mmio);
 611         par->hw_state.fw_blc = i810_readl(FW_BLC, mmio);
 612         par->hw_state.bltcntl = i810_readw(BLTCNTL, mmio);
 613         par->hw_state.hwstam = i810_readw(HWSTAM, mmio);
 614         par->hw_state.hws_pga = i810_readl(HWS_PGA, mmio);
 615         par->hw_state.ier = i810_readw(IER, mmio);
 616         par->hw_state.imr = i810_readw(IMR, mmio);
 617         par->hw_state.dplystas = i810_readl(DPLYSTAS, mmio);
 618 }
 619
 620 static void i810_save_vga_state(struct i810fb_par *par)
 621 {
 622         i810_save_vga(par);
 623         i810_save_vgax(par);
 624         i810_save_2d(par);
 625 }
 626
 627 /************************************************************
 628  *                    Helpers                               *
 629  ************************************************************/
 630 /**
 631  * get_line_length - calculates buffer pitch in bytes
 632  * @par: pointer to i810fb_par structure
 633  * @xres_virtual: virtual resolution of the frame
 634  * @bpp: bits per pixel
 635  *
 636  * DESCRIPTION:
 637  * Calculates buffer pitch in bytes.
 638  */
 639 static u32 get_line_length(struct i810fb_par *par, int xres_virtual, int bpp)
 640 {
 641         u32 length;
 642
 643         length = xres_virtual*bpp;
 644         length = (length+31)&-32;
 645         length >>= 3;
 646         return length;
 647 }
 648
 649 /**
 650  * i810_calc_dclk - calculates the P, M, and N values of a pixelclock value
 651  * @freq: target pixelclock in picoseconds
 652  * @m: where to write M register
 653  * @n: where to write N register
 654  * @p: where to write P register
 655  *
 656  * DESCRIPTION:
 657  * Based on the formula Freq_actual = (4*M*Freq_ref)/(N^P)
 658  * Repeatedly computes the Freq until the actual Freq is equal to
 659  * the target Freq or until the loop count is zero.  In the latter
 660  * case, the actual frequency nearest the target will be used.
 661  */
 662 static void i810_calc_dclk(u32 freq, u32 *m, u32 *n, u32 *p)
 663 {
 664         u32 m_reg, n_reg, p_divisor, n_target_max;
 665         u32 m_target, n_target, p_target, n_best, m_best, mod;
 666         u32 f_out, target_freq, diff = 0, mod_min, diff_min;
 667
 668         diff_min = mod_min = 0xFFFFFFFF;
 669         n_best = m_best = m_target = f_out = 0;
 670
 671         target_freq =  freq;
 672         n_target_max = 30;
 673
 674         /*
 675          * find P such that target freq is 16x reference freq (Hz).
 676          */
 677         p_divisor = 1;
 678         p_target = 0;
 679         while(!((1000000 * p_divisor)/(16 * 24 * target_freq)) &&
 680               p_divisor <= 32) {
 681                 p_divisor <<= 1;
 682                 p_target++;
 683         }
 684
 685         n_reg = m_reg = n_target = 3;
 686         while (diff_min && mod_min && (n_target < n_target_max)) {
 687                 f_out = (p_divisor * n_reg * 1000000)/(4 * 24 * m_reg);
 688                 mod = (p_divisor * n_reg * 1000000) % (4 * 24 * m_reg);
 689                 m_target = m_reg;
 690                 n_target = n_reg;
 691                 if (f_out <= target_freq) {
 692                         n_reg++;
 693                         diff = target_freq - f_out;
 694                 } else {
 695                         m_reg++;
 696                         diff = f_out - target_freq;
 697                 }
 698
 699                 if (diff_min > diff) {
 700                         diff_min = diff;
 701                         n_best = n_target;
 702                         m_best = m_target;
 703                 }
 704
 705                 if (!diff && mod_min > mod) {
 706                         mod_min = mod;
 707                         n_best = n_target;
 708                         m_best = m_target;
 709                 }
 710         }
 711         if (m) *m = (m_best - 2) & 0x3FF;
 712         if (n) *n = (n_best - 2) & 0x3FF;
 713         if (p) *p = (p_target << 4);
 714 }
 715
 716 /*************************************************************
 717  *                Hardware Cursor Routines                   *
 718  *************************************************************/
 719
 720 /**
 721  * i810_enable_cursor - show or hide the hardware cursor
 722  * @mmio: address of register space
 723  * @mode: show (1) or hide (0)
 724  *
 725  * Description:
 726  * Shows or hides the hardware cursor
 727  */
 728 static void i810_enable_cursor(u8 __iomem *mmio, int mode)
 729 {
 730         u32 temp;
 731
 732         temp = i810_readl(PIXCONF, mmio);
 733         temp = (mode == ON) ? temp | CURSOR_ENABLE_MASK :
 734                 temp & ~CURSOR_ENABLE_MASK;
 735
 736         i810_writel(PIXCONF, mmio, temp);
 737 }
 738
 739 static void i810_reset_cursor_image(struct i810fb_par *par)
 740 {
 741         u8 __iomem *addr = par->cursor_heap.virtual;
 742         int i, j;
 743
 744         for (i = 64; i--; ) {
 745                 for (j = 0; j < 8; j++) {
 746                         i810_writeb(j, addr, 0xff);
 747                         i810_writeb(j+8, addr, 0x00);
 748                 }
 749                 addr +=16;
 750         }
 751 }
 752
 753 static void i810_load_cursor_image(int width, int height, u8 *data,
 754                                    struct i810fb_par *par)
 755 {
 756         u8 __iomem *addr = par->cursor_heap.virtual;
 757         int i, j, w = width/8;
 758         int mod = width % 8, t_mask, d_mask;
 759
 760         t_mask = 0xff >> mod;
 761         d_mask = ~(0xff >> mod);
 762         for (i = height; i--; ) {
 763                 for (j = 0; j < w; j++) {
 764                         i810_writeb(j+0, addr, 0x00);
 765                         i810_writeb(j+8, addr, *data++);
 766                 }
 767                 if (mod) {
 768                         i810_writeb(j+0, addr, t_mask);
 769                         i810_writeb(j+8, addr, *data++ & d_mask);
 770                 }
 771                 addr += 16;
 772         }
 773 }
 774
 775 static void i810_load_cursor_colors(int fg, int bg, struct fb_info *info)
 776 {
 777         struct i810fb_par *par = (struct i810fb_par *) info->par;
 778         u8 __iomem *mmio = par->mmio_start_virtual;
 779         u8 red, green, blue, trans, temp;
 780
 781         i810fb_getcolreg(bg, &red, &green, &blue, &trans, info);
 782
 783         temp = i810_readb(PIXCONF1, mmio);
 784         i810_writeb(PIXCONF1, mmio, temp | EXTENDED_PALETTE);
 785
 786         i810_write_dac(4, red, green, blue, mmio);
 787
 788         i810_writeb(PIXCONF1, mmio, temp);
 789
 790         i810fb_getcolreg(fg, &red, &green, &blue, &trans, info);
 791         temp = i810_readb(PIXCONF1, mmio);
 792         i810_writeb(PIXCONF1, mmio, temp | EXTENDED_PALETTE);
 793
 794         i810_write_dac(5, red, green, blue, mmio);
 795
 796         i810_writeb(PIXCONF1, mmio, temp);
 797 }
 798
 799 /**
 800  * i810_init_cursor - initializes the cursor
 801  * @par: pointer to i810fb_par structure
 802  *
 803  * DESCRIPTION:
 804  * Initializes the cursor registers
 805  */
 806 static void i810_init_cursor(struct i810fb_par *par)
 807 {
 808         u8 __iomem *mmio = par->mmio_start_virtual;
 809
 810         i810_enable_cursor(mmio, OFF);
 811         i810_writel(CURBASE, mmio, par->cursor_heap.physical);
 812         i810_writew(CURCNTR, mmio, COORD_ACTIVE | CURSOR_MODE_64_XOR);
 813 }
 814
 815 /*********************************************************************
 816  *                    Framebuffer hook helpers                       *
 817  *********************************************************************/
 818 /**
 819  * i810_round_off -  Round off values to capability of hardware
 820  * @var: pointer to fb_var_screeninfo structure
 821  *
 822  * DESCRIPTION:
 823  * @var contains user-defined information for the mode to be set.
 824  * This will try modify those values to ones nearest the
 825  * capability of the hardware
 826  */
 827 static void i810_round_off(struct fb_var_screeninfo *var)
 828 {
 829         u32 xres, yres, vxres, vyres;
 830
 831         /*
 832          *  Presently supports only these configurations
 833          */
 834
 835         xres = var->xres;
 836         yres = var->yres;
 837         vxres = var->xres_virtual;
 838         vyres = var->yres_virtual;
 839
 840         var->bits_per_pixel += 7;
 841         var->bits_per_pixel &= ~7;
 842
 843         if (var->bits_per_pixel < 8)
 844                 var->bits_per_pixel = 8;
 845         if (var->bits_per_pixel > 32)
 846                 var->bits_per_pixel = 32;
 847
 848         round_off_xres(&xres);
 849         if (xres < 40)
 850                 xres = 40;
 851         if (xres > 2048)
 852                 xres = 2048;
 853         xres = (xres + 7) & ~7;
 854
 855         if (vxres < xres)
 856                 vxres = xres;
 857
 858         round_off_yres(&xres, &yres);
 859         if (yres < 1)
 860                 yres = 1;
 861         if (yres >= 2048)
 862                 yres = 2048;
 863
 864         if (vyres < yres)
 865                 vyres = yres;
 866
 867         if (var->bits_per_pixel == 32)
 868                 var->accel_flags = 0;
 869
 870         /* round of horizontal timings to nearest 8 pixels */
 871         var->left_margin = (var->left_margin + 4) & ~7;
 872         var->right_margin = (var->right_margin + 4) & ~7;
 873         var->hsync_len = (var->hsync_len + 4) & ~7;
 874
 875         if (var->vmode & FB_VMODE_INTERLACED) {
 876                 if (!((yres + var->upper_margin + var->vsync_len +
 877                        var->lower_margin) & 1))
 878                         var->upper_margin++;
 879         }
 880
 881         var->xres = xres;
 882         var->yres = yres;
 883         var->xres_virtual = vxres;
 884         var->yres_virtual = vyres;
 885 }
 886
 887 /**
 888  * set_color_bitfields - sets rgba fields
 889  * @var: pointer to fb_var_screeninfo
 890  *
 891  * DESCRIPTION:
 892  * The length, offset and ordering  for each color field
 893  * (red, green, blue)  will be set as specified
 894  * by the hardware
 895  */
 896 static void set_color_bitfields(struct fb_var_screeninfo *var)
 897 {
 898         switch (var->bits_per_pixel) {
 899         case 8:
 900                 var->red.offset = 0;
 901                 var->red.length = 8;
 902                 var->green.offset = 0;
 903                 var->green.length = 8;
 904                 var->blue.offset = 0;
 905                 var->blue.length = 8;
 906                 var->transp.offset = 0;
 907                 var->transp.length = 0;
 908                 break;
 909         case 16:
 910                 var->green.length = (var->green.length == 5) ? 5 : 6;
 911                 var->red.length = 5;
 912                 var->blue.length = 5;
 913                 var->transp.length = 6 - var->green.length;
 914                 var->blue.offset = 0;
 915                 var->green.offset = 5;
 916                 var->red.offset = 5 + var->green.length;
 917                 var->transp.offset =  (5 + var->red.offset) & 15;
 918                 break;
 919         case 24:        /* RGB 888   */
 920         case 32:        /* RGBA 8888 */
 921                 var->red.offset = 16;
 922                 var->red.length = 8;
 923                 var->green.offset = 8;
 924                 var->green.length = 8;
 925                 var->blue.offset = 0;
 926                 var->blue.length = 8;
 927                 var->transp.length = var->bits_per_pixel - 24;
 928                 var->transp.offset = (var->transp.length) ? 24 : 0;
 929                 break;
 930         }
 931         var->red.msb_right = 0;
 932         var->green.msb_right = 0;
 933         var->blue.msb_right = 0;
 934         var->transp.msb_right = 0;
 935 }
 936
 937 /**
 938  * i810_check_params - check if contents in var are valid
 939  * @var: pointer to fb_var_screeninfo
 940  * @info: pointer to fb_info
 941  *
 942  * DESCRIPTION:
 943  * This will check if the framebuffer size is sufficient
 944  * for the current mode and if the user's monitor has the
 945  * required specifications to display the current mode.
 946  */
 947 static int i810_check_params(struct fb_var_screeninfo *var,
 948                              struct fb_info *info)
 949 {
 950         struct i810fb_par *par = (struct i810fb_par *) info->par;
 951         int line_length, vidmem, mode_valid = 0;
 952         u32 vyres = var->yres_virtual, vxres = var->xres_virtual;
 953         /*
 954          *  Memory limit
 955          */
 956         line_length = get_line_length(par, vxres, var->bits_per_pixel);
 957         vidmem = line_length*vyres;
 958
 959         if (vidmem > par->fb.size) {
 960                 vyres = par->fb.size/line_length;
 961                 if (vyres < var->yres) {
 962                         vyres = yres;
 963                         vxres = par->fb.size/vyres;
 964                         vxres /= var->bits_per_pixel >> 3;
 965                         line_length = get_line_length(par, vxres,
 966                                                       var->bits_per_pixel);
 967                         vidmem = line_length * yres;
 968                         if (vxres < var->xres) {
 969                                 printk("i810fb: required video memory, "
 970                                        "%d bytes, for %dx%d-%d (virtual) "
 971                                        "is out of range\n",
 972                                        vidmem, vxres, vyres,
 973                                        var->bits_per_pixel);
 974                                 return -ENOMEM;
 975                         }
 976                 }
 977         }
 978
 979         var->xres_virtual = vxres;
 980         var->yres_virtual = vyres;
 981
 982         /*
 983          * Monitor limit
 984          */
 985         switch (var->bits_per_pixel) {
 986         case 8:
 987                 info->monspecs.dclkmax = 234000000;
 988                 break;
 989         case 16:
 990                 info->monspecs.dclkmax = 229000000;
 991                 break;
 992         case 24:
 993         case 32:
 994                 info->monspecs.dclkmax = 204000000;
 995                 break;
 996         }
 997
 998         info->monspecs.dclkmin = 15000000;
 999
1000         if (!fb_validate_mode(var, info))
1001                 mode_valid = 1;
1002
1003 #ifdef CONFIG_FB_I810_I2C
1004         if (!mode_valid && info->monspecs.gtf &&
1005             !fb_get_mode(FB_MAXTIMINGS, 0, var, info))
1006                 mode_valid = 1;
1007
1008         if (!mode_valid && info->monspecs.modedb_len) {
1009                 struct fb_videomode *mode;
1010
1011                 mode = fb_find_best_mode(var, &info->modelist);
1012                 if (mode) {
1013                         fb_videomode_to_var(var, mode);
1014                         mode_valid = 1;
1015                 }
1016         }
1017 #endif
1018         if (!mode_valid && info->monspecs.modedb_len == 0) {
1019                 if (fb_get_mode(FB_MAXTIMINGS, 0, var, info)) {
1020                         int default_sync = (info->monspecs.hfmin-HFMIN)
1021                                 |(info->monspecs.hfmax-HFMAX)
1022                                 |(info->monspecs.vfmin-VFMIN)
1023                                 |(info->monspecs.vfmax-VFMAX);
1024                         printk("i810fb: invalid video mode%s\n",
1025                                default_sync ? "" : ". Specifying "
1026                                "vsyncN/hsyncN parameters may help");
1027                 }
1028         }
1029
1030         return 0;
1031 }
1032
1033 /**
1034  * encode_fix - fill up fb_fix_screeninfo structure
1035  * @fix: pointer to fb_fix_screeninfo
1036  * @info: pointer to fb_info
1037  *
1038  * DESCRIPTION:
1039  * This will set up parameters that are unmodifiable by the user.
1040  */
1041 static int encode_fix(struct fb_fix_screeninfo *fix, struct fb_info *info)
1042 {
1043         struct i810fb_par *par = (struct i810fb_par *) info->par;
1044
1045         memset(fix, 0, sizeof(struct fb_fix_screeninfo));
1046
1047         strcpy(fix->id, "I810");
1048         fix->smem_start = par->fb.physical;
1049         fix->smem_len = par->fb.size;
1050         fix->type = FB_TYPE_PACKED_PIXELS;
1051         fix->type_aux = 0;
1052         fix->xpanstep = 8;
1053         fix->ypanstep = 1;
1054
1055         switch (info->var.bits_per_pixel) {
1056         case 8:
1057                 fix->visual = FB_VISUAL_PSEUDOCOLOR;
1058                 break;
1059         case 16:
1060         case 24:
1061         case 32:
1062                 if (info->var.nonstd)
1063                         fix->visual = FB_VISUAL_DIRECTCOLOR;
1064                 else
1065                         fix->visual = FB_VISUAL_TRUECOLOR;
1066                 break;
1067         default:
1068                 return -EINVAL;
1069         }
1070         fix->ywrapstep = 0;
1071         fix->line_length = par->pitch;
1072         fix->mmio_start = par->mmio_start_phys;
1073         fix->mmio_len = MMIO_SIZE;
1074         fix->accel = FB_ACCEL_I810;
1075
1076         return 0;
1077 }
1078
1079 /**
1080  * decode_var - modify par according to contents of var
1081  * @var: pointer to fb_var_screeninfo
1082  * @par: pointer to i810fb_par
1083  *
1084  * DESCRIPTION:
1085  * Based on the contents of @var, @par will be dynamically filled up.
1086  * @par contains all information necessary to modify the hardware.
1087 */
1088 static void decode_var(const struct fb_var_screeninfo *var,
1089                        struct i810fb_par *par)
1090 {
1091         u32 xres, yres, vxres, vyres;
1092
1093         xres = var->xres;
1094         yres = var->yres;
1095         vxres = var->xres_virtual;
1096         vyres = var->yres_virtual;
1097
1098         switch (var->bits_per_pixel) {
1099         case 8:
1100                 par->pixconf = PIXCONF8;
1101                 par->bltcntl = 0;
1102                 par->depth = 1;
1103                 par->blit_bpp = BPP8;
1104                 break;
1105         case 16:
1106                 if (var->green.length == 5)
1107                         par->pixconf = PIXCONF15;
1108                 else
1109                         par->pixconf = PIXCONF16;
1110                 par->bltcntl = 16;
1111                 par->depth = 2;
1112                 par->blit_bpp = BPP16;
1113                 break;
1114         case 24:
1115                 par->pixconf = PIXCONF24;
1116                 par->bltcntl = 32;
1117                 par->depth = 3;
1118                 par->blit_bpp = BPP24;
1119                 break;
1120         case 32:
1121                 par->pixconf = PIXCONF32;
1122                 par->bltcntl = 0;
1123                 par->depth = 4;
1124                 par->blit_bpp = 3 << 24;
1125                 break;
1126         }
1127         if (var->nonstd && var->bits_per_pixel != 8)
1128                 par->pixconf |= 1 << 27;
1129
1130         i810_calc_dclk(var->pixclock, &par->regs.M,
1131                        &par->regs.N, &par->regs.P);
1132         i810fb_encode_registers(var, par, xres, yres);
1133
1134         par->watermark = i810_get_watermark(var, par);
1135         par->pitch = get_line_length(par, vxres, var->bits_per_pixel);
1136 }
1137
1138 /**
1139  * i810fb_getcolreg - gets red, green and blue values of the hardware DAC
1140  * @regno: DAC index
1141  * @red: red
1142  * @green: green
1143  * @blue: blue
1144  * @transp: transparency (alpha)
1145  * @info: pointer to fb_info
1146  *
1147  * DESCRIPTION:
1148  * Gets the red, green and blue values of the hardware DAC as pointed by @regno
1149  * and writes them to @red, @green and @blue respectively
1150  */
1151 static int i810fb_getcolreg(u8 regno, u8 *red, u8 *green, u8 *blue,
1152                             u8 *transp, struct fb_info *info)
1153 {
1154         struct i810fb_par *par = (struct i810fb_par *) info->par;
1155         u8 __iomem *mmio = par->mmio_start_virtual;
1156         u8 temp;
1157
1158         if (info->fix.visual == FB_VISUAL_DIRECTCOLOR) {
1159                 if ((info->var.green.length == 5 && regno > 31) ||
1160                     (info->var.green.length == 6 && regno > 63))
1161                         return 1;
1162         }
1163
1164         temp = i810_readb(PIXCONF1, mmio);
1165         i810_writeb(PIXCONF1, mmio, temp & ~EXTENDED_PALETTE);
1166
1167         if (info->fix.visual == FB_VISUAL_DIRECTCOLOR &&
1168             info->var.green.length == 5)
1169                 i810_read_dac(regno * 8, red, green, blue, mmio);
1170
1171         else if (info->fix.visual == FB_VISUAL_DIRECTCOLOR &&
1172                  info->var.green.length == 6) {
1173                 u8 tmp;
1174
1175                 i810_read_dac(regno * 8, red, &tmp, blue, mmio);
1176                 i810_read_dac(regno * 4, &tmp, green, &tmp, mmio);
1177         }
1178         else
1179                 i810_read_dac(regno, red, green, blue, mmio);
1180
1181         *transp = 0;
1182         i810_writeb(PIXCONF1, mmio, temp);
1183
1184         return 0;
1185 }
1186
1187 /******************************************************************
1188  *           Framebuffer device-specific hooks                    *
1189  ******************************************************************/
1190
1191 static int i810fb_open(struct fb_info *info, int user)
1192 {
1193         struct i810fb_par *par = (struct i810fb_par *) info->par;
1194         u32 count = atomic_read(&par->use_count);
1195
1196         if (count == 0) {
1197                 memset(&par->state, 0, sizeof(struct vgastate));
1198                 par->state.flags = VGA_SAVE_CMAP;
1199                 par->state.vgabase = par->mmio_start_virtual;
1200                 save_vga(&par->state);
1201
1202                 i810_save_vga_state(par);
1203         }
1204
1205         atomic_inc(&par->use_count);
1206
1207         return 0;
1208 }
1209
1210 static int i810fb_release(struct fb_info *info, int user)
1211 {
1212         struct i810fb_par *par = (struct i810fb_par *) info->par;
1213         u32 count;
1214
1215         count = atomic_read(&par->use_count);
1216         if (count == 0)
1217                 return -EINVAL;
1218
1219         if (count == 1) {
1220                 i810_restore_vga_state(par);
1221                 restore_vga(&par->state);
1222         }
1223
1224         atomic_dec(&par->use_count);
1225
1226         return 0;
1227 }
1228
1229
1230 static int i810fb_setcolreg(unsigned regno, unsigned red, unsigned green,
1231                             unsigned blue, unsigned transp,
1232                             struct fb_info *info)
1233 {
1234         struct i810fb_par *par = (struct i810fb_par *) info->par;
1235         u8 __iomem *mmio = par->mmio_start_virtual;
1236         u8 temp;
1237         int i;
1238
1239         if (regno > 255) return 1;
1240
1241         if (info->fix.visual == FB_VISUAL_DIRECTCOLOR) {
1242                 if ((info->var.green.length == 5 && regno > 31) ||
1243                     (info->var.green.length == 6 && regno > 63))
1244                         return 1;
1245         }
1246
1247         if (info->var.grayscale)
1248                 red = green = blue = (19595 * red + 38470 * green +
1249                                       7471 * blue) >> 16;
1250
1251         temp = i810_readb(PIXCONF1, mmio);
1252         i810_writeb(PIXCONF1, mmio, temp & ~EXTENDED_PALETTE);
1253
1254         if (info->fix.visual == FB_VISUAL_DIRECTCOLOR &&
1255             info->var.green.length == 5) {
1256                 for (i = 0; i < 8; i++)
1257                         i810_write_dac((u8) (regno * 8) + i, (u8) red,
1258                                        (u8) green, (u8) blue, mmio);
1259         } else if (info->fix.visual == FB_VISUAL_DIRECTCOLOR &&
1260                  info->var.green.length == 6) {
1261                 u8 r, g, b;
1262
1263                 if (regno < 32) {
1264                         for (i = 0; i < 8; i++)
1265                                 i810_write_dac((u8) (regno * 8) + i,
1266                                                (u8) red, (u8) green,
1267                                                (u8) blue, mmio);
1268                 }
1269                 i810_read_dac((u8) (regno*4), &r, &g, &b, mmio);
1270                 for (i = 0; i < 4; i++)
1271                         i810_write_dac((u8) (regno*4) + i, r, (u8) green,
1272                                        b, mmio);
1273         } else if (info->fix.visual == FB_VISUAL_PSEUDOCOLOR) {
1274                 i810_write_dac((u8) regno, (u8) red, (u8) green,
1275                                (u8) blue, mmio);
1276         }
1277
1278         i810_writeb(PIXCONF1, mmio, temp);
1279
1280         if (regno < 16) {
1281                 switch (info->var.bits_per_pixel) {
1282                 case 16:
1283                         if (info->fix.visual == FB_VISUAL_DIRECTCOLOR) {
1284                                 if (info->var.green.length == 5)
1285                                         ((u32 *)info->pseudo_palette)[regno] =
1286                                                 (regno << 10) | (regno << 5) |
1287                                                 regno;
1288                                 else
1289                                         ((u32 *)info->pseudo_palette)[regno] =
1290                                                 (regno << 11) | (regno << 5) |
1291                                                 regno;
1292                         } else {
1293                                 if (info->var.green.length == 5) {
1294                                         /* RGB 555 */
1295                                         ((u32 *)info->pseudo_palette)[regno] =
1296                                                 ((red & 0xf800) >> 1) |
1297                                                 ((green & 0xf800) >> 6) |
1298                                                 ((blue & 0xf800) >> 11);
1299                                 } else {
1300                                         /* RGB 565 */
1301                                         ((u32 *)info->pseudo_palette)[regno] =
1302                                                 (red & 0xf800) |
1303                                                 ((green & 0xf800) >> 5) |
1304                                                 ((blue & 0xf800) >> 11);
1305                                 }
1306                         }
1307                         break;
1308                 case 24:        /* RGB 888 */
1309                 case 32:        /* RGBA 8888 */
1310                         if (info->fix.visual == FB_VISUAL_DIRECTCOLOR)
1311                                 ((u32 *)info->pseudo_palette)[regno] =
1312                                         (regno << 16) | (regno << 8) |
1313                                         regno;
1314                         else
1315                                 ((u32 *)info->pseudo_palette)[regno] =
1316                                         ((red & 0xff00) << 8) |
1317                                         (green & 0xff00) |
1318                                         ((blue & 0xff00) >> 8);
1319                         break;
1320                 }
1321         }
1322         return 0;
1323 }
1324
1325 static int i810fb_pan_display(struct fb_var_screeninfo *var,
1326                               struct fb_info *info)
1327 {
1328         struct i810fb_par *par = (struct i810fb_par *) info->par;
1329         u32 total;
1330
1331         total = var->xoffset * par->depth +
1332                 var->yoffset * info->fix.line_length;
1333         i810fb_load_front(total, info);
1334
1335         return 0;
1336 }
1337
1338 static int i810fb_blank (int blank_mode, struct fb_info *info)
1339 {
1340         struct i810fb_par *par = (struct i810fb_par *) info->par;
1341         u8 __iomem *mmio = par->mmio_start_virtual;
1342         int mode = 0, pwr, scr_off = 0;
1343
1344         pwr = i810_readl(PWR_CLKC, mmio);
1345
1346         switch (blank_mode) {
1347         case FB_BLANK_UNBLANK:
1348                 mode = POWERON;
1349                 pwr |= 1;
1350                 scr_off = ON;
1351                 break;
1352         case FB_BLANK_NORMAL:
1353                 mode = POWERON;
1354                 pwr |= 1;
1355                 scr_off = OFF;
1356                 break;
1357         case FB_BLANK_VSYNC_SUSPEND:
1358                 mode = STANDBY;
1359                 pwr |= 1;
1360                 scr_off = OFF;
1361                 break;
1362         case FB_BLANK_HSYNC_SUSPEND:
1363                 mode = SUSPEND;
1364                 pwr |= 1;
1365                 scr_off = OFF;
1366                 break;
1367         case FB_BLANK_POWERDOWN:
1368                 mode = POWERDOWN;
1369                 pwr &= ~1;
1370                 scr_off = OFF;
1371                 break;
1372         default:
1373                 return -EINVAL;
1374         }
1375
1376         i810_screen_off(mmio, scr_off);
1377         i810_writel(HVSYNC, mmio, mode);
1378         i810_writel(PWR_CLKC, mmio, pwr);
1379
1380         return 0;
1381 }
1382
1383 static int i810fb_set_par(struct fb_info *info)
1384 {
1385         struct i810fb_par *par = (struct i810fb_par *) info->par;
1386
1387         decode_var(&info->var, par);
1388         i810_load_regs(par);
1389         i810_init_cursor(par);
1390         encode_fix(&info->fix, info);
1391
1392         if (info->var.accel_flags && !(par->dev_flags & LOCKUP)) {
1393                 info->flags = FBINFO_DEFAULT | FBINFO_HWACCEL_YPAN |
1394                 FBINFO_HWACCEL_COPYAREA | FBINFO_HWACCEL_FILLRECT |
1395                 FBINFO_HWACCEL_IMAGEBLIT;
1396                 info->pixmap.scan_align = 2;
1397         } else {
1398                 info->pixmap.scan_align = 1;
1399                 info->flags = FBINFO_DEFAULT | FBINFO_HWACCEL_YPAN;
1400         }
1401         return 0;
1402 }
1403
1404 static int i810fb_check_var(struct fb_var_screeninfo *var,
1405                             struct fb_info *info)
1406 {
1407         int err;
1408
1409         if (IS_DVT) {
1410                 var->vmode &= ~FB_VMODE_MASK;
1411                 var->vmode |= FB_VMODE_NONINTERLACED;
1412         }
1413         if (var->vmode & FB_VMODE_DOUBLE) {
1414                 var->vmode &= ~FB_VMODE_MASK;
1415                 var->vmode |= FB_VMODE_NONINTERLACED;
1416         }
1417
1418         i810_round_off(var);
1419         if ((err = i810_check_params(var, info)))
1420                 return err;
1421
1422         i810fb_fill_var_timings(var);
1423         set_color_bitfields(var);
1424         return 0;
1425 }
1426
1427 static int i810fb_cursor(struct fb_info *info, struct fb_cursor *cursor)
1428 {
1429         struct i810fb_par *par = (struct i810fb_par *)info->par;
1430         u8 __iomem *mmio = par->mmio_start_virtual;
1431
1432         if (!par->dev_flags & LOCKUP)
1433                 return -ENXIO;
1434
1435         if (cursor->image.width > 64 || cursor->image.height > 64)
1436                 return -ENXIO;
1437
1438         if ((i810_readl(CURBASE, mmio) & 0xf) != par->cursor_heap.physical) {
1439                 i810_init_cursor(par);
1440                 cursor->set |= FB_CUR_SETALL;
1441         }
1442
1443         i810_enable_cursor(mmio, OFF);
1444
1445         if (cursor->set & FB_CUR_SETPOS) {
1446                 u32 tmp;
1447
1448                 tmp = (cursor->image.dx - info->var.xoffset) & 0xffff;
1449                 tmp |= (cursor->image.dy - info->var.yoffset) << 16;
1450                 i810_writel(CURPOS, mmio, tmp);
1451         }
1452
1453         if (cursor->set & FB_CUR_SETSIZE)
1454                 i810_reset_cursor_image(par);
1455
1456         if (cursor->set & FB_CUR_SETCMAP)
1457                 i810_load_cursor_colors(cursor->image.fg_color,
1458                                         cursor->image.bg_color,
1459                                         info);
1460
1461         if (cursor->set & (FB_CUR_SETSHAPE | FB_CUR_SETIMAGE)) {
1462                 int size = ((cursor->image.width + 7) >> 3) *
1463                         cursor->image.height;
1464                 int i;
1465                 u8 *data = kmalloc(64 * 8, GFP_KERNEL);
1466
1467                 if (data == NULL)
1468                         return -ENOMEM;
1469
1470                 switch (cursor->rop) {
1471                 case ROP_XOR:
1472                         for (i = 0; i < size; i++)
1473                                 data[i] = cursor->image.data[i] ^ cursor->mask[i];
1474                         break;
1475                 case ROP_COPY:
1476                 default:
1477                         for (i = 0; i < size; i++)
1478                                 data[i] = cursor->image.data[i] & cursor->mask[i];
1479                         break;
1480                 }
1481
1482                 i810_load_cursor_image(cursor->image.width,
1483                                        cursor->image.height, data,
1484                                        par);
1485                 kfree(data);
1486         }
1487
1488         if (cursor->enable)
1489                 i810_enable_cursor(mmio, ON);
1490
1491         return 0;
1492 }
1493
1494 static struct fb_ops i810fb_ops __devinitdata = {
1495         .owner =             THIS_MODULE,
1496         .fb_open =           i810fb_open,
1497         .fb_release =        i810fb_release,
1498         .fb_check_var =      i810fb_check_var,
1499         .fb_set_par =        i810fb_set_par,
1500         .fb_setcolreg =      i810fb_setcolreg,
1501         .fb_blank =          i810fb_blank,
1502         .fb_pan_display =    i810fb_pan_display,
1503         .fb_fillrect =       i810fb_fillrect,
1504         .fb_copyarea =       i810fb_copyarea,
1505         .fb_imageblit =      i810fb_imageblit,
1506         .fb_cursor =         i810fb_cursor,
1507         .fb_sync =           i810fb_sync,
1508 };
1509
1510 /***********************************************************************
1511  *                         Power Management                            *
1512  ***********************************************************************/
1513 static int i810fb_suspend(struct pci_dev *dev, pm_message_t state)
1514 {
1515         struct fb_info *info = pci_get_drvdata(dev);
1516         struct i810fb_par *par = (struct i810fb_par *) info->par;
1517         int blank = 0, prev_state = par->cur_state;
1518
1519         if (state.event == prev_state)
1520                 return 0;
1521
1522         par->cur_state = state.event;
1523
1524         switch (state.event) {
1525         case 1:
1526                 blank = VESA_VSYNC_SUSPEND;
1527                 break;
1528         case 2:
1529                 blank = VESA_HSYNC_SUSPEND;
1530                 break;
1531         case 3:
1532                 blank = VESA_POWERDOWN;
1533                 break;
1534         default:
1535                 return -EINVAL;
1536         }
1537         info->fbops->fb_blank(blank, info);
1538
1539         if (!prev_state) {
1540                 agp_unbind_memory(par->i810_gtt.i810_fb_memory);
1541                 agp_unbind_memory(par->i810_gtt.i810_cursor_memory);
1542                 pci_disable_device(dev);
1543         }
1544         pci_save_state(dev);
1545         pci_set_power_state(dev, pci_choose_state(dev, state));
1546
1547         return 0;
1548 }
1549
1550 static int i810fb_resume(struct pci_dev *dev)
1551 {
1552         struct fb_info *info = pci_get_drvdata(dev);
1553         struct i810fb_par *par = (struct i810fb_par *) info->par;
1554
1555         if (par->cur_state == 0)
1556                 return 0;
1557
1558         pci_restore_state(dev);
1559         pci_set_power_state(dev, PCI_D0);
1560         pci_enable_device(dev);
1561         agp_bind_memory(par->i810_gtt.i810_fb_memory,
1562                         par->fb.offset);
1563         agp_bind_memory(par->i810_gtt.i810_cursor_memory,
1564                         par->cursor_heap.offset);
1565
1566         info->fbops->fb_blank(VESA_NO_BLANKING, info);
1567
1568         par->cur_state = 0;
1569
1570         return 0;
1571 }
1572 /***********************************************************************
1573  *                  AGP resource allocation                            *
1574  ***********************************************************************/
1575
1576 static void __devinit i810_fix_pointers(struct i810fb_par *par)
1577 {
1578         par->fb.physical = par->aperture.physical+(par->fb.offset << 12);
1579         par->fb.virtual = par->aperture.virtual+(par->fb.offset << 12);
1580         par->iring.physical = par->aperture.physical +
1581                 (par->iring.offset << 12);
1582         par->iring.virtual = par->aperture.virtual +
1583                 (par->iring.offset << 12);
1584         par->cursor_heap.virtual = par->aperture.virtual+
1585                 (par->cursor_heap.offset << 12);
1586 }
1587
1588 static void __devinit i810_fix_offsets(struct i810fb_par *par)
1589 {
1590         if (vram + 1 > par->aperture.size >> 20)
1591                 vram = (par->aperture.size >> 20) - 1;
1592         if (v_offset_default > (par->aperture.size >> 20))
1593                 v_offset_default = (par->aperture.size >> 20);
1594         if (vram + v_offset_default + 1 > par->aperture.size >> 20)
1595                 v_offset_default = (par->aperture.size >> 20) - (vram + 1);
1596
1597         par->fb.size = vram << 20;
1598         par->fb.offset = v_offset_default << 20;
1599         par->fb.offset >>= 12;
1600
1601         par->iring.offset = par->fb.offset + (par->fb.size >> 12);
1602         par->iring.size = RINGBUFFER_SIZE;
1603
1604         par->cursor_heap.offset = par->iring.offset + (RINGBUFFER_SIZE >> 12);
1605         par->cursor_heap.size = 4096;
1606 }
1607
1608 static int __devinit i810_alloc_agp_mem(struct fb_info *info)
1609 {
1610         struct i810fb_par *par = (struct i810fb_par *) info->par;
1611         int size;
1612         struct agp_bridge_data *bridge;
1613
1614         i810_fix_offsets(par);
1615         size = par->fb.size + par->iring.size;
1616
1617         if (!(bridge = agp_backend_acquire(par->dev))) {
1618                 printk("i810fb_alloc_fbmem: cannot acquire agpgart\n");
1619                 return -ENODEV;
1620         }
1621         if (!(par->i810_gtt.i810_fb_memory =
1622               agp_allocate_memory(bridge, size >> 12, AGP_NORMAL_MEMORY))) {
1623                 printk("i810fb_alloc_fbmem: can't allocate framebuffer "
1624                        "memory\n");
1625                 agp_backend_release(bridge);
1626                 return -ENOMEM;
1627         }
1628         if (agp_bind_memory(par->i810_gtt.i810_fb_memory,
1629                             par->fb.offset)) {
1630                 printk("i810fb_alloc_fbmem: can't bind framebuffer memory\n");
1631                 agp_backend_release(bridge);
1632                 return -EBUSY;
1633         }
1634
1635         if (!(par->i810_gtt.i810_cursor_memory =
1636               agp_allocate_memory(bridge, par->cursor_heap.size >> 12,
1637                                   AGP_PHYSICAL_MEMORY))) {
1638                 printk("i810fb_alloc_cursormem:  can't allocate"
1639                        "cursor memory\n");
1640                 agp_backend_release(bridge);
1641                 return -ENOMEM;
1642         }
1643         if (agp_bind_memory(par->i810_gtt.i810_cursor_memory,
1644                             par->cursor_heap.offset)) {
1645                 printk("i810fb_alloc_cursormem: cannot bind cursor memory\n");
1646                 agp_backend_release(bridge);
1647                 return -EBUSY;
1648         }
1649
1650         par->cursor_heap.physical = par->i810_gtt.i810_cursor_memory->physical;
1651
1652         i810_fix_pointers(par);
1653
1654         agp_backend_release(bridge);
1655
1656         return 0;
1657 }
1658
1659 /***************************************************************
1660  *                    Initialization                           *
1661  ***************************************************************/
1662
1663 /**
1664  * i810_init_monspecs
1665  * @info: pointer to device specific info structure
1666  *
1667  * DESCRIPTION:
1668  * Sets the the user monitor's horizontal and vertical
1669  * frequency limits
1670  */
1671 static void __devinit i810_init_monspecs(struct fb_info *info)
1672 {
1673         if (!hsync1)
1674                 hsync1 = HFMIN;
1675         if (!hsync2)
1676                 hsync2 = HFMAX;
1677         if (!info->monspecs.hfmax)
1678                 info->monspecs.hfmax = hsync2;
1679         if (!info->monspecs.hfmin)
1680                 info->monspecs.hfmin = hsync1;
1681         if (hsync2 < hsync1)
1682                 info->monspecs.hfmin = hsync2;
1683
1684         if (!vsync1)
1685                 vsync1 = VFMIN;
1686         if (!vsync2)
1687                 vsync2 = VFMAX;
1688         if (IS_DVT && vsync1 < 60)
1689                 vsync1 = 60;
1690         if (!info->monspecs.vfmax)
1691                 info->monspecs.vfmax = vsync2;
1692         if (!info->monspecs.vfmin)
1693                 info->monspecs.vfmin = vsync1;
1694         if (vsync2 < vsync1)
1695                 info->monspecs.vfmin = vsync2;
1696 }
1697
1698 /**
1699  * i810_init_defaults - initializes default values to use
1700  * @par: pointer to i810fb_par structure
1701  * @info: pointer to current fb_info structure
1702  */
1703 static void __devinit i810_init_defaults(struct i810fb_par *par,
1704                                       struct fb_info *info)
1705 {
1706         if (voffset)
1707                 v_offset_default = voffset;
1708         else if (par->aperture.size > 32 * 1024 * 1024)
1709                 v_offset_default = 16;
1710         else
1711                 v_offset_default = 8;
1712
1713         if (!vram)
1714                 vram = 1;
1715
1716         if (accel)
1717                 par->dev_flags |= HAS_ACCELERATION;
1718
1719         if (sync)
1720                 par->dev_flags |= ALWAYS_SYNC;
1721
1722         if (bpp < 8)
1723                 bpp = 8;
1724
1725         if (!vyres)
1726                 vyres = (vram << 20)/(xres*bpp >> 3);
1727
1728         par->i810fb_ops = i810fb_ops;
1729         info->var.xres = xres;
1730         info->var.yres = yres;
1731         info->var.yres_virtual = vyres;
1732         info->var.bits_per_pixel = bpp;
1733
1734         if (dcolor)
1735                 info->var.nonstd = 1;
1736
1737         if (par->dev_flags & HAS_ACCELERATION)
1738                 info->var.accel_flags = 1;
1739
1740         i810_init_monspecs(info);
1741 }
1742
1743 /**
1744  * i810_init_device - initialize device
1745  * @par: pointer to i810fb_par structure
1746  */
1747 static void __devinit i810_init_device(struct i810fb_par *par)
1748 {
1749         u8 reg;
1750         u8 __iomem *mmio = par->mmio_start_virtual;
1751
1752         if (mtrr) set_mtrr(par);
1753
1754         i810_init_cursor(par);
1755
1756         /* mvo: enable external vga-connector (for laptops) */
1757         if (ext_vga) {
1758                 i810_writel(HVSYNC, mmio, 0);
1759                 i810_writel(PWR_CLKC, mmio, 3);
1760         }
1761
1762         pci_read_config_byte(par->dev, 0x50, &reg);
1763         reg &= FREQ_MASK;
1764         par->mem_freq = (reg) ? 133 : 100;
1765
1766 }
1767
1768 static int __devinit
1769 i810_allocate_pci_resource(struct i810fb_par *par,
1770                            const struct pci_device_id *entry)
1771 {
1772         int err;
1773
1774         if ((err = pci_enable_device(par->dev))) {
1775                 printk("i810fb_init: cannot enable device\n");
1776                 return err;
1777         }
1778         par->res_flags |= PCI_DEVICE_ENABLED;
1779
1780         if (pci_resource_len(par->dev, 0) > 512 * 1024) {
1781                 par->aperture.physical = pci_resource_start(par->dev, 0);
1782                 par->aperture.size = pci_resource_len(par->dev, 0);
1783                 par->mmio_start_phys = pci_resource_start(par->dev, 1);
1784         } else {
1785                 par->aperture.physical = pci_resource_start(par->dev, 1);
1786                 par->aperture.size = pci_resource_len(par->dev, 1);
1787                 par->mmio_start_phys = pci_resource_start(par->dev, 0);
1788         }
1789         if (!par->aperture.size) {
1790                 printk("i810fb_init: device is disabled\n");
1791                 return -ENOMEM;
1792         }
1793
1794         if (!request_mem_region(par->aperture.physical,
1795                                 par->aperture.size,
1796                                 i810_pci_list[entry->driver_data])) {
1797                 printk("i810fb_init: cannot request framebuffer region\n");
1798                 return -ENODEV;
1799         }
1800         par->res_flags |= FRAMEBUFFER_REQ;
1801
1802         par->aperture.virtual = ioremap_nocache(par->aperture.physical,
1803                                         par->aperture.size);
1804         if (!par->aperture.virtual) {
1805                 printk("i810fb_init: cannot remap framebuffer region\n");
1806                 return -ENODEV;
1807         }
1808
1809         if (!request_mem_region(par->mmio_start_phys,
1810                                 MMIO_SIZE,
1811                                 i810_pci_list[entry->driver_data])) {
1812                 printk("i810fb_init: cannot request mmio region\n");
1813                 return -ENODEV;
1814         }
1815         par->res_flags |= MMIO_REQ;
1816
1817         par->mmio_start_virtual = ioremap_nocache(par->mmio_start_phys,
1818                                                   MMIO_SIZE);
1819         if (!par->mmio_start_virtual) {
1820                 printk("i810fb_init: cannot remap mmio region\n");
1821                 return -ENODEV;
1822         }
1823
1824         return 0;
1825 }
1826
1827 static void __devinit i810fb_find_init_mode(struct fb_info *info)
1828 {
1829         struct fb_videomode mode;
1830         struct fb_var_screeninfo var;
1831         struct fb_monspecs *specs = NULL;
1832         int found = 0;
1833 #ifdef CONFIG_FB_I810_I2C
1834         int i;
1835         int err;
1836         struct i810fb_par *par = info->par;
1837 #endif
1838
1839         INIT_LIST_HEAD(&info->modelist);
1840         memset(&mode, 0, sizeof(struct fb_videomode));
1841         var = info->var;
1842 #ifdef CONFIG_FB_I810_I2C
1843         i810_create_i2c_busses(par);
1844
1845         for (i = 0; i < 3; i++) {
1846                 err = i810_probe_i2c_connector(info, &par->edid, i+1);
1847                 if (!err)
1848                         break;
1849         }
1850
1851         if (!err)
1852                 printk("i810fb_init_pci: DDC probe successful\n");
1853
1854         fb_edid_to_monspecs(par->edid, &info->monspecs);
1855
1856         if (info->monspecs.modedb == NULL)
1857                 printk("i810fb_init_pci: Unable to get Mode Database\n");
1858
1859         specs = &info->monspecs;
1860         fb_videomode_to_modelist(specs->modedb, specs->modedb_len,
1861                                  &info->modelist);
1862         if (specs->modedb != NULL) {
1863                 if (specs->misc & FB_MISC_1ST_DETAIL) {
1864                         for (i = 0; i < specs->modedb_len; i++) {
1865                                 if (specs->modedb[i].flag & FB_MODE_IS_FIRST) {
1866                                         mode = specs->modedb[i];
1867                                         found = 1;
1868                                         break;
1869                                 }
1870                         }
1871                 }
1872
1873                 if (!found) {
1874                         mode = specs->modedb[0];
1875                         found = 1;
1876                 }
1877
1878                 fb_videomode_to_var(&var, &mode);
1879         }
1880 #endif
1881         if (mode_option)
1882                 fb_find_mode(&var, info, mode_option, specs->modedb,
1883                              specs->modedb_len, (found) ? &mode : NULL,
1884                              info->var.bits_per_pixel);
1885
1886         info->var = var;
1887         fb_destroy_modedb(specs->modedb);
1888         specs->modedb = NULL;
1889 }
1890
1891 #ifndef MODULE
1892 static int __devinit i810fb_setup(char *options)
1893 {
1894         char *this_opt, *suffix = NULL;
1895
1896         if (!options || !*options)
1897                 return 0;
1898
1899         while ((this_opt = strsep(&options, ",")) != NULL) {
1900                 if (!strncmp(this_opt, "mtrr", 4))
1901                         mtrr = 1;
1902                 else if (!strncmp(this_opt, "accel", 5))
1903                         accel = 1;
1904                 else if (!strncmp(this_opt, "ext_vga", 7))
1905                         ext_vga = 1;
1906                 else if (!strncmp(this_opt, "sync", 4))
1907                         sync = 1;
1908                 else if (!strncmp(this_opt, "vram:", 5))
1909                         vram = (simple_strtoul(this_opt+5, NULL, 0));
1910                 else if (!strncmp(this_opt, "voffset:", 8))
1911                         voffset = (simple_strtoul(this_opt+8, NULL, 0));
1912                 else if (!strncmp(this_opt, "xres:", 5))
1913                         xres = simple_strtoul(this_opt+5, NULL, 0);
1914                 else if (!strncmp(this_opt, "yres:", 5))
1915                         yres = simple_strtoul(this_opt+5, NULL, 0);
1916                 else if (!strncmp(this_opt, "vyres:", 6))
1917                         vyres = simple_strtoul(this_opt+6, NULL, 0);
1918                 else if (!strncmp(this_opt, "bpp:", 4))
1919                         bpp = simple_strtoul(this_opt+4, NULL, 0);
1920                 else if (!strncmp(this_opt, "hsync1:", 7)) {
1921                         hsync1 = simple_strtoul(this_opt+7, &suffix, 0);
1922                         if (strncmp(suffix, "H", 1))
1923                                 hsync1 *= 1000;
1924                 } else if (!strncmp(this_opt, "hsync2:", 7)) {
1925                         hsync2 = simple_strtoul(this_opt+7, &suffix, 0);
1926                         if (strncmp(suffix, "H", 1))
1927                                 hsync2 *= 1000;
1928                 } else if (!strncmp(this_opt, "vsync1:", 7))
1929                         vsync1 = simple_strtoul(this_opt+7, NULL, 0);
1930                 else if (!strncmp(this_opt, "vsync2:", 7))
1931                         vsync2 = simple_strtoul(this_opt+7, NULL, 0);
1932                 else if (!strncmp(this_opt, "dcolor", 6))
1933                         dcolor = 1;
1934                 else
1935                         mode_option = this_opt;
1936         }
1937         return 0;
1938 }
1939 #endif
1940
1941 static int __devinit i810fb_init_pci (struct pci_dev *dev,
1942                                    const struct pci_device_id *entry)
1943 {
1944         struct fb_info    *info;
1945         struct i810fb_par *par = NULL;
1946         struct fb_videomode mode;
1947         int i, err = -1, vfreq, hfreq, pixclock;
1948
1949         i = 0;
1950
1951         info = framebuffer_alloc(sizeof(struct i810fb_par), &dev->dev);
1952         if (!info)
1953                 return -ENOMEM;
1954
1955         par = info->par;
1956         par->dev = dev;
1957
1958         if (!(info->pixmap.addr = kmalloc(8*1024, GFP_KERNEL))) {
1959                 i810fb_release_resource(info, par);
1960                 return -ENOMEM;
1961         }
1962         memset(info->pixmap.addr, 0, 8*1024);
1963         info->pixmap.size = 8*1024;
1964         info->pixmap.buf_align = 8;
1965         info->pixmap.access_align = 32;
1966         info->pixmap.flags = FB_PIXMAP_SYSTEM;
1967
1968         if ((err = i810_allocate_pci_resource(par, entry))) {
1969                 i810fb_release_resource(info, par);
1970                 return err;
1971         }
1972
1973         i810_init_defaults(par, info);
1974
1975         if ((err = i810_alloc_agp_mem(info))) {
1976                 i810fb_release_resource(info, par);
1977                 return err;
1978         }
1979
1980         i810_init_device(par);
1981
1982         info->screen_base = par->fb.virtual;
1983         info->fbops = &par->i810fb_ops;
1984         info->pseudo_palette = par->pseudo_palette;
1985         fb_alloc_cmap(&info->cmap, 256, 0);
1986         i810fb_find_init_mode(info);
1987
1988         if ((err = info->fbops->fb_check_var(&info->var, info))) {
1989                 i810fb_release_resource(info, par);
1990                 return err;
1991         }
1992
1993         fb_var_to_videomode(&mode, &info->var);
1994         fb_add_videomode(&mode, &info->modelist);
1995         encode_fix(&info->fix, info);
1996
1997         i810fb_init_ringbuffer(info);
1998         err = register_framebuffer(info);
1999
2000         if (err < 0) {
2001                 i810fb_release_resource(info, par);
2002                 printk("i810fb_init: cannot register framebuffer device\n");
2003                 return err;
2004         }
2005
2006         pci_set_drvdata(dev, info);
2007         pixclock = 1000000000/(info->var.pixclock);
2008         pixclock *= 1000;
2009         hfreq = pixclock/(info->var.xres + info->var.left_margin +
2010                           info->var.hsync_len + info->var.right_margin);
2011         vfreq = hfreq/(info->var.yres + info->var.upper_margin +
2012                        info->var.vsync_len + info->var.lower_margin);
2013
2014         printk("I810FB: fb%d         : %s v%d.%d.%d%s\n"
2015                "I810FB: Video RAM   : %dK\n"
2016                "I810FB: Monitor     : H: %d-%d KHz V: %d-%d Hz\n"
2017                "I810FB: Mode        : %dx%d-%dbpp@%dHz\n",
2018                info->node,
2019                i810_pci_list[entry->driver_data],
2020                VERSION_MAJOR, VERSION_MINOR, VERSION_TEENIE, BRANCH_VERSION,
2021                (int) par->fb.size>>10, info->monspecs.hfmin/1000,
2022                info->monspecs.hfmax/1000, info->monspecs.vfmin,
2023                info->monspecs.vfmax, info->var.xres,
2024                info->var.yres, info->var.bits_per_pixel, vfreq);
2025         return 0;
2026 }
2027
2028 /***************************************************************
2029  *                     De-initialization                        *
2030  ***************************************************************/
2031
2032 static void i810fb_release_resource(struct fb_info *info,
2033                                     struct i810fb_par *par)
2034 {
2035         struct gtt_data *gtt = &par->i810_gtt;
2036         unset_mtrr(par);
2037
2038         i810_delete_i2c_busses(par);
2039
2040         if (par->i810_gtt.i810_cursor_memory)
2041                 agp_free_memory(gtt->i810_cursor_memory);
2042         if (par->i810_gtt.i810_fb_memory)
2043                 agp_free_memory(gtt->i810_fb_memory);
2044
2045         if (par->mmio_start_virtual)
2046                 iounmap(par->mmio_start_virtual);
2047         if (par->aperture.virtual)
2048                 iounmap(par->aperture.virtual);
2049         if (par->edid)
2050                 kfree(par->edid);
2051         if (par->res_flags & FRAMEBUFFER_REQ)
2052                 release_mem_region(par->aperture.physical,
2053                                    par->aperture.size);
2054         if (par->res_flags & MMIO_REQ)
2055                 release_mem_region(par->mmio_start_phys, MMIO_SIZE);
2056
2057         if (par->res_flags & PCI_DEVICE_ENABLED)
2058                 pci_disable_device(par->dev);
2059
2060         framebuffer_release(info);
2061
2062 }
2063
2064 static void __exit i810fb_remove_pci(struct pci_dev *dev)
2065 {
2066         struct fb_info *info = pci_get_drvdata(dev);
2067         struct i810fb_par *par = (struct i810fb_par *) info->par;
2068
2069         unregister_framebuffer(info);
2070         i810fb_release_resource(info, par);
2071         pci_set_drvdata(dev, NULL);
2072         printk("cleanup_module:  unloaded i810 framebuffer device\n");
2073 }
2074
2075 #ifndef MODULE
2076 static int __devinit i810fb_init(void)
2077 {
2078         char *option = NULL;
2079
2080         if (fb_get_options("i810fb", &option))
2081                 return -ENODEV;
2082         i810fb_setup(option);
2083
2084         return pci_register_driver(&i810fb_driver);
2085 }
2086 #endif
2087
2088 /*********************************************************************
2089  *                          Modularization                           *
2090  *********************************************************************/
2091
2092 #ifdef MODULE
2093
2094 static int __devinit i810fb_init(void)
2095 {
2096         hsync1 *= 1000;
2097         hsync2 *= 1000;
2098
2099         return pci_register_driver(&i810fb_driver);
2100 }
2101
2102 module_param(vram, int, 0);
2103 MODULE_PARM_DESC(vram, "System RAM to allocate to framebuffer in MiB"
2104                  " (default=4)");
2105 module_param(voffset, int, 0);
2106 MODULE_PARM_DESC(voffset, "at what offset to place start of framebuffer "
2107                  "memory (0 to maximum aperture size), in MiB (default = 48)");
2108 module_param(bpp, int, 0);
2109 MODULE_PARM_DESC(bpp, "Color depth for display in bits per pixel"
2110                  " (default = 8)");
2111 module_param(xres, int, 0);
2112 MODULE_PARM_DESC(xres, "Horizontal resolution in pixels (default = 640)");
2113 module_param(yres, int, 0);
2114 MODULE_PARM_DESC(yres, "Vertical resolution in scanlines (default = 480)");
2115 module_param(vyres,int, 0);
2116 MODULE_PARM_DESC(vyres, "Virtual vertical resolution in scanlines"
2117                  " (default = 480)");
2118 module_param(hsync1, int, 0);
2119 MODULE_PARM_DESC(hsync1, "Minimum horizontal frequency of monitor in KHz"
2120                  " (default = 29)");
2121 module_param(hsync2, int, 0);
2122 MODULE_PARM_DESC(hsync2, "Maximum horizontal frequency of monitor in KHz"
2123                  " (default = 30)");
2124 module_param(vsync1, int, 0);
2125 MODULE_PARM_DESC(vsync1, "Minimum vertical frequency of monitor in Hz"
2126                  " (default = 50)");
2127 module_param(vsync2, int, 0);
2128 MODULE_PARM_DESC(vsync2, "Maximum vertical frequency of monitor in Hz"
2129                  " (default = 60)");
2130 module_param(accel, bool, 0);
2131 MODULE_PARM_DESC(accel, "Use Acceleration (BLIT) engine (default = 0)");
2132 module_param(mtrr, bool, 0);
2133 MODULE_PARM_DESC(mtrr, "Use MTRR (default = 0)");
2134 module_param(ext_vga, bool, 0);
2135 MODULE_PARM_DESC(ext_vga, "Enable external VGA connector (default = 0)");
2136 module_param(sync, bool, 0);
2137 MODULE_PARM_DESC(sync, "wait for accel engine to finish drawing"
2138                  " (default = 0)");
2139 module_param(dcolor, bool, 0);
2140 MODULE_PARM_DESC(dcolor, "use DirectColor visuals"
2141                  " (default = 0 = TrueColor)");
2142 module_param(mode_option, charp, 0);
2143 MODULE_PARM_DESC(mode_option, "Specify initial video mode");
2144
2145 MODULE_AUTHOR("Tony A. Daplas");
2146 MODULE_DESCRIPTION("Framebuffer device for the Intel 810/815 and"
2147                    " compatible cards");
2148 MODULE_LICENSE("GPL");
2149
2150 static void __exit i810fb_exit(void)
2151 {
2152         pci_unregister_driver(&i810fb_driver);
2153 }
2154 module_exit(i810fb_exit);
2155
2156 #endif /* MODULE */
2157
2158 module_init(i810fb_init);