2 * Epson Blizzard LCD controller driver
4 * Copyright (C) 2004-2005 Nokia Corporation
5 * Authors: Juha Yrjola <juha.yrjola@nokia.com>
6 * Imre Deak <imre.deak@nokia.com>
7 * YUV support: Jussi Laako <jussi.laako@nokia.com>
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the
11 * Free Software Foundation; either version 2 of the License, or (at your
12 * option) any later version.
14 * This program is distributed in the hope that it will be useful, but
15 * WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
17 * General Public License for more details.
19 * You should have received a copy of the GNU General Public License along
20 * with this program; if not, write to the Free Software Foundation, Inc.,
21 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
23 #include <linux/module.h>
26 #include <linux/delay.h>
27 #include <linux/clk.h>
29 #include <asm/arch/dma.h>
30 #include <asm/arch/omapfb.h>
31 #include <asm/arch/blizzard.h>
35 #define MODULE_NAME "blizzard"
37 #define BLIZZARD_REV_CODE 0x00
38 #define BLIZZARD_CONFIG 0x02
39 #define BLIZZARD_PLL_DIV 0x04
40 #define BLIZZARD_PLL_LOCK_RANGE 0x06
41 #define BLIZZARD_PLL_CLOCK_SYNTH_0 0x08
42 #define BLIZZARD_PLL_CLOCK_SYNTH_1 0x0a
43 #define BLIZZARD_PLL_MODE 0x0c
44 #define BLIZZARD_CLK_SRC 0x0e
45 #define BLIZZARD_MEM_BANK0_ACTIVATE 0x10
46 #define BLIZZARD_MEM_BANK0_STATUS 0x14
47 #define BLIZZARD_PANEL_CONFIGURATION 0x28
48 #define BLIZZARD_HDISP 0x2a
49 #define BLIZZARD_HNDP 0x2c
50 #define BLIZZARD_VDISP0 0x2e
51 #define BLIZZARD_VDISP1 0x30
52 #define BLIZZARD_VNDP 0x32
53 #define BLIZZARD_HSW 0x34
54 #define BLIZZARD_VSW 0x38
55 #define BLIZZARD_DISPLAY_MODE 0x68
56 #define BLIZZARD_INPUT_WIN_X_START_0 0x6c
57 #define BLIZZARD_DATA_SOURCE_SELECT 0x8e
58 #define BLIZZARD_DISP_MEM_DATA_PORT 0x90
59 #define BLIZZARD_DISP_MEM_READ_ADDR0 0x92
60 #define BLIZZARD_POWER_SAVE 0xE6
61 #define BLIZZARD_NDISP_CTRL_STATUS 0xE8
63 /* Data source select */
65 #define BLIZZARD_SRC_WRITE_LCD_BACKGROUND 0x00
66 #define BLIZZARD_SRC_WRITE_LCD_DESTRUCTIVE 0x01
67 #define BLIZZARD_SRC_WRITE_OVERLAY_ENABLE 0x04
68 #define BLIZZARD_SRC_DISABLE_OVERLAY 0x05
70 #define BLIZZARD_SRC_WRITE_LCD 0x00
71 #define BLIZZARD_SRC_BLT_LCD 0x06
73 #define BLIZZARD_COLOR_RGB565 0x01
74 #define BLIZZARD_COLOR_YUV420 0x09
76 #define BLIZZARD_VERSION_S1D13745 0x01 /* Hailstorm */
77 #define BLIZZARD_VERSION_S1D13744 0x02 /* Blizzard */
79 #define BLIZZARD_AUTO_UPDATE_TIME (HZ / 20)
81 /* Reserve 4 request slots for requests in irq context */
82 #define REQ_POOL_SIZE 24
83 #define IRQ_REQ_POOL_SIZE 4
85 #define REQ_FROM_IRQ_POOL 0x01
87 #define REQ_COMPLETE 0
90 struct blizzard_reg_list {
95 /* These need to be saved / restored separately from the rest. */
96 static struct blizzard_reg_list blizzard_pll_regs[] = {
98 .start = 0x04, /* Don't save PLL ctrl (0x0C) */
102 .start = 0x0e, /* Clock configuration */
107 static struct blizzard_reg_list blizzard_gen_regs[] = {
109 .start = 0x18, /* SDRAM control */
113 .start = 0x28, /* LCD Panel configuration */
114 .end = 0x5a, /* HSSI interface, TV configuration */
118 static u8 blizzard_reg_cache[0x5a / 2];
120 struct update_param {
122 int x, y, width, height;
124 int out_width, out_height;
130 struct blizzard_request {
131 struct list_head entry;
134 int (*handler)(struct blizzard_request *req);
135 void (*complete)(void *data);
139 struct update_param update;
140 struct completion *sync;
145 unsigned long offset;
148 int out_width, out_height;
154 struct blizzard_struct {
155 enum omapfb_update_mode update_mode;
156 enum omapfb_update_mode update_mode_before_suspend;
158 struct timer_list auto_update_timer;
159 int stop_auto_update;
160 struct omapfb_update_window auto_update_window;
162 int vid_nonstd_color;
168 unsigned te_connected:1;
169 unsigned vsync_only:1;
171 struct plane_info plane[OMAPFB_PLANE_NUM];
173 struct blizzard_request req_pool[REQ_POOL_SIZE];
174 struct list_head pending_req_list;
175 struct list_head free_req_list;
176 struct semaphore req_sema;
179 unsigned long sys_ck_rate;
180 struct extif_timings reg_timings, lut_timings;
182 u32 max_transmit_size;
183 u32 extif_clk_period;
185 unsigned long pix_tx_time;
186 unsigned long line_upd_time;
188 struct omapfb_device *fbdev;
189 struct lcd_ctrl_extif *extif;
190 struct lcd_ctrl *int_ctrl;
192 void (*power_up)(struct device *dev);
193 void (*power_down)(struct device *dev);
198 struct lcd_ctrl blizzard_ctrl;
200 static u8 blizzard_read_reg(u8 reg)
204 blizzard.extif->set_bits_per_cycle(8);
205 blizzard.extif->write_command(®, 1);
206 blizzard.extif->read_data(&data, 1);
211 static void blizzard_write_reg(u8 reg, u8 val)
213 blizzard.extif->set_bits_per_cycle(8);
214 blizzard.extif->write_command(®, 1);
215 blizzard.extif->write_data(&val, 1);
218 static void blizzard_restart_sdram(void)
222 blizzard_write_reg(BLIZZARD_MEM_BANK0_ACTIVATE, 0);
224 blizzard_write_reg(BLIZZARD_MEM_BANK0_ACTIVATE, 1);
225 tmo = jiffies + msecs_to_jiffies(200);
226 while (!(blizzard_read_reg(BLIZZARD_MEM_BANK0_STATUS) & 0x01)) {
227 if (time_after(jiffies, tmo)) {
228 dev_err(blizzard.fbdev->dev,
229 "s1d1374x: SDRAM not ready\n");
236 static void blizzard_stop_sdram(void)
238 blizzard_write_reg(BLIZZARD_MEM_BANK0_ACTIVATE, 0);
241 /* Wait until the last window was completely written into the controllers
242 * SDRAM and we can start transferring the next window.
244 static void blizzard_wait_line_buffer(void)
246 unsigned long tmo = jiffies + msecs_to_jiffies(30);
248 while (blizzard_read_reg(BLIZZARD_NDISP_CTRL_STATUS) & (1 << 7)) {
249 if (time_after(jiffies, tmo)) {
250 if (printk_ratelimit())
251 dev_err(blizzard.fbdev->dev,
252 "s1d1374x: line buffer not ready\n");
258 /* Wait until the YYC color space converter is idle. */
259 static void blizzard_wait_yyc(void)
261 unsigned long tmo = jiffies + msecs_to_jiffies(30);
263 while (blizzard_read_reg(BLIZZARD_NDISP_CTRL_STATUS) & (1 << 4)) {
264 if (time_after(jiffies, tmo)) {
265 if (printk_ratelimit())
266 dev_err(blizzard.fbdev->dev,
267 "s1d1374x: YYC not ready\n");
273 static void disable_overlay(void)
275 blizzard_write_reg(BLIZZARD_DATA_SOURCE_SELECT,
276 BLIZZARD_SRC_DISABLE_OVERLAY);
279 static void set_window_regs(int x_start, int y_start, int x_end, int y_end,
280 int x_out_start, int y_out_start,
281 int x_out_end, int y_out_end, int color_mode,
282 int zoom_off, int flags)
290 tmp[1] = x_start >> 8;
292 tmp[3] = y_start >> 8;
300 tmp[8] = x_out_start;
301 tmp[9] = x_out_start >> 8;
302 tmp[10] = y_out_start;
303 tmp[11] = y_out_start >> 8;
305 tmp[13] = x_out_end >> 8;
307 tmp[15] = y_out_end >> 8;
309 tmp[16] = color_mode;
310 if (zoom_off && blizzard.version == BLIZZARD_VERSION_S1D13745)
311 tmp[17] = BLIZZARD_SRC_WRITE_LCD_BACKGROUND;
312 else if (flags & OMAPFB_FORMAT_FLAG_ENABLE_OVERLAY)
313 tmp[17] = BLIZZARD_SRC_WRITE_OVERLAY_ENABLE;
315 tmp[17] = blizzard.version == BLIZZARD_VERSION_S1D13744 ?
316 BLIZZARD_SRC_WRITE_LCD :
317 BLIZZARD_SRC_WRITE_LCD_DESTRUCTIVE;
319 blizzard.extif->set_bits_per_cycle(8);
320 cmd = BLIZZARD_INPUT_WIN_X_START_0;
321 blizzard.extif->write_command(&cmd, 1);
322 blizzard.extif->write_data(tmp, 18);
325 static void enable_tearsync(int y, int width, int height, int screen_height,
326 int out_height, int force_vsync)
330 b = blizzard_read_reg(BLIZZARD_NDISP_CTRL_STATUS);
332 blizzard_write_reg(BLIZZARD_NDISP_CTRL_STATUS, b);
334 if (likely(blizzard.vsync_only || force_vsync)) {
335 blizzard.extif->enable_tearsync(1, 0);
339 if (width * blizzard.pix_tx_time < blizzard.line_upd_time) {
340 blizzard.extif->enable_tearsync(1, 0);
344 if ((width * blizzard.pix_tx_time / 1000) * height <
345 (y + out_height) * (blizzard.line_upd_time / 1000)) {
346 blizzard.extif->enable_tearsync(1, 0);
350 blizzard.extif->enable_tearsync(1, y + 1);
353 static void disable_tearsync(void)
357 blizzard.extif->enable_tearsync(0, 0);
358 b = blizzard_read_reg(BLIZZARD_NDISP_CTRL_STATUS);
360 blizzard_write_reg(BLIZZARD_NDISP_CTRL_STATUS, b);
361 b = blizzard_read_reg(BLIZZARD_NDISP_CTRL_STATUS);
364 static inline void set_extif_timings(const struct extif_timings *t);
366 static inline struct blizzard_request *alloc_req(void)
369 struct blizzard_request *req;
373 down(&blizzard.req_sema);
375 req_flags = REQ_FROM_IRQ_POOL;
377 spin_lock_irqsave(&blizzard.req_lock, flags);
378 BUG_ON(list_empty(&blizzard.free_req_list));
379 req = list_entry(blizzard.free_req_list.next,
380 struct blizzard_request, entry);
381 list_del(&req->entry);
382 spin_unlock_irqrestore(&blizzard.req_lock, flags);
384 INIT_LIST_HEAD(&req->entry);
385 req->flags = req_flags;
390 static inline void free_req(struct blizzard_request *req)
394 spin_lock_irqsave(&blizzard.req_lock, flags);
396 list_del(&req->entry);
397 list_add(&req->entry, &blizzard.free_req_list);
398 if (!(req->flags & REQ_FROM_IRQ_POOL))
399 up(&blizzard.req_sema);
401 spin_unlock_irqrestore(&blizzard.req_lock, flags);
404 static void process_pending_requests(void)
408 spin_lock_irqsave(&blizzard.req_lock, flags);
410 while (!list_empty(&blizzard.pending_req_list)) {
411 struct blizzard_request *req;
412 void (*complete)(void *);
415 req = list_entry(blizzard.pending_req_list.next,
416 struct blizzard_request, entry);
417 spin_unlock_irqrestore(&blizzard.req_lock, flags);
419 if (req->handler(req) == REQ_PENDING)
422 complete = req->complete;
423 complete_data = req->complete_data;
427 complete(complete_data);
429 spin_lock_irqsave(&blizzard.req_lock, flags);
432 spin_unlock_irqrestore(&blizzard.req_lock, flags);
435 static void submit_req_list(struct list_head *head)
440 spin_lock_irqsave(&blizzard.req_lock, flags);
441 if (likely(!list_empty(&blizzard.pending_req_list)))
443 list_splice_init(head, blizzard.pending_req_list.prev);
444 spin_unlock_irqrestore(&blizzard.req_lock, flags);
447 process_pending_requests();
450 static void request_complete(void *data)
452 struct blizzard_request *req = (struct blizzard_request *)data;
453 void (*complete)(void *);
456 complete = req->complete;
457 complete_data = req->complete_data;
462 complete(complete_data);
464 process_pending_requests();
468 static int do_full_screen_update(struct blizzard_request *req)
473 for (i = 0; i < 3; i++) {
474 struct plane_info *p = &blizzard.plane[i];
475 if (!(blizzard.enabled_planes & (1 << i))) {
476 blizzard.int_ctrl->enable_plane(i, 0);
479 dev_dbg(blizzard.fbdev->dev, "pw %d ph %d\n",
480 p->width, p->height);
481 blizzard.int_ctrl->setup_plane(i,
482 OMAPFB_CHANNEL_OUT_LCD, p->offset,
483 p->scr_width, p->pos_x, p->pos_y,
486 blizzard.int_ctrl->enable_plane(i, 1);
489 dev_dbg(blizzard.fbdev->dev, "sw %d sh %d\n",
490 blizzard.screen_width, blizzard.screen_height);
491 blizzard_wait_line_buffer();
492 flags = req->par.update.flags;
493 if (flags & OMAPFB_FORMAT_FLAG_TEARSYNC)
494 enable_tearsync(0, blizzard.screen_width,
495 blizzard.screen_height,
496 blizzard.screen_height,
497 blizzard.screen_height,
498 flags & OMAPFB_FORMAT_FLAG_FORCE_VSYNC);
502 set_window_regs(0, 0, blizzard.screen_width, blizzard.screen_height,
503 0, 0, blizzard.screen_width, blizzard.screen_height,
504 BLIZZARD_COLOR_RGB565, blizzard.zoom_on, flags);
505 blizzard.zoom_on = 0;
507 blizzard.extif->set_bits_per_cycle(16);
508 /* set_window_regs has left the register index at the right
509 * place, so no need to set it here.
511 blizzard.extif->transfer_area(blizzard.screen_width,
512 blizzard.screen_height,
513 request_complete, req);
517 /* Setup all planes with an overlapping area with the update window. */
518 static int do_partial_update(struct blizzard_request *req, int plane,
519 int x, int y, int w, int h,
520 int x_out, int y_out, int w_out, int h_out,
521 int wnd_color_mode, int bpp)
524 int gx1, gy1, gx2, gy2;
525 int gx1_out, gy1_out, gx2_out, gy2_out;
530 /* Global coordinates, relative to pixel 0,0 of the LCD */
531 gx1 = x + blizzard.plane[plane].pos_x;
532 gy1 = y + blizzard.plane[plane].pos_y;
536 flags = req->par.update.flags;
537 if (flags & OMAPFB_FORMAT_FLAG_DOUBLE) {
540 gx2_out = gx1 + w * 2;
541 gy2_out = gy1 + h * 2;
543 gx1_out = x_out + blizzard.plane[plane].pos_x;
544 gy1_out = y_out + blizzard.plane[plane].pos_y;
545 gx2_out = gx1_out + w_out;
546 gy2_out = gy1_out + h_out;
548 zoom_off = blizzard.zoom_on && gx1 == 0 && gy1 == 0 &&
549 w == blizzard.screen_width && h == blizzard.screen_height;
550 blizzard.zoom_on = (!zoom_off && blizzard.zoom_on) ||
551 (w < w_out || h < h_out);
553 for (i = 0; i < OMAPFB_PLANE_NUM; i++) {
554 struct plane_info *p = &blizzard.plane[i];
559 unsigned long offset;
561 if (!(blizzard.enabled_planes & (1 << i)) ||
562 (wnd_color_mode && i != plane)) {
563 blizzard.int_ctrl->enable_plane(i, 0);
566 /* Plane coordinates */
568 /* Plane in which we are doing the update.
569 * Local coordinates are the one in the update
579 /* Check if this plane has an overlapping part */
580 px1 = gx1 - p->pos_x;
581 py1 = gy1 - p->pos_y;
582 px2 = gx2 - p->pos_x;
583 py2 = gy2 - p->pos_y;
584 if (px1 >= p->width || py1 >= p->height ||
585 px2 <= 0 || py2 <= 0) {
586 blizzard.int_ctrl->enable_plane(i, 0);
589 /* Calculate the coordinates for the overlapping
590 * part in the plane's local coordinates.
609 offset = p->offset + (p->scr_width * py1 + px1) * p->bpp / 8;
611 /* Window embedded in the plane with a differing
612 * color mode / bpp. Calculate the number of DMA
613 * transfer elements in terms of the plane's bpp.
615 pw = (pw + 1) * bpp / p->bpp;
617 dev_dbg(blizzard.fbdev->dev,
618 "plane %d offset %#08lx pposx %d pposy %d "
619 "px1 %d py1 %d pw %d ph %d\n",
620 i, offset, pposx, pposy, px1, py1, pw, ph);
622 blizzard.int_ctrl->setup_plane(i,
623 OMAPFB_CHANNEL_OUT_LCD, offset,
625 pposx, pposy, pw, ph,
628 blizzard.int_ctrl->enable_plane(i, 1);
631 switch (wnd_color_mode) {
632 case OMAPFB_COLOR_YUV420:
633 color_mode = BLIZZARD_COLOR_YUV420;
634 /* Currently only the 16 bits/pixel cycle format is
635 * supported on the external interface. Adjust the number
636 * of transfer elements per line for 12bpp format.
641 color_mode = BLIZZARD_COLOR_RGB565;
645 blizzard_wait_line_buffer();
646 if (blizzard.last_color_mode == BLIZZARD_COLOR_YUV420)
648 blizzard.last_color_mode = color_mode;
649 if (flags & OMAPFB_FORMAT_FLAG_TEARSYNC)
650 enable_tearsync(gy1, w, h,
651 blizzard.screen_height,
653 flags & OMAPFB_FORMAT_FLAG_FORCE_VSYNC);
657 set_window_regs(gx1, gy1, gx2, gy2, gx1_out, gy1_out, gx2_out, gy2_out,
658 color_mode, zoom_off, flags);
660 blizzard.extif->set_bits_per_cycle(16);
661 /* set_window_regs has left the register index at the right
662 * place, so no need to set it here.
664 blizzard.extif->transfer_area(w, h, request_complete, req);
669 static int send_frame_handler(struct blizzard_request *req)
671 struct update_param *par = &req->par.update;
672 int plane = par->plane;
675 dev_dbg(blizzard.fbdev->dev,
676 "send_frame: x %d y %d w %d h %d "
677 "x_out %d y_out %d w_out %d h_out %d "
678 "color_mode %04x flags %04x planes %01x\n",
679 par->x, par->y, par->width, par->height,
680 par->out_x, par->out_y, par->out_width, par->out_height,
681 par->color_mode, par->flags, blizzard.enabled_planes);
683 if (par->flags & OMAPFB_FORMAT_FLAG_DISABLE_OVERLAY)
686 if ((blizzard.enabled_planes & blizzard.vid_nonstd_color) ||
687 (blizzard.enabled_planes & blizzard.vid_scaled))
688 return do_full_screen_update(req);
690 return do_partial_update(req, plane, par->x, par->y,
691 par->width, par->height,
692 par->out_x, par->out_y,
693 par->out_width, par->out_height,
694 par->color_mode, par->bpp);
697 static void send_frame_complete(void *data)
701 #define ADD_PREQ(_x, _y, _w, _h, _x_out, _y_out, _w_out, _h_out) do { \
703 req->handler = send_frame_handler; \
704 req->complete = send_frame_complete; \
705 req->par.update.plane = plane_idx; \
706 req->par.update.x = _x; \
707 req->par.update.y = _y; \
708 req->par.update.width = _w; \
709 req->par.update.height = _h; \
710 req->par.update.out_x = _x_out; \
711 req->par.update.out_y = _y_out; \
712 req->par.update.out_width = _w_out; \
713 req->par.update.out_height = _h_out; \
714 req->par.update.bpp = bpp; \
715 req->par.update.color_mode = color_mode;\
716 req->par.update.flags = flags; \
717 list_add_tail(&req->entry, req_head); \
720 static void create_req_list(int plane_idx,
721 struct omapfb_update_window *win,
722 struct list_head *req_head)
724 struct blizzard_request *req;
727 int width = win->width;
728 int height = win->height;
729 int x_out = win->out_x;
730 int y_out = win->out_y;
731 int width_out = win->out_width;
732 int height_out = win->out_height;
736 unsigned int ystart = y;
737 unsigned int yspan = height;
738 unsigned int ystart_out = y_out;
739 unsigned int yspan_out = height_out;
741 flags = win->format & ~OMAPFB_FORMAT_MASK;
742 color_mode = win->format & OMAPFB_FORMAT_MASK;
743 switch (color_mode) {
744 case OMAPFB_COLOR_YUV420:
745 /* Embedded window with different color mode */
747 /* X, Y, height must be aligned at 2, width at 4 pixels */
750 height = yspan = height & ~1;
754 /* Same as the plane color mode */
755 bpp = blizzard.plane[plane_idx].bpp;
758 if (width * height * bpp / 8 > blizzard.max_transmit_size) {
759 yspan = blizzard.max_transmit_size / (width * bpp / 8);
760 yspan_out = yspan * height_out / height;
761 ADD_PREQ(x, ystart, width, yspan, x_out, ystart_out,
762 width_out, yspan_out);
764 ystart_out += yspan_out;
765 yspan = height - yspan;
766 yspan_out = height_out - yspan_out;
767 flags &= ~OMAPFB_FORMAT_FLAG_TEARSYNC;
770 ADD_PREQ(x, ystart, width, yspan, x_out, ystart_out,
771 width_out, yspan_out);
774 static void auto_update_complete(void *data)
776 if (!blizzard.stop_auto_update)
777 mod_timer(&blizzard.auto_update_timer,
778 jiffies + BLIZZARD_AUTO_UPDATE_TIME);
781 static void blizzard_update_window_auto(unsigned long arg)
784 struct blizzard_request *last;
785 struct omapfb_plane_struct *plane;
787 plane = blizzard.fbdev->fb_info[0]->par;
788 create_req_list(plane->idx,
789 &blizzard.auto_update_window, &req_list);
790 last = list_entry(req_list.prev, struct blizzard_request, entry);
792 last->complete = auto_update_complete;
793 last->complete_data = NULL;
795 submit_req_list(&req_list);
798 int blizzard_update_window_async(struct fb_info *fbi,
799 struct omapfb_update_window *win,
800 void (*complete_callback)(void *arg),
801 void *complete_callback_data)
804 struct blizzard_request *last;
805 struct omapfb_plane_struct *plane = fbi->par;
807 if (unlikely(blizzard.update_mode != OMAPFB_MANUAL_UPDATE))
809 if (unlikely(!blizzard.te_connected &&
810 (win->format & OMAPFB_FORMAT_FLAG_TEARSYNC)))
813 create_req_list(plane->idx, win, &req_list);
814 last = list_entry(req_list.prev, struct blizzard_request, entry);
816 last->complete = complete_callback;
817 last->complete_data = (void *)complete_callback_data;
819 submit_req_list(&req_list);
823 EXPORT_SYMBOL(blizzard_update_window_async);
825 static int update_full_screen(void)
827 return blizzard_update_window_async(blizzard.fbdev->fb_info[0],
828 &blizzard.auto_update_window, NULL, NULL);
832 static int blizzard_setup_plane(int plane, int channel_out,
833 unsigned long offset, int screen_width,
834 int pos_x, int pos_y, int width, int height,
837 struct plane_info *p;
840 dev_dbg(blizzard.fbdev->dev,
841 "plane %d ch_out %d offset %#08lx scr_width %d "
842 "pos_x %d pos_y %d width %d height %d color_mode %d\n",
843 plane, channel_out, offset, screen_width,
844 pos_x, pos_y, width, height, color_mode);
846 if ((unsigned)plane > OMAPFB_PLANE_NUM)
848 p = &blizzard.plane[plane];
850 switch (color_mode) {
851 case OMAPFB_COLOR_YUV422:
852 case OMAPFB_COLOR_YUY422:
854 blizzard.vid_nonstd_color &= ~(1 << plane);
856 case OMAPFB_COLOR_YUV420:
858 blizzard.vid_nonstd_color |= 1 << plane;
860 case OMAPFB_COLOR_RGB565:
862 blizzard.vid_nonstd_color &= ~(1 << plane);
873 p->scr_width = screen_width;
875 p->out_width = width;
877 p->out_height = height;
879 p->color_mode = color_mode;
884 static int blizzard_set_scale(int plane, int orig_w, int orig_h,
885 int out_w, int out_h)
887 struct plane_info *p = &blizzard.plane[plane];
890 dev_dbg(blizzard.fbdev->dev,
891 "plane %d orig_w %d orig_h %d out_w %d out_h %d\n",
892 plane, orig_w, orig_h, out_w, out_h);
893 if ((unsigned)plane > OMAPFB_PLANE_NUM)
896 r = blizzard.int_ctrl->set_scale(plane, orig_w, orig_h, out_w, out_h);
902 p->out_width = out_w;
903 p->out_height = out_h;
904 if (orig_w == out_w && orig_h == out_h)
905 blizzard.vid_scaled &= ~(1 << plane);
907 blizzard.vid_scaled |= 1 << plane;
912 static int blizzard_set_rotate(int angle)
916 l = blizzard_read_reg(BLIZZARD_PANEL_CONFIGURATION);
936 blizzard_write_reg(BLIZZARD_PANEL_CONFIGURATION, l);
941 static int blizzard_enable_plane(int plane, int enable)
944 blizzard.enabled_planes |= 1 << plane;
946 blizzard.enabled_planes &= ~(1 << plane);
951 static int sync_handler(struct blizzard_request *req)
953 complete(req->par.sync);
957 static void blizzard_sync(void)
960 struct blizzard_request *req;
961 struct completion comp;
965 req->handler = sync_handler;
966 req->complete = NULL;
967 init_completion(&comp);
968 req->par.sync = ∁
970 list_add(&req->entry, &req_list);
971 submit_req_list(&req_list);
973 wait_for_completion(&comp);
977 static void blizzard_bind_client(struct omapfb_notifier_block *nb)
979 if (blizzard.update_mode == OMAPFB_MANUAL_UPDATE) {
980 omapfb_notify_clients(blizzard.fbdev, OMAPFB_EVENT_READY);
984 static int blizzard_set_update_mode(enum omapfb_update_mode mode)
986 if (unlikely(mode != OMAPFB_MANUAL_UPDATE &&
987 mode != OMAPFB_AUTO_UPDATE &&
988 mode != OMAPFB_UPDATE_DISABLED))
991 if (mode == blizzard.update_mode)
994 dev_info(blizzard.fbdev->dev, "s1d1374x: setting update mode to %s\n",
995 mode == OMAPFB_UPDATE_DISABLED ? "disabled" :
996 (mode == OMAPFB_AUTO_UPDATE ? "auto" : "manual"));
998 switch (blizzard.update_mode) {
999 case OMAPFB_MANUAL_UPDATE:
1000 omapfb_notify_clients(blizzard.fbdev, OMAPFB_EVENT_DISABLED);
1002 case OMAPFB_AUTO_UPDATE:
1003 blizzard.stop_auto_update = 1;
1004 del_timer_sync(&blizzard.auto_update_timer);
1006 case OMAPFB_UPDATE_DISABLED:
1010 blizzard.update_mode = mode;
1012 blizzard.stop_auto_update = 0;
1015 case OMAPFB_MANUAL_UPDATE:
1016 omapfb_notify_clients(blizzard.fbdev, OMAPFB_EVENT_READY);
1018 case OMAPFB_AUTO_UPDATE:
1019 blizzard_update_window_auto(0);
1021 case OMAPFB_UPDATE_DISABLED:
1028 static enum omapfb_update_mode blizzard_get_update_mode(void)
1030 return blizzard.update_mode;
1033 static inline void set_extif_timings(const struct extif_timings *t)
1035 blizzard.extif->set_timings(t);
1038 static inline unsigned long round_to_extif_ticks(unsigned long ps, int div)
1040 int bus_tick = blizzard.extif_clk_period * div;
1041 return (ps + bus_tick - 1) / bus_tick * bus_tick;
1044 static int calc_reg_timing(unsigned long sysclk, int div)
1046 struct extif_timings *t;
1047 unsigned long systim;
1049 /* CSOnTime 0, WEOnTime 2 ns, REOnTime 2 ns,
1050 * AccessTime 2 ns + 12.2 ns (regs),
1051 * WEOffTime = WEOnTime + 1 ns,
1052 * REOffTime = REOnTime + 12 ns (regs),
1053 * CSOffTime = REOffTime + 1 ns
1054 * ReadCycle = 2ns + 2*SYSCLK (regs),
1055 * WriteCycle = 2*SYSCLK + 2 ns,
1056 * CSPulseWidth = 10 ns */
1058 systim = 1000000000 / (sysclk / 1000);
1059 dev_dbg(blizzard.fbdev->dev,
1060 "Blizzard systim %lu ps extif_clk_period %u div %d\n",
1061 systim, blizzard.extif_clk_period, div);
1063 t = &blizzard.reg_timings;
1064 memset(t, 0, sizeof(*t));
1069 t->we_on_time = round_to_extif_ticks(t->cs_on_time + 2000, div);
1070 t->re_on_time = round_to_extif_ticks(t->cs_on_time + 2000, div);
1071 t->access_time = round_to_extif_ticks(t->re_on_time + 12200, div);
1072 t->we_off_time = round_to_extif_ticks(t->we_on_time + 1000, div);
1073 t->re_off_time = round_to_extif_ticks(t->re_on_time + 13000, div);
1074 t->cs_off_time = round_to_extif_ticks(t->re_off_time + 1000, div);
1075 t->we_cycle_time = round_to_extif_ticks(2 * systim + 2000, div);
1076 if (t->we_cycle_time < t->we_off_time)
1077 t->we_cycle_time = t->we_off_time;
1078 t->re_cycle_time = round_to_extif_ticks(2 * systim + 2000, div);
1079 if (t->re_cycle_time < t->re_off_time)
1080 t->re_cycle_time = t->re_off_time;
1081 t->cs_pulse_width = 0;
1083 dev_dbg(blizzard.fbdev->dev, "[reg]cson %d csoff %d reon %d reoff %d\n",
1084 t->cs_on_time, t->cs_off_time, t->re_on_time, t->re_off_time);
1085 dev_dbg(blizzard.fbdev->dev, "[reg]weon %d weoff %d recyc %d wecyc %d\n",
1086 t->we_on_time, t->we_off_time, t->re_cycle_time,
1088 dev_dbg(blizzard.fbdev->dev, "[reg]rdaccess %d cspulse %d\n",
1089 t->access_time, t->cs_pulse_width);
1091 return blizzard.extif->convert_timings(t);
1094 static int calc_lut_timing(unsigned long sysclk, int div)
1096 struct extif_timings *t;
1097 unsigned long systim;
1099 /* CSOnTime 0, WEOnTime 2 ns, REOnTime 2 ns,
1100 * AccessTime 2 ns + 4 * SYSCLK + 26 (lut),
1101 * WEOffTime = WEOnTime + 1 ns,
1102 * REOffTime = REOnTime + 4*SYSCLK + 26 ns (lut),
1103 * CSOffTime = REOffTime + 1 ns
1104 * ReadCycle = 2ns + 4*SYSCLK + 26 ns (lut),
1105 * WriteCycle = 2*SYSCLK + 2 ns,
1106 * CSPulseWidth = 10 ns */
1108 systim = 1000000000 / (sysclk / 1000);
1109 dev_dbg(blizzard.fbdev->dev,
1110 "Blizzard systim %lu ps extif_clk_period %u div %d\n",
1111 systim, blizzard.extif_clk_period, div);
1113 t = &blizzard.lut_timings;
1114 memset(t, 0, sizeof(*t));
1119 t->we_on_time = round_to_extif_ticks(t->cs_on_time + 2000, div);
1120 t->re_on_time = round_to_extif_ticks(t->cs_on_time + 2000, div);
1121 t->access_time = round_to_extif_ticks(t->re_on_time + 4 * systim +
1123 t->we_off_time = round_to_extif_ticks(t->we_on_time + 1000, div);
1124 t->re_off_time = round_to_extif_ticks(t->re_on_time + 4 * systim +
1126 t->cs_off_time = round_to_extif_ticks(t->re_off_time + 1000, div);
1127 t->we_cycle_time = round_to_extif_ticks(2 * systim + 2000, div);
1128 if (t->we_cycle_time < t->we_off_time)
1129 t->we_cycle_time = t->we_off_time;
1130 t->re_cycle_time = round_to_extif_ticks(2000 + 4 * systim + 26000, div);
1131 if (t->re_cycle_time < t->re_off_time)
1132 t->re_cycle_time = t->re_off_time;
1133 t->cs_pulse_width = 0;
1135 dev_dbg(blizzard.fbdev->dev,
1136 "[lut]cson %d csoff %d reon %d reoff %d\n",
1137 t->cs_on_time, t->cs_off_time, t->re_on_time, t->re_off_time);
1138 dev_dbg(blizzard.fbdev->dev,
1139 "[lut]weon %d weoff %d recyc %d wecyc %d\n",
1140 t->we_on_time, t->we_off_time, t->re_cycle_time,
1142 dev_dbg(blizzard.fbdev->dev, "[lut]rdaccess %d cspulse %d\n",
1143 t->access_time, t->cs_pulse_width);
1145 return blizzard.extif->convert_timings(t);
1148 static int calc_extif_timings(unsigned long sysclk, int *extif_mem_div)
1153 blizzard.extif->get_clk_info(&blizzard.extif_clk_period, &max_clk_div);
1154 for (div = 1; div <= max_clk_div; div++) {
1155 if (calc_reg_timing(sysclk, div) == 0)
1158 if (div > max_clk_div) {
1159 dev_dbg(blizzard.fbdev->dev, "reg timing failed\n");
1162 *extif_mem_div = div;
1164 for (div = 1; div <= max_clk_div; div++) {
1165 if (calc_lut_timing(sysclk, div) == 0)
1169 if (div > max_clk_div)
1172 blizzard.extif_clk_div = div;
1176 dev_err(blizzard.fbdev->dev, "can't setup timings\n");
1180 static void calc_blizzard_clk_rates(unsigned long ext_clk,
1181 unsigned long *sys_clk, unsigned long *pix_clk)
1184 int sys_div = 0, sys_mul = 0;
1187 pix_clk_src = blizzard_read_reg(BLIZZARD_CLK_SRC);
1188 pix_div = ((pix_clk_src >> 3) & 0x1f) + 1;
1189 if ((pix_clk_src & (0x3 << 1)) == 0) {
1190 /* Source is the PLL */
1191 sys_div = (blizzard_read_reg(BLIZZARD_PLL_DIV) & 0x3f) + 1;
1192 sys_mul = blizzard_read_reg(BLIZZARD_PLL_CLOCK_SYNTH_0);
1193 sys_mul |= ((blizzard_read_reg(BLIZZARD_PLL_CLOCK_SYNTH_1)
1195 *sys_clk = ext_clk * sys_mul / sys_div;
1196 } else /* else source is ext clk, or oscillator */
1199 *pix_clk = *sys_clk / pix_div; /* HZ */
1200 dev_dbg(blizzard.fbdev->dev,
1201 "ext_clk %ld pix_src %d pix_div %d sys_div %d sys_mul %d\n",
1202 ext_clk, pix_clk_src & (0x3 << 1), pix_div, sys_div, sys_mul);
1203 dev_dbg(blizzard.fbdev->dev, "sys_clk %ld pix_clk %ld\n",
1204 *sys_clk, *pix_clk);
1207 static int setup_tearsync(unsigned long pix_clk, int extif_div)
1213 int hs_pol_inv, vs_pol_inv;
1214 int use_hsvs, use_ndp;
1217 hsw = blizzard_read_reg(BLIZZARD_HSW);
1218 vsw = blizzard_read_reg(BLIZZARD_VSW);
1219 hs_pol_inv = !(hsw & 0x80);
1220 vs_pol_inv = !(vsw & 0x80);
1224 hdisp = blizzard_read_reg(BLIZZARD_HDISP) * 8;
1225 vdisp = blizzard_read_reg(BLIZZARD_VDISP0) +
1226 ((blizzard_read_reg(BLIZZARD_VDISP1) & 0x3) << 8);
1228 hndp = blizzard_read_reg(BLIZZARD_HNDP) & 0x3f;
1229 vndp = blizzard_read_reg(BLIZZARD_VNDP);
1231 /* time to transfer one pixel (16bpp) in ps */
1232 blizzard.pix_tx_time = blizzard.reg_timings.we_cycle_time;
1233 if (blizzard.extif->get_max_tx_rate != NULL) {
1234 /* The external interface might have a rate limitation,
1235 * if so, we have to maximize our transfer rate.
1237 unsigned long min_tx_time;
1238 unsigned long max_tx_rate = blizzard.extif->get_max_tx_rate();
1240 dev_dbg(blizzard.fbdev->dev, "max_tx_rate %ld HZ\n",
1242 min_tx_time = 1000000000 / (max_tx_rate / 1000); /* ps */
1243 if (blizzard.pix_tx_time < min_tx_time)
1244 blizzard.pix_tx_time = min_tx_time;
1247 /* time to update one line in ps */
1248 blizzard.line_upd_time = (hdisp + hndp) * 1000000 / (pix_clk / 1000);
1249 blizzard.line_upd_time *= 1000;
1250 if (hdisp * blizzard.pix_tx_time > blizzard.line_upd_time)
1251 /* transfer speed too low, we might have to use both
1255 /* decent transfer speed, we'll always use only VS */
1258 if (use_hsvs && (hs_pol_inv || vs_pol_inv)) {
1259 /* HS or'ed with VS doesn't work, use the active high
1260 * TE signal based on HNDP / VNDP */
1267 /* Use HS or'ed with VS as a TE signal if both are needed
1268 * or VNDP if only vsync is needed. */
1278 hs = hs * 1000000 / (pix_clk / 1000); /* ps */
1281 vs = vs * (hdisp + hndp) * 1000000 / (pix_clk / 1000); /* ps */
1286 /* set VS to 120% of HS to minimize VS detection time */
1288 /* minimize HS too */
1292 b = blizzard_read_reg(BLIZZARD_NDISP_CTRL_STATUS);
1294 b |= use_hsvs ? 1 : 0;
1295 b |= (use_ndp && use_hsvs) ? 0 : 2;
1296 blizzard_write_reg(BLIZZARD_NDISP_CTRL_STATUS, b);
1298 blizzard.vsync_only = !use_hsvs;
1300 dev_dbg(blizzard.fbdev->dev,
1301 "pix_clk %ld HZ pix_tx_time %ld ps line_upd_time %ld ps\n",
1302 pix_clk, blizzard.pix_tx_time, blizzard.line_upd_time);
1303 dev_dbg(blizzard.fbdev->dev,
1304 "hs %d ps vs %d ps mode %d vsync_only %d\n",
1305 hs, vs, b & 0x3, !use_hsvs);
1307 return blizzard.extif->setup_tearsync(1, hs, vs,
1308 hs_pol_inv, vs_pol_inv,
1312 static void blizzard_get_caps(int plane, struct omapfb_caps *caps)
1314 blizzard.int_ctrl->get_caps(plane, caps);
1315 caps->ctrl |= OMAPFB_CAPS_MANUAL_UPDATE |
1316 OMAPFB_CAPS_WINDOW_PIXEL_DOUBLE |
1317 OMAPFB_CAPS_WINDOW_SCALE |
1318 OMAPFB_CAPS_WINDOW_OVERLAY |
1319 OMAPFB_CAPS_WINDOW_ROTATE;
1320 if (blizzard.te_connected)
1321 caps->ctrl |= OMAPFB_CAPS_TEARSYNC;
1322 caps->wnd_color |= (1 << OMAPFB_COLOR_RGB565) |
1323 (1 << OMAPFB_COLOR_YUV420);
1326 static void _save_regs(struct blizzard_reg_list *list, int cnt)
1330 for (i = 0; i < cnt; i++, list++) {
1332 for (reg = list->start; reg <= list->end; reg += 2)
1333 blizzard_reg_cache[reg / 2] = blizzard_read_reg(reg);
1337 static void _restore_regs(struct blizzard_reg_list *list, int cnt)
1341 for (i = 0; i < cnt; i++, list++) {
1343 for (reg = list->start; reg <= list->end; reg += 2)
1344 blizzard_write_reg(reg, blizzard_reg_cache[reg / 2]);
1348 static void blizzard_save_all_regs(void)
1350 _save_regs(blizzard_pll_regs, ARRAY_SIZE(blizzard_pll_regs));
1351 _save_regs(blizzard_gen_regs, ARRAY_SIZE(blizzard_gen_regs));
1354 static void blizzard_restore_pll_regs(void)
1356 _restore_regs(blizzard_pll_regs, ARRAY_SIZE(blizzard_pll_regs));
1359 static void blizzard_restore_gen_regs(void)
1361 _restore_regs(blizzard_gen_regs, ARRAY_SIZE(blizzard_gen_regs));
1364 static void blizzard_suspend(void)
1369 if (blizzard.last_color_mode) {
1370 update_full_screen();
1373 blizzard.update_mode_before_suspend = blizzard.update_mode;
1374 /* the following will disable clocks as well */
1375 blizzard_set_update_mode(OMAPFB_UPDATE_DISABLED);
1377 blizzard_save_all_regs();
1379 blizzard_stop_sdram();
1381 l = blizzard_read_reg(BLIZZARD_POWER_SAVE);
1382 /* Standby, Sleep. We assume we use an external clock. */
1384 blizzard_write_reg(BLIZZARD_POWER_SAVE, l);
1386 tmo = jiffies + msecs_to_jiffies(100);
1387 while (!(blizzard_read_reg(BLIZZARD_PLL_MODE) & (1 << 1))) {
1388 if (time_after(jiffies, tmo)) {
1389 dev_err(blizzard.fbdev->dev,
1390 "s1d1374x: sleep timeout, stopping PLL manually\n");
1391 l = blizzard_read_reg(BLIZZARD_PLL_MODE);
1393 /* Disable PLL, counter function */
1395 blizzard_write_reg(BLIZZARD_PLL_MODE, l);
1401 if (blizzard.power_down != NULL)
1402 blizzard.power_down(blizzard.fbdev->dev);
1405 static void blizzard_resume(void)
1409 if (blizzard.power_up != NULL)
1410 blizzard.power_up(blizzard.fbdev->dev);
1412 l = blizzard_read_reg(BLIZZARD_POWER_SAVE);
1413 /* Standby, Sleep */
1415 blizzard_write_reg(BLIZZARD_POWER_SAVE, l);
1417 blizzard_restore_pll_regs();
1418 l = blizzard_read_reg(BLIZZARD_PLL_MODE);
1420 /* Enable PLL, counter function */
1422 blizzard_write_reg(BLIZZARD_PLL_MODE, l);
1424 while (!(blizzard_read_reg(BLIZZARD_PLL_DIV) & (1 << 7)))
1427 blizzard_restart_sdram();
1429 blizzard_restore_gen_regs();
1431 /* Enable display */
1432 blizzard_write_reg(BLIZZARD_DISPLAY_MODE, 0x01);
1434 /* the following will enable clocks as necessary */
1435 blizzard_set_update_mode(blizzard.update_mode_before_suspend);
1437 /* Force a background update */
1438 blizzard.zoom_on = 1;
1439 update_full_screen();
1443 static int blizzard_init(struct omapfb_device *fbdev, int ext_mode,
1444 struct omapfb_mem_desc *req_vram)
1448 unsigned long ext_clk;
1450 unsigned long sys_clk, pix_clk;
1451 struct omapfb_platform_data *omapfb_conf;
1452 struct blizzard_platform_data *ctrl_conf;
1454 blizzard.fbdev = fbdev;
1456 BUG_ON(!fbdev->ext_if || !fbdev->int_ctrl);
1458 blizzard.fbdev = fbdev;
1459 blizzard.extif = fbdev->ext_if;
1460 blizzard.int_ctrl = fbdev->int_ctrl;
1462 omapfb_conf = fbdev->dev->platform_data;
1463 ctrl_conf = omapfb_conf->ctrl_platform_data;
1464 if (ctrl_conf == NULL || ctrl_conf->get_clock_rate == NULL) {
1465 dev_err(fbdev->dev, "s1d1374x: missing platform data\n");
1470 blizzard.power_down = ctrl_conf->power_down;
1471 blizzard.power_up = ctrl_conf->power_up;
1473 spin_lock_init(&blizzard.req_lock);
1475 if ((r = blizzard.int_ctrl->init(fbdev, 1, req_vram)) < 0)
1478 if ((r = blizzard.extif->init(fbdev)) < 0)
1481 blizzard_ctrl.set_color_key = blizzard.int_ctrl->set_color_key;
1482 blizzard_ctrl.get_color_key = blizzard.int_ctrl->get_color_key;
1483 blizzard_ctrl.setup_mem = blizzard.int_ctrl->setup_mem;
1484 blizzard_ctrl.mmap = blizzard.int_ctrl->mmap;
1486 ext_clk = ctrl_conf->get_clock_rate(fbdev->dev);
1487 if ((r = calc_extif_timings(ext_clk, &extif_div)) < 0)
1490 set_extif_timings(&blizzard.reg_timings);
1492 if (blizzard.power_up != NULL)
1493 blizzard.power_up(fbdev->dev);
1495 calc_blizzard_clk_rates(ext_clk, &sys_clk, &pix_clk);
1497 if ((r = calc_extif_timings(sys_clk, &extif_div)) < 0)
1499 set_extif_timings(&blizzard.reg_timings);
1501 if (!(blizzard_read_reg(BLIZZARD_PLL_DIV) & 0x80)) {
1503 "controller not initialized by the bootloader\n");
1508 if (ctrl_conf->te_connected) {
1509 if ((r = setup_tearsync(pix_clk, extif_div)) < 0)
1511 blizzard.te_connected = 1;
1514 rev = blizzard_read_reg(BLIZZARD_REV_CODE);
1515 conf = blizzard_read_reg(BLIZZARD_CONFIG);
1517 switch (rev & 0xfc) {
1519 blizzard.version = BLIZZARD_VERSION_S1D13744;
1520 pr_info("omapfb: s1d13744 LCD controller rev %d "
1521 "initialized (CNF pins %x)\n", rev & 0x03, conf & 0x07);
1524 blizzard.version = BLIZZARD_VERSION_S1D13745;
1525 pr_info("omapfb: s1d13745 LCD controller rev %d "
1526 "initialized (CNF pins %x)\n", rev & 0x03, conf & 0x07);
1529 dev_err(fbdev->dev, "invalid s1d1374x revision %02x\n",
1535 blizzard.max_transmit_size = blizzard.extif->max_transmit_size;
1537 blizzard.update_mode = OMAPFB_UPDATE_DISABLED;
1539 blizzard.auto_update_window.x = 0;
1540 blizzard.auto_update_window.y = 0;
1541 blizzard.auto_update_window.width = fbdev->panel->x_res;
1542 blizzard.auto_update_window.height = fbdev->panel->y_res;
1543 blizzard.auto_update_window.out_x = 0;
1544 blizzard.auto_update_window.out_x = 0;
1545 blizzard.auto_update_window.out_width = fbdev->panel->x_res;
1546 blizzard.auto_update_window.out_height = fbdev->panel->y_res;
1547 blizzard.auto_update_window.format = 0;
1549 blizzard.screen_width = fbdev->panel->x_res;
1550 blizzard.screen_height = fbdev->panel->y_res;
1552 init_timer(&blizzard.auto_update_timer);
1553 blizzard.auto_update_timer.function = blizzard_update_window_auto;
1554 blizzard.auto_update_timer.data = 0;
1556 INIT_LIST_HEAD(&blizzard.free_req_list);
1557 INIT_LIST_HEAD(&blizzard.pending_req_list);
1558 for (i = 0; i < ARRAY_SIZE(blizzard.req_pool); i++)
1559 list_add(&blizzard.req_pool[i].entry, &blizzard.free_req_list);
1560 BUG_ON(i <= IRQ_REQ_POOL_SIZE);
1561 sema_init(&blizzard.req_sema, i - IRQ_REQ_POOL_SIZE);
1565 if (blizzard.power_down != NULL)
1566 blizzard.power_down(fbdev->dev);
1567 blizzard.extif->cleanup();
1569 blizzard.int_ctrl->cleanup();
1574 static void blizzard_cleanup(void)
1576 blizzard_set_update_mode(OMAPFB_UPDATE_DISABLED);
1577 blizzard.extif->cleanup();
1578 blizzard.int_ctrl->cleanup();
1579 if (blizzard.power_down != NULL)
1580 blizzard.power_down(blizzard.fbdev->dev);
1583 struct lcd_ctrl blizzard_ctrl = {
1585 .init = blizzard_init,
1586 .cleanup = blizzard_cleanup,
1587 .bind_client = blizzard_bind_client,
1588 .get_caps = blizzard_get_caps,
1589 .set_update_mode = blizzard_set_update_mode,
1590 .get_update_mode = blizzard_get_update_mode,
1591 .setup_plane = blizzard_setup_plane,
1592 .set_scale = blizzard_set_scale,
1593 .enable_plane = blizzard_enable_plane,
1594 .set_rotate = blizzard_set_rotate,
1595 .update_window = blizzard_update_window_async,
1596 .sync = blizzard_sync,
1597 .suspend = blizzard_suspend,
1598 .resume = blizzard_resume,