2 * OMAP2 Remote Frame Buffer Interface support
4 * Copyright (C) 2005 Nokia Corporation
5 * Author: Juha Yrj�l� <juha.yrjola@nokia.com>
6 * Imre Deak <imre.deak@nokia.com>
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * General Public License for more details.
18 * You should have received a copy of the GNU General Public License along
19 * with this program; if not, write to the Free Software Foundation, Inc.,
20 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
22 #include <linux/module.h>
23 #include <linux/delay.h>
24 #include <linux/i2c.h>
25 #include <linux/err.h>
26 #include <linux/interrupt.h>
27 #include <linux/clk.h>
30 #include <mach/omapfb.h>
34 /* To work around an RFBI transfer rate limitation */
35 #define OMAP_RFBI_RATE_LIMIT 1
37 #define RFBI_BASE 0x48050800
38 #define RFBI_REVISION 0x0000
39 #define RFBI_SYSCONFIG 0x0010
40 #define RFBI_SYSSTATUS 0x0014
41 #define RFBI_CONTROL 0x0040
42 #define RFBI_PIXEL_CNT 0x0044
43 #define RFBI_LINE_NUMBER 0x0048
44 #define RFBI_CMD 0x004c
45 #define RFBI_PARAM 0x0050
46 #define RFBI_DATA 0x0054
47 #define RFBI_READ 0x0058
48 #define RFBI_STATUS 0x005c
49 #define RFBI_CONFIG0 0x0060
50 #define RFBI_ONOFF_TIME0 0x0064
51 #define RFBI_CYCLE_TIME0 0x0068
52 #define RFBI_DATA_CYCLE1_0 0x006c
53 #define RFBI_DATA_CYCLE2_0 0x0070
54 #define RFBI_DATA_CYCLE3_0 0x0074
55 #define RFBI_VSYNC_WIDTH 0x0090
56 #define RFBI_HSYNC_WIDTH 0x0094
58 #define DISPC_BASE 0x48050400
59 #define DISPC_CONTROL 0x0040
60 #define DISPC_IRQ_FRAMEMASK 0x0001
64 void (*lcdc_callback)(void *data);
65 void *lcdc_callback_data;
68 struct omapfb_device *fbdev;
71 unsigned tearsync_pin_cnt;
72 unsigned tearsync_mode;
75 static inline void rfbi_write_reg(int idx, u32 val)
77 __raw_writel(val, rfbi.base + idx);
80 static inline u32 rfbi_read_reg(int idx)
82 return __raw_readl(rfbi.base + idx);
85 static int rfbi_get_clocks(void)
87 if (IS_ERR((rfbi.dss_ick = clk_get(rfbi.fbdev->dev, "dss_ick")))) {
88 dev_err(rfbi.fbdev->dev, "can't get dss_ick\n");
89 return PTR_ERR(rfbi.dss_ick);
92 if (IS_ERR((rfbi.dss1_fck = clk_get(rfbi.fbdev->dev, "dss1_fck")))) {
93 dev_err(rfbi.fbdev->dev, "can't get dss1_fck\n");
94 clk_put(rfbi.dss_ick);
95 return PTR_ERR(rfbi.dss1_fck);
101 static void rfbi_put_clocks(void)
103 clk_put(rfbi.dss1_fck);
104 clk_put(rfbi.dss_ick);
107 static void rfbi_enable_clocks(int enable)
110 clk_enable(rfbi.dss_ick);
111 clk_enable(rfbi.dss1_fck);
113 clk_disable(rfbi.dss1_fck);
114 clk_disable(rfbi.dss_ick);
120 static void rfbi_print_timings(void)
125 l = rfbi_read_reg(RFBI_CONFIG0);
126 time = 1000000000 / rfbi.l4_khz;
130 dev_dbg(rfbi.fbdev->dev, "Tick time %u ps\n", time);
131 l = rfbi_read_reg(RFBI_ONOFF_TIME0);
132 dev_dbg(rfbi.fbdev->dev,
133 "CSONTIME %d, CSOFFTIME %d, WEONTIME %d, WEOFFTIME %d, "
134 "REONTIME %d, REOFFTIME %d\n",
135 l & 0x0f, (l >> 4) & 0x3f, (l >> 10) & 0x0f, (l >> 14) & 0x3f,
136 (l >> 20) & 0x0f, (l >> 24) & 0x3f);
138 l = rfbi_read_reg(RFBI_CYCLE_TIME0);
139 dev_dbg(rfbi.fbdev->dev,
140 "WECYCLETIME %d, RECYCLETIME %d, CSPULSEWIDTH %d, "
142 (l & 0x3f), (l >> 6) & 0x3f, (l >> 12) & 0x3f,
146 static void rfbi_print_timings(void) {}
149 static void rfbi_set_timings(const struct extif_timings *t)
153 BUG_ON(!t->converted);
155 rfbi_enable_clocks(1);
156 rfbi_write_reg(RFBI_ONOFF_TIME0, t->tim[0]);
157 rfbi_write_reg(RFBI_CYCLE_TIME0, t->tim[1]);
159 l = rfbi_read_reg(RFBI_CONFIG0);
161 l |= (t->tim[2] ? 1 : 0) << 4;
162 rfbi_write_reg(RFBI_CONFIG0, l);
164 rfbi_print_timings();
165 rfbi_enable_clocks(0);
168 static void rfbi_get_clk_info(u32 *clk_period, u32 *max_clk_div)
170 *clk_period = 1000000000 / rfbi.l4_khz;
174 static int ps_to_rfbi_ticks(int time, int div)
176 unsigned long tick_ps;
179 /* Calculate in picosecs to yield more exact results */
180 tick_ps = 1000000000 / (rfbi.l4_khz) * div;
182 ret = (time + tick_ps - 1) / tick_ps;
187 #ifdef OMAP_RFBI_RATE_LIMIT
188 static unsigned long rfbi_get_max_tx_rate(void)
190 unsigned long l4_rate, dss1_rate;
191 int min_l4_ticks = 0;
194 /* According to TI this can't be calculated so make the
195 * adjustments for a couple of known frequencies and warn for
198 static const struct {
199 unsigned long l4_clk; /* HZ */
200 unsigned long dss1_clk; /* HZ */
201 unsigned long min_l4_ticks;
203 { 55, 132, 7, }, /* 7.86 MPix/s */
204 { 110, 110, 12, }, /* 9.16 MPix/s */
205 { 110, 132, 10, }, /* 11 Mpix/s */
206 { 120, 120, 10, }, /* 12 Mpix/s */
207 { 133, 133, 10, }, /* 13.3 Mpix/s */
210 l4_rate = rfbi.l4_khz / 1000;
211 dss1_rate = clk_get_rate(rfbi.dss1_fck) / 1000000;
213 for (i = 0; i < ARRAY_SIZE(ftab); i++) {
214 /* Use a window instead of an exact match, to account
215 * for different DPLL multiplier / divider pairs.
217 if (abs(ftab[i].l4_clk - l4_rate) < 3 &&
218 abs(ftab[i].dss1_clk - dss1_rate) < 3) {
219 min_l4_ticks = ftab[i].min_l4_ticks;
223 if (i == ARRAY_SIZE(ftab)) {
224 /* Can't be sure, return anyway the maximum not
225 * rate-limited. This might cause a problem only for the
226 * tearing synchronisation.
228 dev_err(rfbi.fbdev->dev,
229 "can't determine maximum RFBI transfer rate\n");
230 return rfbi.l4_khz * 1000;
232 return rfbi.l4_khz * 1000 / min_l4_ticks;
235 static int rfbi_get_max_tx_rate(void)
237 return rfbi.l4_khz * 1000;
242 static int rfbi_convert_timings(struct extif_timings *t)
245 int reon, reoff, weon, weoff, cson, csoff, cs_pulse;
246 int actim, recyc, wecyc;
247 int div = t->clk_div;
249 if (div <= 0 || div > 2)
252 /* Make sure that after conversion it still holds that:
253 * weoff > weon, reoff > reon, recyc >= reoff, wecyc >= weoff,
254 * csoff > cson, csoff >= max(weoff, reoff), actim > reon
256 weon = ps_to_rfbi_ticks(t->we_on_time, div);
257 weoff = ps_to_rfbi_ticks(t->we_off_time, div);
265 reon = ps_to_rfbi_ticks(t->re_on_time, div);
266 reoff = ps_to_rfbi_ticks(t->re_off_time, div);
274 cson = ps_to_rfbi_ticks(t->cs_on_time, div);
275 csoff = ps_to_rfbi_ticks(t->cs_off_time, div);
278 if (csoff < max(weoff, reoff))
279 csoff = max(weoff, reoff);
294 actim = ps_to_rfbi_ticks(t->access_time, div);
300 wecyc = ps_to_rfbi_ticks(t->we_cycle_time, div);
306 recyc = ps_to_rfbi_ticks(t->re_cycle_time, div);
312 cs_pulse = ps_to_rfbi_ticks(t->cs_pulse_width, div);
330 static int rfbi_setup_tearsync(unsigned pin_cnt,
331 unsigned hs_pulse_time, unsigned vs_pulse_time,
332 int hs_pol_inv, int vs_pol_inv, int extif_div)
338 if (pin_cnt != 1 && pin_cnt != 2)
341 hs = ps_to_rfbi_ticks(hs_pulse_time, 1);
342 vs = ps_to_rfbi_ticks(vs_pulse_time, 1);
353 rfbi.tearsync_pin_cnt = pin_cnt;
354 dev_dbg(rfbi.fbdev->dev,
355 "setup_tearsync: pins %d hs %d vs %d hs_inv %d vs_inv %d\n",
356 pin_cnt, hs, vs, hs_pol_inv, vs_pol_inv);
358 rfbi_enable_clocks(1);
359 rfbi_write_reg(RFBI_HSYNC_WIDTH, hs);
360 rfbi_write_reg(RFBI_VSYNC_WIDTH, vs);
362 l = rfbi_read_reg(RFBI_CONFIG0);
371 rfbi_enable_clocks(0);
376 static int rfbi_enable_tearsync(int enable, unsigned line)
380 dev_dbg(rfbi.fbdev->dev, "tearsync %d line %d mode %d\n",
381 enable, line, rfbi.tearsync_mode);
382 if (line > (1 << 11) - 1)
385 rfbi_enable_clocks(1);
386 l = rfbi_read_reg(RFBI_CONFIG0);
389 rfbi.tearsync_mode = rfbi.tearsync_pin_cnt;
390 l |= rfbi.tearsync_mode << 2;
392 rfbi.tearsync_mode = 0;
393 rfbi_write_reg(RFBI_CONFIG0, l);
394 rfbi_write_reg(RFBI_LINE_NUMBER, line);
395 rfbi_enable_clocks(0);
400 static void rfbi_write_command(const void *buf, unsigned int len)
402 rfbi_enable_clocks(1);
403 if (rfbi.bits_per_cycle == 16) {
406 for (; len; len -= 2)
407 rfbi_write_reg(RFBI_CMD, *w++);
410 BUG_ON(rfbi.bits_per_cycle != 8);
412 rfbi_write_reg(RFBI_CMD, *b++);
414 rfbi_enable_clocks(0);
417 static void rfbi_read_data(void *buf, unsigned int len)
419 rfbi_enable_clocks(1);
420 if (rfbi.bits_per_cycle == 16) {
423 for (; len; len -= 2) {
424 rfbi_write_reg(RFBI_READ, 0);
425 *w++ = rfbi_read_reg(RFBI_READ);
429 BUG_ON(rfbi.bits_per_cycle != 8);
431 rfbi_write_reg(RFBI_READ, 0);
432 *b++ = rfbi_read_reg(RFBI_READ);
435 rfbi_enable_clocks(0);
438 static void rfbi_write_data(const void *buf, unsigned int len)
440 rfbi_enable_clocks(1);
441 if (rfbi.bits_per_cycle == 16) {
444 for (; len; len -= 2)
445 rfbi_write_reg(RFBI_PARAM, *w++);
448 BUG_ON(rfbi.bits_per_cycle != 8);
450 rfbi_write_reg(RFBI_PARAM, *b++);
452 rfbi_enable_clocks(0);
455 static void rfbi_transfer_area(int width, int height,
456 void (callback)(void * data), void *data)
460 BUG_ON(callback == NULL);
462 rfbi_enable_clocks(1);
463 omap_dispc_set_lcd_size(width, height);
465 rfbi.lcdc_callback = callback;
466 rfbi.lcdc_callback_data = data;
468 rfbi_write_reg(RFBI_PIXEL_CNT, width * height);
470 w = rfbi_read_reg(RFBI_CONTROL);
472 if (!rfbi.tearsync_mode)
473 w |= 1 << 4; /* internal trigger, reset by HW */
474 rfbi_write_reg(RFBI_CONTROL, w);
476 omap_dispc_enable_lcd_out(1);
479 static inline void _stop_transfer(void)
483 w = rfbi_read_reg(RFBI_CONTROL);
484 rfbi_write_reg(RFBI_CONTROL, w & ~(1 << 0));
485 rfbi_enable_clocks(0);
488 static void rfbi_dma_callback(void *data)
491 rfbi.lcdc_callback(rfbi.lcdc_callback_data);
494 static void rfbi_set_bits_per_cycle(int bpc)
498 rfbi_enable_clocks(1);
499 l = rfbi_read_reg(RFBI_CONFIG0);
511 rfbi_write_reg(RFBI_CONFIG0, l);
512 rfbi.bits_per_cycle = bpc;
513 rfbi_enable_clocks(0);
516 static int rfbi_init(struct omapfb_device *fbdev)
522 rfbi.base = ioremap(RFBI_BASE, SZ_1K);
524 dev_err(fbdev->dev, "can't ioremap RFBI\n");
528 if ((r = rfbi_get_clocks()) < 0)
530 rfbi_enable_clocks(1);
532 rfbi.l4_khz = clk_get_rate(rfbi.dss_ick) / 1000;
535 rfbi_write_reg(RFBI_SYSCONFIG, 1 << 1);
536 while (!(rfbi_read_reg(RFBI_SYSSTATUS) & (1 << 0)));
538 l = rfbi_read_reg(RFBI_SYSCONFIG);
539 /* Enable autoidle and smart-idle */
540 l |= (1 << 0) | (2 << 3);
541 rfbi_write_reg(RFBI_SYSCONFIG, l);
543 /* 16-bit interface, ITE trigger mode, 16-bit data */
544 l = (0x03 << 0) | (0x00 << 2) | (0x01 << 5) | (0x02 << 7);
545 l |= (0 << 9) | (1 << 20) | (1 << 21);
546 rfbi_write_reg(RFBI_CONFIG0, l);
548 rfbi_write_reg(RFBI_DATA_CYCLE1_0, 0x00000010);
550 l = rfbi_read_reg(RFBI_CONTROL);
551 /* Select CS0, clear bypass mode */
553 rfbi_write_reg(RFBI_CONTROL, l);
555 if ((r = omap_dispc_request_irq(DISPC_IRQ_FRAMEMASK, rfbi_dma_callback,
557 dev_err(fbdev->dev, "can't get DISPC irq\n");
558 rfbi_enable_clocks(0);
562 l = rfbi_read_reg(RFBI_REVISION);
563 pr_info("omapfb: RFBI version %d.%d initialized\n",
564 (l >> 4) & 0x0f, l & 0x0f);
566 rfbi_enable_clocks(0);
571 static void rfbi_cleanup(void)
573 omap_dispc_free_irq(DISPC_IRQ_FRAMEMASK, rfbi_dma_callback, NULL);
578 const struct lcd_ctrl_extif omap2_ext_if = {
580 .cleanup = rfbi_cleanup,
581 .get_clk_info = rfbi_get_clk_info,
582 .get_max_tx_rate = rfbi_get_max_tx_rate,
583 .set_bits_per_cycle = rfbi_set_bits_per_cycle,
584 .convert_timings = rfbi_convert_timings,
585 .set_timings = rfbi_set_timings,
586 .write_command = rfbi_write_command,
587 .read_data = rfbi_read_data,
588 .write_data = rfbi_write_data,
589 .transfer_area = rfbi_transfer_area,
590 .setup_tearsync = rfbi_setup_tearsync,
591 .enable_tearsync = rfbi_enable_tearsync,
593 .max_transmit_size = (u32) ~0,