2 * linux/drivers/video/pxafb.c
4 * Copyright (C) 1999 Eric A. Thomas.
5 * Copyright (C) 2004 Jean-Frederic Clere.
6 * Copyright (C) 2004 Ian Campbell.
7 * Copyright (C) 2004 Jeff Lackey.
8 * Based on sa1100fb.c Copyright (C) 1999 Eric A. Thomas
10 * Based on acornfb.c Copyright (C) Russell King.
12 * This file is subject to the terms and conditions of the GNU General Public
13 * License. See the file COPYING in the main directory of this archive for
16 * Intel PXA250/210 LCD Controller Frame Buffer Driver
18 * Please direct your questions and comments on this driver to the following
21 * linux-arm-kernel@lists.arm.linux.org.uk
23 * Add support for overlay1 and overlay2 based on pxafb_overlay.c:
25 * Copyright (C) 2004, Intel Corporation
27 * 2003/08/27: <yu.tang@intel.com>
28 * 2004/03/10: <stanley.cai@intel.com>
29 * 2004/10/28: <yan.yin@intel.com>
31 * Copyright (C) 2006-2008 Marvell International Ltd.
35 #include <linux/module.h>
36 #include <linux/moduleparam.h>
37 #include <linux/kernel.h>
38 #include <linux/sched.h>
39 #include <linux/errno.h>
40 #include <linux/string.h>
41 #include <linux/interrupt.h>
42 #include <linux/slab.h>
45 #include <linux/delay.h>
46 #include <linux/init.h>
47 #include <linux/ioport.h>
48 #include <linux/cpufreq.h>
49 #include <linux/platform_device.h>
50 #include <linux/dma-mapping.h>
51 #include <linux/clk.h>
52 #include <linux/err.h>
53 #include <linux/completion.h>
54 #include <linux/mutex.h>
55 #include <linux/kthread.h>
56 #include <linux/freezer.h>
58 #include <mach/hardware.h>
61 #include <asm/div64.h>
62 #include <mach/bitfield.h>
63 #include <mach/pxafb.h>
66 * Complain if VAR is out of range.
72 /* Bits which should not be set in machine configuration structures */
73 #define LCCR0_INVALID_CONFIG_MASK (LCCR0_OUM | LCCR0_BM | LCCR0_QDM |\
74 LCCR0_DIS | LCCR0_EFM | LCCR0_IUM |\
75 LCCR0_SFM | LCCR0_LDM | LCCR0_ENB)
77 #define LCCR3_INVALID_CONFIG_MASK (LCCR3_HSP | LCCR3_VSP |\
78 LCCR3_PCD | LCCR3_BPP(0xf))
80 static int pxafb_activate_var(struct fb_var_screeninfo *var,
82 static void set_ctrlr_state(struct pxafb_info *fbi, u_int state);
83 static void setup_base_frame(struct pxafb_info *fbi, int branch);
84 static int setup_frame_dma(struct pxafb_info *fbi, int dma, int pal,
85 unsigned long offset, size_t size);
87 static unsigned long video_mem_size = 0;
89 static inline unsigned long
90 lcd_readl(struct pxafb_info *fbi, unsigned int off)
92 return __raw_readl(fbi->mmio_base + off);
96 lcd_writel(struct pxafb_info *fbi, unsigned int off, unsigned long val)
98 __raw_writel(val, fbi->mmio_base + off);
101 static inline void pxafb_schedule_work(struct pxafb_info *fbi, u_int state)
105 local_irq_save(flags);
107 * We need to handle two requests being made at the same time.
108 * There are two important cases:
109 * 1. When we are changing VT (C_REENABLE) while unblanking
110 * (C_ENABLE) We must perform the unblanking, which will
111 * do our REENABLE for us.
112 * 2. When we are blanking, but immediately unblank before
113 * we have blanked. We do the "REENABLE" thing here as
114 * well, just to be sure.
116 if (fbi->task_state == C_ENABLE && state == C_REENABLE)
118 if (fbi->task_state == C_DISABLE && state == C_ENABLE)
121 if (state != (u_int)-1) {
122 fbi->task_state = state;
123 schedule_work(&fbi->task);
125 local_irq_restore(flags);
128 static inline u_int chan_to_field(u_int chan, struct fb_bitfield *bf)
131 chan >>= 16 - bf->length;
132 return chan << bf->offset;
136 pxafb_setpalettereg(u_int regno, u_int red, u_int green, u_int blue,
137 u_int trans, struct fb_info *info)
139 struct pxafb_info *fbi = (struct pxafb_info *)info;
142 if (regno >= fbi->palette_size)
145 if (fbi->fb.var.grayscale) {
146 fbi->palette_cpu[regno] = ((blue >> 8) & 0x00ff);
150 switch (fbi->lccr4 & LCCR4_PAL_FOR_MASK) {
151 case LCCR4_PAL_FOR_0:
152 val = ((red >> 0) & 0xf800);
153 val |= ((green >> 5) & 0x07e0);
154 val |= ((blue >> 11) & 0x001f);
155 fbi->palette_cpu[regno] = val;
157 case LCCR4_PAL_FOR_1:
158 val = ((red << 8) & 0x00f80000);
159 val |= ((green >> 0) & 0x0000fc00);
160 val |= ((blue >> 8) & 0x000000f8);
161 ((u32 *)(fbi->palette_cpu))[regno] = val;
163 case LCCR4_PAL_FOR_2:
164 val = ((red << 8) & 0x00fc0000);
165 val |= ((green >> 0) & 0x0000fc00);
166 val |= ((blue >> 8) & 0x000000fc);
167 ((u32 *)(fbi->palette_cpu))[regno] = val;
169 case LCCR4_PAL_FOR_3:
170 val = ((red << 8) & 0x00ff0000);
171 val |= ((green >> 0) & 0x0000ff00);
172 val |= ((blue >> 8) & 0x000000ff);
173 ((u32 *)(fbi->palette_cpu))[regno] = val;
181 pxafb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
182 u_int trans, struct fb_info *info)
184 struct pxafb_info *fbi = (struct pxafb_info *)info;
189 * If inverse mode was selected, invert all the colours
190 * rather than the register number. The register number
191 * is what you poke into the framebuffer to produce the
192 * colour you requested.
194 if (fbi->cmap_inverse) {
196 green = 0xffff - green;
197 blue = 0xffff - blue;
201 * If greyscale is true, then we convert the RGB value
202 * to greyscale no matter what visual we are using.
204 if (fbi->fb.var.grayscale)
205 red = green = blue = (19595 * red + 38470 * green +
208 switch (fbi->fb.fix.visual) {
209 case FB_VISUAL_TRUECOLOR:
211 * 16-bit True Colour. We encode the RGB value
212 * according to the RGB bitfield information.
215 u32 *pal = fbi->fb.pseudo_palette;
217 val = chan_to_field(red, &fbi->fb.var.red);
218 val |= chan_to_field(green, &fbi->fb.var.green);
219 val |= chan_to_field(blue, &fbi->fb.var.blue);
226 case FB_VISUAL_STATIC_PSEUDOCOLOR:
227 case FB_VISUAL_PSEUDOCOLOR:
228 ret = pxafb_setpalettereg(regno, red, green, blue, trans, info);
235 /* calculate pixel depth, transparency bit included, >=16bpp formats _only_ */
236 static inline int var_to_depth(struct fb_var_screeninfo *var)
238 return var->red.length + var->green.length +
239 var->blue.length + var->transp.length;
242 /* calculate 4-bit BPP value for LCCR3 and OVLxC1 */
243 static int pxafb_var_to_bpp(struct fb_var_screeninfo *var)
247 switch (var->bits_per_pixel) {
248 case 1: bpp = 0; break;
249 case 2: bpp = 1; break;
250 case 4: bpp = 2; break;
251 case 8: bpp = 3; break;
252 case 16: bpp = 4; break;
254 switch (var_to_depth(var)) {
255 case 18: bpp = 6; break; /* 18-bits/pixel packed */
256 case 19: bpp = 8; break; /* 19-bits/pixel packed */
257 case 24: bpp = 9; break;
261 switch (var_to_depth(var)) {
262 case 18: bpp = 5; break; /* 18-bits/pixel unpacked */
263 case 19: bpp = 7; break; /* 19-bits/pixel unpacked */
264 case 25: bpp = 10; break;
272 * pxafb_var_to_lccr3():
273 * Convert a bits per pixel value to the correct bit pattern for LCCR3
275 * NOTE: for PXA27x with overlays support, the LCCR3_PDFOR_x bits have an
276 * implication of the acutal use of transparency bit, which we handle it
277 * here separatedly. See PXA27x Developer's Manual, Section <<7.4.6 Pixel
278 * Formats>> for the valid combination of PDFOR, PAL_FOR for various BPP.
280 * Transparency for palette pixel formats is not supported at the moment.
282 static uint32_t pxafb_var_to_lccr3(struct fb_var_screeninfo *var)
284 int bpp = pxafb_var_to_bpp(var);
290 lccr3 = LCCR3_BPP(bpp);
292 switch (var_to_depth(var)) {
293 case 16: lccr3 |= var->transp.length ? LCCR3_PDFOR_3 : 0; break;
294 case 18: lccr3 |= LCCR3_PDFOR_3; break;
295 case 24: lccr3 |= var->transp.length ? LCCR3_PDFOR_2 : LCCR3_PDFOR_3;
298 case 25: lccr3 |= LCCR3_PDFOR_0; break;
303 #define SET_PIXFMT(v, r, g, b, t) \
305 (v)->transp.offset = (t) ? (r) + (g) + (b) : 0; \
306 (v)->transp.length = (t) ? (t) : 0; \
307 (v)->blue.length = (b); (v)->blue.offset = 0; \
308 (v)->green.length = (g); (v)->green.offset = (b); \
309 (v)->red.length = (r); (v)->red.offset = (b) + (g); \
312 /* set the RGBT bitfields of fb_var_screeninf according to
313 * var->bits_per_pixel and given depth
315 static void pxafb_set_pixfmt(struct fb_var_screeninfo *var, int depth)
318 depth = var->bits_per_pixel;
320 if (var->bits_per_pixel < 16) {
321 /* indexed pixel formats */
322 var->red.offset = 0; var->red.length = 8;
323 var->green.offset = 0; var->green.length = 8;
324 var->blue.offset = 0; var->blue.length = 8;
325 var->transp.offset = 0; var->transp.length = 8;
329 case 16: var->transp.length ?
330 SET_PIXFMT(var, 5, 5, 5, 1) : /* RGBT555 */
331 SET_PIXFMT(var, 5, 6, 5, 0); break; /* RGB565 */
332 case 18: SET_PIXFMT(var, 6, 6, 6, 0); break; /* RGB666 */
333 case 19: SET_PIXFMT(var, 6, 6, 6, 1); break; /* RGBT666 */
334 case 24: var->transp.length ?
335 SET_PIXFMT(var, 8, 8, 7, 1) : /* RGBT887 */
336 SET_PIXFMT(var, 8, 8, 8, 0); break; /* RGB888 */
337 case 25: SET_PIXFMT(var, 8, 8, 8, 1); break; /* RGBT888 */
341 #ifdef CONFIG_CPU_FREQ
343 * pxafb_display_dma_period()
344 * Calculate the minimum period (in picoseconds) between two DMA
345 * requests for the LCD controller. If we hit this, it means we're
346 * doing nothing but LCD DMA.
348 static unsigned int pxafb_display_dma_period(struct fb_var_screeninfo *var)
351 * Period = pixclock * bits_per_byte * bytes_per_transfer
352 * / memory_bits_per_pixel;
354 return var->pixclock * 8 * 16 / var->bits_per_pixel;
359 * Select the smallest mode that allows the desired resolution to be
360 * displayed. If desired parameters can be rounded up.
362 static struct pxafb_mode_info *pxafb_getmode(struct pxafb_mach_info *mach,
363 struct fb_var_screeninfo *var)
365 struct pxafb_mode_info *mode = NULL;
366 struct pxafb_mode_info *modelist = mach->modes;
367 unsigned int best_x = 0xffffffff, best_y = 0xffffffff;
370 for (i = 0; i < mach->num_modes; i++) {
371 if (modelist[i].xres >= var->xres &&
372 modelist[i].yres >= var->yres &&
373 modelist[i].xres < best_x &&
374 modelist[i].yres < best_y &&
375 modelist[i].bpp >= var->bits_per_pixel) {
376 best_x = modelist[i].xres;
377 best_y = modelist[i].yres;
385 static void pxafb_setmode(struct fb_var_screeninfo *var,
386 struct pxafb_mode_info *mode)
388 var->xres = mode->xres;
389 var->yres = mode->yres;
390 var->bits_per_pixel = mode->bpp;
391 var->pixclock = mode->pixclock;
392 var->hsync_len = mode->hsync_len;
393 var->left_margin = mode->left_margin;
394 var->right_margin = mode->right_margin;
395 var->vsync_len = mode->vsync_len;
396 var->upper_margin = mode->upper_margin;
397 var->lower_margin = mode->lower_margin;
398 var->sync = mode->sync;
399 var->grayscale = mode->cmap_greyscale;
401 /* set the initial RGBA bitfields */
402 pxafb_set_pixfmt(var, mode->depth);
405 static int pxafb_adjust_timing(struct pxafb_info *fbi,
406 struct fb_var_screeninfo *var)
410 var->xres = max_t(int, var->xres, MIN_XRES);
411 var->yres = max_t(int, var->yres, MIN_YRES);
413 if (!(fbi->lccr0 & LCCR0_LCDT)) {
414 clamp_val(var->hsync_len, 1, 64);
415 clamp_val(var->vsync_len, 1, 64);
416 clamp_val(var->left_margin, 1, 255);
417 clamp_val(var->right_margin, 1, 255);
418 clamp_val(var->upper_margin, 1, 255);
419 clamp_val(var->lower_margin, 1, 255);
422 /* make sure each line is aligned on word boundary */
423 line_length = var->xres * var->bits_per_pixel / 8;
424 line_length = ALIGN(line_length, 4);
425 var->xres = line_length * 8 / var->bits_per_pixel;
427 /* we don't support xpan, force xres_virtual to be equal to xres */
428 var->xres_virtual = var->xres;
430 if (var->accel_flags & FB_ACCELF_TEXT)
431 var->yres_virtual = fbi->fb.fix.smem_len / line_length;
433 var->yres_virtual = max(var->yres_virtual, var->yres);
435 /* check for limits */
436 if (var->xres > MAX_XRES || var->yres > MAX_YRES)
439 if (var->yres > var->yres_virtual)
447 * Get the video params out of 'var'. If a value doesn't fit, round it up,
448 * if it's too big, return -EINVAL.
450 * Round up in the following order: bits_per_pixel, xres,
451 * yres, xres_virtual, yres_virtual, xoffset, yoffset, grayscale,
452 * bitfields, horizontal timing, vertical timing.
454 static int pxafb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
456 struct pxafb_info *fbi = (struct pxafb_info *)info;
457 struct pxafb_mach_info *inf = fbi->dev->platform_data;
460 if (inf->fixed_modes) {
461 struct pxafb_mode_info *mode;
463 mode = pxafb_getmode(inf, var);
466 pxafb_setmode(var, mode);
469 /* do a test conversion to BPP fields to check the color formats */
470 err = pxafb_var_to_bpp(var);
474 pxafb_set_pixfmt(var, var_to_depth(var));
476 err = pxafb_adjust_timing(fbi, var);
480 #ifdef CONFIG_CPU_FREQ
481 pr_debug("pxafb: dma period = %d ps\n",
482 pxafb_display_dma_period(var));
490 * Set the user defined part of the display for the specified console
492 static int pxafb_set_par(struct fb_info *info)
494 struct pxafb_info *fbi = (struct pxafb_info *)info;
495 struct fb_var_screeninfo *var = &info->var;
497 if (var->bits_per_pixel >= 16)
498 fbi->fb.fix.visual = FB_VISUAL_TRUECOLOR;
499 else if (!fbi->cmap_static)
500 fbi->fb.fix.visual = FB_VISUAL_PSEUDOCOLOR;
503 * Some people have weird ideas about wanting static
504 * pseudocolor maps. I suspect their user space
505 * applications are broken.
507 fbi->fb.fix.visual = FB_VISUAL_STATIC_PSEUDOCOLOR;
510 fbi->fb.fix.line_length = var->xres_virtual *
511 var->bits_per_pixel / 8;
512 if (var->bits_per_pixel >= 16)
513 fbi->palette_size = 0;
515 fbi->palette_size = var->bits_per_pixel == 1 ?
516 4 : 1 << var->bits_per_pixel;
518 fbi->palette_cpu = (u16 *)&fbi->dma_buff->palette[0];
520 if (fbi->fb.var.bits_per_pixel >= 16)
521 fb_dealloc_cmap(&fbi->fb.cmap);
523 fb_alloc_cmap(&fbi->fb.cmap, 1<<fbi->fb.var.bits_per_pixel, 0);
525 pxafb_activate_var(var, fbi);
530 static int pxafb_pan_display(struct fb_var_screeninfo *var,
531 struct fb_info *info)
533 struct pxafb_info *fbi = (struct pxafb_info *)info;
534 int dma = DMA_MAX + DMA_BASE;
536 if (fbi->state != C_ENABLE)
539 setup_base_frame(fbi, 1);
541 if (fbi->lccr0 & LCCR0_SDS)
542 lcd_writel(fbi, FBR1, fbi->fdadr[dma + 1] | 0x1);
544 lcd_writel(fbi, FBR0, fbi->fdadr[dma] | 0x1);
550 * Blank the display by setting all palette values to zero. Note, the
551 * 16 bpp mode does not really use the palette, so this will not
552 * blank the display in all modes.
554 static int pxafb_blank(int blank, struct fb_info *info)
556 struct pxafb_info *fbi = (struct pxafb_info *)info;
560 case FB_BLANK_POWERDOWN:
561 case FB_BLANK_VSYNC_SUSPEND:
562 case FB_BLANK_HSYNC_SUSPEND:
563 case FB_BLANK_NORMAL:
564 if (fbi->fb.fix.visual == FB_VISUAL_PSEUDOCOLOR ||
565 fbi->fb.fix.visual == FB_VISUAL_STATIC_PSEUDOCOLOR)
566 for (i = 0; i < fbi->palette_size; i++)
567 pxafb_setpalettereg(i, 0, 0, 0, 0, info);
569 pxafb_schedule_work(fbi, C_DISABLE);
570 /* TODO if (pxafb_blank_helper) pxafb_blank_helper(blank); */
573 case FB_BLANK_UNBLANK:
574 /* TODO if (pxafb_blank_helper) pxafb_blank_helper(blank); */
575 if (fbi->fb.fix.visual == FB_VISUAL_PSEUDOCOLOR ||
576 fbi->fb.fix.visual == FB_VISUAL_STATIC_PSEUDOCOLOR)
577 fb_set_cmap(&fbi->fb.cmap, info);
578 pxafb_schedule_work(fbi, C_ENABLE);
583 static struct fb_ops pxafb_ops = {
584 .owner = THIS_MODULE,
585 .fb_check_var = pxafb_check_var,
586 .fb_set_par = pxafb_set_par,
587 .fb_pan_display = pxafb_pan_display,
588 .fb_setcolreg = pxafb_setcolreg,
589 .fb_fillrect = cfb_fillrect,
590 .fb_copyarea = cfb_copyarea,
591 .fb_imageblit = cfb_imageblit,
592 .fb_blank = pxafb_blank,
595 #ifdef CONFIG_FB_PXA_OVERLAY
596 static void overlay1fb_setup(struct pxafb_layer *ofb)
598 int size = ofb->fb.fix.line_length * ofb->fb.var.yres_virtual;
599 unsigned long start = ofb->video_mem_phys;
600 setup_frame_dma(ofb->fbi, DMA_OV1, PAL_NONE, start, size);
603 /* Depending on the enable status of overlay1/2, the DMA should be
604 * updated from FDADRx (when disabled) or FBRx (when enabled).
606 static void overlay1fb_enable(struct pxafb_layer *ofb)
608 int enabled = lcd_readl(ofb->fbi, OVL1C1) & OVLxC1_OEN;
609 uint32_t fdadr1 = ofb->fbi->fdadr[DMA_OV1] | (enabled ? 0x1 : 0);
611 lcd_writel(ofb->fbi, enabled ? FBR1 : FDADR1, fdadr1);
612 lcd_writel(ofb->fbi, OVL1C2, ofb->control[1]);
613 lcd_writel(ofb->fbi, OVL1C1, ofb->control[0] | OVLxC1_OEN);
616 static void overlay1fb_disable(struct pxafb_layer *ofb)
618 uint32_t lccr5 = lcd_readl(ofb->fbi, LCCR5);
620 lcd_writel(ofb->fbi, OVL1C1, ofb->control[0] & ~OVLxC1_OEN);
622 lcd_writel(ofb->fbi, LCSR1, LCSR1_BS(1));
623 lcd_writel(ofb->fbi, LCCR5, lccr5 & ~LCSR1_BS(1));
624 lcd_writel(ofb->fbi, FBR1, ofb->fbi->fdadr[DMA_OV1] | 0x3);
626 if (wait_for_completion_timeout(&ofb->branch_done, 1 * HZ) == 0)
627 pr_warning("%s: timeout disabling overlay1\n", __func__);
629 lcd_writel(ofb->fbi, LCCR5, lccr5);
632 static void overlay2fb_setup(struct pxafb_layer *ofb)
634 int size, div = 1, pfor = NONSTD_TO_PFOR(ofb->fb.var.nonstd);
635 unsigned long start[3] = { ofb->video_mem_phys, 0, 0 };
637 if (pfor == OVERLAY_FORMAT_RGB || pfor == OVERLAY_FORMAT_YUV444_PACKED) {
638 size = ofb->fb.fix.line_length * ofb->fb.var.yres_virtual;
639 setup_frame_dma(ofb->fbi, DMA_OV2_Y, -1, start[0], size);
641 size = ofb->fb.var.xres_virtual * ofb->fb.var.yres_virtual;
643 case OVERLAY_FORMAT_YUV444_PLANAR: div = 1; break;
644 case OVERLAY_FORMAT_YUV422_PLANAR: div = 2; break;
645 case OVERLAY_FORMAT_YUV420_PLANAR: div = 4; break;
647 start[1] = start[0] + size;
648 start[2] = start[1] + size / div;
649 setup_frame_dma(ofb->fbi, DMA_OV2_Y, -1, start[0], size);
650 setup_frame_dma(ofb->fbi, DMA_OV2_Cb, -1, start[1], size / div);
651 setup_frame_dma(ofb->fbi, DMA_OV2_Cr, -1, start[2], size / div);
655 static void overlay2fb_enable(struct pxafb_layer *ofb)
657 int pfor = NONSTD_TO_PFOR(ofb->fb.var.nonstd);
658 int enabled = lcd_readl(ofb->fbi, OVL2C1) & OVLxC1_OEN;
659 uint32_t fdadr2 = ofb->fbi->fdadr[DMA_OV2_Y] | (enabled ? 0x1 : 0);
660 uint32_t fdadr3 = ofb->fbi->fdadr[DMA_OV2_Cb] | (enabled ? 0x1 : 0);
661 uint32_t fdadr4 = ofb->fbi->fdadr[DMA_OV2_Cr] | (enabled ? 0x1 : 0);
663 if (pfor == OVERLAY_FORMAT_RGB || pfor == OVERLAY_FORMAT_YUV444_PACKED)
664 lcd_writel(ofb->fbi, enabled ? FBR2 : FDADR2, fdadr2);
666 lcd_writel(ofb->fbi, enabled ? FBR2 : FDADR2, fdadr2);
667 lcd_writel(ofb->fbi, enabled ? FBR3 : FDADR3, fdadr3);
668 lcd_writel(ofb->fbi, enabled ? FBR4 : FDADR4, fdadr4);
670 lcd_writel(ofb->fbi, OVL2C2, ofb->control[1]);
671 lcd_writel(ofb->fbi, OVL2C1, ofb->control[0] | OVLxC1_OEN);
674 static void overlay2fb_disable(struct pxafb_layer *ofb)
676 uint32_t lccr5 = lcd_readl(ofb->fbi, LCCR5);
678 lcd_writel(ofb->fbi, OVL2C1, ofb->control[0] & ~OVLxC1_OEN);
680 lcd_writel(ofb->fbi, LCSR1, LCSR1_BS(2));
681 lcd_writel(ofb->fbi, LCCR5, lccr5 & ~LCSR1_BS(2));
682 lcd_writel(ofb->fbi, FBR2, ofb->fbi->fdadr[DMA_OV2_Y] | 0x3);
683 lcd_writel(ofb->fbi, FBR3, ofb->fbi->fdadr[DMA_OV2_Cb] | 0x3);
684 lcd_writel(ofb->fbi, FBR4, ofb->fbi->fdadr[DMA_OV2_Cr] | 0x3);
686 if (wait_for_completion_timeout(&ofb->branch_done, 1 * HZ) == 0)
687 pr_warning("%s: timeout disabling overlay2\n", __func__);
690 static struct pxafb_layer_ops ofb_ops[] = {
692 .enable = overlay1fb_enable,
693 .disable = overlay1fb_disable,
694 .setup = overlay1fb_setup,
697 .enable = overlay2fb_enable,
698 .disable = overlay2fb_disable,
699 .setup = overlay2fb_setup,
703 static int overlayfb_open(struct fb_info *info, int user)
705 struct pxafb_layer *ofb = (struct pxafb_layer *)info;
707 /* no support for framebuffer console on overlay */
711 /* allow only one user at a time */
712 if (atomic_inc_and_test(&ofb->usage))
715 /* unblank the base framebuffer */
716 fb_blank(&ofb->fbi->fb, FB_BLANK_UNBLANK);
720 static int overlayfb_release(struct fb_info *info, int user)
722 struct pxafb_layer *ofb = (struct pxafb_layer*) info;
724 atomic_dec(&ofb->usage);
725 ofb->ops->disable(ofb);
727 free_pages_exact(ofb->video_mem, ofb->video_mem_size);
728 ofb->video_mem = NULL;
729 ofb->video_mem_size = 0;
733 static int overlayfb_check_var(struct fb_var_screeninfo *var,
734 struct fb_info *info)
736 struct pxafb_layer *ofb = (struct pxafb_layer *)info;
737 struct fb_var_screeninfo *base_var = &ofb->fbi->fb.var;
738 int xpos, ypos, pfor, bpp;
740 xpos = NONSTD_TO_XPOS(var->nonstd);
741 ypos = NONSTD_TO_XPOS(var->nonstd);
742 pfor = NONSTD_TO_PFOR(var->nonstd);
744 bpp = pxafb_var_to_bpp(var);
748 /* no support for YUV format on overlay1 */
749 if (ofb->id == OVERLAY1 && pfor != 0)
752 /* for YUV packed formats, bpp = 'minimum bpp of YUV components' */
754 case OVERLAY_FORMAT_RGB:
755 bpp = pxafb_var_to_bpp(var);
759 pxafb_set_pixfmt(var, var_to_depth(var));
761 case OVERLAY_FORMAT_YUV444_PACKED: bpp = 24; break;
762 case OVERLAY_FORMAT_YUV444_PLANAR: bpp = 8; break;
763 case OVERLAY_FORMAT_YUV422_PLANAR: bpp = 4; break;
764 case OVERLAY_FORMAT_YUV420_PLANAR: bpp = 2; break;
769 /* each line must start at a 32-bit word boundary */
770 if ((xpos * bpp) % 32)
773 /* xres must align on 32-bit word boundary */
774 var->xres = roundup(var->xres * bpp, 32) / bpp;
776 if ((xpos + var->xres > base_var->xres) ||
777 (ypos + var->yres > base_var->yres))
780 var->xres_virtual = var->xres;
781 var->yres_virtual = max(var->yres, var->yres_virtual);
785 static int overlayfb_map_video_memory(struct pxafb_layer *ofb)
787 struct fb_var_screeninfo *var = &ofb->fb.var;
788 int pfor = NONSTD_TO_PFOR(var->nonstd);
792 case OVERLAY_FORMAT_RGB: bpp = var->bits_per_pixel; break;
793 case OVERLAY_FORMAT_YUV444_PACKED: bpp = 24; break;
794 case OVERLAY_FORMAT_YUV444_PLANAR: bpp = 24; break;
795 case OVERLAY_FORMAT_YUV422_PLANAR: bpp = 16; break;
796 case OVERLAY_FORMAT_YUV420_PLANAR: bpp = 12; break;
799 ofb->fb.fix.line_length = var->xres_virtual * bpp / 8;
801 size = PAGE_ALIGN(ofb->fb.fix.line_length * var->yres_virtual);
803 /* don't re-allocate if the original video memory is enough */
804 if (ofb->video_mem) {
805 if (ofb->video_mem_size >= size)
808 free_pages_exact(ofb->video_mem, ofb->video_mem_size);
811 ofb->video_mem = alloc_pages_exact(size, GFP_KERNEL | __GFP_ZERO);
812 if (ofb->video_mem == NULL)
815 ofb->video_mem_phys = virt_to_phys(ofb->video_mem);
816 ofb->video_mem_size = size;
818 ofb->fb.fix.smem_start = ofb->video_mem_phys;
819 ofb->fb.fix.smem_len = ofb->fb.fix.line_length * var->yres_virtual;
820 ofb->fb.screen_base = ofb->video_mem;
824 static int overlayfb_set_par(struct fb_info *info)
826 struct pxafb_layer *ofb = (struct pxafb_layer *)info;
827 struct fb_var_screeninfo *var = &info->var;
828 int xpos, ypos, pfor, bpp, ret;
830 ret = overlayfb_map_video_memory(ofb);
834 bpp = pxafb_var_to_bpp(var);
835 xpos = NONSTD_TO_XPOS(var->nonstd);
836 ypos = NONSTD_TO_XPOS(var->nonstd);
837 pfor = NONSTD_TO_PFOR(var->nonstd);
839 ofb->control[0] = OVLxC1_PPL(var->xres) | OVLxC1_LPO(var->yres) |
841 ofb->control[1] = OVLxC2_XPOS(xpos) | OVLxC2_YPOS(ypos);
843 if (ofb->id == OVERLAY2)
844 ofb->control[1] |= OVL2C2_PFOR(pfor);
846 ofb->ops->setup(ofb);
847 ofb->ops->enable(ofb);
851 static struct fb_ops overlay_fb_ops = {
852 .owner = THIS_MODULE,
853 .fb_open = overlayfb_open,
854 .fb_release = overlayfb_release,
855 .fb_check_var = overlayfb_check_var,
856 .fb_set_par = overlayfb_set_par,
859 static void __devinit init_pxafb_overlay(struct pxafb_info *fbi,
860 struct pxafb_layer *ofb, int id)
862 sprintf(ofb->fb.fix.id, "overlay%d", id + 1);
864 ofb->fb.fix.type = FB_TYPE_PACKED_PIXELS;
865 ofb->fb.fix.xpanstep = 0;
866 ofb->fb.fix.ypanstep = 1;
868 ofb->fb.var.activate = FB_ACTIVATE_NOW;
869 ofb->fb.var.height = -1;
870 ofb->fb.var.width = -1;
871 ofb->fb.var.vmode = FB_VMODE_NONINTERLACED;
873 ofb->fb.fbops = &overlay_fb_ops;
874 ofb->fb.flags = FBINFO_FLAG_DEFAULT;
876 ofb->fb.pseudo_palette = NULL;
879 ofb->ops = &ofb_ops[id];
880 atomic_set(&ofb->usage, 0);
882 init_completion(&ofb->branch_done);
885 static int __devinit pxafb_overlay_init(struct pxafb_info *fbi)
889 for (i = 0; i < 2; i++) {
890 init_pxafb_overlay(fbi, &fbi->overlay[i], i);
891 ret = register_framebuffer(&fbi->overlay[i].fb);
893 dev_err(fbi->dev, "failed to register overlay %d\n", i);
898 /* mask all IU/BS/EOF/SOF interrupts */
899 lcd_writel(fbi, LCCR5, ~0);
901 /* place overlay(s) on top of base */
902 fbi->lccr0 |= LCCR0_OUC;
903 pr_info("PXA Overlay driver loaded successfully!\n");
907 static void __devexit pxafb_overlay_exit(struct pxafb_info *fbi)
911 for (i = 0; i < 2; i++)
912 unregister_framebuffer(&fbi->overlay[i].fb);
915 static inline void pxafb_overlay_init(struct pxafb_info *fbi) {}
916 static inline void pxafb_overlay_exit(struct pxafb_info *fbi) {}
917 #endif /* CONFIG_FB_PXA_OVERLAY */
920 * Calculate the PCD value from the clock rate (in picoseconds).
921 * We take account of the PPCR clock setting.
922 * From PXA Developer's Manual:
933 * LCLK = LCD/Memory Clock
936 * PixelClock here is in Hz while the pixclock argument given is the
937 * period in picoseconds. Hence PixelClock = 1 / ( pixclock * 10^-12 )
939 * The function get_lclk_frequency_10khz returns LCLK in units of
940 * 10khz. Calling the result of this function lclk gives us the
943 * PCD = (lclk * 10^4 ) * ( pixclock * 10^-12 )
944 * -------------------------------------- - 1
947 * Factoring the 10^4 and 10^-12 out gives 10^-8 == 1 / 100000000 as used below.
949 static inline unsigned int get_pcd(struct pxafb_info *fbi,
950 unsigned int pixclock)
952 unsigned long long pcd;
954 /* FIXME: Need to take into account Double Pixel Clock mode
955 * (DPC) bit? or perhaps set it based on the various clock
957 pcd = (unsigned long long)(clk_get_rate(fbi->clk) / 10000);
959 do_div(pcd, 100000000 * 2);
960 /* no need for this, since we should subtract 1 anyway. they cancel */
961 /* pcd += 1; */ /* make up for integer math truncations */
962 return (unsigned int)pcd;
966 * Some touchscreens need hsync information from the video driver to
967 * function correctly. We export it here. Note that 'hsync_time' and
968 * the value returned from pxafb_get_hsync_time() is the *reciprocal*
969 * of the hsync period in seconds.
971 static inline void set_hsync_time(struct pxafb_info *fbi, unsigned int pcd)
975 if ((pcd == 0) || (fbi->fb.var.hsync_len == 0)) {
980 htime = clk_get_rate(fbi->clk) / (pcd * fbi->fb.var.hsync_len);
982 fbi->hsync_time = htime;
985 unsigned long pxafb_get_hsync_time(struct device *dev)
987 struct pxafb_info *fbi = dev_get_drvdata(dev);
989 /* If display is blanked/suspended, hsync isn't active */
990 if (!fbi || (fbi->state != C_ENABLE))
993 return fbi->hsync_time;
995 EXPORT_SYMBOL(pxafb_get_hsync_time);
997 static int setup_frame_dma(struct pxafb_info *fbi, int dma, int pal,
998 unsigned long start, size_t size)
1000 struct pxafb_dma_descriptor *dma_desc, *pal_desc;
1001 unsigned int dma_desc_off, pal_desc_off;
1003 if (dma < 0 || dma >= DMA_MAX * 2)
1006 dma_desc = &fbi->dma_buff->dma_desc[dma];
1007 dma_desc_off = offsetof(struct pxafb_dma_buff, dma_desc[dma]);
1009 dma_desc->fsadr = start;
1011 dma_desc->ldcmd = size;
1013 if (pal < 0 || pal >= PAL_MAX * 2) {
1014 dma_desc->fdadr = fbi->dma_buff_phys + dma_desc_off;
1015 fbi->fdadr[dma] = fbi->dma_buff_phys + dma_desc_off;
1017 pal_desc = &fbi->dma_buff->pal_desc[pal];
1018 pal_desc_off = offsetof(struct pxafb_dma_buff, pal_desc[pal]);
1020 pal_desc->fsadr = fbi->dma_buff_phys + pal * PALETTE_SIZE;
1023 if ((fbi->lccr4 & LCCR4_PAL_FOR_MASK) == LCCR4_PAL_FOR_0)
1024 pal_desc->ldcmd = fbi->palette_size * sizeof(u16);
1026 pal_desc->ldcmd = fbi->palette_size * sizeof(u32);
1028 pal_desc->ldcmd |= LDCMD_PAL;
1030 /* flip back and forth between palette and frame buffer */
1031 pal_desc->fdadr = fbi->dma_buff_phys + dma_desc_off;
1032 dma_desc->fdadr = fbi->dma_buff_phys + pal_desc_off;
1033 fbi->fdadr[dma] = fbi->dma_buff_phys + dma_desc_off;
1039 static void setup_base_frame(struct pxafb_info *fbi, int branch)
1041 struct fb_var_screeninfo *var = &fbi->fb.var;
1042 struct fb_fix_screeninfo *fix = &fbi->fb.fix;
1043 int nbytes, dma, pal, bpp = var->bits_per_pixel;
1044 unsigned long offset;
1046 dma = DMA_BASE + (branch ? DMA_MAX : 0);
1047 pal = (bpp >= 16) ? PAL_NONE : PAL_BASE + (branch ? PAL_MAX : 0);
1049 nbytes = fix->line_length * var->yres;
1050 offset = fix->line_length * var->yoffset + fbi->video_mem_phys;
1052 if (fbi->lccr0 & LCCR0_SDS) {
1053 nbytes = nbytes / 2;
1054 setup_frame_dma(fbi, dma + 1, PAL_NONE, offset + nbytes, nbytes);
1057 setup_frame_dma(fbi, dma, pal, offset, nbytes);
1060 #ifdef CONFIG_FB_PXA_SMARTPANEL
1061 static int setup_smart_dma(struct pxafb_info *fbi)
1063 struct pxafb_dma_descriptor *dma_desc;
1064 unsigned long dma_desc_off, cmd_buff_off;
1066 dma_desc = &fbi->dma_buff->dma_desc[DMA_CMD];
1067 dma_desc_off = offsetof(struct pxafb_dma_buff, dma_desc[DMA_CMD]);
1068 cmd_buff_off = offsetof(struct pxafb_dma_buff, cmd_buff);
1070 dma_desc->fdadr = fbi->dma_buff_phys + dma_desc_off;
1071 dma_desc->fsadr = fbi->dma_buff_phys + cmd_buff_off;
1073 dma_desc->ldcmd = fbi->n_smart_cmds * sizeof(uint16_t);
1075 fbi->fdadr[DMA_CMD] = dma_desc->fdadr;
1079 int pxafb_smart_flush(struct fb_info *info)
1081 struct pxafb_info *fbi = container_of(info, struct pxafb_info, fb);
1085 /* disable controller until all registers are set up */
1086 lcd_writel(fbi, LCCR0, fbi->reg_lccr0 & ~LCCR0_ENB);
1088 /* 1. make it an even number of commands to align on 32-bit boundary
1089 * 2. add the interrupt command to the end of the chain so we can
1090 * keep track of the end of the transfer
1093 while (fbi->n_smart_cmds & 1)
1094 fbi->smart_cmds[fbi->n_smart_cmds++] = SMART_CMD_NOOP;
1096 fbi->smart_cmds[fbi->n_smart_cmds++] = SMART_CMD_INTERRUPT;
1097 fbi->smart_cmds[fbi->n_smart_cmds++] = SMART_CMD_WAIT_FOR_VSYNC;
1098 setup_smart_dma(fbi);
1100 /* continue to execute next command */
1101 prsr = lcd_readl(fbi, PRSR) | PRSR_ST_OK | PRSR_CON_NT;
1102 lcd_writel(fbi, PRSR, prsr);
1104 /* stop the processor in case it executed "wait for sync" cmd */
1105 lcd_writel(fbi, CMDCR, 0x0001);
1107 /* don't send interrupts for fifo underruns on channel 6 */
1108 lcd_writel(fbi, LCCR5, LCCR5_IUM(6));
1110 lcd_writel(fbi, LCCR1, fbi->reg_lccr1);
1111 lcd_writel(fbi, LCCR2, fbi->reg_lccr2);
1112 lcd_writel(fbi, LCCR3, fbi->reg_lccr3);
1113 lcd_writel(fbi, LCCR4, fbi->reg_lccr4);
1114 lcd_writel(fbi, FDADR0, fbi->fdadr[0]);
1115 lcd_writel(fbi, FDADR6, fbi->fdadr[6]);
1118 lcd_writel(fbi, LCCR0, fbi->reg_lccr0 | LCCR0_ENB);
1120 if (wait_for_completion_timeout(&fbi->command_done, HZ/2) == 0) {
1121 pr_warning("%s: timeout waiting for command done\n",
1127 prsr = lcd_readl(fbi, PRSR) & ~(PRSR_ST_OK | PRSR_CON_NT);
1128 lcd_writel(fbi, PRSR, prsr);
1129 lcd_writel(fbi, LCCR0, fbi->reg_lccr0 & ~LCCR0_ENB);
1130 lcd_writel(fbi, FDADR6, 0);
1131 fbi->n_smart_cmds = 0;
1135 int pxafb_smart_queue(struct fb_info *info, uint16_t *cmds, int n_cmds)
1138 struct pxafb_info *fbi = container_of(info, struct pxafb_info, fb);
1140 for (i = 0; i < n_cmds; i++, cmds++) {
1141 /* if it is a software delay, flush and delay */
1142 if ((*cmds & 0xff00) == SMART_CMD_DELAY) {
1143 pxafb_smart_flush(info);
1144 mdelay(*cmds & 0xff);
1148 /* leave 2 commands for INTERRUPT and WAIT_FOR_SYNC */
1149 if (fbi->n_smart_cmds == CMD_BUFF_SIZE - 8)
1150 pxafb_smart_flush(info);
1152 fbi->smart_cmds[fbi->n_smart_cmds++] = *cmds;
1158 static unsigned int __smart_timing(unsigned time_ns, unsigned long lcd_clk)
1160 unsigned int t = (time_ns * (lcd_clk / 1000000) / 1000);
1161 return (t == 0) ? 1 : t;
1164 static void setup_smart_timing(struct pxafb_info *fbi,
1165 struct fb_var_screeninfo *var)
1167 struct pxafb_mach_info *inf = fbi->dev->platform_data;
1168 struct pxafb_mode_info *mode = &inf->modes[0];
1169 unsigned long lclk = clk_get_rate(fbi->clk);
1170 unsigned t1, t2, t3, t4;
1172 t1 = max(mode->a0csrd_set_hld, mode->a0cswr_set_hld);
1173 t2 = max(mode->rd_pulse_width, mode->wr_pulse_width);
1174 t3 = mode->op_hold_time;
1175 t4 = mode->cmd_inh_time;
1178 LCCR1_DisWdth(var->xres) |
1179 LCCR1_BegLnDel(__smart_timing(t1, lclk)) |
1180 LCCR1_EndLnDel(__smart_timing(t2, lclk)) |
1181 LCCR1_HorSnchWdth(__smart_timing(t3, lclk));
1183 fbi->reg_lccr2 = LCCR2_DisHght(var->yres);
1184 fbi->reg_lccr3 = fbi->lccr3 | LCCR3_PixClkDiv(__smart_timing(t4, lclk));
1185 fbi->reg_lccr3 |= (var->sync & FB_SYNC_HOR_HIGH_ACT) ? LCCR3_HSP : 0;
1186 fbi->reg_lccr3 |= (var->sync & FB_SYNC_VERT_HIGH_ACT) ? LCCR3_VSP : 0;
1188 /* FIXME: make this configurable */
1192 static int pxafb_smart_thread(void *arg)
1194 struct pxafb_info *fbi = arg;
1195 struct pxafb_mach_info *inf = fbi->dev->platform_data;
1197 if (!fbi || !inf->smart_update) {
1198 pr_err("%s: not properly initialized, thread terminated\n",
1203 pr_debug("%s(): task starting\n", __func__);
1206 while (!kthread_should_stop()) {
1208 if (try_to_freeze())
1211 mutex_lock(&fbi->ctrlr_lock);
1213 if (fbi->state == C_ENABLE) {
1214 inf->smart_update(&fbi->fb);
1215 complete(&fbi->refresh_done);
1218 mutex_unlock(&fbi->ctrlr_lock);
1220 set_current_state(TASK_INTERRUPTIBLE);
1221 schedule_timeout(30 * HZ / 1000);
1224 pr_debug("%s(): task ending\n", __func__);
1228 static int pxafb_smart_init(struct pxafb_info *fbi)
1230 if (!(fbi->lccr0 & LCCR0_LCDT))
1233 fbi->smart_cmds = (uint16_t *) fbi->dma_buff->cmd_buff;
1234 fbi->n_smart_cmds = 0;
1236 init_completion(&fbi->command_done);
1237 init_completion(&fbi->refresh_done);
1239 fbi->smart_thread = kthread_run(pxafb_smart_thread, fbi,
1241 if (IS_ERR(fbi->smart_thread)) {
1242 pr_err("%s: unable to create kernel thread\n", __func__);
1243 return PTR_ERR(fbi->smart_thread);
1249 int pxafb_smart_queue(struct fb_info *info, uint16_t *cmds, int n_cmds)
1254 int pxafb_smart_flush(struct fb_info *info)
1259 static inline int pxafb_smart_init(struct pxafb_info *fbi) { return 0; }
1260 #endif /* CONFIG_FB_PXA_SMARTPANEL */
1262 static void setup_parallel_timing(struct pxafb_info *fbi,
1263 struct fb_var_screeninfo *var)
1265 unsigned int lines_per_panel, pcd = get_pcd(fbi, var->pixclock);
1268 LCCR1_DisWdth(var->xres) +
1269 LCCR1_HorSnchWdth(var->hsync_len) +
1270 LCCR1_BegLnDel(var->left_margin) +
1271 LCCR1_EndLnDel(var->right_margin);
1274 * If we have a dual scan LCD, we need to halve
1275 * the YRES parameter.
1277 lines_per_panel = var->yres;
1278 if ((fbi->lccr0 & LCCR0_SDS) == LCCR0_Dual)
1279 lines_per_panel /= 2;
1282 LCCR2_DisHght(lines_per_panel) +
1283 LCCR2_VrtSnchWdth(var->vsync_len) +
1284 LCCR2_BegFrmDel(var->upper_margin) +
1285 LCCR2_EndFrmDel(var->lower_margin);
1287 fbi->reg_lccr3 = fbi->lccr3 |
1288 (var->sync & FB_SYNC_HOR_HIGH_ACT ?
1289 LCCR3_HorSnchH : LCCR3_HorSnchL) |
1290 (var->sync & FB_SYNC_VERT_HIGH_ACT ?
1291 LCCR3_VrtSnchH : LCCR3_VrtSnchL);
1294 fbi->reg_lccr3 |= LCCR3_PixClkDiv(pcd);
1295 set_hsync_time(fbi, pcd);
1300 * pxafb_activate_var():
1301 * Configures LCD Controller based on entries in var parameter.
1302 * Settings are only written to the controller if changes were made.
1304 static int pxafb_activate_var(struct fb_var_screeninfo *var,
1305 struct pxafb_info *fbi)
1309 /* Update shadow copy atomically */
1310 local_irq_save(flags);
1312 #ifdef CONFIG_FB_PXA_SMARTPANEL
1313 if (fbi->lccr0 & LCCR0_LCDT)
1314 setup_smart_timing(fbi, var);
1317 setup_parallel_timing(fbi, var);
1319 setup_base_frame(fbi, 0);
1321 fbi->reg_lccr0 = fbi->lccr0 |
1322 (LCCR0_LDM | LCCR0_SFM | LCCR0_IUM | LCCR0_EFM |
1323 LCCR0_QDM | LCCR0_BM | LCCR0_OUM);
1325 fbi->reg_lccr3 |= pxafb_var_to_lccr3(var);
1327 fbi->reg_lccr4 = lcd_readl(fbi, LCCR4) & ~LCCR4_PAL_FOR_MASK;
1328 fbi->reg_lccr4 |= (fbi->lccr4 & LCCR4_PAL_FOR_MASK);
1329 local_irq_restore(flags);
1332 * Only update the registers if the controller is enabled
1333 * and something has changed.
1335 if ((lcd_readl(fbi, LCCR0) != fbi->reg_lccr0) ||
1336 (lcd_readl(fbi, LCCR1) != fbi->reg_lccr1) ||
1337 (lcd_readl(fbi, LCCR2) != fbi->reg_lccr2) ||
1338 (lcd_readl(fbi, LCCR3) != fbi->reg_lccr3) ||
1339 (lcd_readl(fbi, LCCR4) != fbi->reg_lccr4) ||
1340 (lcd_readl(fbi, FDADR0) != fbi->fdadr[0]) ||
1341 (lcd_readl(fbi, FDADR1) != fbi->fdadr[1]))
1342 pxafb_schedule_work(fbi, C_REENABLE);
1348 * NOTE! The following functions are purely helpers for set_ctrlr_state.
1349 * Do not call them directly; set_ctrlr_state does the correct serialisation
1350 * to ensure that things happen in the right way 100% of time time.
1353 static inline void __pxafb_backlight_power(struct pxafb_info *fbi, int on)
1355 pr_debug("pxafb: backlight o%s\n", on ? "n" : "ff");
1357 if (fbi->backlight_power)
1358 fbi->backlight_power(on);
1361 static inline void __pxafb_lcd_power(struct pxafb_info *fbi, int on)
1363 pr_debug("pxafb: LCD power o%s\n", on ? "n" : "ff");
1366 fbi->lcd_power(on, &fbi->fb.var);
1369 static void pxafb_enable_controller(struct pxafb_info *fbi)
1371 pr_debug("pxafb: Enabling LCD controller\n");
1372 pr_debug("fdadr0 0x%08x\n", (unsigned int) fbi->fdadr[0]);
1373 pr_debug("fdadr1 0x%08x\n", (unsigned int) fbi->fdadr[1]);
1374 pr_debug("reg_lccr0 0x%08x\n", (unsigned int) fbi->reg_lccr0);
1375 pr_debug("reg_lccr1 0x%08x\n", (unsigned int) fbi->reg_lccr1);
1376 pr_debug("reg_lccr2 0x%08x\n", (unsigned int) fbi->reg_lccr2);
1377 pr_debug("reg_lccr3 0x%08x\n", (unsigned int) fbi->reg_lccr3);
1379 /* enable LCD controller clock */
1380 clk_enable(fbi->clk);
1382 if (fbi->lccr0 & LCCR0_LCDT)
1385 /* Sequence from 11.7.10 */
1386 lcd_writel(fbi, LCCR4, fbi->reg_lccr4);
1387 lcd_writel(fbi, LCCR3, fbi->reg_lccr3);
1388 lcd_writel(fbi, LCCR2, fbi->reg_lccr2);
1389 lcd_writel(fbi, LCCR1, fbi->reg_lccr1);
1390 lcd_writel(fbi, LCCR0, fbi->reg_lccr0 & ~LCCR0_ENB);
1392 lcd_writel(fbi, FDADR0, fbi->fdadr[0]);
1393 lcd_writel(fbi, FDADR1, fbi->fdadr[1]);
1394 lcd_writel(fbi, LCCR0, fbi->reg_lccr0 | LCCR0_ENB);
1397 static void pxafb_disable_controller(struct pxafb_info *fbi)
1401 #ifdef CONFIG_FB_PXA_SMARTPANEL
1402 if (fbi->lccr0 & LCCR0_LCDT) {
1403 wait_for_completion_timeout(&fbi->refresh_done,
1409 /* Clear LCD Status Register */
1410 lcd_writel(fbi, LCSR, 0xffffffff);
1412 lccr0 = lcd_readl(fbi, LCCR0) & ~LCCR0_LDM;
1413 lcd_writel(fbi, LCCR0, lccr0);
1414 lcd_writel(fbi, LCCR0, lccr0 | LCCR0_DIS);
1416 wait_for_completion_timeout(&fbi->disable_done, 200 * HZ / 1000);
1418 /* disable LCD controller clock */
1419 clk_disable(fbi->clk);
1423 * pxafb_handle_irq: Handle 'LCD DONE' interrupts.
1425 static irqreturn_t pxafb_handle_irq(int irq, void *dev_id)
1427 struct pxafb_info *fbi = dev_id;
1428 unsigned int lccr0, lcsr, lcsr1;
1430 lcsr = lcd_readl(fbi, LCSR);
1431 if (lcsr & LCSR_LDD) {
1432 lccr0 = lcd_readl(fbi, LCCR0);
1433 lcd_writel(fbi, LCCR0, lccr0 | LCCR0_LDM);
1434 complete(&fbi->disable_done);
1437 #ifdef CONFIG_FB_PXA_SMARTPANEL
1438 if (lcsr & LCSR_CMD_INT)
1439 complete(&fbi->command_done);
1441 lcd_writel(fbi, LCSR, lcsr);
1443 #ifdef CONFIG_FB_PXA_OVERLAY
1444 lcsr1 = lcd_readl(fbi, LCSR1);
1445 if (lcsr1 & LCSR1_BS(1))
1446 complete(&fbi->overlay[0].branch_done);
1448 if (lcsr1 & LCSR1_BS(2))
1449 complete(&fbi->overlay[1].branch_done);
1451 lcd_writel(fbi, LCSR1, lcsr1);
1457 * This function must be called from task context only, since it will
1458 * sleep when disabling the LCD controller, or if we get two contending
1459 * processes trying to alter state.
1461 static void set_ctrlr_state(struct pxafb_info *fbi, u_int state)
1465 mutex_lock(&fbi->ctrlr_lock);
1467 old_state = fbi->state;
1470 * Hack around fbcon initialisation.
1472 if (old_state == C_STARTUP && state == C_REENABLE)
1476 case C_DISABLE_CLKCHANGE:
1478 * Disable controller for clock change. If the
1479 * controller is already disabled, then do nothing.
1481 if (old_state != C_DISABLE && old_state != C_DISABLE_PM) {
1483 /* TODO __pxafb_lcd_power(fbi, 0); */
1484 pxafb_disable_controller(fbi);
1491 * Disable controller
1493 if (old_state != C_DISABLE) {
1495 __pxafb_backlight_power(fbi, 0);
1496 __pxafb_lcd_power(fbi, 0);
1497 if (old_state != C_DISABLE_CLKCHANGE)
1498 pxafb_disable_controller(fbi);
1502 case C_ENABLE_CLKCHANGE:
1504 * Enable the controller after clock change. Only
1505 * do this if we were disabled for the clock change.
1507 if (old_state == C_DISABLE_CLKCHANGE) {
1508 fbi->state = C_ENABLE;
1509 pxafb_enable_controller(fbi);
1510 /* TODO __pxafb_lcd_power(fbi, 1); */
1516 * Re-enable the controller only if it was already
1517 * enabled. This is so we reprogram the control
1520 if (old_state == C_ENABLE) {
1521 __pxafb_lcd_power(fbi, 0);
1522 pxafb_disable_controller(fbi);
1523 pxafb_enable_controller(fbi);
1524 __pxafb_lcd_power(fbi, 1);
1530 * Re-enable the controller after PM. This is not
1531 * perfect - think about the case where we were doing
1532 * a clock change, and we suspended half-way through.
1534 if (old_state != C_DISABLE_PM)
1540 * Power up the LCD screen, enable controller, and
1541 * turn on the backlight.
1543 if (old_state != C_ENABLE) {
1544 fbi->state = C_ENABLE;
1545 pxafb_enable_controller(fbi);
1546 __pxafb_lcd_power(fbi, 1);
1547 __pxafb_backlight_power(fbi, 1);
1551 mutex_unlock(&fbi->ctrlr_lock);
1555 * Our LCD controller task (which is called when we blank or unblank)
1558 static void pxafb_task(struct work_struct *work)
1560 struct pxafb_info *fbi =
1561 container_of(work, struct pxafb_info, task);
1562 u_int state = xchg(&fbi->task_state, -1);
1564 set_ctrlr_state(fbi, state);
1567 #ifdef CONFIG_CPU_FREQ
1569 * CPU clock speed change handler. We need to adjust the LCD timing
1570 * parameters when the CPU clock is adjusted by the power management
1573 * TODO: Determine why f->new != 10*get_lclk_frequency_10khz()
1576 pxafb_freq_transition(struct notifier_block *nb, unsigned long val, void *data)
1578 struct pxafb_info *fbi = TO_INF(nb, freq_transition);
1579 /* TODO struct cpufreq_freqs *f = data; */
1583 case CPUFREQ_PRECHANGE:
1584 set_ctrlr_state(fbi, C_DISABLE_CLKCHANGE);
1587 case CPUFREQ_POSTCHANGE:
1588 pcd = get_pcd(fbi, fbi->fb.var.pixclock);
1589 set_hsync_time(fbi, pcd);
1590 fbi->reg_lccr3 = (fbi->reg_lccr3 & ~0xff) |
1591 LCCR3_PixClkDiv(pcd);
1592 set_ctrlr_state(fbi, C_ENABLE_CLKCHANGE);
1599 pxafb_freq_policy(struct notifier_block *nb, unsigned long val, void *data)
1601 struct pxafb_info *fbi = TO_INF(nb, freq_policy);
1602 struct fb_var_screeninfo *var = &fbi->fb.var;
1603 struct cpufreq_policy *policy = data;
1606 case CPUFREQ_ADJUST:
1607 case CPUFREQ_INCOMPATIBLE:
1608 pr_debug("min dma period: %d ps, "
1609 "new clock %d kHz\n", pxafb_display_dma_period(var),
1611 /* TODO: fill in min/max values */
1620 * Power management hooks. Note that we won't be called from IRQ context,
1621 * unlike the blank functions above, so we may sleep.
1623 static int pxafb_suspend(struct platform_device *dev, pm_message_t state)
1625 struct pxafb_info *fbi = platform_get_drvdata(dev);
1627 set_ctrlr_state(fbi, C_DISABLE_PM);
1631 static int pxafb_resume(struct platform_device *dev)
1633 struct pxafb_info *fbi = platform_get_drvdata(dev);
1635 set_ctrlr_state(fbi, C_ENABLE_PM);
1639 #define pxafb_suspend NULL
1640 #define pxafb_resume NULL
1643 static int __devinit pxafb_init_video_memory(struct pxafb_info *fbi)
1645 int size = PAGE_ALIGN(fbi->video_mem_size);
1647 fbi->video_mem = alloc_pages_exact(size, GFP_KERNEL | __GFP_ZERO);
1648 if (fbi->video_mem == NULL)
1651 fbi->video_mem_phys = virt_to_phys(fbi->video_mem);
1652 fbi->video_mem_size = size;
1654 fbi->fb.fix.smem_start = fbi->video_mem_phys;
1655 fbi->fb.fix.smem_len = fbi->video_mem_size;
1656 fbi->fb.screen_base = fbi->video_mem;
1658 return fbi->video_mem ? 0 : -ENOMEM;
1661 static void pxafb_decode_mach_info(struct pxafb_info *fbi,
1662 struct pxafb_mach_info *inf)
1664 unsigned int lcd_conn = inf->lcd_conn;
1665 struct pxafb_mode_info *m;
1668 fbi->cmap_inverse = inf->cmap_inverse;
1669 fbi->cmap_static = inf->cmap_static;
1670 fbi->lccr4 = inf->lccr4;
1672 switch (lcd_conn & LCD_TYPE_MASK) {
1673 case LCD_TYPE_MONO_STN:
1674 fbi->lccr0 = LCCR0_CMS;
1676 case LCD_TYPE_MONO_DSTN:
1677 fbi->lccr0 = LCCR0_CMS | LCCR0_SDS;
1679 case LCD_TYPE_COLOR_STN:
1682 case LCD_TYPE_COLOR_DSTN:
1683 fbi->lccr0 = LCCR0_SDS;
1685 case LCD_TYPE_COLOR_TFT:
1686 fbi->lccr0 = LCCR0_PAS;
1688 case LCD_TYPE_SMART_PANEL:
1689 fbi->lccr0 = LCCR0_LCDT | LCCR0_PAS;
1692 /* fall back to backward compatibility way */
1693 fbi->lccr0 = inf->lccr0;
1694 fbi->lccr3 = inf->lccr3;
1698 if (lcd_conn == LCD_MONO_STN_8BPP)
1699 fbi->lccr0 |= LCCR0_DPD;
1701 fbi->lccr0 |= (lcd_conn & LCD_ALTERNATE_MAPPING) ? LCCR0_LDDALT : 0;
1703 fbi->lccr3 = LCCR3_Acb((inf->lcd_conn >> 10) & 0xff);
1704 fbi->lccr3 |= (lcd_conn & LCD_BIAS_ACTIVE_LOW) ? LCCR3_OEP : 0;
1705 fbi->lccr3 |= (lcd_conn & LCD_PCLK_EDGE_FALL) ? LCCR3_PCP : 0;
1708 pxafb_setmode(&fbi->fb.var, &inf->modes[0]);
1710 /* decide video memory size as follows:
1711 * 1. default to mode of maximum resolution
1712 * 2. allow platform to override
1713 * 3. allow module parameter to override
1715 for (i = 0, m = &inf->modes[0]; i < inf->num_modes; i++, m++)
1716 fbi->video_mem_size = max_t(size_t, fbi->video_mem_size,
1717 m->xres * m->yres * m->bpp / 8);
1719 if (inf->video_mem_size > fbi->video_mem_size)
1720 fbi->video_mem_size = inf->video_mem_size;
1722 if (video_mem_size > fbi->video_mem_size)
1723 fbi->video_mem_size = video_mem_size;
1726 static struct pxafb_info * __devinit pxafb_init_fbinfo(struct device *dev)
1728 struct pxafb_info *fbi;
1730 struct pxafb_mach_info *inf = dev->platform_data;
1732 /* Alloc the pxafb_info and pseudo_palette in one step */
1733 fbi = kmalloc(sizeof(struct pxafb_info) + sizeof(u32) * 16, GFP_KERNEL);
1737 memset(fbi, 0, sizeof(struct pxafb_info));
1740 fbi->clk = clk_get(dev, NULL);
1741 if (IS_ERR(fbi->clk)) {
1746 strcpy(fbi->fb.fix.id, PXA_NAME);
1748 fbi->fb.fix.type = FB_TYPE_PACKED_PIXELS;
1749 fbi->fb.fix.type_aux = 0;
1750 fbi->fb.fix.xpanstep = 0;
1751 fbi->fb.fix.ypanstep = 1;
1752 fbi->fb.fix.ywrapstep = 0;
1753 fbi->fb.fix.accel = FB_ACCEL_NONE;
1755 fbi->fb.var.nonstd = 0;
1756 fbi->fb.var.activate = FB_ACTIVATE_NOW;
1757 fbi->fb.var.height = -1;
1758 fbi->fb.var.width = -1;
1759 fbi->fb.var.accel_flags = FB_ACCELF_TEXT;
1760 fbi->fb.var.vmode = FB_VMODE_NONINTERLACED;
1762 fbi->fb.fbops = &pxafb_ops;
1763 fbi->fb.flags = FBINFO_DEFAULT;
1767 addr = addr + sizeof(struct pxafb_info);
1768 fbi->fb.pseudo_palette = addr;
1770 fbi->state = C_STARTUP;
1771 fbi->task_state = (u_char)-1;
1773 pxafb_decode_mach_info(fbi, inf);
1775 init_waitqueue_head(&fbi->ctrlr_wait);
1776 INIT_WORK(&fbi->task, pxafb_task);
1777 mutex_init(&fbi->ctrlr_lock);
1778 init_completion(&fbi->disable_done);
1783 #ifdef CONFIG_FB_PXA_PARAMETERS
1784 static int __devinit parse_opt_mode(struct device *dev, const char *this_opt)
1786 struct pxafb_mach_info *inf = dev->platform_data;
1788 const char *name = this_opt+5;
1789 unsigned int namelen = strlen(name);
1790 int res_specified = 0, bpp_specified = 0;
1791 unsigned int xres = 0, yres = 0, bpp = 0;
1792 int yres_specified = 0;
1794 for (i = namelen-1; i >= 0; i--) {
1798 if (!bpp_specified && !yres_specified) {
1799 bpp = simple_strtoul(&name[i+1], NULL, 0);
1805 if (!yres_specified) {
1806 yres = simple_strtoul(&name[i+1], NULL, 0);
1817 if (i < 0 && yres_specified) {
1818 xres = simple_strtoul(name, NULL, 0);
1822 if (res_specified) {
1823 dev_info(dev, "overriding resolution: %dx%d\n", xres, yres);
1824 inf->modes[0].xres = xres; inf->modes[0].yres = yres;
1833 inf->modes[0].bpp = bpp;
1834 dev_info(dev, "overriding bit depth: %d\n", bpp);
1837 dev_err(dev, "Depth %d is not valid\n", bpp);
1843 static int __devinit parse_opt(struct device *dev, char *this_opt)
1845 struct pxafb_mach_info *inf = dev->platform_data;
1846 struct pxafb_mode_info *mode = &inf->modes[0];
1851 if (!strncmp(this_opt, "vmem:", 5)) {
1852 video_mem_size = memparse(this_opt + 5, NULL);
1853 } else if (!strncmp(this_opt, "mode:", 5)) {
1854 return parse_opt_mode(dev, this_opt);
1855 } else if (!strncmp(this_opt, "pixclock:", 9)) {
1856 mode->pixclock = simple_strtoul(this_opt+9, NULL, 0);
1857 sprintf(s, "pixclock: %ld\n", mode->pixclock);
1858 } else if (!strncmp(this_opt, "left:", 5)) {
1859 mode->left_margin = simple_strtoul(this_opt+5, NULL, 0);
1860 sprintf(s, "left: %u\n", mode->left_margin);
1861 } else if (!strncmp(this_opt, "right:", 6)) {
1862 mode->right_margin = simple_strtoul(this_opt+6, NULL, 0);
1863 sprintf(s, "right: %u\n", mode->right_margin);
1864 } else if (!strncmp(this_opt, "upper:", 6)) {
1865 mode->upper_margin = simple_strtoul(this_opt+6, NULL, 0);
1866 sprintf(s, "upper: %u\n", mode->upper_margin);
1867 } else if (!strncmp(this_opt, "lower:", 6)) {
1868 mode->lower_margin = simple_strtoul(this_opt+6, NULL, 0);
1869 sprintf(s, "lower: %u\n", mode->lower_margin);
1870 } else if (!strncmp(this_opt, "hsynclen:", 9)) {
1871 mode->hsync_len = simple_strtoul(this_opt+9, NULL, 0);
1872 sprintf(s, "hsynclen: %u\n", mode->hsync_len);
1873 } else if (!strncmp(this_opt, "vsynclen:", 9)) {
1874 mode->vsync_len = simple_strtoul(this_opt+9, NULL, 0);
1875 sprintf(s, "vsynclen: %u\n", mode->vsync_len);
1876 } else if (!strncmp(this_opt, "hsync:", 6)) {
1877 if (simple_strtoul(this_opt+6, NULL, 0) == 0) {
1878 sprintf(s, "hsync: Active Low\n");
1879 mode->sync &= ~FB_SYNC_HOR_HIGH_ACT;
1881 sprintf(s, "hsync: Active High\n");
1882 mode->sync |= FB_SYNC_HOR_HIGH_ACT;
1884 } else if (!strncmp(this_opt, "vsync:", 6)) {
1885 if (simple_strtoul(this_opt+6, NULL, 0) == 0) {
1886 sprintf(s, "vsync: Active Low\n");
1887 mode->sync &= ~FB_SYNC_VERT_HIGH_ACT;
1889 sprintf(s, "vsync: Active High\n");
1890 mode->sync |= FB_SYNC_VERT_HIGH_ACT;
1892 } else if (!strncmp(this_opt, "dpc:", 4)) {
1893 if (simple_strtoul(this_opt+4, NULL, 0) == 0) {
1894 sprintf(s, "double pixel clock: false\n");
1895 inf->lccr3 &= ~LCCR3_DPC;
1897 sprintf(s, "double pixel clock: true\n");
1898 inf->lccr3 |= LCCR3_DPC;
1900 } else if (!strncmp(this_opt, "outputen:", 9)) {
1901 if (simple_strtoul(this_opt+9, NULL, 0) == 0) {
1902 sprintf(s, "output enable: active low\n");
1903 inf->lccr3 = (inf->lccr3 & ~LCCR3_OEP) | LCCR3_OutEnL;
1905 sprintf(s, "output enable: active high\n");
1906 inf->lccr3 = (inf->lccr3 & ~LCCR3_OEP) | LCCR3_OutEnH;
1908 } else if (!strncmp(this_opt, "pixclockpol:", 12)) {
1909 if (simple_strtoul(this_opt+12, NULL, 0) == 0) {
1910 sprintf(s, "pixel clock polarity: falling edge\n");
1911 inf->lccr3 = (inf->lccr3 & ~LCCR3_PCP) | LCCR3_PixFlEdg;
1913 sprintf(s, "pixel clock polarity: rising edge\n");
1914 inf->lccr3 = (inf->lccr3 & ~LCCR3_PCP) | LCCR3_PixRsEdg;
1916 } else if (!strncmp(this_opt, "color", 5)) {
1917 inf->lccr0 = (inf->lccr0 & ~LCCR0_CMS) | LCCR0_Color;
1918 } else if (!strncmp(this_opt, "mono", 4)) {
1919 inf->lccr0 = (inf->lccr0 & ~LCCR0_CMS) | LCCR0_Mono;
1920 } else if (!strncmp(this_opt, "active", 6)) {
1921 inf->lccr0 = (inf->lccr0 & ~LCCR0_PAS) | LCCR0_Act;
1922 } else if (!strncmp(this_opt, "passive", 7)) {
1923 inf->lccr0 = (inf->lccr0 & ~LCCR0_PAS) | LCCR0_Pas;
1924 } else if (!strncmp(this_opt, "single", 6)) {
1925 inf->lccr0 = (inf->lccr0 & ~LCCR0_SDS) | LCCR0_Sngl;
1926 } else if (!strncmp(this_opt, "dual", 4)) {
1927 inf->lccr0 = (inf->lccr0 & ~LCCR0_SDS) | LCCR0_Dual;
1928 } else if (!strncmp(this_opt, "4pix", 4)) {
1929 inf->lccr0 = (inf->lccr0 & ~LCCR0_DPD) | LCCR0_4PixMono;
1930 } else if (!strncmp(this_opt, "8pix", 4)) {
1931 inf->lccr0 = (inf->lccr0 & ~LCCR0_DPD) | LCCR0_8PixMono;
1933 dev_err(dev, "unknown option: %s\n", this_opt);
1938 dev_info(dev, "override %s", s);
1943 static int __devinit pxafb_parse_options(struct device *dev, char *options)
1948 if (!options || !*options)
1951 dev_dbg(dev, "options are \"%s\"\n", options ? options : "null");
1953 /* could be made table driven or similar?... */
1954 while ((this_opt = strsep(&options, ",")) != NULL) {
1955 ret = parse_opt(dev, this_opt);
1962 static char g_options[256] __devinitdata = "";
1965 static int __init pxafb_setup_options(void)
1967 char *options = NULL;
1969 if (fb_get_options("pxafb", &options))
1973 strlcpy(g_options, options, sizeof(g_options));
1978 #define pxafb_setup_options() (0)
1980 module_param_string(options, g_options, sizeof(g_options), 0);
1981 MODULE_PARM_DESC(options, "LCD parameters (see Documentation/fb/pxafb.txt)");
1985 #define pxafb_parse_options(...) (0)
1986 #define pxafb_setup_options() (0)
1990 /* Check for various illegal bit-combinations. Currently only
1991 * a warning is given. */
1992 static void __devinit pxafb_check_options(struct device *dev,
1993 struct pxafb_mach_info *inf)
1998 if (inf->lccr0 & LCCR0_INVALID_CONFIG_MASK)
1999 dev_warn(dev, "machine LCCR0 setting contains "
2000 "illegal bits: %08x\n",
2001 inf->lccr0 & LCCR0_INVALID_CONFIG_MASK);
2002 if (inf->lccr3 & LCCR3_INVALID_CONFIG_MASK)
2003 dev_warn(dev, "machine LCCR3 setting contains "
2004 "illegal bits: %08x\n",
2005 inf->lccr3 & LCCR3_INVALID_CONFIG_MASK);
2006 if (inf->lccr0 & LCCR0_DPD &&
2007 ((inf->lccr0 & LCCR0_PAS) != LCCR0_Pas ||
2008 (inf->lccr0 & LCCR0_SDS) != LCCR0_Sngl ||
2009 (inf->lccr0 & LCCR0_CMS) != LCCR0_Mono))
2010 dev_warn(dev, "Double Pixel Data (DPD) mode is "
2011 "only valid in passive mono"
2012 " single panel mode\n");
2013 if ((inf->lccr0 & LCCR0_PAS) == LCCR0_Act &&
2014 (inf->lccr0 & LCCR0_SDS) == LCCR0_Dual)
2015 dev_warn(dev, "Dual panel only valid in passive mode\n");
2016 if ((inf->lccr0 & LCCR0_PAS) == LCCR0_Pas &&
2017 (inf->modes->upper_margin || inf->modes->lower_margin))
2018 dev_warn(dev, "Upper and lower margins must be 0 in "
2022 #define pxafb_check_options(...) do {} while (0)
2025 static int __devinit pxafb_probe(struct platform_device *dev)
2027 struct pxafb_info *fbi;
2028 struct pxafb_mach_info *inf;
2032 dev_dbg(&dev->dev, "pxafb_probe\n");
2034 inf = dev->dev.platform_data;
2040 ret = pxafb_parse_options(&dev->dev, g_options);
2044 pxafb_check_options(&dev->dev, inf);
2046 dev_dbg(&dev->dev, "got a %dx%dx%d LCD\n",
2050 if (inf->modes->xres == 0 ||
2051 inf->modes->yres == 0 ||
2052 inf->modes->bpp == 0) {
2053 dev_err(&dev->dev, "Invalid resolution or bit depth\n");
2058 fbi = pxafb_init_fbinfo(&dev->dev);
2060 /* only reason for pxafb_init_fbinfo to fail is kmalloc */
2061 dev_err(&dev->dev, "Failed to initialize framebuffer device\n");
2066 fbi->backlight_power = inf->pxafb_backlight_power;
2067 fbi->lcd_power = inf->pxafb_lcd_power;
2069 r = platform_get_resource(dev, IORESOURCE_MEM, 0);
2071 dev_err(&dev->dev, "no I/O memory resource defined\n");
2076 r = request_mem_region(r->start, r->end - r->start + 1, dev->name);
2078 dev_err(&dev->dev, "failed to request I/O memory\n");
2083 fbi->mmio_base = ioremap(r->start, r->end - r->start + 1);
2084 if (fbi->mmio_base == NULL) {
2085 dev_err(&dev->dev, "failed to map I/O memory\n");
2087 goto failed_free_res;
2090 fbi->dma_buff_size = PAGE_ALIGN(sizeof(struct pxafb_dma_buff));
2091 fbi->dma_buff = dma_alloc_coherent(fbi->dev, fbi->dma_buff_size,
2092 &fbi->dma_buff_phys, GFP_KERNEL);
2093 if (fbi->dma_buff == NULL) {
2094 dev_err(&dev->dev, "failed to allocate memory for DMA\n");
2096 goto failed_free_io;
2099 ret = pxafb_init_video_memory(fbi);
2101 dev_err(&dev->dev, "Failed to allocate video RAM: %d\n", ret);
2103 goto failed_free_dma;
2106 irq = platform_get_irq(dev, 0);
2108 dev_err(&dev->dev, "no IRQ defined\n");
2110 goto failed_free_mem;
2113 ret = request_irq(irq, pxafb_handle_irq, IRQF_DISABLED, "LCD", fbi);
2115 dev_err(&dev->dev, "request_irq failed: %d\n", ret);
2117 goto failed_free_mem;
2120 ret = pxafb_smart_init(fbi);
2122 dev_err(&dev->dev, "failed to initialize smartpanel\n");
2123 goto failed_free_irq;
2127 * This makes sure that our colour bitfield
2128 * descriptors are correctly initialised.
2130 ret = pxafb_check_var(&fbi->fb.var, &fbi->fb);
2132 dev_err(&dev->dev, "failed to get suitable mode\n");
2133 goto failed_free_irq;
2136 ret = pxafb_set_par(&fbi->fb);
2138 dev_err(&dev->dev, "Failed to set parameters\n");
2139 goto failed_free_irq;
2142 platform_set_drvdata(dev, fbi);
2144 ret = register_framebuffer(&fbi->fb);
2147 "Failed to register framebuffer device: %d\n", ret);
2148 goto failed_free_cmap;
2151 pxafb_overlay_init(fbi);
2153 #ifdef CONFIG_CPU_FREQ
2154 fbi->freq_transition.notifier_call = pxafb_freq_transition;
2155 fbi->freq_policy.notifier_call = pxafb_freq_policy;
2156 cpufreq_register_notifier(&fbi->freq_transition,
2157 CPUFREQ_TRANSITION_NOTIFIER);
2158 cpufreq_register_notifier(&fbi->freq_policy,
2159 CPUFREQ_POLICY_NOTIFIER);
2163 * Ok, now enable the LCD controller
2165 set_ctrlr_state(fbi, C_ENABLE);
2170 if (fbi->fb.cmap.len)
2171 fb_dealloc_cmap(&fbi->fb.cmap);
2175 free_pages_exact(fbi->video_mem, fbi->video_mem_size);
2177 dma_free_coherent(&dev->dev, fbi->dma_buff_size,
2178 fbi->dma_buff, fbi->dma_buff_phys);
2180 iounmap(fbi->mmio_base);
2182 release_mem_region(r->start, r->end - r->start + 1);
2185 platform_set_drvdata(dev, NULL);
2191 static int __devexit pxafb_remove(struct platform_device *dev)
2193 struct pxafb_info *fbi = platform_get_drvdata(dev);
2196 struct fb_info *info;
2203 pxafb_overlay_exit(fbi);
2204 unregister_framebuffer(info);
2206 pxafb_disable_controller(fbi);
2208 if (fbi->fb.cmap.len)
2209 fb_dealloc_cmap(&fbi->fb.cmap);
2211 irq = platform_get_irq(dev, 0);
2214 free_pages_exact(fbi->video_mem, fbi->video_mem_size);
2216 dma_free_writecombine(&dev->dev, fbi->dma_buff_size,
2217 fbi->dma_buff, fbi->dma_buff_phys);
2219 iounmap(fbi->mmio_base);
2221 r = platform_get_resource(dev, IORESOURCE_MEM, 0);
2222 release_mem_region(r->start, r->end - r->start + 1);
2230 static struct platform_driver pxafb_driver = {
2231 .probe = pxafb_probe,
2232 .remove = __devexit_p(pxafb_remove),
2233 .suspend = pxafb_suspend,
2234 .resume = pxafb_resume,
2236 .owner = THIS_MODULE,
2237 .name = "pxa2xx-fb",
2241 static int __init pxafb_init(void)
2243 if (pxafb_setup_options())
2246 return platform_driver_register(&pxafb_driver);
2249 static void __exit pxafb_exit(void)
2251 platform_driver_unregister(&pxafb_driver);
2254 module_init(pxafb_init);
2255 module_exit(pxafb_exit);
2257 MODULE_DESCRIPTION("loadable framebuffer driver for PXA");
2258 MODULE_LICENSE("GPL");