2 * linux/drivers/video/riva/fbdev.c - nVidia RIVA 128/TNT/TNT2 fb driver
4 * Maintained by Ani Joshi <ajoshi@shell.unixbox.com>
6 * Copyright 1999-2000 Jeff Garzik
10 * Ani Joshi: Lots of debugging and cleanup work, really helped
11 * get the driver going
13 * Ferenc Bakonyi: Bug fixes, cleanup, modularization
15 * Jindrich Makovicka: Accel code help, hw cursor, mtrr
17 * Paul Richards: Bug fixes, updates
19 * Initial template from skeletonfb.c, created 28 Dec 1997 by Geert Uytterhoeven
20 * Includes riva_hw.c from nVidia, see copyright below.
21 * KGI code provided the basis for state storage, init, and mode switching.
23 * This file is subject to the terms and conditions of the GNU General Public
24 * License. See the file COPYING in the main directory of this archive
27 * Known bugs and issues:
28 * restoring text mode fails
29 * doublescan modes are broken
32 #include <linux/module.h>
33 #include <linux/kernel.h>
34 #include <linux/errno.h>
35 #include <linux/string.h>
37 #include <linux/slab.h>
38 #include <linux/delay.h>
40 #include <linux/init.h>
41 #include <linux/pci.h>
42 #include <linux/backlight.h>
43 #include <linux/bitrev.h>
49 #include <asm/pci-bridge.h>
51 #ifdef CONFIG_PMAC_BACKLIGHT
52 #include <asm/machdep.h>
53 #include <asm/backlight.h>
59 #ifndef CONFIG_PCI /* sanity check */
60 #error This driver requires PCI support.
63 /* version number of this driver */
64 #define RIVAFB_VERSION "0.9.5b"
66 /* ------------------------------------------------------------------------- *
68 * various helpful macros and constants
70 * ------------------------------------------------------------------------- */
71 #ifdef CONFIG_FB_RIVA_DEBUG
72 #define NVTRACE printk
74 #define NVTRACE if(0) printk
77 #define NVTRACE_ENTER(...) NVTRACE("%s START\n", __FUNCTION__)
78 #define NVTRACE_LEAVE(...) NVTRACE("%s END\n", __FUNCTION__)
80 #ifdef CONFIG_FB_RIVA_DEBUG
81 #define assert(expr) \
83 printk( "Assertion failed! %s,%s,%s,line=%d\n",\
84 #expr,__FILE__,__FUNCTION__,__LINE__); \
91 #define PFX "rivafb: "
93 /* macro that allows you to set overflow bits */
94 #define SetBitField(value,from,to) SetBF(to,GetBF(value,from))
95 #define SetBit(n) (1<<(n))
96 #define Set8Bits(value) ((value)&0xff)
98 /* HW cursor parameters */
101 /* ------------------------------------------------------------------------- *
105 * ------------------------------------------------------------------------- */
107 static int rivafb_blank(int blank, struct fb_info *info);
109 /* ------------------------------------------------------------------------- *
111 * card identification
113 * ------------------------------------------------------------------------- */
115 static struct pci_device_id rivafb_pci_tbl[] = {
116 { PCI_VENDOR_ID_NVIDIA_SGS, PCI_DEVICE_ID_NVIDIA_SGS_RIVA128,
117 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
118 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_TNT,
119 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
120 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_TNT2,
121 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
122 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_UTNT2,
123 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
124 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_VTNT2,
125 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
126 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_UVTNT2,
127 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
128 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_ITNT2,
129 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
130 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_SDR,
131 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
132 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_DDR,
133 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
134 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO,
135 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
136 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE2_MX,
137 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
138 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE2_MX2,
139 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
140 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE2_GO,
141 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
142 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO2_MXR,
143 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
144 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE2_GTS,
145 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
146 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE2_GTS2,
147 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
148 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE2_ULTRA,
149 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
150 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO2_PRO,
151 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
152 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_460,
153 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
154 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_440,
155 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
156 // NF2/IGP version, GeForce 4 MX, NV18
157 { PCI_VENDOR_ID_NVIDIA, 0x01f0,
158 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
159 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_420,
160 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
161 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_440_GO,
162 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
163 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_420_GO,
164 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
165 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_420_GO_M32,
166 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
167 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_500XGL,
168 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
169 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_440_GO_M64,
170 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
171 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_200,
172 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
173 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_550XGL,
174 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
175 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_500_GOGL,
176 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
177 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_IGEFORCE2,
178 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
179 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE3,
180 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
181 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE3_1,
182 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
183 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE3_2,
184 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
185 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO_DDC,
186 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
187 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI_4600,
188 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
189 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI_4400,
190 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
191 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI_4200,
192 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
193 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_900XGL,
194 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
195 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_750XGL,
196 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
197 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_700XGL,
198 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
199 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_GO_5200,
200 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
201 { 0, } /* terminate list */
203 MODULE_DEVICE_TABLE(pci, rivafb_pci_tbl);
205 /* ------------------------------------------------------------------------- *
209 * ------------------------------------------------------------------------- */
211 /* command line data, set in rivafb_setup() */
212 static int flatpanel __devinitdata = -1; /* Autodetect later */
213 static int forceCRTC __devinitdata = -1;
214 static int noaccel __devinitdata = 0;
216 static int nomtrr __devinitdata = 0;
219 static char *mode_option __devinitdata = NULL;
220 static int strictmode = 0;
222 static struct fb_fix_screeninfo __devinitdata rivafb_fix = {
223 .type = FB_TYPE_PACKED_PIXELS,
228 static struct fb_var_screeninfo __devinitdata rivafb_default_var = {
238 .activate = FB_ACTIVATE_NOW,
248 .vmode = FB_VMODE_NONINTERLACED
252 static const struct riva_regs reg_template = {
253 {0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, /* ATTR */
254 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F,
255 0x41, 0x01, 0x0F, 0x00, 0x00},
256 {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* CRT */
257 0x00, 0x00, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00,
258 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE3, /* 0x10 */
259 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
260 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 0x20 */
261 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
262 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 0x30 */
263 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
266 {0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x05, 0x0F, /* GRA */
268 {0x03, 0x01, 0x0F, 0x00, 0x0E}, /* SEQ */
275 #ifdef CONFIG_FB_RIVA_BACKLIGHT
276 /* We do not have any information about which values are allowed, thus
277 * we used safe values.
279 #define MIN_LEVEL 0x158
280 #define MAX_LEVEL 0x534
281 #define LEVEL_STEP ((MAX_LEVEL - MIN_LEVEL) / FB_BACKLIGHT_MAX)
283 static struct backlight_properties riva_bl_data;
285 /* Call with fb_info->bl_mutex held */
286 static int riva_bl_get_level_brightness(struct riva_par *par,
289 struct fb_info *info = pci_get_drvdata(par->pdev);
292 /* Get and convert the value */
293 nlevel = MIN_LEVEL + info->bl_curve[level] * LEVEL_STEP;
297 else if (nlevel < MIN_LEVEL)
299 else if (nlevel > MAX_LEVEL)
305 /* Call with fb_info->bl_mutex held */
306 static int __riva_bl_update_status(struct backlight_device *bd)
308 struct riva_par *par = class_get_devdata(&bd->class_dev);
309 U032 tmp_pcrt, tmp_pmc;
312 if (bd->props->power != FB_BLANK_UNBLANK ||
313 bd->props->fb_blank != FB_BLANK_UNBLANK)
316 level = bd->props->brightness;
318 tmp_pmc = par->riva.PMC[0x10F0/4] & 0x0000FFFF;
319 tmp_pcrt = par->riva.PCRTC0[0x081C/4] & 0xFFFFFFFC;
322 tmp_pmc |= (1 << 31); /* backlight bit */
323 tmp_pmc |= riva_bl_get_level_brightness(par, level) << 16; /* level */
325 par->riva.PCRTC0[0x081C/4] = tmp_pcrt;
326 par->riva.PMC[0x10F0/4] = tmp_pmc;
331 static int riva_bl_update_status(struct backlight_device *bd)
333 struct riva_par *par = class_get_devdata(&bd->class_dev);
334 struct fb_info *info = pci_get_drvdata(par->pdev);
337 mutex_lock(&info->bl_mutex);
338 ret = __riva_bl_update_status(bd);
339 mutex_unlock(&info->bl_mutex);
344 static int riva_bl_get_brightness(struct backlight_device *bd)
346 return bd->props->brightness;
349 static struct backlight_properties riva_bl_data = {
350 .owner = THIS_MODULE,
351 .get_brightness = riva_bl_get_brightness,
352 .update_status = riva_bl_update_status,
353 .max_brightness = (FB_BACKLIGHT_LEVELS - 1),
356 static void riva_bl_set_power(struct fb_info *info, int power)
358 mutex_lock(&info->bl_mutex);
361 down(&info->bl_dev->sem);
362 info->bl_dev->props->power = power;
363 __riva_bl_update_status(info->bl_dev);
364 up(&info->bl_dev->sem);
367 mutex_unlock(&info->bl_mutex);
370 static void riva_bl_init(struct riva_par *par)
372 struct fb_info *info = pci_get_drvdata(par->pdev);
373 struct backlight_device *bd;
379 #ifdef CONFIG_PMAC_BACKLIGHT
380 if (!machine_is(powermac) ||
381 !pmac_has_backlight_type("mnca"))
385 snprintf(name, sizeof(name), "rivabl%d", info->node);
387 bd = backlight_device_register(name, par, &riva_bl_data);
390 printk(KERN_WARNING "riva: Backlight registration failed\n");
394 mutex_lock(&info->bl_mutex);
396 fb_bl_default_curve(info, 0,
397 MIN_LEVEL * FB_BACKLIGHT_MAX / MAX_LEVEL,
399 mutex_unlock(&info->bl_mutex);
402 bd->props->brightness = riva_bl_data.max_brightness;
403 bd->props->power = FB_BLANK_UNBLANK;
404 bd->props->update_status(bd);
407 #ifdef CONFIG_PMAC_BACKLIGHT
408 mutex_lock(&pmac_backlight_mutex);
411 mutex_unlock(&pmac_backlight_mutex);
414 printk("riva: Backlight initialized (%s)\n", name);
422 static void riva_bl_exit(struct riva_par *par)
424 struct fb_info *info = pci_get_drvdata(par->pdev);
426 #ifdef CONFIG_PMAC_BACKLIGHT
427 mutex_lock(&pmac_backlight_mutex);
430 mutex_lock(&info->bl_mutex);
432 #ifdef CONFIG_PMAC_BACKLIGHT
433 if (pmac_backlight == info->bl_dev)
434 pmac_backlight = NULL;
437 backlight_device_unregister(info->bl_dev);
439 printk("riva: Backlight unloaded\n");
441 mutex_unlock(&info->bl_mutex);
443 #ifdef CONFIG_PMAC_BACKLIGHT
444 mutex_unlock(&pmac_backlight_mutex);
448 static inline void riva_bl_init(struct riva_par *par) {}
449 static inline void riva_bl_exit(struct riva_par *par) {}
450 static inline void riva_bl_set_power(struct fb_info *info, int power) {}
451 #endif /* CONFIG_FB_RIVA_BACKLIGHT */
453 /* ------------------------------------------------------------------------- *
457 * ------------------------------------------------------------------------- */
459 static inline void CRTCout(struct riva_par *par, unsigned char index,
462 VGA_WR08(par->riva.PCIO, 0x3d4, index);
463 VGA_WR08(par->riva.PCIO, 0x3d5, val);
466 static inline unsigned char CRTCin(struct riva_par *par,
469 VGA_WR08(par->riva.PCIO, 0x3d4, index);
470 return (VGA_RD08(par->riva.PCIO, 0x3d5));
473 static inline void GRAout(struct riva_par *par, unsigned char index,
476 VGA_WR08(par->riva.PVIO, 0x3ce, index);
477 VGA_WR08(par->riva.PVIO, 0x3cf, val);
480 static inline unsigned char GRAin(struct riva_par *par,
483 VGA_WR08(par->riva.PVIO, 0x3ce, index);
484 return (VGA_RD08(par->riva.PVIO, 0x3cf));
487 static inline void SEQout(struct riva_par *par, unsigned char index,
490 VGA_WR08(par->riva.PVIO, 0x3c4, index);
491 VGA_WR08(par->riva.PVIO, 0x3c5, val);
494 static inline unsigned char SEQin(struct riva_par *par,
497 VGA_WR08(par->riva.PVIO, 0x3c4, index);
498 return (VGA_RD08(par->riva.PVIO, 0x3c5));
501 static inline void ATTRout(struct riva_par *par, unsigned char index,
504 VGA_WR08(par->riva.PCIO, 0x3c0, index);
505 VGA_WR08(par->riva.PCIO, 0x3c0, val);
508 static inline unsigned char ATTRin(struct riva_par *par,
511 VGA_WR08(par->riva.PCIO, 0x3c0, index);
512 return (VGA_RD08(par->riva.PCIO, 0x3c1));
515 static inline void MISCout(struct riva_par *par, unsigned char val)
517 VGA_WR08(par->riva.PVIO, 0x3c2, val);
520 static inline unsigned char MISCin(struct riva_par *par)
522 return (VGA_RD08(par->riva.PVIO, 0x3cc));
525 static inline void reverse_order(u32 *l)
528 a[0] = bitrev8(a[0]);
529 a[1] = bitrev8(a[1]);
530 a[2] = bitrev8(a[2]);
531 a[3] = bitrev8(a[3]);
534 /* ------------------------------------------------------------------------- *
538 * ------------------------------------------------------------------------- */
541 * rivafb_load_cursor_image - load cursor image to hardware
542 * @data: address to monochrome bitmap (1 = foreground color, 0 = background)
543 * @par: pointer to private data
544 * @w: width of cursor image in pixels
545 * @h: height of cursor image in scanlines
546 * @bg: background color (ARGB1555) - alpha bit determines opacity
547 * @fg: foreground color (ARGB1555)
550 * Loads cursor image based on a monochrome source and mask bitmap. The
551 * image bits determines the color of the pixel, 0 for background, 1 for
552 * foreground. Only the affected region (as determined by @w and @h
553 * parameters) will be updated.
558 static void rivafb_load_cursor_image(struct riva_par *par, u8 *data8,
559 u16 bg, u16 fg, u32 w, u32 h)
563 u32 *data = (u32 *)data8;
564 bg = le16_to_cpu(bg);
565 fg = le16_to_cpu(fg);
569 for (i = 0; i < h; i++) {
573 for (j = 0; j < w/2; j++) {
575 #if defined (__BIG_ENDIAN)
576 tmp = (b & (1 << 31)) ? fg << 16 : bg << 16;
578 tmp |= (b & (1 << 31)) ? fg : bg;
581 tmp = (b & 1) ? fg : bg;
583 tmp |= (b & 1) ? fg << 16 : bg << 16;
586 writel(tmp, &par->riva.CURSOR[k++]);
588 k += (MAX_CURS - w)/2;
592 /* ------------------------------------------------------------------------- *
594 * general utility functions
596 * ------------------------------------------------------------------------- */
599 * riva_wclut - set CLUT entry
600 * @chip: pointer to RIVA_HW_INST object
601 * @regnum: register number
602 * @red: red component
603 * @green: green component
604 * @blue: blue component
607 * Sets color register @regnum.
612 static void riva_wclut(RIVA_HW_INST *chip,
613 unsigned char regnum, unsigned char red,
614 unsigned char green, unsigned char blue)
616 VGA_WR08(chip->PDIO, 0x3c8, regnum);
617 VGA_WR08(chip->PDIO, 0x3c9, red);
618 VGA_WR08(chip->PDIO, 0x3c9, green);
619 VGA_WR08(chip->PDIO, 0x3c9, blue);
623 * riva_rclut - read fromCLUT register
624 * @chip: pointer to RIVA_HW_INST object
625 * @regnum: register number
626 * @red: red component
627 * @green: green component
628 * @blue: blue component
631 * Reads red, green, and blue from color register @regnum.
636 static void riva_rclut(RIVA_HW_INST *chip,
637 unsigned char regnum, unsigned char *red,
638 unsigned char *green, unsigned char *blue)
641 VGA_WR08(chip->PDIO, 0x3c7, regnum);
642 *red = VGA_RD08(chip->PDIO, 0x3c9);
643 *green = VGA_RD08(chip->PDIO, 0x3c9);
644 *blue = VGA_RD08(chip->PDIO, 0x3c9);
648 * riva_save_state - saves current chip state
649 * @par: pointer to riva_par object containing info for current riva board
650 * @regs: pointer to riva_regs object
653 * Saves current chip state to @regs.
659 static void riva_save_state(struct riva_par *par, struct riva_regs *regs)
664 par->riva.LockUnlock(&par->riva, 0);
666 par->riva.UnloadStateExt(&par->riva, ®s->ext);
668 regs->misc_output = MISCin(par);
670 for (i = 0; i < NUM_CRT_REGS; i++)
671 regs->crtc[i] = CRTCin(par, i);
673 for (i = 0; i < NUM_ATC_REGS; i++)
674 regs->attr[i] = ATTRin(par, i);
676 for (i = 0; i < NUM_GRC_REGS; i++)
677 regs->gra[i] = GRAin(par, i);
679 for (i = 0; i < NUM_SEQ_REGS; i++)
680 regs->seq[i] = SEQin(par, i);
685 * riva_load_state - loads current chip state
686 * @par: pointer to riva_par object containing info for current riva board
687 * @regs: pointer to riva_regs object
690 * Loads chip state from @regs.
693 * riva_load_video_mode()
698 static void riva_load_state(struct riva_par *par, struct riva_regs *regs)
700 RIVA_HW_STATE *state = ®s->ext;
704 CRTCout(par, 0x11, 0x00);
706 par->riva.LockUnlock(&par->riva, 0);
708 par->riva.LoadStateExt(&par->riva, state);
710 MISCout(par, regs->misc_output);
712 for (i = 0; i < NUM_CRT_REGS; i++) {
718 CRTCout(par, i, regs->crtc[i]);
722 for (i = 0; i < NUM_ATC_REGS; i++)
723 ATTRout(par, i, regs->attr[i]);
725 for (i = 0; i < NUM_GRC_REGS; i++)
726 GRAout(par, i, regs->gra[i]);
728 for (i = 0; i < NUM_SEQ_REGS; i++)
729 SEQout(par, i, regs->seq[i]);
734 * riva_load_video_mode - calculate timings
735 * @info: pointer to fb_info object containing info for current riva board
738 * Calculate some timings and then send em off to riva_load_state().
743 static void riva_load_video_mode(struct fb_info *info)
745 int bpp, width, hDisplaySize, hDisplay, hStart,
746 hEnd, hTotal, height, vDisplay, vStart, vEnd, vTotal, dotClock;
747 int hBlankStart, hBlankEnd, vBlankStart, vBlankEnd;
748 struct riva_par *par = info->par;
749 struct riva_regs newmode;
752 /* time to calculate */
753 rivafb_blank(FB_BLANK_NORMAL, info);
755 bpp = info->var.bits_per_pixel;
756 if (bpp == 16 && info->var.green.length == 5)
758 width = info->var.xres_virtual;
759 hDisplaySize = info->var.xres;
760 hDisplay = (hDisplaySize / 8) - 1;
761 hStart = (hDisplaySize + info->var.right_margin) / 8 - 1;
762 hEnd = (hDisplaySize + info->var.right_margin +
763 info->var.hsync_len) / 8 - 1;
764 hTotal = (hDisplaySize + info->var.right_margin +
765 info->var.hsync_len + info->var.left_margin) / 8 - 5;
766 hBlankStart = hDisplay;
767 hBlankEnd = hTotal + 4;
769 height = info->var.yres_virtual;
770 vDisplay = info->var.yres - 1;
771 vStart = info->var.yres + info->var.lower_margin - 1;
772 vEnd = info->var.yres + info->var.lower_margin +
773 info->var.vsync_len - 1;
774 vTotal = info->var.yres + info->var.lower_margin +
775 info->var.vsync_len + info->var.upper_margin + 2;
776 vBlankStart = vDisplay;
777 vBlankEnd = vTotal + 1;
778 dotClock = 1000000000 / info->var.pixclock;
780 memcpy(&newmode, ®_template, sizeof(struct riva_regs));
782 if ((info->var.vmode & FB_VMODE_MASK) == FB_VMODE_INTERLACED)
785 if (par->FlatPanel) {
788 vBlankStart = vStart;
791 hBlankEnd = hTotal + 4;
794 newmode.crtc[0x0] = Set8Bits (hTotal);
795 newmode.crtc[0x1] = Set8Bits (hDisplay);
796 newmode.crtc[0x2] = Set8Bits (hBlankStart);
797 newmode.crtc[0x3] = SetBitField (hBlankEnd, 4: 0, 4:0) | SetBit (7);
798 newmode.crtc[0x4] = Set8Bits (hStart);
799 newmode.crtc[0x5] = SetBitField (hBlankEnd, 5: 5, 7:7)
800 | SetBitField (hEnd, 4: 0, 4:0);
801 newmode.crtc[0x6] = SetBitField (vTotal, 7: 0, 7:0);
802 newmode.crtc[0x7] = SetBitField (vTotal, 8: 8, 0:0)
803 | SetBitField (vDisplay, 8: 8, 1:1)
804 | SetBitField (vStart, 8: 8, 2:2)
805 | SetBitField (vBlankStart, 8: 8, 3:3)
807 | SetBitField (vTotal, 9: 9, 5:5)
808 | SetBitField (vDisplay, 9: 9, 6:6)
809 | SetBitField (vStart, 9: 9, 7:7);
810 newmode.crtc[0x9] = SetBitField (vBlankStart, 9: 9, 5:5)
812 newmode.crtc[0x10] = Set8Bits (vStart);
813 newmode.crtc[0x11] = SetBitField (vEnd, 3: 0, 3:0)
815 newmode.crtc[0x12] = Set8Bits (vDisplay);
816 newmode.crtc[0x13] = (width / 8) * ((bpp + 1) / 8);
817 newmode.crtc[0x15] = Set8Bits (vBlankStart);
818 newmode.crtc[0x16] = Set8Bits (vBlankEnd);
820 newmode.ext.screen = SetBitField(hBlankEnd,6:6,4:4)
821 | SetBitField(vBlankStart,10:10,3:3)
822 | SetBitField(vStart,10:10,2:2)
823 | SetBitField(vDisplay,10:10,1:1)
824 | SetBitField(vTotal,10:10,0:0);
825 newmode.ext.horiz = SetBitField(hTotal,8:8,0:0)
826 | SetBitField(hDisplay,8:8,1:1)
827 | SetBitField(hBlankStart,8:8,2:2)
828 | SetBitField(hStart,8:8,3:3);
829 newmode.ext.extra = SetBitField(vTotal,11:11,0:0)
830 | SetBitField(vDisplay,11:11,2:2)
831 | SetBitField(vStart,11:11,4:4)
832 | SetBitField(vBlankStart,11:11,6:6);
834 if ((info->var.vmode & FB_VMODE_MASK) == FB_VMODE_INTERLACED) {
835 int tmp = (hTotal >> 1) & ~1;
836 newmode.ext.interlace = Set8Bits(tmp);
837 newmode.ext.horiz |= SetBitField(tmp, 8:8,4:4);
839 newmode.ext.interlace = 0xff; /* interlace off */
841 if (par->riva.Architecture >= NV_ARCH_10)
842 par->riva.CURSOR = (U032 __iomem *)(info->screen_base + par->riva.CursorStart);
844 if (info->var.sync & FB_SYNC_HOR_HIGH_ACT)
845 newmode.misc_output &= ~0x40;
847 newmode.misc_output |= 0x40;
848 if (info->var.sync & FB_SYNC_VERT_HIGH_ACT)
849 newmode.misc_output &= ~0x80;
851 newmode.misc_output |= 0x80;
853 par->riva.CalcStateExt(&par->riva, &newmode.ext, bpp, width,
854 hDisplaySize, height, dotClock);
856 newmode.ext.scale = NV_RD32(par->riva.PRAMDAC, 0x00000848) &
858 if (par->FlatPanel == 1) {
859 newmode.ext.pixel |= (1 << 7);
860 newmode.ext.scale |= (1 << 8);
862 if (par->SecondCRTC) {
863 newmode.ext.head = NV_RD32(par->riva.PCRTC0, 0x00000860) &
865 newmode.ext.head2 = NV_RD32(par->riva.PCRTC0, 0x00002860) |
867 newmode.ext.crtcOwner = 3;
868 newmode.ext.pllsel |= 0x20000800;
869 newmode.ext.vpll2 = newmode.ext.vpll;
870 } else if (par->riva.twoHeads) {
871 newmode.ext.head = NV_RD32(par->riva.PCRTC0, 0x00000860) |
873 newmode.ext.head2 = NV_RD32(par->riva.PCRTC0, 0x00002860) &
875 newmode.ext.crtcOwner = 0;
876 newmode.ext.vpll2 = NV_RD32(par->riva.PRAMDAC0, 0x00000520);
878 if (par->FlatPanel == 1) {
879 newmode.ext.pixel |= (1 << 7);
880 newmode.ext.scale |= (1 << 8);
882 newmode.ext.cursorConfig = 0x02000100;
883 par->current_state = newmode;
884 riva_load_state(par, &par->current_state);
885 par->riva.LockUnlock(&par->riva, 0); /* important for HW cursor */
886 rivafb_blank(FB_BLANK_UNBLANK, info);
890 static void riva_update_var(struct fb_var_screeninfo *var, struct fb_videomode *modedb)
893 var->xres = var->xres_virtual = modedb->xres;
894 var->yres = modedb->yres;
895 if (var->yres_virtual < var->yres)
896 var->yres_virtual = var->yres;
897 var->xoffset = var->yoffset = 0;
898 var->pixclock = modedb->pixclock;
899 var->left_margin = modedb->left_margin;
900 var->right_margin = modedb->right_margin;
901 var->upper_margin = modedb->upper_margin;
902 var->lower_margin = modedb->lower_margin;
903 var->hsync_len = modedb->hsync_len;
904 var->vsync_len = modedb->vsync_len;
905 var->sync = modedb->sync;
906 var->vmode = modedb->vmode;
911 * rivafb_do_maximize -
912 * @info: pointer to fb_info object containing info for current riva board
921 * -EINVAL on failure, 0 on success
927 static int rivafb_do_maximize(struct fb_info *info,
928 struct fb_var_screeninfo *var,
944 /* use highest possible virtual resolution */
945 if (var->xres_virtual == -1 && var->yres_virtual == -1) {
946 printk(KERN_WARNING PFX
947 "using maximum available virtual resolution\n");
948 for (i = 0; modes[i].xres != -1; i++) {
949 if (modes[i].xres * nom / den * modes[i].yres <
953 if (modes[i].xres == -1) {
955 "could not find a virtual resolution that fits into video memory!!\n");
956 NVTRACE("EXIT - EINVAL error\n");
959 var->xres_virtual = modes[i].xres;
960 var->yres_virtual = modes[i].yres;
963 "virtual resolution set to maximum of %dx%d\n",
964 var->xres_virtual, var->yres_virtual);
965 } else if (var->xres_virtual == -1) {
966 var->xres_virtual = (info->fix.smem_len * den /
967 (nom * var->yres_virtual)) & ~15;
968 printk(KERN_WARNING PFX
969 "setting virtual X resolution to %d\n", var->xres_virtual);
970 } else if (var->yres_virtual == -1) {
971 var->xres_virtual = (var->xres_virtual + 15) & ~15;
972 var->yres_virtual = info->fix.smem_len * den /
973 (nom * var->xres_virtual);
974 printk(KERN_WARNING PFX
975 "setting virtual Y resolution to %d\n", var->yres_virtual);
977 var->xres_virtual = (var->xres_virtual + 15) & ~15;
978 if (var->xres_virtual * nom / den * var->yres_virtual > info->fix.smem_len) {
980 "mode %dx%dx%d rejected...resolution too high to fit into video memory!\n",
981 var->xres, var->yres, var->bits_per_pixel);
982 NVTRACE("EXIT - EINVAL error\n");
987 if (var->xres_virtual * nom / den >= 8192) {
988 printk(KERN_WARNING PFX
989 "virtual X resolution (%d) is too high, lowering to %d\n",
990 var->xres_virtual, 8192 * den / nom - 16);
991 var->xres_virtual = 8192 * den / nom - 16;
994 if (var->xres_virtual < var->xres) {
996 "virtual X resolution (%d) is smaller than real\n", var->xres_virtual);
1000 if (var->yres_virtual < var->yres) {
1002 "virtual Y resolution (%d) is smaller than real\n", var->yres_virtual);
1005 if (var->yres_virtual > 0x7fff/nom)
1006 var->yres_virtual = 0x7fff/nom;
1007 if (var->xres_virtual > 0x7fff/nom)
1008 var->xres_virtual = 0x7fff/nom;
1014 riva_set_pattern(struct riva_par *par, int clr0, int clr1, int pat0, int pat1)
1016 RIVA_FIFO_FREE(par->riva, Patt, 4);
1017 NV_WR32(&par->riva.Patt->Color0, 0, clr0);
1018 NV_WR32(&par->riva.Patt->Color1, 0, clr1);
1019 NV_WR32(par->riva.Patt->Monochrome, 0, pat0);
1020 NV_WR32(par->riva.Patt->Monochrome, 4, pat1);
1023 /* acceleration routines */
1024 static inline void wait_for_idle(struct riva_par *par)
1026 while (par->riva.Busy(&par->riva));
1030 * Set ROP. Translate X rop into ROP3. Internal routine.
1033 riva_set_rop_solid(struct riva_par *par, int rop)
1035 riva_set_pattern(par, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF);
1036 RIVA_FIFO_FREE(par->riva, Rop, 1);
1037 NV_WR32(&par->riva.Rop->Rop3, 0, rop);
1041 static void riva_setup_accel(struct fb_info *info)
1043 struct riva_par *par = info->par;
1045 RIVA_FIFO_FREE(par->riva, Clip, 2);
1046 NV_WR32(&par->riva.Clip->TopLeft, 0, 0x0);
1047 NV_WR32(&par->riva.Clip->WidthHeight, 0,
1048 (info->var.xres_virtual & 0xffff) |
1049 (info->var.yres_virtual << 16));
1050 riva_set_rop_solid(par, 0xcc);
1055 * riva_get_cmap_len - query current color map length
1056 * @var: standard kernel fb changeable data
1059 * Get current color map length.
1062 * Length of color map
1065 * rivafb_setcolreg()
1067 static int riva_get_cmap_len(const struct fb_var_screeninfo *var)
1069 int rc = 256; /* reasonable default */
1071 switch (var->green.length) {
1073 rc = 256; /* 256 entries (2^8), 8 bpp and RGB8888 */
1076 rc = 32; /* 32 entries (2^5), 16 bpp, RGB555 */
1079 rc = 64; /* 64 entries (2^6), 16 bpp, RGB565 */
1082 /* should not occur */
1088 /* ------------------------------------------------------------------------- *
1090 * framebuffer operations
1092 * ------------------------------------------------------------------------- */
1094 static int rivafb_open(struct fb_info *info, int user)
1096 struct riva_par *par = info->par;
1097 int cnt = atomic_read(&par->ref_count);
1102 memset(&par->state, 0, sizeof(struct vgastate));
1103 par->state.flags = VGA_SAVE_MODE | VGA_SAVE_FONTS;
1104 /* save the DAC for Riva128 */
1105 if (par->riva.Architecture == NV_ARCH_03)
1106 par->state.flags |= VGA_SAVE_CMAP;
1107 save_vga(&par->state);
1109 /* vgaHWunlock() + riva unlock (0x7F) */
1110 CRTCout(par, 0x11, 0xFF);
1111 par->riva.LockUnlock(&par->riva, 0);
1113 riva_save_state(par, &par->initial_state);
1115 atomic_inc(&par->ref_count);
1120 static int rivafb_release(struct fb_info *info, int user)
1122 struct riva_par *par = info->par;
1123 int cnt = atomic_read(&par->ref_count);
1129 par->riva.LockUnlock(&par->riva, 0);
1130 par->riva.LoadStateExt(&par->riva, &par->initial_state.ext);
1131 riva_load_state(par, &par->initial_state);
1133 restore_vga(&par->state);
1135 par->riva.LockUnlock(&par->riva, 1);
1137 atomic_dec(&par->ref_count);
1142 static int rivafb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
1144 struct fb_videomode *mode;
1145 struct riva_par *par = info->par;
1146 int nom, den; /* translating from pixels->bytes */
1150 switch (var->bits_per_pixel) {
1152 var->red.offset = var->green.offset = var->blue.offset = 0;
1153 var->red.length = var->green.length = var->blue.length = 8;
1154 var->bits_per_pixel = 8;
1158 var->green.length = 5;
1161 var->bits_per_pixel = 16;
1162 /* The Riva128 supports RGB555 only */
1163 if (par->riva.Architecture == NV_ARCH_03)
1164 var->green.length = 5;
1165 if (var->green.length == 5) {
1166 /* 0rrrrrgg gggbbbbb */
1167 var->red.offset = 10;
1168 var->green.offset = 5;
1169 var->blue.offset = 0;
1170 var->red.length = 5;
1171 var->green.length = 5;
1172 var->blue.length = 5;
1174 /* rrrrrggg gggbbbbb */
1175 var->red.offset = 11;
1176 var->green.offset = 5;
1177 var->blue.offset = 0;
1178 var->red.length = 5;
1179 var->green.length = 6;
1180 var->blue.length = 5;
1186 var->red.length = var->green.length = var->blue.length = 8;
1187 var->bits_per_pixel = 32;
1188 var->red.offset = 16;
1189 var->green.offset = 8;
1190 var->blue.offset = 0;
1196 "mode %dx%dx%d rejected...color depth not supported.\n",
1197 var->xres, var->yres, var->bits_per_pixel);
1198 NVTRACE("EXIT, returning -EINVAL\n");
1203 if (!info->monspecs.vfmax || !info->monspecs.hfmax ||
1204 !info->monspecs.dclkmax || !fb_validate_mode(var, info))
1208 /* calculate modeline if supported by monitor */
1209 if (!mode_valid && info->monspecs.gtf) {
1210 if (!fb_get_mode(FB_MAXTIMINGS, 0, var, info))
1215 mode = fb_find_best_mode(var, &info->modelist);
1217 riva_update_var(var, mode);
1222 if (!mode_valid && info->monspecs.modedb_len)
1225 if (var->xres_virtual < var->xres)
1226 var->xres_virtual = var->xres;
1227 if (var->yres_virtual <= var->yres)
1228 var->yres_virtual = -1;
1229 if (rivafb_do_maximize(info, var, nom, den) < 0)
1232 if (var->xoffset < 0)
1234 if (var->yoffset < 0)
1237 /* truncate xoffset and yoffset to maximum if too high */
1238 if (var->xoffset > var->xres_virtual - var->xres)
1239 var->xoffset = var->xres_virtual - var->xres - 1;
1241 if (var->yoffset > var->yres_virtual - var->yres)
1242 var->yoffset = var->yres_virtual - var->yres - 1;
1244 var->red.msb_right =
1245 var->green.msb_right =
1246 var->blue.msb_right =
1247 var->transp.offset = var->transp.length = var->transp.msb_right = 0;
1252 static int rivafb_set_par(struct fb_info *info)
1254 struct riva_par *par = info->par;
1257 /* vgaHWunlock() + riva unlock (0x7F) */
1258 CRTCout(par, 0x11, 0xFF);
1259 par->riva.LockUnlock(&par->riva, 0);
1260 riva_load_video_mode(info);
1261 if(!(info->flags & FBINFO_HWACCEL_DISABLED))
1262 riva_setup_accel(info);
1264 par->cursor_reset = 1;
1265 info->fix.line_length = (info->var.xres_virtual * (info->var.bits_per_pixel >> 3));
1266 info->fix.visual = (info->var.bits_per_pixel == 8) ?
1267 FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_DIRECTCOLOR;
1269 if (info->flags & FBINFO_HWACCEL_DISABLED)
1270 info->pixmap.scan_align = 1;
1272 info->pixmap.scan_align = 4;
1278 * rivafb_pan_display
1279 * @var: standard kernel fb changeable data
1281 * @info: pointer to fb_info object containing info for current riva board
1284 * Pan (or wrap, depending on the `vmode' field) the display using the
1285 * `xoffset' and `yoffset' fields of the `var' structure.
1286 * If the values don't fit, return -EINVAL.
1288 * This call looks only at xoffset, yoffset and the FB_VMODE_YWRAP flag
1290 static int rivafb_pan_display(struct fb_var_screeninfo *var,
1291 struct fb_info *info)
1293 struct riva_par *par = info->par;
1297 base = var->yoffset * info->fix.line_length + var->xoffset;
1298 par->riva.SetStartAddress(&par->riva, base);
1303 static int rivafb_blank(int blank, struct fb_info *info)
1305 struct riva_par *par= info->par;
1306 unsigned char tmp, vesa;
1308 tmp = SEQin(par, 0x01) & ~0x20; /* screen on/off */
1309 vesa = CRTCin(par, 0x1a) & ~0xc0; /* sync on/off */
1317 case FB_BLANK_UNBLANK:
1318 case FB_BLANK_NORMAL:
1320 case FB_BLANK_VSYNC_SUSPEND:
1323 case FB_BLANK_HSYNC_SUSPEND:
1326 case FB_BLANK_POWERDOWN:
1331 SEQout(par, 0x01, tmp);
1332 CRTCout(par, 0x1a, vesa);
1334 riva_bl_set_power(info, blank);
1343 * @regno: register index
1344 * @red: red component
1345 * @green: green component
1346 * @blue: blue component
1347 * @transp: transparency
1348 * @info: pointer to fb_info object containing info for current riva board
1351 * Set a single color register. The values supplied have a 16 bit
1355 * Return != 0 for invalid regno.
1358 * fbcmap.c:fb_set_cmap()
1360 static int rivafb_setcolreg(unsigned regno, unsigned red, unsigned green,
1361 unsigned blue, unsigned transp,
1362 struct fb_info *info)
1364 struct riva_par *par = info->par;
1365 RIVA_HW_INST *chip = &par->riva;
1368 if (regno >= riva_get_cmap_len(&info->var))
1371 if (info->var.grayscale) {
1372 /* gray = 0.30*R + 0.59*G + 0.11*B */
1373 red = green = blue =
1374 (red * 77 + green * 151 + blue * 28) >> 8;
1377 if (regno < 16 && info->fix.visual == FB_VISUAL_DIRECTCOLOR) {
1378 ((u32 *) info->pseudo_palette)[regno] =
1379 (regno << info->var.red.offset) |
1380 (regno << info->var.green.offset) |
1381 (regno << info->var.blue.offset);
1383 * The Riva128 2D engine requires color information in
1384 * TrueColor format even if framebuffer is in DirectColor
1386 if (par->riva.Architecture == NV_ARCH_03) {
1387 switch (info->var.bits_per_pixel) {
1389 par->palette[regno] = ((red & 0xf800) >> 1) |
1390 ((green & 0xf800) >> 6) |
1391 ((blue & 0xf800) >> 11);
1394 par->palette[regno] = ((red & 0xff00) << 8) |
1395 ((green & 0xff00)) |
1396 ((blue & 0xff00) >> 8);
1402 switch (info->var.bits_per_pixel) {
1404 /* "transparent" stuff is completely ignored. */
1405 riva_wclut(chip, regno, red >> 8, green >> 8, blue >> 8);
1408 if (info->var.green.length == 5) {
1409 for (i = 0; i < 8; i++) {
1410 riva_wclut(chip, regno*8+i, red >> 8,
1411 green >> 8, blue >> 8);
1417 for (i = 0; i < 8; i++) {
1418 riva_wclut(chip, regno*8+i,
1419 red >> 8, green >> 8,
1423 riva_rclut(chip, regno*4, &r, &g, &b);
1424 for (i = 0; i < 4; i++)
1425 riva_wclut(chip, regno*4+i, r,
1430 riva_wclut(chip, regno, red >> 8, green >> 8, blue >> 8);
1440 * rivafb_fillrect - hardware accelerated color fill function
1441 * @info: pointer to fb_info structure
1442 * @rect: pointer to fb_fillrect structure
1445 * This function fills up a region of framebuffer memory with a solid
1446 * color with a choice of two different ROP's, copy or invert.
1451 static void rivafb_fillrect(struct fb_info *info, const struct fb_fillrect *rect)
1453 struct riva_par *par = info->par;
1454 u_int color, rop = 0;
1456 if ((info->flags & FBINFO_HWACCEL_DISABLED)) {
1457 cfb_fillrect(info, rect);
1461 if (info->var.bits_per_pixel == 8)
1462 color = rect->color;
1464 if (par->riva.Architecture != NV_ARCH_03)
1465 color = ((u32 *)info->pseudo_palette)[rect->color];
1467 color = par->palette[rect->color];
1470 switch (rect->rop) {
1480 riva_set_rop_solid(par, rop);
1482 RIVA_FIFO_FREE(par->riva, Bitmap, 1);
1483 NV_WR32(&par->riva.Bitmap->Color1A, 0, color);
1485 RIVA_FIFO_FREE(par->riva, Bitmap, 2);
1486 NV_WR32(&par->riva.Bitmap->UnclippedRectangle[0].TopLeft, 0,
1487 (rect->dx << 16) | rect->dy);
1489 NV_WR32(&par->riva.Bitmap->UnclippedRectangle[0].WidthHeight, 0,
1490 (rect->width << 16) | rect->height);
1492 riva_set_rop_solid(par, 0xcc);
1497 * rivafb_copyarea - hardware accelerated blit function
1498 * @info: pointer to fb_info structure
1499 * @region: pointer to fb_copyarea structure
1502 * This copies an area of pixels from one location to another
1507 static void rivafb_copyarea(struct fb_info *info, const struct fb_copyarea *region)
1509 struct riva_par *par = info->par;
1511 if ((info->flags & FBINFO_HWACCEL_DISABLED)) {
1512 cfb_copyarea(info, region);
1516 RIVA_FIFO_FREE(par->riva, Blt, 3);
1517 NV_WR32(&par->riva.Blt->TopLeftSrc, 0,
1518 (region->sy << 16) | region->sx);
1519 NV_WR32(&par->riva.Blt->TopLeftDst, 0,
1520 (region->dy << 16) | region->dx);
1522 NV_WR32(&par->riva.Blt->WidthHeight, 0,
1523 (region->height << 16) | region->width);
1527 static inline void convert_bgcolor_16(u32 *col)
1529 *col = ((*col & 0x0000F800) << 8)
1530 | ((*col & 0x00007E0) << 5)
1531 | ((*col & 0x0000001F) << 3)
1537 * rivafb_imageblit: hardware accelerated color expand function
1538 * @info: pointer to fb_info structure
1539 * @image: pointer to fb_image structure
1542 * If the source is a monochrome bitmap, the function fills up a a region
1543 * of framebuffer memory with pixels whose color is determined by the bit
1544 * setting of the bitmap, 1 - foreground, 0 - background.
1546 * If the source is not a monochrome bitmap, color expansion is not done.
1547 * In this case, it is channeled to a software function.
1552 static void rivafb_imageblit(struct fb_info *info,
1553 const struct fb_image *image)
1555 struct riva_par *par = info->par;
1556 u32 fgx = 0, bgx = 0, width, tmp;
1557 u8 *cdat = (u8 *) image->data;
1558 volatile u32 __iomem *d;
1561 if ((info->flags & FBINFO_HWACCEL_DISABLED) || image->depth != 1) {
1562 cfb_imageblit(info, image);
1566 switch (info->var.bits_per_pixel) {
1568 fgx = image->fg_color;
1569 bgx = image->bg_color;
1573 if (par->riva.Architecture != NV_ARCH_03) {
1574 fgx = ((u32 *)info->pseudo_palette)[image->fg_color];
1575 bgx = ((u32 *)info->pseudo_palette)[image->bg_color];
1577 fgx = par->palette[image->fg_color];
1578 bgx = par->palette[image->bg_color];
1580 if (info->var.green.length == 6)
1581 convert_bgcolor_16(&bgx);
1585 RIVA_FIFO_FREE(par->riva, Bitmap, 7);
1586 NV_WR32(&par->riva.Bitmap->ClipE.TopLeft, 0,
1587 (image->dy << 16) | (image->dx & 0xFFFF));
1588 NV_WR32(&par->riva.Bitmap->ClipE.BottomRight, 0,
1589 (((image->dy + image->height) << 16) |
1590 ((image->dx + image->width) & 0xffff)));
1591 NV_WR32(&par->riva.Bitmap->Color0E, 0, bgx);
1592 NV_WR32(&par->riva.Bitmap->Color1E, 0, fgx);
1593 NV_WR32(&par->riva.Bitmap->WidthHeightInE, 0,
1594 (image->height << 16) | ((image->width + 31) & ~31));
1595 NV_WR32(&par->riva.Bitmap->WidthHeightOutE, 0,
1596 (image->height << 16) | ((image->width + 31) & ~31));
1597 NV_WR32(&par->riva.Bitmap->PointE, 0,
1598 (image->dy << 16) | (image->dx & 0xFFFF));
1600 d = &par->riva.Bitmap->MonochromeData01E;
1602 width = (image->width + 31)/32;
1603 size = width * image->height;
1604 while (size >= 16) {
1605 RIVA_FIFO_FREE(par->riva, Bitmap, 16);
1606 for (i = 0; i < 16; i++) {
1607 tmp = *((u32 *)cdat);
1608 cdat = (u8 *)((u32 *)cdat + 1);
1609 reverse_order(&tmp);
1610 NV_WR32(d, i*4, tmp);
1615 RIVA_FIFO_FREE(par->riva, Bitmap, size);
1616 for (i = 0; i < size; i++) {
1617 tmp = *((u32 *) cdat);
1618 cdat = (u8 *)((u32 *)cdat + 1);
1619 reverse_order(&tmp);
1620 NV_WR32(d, i*4, tmp);
1626 * rivafb_cursor - hardware cursor function
1627 * @info: pointer to info structure
1628 * @cursor: pointer to fbcursor structure
1631 * A cursor function that supports displaying a cursor image via hardware.
1632 * Within the kernel, copy and invert rops are supported. If exported
1633 * to user space, only the copy rop will be supported.
1638 static int rivafb_cursor(struct fb_info *info, struct fb_cursor *cursor)
1640 struct riva_par *par = info->par;
1641 u8 data[MAX_CURS * MAX_CURS/8];
1642 int i, set = cursor->set;
1645 if (cursor->image.width > MAX_CURS || cursor->image.height > MAX_CURS)
1648 par->riva.ShowHideCursor(&par->riva, 0);
1650 if (par->cursor_reset) {
1651 set = FB_CUR_SETALL;
1652 par->cursor_reset = 0;
1655 if (set & FB_CUR_SETSIZE)
1656 memset_io(par->riva.CURSOR, 0, MAX_CURS * MAX_CURS * 2);
1658 if (set & FB_CUR_SETPOS) {
1661 yy = cursor->image.dy - info->var.yoffset;
1662 xx = cursor->image.dx - info->var.xoffset;
1666 NV_WR32(par->riva.PRAMDAC, 0x0000300, temp);
1670 if (set & (FB_CUR_SETSHAPE | FB_CUR_SETCMAP | FB_CUR_SETIMAGE)) {
1671 u32 bg_idx = cursor->image.bg_color;
1672 u32 fg_idx = cursor->image.fg_color;
1673 u32 s_pitch = (cursor->image.width+7) >> 3;
1674 u32 d_pitch = MAX_CURS/8;
1675 u8 *dat = (u8 *) cursor->image.data;
1676 u8 *msk = (u8 *) cursor->mask;
1679 src = kmalloc(s_pitch * cursor->image.height, GFP_ATOMIC);
1682 switch (cursor->rop) {
1684 for (i = 0; i < s_pitch * cursor->image.height; i++)
1685 src[i] = dat[i] ^ msk[i];
1689 for (i = 0; i < s_pitch * cursor->image.height; i++)
1690 src[i] = dat[i] & msk[i];
1694 fb_pad_aligned_buffer(data, d_pitch, src, s_pitch,
1695 cursor->image.height);
1697 bg = ((info->cmap.red[bg_idx] & 0xf8) << 7) |
1698 ((info->cmap.green[bg_idx] & 0xf8) << 2) |
1699 ((info->cmap.blue[bg_idx] & 0xf8) >> 3) |
1702 fg = ((info->cmap.red[fg_idx] & 0xf8) << 7) |
1703 ((info->cmap.green[fg_idx] & 0xf8) << 2) |
1704 ((info->cmap.blue[fg_idx] & 0xf8) >> 3) |
1707 par->riva.LockUnlock(&par->riva, 0);
1709 rivafb_load_cursor_image(par, data, bg, fg,
1710 cursor->image.width,
1711 cursor->image.height);
1717 par->riva.ShowHideCursor(&par->riva, 1);
1722 static int rivafb_sync(struct fb_info *info)
1724 struct riva_par *par = info->par;
1730 /* ------------------------------------------------------------------------- *
1732 * initialization helper functions
1734 * ------------------------------------------------------------------------- */
1736 /* kernel interface */
1737 static struct fb_ops riva_fb_ops = {
1738 .owner = THIS_MODULE,
1739 .fb_open = rivafb_open,
1740 .fb_release = rivafb_release,
1741 .fb_check_var = rivafb_check_var,
1742 .fb_set_par = rivafb_set_par,
1743 .fb_setcolreg = rivafb_setcolreg,
1744 .fb_pan_display = rivafb_pan_display,
1745 .fb_blank = rivafb_blank,
1746 .fb_fillrect = rivafb_fillrect,
1747 .fb_copyarea = rivafb_copyarea,
1748 .fb_imageblit = rivafb_imageblit,
1749 .fb_cursor = rivafb_cursor,
1750 .fb_sync = rivafb_sync,
1753 static int __devinit riva_set_fbinfo(struct fb_info *info)
1755 unsigned int cmap_len;
1756 struct riva_par *par = info->par;
1759 info->flags = FBINFO_DEFAULT
1760 | FBINFO_HWACCEL_XPAN
1761 | FBINFO_HWACCEL_YPAN
1762 | FBINFO_HWACCEL_COPYAREA
1763 | FBINFO_HWACCEL_FILLRECT
1764 | FBINFO_HWACCEL_IMAGEBLIT;
1766 /* Accel seems to not work properly on NV30 yet...*/
1767 if ((par->riva.Architecture == NV_ARCH_30) || noaccel) {
1768 printk(KERN_DEBUG PFX "disabling acceleration\n");
1769 info->flags |= FBINFO_HWACCEL_DISABLED;
1772 info->var = rivafb_default_var;
1773 info->fix.visual = (info->var.bits_per_pixel == 8) ?
1774 FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_DIRECTCOLOR;
1776 info->pseudo_palette = par->pseudo_palette;
1778 cmap_len = riva_get_cmap_len(&info->var);
1779 fb_alloc_cmap(&info->cmap, cmap_len, 0);
1781 info->pixmap.size = 8 * 1024;
1782 info->pixmap.buf_align = 4;
1783 info->pixmap.access_align = 32;
1784 info->pixmap.flags = FB_PIXMAP_SYSTEM;
1785 info->var.yres_virtual = -1;
1787 return (rivafb_check_var(&info->var, info));
1790 #ifdef CONFIG_PPC_OF
1791 static int __devinit riva_get_EDID_OF(struct fb_info *info, struct pci_dev *pd)
1793 struct riva_par *par = info->par;
1794 struct device_node *dp;
1795 const unsigned char *pedid = NULL;
1796 const unsigned char *disptype = NULL;
1797 static char *propnames[] = {
1798 "DFP,EDID", "LCD,EDID", "EDID", "EDID1", "EDID,B", "EDID,A", NULL };
1802 dp = pci_device_to_OF_node(pd);
1803 for (; dp != NULL; dp = dp->child) {
1804 disptype = get_property(dp, "display-type", NULL);
1805 if (disptype == NULL)
1807 if (strncmp(disptype, "LCD", 3) != 0)
1809 for (i = 0; propnames[i] != NULL; ++i) {
1810 pedid = get_property(dp, propnames[i], NULL);
1811 if (pedid != NULL) {
1812 par->EDID = (unsigned char *)pedid;
1813 NVTRACE("LCD found.\n");
1821 #endif /* CONFIG_PPC_OF */
1823 #if defined(CONFIG_FB_RIVA_I2C) && !defined(CONFIG_PPC_OF)
1824 static int __devinit riva_get_EDID_i2c(struct fb_info *info)
1826 struct riva_par *par = info->par;
1827 struct fb_var_screeninfo var;
1831 riva_create_i2c_busses(par);
1832 for (i = 0; i < par->bus; i++) {
1833 riva_probe_i2c_connector(par, i+1, &par->EDID);
1834 if (par->EDID && !fb_parse_edid(par->EDID, &var)) {
1835 printk(PFX "Found EDID Block from BUS %i\n", i);
1841 return (par->EDID) ? 1 : 0;
1843 #endif /* CONFIG_FB_RIVA_I2C */
1845 static void __devinit riva_update_default_var(struct fb_var_screeninfo *var,
1846 struct fb_info *info)
1848 struct fb_monspecs *specs = &info->monspecs;
1849 struct fb_videomode modedb;
1852 /* respect mode options */
1854 fb_find_mode(var, info, mode_option,
1855 specs->modedb, specs->modedb_len,
1857 } else if (specs->modedb != NULL) {
1858 /* get preferred timing */
1859 if (info->monspecs.misc & FB_MISC_1ST_DETAIL) {
1862 for (i = 0; i < specs->modedb_len; i++) {
1863 if (specs->modedb[i].flag & FB_MODE_IS_FIRST) {
1864 modedb = specs->modedb[i];
1869 /* otherwise, get first mode in database */
1870 modedb = specs->modedb[0];
1872 var->bits_per_pixel = 8;
1873 riva_update_var(var, &modedb);
1879 static void __devinit riva_get_EDID(struct fb_info *info, struct pci_dev *pdev)
1882 #ifdef CONFIG_PPC_OF
1883 if (!riva_get_EDID_OF(info, pdev))
1884 printk(PFX "could not retrieve EDID from OF\n");
1885 #elif defined(CONFIG_FB_RIVA_I2C)
1886 if (!riva_get_EDID_i2c(info))
1887 printk(PFX "could not retrieve EDID from DDC/I2C\n");
1893 static void __devinit riva_get_edidinfo(struct fb_info *info)
1895 struct fb_var_screeninfo *var = &rivafb_default_var;
1896 struct riva_par *par = info->par;
1898 fb_edid_to_monspecs(par->EDID, &info->monspecs);
1899 fb_videomode_to_modelist(info->monspecs.modedb, info->monspecs.modedb_len,
1901 riva_update_default_var(var, info);
1903 /* if user specified flatpanel, we respect that */
1904 if (info->monspecs.input & FB_DISP_DDI)
1908 /* ------------------------------------------------------------------------- *
1912 * ------------------------------------------------------------------------- */
1914 static u32 __devinit riva_get_arch(struct pci_dev *pd)
1918 switch (pd->device & 0x0ff0) {
1919 case 0x0100: /* GeForce 256 */
1920 case 0x0110: /* GeForce2 MX */
1921 case 0x0150: /* GeForce2 */
1922 case 0x0170: /* GeForce4 MX */
1923 case 0x0180: /* GeForce4 MX (8x AGP) */
1924 case 0x01A0: /* nForce */
1925 case 0x01F0: /* nForce2 */
1928 case 0x0200: /* GeForce3 */
1929 case 0x0250: /* GeForce4 Ti */
1930 case 0x0280: /* GeForce4 Ti (8x AGP) */
1933 case 0x0300: /* GeForceFX 5800 */
1934 case 0x0310: /* GeForceFX 5600 */
1935 case 0x0320: /* GeForceFX 5200 */
1936 case 0x0330: /* GeForceFX 5900 */
1937 case 0x0340: /* GeForceFX 5700 */
1940 case 0x0020: /* TNT, TNT2 */
1943 case 0x0010: /* Riva128 */
1946 default: /* unknown architecture */
1952 static int __devinit rivafb_probe(struct pci_dev *pd,
1953 const struct pci_device_id *ent)
1955 struct riva_par *default_par;
1956 struct fb_info *info;
1962 info = framebuffer_alloc(sizeof(struct riva_par), &pd->dev);
1964 printk (KERN_ERR PFX "could not allocate memory\n");
1968 default_par = info->par;
1969 default_par->pdev = pd;
1971 info->pixmap.addr = kmalloc(8 * 1024, GFP_KERNEL);
1972 if (info->pixmap.addr == NULL) {
1974 goto err_framebuffer_release;
1976 memset(info->pixmap.addr, 0, 8 * 1024);
1978 ret = pci_enable_device(pd);
1980 printk(KERN_ERR PFX "cannot enable PCI device\n");
1981 goto err_free_pixmap;
1984 ret = pci_request_regions(pd, "rivafb");
1986 printk(KERN_ERR PFX "cannot request PCI regions\n");
1987 goto err_disable_device;
1990 default_par->riva.Architecture = riva_get_arch(pd);
1992 default_par->Chipset = (pd->vendor << 16) | pd->device;
1993 printk(KERN_INFO PFX "nVidia device/chipset %X\n",default_par->Chipset);
1995 if(default_par->riva.Architecture == 0) {
1996 printk(KERN_ERR PFX "unknown NV_ARCH\n");
1998 goto err_release_region;
2000 if(default_par->riva.Architecture == NV_ARCH_10 ||
2001 default_par->riva.Architecture == NV_ARCH_20 ||
2002 default_par->riva.Architecture == NV_ARCH_30) {
2003 sprintf(rivafb_fix.id, "NV%x", (pd->device & 0x0ff0) >> 4);
2005 sprintf(rivafb_fix.id, "NV%x", default_par->riva.Architecture);
2008 default_par->FlatPanel = flatpanel;
2010 printk(KERN_INFO PFX "flatpanel support enabled\n");
2011 default_par->forceCRTC = forceCRTC;
2013 rivafb_fix.mmio_len = pci_resource_len(pd, 0);
2014 rivafb_fix.smem_len = pci_resource_len(pd, 1);
2017 /* enable IO and mem if not already done */
2020 pci_read_config_word(pd, PCI_COMMAND, &cmd);
2021 cmd |= (PCI_COMMAND_IO | PCI_COMMAND_MEMORY);
2022 pci_write_config_word(pd, PCI_COMMAND, cmd);
2025 rivafb_fix.mmio_start = pci_resource_start(pd, 0);
2026 rivafb_fix.smem_start = pci_resource_start(pd, 1);
2028 default_par->ctrl_base = ioremap(rivafb_fix.mmio_start,
2029 rivafb_fix.mmio_len);
2030 if (!default_par->ctrl_base) {
2031 printk(KERN_ERR PFX "cannot ioremap MMIO base\n");
2033 goto err_release_region;
2036 switch (default_par->riva.Architecture) {
2038 /* Riva128's PRAMIN is in the "framebuffer" space
2039 * Since these cards were never made with more than 8 megabytes
2040 * we can safely allocate this separately.
2042 default_par->riva.PRAMIN = ioremap(rivafb_fix.smem_start + 0x00C00000, 0x00008000);
2043 if (!default_par->riva.PRAMIN) {
2044 printk(KERN_ERR PFX "cannot ioremap PRAMIN region\n");
2046 goto err_iounmap_ctrl_base;
2053 default_par->riva.PCRTC0 =
2054 (u32 __iomem *)(default_par->ctrl_base + 0x00600000);
2055 default_par->riva.PRAMIN =
2056 (u32 __iomem *)(default_par->ctrl_base + 0x00710000);
2059 riva_common_setup(default_par);
2061 if (default_par->riva.Architecture == NV_ARCH_03) {
2062 default_par->riva.PCRTC = default_par->riva.PCRTC0
2063 = default_par->riva.PGRAPH;
2066 rivafb_fix.smem_len = riva_get_memlen(default_par) * 1024;
2067 default_par->dclk_max = riva_get_maxdclk(default_par) * 1000;
2068 info->screen_base = ioremap(rivafb_fix.smem_start,
2069 rivafb_fix.smem_len);
2070 if (!info->screen_base) {
2071 printk(KERN_ERR PFX "cannot ioremap FB base\n");
2073 goto err_iounmap_pramin;
2078 default_par->mtrr.vram = mtrr_add(rivafb_fix.smem_start,
2079 rivafb_fix.smem_len,
2080 MTRR_TYPE_WRCOMB, 1);
2081 if (default_par->mtrr.vram < 0) {
2082 printk(KERN_ERR PFX "unable to setup MTRR\n");
2084 default_par->mtrr.vram_valid = 1;
2085 /* let there be speed */
2086 printk(KERN_INFO PFX "RIVA MTRR set to ON\n");
2089 #endif /* CONFIG_MTRR */
2091 info->fbops = &riva_fb_ops;
2092 info->fix = rivafb_fix;
2093 riva_get_EDID(info, pd);
2094 riva_get_edidinfo(info);
2096 ret=riva_set_fbinfo(info);
2098 printk(KERN_ERR PFX "error setting initial video mode\n");
2099 goto err_iounmap_screen_base;
2102 fb_destroy_modedb(info->monspecs.modedb);
2103 info->monspecs.modedb = NULL;
2105 pci_set_drvdata(pd, info);
2106 riva_bl_init(info->par);
2107 ret = register_framebuffer(info);
2110 "error registering riva framebuffer\n");
2111 goto err_iounmap_screen_base;
2114 printk(KERN_INFO PFX
2115 "PCI nVidia %s framebuffer ver %s (%dMB @ 0x%lX)\n",
2118 info->fix.smem_len / (1024 * 1024),
2119 info->fix.smem_start);
2124 err_iounmap_screen_base:
2125 #ifdef CONFIG_FB_RIVA_I2C
2126 riva_delete_i2c_busses(info->par);
2128 iounmap(info->screen_base);
2130 if (default_par->riva.Architecture == NV_ARCH_03)
2131 iounmap(default_par->riva.PRAMIN);
2132 err_iounmap_ctrl_base:
2133 iounmap(default_par->ctrl_base);
2135 pci_release_regions(pd);
2138 kfree(info->pixmap.addr);
2139 err_framebuffer_release:
2140 framebuffer_release(info);
2145 static void __exit rivafb_remove(struct pci_dev *pd)
2147 struct fb_info *info = pci_get_drvdata(pd);
2148 struct riva_par *par = info->par;
2154 #ifdef CONFIG_FB_RIVA_I2C
2155 riva_delete_i2c_busses(par);
2159 unregister_framebuffer(info);
2161 if (par->mtrr.vram_valid)
2162 mtrr_del(par->mtrr.vram, info->fix.smem_start,
2163 info->fix.smem_len);
2164 #endif /* CONFIG_MTRR */
2166 iounmap(par->ctrl_base);
2167 iounmap(info->screen_base);
2168 if (par->riva.Architecture == NV_ARCH_03)
2169 iounmap(par->riva.PRAMIN);
2170 pci_release_regions(pd);
2171 kfree(info->pixmap.addr);
2172 framebuffer_release(info);
2173 pci_set_drvdata(pd, NULL);
2177 /* ------------------------------------------------------------------------- *
2181 * ------------------------------------------------------------------------- */
2184 static int __init rivafb_setup(char *options)
2189 if (!options || !*options)
2192 while ((this_opt = strsep(&options, ",")) != NULL) {
2193 if (!strncmp(this_opt, "forceCRTC", 9)) {
2197 if (!*p || !*(++p)) continue;
2198 forceCRTC = *p - '0';
2199 if (forceCRTC < 0 || forceCRTC > 1)
2201 } else if (!strncmp(this_opt, "flatpanel", 9)) {
2204 } else if (!strncmp(this_opt, "nomtrr", 6)) {
2207 } else if (!strncmp(this_opt, "strictmode", 10)) {
2209 } else if (!strncmp(this_opt, "noaccel", 7)) {
2212 mode_option = this_opt;
2217 #endif /* !MODULE */
2219 static struct pci_driver rivafb_driver = {
2221 .id_table = rivafb_pci_tbl,
2222 .probe = rivafb_probe,
2223 .remove = __exit_p(rivafb_remove),
2228 /* ------------------------------------------------------------------------- *
2232 * ------------------------------------------------------------------------- */
2234 static int __devinit rivafb_init(void)
2237 char *option = NULL;
2239 if (fb_get_options("rivafb", &option))
2241 rivafb_setup(option);
2243 return pci_register_driver(&rivafb_driver);
2247 module_init(rivafb_init);
2250 static void __exit rivafb_exit(void)
2252 pci_unregister_driver(&rivafb_driver);
2255 module_exit(rivafb_exit);
2258 module_param(noaccel, bool, 0);
2259 MODULE_PARM_DESC(noaccel, "bool: disable acceleration");
2260 module_param(flatpanel, int, 0);
2261 MODULE_PARM_DESC(flatpanel, "Enables experimental flat panel support for some chipsets. (0 or 1=enabled) (default=0)");
2262 module_param(forceCRTC, int, 0);
2263 MODULE_PARM_DESC(forceCRTC, "Forces usage of a particular CRTC in case autodetection fails. (0 or 1) (default=autodetect)");
2265 module_param(nomtrr, bool, 0);
2266 MODULE_PARM_DESC(nomtrr, "Disables MTRR support (0 or 1=disabled) (default=0)");
2268 module_param(strictmode, bool, 0);
2269 MODULE_PARM_DESC(strictmode, "Only use video modes from EDID");
2271 MODULE_AUTHOR("Ani Joshi, maintainer");
2272 MODULE_DESCRIPTION("Framebuffer driver for nVidia Riva 128, TNT, TNT2, and the GeForce series");
2273 MODULE_LICENSE("GPL");