2 * linux/drivers/video/riva/fbdev.c - nVidia RIVA 128/TNT/TNT2 fb driver
4 * Maintained by Ani Joshi <ajoshi@shell.unixbox.com>
6 * Copyright 1999-2000 Jeff Garzik
10 * Ani Joshi: Lots of debugging and cleanup work, really helped
11 * get the driver going
13 * Ferenc Bakonyi: Bug fixes, cleanup, modularization
15 * Jindrich Makovicka: Accel code help, hw cursor, mtrr
17 * Paul Richards: Bug fixes, updates
19 * Initial template from skeletonfb.c, created 28 Dec 1997 by Geert Uytterhoeven
20 * Includes riva_hw.c from nVidia, see copyright below.
21 * KGI code provided the basis for state storage, init, and mode switching.
23 * This file is subject to the terms and conditions of the GNU General Public
24 * License. See the file COPYING in the main directory of this archive
27 * Known bugs and issues:
28 * restoring text mode fails
29 * doublescan modes are broken
32 #include <linux/config.h>
33 #include <linux/module.h>
34 #include <linux/kernel.h>
35 #include <linux/errno.h>
36 #include <linux/string.h>
38 #include <linux/tty.h>
39 #include <linux/slab.h>
40 #include <linux/delay.h>
42 #include <linux/init.h>
43 #include <linux/pci.h>
49 #include <asm/pci-bridge.h>
51 #ifdef CONFIG_PMAC_BACKLIGHT
52 #include <asm/backlight.h>
58 #ifndef CONFIG_PCI /* sanity check */
59 #error This driver requires PCI support.
62 /* version number of this driver */
63 #define RIVAFB_VERSION "0.9.5b"
65 /* ------------------------------------------------------------------------- *
67 * various helpful macros and constants
69 * ------------------------------------------------------------------------- */
70 #ifdef CONFIG_FB_RIVA_DEBUG
71 #define NVTRACE printk
73 #define NVTRACE if(0) printk
76 #define NVTRACE_ENTER(...) NVTRACE("%s START\n", __FUNCTION__)
77 #define NVTRACE_LEAVE(...) NVTRACE("%s END\n", __FUNCTION__)
79 #ifdef CONFIG_FB_RIVA_DEBUG
80 #define assert(expr) \
82 printk( "Assertion failed! %s,%s,%s,line=%d\n",\
83 #expr,__FILE__,__FUNCTION__,__LINE__); \
90 #define PFX "rivafb: "
92 /* macro that allows you to set overflow bits */
93 #define SetBitField(value,from,to) SetBF(to,GetBF(value,from))
94 #define SetBit(n) (1<<(n))
95 #define Set8Bits(value) ((value)&0xff)
97 /* HW cursor parameters */
100 /* ------------------------------------------------------------------------- *
104 * ------------------------------------------------------------------------- */
106 static int rivafb_blank(int blank, struct fb_info *info);
108 /* ------------------------------------------------------------------------- *
110 * card identification
112 * ------------------------------------------------------------------------- */
114 static struct pci_device_id rivafb_pci_tbl[] = {
115 { PCI_VENDOR_ID_NVIDIA_SGS, PCI_DEVICE_ID_NVIDIA_SGS_RIVA128,
116 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
117 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_TNT,
118 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
119 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_TNT2,
120 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
121 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_UTNT2,
122 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
123 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_VTNT2,
124 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
125 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_UVTNT2,
126 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
127 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_ITNT2,
128 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
129 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_SDR,
130 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
131 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_DDR,
132 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
133 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO,
134 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
135 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE2_MX,
136 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
137 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE2_MX2,
138 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
139 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE2_GO,
140 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
141 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO2_MXR,
142 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
143 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE2_GTS,
144 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
145 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE2_GTS2,
146 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
147 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE2_ULTRA,
148 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
149 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO2_PRO,
150 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
151 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_460,
152 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
153 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_440,
154 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
155 // NF2/IGP version, GeForce 4 MX, NV18
156 { PCI_VENDOR_ID_NVIDIA, 0x01f0,
157 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
158 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_420,
159 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
160 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_440_GO,
161 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
162 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_420_GO,
163 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
164 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_420_GO_M32,
165 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
166 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_500XGL,
167 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
168 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_440_GO_M64,
169 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
170 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_200,
171 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
172 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_550XGL,
173 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
174 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_500_GOGL,
175 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
176 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_IGEFORCE2,
177 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
178 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE3,
179 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
180 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE3_1,
181 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
182 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE3_2,
183 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
184 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO_DDC,
185 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
186 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI_4600,
187 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
188 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI_4400,
189 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
190 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI_4200,
191 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
192 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_900XGL,
193 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
194 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_750XGL,
195 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
196 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_700XGL,
197 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
198 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_GO_5200,
199 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
200 { 0, } /* terminate list */
202 MODULE_DEVICE_TABLE(pci, rivafb_pci_tbl);
204 /* ------------------------------------------------------------------------- *
208 * ------------------------------------------------------------------------- */
210 /* command line data, set in rivafb_setup() */
211 static int flatpanel __devinitdata = -1; /* Autodetect later */
212 static int forceCRTC __devinitdata = -1;
213 static int noaccel __devinitdata = 0;
215 static int nomtrr __devinitdata = 0;
218 static char *mode_option __devinitdata = NULL;
219 static int strictmode = 0;
221 static struct fb_fix_screeninfo __devinitdata rivafb_fix = {
222 .type = FB_TYPE_PACKED_PIXELS,
227 static struct fb_var_screeninfo __devinitdata rivafb_default_var = {
237 .activate = FB_ACTIVATE_NOW,
247 .vmode = FB_VMODE_NONINTERLACED
251 static const struct riva_regs reg_template = {
252 {0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, /* ATTR */
253 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F,
254 0x41, 0x01, 0x0F, 0x00, 0x00},
255 {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* CRT */
256 0x00, 0x00, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00,
257 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE3, /* 0x10 */
258 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
259 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 0x20 */
260 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
261 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 0x30 */
262 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
265 {0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x05, 0x0F, /* GRA */
267 {0x03, 0x01, 0x0F, 0x00, 0x0E}, /* SEQ */
274 #ifdef CONFIG_PMAC_BACKLIGHT
276 static int riva_backlight_levels[] = {
295 static int riva_set_backlight_enable(int on, int level, void *data);
296 static int riva_set_backlight_level(int level, void *data);
297 static struct backlight_controller riva_backlight_controller = {
298 riva_set_backlight_enable,
299 riva_set_backlight_level
301 #endif /* CONFIG_PMAC_BACKLIGHT */
303 /* ------------------------------------------------------------------------- *
307 * ------------------------------------------------------------------------- */
309 static inline void CRTCout(struct riva_par *par, unsigned char index,
312 VGA_WR08(par->riva.PCIO, 0x3d4, index);
313 VGA_WR08(par->riva.PCIO, 0x3d5, val);
316 static inline unsigned char CRTCin(struct riva_par *par,
319 VGA_WR08(par->riva.PCIO, 0x3d4, index);
320 return (VGA_RD08(par->riva.PCIO, 0x3d5));
323 static inline void GRAout(struct riva_par *par, unsigned char index,
326 VGA_WR08(par->riva.PVIO, 0x3ce, index);
327 VGA_WR08(par->riva.PVIO, 0x3cf, val);
330 static inline unsigned char GRAin(struct riva_par *par,
333 VGA_WR08(par->riva.PVIO, 0x3ce, index);
334 return (VGA_RD08(par->riva.PVIO, 0x3cf));
337 static inline void SEQout(struct riva_par *par, unsigned char index,
340 VGA_WR08(par->riva.PVIO, 0x3c4, index);
341 VGA_WR08(par->riva.PVIO, 0x3c5, val);
344 static inline unsigned char SEQin(struct riva_par *par,
347 VGA_WR08(par->riva.PVIO, 0x3c4, index);
348 return (VGA_RD08(par->riva.PVIO, 0x3c5));
351 static inline void ATTRout(struct riva_par *par, unsigned char index,
354 VGA_WR08(par->riva.PCIO, 0x3c0, index);
355 VGA_WR08(par->riva.PCIO, 0x3c0, val);
358 static inline unsigned char ATTRin(struct riva_par *par,
361 VGA_WR08(par->riva.PCIO, 0x3c0, index);
362 return (VGA_RD08(par->riva.PCIO, 0x3c1));
365 static inline void MISCout(struct riva_par *par, unsigned char val)
367 VGA_WR08(par->riva.PVIO, 0x3c2, val);
370 static inline unsigned char MISCin(struct riva_par *par)
372 return (VGA_RD08(par->riva.PVIO, 0x3cc));
375 static u8 byte_rev[256] = {
376 0x00, 0x80, 0x40, 0xc0, 0x20, 0xa0, 0x60, 0xe0,
377 0x10, 0x90, 0x50, 0xd0, 0x30, 0xb0, 0x70, 0xf0,
378 0x08, 0x88, 0x48, 0xc8, 0x28, 0xa8, 0x68, 0xe8,
379 0x18, 0x98, 0x58, 0xd8, 0x38, 0xb8, 0x78, 0xf8,
380 0x04, 0x84, 0x44, 0xc4, 0x24, 0xa4, 0x64, 0xe4,
381 0x14, 0x94, 0x54, 0xd4, 0x34, 0xb4, 0x74, 0xf4,
382 0x0c, 0x8c, 0x4c, 0xcc, 0x2c, 0xac, 0x6c, 0xec,
383 0x1c, 0x9c, 0x5c, 0xdc, 0x3c, 0xbc, 0x7c, 0xfc,
384 0x02, 0x82, 0x42, 0xc2, 0x22, 0xa2, 0x62, 0xe2,
385 0x12, 0x92, 0x52, 0xd2, 0x32, 0xb2, 0x72, 0xf2,
386 0x0a, 0x8a, 0x4a, 0xca, 0x2a, 0xaa, 0x6a, 0xea,
387 0x1a, 0x9a, 0x5a, 0xda, 0x3a, 0xba, 0x7a, 0xfa,
388 0x06, 0x86, 0x46, 0xc6, 0x26, 0xa6, 0x66, 0xe6,
389 0x16, 0x96, 0x56, 0xd6, 0x36, 0xb6, 0x76, 0xf6,
390 0x0e, 0x8e, 0x4e, 0xce, 0x2e, 0xae, 0x6e, 0xee,
391 0x1e, 0x9e, 0x5e, 0xde, 0x3e, 0xbe, 0x7e, 0xfe,
392 0x01, 0x81, 0x41, 0xc1, 0x21, 0xa1, 0x61, 0xe1,
393 0x11, 0x91, 0x51, 0xd1, 0x31, 0xb1, 0x71, 0xf1,
394 0x09, 0x89, 0x49, 0xc9, 0x29, 0xa9, 0x69, 0xe9,
395 0x19, 0x99, 0x59, 0xd9, 0x39, 0xb9, 0x79, 0xf9,
396 0x05, 0x85, 0x45, 0xc5, 0x25, 0xa5, 0x65, 0xe5,
397 0x15, 0x95, 0x55, 0xd5, 0x35, 0xb5, 0x75, 0xf5,
398 0x0d, 0x8d, 0x4d, 0xcd, 0x2d, 0xad, 0x6d, 0xed,
399 0x1d, 0x9d, 0x5d, 0xdd, 0x3d, 0xbd, 0x7d, 0xfd,
400 0x03, 0x83, 0x43, 0xc3, 0x23, 0xa3, 0x63, 0xe3,
401 0x13, 0x93, 0x53, 0xd3, 0x33, 0xb3, 0x73, 0xf3,
402 0x0b, 0x8b, 0x4b, 0xcb, 0x2b, 0xab, 0x6b, 0xeb,
403 0x1b, 0x9b, 0x5b, 0xdb, 0x3b, 0xbb, 0x7b, 0xfb,
404 0x07, 0x87, 0x47, 0xc7, 0x27, 0xa7, 0x67, 0xe7,
405 0x17, 0x97, 0x57, 0xd7, 0x37, 0xb7, 0x77, 0xf7,
406 0x0f, 0x8f, 0x4f, 0xcf, 0x2f, 0xaf, 0x6f, 0xef,
407 0x1f, 0x9f, 0x5f, 0xdf, 0x3f, 0xbf, 0x7f, 0xff,
410 static inline void reverse_order(u32 *l)
413 *a = byte_rev[*a], a++;
414 *a = byte_rev[*a], a++;
415 *a = byte_rev[*a], a++;
419 /* ------------------------------------------------------------------------- *
423 * ------------------------------------------------------------------------- */
426 * rivafb_load_cursor_image - load cursor image to hardware
427 * @data: address to monochrome bitmap (1 = foreground color, 0 = background)
428 * @par: pointer to private data
429 * @w: width of cursor image in pixels
430 * @h: height of cursor image in scanlines
431 * @bg: background color (ARGB1555) - alpha bit determines opacity
432 * @fg: foreground color (ARGB1555)
435 * Loads cursor image based on a monochrome source and mask bitmap. The
436 * image bits determines the color of the pixel, 0 for background, 1 for
437 * foreground. Only the affected region (as determined by @w and @h
438 * parameters) will be updated.
443 static void rivafb_load_cursor_image(struct riva_par *par, u8 *data8,
444 u16 bg, u16 fg, u32 w, u32 h)
448 u32 *data = (u32 *)data8;
449 bg = le16_to_cpu(bg);
450 fg = le16_to_cpu(fg);
454 for (i = 0; i < h; i++) {
458 for (j = 0; j < w/2; j++) {
460 #if defined (__BIG_ENDIAN)
461 tmp = (b & (1 << 31)) ? fg << 16 : bg << 16;
463 tmp |= (b & (1 << 31)) ? fg : bg;
466 tmp = (b & 1) ? fg : bg;
468 tmp |= (b & 1) ? fg << 16 : bg << 16;
471 writel(tmp, &par->riva.CURSOR[k++]);
473 k += (MAX_CURS - w)/2;
477 /* ------------------------------------------------------------------------- *
479 * general utility functions
481 * ------------------------------------------------------------------------- */
484 * riva_wclut - set CLUT entry
485 * @chip: pointer to RIVA_HW_INST object
486 * @regnum: register number
487 * @red: red component
488 * @green: green component
489 * @blue: blue component
492 * Sets color register @regnum.
497 static void riva_wclut(RIVA_HW_INST *chip,
498 unsigned char regnum, unsigned char red,
499 unsigned char green, unsigned char blue)
501 VGA_WR08(chip->PDIO, 0x3c8, regnum);
502 VGA_WR08(chip->PDIO, 0x3c9, red);
503 VGA_WR08(chip->PDIO, 0x3c9, green);
504 VGA_WR08(chip->PDIO, 0x3c9, blue);
508 * riva_rclut - read fromCLUT register
509 * @chip: pointer to RIVA_HW_INST object
510 * @regnum: register number
511 * @red: red component
512 * @green: green component
513 * @blue: blue component
516 * Reads red, green, and blue from color register @regnum.
521 static void riva_rclut(RIVA_HW_INST *chip,
522 unsigned char regnum, unsigned char *red,
523 unsigned char *green, unsigned char *blue)
526 VGA_WR08(chip->PDIO, 0x3c7, regnum);
527 *red = VGA_RD08(chip->PDIO, 0x3c9);
528 *green = VGA_RD08(chip->PDIO, 0x3c9);
529 *blue = VGA_RD08(chip->PDIO, 0x3c9);
533 * riva_save_state - saves current chip state
534 * @par: pointer to riva_par object containing info for current riva board
535 * @regs: pointer to riva_regs object
538 * Saves current chip state to @regs.
544 static void riva_save_state(struct riva_par *par, struct riva_regs *regs)
549 par->riva.LockUnlock(&par->riva, 0);
551 par->riva.UnloadStateExt(&par->riva, ®s->ext);
553 regs->misc_output = MISCin(par);
555 for (i = 0; i < NUM_CRT_REGS; i++)
556 regs->crtc[i] = CRTCin(par, i);
558 for (i = 0; i < NUM_ATC_REGS; i++)
559 regs->attr[i] = ATTRin(par, i);
561 for (i = 0; i < NUM_GRC_REGS; i++)
562 regs->gra[i] = GRAin(par, i);
564 for (i = 0; i < NUM_SEQ_REGS; i++)
565 regs->seq[i] = SEQin(par, i);
570 * riva_load_state - loads current chip state
571 * @par: pointer to riva_par object containing info for current riva board
572 * @regs: pointer to riva_regs object
575 * Loads chip state from @regs.
578 * riva_load_video_mode()
583 static void riva_load_state(struct riva_par *par, struct riva_regs *regs)
585 RIVA_HW_STATE *state = ®s->ext;
589 CRTCout(par, 0x11, 0x00);
591 par->riva.LockUnlock(&par->riva, 0);
593 par->riva.LoadStateExt(&par->riva, state);
595 MISCout(par, regs->misc_output);
597 for (i = 0; i < NUM_CRT_REGS; i++) {
603 CRTCout(par, i, regs->crtc[i]);
607 for (i = 0; i < NUM_ATC_REGS; i++)
608 ATTRout(par, i, regs->attr[i]);
610 for (i = 0; i < NUM_GRC_REGS; i++)
611 GRAout(par, i, regs->gra[i]);
613 for (i = 0; i < NUM_SEQ_REGS; i++)
614 SEQout(par, i, regs->seq[i]);
619 * riva_load_video_mode - calculate timings
620 * @info: pointer to fb_info object containing info for current riva board
623 * Calculate some timings and then send em off to riva_load_state().
628 static void riva_load_video_mode(struct fb_info *info)
630 int bpp, width, hDisplaySize, hDisplay, hStart,
631 hEnd, hTotal, height, vDisplay, vStart, vEnd, vTotal, dotClock;
632 int hBlankStart, hBlankEnd, vBlankStart, vBlankEnd;
633 struct riva_par *par = (struct riva_par *) info->par;
634 struct riva_regs newmode;
637 /* time to calculate */
638 rivafb_blank(1, info);
640 bpp = info->var.bits_per_pixel;
641 if (bpp == 16 && info->var.green.length == 5)
643 width = info->var.xres_virtual;
644 hDisplaySize = info->var.xres;
645 hDisplay = (hDisplaySize / 8) - 1;
646 hStart = (hDisplaySize + info->var.right_margin) / 8 - 1;
647 hEnd = (hDisplaySize + info->var.right_margin +
648 info->var.hsync_len) / 8 - 1;
649 hTotal = (hDisplaySize + info->var.right_margin +
650 info->var.hsync_len + info->var.left_margin) / 8 - 5;
651 hBlankStart = hDisplay;
652 hBlankEnd = hTotal + 4;
654 height = info->var.yres_virtual;
655 vDisplay = info->var.yres - 1;
656 vStart = info->var.yres + info->var.lower_margin - 1;
657 vEnd = info->var.yres + info->var.lower_margin +
658 info->var.vsync_len - 1;
659 vTotal = info->var.yres + info->var.lower_margin +
660 info->var.vsync_len + info->var.upper_margin + 2;
661 vBlankStart = vDisplay;
662 vBlankEnd = vTotal + 1;
663 dotClock = 1000000000 / info->var.pixclock;
665 memcpy(&newmode, ®_template, sizeof(struct riva_regs));
667 if ((info->var.vmode & FB_VMODE_MASK) == FB_VMODE_INTERLACED)
670 if (par->FlatPanel) {
673 vBlankStart = vStart;
676 hBlankEnd = hTotal + 4;
679 newmode.crtc[0x0] = Set8Bits (hTotal);
680 newmode.crtc[0x1] = Set8Bits (hDisplay);
681 newmode.crtc[0x2] = Set8Bits (hBlankStart);
682 newmode.crtc[0x3] = SetBitField (hBlankEnd, 4: 0, 4:0) | SetBit (7);
683 newmode.crtc[0x4] = Set8Bits (hStart);
684 newmode.crtc[0x5] = SetBitField (hBlankEnd, 5: 5, 7:7)
685 | SetBitField (hEnd, 4: 0, 4:0);
686 newmode.crtc[0x6] = SetBitField (vTotal, 7: 0, 7:0);
687 newmode.crtc[0x7] = SetBitField (vTotal, 8: 8, 0:0)
688 | SetBitField (vDisplay, 8: 8, 1:1)
689 | SetBitField (vStart, 8: 8, 2:2)
690 | SetBitField (vBlankStart, 8: 8, 3:3)
692 | SetBitField (vTotal, 9: 9, 5:5)
693 | SetBitField (vDisplay, 9: 9, 6:6)
694 | SetBitField (vStart, 9: 9, 7:7);
695 newmode.crtc[0x9] = SetBitField (vBlankStart, 9: 9, 5:5)
697 newmode.crtc[0x10] = Set8Bits (vStart);
698 newmode.crtc[0x11] = SetBitField (vEnd, 3: 0, 3:0)
700 newmode.crtc[0x12] = Set8Bits (vDisplay);
701 newmode.crtc[0x13] = (width / 8) * ((bpp + 1) / 8);
702 newmode.crtc[0x15] = Set8Bits (vBlankStart);
703 newmode.crtc[0x16] = Set8Bits (vBlankEnd);
705 newmode.ext.screen = SetBitField(hBlankEnd,6:6,4:4)
706 | SetBitField(vBlankStart,10:10,3:3)
707 | SetBitField(vStart,10:10,2:2)
708 | SetBitField(vDisplay,10:10,1:1)
709 | SetBitField(vTotal,10:10,0:0);
710 newmode.ext.horiz = SetBitField(hTotal,8:8,0:0)
711 | SetBitField(hDisplay,8:8,1:1)
712 | SetBitField(hBlankStart,8:8,2:2)
713 | SetBitField(hStart,8:8,3:3);
714 newmode.ext.extra = SetBitField(vTotal,11:11,0:0)
715 | SetBitField(vDisplay,11:11,2:2)
716 | SetBitField(vStart,11:11,4:4)
717 | SetBitField(vBlankStart,11:11,6:6);
719 if ((info->var.vmode & FB_VMODE_MASK) == FB_VMODE_INTERLACED) {
720 int tmp = (hTotal >> 1) & ~1;
721 newmode.ext.interlace = Set8Bits(tmp);
722 newmode.ext.horiz |= SetBitField(tmp, 8:8,4:4);
724 newmode.ext.interlace = 0xff; /* interlace off */
726 if (par->riva.Architecture >= NV_ARCH_10)
727 par->riva.CURSOR = (U032 __iomem *)(info->screen_base + par->riva.CursorStart);
729 if (info->var.sync & FB_SYNC_HOR_HIGH_ACT)
730 newmode.misc_output &= ~0x40;
732 newmode.misc_output |= 0x40;
733 if (info->var.sync & FB_SYNC_VERT_HIGH_ACT)
734 newmode.misc_output &= ~0x80;
736 newmode.misc_output |= 0x80;
738 par->riva.CalcStateExt(&par->riva, &newmode.ext, bpp, width,
739 hDisplaySize, height, dotClock);
741 newmode.ext.scale = NV_RD32(par->riva.PRAMDAC, 0x00000848) &
743 if (par->FlatPanel == 1) {
744 newmode.ext.pixel |= (1 << 7);
745 newmode.ext.scale |= (1 << 8);
747 if (par->SecondCRTC) {
748 newmode.ext.head = NV_RD32(par->riva.PCRTC0, 0x00000860) &
750 newmode.ext.head2 = NV_RD32(par->riva.PCRTC0, 0x00002860) |
752 newmode.ext.crtcOwner = 3;
753 newmode.ext.pllsel |= 0x20000800;
754 newmode.ext.vpll2 = newmode.ext.vpll;
755 } else if (par->riva.twoHeads) {
756 newmode.ext.head = NV_RD32(par->riva.PCRTC0, 0x00000860) |
758 newmode.ext.head2 = NV_RD32(par->riva.PCRTC0, 0x00002860) &
760 newmode.ext.crtcOwner = 0;
761 newmode.ext.vpll2 = NV_RD32(par->riva.PRAMDAC0, 0x00000520);
763 if (par->FlatPanel == 1) {
764 newmode.ext.pixel |= (1 << 7);
765 newmode.ext.scale |= (1 << 8);
767 newmode.ext.cursorConfig = 0x02000100;
768 par->current_state = newmode;
769 riva_load_state(par, &par->current_state);
770 par->riva.LockUnlock(&par->riva, 0); /* important for HW cursor */
771 rivafb_blank(0, info);
775 static void riva_update_var(struct fb_var_screeninfo *var, struct fb_videomode *modedb)
778 var->xres = var->xres_virtual = modedb->xres;
779 var->yres = modedb->yres;
780 if (var->yres_virtual < var->yres)
781 var->yres_virtual = var->yres;
782 var->xoffset = var->yoffset = 0;
783 var->pixclock = modedb->pixclock;
784 var->left_margin = modedb->left_margin;
785 var->right_margin = modedb->right_margin;
786 var->upper_margin = modedb->upper_margin;
787 var->lower_margin = modedb->lower_margin;
788 var->hsync_len = modedb->hsync_len;
789 var->vsync_len = modedb->vsync_len;
790 var->sync = modedb->sync;
791 var->vmode = modedb->vmode;
796 * rivafb_do_maximize -
797 * @info: pointer to fb_info object containing info for current riva board
806 * -EINVAL on failure, 0 on success
812 static int rivafb_do_maximize(struct fb_info *info,
813 struct fb_var_screeninfo *var,
829 /* use highest possible virtual resolution */
830 if (var->xres_virtual == -1 && var->yres_virtual == -1) {
831 printk(KERN_WARNING PFX
832 "using maximum available virtual resolution\n");
833 for (i = 0; modes[i].xres != -1; i++) {
834 if (modes[i].xres * nom / den * modes[i].yres <
838 if (modes[i].xres == -1) {
840 "could not find a virtual resolution that fits into video memory!!\n");
841 NVTRACE("EXIT - EINVAL error\n");
844 var->xres_virtual = modes[i].xres;
845 var->yres_virtual = modes[i].yres;
848 "virtual resolution set to maximum of %dx%d\n",
849 var->xres_virtual, var->yres_virtual);
850 } else if (var->xres_virtual == -1) {
851 var->xres_virtual = (info->fix.smem_len * den /
852 (nom * var->yres_virtual)) & ~15;
853 printk(KERN_WARNING PFX
854 "setting virtual X resolution to %d\n", var->xres_virtual);
855 } else if (var->yres_virtual == -1) {
856 var->xres_virtual = (var->xres_virtual + 15) & ~15;
857 var->yres_virtual = info->fix.smem_len * den /
858 (nom * var->xres_virtual);
859 printk(KERN_WARNING PFX
860 "setting virtual Y resolution to %d\n", var->yres_virtual);
862 var->xres_virtual = (var->xres_virtual + 15) & ~15;
863 if (var->xres_virtual * nom / den * var->yres_virtual > info->fix.smem_len) {
865 "mode %dx%dx%d rejected...resolution too high to fit into video memory!\n",
866 var->xres, var->yres, var->bits_per_pixel);
867 NVTRACE("EXIT - EINVAL error\n");
872 if (var->xres_virtual * nom / den >= 8192) {
873 printk(KERN_WARNING PFX
874 "virtual X resolution (%d) is too high, lowering to %d\n",
875 var->xres_virtual, 8192 * den / nom - 16);
876 var->xres_virtual = 8192 * den / nom - 16;
879 if (var->xres_virtual < var->xres) {
881 "virtual X resolution (%d) is smaller than real\n", var->xres_virtual);
885 if (var->yres_virtual < var->yres) {
887 "virtual Y resolution (%d) is smaller than real\n", var->yres_virtual);
890 if (var->yres_virtual > 0x7fff/nom)
891 var->yres_virtual = 0x7fff/nom;
892 if (var->xres_virtual > 0x7fff/nom)
893 var->xres_virtual = 0x7fff/nom;
899 riva_set_pattern(struct riva_par *par, int clr0, int clr1, int pat0, int pat1)
901 RIVA_FIFO_FREE(par->riva, Patt, 4);
902 NV_WR32(&par->riva.Patt->Color0, 0, clr0);
903 NV_WR32(&par->riva.Patt->Color1, 0, clr1);
904 NV_WR32(par->riva.Patt->Monochrome, 0, pat0);
905 NV_WR32(par->riva.Patt->Monochrome, 4, pat1);
908 /* acceleration routines */
909 static inline void wait_for_idle(struct riva_par *par)
911 while (par->riva.Busy(&par->riva));
915 * Set ROP. Translate X rop into ROP3. Internal routine.
918 riva_set_rop_solid(struct riva_par *par, int rop)
920 riva_set_pattern(par, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF);
921 RIVA_FIFO_FREE(par->riva, Rop, 1);
922 NV_WR32(&par->riva.Rop->Rop3, 0, rop);
926 static void riva_setup_accel(struct fb_info *info)
928 struct riva_par *par = (struct riva_par *) info->par;
930 RIVA_FIFO_FREE(par->riva, Clip, 2);
931 NV_WR32(&par->riva.Clip->TopLeft, 0, 0x0);
932 NV_WR32(&par->riva.Clip->WidthHeight, 0,
933 (info->var.xres_virtual & 0xffff) |
934 (info->var.yres_virtual << 16));
935 riva_set_rop_solid(par, 0xcc);
940 * riva_get_cmap_len - query current color map length
941 * @var: standard kernel fb changeable data
944 * Get current color map length.
947 * Length of color map
952 static int riva_get_cmap_len(const struct fb_var_screeninfo *var)
954 int rc = 256; /* reasonable default */
956 switch (var->green.length) {
958 rc = 256; /* 256 entries (2^8), 8 bpp and RGB8888 */
961 rc = 32; /* 32 entries (2^5), 16 bpp, RGB555 */
964 rc = 64; /* 64 entries (2^6), 16 bpp, RGB565 */
967 /* should not occur */
973 /* ------------------------------------------------------------------------- *
975 * Backlight operations
977 * ------------------------------------------------------------------------- */
979 #ifdef CONFIG_PMAC_BACKLIGHT
980 static int riva_set_backlight_enable(int on, int level, void *data)
982 struct riva_par *par = (struct riva_par *)data;
983 U032 tmp_pcrt, tmp_pmc;
985 tmp_pmc = par->riva.PMC[0x10F0/4] & 0x0000FFFF;
986 tmp_pcrt = par->riva.PCRTC0[0x081C/4] & 0xFFFFFFFC;
987 if(on && (level > BACKLIGHT_OFF)) {
989 tmp_pmc |= (1 << 31); // backlight bit
990 tmp_pmc |= riva_backlight_levels[level-1] << 16; // level
992 par->riva.PCRTC0[0x081C/4] = tmp_pcrt;
993 par->riva.PMC[0x10F0/4] = tmp_pmc;
997 static int riva_set_backlight_level(int level, void *data)
999 return riva_set_backlight_enable(1, level, data);
1001 #endif /* CONFIG_PMAC_BACKLIGHT */
1003 /* ------------------------------------------------------------------------- *
1005 * framebuffer operations
1007 * ------------------------------------------------------------------------- */
1009 static int rivafb_open(struct fb_info *info, int user)
1011 struct riva_par *par = (struct riva_par *) info->par;
1012 int cnt = atomic_read(&par->ref_count);
1017 memset(&par->state, 0, sizeof(struct vgastate));
1018 par->state.flags = VGA_SAVE_MODE | VGA_SAVE_FONTS;
1019 /* save the DAC for Riva128 */
1020 if (par->riva.Architecture == NV_ARCH_03)
1021 par->state.flags |= VGA_SAVE_CMAP;
1022 save_vga(&par->state);
1024 /* vgaHWunlock() + riva unlock (0x7F) */
1025 CRTCout(par, 0x11, 0xFF);
1026 par->riva.LockUnlock(&par->riva, 0);
1028 riva_save_state(par, &par->initial_state);
1030 atomic_inc(&par->ref_count);
1035 static int rivafb_release(struct fb_info *info, int user)
1037 struct riva_par *par = (struct riva_par *) info->par;
1038 int cnt = atomic_read(&par->ref_count);
1044 par->riva.LockUnlock(&par->riva, 0);
1045 par->riva.LoadStateExt(&par->riva, &par->initial_state.ext);
1046 riva_load_state(par, &par->initial_state);
1048 restore_vga(&par->state);
1050 par->riva.LockUnlock(&par->riva, 1);
1052 atomic_dec(&par->ref_count);
1057 static int rivafb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
1059 struct fb_videomode *mode;
1060 struct riva_par *par = (struct riva_par *) info->par;
1061 int nom, den; /* translating from pixels->bytes */
1065 switch (var->bits_per_pixel) {
1067 var->red.offset = var->green.offset = var->blue.offset = 0;
1068 var->red.length = var->green.length = var->blue.length = 8;
1069 var->bits_per_pixel = 8;
1073 var->green.length = 5;
1076 var->bits_per_pixel = 16;
1077 /* The Riva128 supports RGB555 only */
1078 if (par->riva.Architecture == NV_ARCH_03)
1079 var->green.length = 5;
1080 if (var->green.length == 5) {
1081 /* 0rrrrrgg gggbbbbb */
1082 var->red.offset = 10;
1083 var->green.offset = 5;
1084 var->blue.offset = 0;
1085 var->red.length = 5;
1086 var->green.length = 5;
1087 var->blue.length = 5;
1089 /* rrrrrggg gggbbbbb */
1090 var->red.offset = 11;
1091 var->green.offset = 5;
1092 var->blue.offset = 0;
1093 var->red.length = 5;
1094 var->green.length = 6;
1095 var->blue.length = 5;
1101 var->red.length = var->green.length = var->blue.length = 8;
1102 var->bits_per_pixel = 32;
1103 var->red.offset = 16;
1104 var->green.offset = 8;
1105 var->blue.offset = 0;
1111 "mode %dx%dx%d rejected...color depth not supported.\n",
1112 var->xres, var->yres, var->bits_per_pixel);
1113 NVTRACE("EXIT, returning -EINVAL\n");
1118 if (!info->monspecs.vfmax || !info->monspecs.hfmax ||
1119 !info->monspecs.dclkmax || !fb_validate_mode(var, info))
1123 /* calculate modeline if supported by monitor */
1124 if (!mode_valid && info->monspecs.gtf) {
1125 if (!fb_get_mode(FB_MAXTIMINGS, 0, var, info))
1130 mode = fb_find_best_mode(var, &info->modelist);
1132 riva_update_var(var, mode);
1137 if (!mode_valid && info->monspecs.modedb_len)
1140 if (var->xres_virtual < var->xres)
1141 var->xres_virtual = var->xres;
1142 if (var->yres_virtual <= var->yres)
1143 var->yres_virtual = -1;
1144 if (rivafb_do_maximize(info, var, nom, den) < 0)
1147 if (var->xoffset < 0)
1149 if (var->yoffset < 0)
1152 /* truncate xoffset and yoffset to maximum if too high */
1153 if (var->xoffset > var->xres_virtual - var->xres)
1154 var->xoffset = var->xres_virtual - var->xres - 1;
1156 if (var->yoffset > var->yres_virtual - var->yres)
1157 var->yoffset = var->yres_virtual - var->yres - 1;
1159 var->red.msb_right =
1160 var->green.msb_right =
1161 var->blue.msb_right =
1162 var->transp.offset = var->transp.length = var->transp.msb_right = 0;
1167 static int rivafb_set_par(struct fb_info *info)
1169 struct riva_par *par = (struct riva_par *) info->par;
1172 /* vgaHWunlock() + riva unlock (0x7F) */
1173 CRTCout(par, 0x11, 0xFF);
1174 par->riva.LockUnlock(&par->riva, 0);
1175 riva_load_video_mode(info);
1176 if(!(info->flags & FBINFO_HWACCEL_DISABLED))
1177 riva_setup_accel(info);
1179 par->cursor_reset = 1;
1180 info->fix.line_length = (info->var.xres_virtual * (info->var.bits_per_pixel >> 3));
1181 info->fix.visual = (info->var.bits_per_pixel == 8) ?
1182 FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_DIRECTCOLOR;
1184 if (info->flags & FBINFO_HWACCEL_DISABLED)
1185 info->pixmap.scan_align = 1;
1187 info->pixmap.scan_align = 4;
1193 * rivafb_pan_display
1194 * @var: standard kernel fb changeable data
1196 * @info: pointer to fb_info object containing info for current riva board
1199 * Pan (or wrap, depending on the `vmode' field) the display using the
1200 * `xoffset' and `yoffset' fields of the `var' structure.
1201 * If the values don't fit, return -EINVAL.
1203 * This call looks only at xoffset, yoffset and the FB_VMODE_YWRAP flag
1205 static int rivafb_pan_display(struct fb_var_screeninfo *var,
1206 struct fb_info *info)
1208 struct riva_par *par = (struct riva_par *)info->par;
1212 if (var->xoffset > (var->xres_virtual - var->xres))
1214 if (var->yoffset > (var->yres_virtual - var->yres))
1217 if (var->vmode & FB_VMODE_YWRAP) {
1218 if (var->yoffset < 0
1219 || var->yoffset >= info->var.yres_virtual
1220 || var->xoffset) return -EINVAL;
1222 if (var->xoffset + info->var.xres > info->var.xres_virtual ||
1223 var->yoffset + info->var.yres > info->var.yres_virtual)
1227 base = var->yoffset * info->fix.line_length + var->xoffset;
1229 par->riva.SetStartAddress(&par->riva, base);
1231 info->var.xoffset = var->xoffset;
1232 info->var.yoffset = var->yoffset;
1234 if (var->vmode & FB_VMODE_YWRAP)
1235 info->var.vmode |= FB_VMODE_YWRAP;
1237 info->var.vmode &= ~FB_VMODE_YWRAP;
1242 static int rivafb_blank(int blank, struct fb_info *info)
1244 struct riva_par *par= (struct riva_par *)info->par;
1245 unsigned char tmp, vesa;
1247 tmp = SEQin(par, 0x01) & ~0x20; /* screen on/off */
1248 vesa = CRTCin(par, 0x1a) & ~0xc0; /* sync on/off */
1256 case FB_BLANK_UNBLANK:
1257 case FB_BLANK_NORMAL:
1259 case FB_BLANK_VSYNC_SUSPEND:
1262 case FB_BLANK_HSYNC_SUSPEND:
1265 case FB_BLANK_POWERDOWN:
1270 SEQout(par, 0x01, tmp);
1271 CRTCout(par, 0x1a, vesa);
1273 #ifdef CONFIG_PMAC_BACKLIGHT
1274 if ( par->FlatPanel && _machine == _MACH_Pmac) {
1275 set_backlight_enable(!blank);
1286 * @regno: register index
1287 * @red: red component
1288 * @green: green component
1289 * @blue: blue component
1290 * @transp: transparency
1291 * @info: pointer to fb_info object containing info for current riva board
1294 * Set a single color register. The values supplied have a 16 bit
1298 * Return != 0 for invalid regno.
1301 * fbcmap.c:fb_set_cmap()
1303 static int rivafb_setcolreg(unsigned regno, unsigned red, unsigned green,
1304 unsigned blue, unsigned transp,
1305 struct fb_info *info)
1307 struct riva_par *par = (struct riva_par *)info->par;
1308 RIVA_HW_INST *chip = &par->riva;
1311 if (regno >= riva_get_cmap_len(&info->var))
1314 if (info->var.grayscale) {
1315 /* gray = 0.30*R + 0.59*G + 0.11*B */
1316 red = green = blue =
1317 (red * 77 + green * 151 + blue * 28) >> 8;
1320 if (regno < 16 && info->fix.visual == FB_VISUAL_DIRECTCOLOR) {
1321 ((u32 *) info->pseudo_palette)[regno] =
1322 (regno << info->var.red.offset) |
1323 (regno << info->var.green.offset) |
1324 (regno << info->var.blue.offset);
1326 * The Riva128 2D engine requires color information in
1327 * TrueColor format even if framebuffer is in DirectColor
1329 if (par->riva.Architecture == NV_ARCH_03) {
1330 switch (info->var.bits_per_pixel) {
1332 par->palette[regno] = ((red & 0xf800) >> 1) |
1333 ((green & 0xf800) >> 6) |
1334 ((blue & 0xf800) >> 11);
1337 par->palette[regno] = ((red & 0xff00) << 8) |
1338 ((green & 0xff00)) |
1339 ((blue & 0xff00) >> 8);
1345 switch (info->var.bits_per_pixel) {
1347 /* "transparent" stuff is completely ignored. */
1348 riva_wclut(chip, regno, red >> 8, green >> 8, blue >> 8);
1351 if (info->var.green.length == 5) {
1352 for (i = 0; i < 8; i++) {
1353 riva_wclut(chip, regno*8+i, red >> 8,
1354 green >> 8, blue >> 8);
1360 for (i = 0; i < 8; i++) {
1361 riva_wclut(chip, regno*8+i,
1362 red >> 8, green >> 8,
1366 riva_rclut(chip, regno*4, &r, &g, &b);
1367 for (i = 0; i < 4; i++)
1368 riva_wclut(chip, regno*4+i, r,
1373 riva_wclut(chip, regno, red >> 8, green >> 8, blue >> 8);
1383 * rivafb_fillrect - hardware accelerated color fill function
1384 * @info: pointer to fb_info structure
1385 * @rect: pointer to fb_fillrect structure
1388 * This function fills up a region of framebuffer memory with a solid
1389 * color with a choice of two different ROP's, copy or invert.
1394 static void rivafb_fillrect(struct fb_info *info, const struct fb_fillrect *rect)
1396 struct riva_par *par = (struct riva_par *) info->par;
1397 u_int color, rop = 0;
1399 if ((info->flags & FBINFO_HWACCEL_DISABLED)) {
1400 cfb_fillrect(info, rect);
1404 if (info->var.bits_per_pixel == 8)
1405 color = rect->color;
1407 if (par->riva.Architecture != NV_ARCH_03)
1408 color = ((u32 *)info->pseudo_palette)[rect->color];
1410 color = par->palette[rect->color];
1413 switch (rect->rop) {
1423 riva_set_rop_solid(par, rop);
1425 RIVA_FIFO_FREE(par->riva, Bitmap, 1);
1426 NV_WR32(&par->riva.Bitmap->Color1A, 0, color);
1428 RIVA_FIFO_FREE(par->riva, Bitmap, 2);
1429 NV_WR32(&par->riva.Bitmap->UnclippedRectangle[0].TopLeft, 0,
1430 (rect->dx << 16) | rect->dy);
1432 NV_WR32(&par->riva.Bitmap->UnclippedRectangle[0].WidthHeight, 0,
1433 (rect->width << 16) | rect->height);
1435 riva_set_rop_solid(par, 0xcc);
1440 * rivafb_copyarea - hardware accelerated blit function
1441 * @info: pointer to fb_info structure
1442 * @region: pointer to fb_copyarea structure
1445 * This copies an area of pixels from one location to another
1450 static void rivafb_copyarea(struct fb_info *info, const struct fb_copyarea *region)
1452 struct riva_par *par = (struct riva_par *) info->par;
1454 if ((info->flags & FBINFO_HWACCEL_DISABLED)) {
1455 cfb_copyarea(info, region);
1459 RIVA_FIFO_FREE(par->riva, Blt, 3);
1460 NV_WR32(&par->riva.Blt->TopLeftSrc, 0,
1461 (region->sy << 16) | region->sx);
1462 NV_WR32(&par->riva.Blt->TopLeftDst, 0,
1463 (region->dy << 16) | region->dx);
1465 NV_WR32(&par->riva.Blt->WidthHeight, 0,
1466 (region->height << 16) | region->width);
1470 static inline void convert_bgcolor_16(u32 *col)
1472 *col = ((*col & 0x0000F800) << 8)
1473 | ((*col & 0x00007E0) << 5)
1474 | ((*col & 0x0000001F) << 3)
1480 * rivafb_imageblit: hardware accelerated color expand function
1481 * @info: pointer to fb_info structure
1482 * @image: pointer to fb_image structure
1485 * If the source is a monochrome bitmap, the function fills up a a region
1486 * of framebuffer memory with pixels whose color is determined by the bit
1487 * setting of the bitmap, 1 - foreground, 0 - background.
1489 * If the source is not a monochrome bitmap, color expansion is not done.
1490 * In this case, it is channeled to a software function.
1495 static void rivafb_imageblit(struct fb_info *info,
1496 const struct fb_image *image)
1498 struct riva_par *par = (struct riva_par *) info->par;
1499 u32 fgx = 0, bgx = 0, width, tmp;
1500 u8 *cdat = (u8 *) image->data;
1501 volatile u32 __iomem *d;
1504 if ((info->flags & FBINFO_HWACCEL_DISABLED) || image->depth != 1) {
1505 cfb_imageblit(info, image);
1509 switch (info->var.bits_per_pixel) {
1511 fgx = image->fg_color;
1512 bgx = image->bg_color;
1516 if (par->riva.Architecture != NV_ARCH_03) {
1517 fgx = ((u32 *)info->pseudo_palette)[image->fg_color];
1518 bgx = ((u32 *)info->pseudo_palette)[image->bg_color];
1520 fgx = par->palette[image->fg_color];
1521 bgx = par->palette[image->bg_color];
1523 if (info->var.green.length == 6)
1524 convert_bgcolor_16(&bgx);
1528 RIVA_FIFO_FREE(par->riva, Bitmap, 7);
1529 NV_WR32(&par->riva.Bitmap->ClipE.TopLeft, 0,
1530 (image->dy << 16) | (image->dx & 0xFFFF));
1531 NV_WR32(&par->riva.Bitmap->ClipE.BottomRight, 0,
1532 (((image->dy + image->height) << 16) |
1533 ((image->dx + image->width) & 0xffff)));
1534 NV_WR32(&par->riva.Bitmap->Color0E, 0, bgx);
1535 NV_WR32(&par->riva.Bitmap->Color1E, 0, fgx);
1536 NV_WR32(&par->riva.Bitmap->WidthHeightInE, 0,
1537 (image->height << 16) | ((image->width + 31) & ~31));
1538 NV_WR32(&par->riva.Bitmap->WidthHeightOutE, 0,
1539 (image->height << 16) | ((image->width + 31) & ~31));
1540 NV_WR32(&par->riva.Bitmap->PointE, 0,
1541 (image->dy << 16) | (image->dx & 0xFFFF));
1543 d = &par->riva.Bitmap->MonochromeData01E;
1545 width = (image->width + 31)/32;
1546 size = width * image->height;
1547 while (size >= 16) {
1548 RIVA_FIFO_FREE(par->riva, Bitmap, 16);
1549 for (i = 0; i < 16; i++) {
1550 tmp = *((u32 *)cdat);
1551 cdat = (u8 *)((u32 *)cdat + 1);
1552 reverse_order(&tmp);
1553 NV_WR32(d, i*4, tmp);
1558 RIVA_FIFO_FREE(par->riva, Bitmap, size);
1559 for (i = 0; i < size; i++) {
1560 tmp = *((u32 *) cdat);
1561 cdat = (u8 *)((u32 *)cdat + 1);
1562 reverse_order(&tmp);
1563 NV_WR32(d, i*4, tmp);
1569 * rivafb_cursor - hardware cursor function
1570 * @info: pointer to info structure
1571 * @cursor: pointer to fbcursor structure
1574 * A cursor function that supports displaying a cursor image via hardware.
1575 * Within the kernel, copy and invert rops are supported. If exported
1576 * to user space, only the copy rop will be supported.
1581 static int rivafb_cursor(struct fb_info *info, struct fb_cursor *cursor)
1583 struct riva_par *par = (struct riva_par *) info->par;
1584 u8 data[MAX_CURS * MAX_CURS/8];
1585 int i, set = cursor->set;
1588 if (cursor->image.width > MAX_CURS || cursor->image.height > MAX_CURS)
1591 par->riva.ShowHideCursor(&par->riva, 0);
1593 if (par->cursor_reset) {
1594 set = FB_CUR_SETALL;
1595 par->cursor_reset = 0;
1598 if (set & FB_CUR_SETSIZE)
1599 memset_io(par->riva.CURSOR, 0, MAX_CURS * MAX_CURS * 2);
1601 if (set & FB_CUR_SETPOS) {
1604 yy = cursor->image.dy - info->var.yoffset;
1605 xx = cursor->image.dx - info->var.xoffset;
1609 NV_WR32(par->riva.PRAMDAC, 0x0000300, temp);
1613 if (set & (FB_CUR_SETSHAPE | FB_CUR_SETCMAP | FB_CUR_SETIMAGE)) {
1614 u32 bg_idx = cursor->image.bg_color;
1615 u32 fg_idx = cursor->image.fg_color;
1616 u32 s_pitch = (cursor->image.width+7) >> 3;
1617 u32 d_pitch = MAX_CURS/8;
1618 u8 *dat = (u8 *) cursor->image.data;
1619 u8 *msk = (u8 *) cursor->mask;
1622 src = kmalloc(s_pitch * cursor->image.height, GFP_ATOMIC);
1625 switch (cursor->rop) {
1627 for (i = 0; i < s_pitch * cursor->image.height; i++)
1628 src[i] = dat[i] ^ msk[i];
1632 for (i = 0; i < s_pitch * cursor->image.height; i++)
1633 src[i] = dat[i] & msk[i];
1637 fb_pad_aligned_buffer(data, d_pitch, src, s_pitch,
1638 cursor->image.height);
1640 bg = ((info->cmap.red[bg_idx] & 0xf8) << 7) |
1641 ((info->cmap.green[bg_idx] & 0xf8) << 2) |
1642 ((info->cmap.blue[bg_idx] & 0xf8) >> 3) |
1645 fg = ((info->cmap.red[fg_idx] & 0xf8) << 7) |
1646 ((info->cmap.green[fg_idx] & 0xf8) << 2) |
1647 ((info->cmap.blue[fg_idx] & 0xf8) >> 3) |
1650 par->riva.LockUnlock(&par->riva, 0);
1652 rivafb_load_cursor_image(par, data, bg, fg,
1653 cursor->image.width,
1654 cursor->image.height);
1660 par->riva.ShowHideCursor(&par->riva, 1);
1665 static int rivafb_sync(struct fb_info *info)
1667 struct riva_par *par = (struct riva_par *)info->par;
1673 /* ------------------------------------------------------------------------- *
1675 * initialization helper functions
1677 * ------------------------------------------------------------------------- */
1679 /* kernel interface */
1680 static struct fb_ops riva_fb_ops = {
1681 .owner = THIS_MODULE,
1682 .fb_open = rivafb_open,
1683 .fb_release = rivafb_release,
1684 .fb_check_var = rivafb_check_var,
1685 .fb_set_par = rivafb_set_par,
1686 .fb_setcolreg = rivafb_setcolreg,
1687 .fb_pan_display = rivafb_pan_display,
1688 .fb_blank = rivafb_blank,
1689 .fb_fillrect = rivafb_fillrect,
1690 .fb_copyarea = rivafb_copyarea,
1691 .fb_imageblit = rivafb_imageblit,
1692 .fb_cursor = rivafb_cursor,
1693 .fb_sync = rivafb_sync,
1696 static int __devinit riva_set_fbinfo(struct fb_info *info)
1698 unsigned int cmap_len;
1699 struct riva_par *par = (struct riva_par *) info->par;
1702 info->flags = FBINFO_DEFAULT
1703 | FBINFO_HWACCEL_XPAN
1704 | FBINFO_HWACCEL_YPAN
1705 | FBINFO_HWACCEL_COPYAREA
1706 | FBINFO_HWACCEL_FILLRECT
1707 | FBINFO_HWACCEL_IMAGEBLIT;
1709 /* Accel seems to not work properly on NV30 yet...*/
1710 if ((par->riva.Architecture == NV_ARCH_30) || noaccel) {
1711 printk(KERN_DEBUG PFX "disabling acceleration\n");
1712 info->flags |= FBINFO_HWACCEL_DISABLED;
1715 info->var = rivafb_default_var;
1716 info->fix.visual = (info->var.bits_per_pixel == 8) ?
1717 FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_DIRECTCOLOR;
1719 info->pseudo_palette = par->pseudo_palette;
1721 cmap_len = riva_get_cmap_len(&info->var);
1722 fb_alloc_cmap(&info->cmap, cmap_len, 0);
1724 info->pixmap.size = 8 * 1024;
1725 info->pixmap.buf_align = 4;
1726 info->pixmap.flags = FB_PIXMAP_SYSTEM;
1727 info->var.yres_virtual = -1;
1729 return (rivafb_check_var(&info->var, info));
1732 #ifdef CONFIG_PPC_OF
1733 static int __devinit riva_get_EDID_OF(struct fb_info *info, struct pci_dev *pd)
1735 struct riva_par *par = (struct riva_par *) info->par;
1736 struct device_node *dp;
1737 unsigned char *pedid = NULL;
1738 unsigned char *disptype = NULL;
1739 static char *propnames[] = {
1740 "DFP,EDID", "LCD,EDID", "EDID", "EDID1", "EDID,B", "EDID,A", NULL };
1744 dp = pci_device_to_OF_node(pd);
1745 for (; dp != NULL; dp = dp->child) {
1746 disptype = (unsigned char *)get_property(dp, "display-type", NULL);
1747 if (disptype == NULL)
1749 if (strncmp(disptype, "LCD", 3) != 0)
1751 for (i = 0; propnames[i] != NULL; ++i) {
1752 pedid = (unsigned char *)
1753 get_property(dp, propnames[i], NULL);
1754 if (pedid != NULL) {
1756 NVTRACE("LCD found.\n");
1764 #endif /* CONFIG_PPC_OF */
1766 #if defined(CONFIG_FB_RIVA_I2C) && !defined(CONFIG_PPC_OF)
1767 static int __devinit riva_get_EDID_i2c(struct fb_info *info)
1769 struct riva_par *par = (struct riva_par *) info->par;
1770 struct fb_var_screeninfo var;
1774 riva_create_i2c_busses(par);
1775 for (i = 0; i < par->bus; i++) {
1776 riva_probe_i2c_connector(par, i+1, &par->EDID);
1777 if (par->EDID && !fb_parse_edid(par->EDID, &var)) {
1778 printk(PFX "Found EDID Block from BUS %i\n", i);
1784 return (par->EDID) ? 1 : 0;
1786 #endif /* CONFIG_FB_RIVA_I2C */
1788 static void __devinit riva_update_default_var(struct fb_var_screeninfo *var,
1789 struct fb_info *info)
1791 struct fb_monspecs *specs = &info->monspecs;
1792 struct fb_videomode modedb;
1795 /* respect mode options */
1797 fb_find_mode(var, info, mode_option,
1798 specs->modedb, specs->modedb_len,
1800 } else if (specs->modedb != NULL) {
1801 /* get preferred timing */
1802 if (info->monspecs.misc & FB_MISC_1ST_DETAIL) {
1805 for (i = 0; i < specs->modedb_len; i++) {
1806 if (specs->modedb[i].flag & FB_MODE_IS_FIRST) {
1807 modedb = specs->modedb[i];
1812 /* otherwise, get first mode in database */
1813 modedb = specs->modedb[0];
1815 var->bits_per_pixel = 8;
1816 riva_update_var(var, &modedb);
1822 static void __devinit riva_get_EDID(struct fb_info *info, struct pci_dev *pdev)
1825 #ifdef CONFIG_PPC_OF
1826 if (!riva_get_EDID_OF(info, pdev))
1827 printk(PFX "could not retrieve EDID from OF\n");
1828 #elif CONFIG_FB_RIVA_I2C
1829 if (!riva_get_EDID_i2c(info))
1830 printk(PFX "could not retrieve EDID from DDC/I2C\n");
1836 static void __devinit riva_get_edidinfo(struct fb_info *info)
1838 struct fb_var_screeninfo *var = &rivafb_default_var;
1839 struct riva_par *par = (struct riva_par *) info->par;
1841 fb_edid_to_monspecs(par->EDID, &info->monspecs);
1842 fb_videomode_to_modelist(info->monspecs.modedb, info->monspecs.modedb_len,
1844 riva_update_default_var(var, info);
1846 /* if user specified flatpanel, we respect that */
1847 if (info->monspecs.input & FB_DISP_DDI)
1851 /* ------------------------------------------------------------------------- *
1855 * ------------------------------------------------------------------------- */
1857 static u32 __devinit riva_get_arch(struct pci_dev *pd)
1861 switch (pd->device & 0x0ff0) {
1862 case 0x0100: /* GeForce 256 */
1863 case 0x0110: /* GeForce2 MX */
1864 case 0x0150: /* GeForce2 */
1865 case 0x0170: /* GeForce4 MX */
1866 case 0x0180: /* GeForce4 MX (8x AGP) */
1867 case 0x01A0: /* nForce */
1868 case 0x01F0: /* nForce2 */
1871 case 0x0200: /* GeForce3 */
1872 case 0x0250: /* GeForce4 Ti */
1873 case 0x0280: /* GeForce4 Ti (8x AGP) */
1876 case 0x0300: /* GeForceFX 5800 */
1877 case 0x0310: /* GeForceFX 5600 */
1878 case 0x0320: /* GeForceFX 5200 */
1879 case 0x0330: /* GeForceFX 5900 */
1880 case 0x0340: /* GeForceFX 5700 */
1883 case 0x0020: /* TNT, TNT2 */
1886 case 0x0010: /* Riva128 */
1889 default: /* unknown architecture */
1895 static int __devinit rivafb_probe(struct pci_dev *pd,
1896 const struct pci_device_id *ent)
1898 struct riva_par *default_par;
1899 struct fb_info *info;
1905 info = framebuffer_alloc(sizeof(struct riva_par), &pd->dev);
1907 printk (KERN_ERR PFX "could not allocate memory\n");
1911 default_par = (struct riva_par *) info->par;
1912 default_par->pdev = pd;
1914 info->pixmap.addr = kmalloc(8 * 1024, GFP_KERNEL);
1915 if (info->pixmap.addr == NULL) {
1917 goto err_framebuffer_release;
1919 memset(info->pixmap.addr, 0, 8 * 1024);
1921 ret = pci_enable_device(pd);
1923 printk(KERN_ERR PFX "cannot enable PCI device\n");
1924 goto err_free_pixmap;
1927 ret = pci_request_regions(pd, "rivafb");
1929 printk(KERN_ERR PFX "cannot request PCI regions\n");
1930 goto err_disable_device;
1933 default_par->riva.Architecture = riva_get_arch(pd);
1935 default_par->Chipset = (pd->vendor << 16) | pd->device;
1936 printk(KERN_INFO PFX "nVidia device/chipset %X\n",default_par->Chipset);
1938 #ifdef CONFIG_PCI_NAMES
1939 printk(KERN_INFO PFX "%s\n", pd->pretty_name);
1942 if(default_par->riva.Architecture == 0) {
1943 printk(KERN_ERR PFX "unknown NV_ARCH\n");
1945 goto err_release_region;
1947 if(default_par->riva.Architecture == NV_ARCH_10 ||
1948 default_par->riva.Architecture == NV_ARCH_20 ||
1949 default_par->riva.Architecture == NV_ARCH_30) {
1950 sprintf(rivafb_fix.id, "NV%x", (pd->device & 0x0ff0) >> 4);
1952 sprintf(rivafb_fix.id, "NV%x", default_par->riva.Architecture);
1955 default_par->FlatPanel = flatpanel;
1957 printk(KERN_INFO PFX "flatpanel support enabled\n");
1958 default_par->forceCRTC = forceCRTC;
1960 rivafb_fix.mmio_len = pci_resource_len(pd, 0);
1961 rivafb_fix.smem_len = pci_resource_len(pd, 1);
1964 /* enable IO and mem if not already done */
1967 pci_read_config_word(pd, PCI_COMMAND, &cmd);
1968 cmd |= (PCI_COMMAND_IO | PCI_COMMAND_MEMORY);
1969 pci_write_config_word(pd, PCI_COMMAND, cmd);
1972 rivafb_fix.mmio_start = pci_resource_start(pd, 0);
1973 rivafb_fix.smem_start = pci_resource_start(pd, 1);
1975 default_par->ctrl_base = ioremap(rivafb_fix.mmio_start,
1976 rivafb_fix.mmio_len);
1977 if (!default_par->ctrl_base) {
1978 printk(KERN_ERR PFX "cannot ioremap MMIO base\n");
1980 goto err_release_region;
1983 switch (default_par->riva.Architecture) {
1985 /* Riva128's PRAMIN is in the "framebuffer" space
1986 * Since these cards were never made with more than 8 megabytes
1987 * we can safely allocate this separately.
1989 default_par->riva.PRAMIN = ioremap(rivafb_fix.smem_start + 0x00C00000, 0x00008000);
1990 if (!default_par->riva.PRAMIN) {
1991 printk(KERN_ERR PFX "cannot ioremap PRAMIN region\n");
1993 goto err_iounmap_ctrl_base;
2000 default_par->riva.PCRTC0 =
2001 (u32 __iomem *)(default_par->ctrl_base + 0x00600000);
2002 default_par->riva.PRAMIN =
2003 (u32 __iomem *)(default_par->ctrl_base + 0x00710000);
2006 riva_common_setup(default_par);
2008 if (default_par->riva.Architecture == NV_ARCH_03) {
2009 default_par->riva.PCRTC = default_par->riva.PCRTC0
2010 = default_par->riva.PGRAPH;
2013 rivafb_fix.smem_len = riva_get_memlen(default_par) * 1024;
2014 default_par->dclk_max = riva_get_maxdclk(default_par) * 1000;
2015 info->screen_base = ioremap(rivafb_fix.smem_start,
2016 rivafb_fix.smem_len);
2017 if (!info->screen_base) {
2018 printk(KERN_ERR PFX "cannot ioremap FB base\n");
2020 goto err_iounmap_pramin;
2025 default_par->mtrr.vram = mtrr_add(rivafb_fix.smem_start,
2026 rivafb_fix.smem_len,
2027 MTRR_TYPE_WRCOMB, 1);
2028 if (default_par->mtrr.vram < 0) {
2029 printk(KERN_ERR PFX "unable to setup MTRR\n");
2031 default_par->mtrr.vram_valid = 1;
2032 /* let there be speed */
2033 printk(KERN_INFO PFX "RIVA MTRR set to ON\n");
2036 #endif /* CONFIG_MTRR */
2038 info->fbops = &riva_fb_ops;
2039 info->fix = rivafb_fix;
2040 riva_get_EDID(info, pd);
2041 riva_get_edidinfo(info);
2043 ret=riva_set_fbinfo(info);
2045 printk(KERN_ERR PFX "error setting initial video mode\n");
2046 goto err_iounmap_screen_base;
2049 fb_destroy_modedb(info->monspecs.modedb);
2050 info->monspecs.modedb = NULL;
2051 ret = register_framebuffer(info);
2054 "error registering riva framebuffer\n");
2055 goto err_iounmap_screen_base;
2058 pci_set_drvdata(pd, info);
2060 printk(KERN_INFO PFX
2061 "PCI nVidia %s framebuffer ver %s (%dMB @ 0x%lX)\n",
2064 info->fix.smem_len / (1024 * 1024),
2065 info->fix.smem_start);
2066 #ifdef CONFIG_PMAC_BACKLIGHT
2067 if (default_par->FlatPanel && _machine == _MACH_Pmac)
2068 register_backlight_controller(&riva_backlight_controller,
2069 default_par, "mnca");
2074 err_iounmap_screen_base:
2075 #ifdef CONFIG_FB_RIVA_I2C
2076 riva_delete_i2c_busses((struct riva_par *) info->par);
2078 iounmap(info->screen_base);
2080 if (default_par->riva.Architecture == NV_ARCH_03)
2081 iounmap(default_par->riva.PRAMIN);
2082 err_iounmap_ctrl_base:
2083 iounmap(default_par->ctrl_base);
2085 pci_release_regions(pd);
2087 pci_disable_device(pd);
2089 kfree(info->pixmap.addr);
2090 err_framebuffer_release:
2091 framebuffer_release(info);
2096 static void __exit rivafb_remove(struct pci_dev *pd)
2098 struct fb_info *info = pci_get_drvdata(pd);
2099 struct riva_par *par = (struct riva_par *) info->par;
2105 #ifdef CONFIG_FB_RIVA_I2C
2106 riva_delete_i2c_busses(par);
2110 unregister_framebuffer(info);
2112 if (par->mtrr.vram_valid)
2113 mtrr_del(par->mtrr.vram, info->fix.smem_start,
2114 info->fix.smem_len);
2115 #endif /* CONFIG_MTRR */
2117 iounmap(par->ctrl_base);
2118 iounmap(info->screen_base);
2119 if (par->riva.Architecture == NV_ARCH_03)
2120 iounmap(par->riva.PRAMIN);
2121 pci_release_regions(pd);
2122 pci_disable_device(pd);
2123 kfree(info->pixmap.addr);
2124 framebuffer_release(info);
2125 pci_set_drvdata(pd, NULL);
2129 /* ------------------------------------------------------------------------- *
2133 * ------------------------------------------------------------------------- */
2136 static int __init rivafb_setup(char *options)
2141 if (!options || !*options)
2144 while ((this_opt = strsep(&options, ",")) != NULL) {
2145 if (!strncmp(this_opt, "forceCRTC", 9)) {
2149 if (!*p || !*(++p)) continue;
2150 forceCRTC = *p - '0';
2151 if (forceCRTC < 0 || forceCRTC > 1)
2153 } else if (!strncmp(this_opt, "flatpanel", 9)) {
2156 } else if (!strncmp(this_opt, "nomtrr", 6)) {
2159 } else if (!strncmp(this_opt, "strictmode", 10)) {
2161 } else if (!strncmp(this_opt, "noaccel", 7)) {
2164 mode_option = this_opt;
2169 #endif /* !MODULE */
2171 static struct pci_driver rivafb_driver = {
2173 .id_table = rivafb_pci_tbl,
2174 .probe = rivafb_probe,
2175 .remove = __exit_p(rivafb_remove),
2180 /* ------------------------------------------------------------------------- *
2184 * ------------------------------------------------------------------------- */
2186 static int __devinit rivafb_init(void)
2189 char *option = NULL;
2191 if (fb_get_options("rivafb", &option))
2193 rivafb_setup(option);
2195 return pci_register_driver(&rivafb_driver);
2199 module_init(rivafb_init);
2202 static void __exit rivafb_exit(void)
2204 pci_unregister_driver(&rivafb_driver);
2207 module_exit(rivafb_exit);
2210 module_param(noaccel, bool, 0);
2211 MODULE_PARM_DESC(noaccel, "bool: disable acceleration");
2212 module_param(flatpanel, int, 0);
2213 MODULE_PARM_DESC(flatpanel, "Enables experimental flat panel support for some chipsets. (0 or 1=enabled) (default=0)");
2214 module_param(forceCRTC, int, 0);
2215 MODULE_PARM_DESC(forceCRTC, "Forces usage of a particular CRTC in case autodetection fails. (0 or 1) (default=autodetect)");
2217 module_param(nomtrr, bool, 0);
2218 MODULE_PARM_DESC(nomtrr, "Disables MTRR support (0 or 1=disabled) (default=0)");
2220 module_param(strictmode, bool, 0);
2221 MODULE_PARM_DESC(strictmode, "Only use video modes from EDID");
2223 MODULE_AUTHOR("Ani Joshi, maintainer");
2224 MODULE_DESCRIPTION("Framebuffer driver for nVidia Riva 128, TNT, TNT2, and the GeForce series");
2225 MODULE_LICENSE("GPL");