2 * drivers/w1/masters/omap_hdq.c
4 * Copyright (C) 2007 Texas Instruments, Inc.
6 * This file is licensed under the terms of the GNU General Public License
7 * version 2. This program is licensed "as is" without any warranty of any
8 * kind, whether express or implied.
11 #include <linux/kernel.h>
12 #include <linux/module.h>
13 #include <linux/platform_device.h>
14 #include <linux/interrupt.h>
15 #include <linux/err.h>
16 #include <linux/clk.h>
19 #include <mach/hardware.h>
22 #include "../w1_int.h"
24 #define MOD_NAME "OMAP_HDQ:"
26 #define OMAP_HDQ_REVISION 0x00
27 #define OMAP_HDQ_TX_DATA 0x04
28 #define OMAP_HDQ_RX_DATA 0x08
29 #define OMAP_HDQ_CTRL_STATUS 0x0c
30 #define OMAP_HDQ_CTRL_STATUS_INTERRUPTMASK (1<<6)
31 #define OMAP_HDQ_CTRL_STATUS_CLOCKENABLE (1<<5)
32 #define OMAP_HDQ_CTRL_STATUS_GO (1<<4)
33 #define OMAP_HDQ_CTRL_STATUS_INITIALIZATION (1<<2)
34 #define OMAP_HDQ_CTRL_STATUS_DIR (1<<1)
35 #define OMAP_HDQ_CTRL_STATUS_MODE (1<<0)
36 #define OMAP_HDQ_INT_STATUS 0x10
37 #define OMAP_HDQ_INT_STATUS_TXCOMPLETE (1<<2)
38 #define OMAP_HDQ_INT_STATUS_RXCOMPLETE (1<<1)
39 #define OMAP_HDQ_INT_STATUS_TIMEOUT (1<<0)
40 #define OMAP_HDQ_SYSCONFIG 0x14
41 #define OMAP_HDQ_SYSCONFIG_SOFTRESET (1<<1)
42 #define OMAP_HDQ_SYSCONFIG_AUTOIDLE (1<<0)
43 #define OMAP_HDQ_SYSSTATUS 0x18
44 #define OMAP_HDQ_SYSSTATUS_RESETDONE (1<<0)
46 #define OMAP_HDQ_FLAG_CLEAR 0
47 #define OMAP_HDQ_FLAG_SET 1
48 #define OMAP_HDQ_TIMEOUT (HZ/5)
50 #define OMAP_HDQ_MAX_USER 4
52 static DECLARE_WAIT_QUEUE_HEAD(hdq_wait_queue);
57 void __iomem *hdq_base;
58 /* lock status update */
59 struct mutex hdq_mutex;
65 spinlock_t hdq_spinlock;
67 * Used to control the call to omap_hdq_get and omap_hdq_put.
68 * HDQ Protocol: Write the CMD|REG_address first, followed by
69 * the data wrire or read.
74 static int omap_hdq_get(struct hdq_data *hdq_data);
75 static int omap_hdq_put(struct hdq_data *hdq_data);
76 static int omap_hdq_break(struct hdq_data *hdq_data);
78 static int __init omap_hdq_probe(struct platform_device *pdev);
79 static int omap_hdq_remove(struct platform_device *pdev);
81 static struct platform_driver omap_hdq_driver = {
82 .probe = omap_hdq_probe,
83 .remove = omap_hdq_remove,
89 static u8 omap_w1_read_byte(void *_hdq);
90 static void omap_w1_write_byte(void *_hdq, u8 byte);
91 static u8 omap_w1_reset_bus(void *_hdq);
92 static void omap_w1_search_bus(void *_hdq, u8 search_type,
93 w1_slave_found_callback slave_found);
96 static struct w1_bus_master omap_w1_master = {
97 .read_byte = omap_w1_read_byte,
98 .write_byte = omap_w1_write_byte,
99 .reset_bus = omap_w1_reset_bus,
100 .search = omap_w1_search_bus,
103 /* HDQ register I/O routines */
104 static inline u8 hdq_reg_in(struct hdq_data *hdq_data, u32 offset)
106 return __raw_readb(hdq_data->hdq_base + offset);
109 static inline void hdq_reg_out(struct hdq_data *hdq_data, u32 offset, u8 val)
111 __raw_writeb(val, hdq_data->hdq_base + offset);
114 static inline u8 hdq_reg_merge(struct hdq_data *hdq_data, u32 offset,
117 u8 new_val = (__raw_readb(hdq_data->hdq_base + offset) & ~mask)
119 __raw_writeb(new_val, hdq_data->hdq_base + offset);
125 * Wait for one or more bits in flag change.
126 * HDQ_FLAG_SET: wait until any bit in the flag is set.
127 * HDQ_FLAG_CLEAR: wait until all bits in the flag are cleared.
128 * return 0 on success and -ETIMEDOUT in the case of timeout.
130 static int hdq_wait_for_flag(struct hdq_data *hdq_data, u32 offset,
131 u8 flag, u8 flag_set, u8 *status)
134 unsigned long timeout = jiffies + OMAP_HDQ_TIMEOUT;
136 if (flag_set == OMAP_HDQ_FLAG_CLEAR) {
137 /* wait for the flag clear */
138 while (((*status = hdq_reg_in(hdq_data, offset)) & flag)
139 && time_before(jiffies, timeout)) {
140 set_current_state(TASK_UNINTERRUPTIBLE);
145 } else if (flag_set == OMAP_HDQ_FLAG_SET) {
146 /* wait for the flag set */
147 while (!((*status = hdq_reg_in(hdq_data, offset)) & flag)
148 && time_before(jiffies, timeout)) {
149 set_current_state(TASK_UNINTERRUPTIBLE);
152 if (!(*status & flag))
160 /* write out a byte and fill *status with HDQ_INT_STATUS */
161 static int hdq_write_byte(struct hdq_data *hdq_data, u8 val, u8 *status)
165 unsigned long irqflags;
169 spin_lock_irqsave(&hdq_data->hdq_spinlock, irqflags);
170 /* clear interrupt flags via a dummy read */
171 hdq_reg_in(hdq_data, OMAP_HDQ_INT_STATUS);
172 /* ISR loads it with new INT_STATUS */
173 hdq_data->hdq_irqstatus = 0;
174 spin_unlock_irqrestore(&hdq_data->hdq_spinlock, irqflags);
176 hdq_reg_out(hdq_data, OMAP_HDQ_TX_DATA, val);
179 hdq_reg_merge(hdq_data, OMAP_HDQ_CTRL_STATUS, OMAP_HDQ_CTRL_STATUS_GO,
180 OMAP_HDQ_CTRL_STATUS_DIR | OMAP_HDQ_CTRL_STATUS_GO);
181 /* wait for the TXCOMPLETE bit */
182 ret = wait_event_interruptible_timeout(hdq_wait_queue,
183 hdq_data->hdq_irqstatus, OMAP_HDQ_TIMEOUT);
185 dev_dbg(hdq_data->dev, "wait interrupted");
189 spin_lock_irqsave(&hdq_data->hdq_spinlock, irqflags);
190 *status = hdq_data->hdq_irqstatus;
191 spin_unlock_irqrestore(&hdq_data->hdq_spinlock, irqflags);
192 /* check irqstatus */
193 if (!(*status & OMAP_HDQ_INT_STATUS_TXCOMPLETE)) {
194 dev_dbg(hdq_data->dev, "timeout waiting for"
195 "TXCOMPLETE/RXCOMPLETE, %x", *status);
199 /* wait for the GO bit return to zero */
200 ret = hdq_wait_for_flag(hdq_data, OMAP_HDQ_CTRL_STATUS,
201 OMAP_HDQ_CTRL_STATUS_GO,
202 OMAP_HDQ_FLAG_CLEAR, &tmp_status);
204 dev_dbg(hdq_data->dev, "timeout waiting GO bit"
205 "return to zero, %x", tmp_status);
212 /* HDQ Interrupt service routine */
213 static irqreturn_t hdq_isr(int irq, void *_hdq)
215 struct hdq_data *hdq_data = _hdq;
216 unsigned long irqflags;
218 spin_lock_irqsave(&hdq_data->hdq_spinlock, irqflags);
219 hdq_data->hdq_irqstatus = hdq_reg_in(hdq_data, OMAP_HDQ_INT_STATUS);
220 spin_unlock_irqrestore(&hdq_data->hdq_spinlock, irqflags);
221 dev_dbg(hdq_data->dev, "hdq_isr: %x", hdq_data->hdq_irqstatus);
223 if (hdq_data->hdq_irqstatus &
224 (OMAP_HDQ_INT_STATUS_TXCOMPLETE | OMAP_HDQ_INT_STATUS_RXCOMPLETE
225 | OMAP_HDQ_INT_STATUS_TIMEOUT)) {
226 /* wake up sleeping process */
227 wake_up_interruptible(&hdq_wait_queue);
233 /* HDQ Mode: always return success */
234 static u8 omap_w1_reset_bus(void *_hdq)
239 /* W1 search callback function */
240 static void omap_w1_search_bus(void *_hdq, u8 search_type,
241 w1_slave_found_callback slave_found)
243 u64 module_id, rn_le, cs, id;
250 rn_le = cpu_to_le64(module_id);
252 * HDQ might not obey truly the 1-wire spec.
253 * So calculate CRC based on module parameter.
255 cs = w1_calc_crc8((u8 *)&rn_le, 7);
256 id = (cs << 56) | module_id;
258 slave_found(_hdq, id);
261 static int _omap_hdq_reset(struct hdq_data *hdq_data)
266 hdq_reg_out(hdq_data, OMAP_HDQ_SYSCONFIG, OMAP_HDQ_SYSCONFIG_SOFTRESET);
268 * Select HDQ mode & enable clocks.
269 * It is observed that INT flags can't be cleared via a read and GO/INIT
270 * won't return to zero if interrupt is disabled. So we always enable
273 hdq_reg_out(hdq_data, OMAP_HDQ_CTRL_STATUS,
274 OMAP_HDQ_CTRL_STATUS_CLOCKENABLE |
275 OMAP_HDQ_CTRL_STATUS_INTERRUPTMASK);
277 /* wait for reset to complete */
278 ret = hdq_wait_for_flag(hdq_data, OMAP_HDQ_SYSSTATUS,
279 OMAP_HDQ_SYSSTATUS_RESETDONE, OMAP_HDQ_FLAG_SET, &tmp_status);
281 dev_dbg(hdq_data->dev, "timeout waiting HDQ reset, %x",
284 hdq_reg_out(hdq_data, OMAP_HDQ_CTRL_STATUS,
285 OMAP_HDQ_CTRL_STATUS_CLOCKENABLE |
286 OMAP_HDQ_CTRL_STATUS_INTERRUPTMASK);
287 hdq_reg_out(hdq_data, OMAP_HDQ_SYSCONFIG,
288 OMAP_HDQ_SYSCONFIG_AUTOIDLE);
294 /* Issue break pulse to the device */
295 static int omap_hdq_break(struct hdq_data *hdq_data)
299 unsigned long irqflags;
301 ret = mutex_lock_interruptible(&hdq_data->hdq_mutex);
305 if (!hdq_data->hdq_usecount) {
306 mutex_unlock(&hdq_data->hdq_mutex);
310 spin_lock_irqsave(&hdq_data->hdq_spinlock, irqflags);
311 /* clear interrupt flags via a dummy read */
312 hdq_reg_in(hdq_data, OMAP_HDQ_INT_STATUS);
313 /* ISR loads it with new INT_STATUS */
314 hdq_data->hdq_irqstatus = 0;
315 spin_unlock_irqrestore(&hdq_data->hdq_spinlock, irqflags);
317 /* set the INIT and GO bit */
318 hdq_reg_merge(hdq_data, OMAP_HDQ_CTRL_STATUS,
319 OMAP_HDQ_CTRL_STATUS_INITIALIZATION | OMAP_HDQ_CTRL_STATUS_GO,
320 OMAP_HDQ_CTRL_STATUS_DIR | OMAP_HDQ_CTRL_STATUS_INITIALIZATION |
321 OMAP_HDQ_CTRL_STATUS_GO);
323 /* wait for the TIMEOUT bit */
324 ret = wait_event_interruptible_timeout(hdq_wait_queue,
325 hdq_data->hdq_irqstatus, OMAP_HDQ_TIMEOUT);
327 dev_dbg(hdq_data->dev, "wait interrupted");
328 mutex_unlock(&hdq_data->hdq_mutex);
332 spin_lock_irqsave(&hdq_data->hdq_spinlock, irqflags);
333 tmp_status = hdq_data->hdq_irqstatus;
334 spin_unlock_irqrestore(&hdq_data->hdq_spinlock, irqflags);
335 /* check irqstatus */
336 if (!(tmp_status & OMAP_HDQ_INT_STATUS_TIMEOUT)) {
337 dev_dbg(hdq_data->dev, "timeout waiting for TIMEOUT, %x",
339 mutex_unlock(&hdq_data->hdq_mutex);
343 * wait for both INIT and GO bits rerurn to zero.
344 * zero wait time expected for interrupt mode.
346 ret = hdq_wait_for_flag(hdq_data, OMAP_HDQ_CTRL_STATUS,
347 OMAP_HDQ_CTRL_STATUS_INITIALIZATION |
348 OMAP_HDQ_CTRL_STATUS_GO, OMAP_HDQ_FLAG_CLEAR,
351 dev_dbg(hdq_data->dev, "timeout waiting INIT&GO bits"
352 "return to zero, %x", tmp_status);
354 mutex_unlock(&hdq_data->hdq_mutex);
359 static int hdq_read_byte(struct hdq_data *hdq_data, u8 *val)
363 unsigned long irqflags;
364 unsigned long timeout = jiffies + OMAP_HDQ_TIMEOUT;
366 ret = mutex_lock_interruptible(&hdq_data->hdq_mutex);
370 if (!hdq_data->hdq_usecount) {
371 mutex_unlock(&hdq_data->hdq_mutex);
375 if (!(hdq_data->hdq_irqstatus & OMAP_HDQ_INT_STATUS_RXCOMPLETE)) {
376 hdq_reg_merge(hdq_data, OMAP_HDQ_CTRL_STATUS,
377 OMAP_HDQ_CTRL_STATUS_DIR | OMAP_HDQ_CTRL_STATUS_GO,
378 OMAP_HDQ_CTRL_STATUS_DIR | OMAP_HDQ_CTRL_STATUS_GO);
380 * The RX comes immediately after TX. It
381 * triggers another interrupt before we
382 * sleep. So we have to wait for RXCOMPLETE bit.
384 while (!(hdq_data->hdq_irqstatus
385 & OMAP_HDQ_INT_STATUS_RXCOMPLETE)
386 && time_before(jiffies, timeout)) {
387 set_current_state(TASK_UNINTERRUPTIBLE);
390 hdq_reg_merge(hdq_data, OMAP_HDQ_CTRL_STATUS, 0,
391 OMAP_HDQ_CTRL_STATUS_DIR);
392 spin_lock_irqsave(&hdq_data->hdq_spinlock, irqflags);
393 status = hdq_data->hdq_irqstatus;
394 spin_unlock_irqrestore(&hdq_data->hdq_spinlock, irqflags);
395 /* check irqstatus */
396 if (!(status & OMAP_HDQ_INT_STATUS_RXCOMPLETE)) {
397 dev_dbg(hdq_data->dev, "timeout waiting for"
398 "RXCOMPLETE, %x", status);
399 mutex_unlock(&hdq_data->hdq_mutex);
403 /* the data is ready. Read it in! */
404 *val = hdq_reg_in(hdq_data, OMAP_HDQ_RX_DATA);
405 mutex_unlock(&hdq_data->hdq_mutex);
411 /* Enable clocks and set the controller to HDQ mode */
412 static int omap_hdq_get(struct hdq_data *hdq_data)
416 ret = mutex_lock_interruptible(&hdq_data->hdq_mutex);
420 if (OMAP_HDQ_MAX_USER == hdq_data->hdq_usecount) {
421 dev_dbg(hdq_data->dev, "attempt to exceed the max use count");
422 mutex_unlock(&hdq_data->hdq_mutex);
425 hdq_data->hdq_usecount++;
426 try_module_get(THIS_MODULE);
427 if (1 == hdq_data->hdq_usecount) {
428 if (clk_enable(hdq_data->hdq_ick)) {
429 dev_dbg(hdq_data->dev, "Can not enable ick\n");
430 clk_put(hdq_data->hdq_ick);
431 clk_put(hdq_data->hdq_fck);
432 mutex_unlock(&hdq_data->hdq_mutex);
435 if (clk_enable(hdq_data->hdq_fck)) {
436 dev_dbg(hdq_data->dev, "Can not enable fck\n");
437 clk_put(hdq_data->hdq_ick);
438 clk_put(hdq_data->hdq_fck);
439 mutex_unlock(&hdq_data->hdq_mutex);
443 /* make sure HDQ is out of reset */
444 if (!(hdq_reg_in(hdq_data, OMAP_HDQ_SYSSTATUS) &
445 OMAP_HDQ_SYSSTATUS_RESETDONE)) {
446 ret = _omap_hdq_reset(hdq_data);
448 /* back up the count */
449 hdq_data->hdq_usecount--;
451 /* select HDQ mode & enable clocks */
452 hdq_reg_out(hdq_data, OMAP_HDQ_CTRL_STATUS,
453 OMAP_HDQ_CTRL_STATUS_CLOCKENABLE |
454 OMAP_HDQ_CTRL_STATUS_INTERRUPTMASK);
455 hdq_reg_out(hdq_data, OMAP_HDQ_SYSCONFIG,
456 OMAP_HDQ_SYSCONFIG_AUTOIDLE);
457 hdq_reg_in(hdq_data, OMAP_HDQ_INT_STATUS);
461 mutex_unlock(&hdq_data->hdq_mutex);
466 /* Disable clocks to the module */
467 static int omap_hdq_put(struct hdq_data *hdq_data)
471 ret = mutex_lock_interruptible(&hdq_data->hdq_mutex);
475 if (0 == hdq_data->hdq_usecount) {
476 dev_dbg(hdq_data->dev, "attempt to decrement use count"
480 hdq_data->hdq_usecount--;
481 module_put(THIS_MODULE);
482 if (0 == hdq_data->hdq_usecount) {
483 clk_disable(hdq_data->hdq_ick);
484 clk_disable(hdq_data->hdq_fck);
487 mutex_unlock(&hdq_data->hdq_mutex);
492 /* Read a byte of data from the device */
493 static u8 omap_w1_read_byte(void *_hdq)
495 struct hdq_data *hdq_data = _hdq;
499 ret = hdq_read_byte(hdq_data, &val);
501 ret = mutex_lock_interruptible(&hdq_data->hdq_mutex);
503 dev_dbg(hdq_data->dev, "Could not acquire mutex\n");
506 hdq_data->init_trans = 0;
507 mutex_unlock(&hdq_data->hdq_mutex);
508 omap_hdq_put(hdq_data);
512 /* Write followed by a read, release the module */
513 if (hdq_data->init_trans) {
514 ret = mutex_lock_interruptible(&hdq_data->hdq_mutex);
516 dev_dbg(hdq_data->dev, "Could not acquire mutex\n");
519 hdq_data->init_trans = 0;
520 mutex_unlock(&hdq_data->hdq_mutex);
521 omap_hdq_put(hdq_data);
527 /* Write a byte of data to the device */
528 static void omap_w1_write_byte(void *_hdq, u8 byte)
530 struct hdq_data *hdq_data = _hdq;
534 /* First write to initialize the transfer */
535 if (hdq_data->init_trans == 0)
536 omap_hdq_get(hdq_data);
538 ret = mutex_lock_interruptible(&hdq_data->hdq_mutex);
540 dev_dbg(hdq_data->dev, "Could not acquire mutex\n");
543 hdq_data->init_trans++;
544 mutex_unlock(&hdq_data->hdq_mutex);
546 hdq_write_byte(hdq_data, byte, &status);
547 dev_dbg(hdq_data->dev, "Ctrl status %x\n", status);
549 /* Second write, data transfered. Release the module */
550 if (hdq_data->init_trans > 1) {
551 omap_hdq_put(hdq_data);
552 ret = mutex_lock_interruptible(&hdq_data->hdq_mutex);
554 dev_dbg(hdq_data->dev, "Could not acquire mutex\n");
557 hdq_data->init_trans = 0;
558 mutex_unlock(&hdq_data->hdq_mutex);
564 static int __init omap_hdq_probe(struct platform_device *pdev)
566 struct hdq_data *hdq_data;
567 struct resource *res;
574 hdq_data = kmalloc(sizeof(*hdq_data), GFP_KERNEL);
576 dev_dbg(&pdev->dev, "unable to allocate memory\n");
581 hdq_data->dev = &pdev->dev;
582 platform_set_drvdata(pdev, hdq_data);
584 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
586 dev_dbg(&pdev->dev, "unable to get resource\n");
591 hdq_data->hdq_base = ioremap(res->start, SZ_4K);
592 if (!hdq_data->hdq_base) {
593 dev_dbg(&pdev->dev, "ioremap failed\n");
598 /* get interface & functional clock objects */
599 hdq_data->hdq_ick = clk_get(&pdev->dev, "hdq_ick");
600 hdq_data->hdq_fck = clk_get(&pdev->dev, "hdq_fck");
602 if (IS_ERR(hdq_data->hdq_ick) || IS_ERR(hdq_data->hdq_fck)) {
603 dev_dbg(&pdev->dev, "Can't get HDQ clock objects\n");
604 if (IS_ERR(hdq_data->hdq_ick)) {
605 ret = PTR_ERR(hdq_data->hdq_ick);
608 if (IS_ERR(hdq_data->hdq_fck)) {
609 ret = PTR_ERR(hdq_data->hdq_fck);
610 clk_put(hdq_data->hdq_ick);
615 hdq_data->hdq_usecount = 0;
616 mutex_init(&hdq_data->hdq_mutex);
618 if (clk_enable(hdq_data->hdq_ick)) {
619 dev_dbg(&pdev->dev, "Can not enable ick\n");
624 if (clk_enable(hdq_data->hdq_fck)) {
625 dev_dbg(&pdev->dev, "Can not enable fck\n");
630 rev = hdq_reg_in(hdq_data, OMAP_HDQ_REVISION);
631 dev_info(&pdev->dev, "OMAP HDQ Hardware Rev %c.%c. Driver in %s mode\n",
632 (rev >> 4) + '0', (rev & 0x0f) + '0', "Interrupt");
634 spin_lock_init(&hdq_data->hdq_spinlock);
635 omap_hdq_break(hdq_data);
637 irq = platform_get_irq(pdev, 0);
643 ret = request_irq(irq, hdq_isr, IRQF_DISABLED, "omap_hdq", hdq_data);
645 dev_dbg(&pdev->dev, "could not request irq\n");
649 /* don't clock the HDQ until it is needed */
650 clk_disable(hdq_data->hdq_ick);
651 clk_disable(hdq_data->hdq_fck);
653 omap_w1_master.data = hdq_data;
655 ret = w1_add_master_device(&omap_w1_master);
657 dev_dbg(&pdev->dev, "Failure in registering w1 master\n");
665 clk_disable(hdq_data->hdq_fck);
668 clk_disable(hdq_data->hdq_ick);
671 clk_put(hdq_data->hdq_ick);
672 clk_put(hdq_data->hdq_fck);
675 iounmap(hdq_data->hdq_base);
679 platform_set_drvdata(pdev, NULL);
687 static int omap_hdq_remove(struct platform_device *pdev)
689 struct hdq_data *hdq_data = platform_get_drvdata(pdev);
691 mutex_lock(&hdq_data->hdq_mutex);
693 if (0 != hdq_data->hdq_usecount) {
694 dev_dbg(&pdev->dev, "removed when use count is not zero\n");
698 mutex_unlock(&hdq_data->hdq_mutex);
700 /* remove module dependency */
701 clk_put(hdq_data->hdq_ick);
702 clk_put(hdq_data->hdq_fck);
703 free_irq(INT_24XX_HDQ_IRQ, hdq_data);
704 platform_set_drvdata(pdev, NULL);
705 iounmap(hdq_data->hdq_base);
714 return platform_driver_register(&omap_hdq_driver);
716 module_init(omap_hdq_init);
721 platform_driver_unregister(&omap_hdq_driver);
723 module_exit(omap_hdq_exit);
725 module_param(w1_id, int, S_IRUSR);
726 MODULE_PARM_DESC(w1_id, "1-wire id for the slave detection");
728 MODULE_AUTHOR("Texas Instruments");
729 MODULE_DESCRIPTION("HDQ driver Library");
730 MODULE_LICENSE("GPL");