2 * Copyright(c) 2006, Intel Corporation.
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * You should have received a copy of the GNU General Public License along with
14 * this program; if not, write to the Free Software Foundation, Inc.,
15 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
20 #include <linux/types.h>
22 #include <asm/hardware.h>
23 #include <asm/hardware/iop_adma.h>
25 #define ADMA_ACCR(chan) (chan->mmr_base + 0x0)
26 #define ADMA_ACSR(chan) (chan->mmr_base + 0x4)
27 #define ADMA_ADAR(chan) (chan->mmr_base + 0x8)
28 #define ADMA_IIPCR(chan) (chan->mmr_base + 0x18)
29 #define ADMA_IIPAR(chan) (chan->mmr_base + 0x1c)
30 #define ADMA_IIPUAR(chan) (chan->mmr_base + 0x20)
31 #define ADMA_ANDAR(chan) (chan->mmr_base + 0x24)
32 #define ADMA_ADCR(chan) (chan->mmr_base + 0x28)
33 #define ADMA_CARMD(chan) (chan->mmr_base + 0x2c)
34 #define ADMA_ABCR(chan) (chan->mmr_base + 0x30)
35 #define ADMA_DLADR(chan) (chan->mmr_base + 0x34)
36 #define ADMA_DUADR(chan) (chan->mmr_base + 0x38)
37 #define ADMA_SLAR(src, chan) (chan->mmr_base + (0x3c + (src << 3)))
38 #define ADMA_SUAR(src, chan) (chan->mmr_base + (0x40 + (src << 3)))
40 struct iop13xx_adma_src {
45 unsigned int pq_upper_src_addr:24;
46 unsigned int pq_dmlt:8;
51 struct iop13xx_adma_desc_ctrl {
52 unsigned int int_en:1;
53 unsigned int xfer_dir:2;
54 unsigned int src_select:4;
55 unsigned int zero_result:1;
56 unsigned int block_fill_en:1;
57 unsigned int crc_gen_en:1;
58 unsigned int crc_xfer_dis:1;
59 unsigned int crc_seed_fetch_dis:1;
60 unsigned int status_write_back_en:1;
61 unsigned int endian_swap_en:1;
62 unsigned int reserved0:2;
63 unsigned int pq_update_xfer_en:1;
64 unsigned int dual_xor_en:1;
65 unsigned int pq_xfer_en:1;
66 unsigned int p_xfer_dis:1;
67 unsigned int reserved1:10;
68 unsigned int relax_order_en:1;
69 unsigned int no_snoop_en:1;
72 struct iop13xx_adma_byte_count {
73 unsigned int byte_count:24;
74 unsigned int host_if:3;
75 unsigned int reserved:2;
76 unsigned int zero_result_err_q:1;
77 unsigned int zero_result_err:1;
78 unsigned int tx_complete:1;
81 struct iop13xx_adma_desc_hw {
85 struct iop13xx_adma_desc_ctrl desc_ctrl_field;
94 struct iop13xx_adma_byte_count byte_count_field;
102 u32 pq_upper_dest_addr;
104 struct iop13xx_adma_src src[1];
107 struct iop13xx_adma_desc_dual_xor {
113 u32 h_upper_dest_addr;
119 u32 h_upper_src_addr;
121 u32 d_upper_src_addr;
123 u32 d_upper_dest_addr;
126 struct iop13xx_adma_desc_pq_update {
132 u32 p_upper_dest_addr;
138 u32 p_upper_src_addr;
141 unsigned int q_upper_src_addr:24;
142 unsigned int q_dmlt:8;
145 u32 q_upper_dest_addr;
148 static inline int iop_adma_get_max_xor(void)
153 static inline u32 iop_chan_get_current_descriptor(struct iop_adma_chan *chan)
155 return __raw_readl(ADMA_ADAR(chan));
158 static inline void iop_chan_set_next_descriptor(struct iop_adma_chan *chan,
161 __raw_writel(next_desc_addr, ADMA_ANDAR(chan));
164 #define ADMA_STATUS_BUSY (1 << 13)
166 static inline char iop_chan_is_busy(struct iop_adma_chan *chan)
168 if (__raw_readl(ADMA_ACSR(chan)) &
176 iop_chan_get_desc_align(struct iop_adma_chan *chan, int num_slots)
180 #define iop_desc_is_aligned(x, y) 1
183 iop_chan_memcpy_slot_count(size_t len, int *slots_per_op)
189 #define iop_chan_interrupt_slot_count(s, c) iop_chan_memcpy_slot_count(0, s)
192 iop_chan_memset_slot_count(size_t len, int *slots_per_op)
199 iop_chan_xor_slot_count(size_t len, int src_cnt, int *slots_per_op)
202 /* slots_to_find = 1 for basic descriptor + 1 per 4 sources above 1
203 * (1 source => 8 bytes) (1 slot => 32 bytes)
205 num_slots = 1 + (((src_cnt - 1) << 3) >> 5);
206 if (((src_cnt - 1) << 3) & 0x1f)
209 *slots_per_op = num_slots;
214 #define ADMA_MAX_BYTE_COUNT (16 * 1024 * 1024)
215 #define IOP_ADMA_MAX_BYTE_COUNT ADMA_MAX_BYTE_COUNT
216 #define IOP_ADMA_ZERO_SUM_MAX_BYTE_COUNT ADMA_MAX_BYTE_COUNT
217 #define IOP_ADMA_XOR_MAX_BYTE_COUNT ADMA_MAX_BYTE_COUNT
218 #define iop_chan_zero_sum_slot_count(l, s, o) iop_chan_xor_slot_count(l, s, o)
220 static inline u32 iop_desc_get_dest_addr(struct iop_adma_desc_slot *desc,
221 struct iop_adma_chan *chan)
223 struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc;
224 return hw_desc->dest_addr;
227 static inline u32 iop_desc_get_byte_count(struct iop_adma_desc_slot *desc,
228 struct iop_adma_chan *chan)
230 struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc;
231 return hw_desc->byte_count_field.byte_count;
234 static inline u32 iop_desc_get_src_addr(struct iop_adma_desc_slot *desc,
235 struct iop_adma_chan *chan,
238 struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc;
239 return hw_desc->src[src_idx].src_addr;
242 static inline u32 iop_desc_get_src_count(struct iop_adma_desc_slot *desc,
243 struct iop_adma_chan *chan)
245 struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc;
246 return hw_desc->desc_ctrl_field.src_select + 1;
250 iop_desc_init_memcpy(struct iop_adma_desc_slot *desc, int int_en)
252 struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc;
255 struct iop13xx_adma_desc_ctrl field;
258 u_desc_ctrl.value = 0;
259 u_desc_ctrl.field.xfer_dir = 3; /* local to internal bus */
260 u_desc_ctrl.field.int_en = int_en;
261 hw_desc->desc_ctrl = u_desc_ctrl.value;
262 hw_desc->crc_addr = 0;
266 iop_desc_init_memset(struct iop_adma_desc_slot *desc, int int_en)
268 struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc;
271 struct iop13xx_adma_desc_ctrl field;
274 u_desc_ctrl.value = 0;
275 u_desc_ctrl.field.xfer_dir = 3; /* local to internal bus */
276 u_desc_ctrl.field.block_fill_en = 1;
277 u_desc_ctrl.field.int_en = int_en;
278 hw_desc->desc_ctrl = u_desc_ctrl.value;
279 hw_desc->crc_addr = 0;
282 /* to do: support buffers larger than ADMA_MAX_BYTE_COUNT */
284 iop_desc_init_xor(struct iop_adma_desc_slot *desc, int src_cnt, int int_en)
286 struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc;
289 struct iop13xx_adma_desc_ctrl field;
292 u_desc_ctrl.value = 0;
293 u_desc_ctrl.field.src_select = src_cnt - 1;
294 u_desc_ctrl.field.xfer_dir = 3; /* local to internal bus */
295 u_desc_ctrl.field.int_en = int_en;
296 hw_desc->desc_ctrl = u_desc_ctrl.value;
297 hw_desc->crc_addr = 0;
300 #define iop_desc_init_null_xor(d, s, i) iop_desc_init_xor(d, s, i)
302 /* to do: support buffers larger than ADMA_MAX_BYTE_COUNT */
304 iop_desc_init_zero_sum(struct iop_adma_desc_slot *desc, int src_cnt, int int_en)
306 struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc;
309 struct iop13xx_adma_desc_ctrl field;
312 u_desc_ctrl.value = 0;
313 u_desc_ctrl.field.src_select = src_cnt - 1;
314 u_desc_ctrl.field.xfer_dir = 3; /* local to internal bus */
315 u_desc_ctrl.field.zero_result = 1;
316 u_desc_ctrl.field.status_write_back_en = 1;
317 u_desc_ctrl.field.int_en = int_en;
318 hw_desc->desc_ctrl = u_desc_ctrl.value;
319 hw_desc->crc_addr = 0;
324 static inline void iop_desc_set_byte_count(struct iop_adma_desc_slot *desc,
325 struct iop_adma_chan *chan,
328 struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc;
329 hw_desc->byte_count = byte_count;
333 iop_desc_set_zero_sum_byte_count(struct iop_adma_desc_slot *desc, u32 len)
335 int slots_per_op = desc->slots_per_op;
336 struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc, *iter;
339 if (len <= IOP_ADMA_ZERO_SUM_MAX_BYTE_COUNT) {
340 hw_desc->byte_count = len;
343 iter = iop_hw_desc_slot_idx(hw_desc, i);
344 iter->byte_count = IOP_ADMA_ZERO_SUM_MAX_BYTE_COUNT;
345 len -= IOP_ADMA_ZERO_SUM_MAX_BYTE_COUNT;
347 } while (len > IOP_ADMA_ZERO_SUM_MAX_BYTE_COUNT);
350 iter = iop_hw_desc_slot_idx(hw_desc, i);
351 iter->byte_count = len;
357 static inline void iop_desc_set_dest_addr(struct iop_adma_desc_slot *desc,
358 struct iop_adma_chan *chan,
361 struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc;
362 hw_desc->dest_addr = addr;
363 hw_desc->upper_dest_addr = 0;
366 static inline void iop_desc_set_memcpy_src_addr(struct iop_adma_desc_slot *desc,
369 struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc;
370 hw_desc->src[0].src_addr = addr;
371 hw_desc->src[0].upper_src_addr = 0;
374 static inline void iop_desc_set_xor_src_addr(struct iop_adma_desc_slot *desc,
375 int src_idx, dma_addr_t addr)
377 int slot_cnt = desc->slot_cnt, slots_per_op = desc->slots_per_op;
378 struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc, *iter;
382 iter = iop_hw_desc_slot_idx(hw_desc, i);
383 iter->src[src_idx].src_addr = addr;
384 iter->src[src_idx].upper_src_addr = 0;
385 slot_cnt -= slots_per_op;
388 addr += IOP_ADMA_XOR_MAX_BYTE_COUNT;
394 iop_desc_init_interrupt(struct iop_adma_desc_slot *desc,
395 struct iop_adma_chan *chan)
397 iop_desc_init_memcpy(desc, 1);
398 iop_desc_set_byte_count(desc, chan, 0);
399 iop_desc_set_dest_addr(desc, chan, 0);
400 iop_desc_set_memcpy_src_addr(desc, 0);
403 #define iop_desc_set_zero_sum_src_addr iop_desc_set_xor_src_addr
405 static inline void iop_desc_set_next_desc(struct iop_adma_desc_slot *desc,
408 struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc;
409 BUG_ON(hw_desc->next_desc);
410 hw_desc->next_desc = next_desc_addr;
413 static inline u32 iop_desc_get_next_desc(struct iop_adma_desc_slot *desc)
415 struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc;
416 return hw_desc->next_desc;
419 static inline void iop_desc_clear_next_desc(struct iop_adma_desc_slot *desc)
421 struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc;
422 hw_desc->next_desc = 0;
425 static inline void iop_desc_set_block_fill_val(struct iop_adma_desc_slot *desc,
428 struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc;
429 hw_desc->block_fill_data = val;
432 static inline int iop_desc_get_zero_result(struct iop_adma_desc_slot *desc)
434 struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc;
435 struct iop13xx_adma_desc_ctrl desc_ctrl = hw_desc->desc_ctrl_field;
436 struct iop13xx_adma_byte_count byte_count = hw_desc->byte_count_field;
438 BUG_ON(!(byte_count.tx_complete && desc_ctrl.zero_result));
440 if (desc_ctrl.pq_xfer_en)
441 return byte_count.zero_result_err_q;
443 return byte_count.zero_result_err;
446 static inline void iop_chan_append(struct iop_adma_chan *chan)
450 adma_accr = __raw_readl(ADMA_ACCR(chan));
452 __raw_writel(adma_accr, ADMA_ACCR(chan));
455 static inline void iop_chan_idle(int busy, struct iop_adma_chan *chan)
460 static inline u32 iop_chan_get_status(struct iop_adma_chan *chan)
462 return __raw_readl(ADMA_ACSR(chan));
465 static inline void iop_chan_disable(struct iop_adma_chan *chan)
467 u32 adma_chan_ctrl = __raw_readl(ADMA_ACCR(chan));
468 adma_chan_ctrl &= ~0x1;
469 __raw_writel(adma_chan_ctrl, ADMA_ACCR(chan));
472 static inline void iop_chan_enable(struct iop_adma_chan *chan)
476 adma_chan_ctrl = __raw_readl(ADMA_ACCR(chan));
477 adma_chan_ctrl |= 0x1;
478 __raw_writel(adma_chan_ctrl, ADMA_ACCR(chan));
481 static inline void iop_adma_device_clear_eot_status(struct iop_adma_chan *chan)
483 u32 status = __raw_readl(ADMA_ACSR(chan));
485 __raw_writel(status, ADMA_ACSR(chan));
488 static inline void iop_adma_device_clear_eoc_status(struct iop_adma_chan *chan)
490 u32 status = __raw_readl(ADMA_ACSR(chan));
492 __raw_writel(status, ADMA_ACSR(chan));
495 static inline void iop_adma_device_clear_err_status(struct iop_adma_chan *chan)
497 u32 status = __raw_readl(ADMA_ACSR(chan));
498 status &= (1 << 9) | (1 << 5) | (1 << 4) | (1 << 3);
499 __raw_writel(status, ADMA_ACSR(chan));
503 iop_is_err_int_parity(unsigned long status, struct iop_adma_chan *chan)
505 return test_bit(9, &status);
509 iop_is_err_mcu_abort(unsigned long status, struct iop_adma_chan *chan)
511 return test_bit(5, &status);
515 iop_is_err_int_tabort(unsigned long status, struct iop_adma_chan *chan)
517 return test_bit(4, &status);
521 iop_is_err_int_mabort(unsigned long status, struct iop_adma_chan *chan)
523 return test_bit(3, &status);
527 iop_is_err_pci_tabort(unsigned long status, struct iop_adma_chan *chan)
533 iop_is_err_pci_mabort(unsigned long status, struct iop_adma_chan *chan)
539 iop_is_err_split_tx(unsigned long status, struct iop_adma_chan *chan)