include/asm-blackfin/mach-bf548/bfin_serial_5xx.h

   1 #include <linux/serial.h>
   2 #include <asm/dma.h>
   3 #include <asm/portmux.h>
   4
   5 #define NR_PORTS                4
   6
   7 #define OFFSET_DLL              0x00    /* Divisor Latch (Low-Byte)             */
   8 #define OFFSET_DLH              0x04    /* Divisor Latch (High-Byte)            */
   9 #define OFFSET_GCTL             0x08    /* Global Control Register              */
  10 #define OFFSET_LCR              0x0C    /* Line Control Register                */
  11 #define OFFSET_MCR              0x10    /* Modem Control Register               */
  12 #define OFFSET_LSR              0x14    /* Line Status Register                 */
  13 #define OFFSET_MSR              0x18    /* Modem Status Register                */
  14 #define OFFSET_SCR              0x1C    /* SCR Scratch Register                 */
  15 #define OFFSET_IER_SET          0x20    /* Set Interrupt Enable Register        */
  16 #define OFFSET_IER_CLEAR        0x24    /* Clear Interrupt Enable Register      */
  17 #define OFFSET_THR              0x28    /* Transmit Holding register            */
  18 #define OFFSET_RBR              0x2C    /* Receive Buffer register              */
  19
  20 #define UART_GET_CHAR(uart)     bfin_read16(((uart)->port.membase + OFFSET_RBR))
  21 #define UART_GET_DLL(uart)      bfin_read16(((uart)->port.membase + OFFSET_DLL))
  22 #define UART_GET_DLH(uart)      bfin_read16(((uart)->port.membase + OFFSET_DLH))
  23 #define UART_GET_IER(uart)      bfin_read16(((uart)->port.membase + OFFSET_IER_SET))
  24 #define UART_GET_LCR(uart)      bfin_read16(((uart)->port.membase + OFFSET_LCR))
  25 #define UART_GET_LSR(uart)      bfin_read16(((uart)->port.membase + OFFSET_LSR))
  26 #define UART_GET_GCTL(uart)     bfin_read16(((uart)->port.membase + OFFSET_GCTL))
  27
  28 #define UART_PUT_CHAR(uart,v)   bfin_write16(((uart)->port.membase + OFFSET_THR),v)
  29 #define UART_PUT_DLL(uart,v)    bfin_write16(((uart)->port.membase + OFFSET_DLL),v)
  30 #define UART_SET_IER(uart,v)    bfin_write16(((uart)->port.membase + OFFSET_IER_SET),v)
  31 #define UART_CLEAR_IER(uart,v)    bfin_write16(((uart)->port.membase + OFFSET_IER_CLEAR),v)
  32 #define UART_PUT_DLH(uart,v)    bfin_write16(((uart)->port.membase + OFFSET_DLH),v)
  33 #define UART_PUT_LSR(uart,v)    bfin_write16(((uart)->port.membase + OFFSET_LSR),v)
  34 #define UART_PUT_LCR(uart,v)    bfin_write16(((uart)->port.membase + OFFSET_LCR),v)
  35 #define UART_CLEAR_LSR(uart)    bfin_write16(((uart)->port.membase + OFFSET_LSR), -1)
  36 #define UART_PUT_GCTL(uart,v)   bfin_write16(((uart)->port.membase + OFFSET_GCTL),v)
  37
  38 #if defined(CONFIG_BFIN_UART0_CTSRTS) || defined(CONFIG_BFIN_UART1_CTSRTS)
  39 # define CONFIG_SERIAL_BFIN_CTSRTS
  40
  41 # ifndef CONFIG_UART0_CTS_PIN
  42 #  define CONFIG_UART0_CTS_PIN -1
  43 # endif
  44
  45 # ifndef CONFIG_UART0_RTS_PIN
  46 #  define CONFIG_UART0_RTS_PIN -1
  47 # endif
  48
  49 # ifndef CONFIG_UART1_CTS_PIN
  50 #  define CONFIG_UART1_CTS_PIN -1
  51 # endif
  52
  53 # ifndef CONFIG_UART1_RTS_PIN
  54 #  define CONFIG_UART1_RTS_PIN -1
  55 # endif
  56 #endif
  57 /*
  58  * The pin configuration is different from schematic
  59  */
  60 struct bfin_serial_port {
  61         struct uart_port        port;
  62         unsigned int            old_status;
  63 #ifdef CONFIG_SERIAL_BFIN_DMA
  64         int                     tx_done;
  65         int                     tx_count;
  66         struct circ_buf         rx_dma_buf;
  67         struct timer_list       rx_dma_timer;
  68         int                     rx_dma_nrows;
  69         unsigned int            tx_dma_channel;
  70         unsigned int            rx_dma_channel;
  71         struct work_struct      tx_dma_workqueue;
  72 #else
  73         struct work_struct      cts_workqueue;
  74 #endif
  75 #ifdef CONFIG_SERIAL_BFIN_CTSRTS
  76         int             cts_pin;
  77         int             rts_pin;
  78 #endif
  79 };
  80
  81 struct bfin_serial_port bfin_serial_ports[NR_PORTS];
  82 struct bfin_serial_res {
  83         unsigned long   uart_base_addr;
  84         int             uart_irq;
  85 #ifdef CONFIG_SERIAL_BFIN_DMA
  86         unsigned int    uart_tx_dma_channel;
  87         unsigned int    uart_rx_dma_channel;
  88 #endif
  89 #ifdef CONFIG_SERIAL_BFIN_CTSRTS
  90         int     uart_cts_pin;
  91         int     uart_rts_pin;
  92 #endif
  93 };
  94
  95 struct bfin_serial_res bfin_serial_resource[] = {
  96 #ifdef CONFIG_SERIAL_BFIN_UART0
  97         {
  98         0xFFC00400,
  99         IRQ_UART0_RX,
 100 #ifdef CONFIG_SERIAL_BFIN_DMA
 101         CH_UART0_TX,
 102         CH_UART0_RX,
 103 #endif
 104 #ifdef CONFIG_BFIN_UART0_CTSRTS
 105         CONFIG_UART0_CTS_PIN,
 106         CONFIG_UART0_RTS_PIN,
 107 #endif
 108         },
 109 #endif
 110 #ifdef CONFIG_SERIAL_BFIN_UART1
 111         {
 112         0xFFC02000,
 113         IRQ_UART1_RX,
 114 #ifdef CONFIG_SERIAL_BFIN_DMA
 115         CH_UART1_TX,
 116         CH_UART1_RX,
 117 #endif
 118         },
 119 #endif
 120 #ifdef CONFIG_SERIAL_BFIN_UART2
 121         {
 122         0xFFC02100,
 123         IRQ_UART2_RX,
 124 #ifdef CONFIG_SERIAL_BFIN_DMA
 125         CH_UART2_TX,
 126         CH_UART2_RX,
 127 #endif
 128 #ifdef CONFIG_BFIN_UART2_CTSRTS
 129         CONFIG_UART2_CTS_PIN,
 130         CONFIG_UART2_RTS_PIN,
 131 #endif
 132         },
 133 #endif
 134 #ifdef CONFIG_SERIAL_BFIN_UART3
 135         {
 136         0xFFC03100,
 137         IRQ_UART3_RX,
 138 #ifdef CONFIG_SERIAL_BFIN_DMA
 139         CH_UART3_TX,
 140         CH_UART3_RX,
 141 #endif
 142         },
 143 #endif
 144 };
 145
 146 int nr_ports = ARRAY_SIZE(bfin_serial_resource);
 147
 148 #define DRIVER_NAME "bfin-uart"
 149
 150 static void bfin_serial_hw_init(struct bfin_serial_port *uart)
 151 {
 152 #ifdef CONFIG_SERIAL_BFIN_UART0
 153         peripheral_request(P_UART0_TX, DRIVER_NAME);
 154         peripheral_request(P_UART0_RX, DRIVER_NAME);
 155 #endif
 156
 157 #ifdef CONFIG_SERIAL_BFIN_UART1
 158         peripheral_request(P_UART1_TX, DRIVER_NAME);
 159         peripheral_request(P_UART1_RX, DRIVER_NAME);
 160
 161 #ifdef CONFIG_BFIN_UART1_CTSRTS
 162         peripheral_request(P_UART1_RTS, DRIVER_NAME);
 163         peripheral_request(P_UART1_CTS DRIVER_NAME);
 164 #endif
 165 #endif
 166
 167 #ifdef CONFIG_SERIAL_BFIN_UART2
 168         peripheral_request(P_UART2_TX, DRIVER_NAME);
 169         peripheral_request(P_UART2_RX, DRIVER_NAME);
 170 #endif
 171
 172 #ifdef CONFIG_SERIAL_BFIN_UART3
 173         peripheral_request(P_UART3_TX, DRIVER_NAME);
 174         peripheral_request(P_UART3_RX, DRIVER_NAME);
 175
 176 #ifdef CONFIG_BFIN_UART3_CTSRTS
 177         peripheral_request(P_UART3_RTS, DRIVER_NAME);
 178         peripheral_request(P_UART3_CTS DRIVER_NAME);
 179 #endif
 180 #endif
 181         SSYNC();
 182 #ifdef CONFIG_SERIAL_BFIN_CTSRTS
 183         if (uart->cts_pin >= 0) {
 184                 gpio_request(uart->cts_pin, DRIVER_NAME);
 185                 gpio_direction_input(uart->cts_pin);
 186         }
 187
 188         if (uart->rts_pin >= 0) {
 189                 gpio_request(uart->rts_pin, DRIVER_NAME);
 190                 gpio_direction_output(uart->rts_pin, 0);
 191         }
 192 #endif
 193 }