2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * Copyright (c) 1992-1999,2001-2005 Silicon Graphics, Inc. All rights reserved.
9 #ifndef _ASM_IA64_SN_ADDRS_H
10 #define _ASM_IA64_SN_ADDRS_H
12 #include <asm/percpu.h>
13 #include <asm/sn/types.h>
14 #include <asm/sn/arch.h>
15 #include <asm/sn/pda.h>
18 * Memory/SHUB Address Format:
19 * +-+---------+--+--------------+
20 * |0| NASID |AS| NodeOffset |
21 * +-+---------+--+--------------+
23 * NASID: (low NASID bit is 0) Memory and SHUB MMRs
24 * AS: 2-bit Address Space Identifier. Used only if low NASID bit is 0
25 * 00: Local Resources and MMR space
26 * Top bit of NodeOffset
27 * 0: Local resources space
29 * 0: IA64/NT compatibility space
31 * 4: Local memory, regardless of local node id
35 * 11: Cacheable memory space.
37 * NodeOffset: byte offset
41 * +-+----------+--+--------------+
42 * |0| NASID |AS| Nodeoffset |
43 * +-+----------+--+--------------+
45 * NASID: (low NASID bit is 1) TIO
46 * AS: 2-bit Chiplet Identifier
47 * 00: TIO LB (Indicates TIO MMR access.)
48 * 01: TIO ICE (indicates coretalk space access.)
50 * NodeOffset: top bit must be set.
53 * Note that in both of the above address formats, the low
54 * NASID bit indicates if the reference is to the SHUB or TIO MMRs.
59 * Define basic shift & mask constants for manipulating NASIDs and AS values.
61 #define NASID_BITMASK (sn_hub_info->nasid_bitmask)
62 #define NASID_SHIFT (sn_hub_info->nasid_shift)
63 #define AS_SHIFT (sn_hub_info->as_shift)
64 #define AS_BITMASK 0x3UL
66 #define NASID_MASK ((u64)NASID_BITMASK << NASID_SHIFT)
67 #define AS_MASK ((u64)AS_BITMASK << AS_SHIFT)
68 #define REGION_BITS 0xe000000000000000UL
72 * AS values. These are the same on both SHUB1 & SHUB2.
74 #define AS_GET_VAL 1UL
75 #define AS_AMO_VAL 2UL
76 #define AS_CAC_VAL 3UL
77 #define AS_GET_SPACE (AS_GET_VAL << AS_SHIFT)
78 #define AS_AMO_SPACE (AS_AMO_VAL << AS_SHIFT)
79 #define AS_CAC_SPACE (AS_CAC_VAL << AS_SHIFT)
83 * Base addresses for various address ranges.
85 #define CACHED 0xe000000000000000UL
86 #define UNCACHED 0xc000000000000000UL
87 #define UNCACHED_PHYS 0x8000000000000000UL
91 * Virtual Mode Local & Global MMR space.
93 #define SH1_LOCAL_MMR_OFFSET 0x8000000000UL
94 #define SH2_LOCAL_MMR_OFFSET 0x0200000000UL
95 #define LOCAL_MMR_OFFSET (is_shub2() ? SH2_LOCAL_MMR_OFFSET : SH1_LOCAL_MMR_OFFSET)
96 #define LOCAL_MMR_SPACE (UNCACHED | LOCAL_MMR_OFFSET)
97 #define LOCAL_PHYS_MMR_SPACE (UNCACHED_PHYS | LOCAL_MMR_OFFSET)
99 #define SH1_GLOBAL_MMR_OFFSET 0x0800000000UL
100 #define SH2_GLOBAL_MMR_OFFSET 0x0300000000UL
101 #define GLOBAL_MMR_OFFSET (is_shub2() ? SH2_GLOBAL_MMR_OFFSET : SH1_GLOBAL_MMR_OFFSET)
102 #define GLOBAL_MMR_SPACE (UNCACHED | GLOBAL_MMR_OFFSET)
105 * Physical mode addresses
107 #define GLOBAL_PHYS_MMR_SPACE (UNCACHED_PHYS | GLOBAL_MMR_OFFSET)
111 * Clear region & AS bits.
113 #define TO_PHYS_MASK (~(REGION_BITS | AS_MASK))
117 * Misc NASID manipulation.
119 #define NASID_SPACE(n) ((u64)(n) << NASID_SHIFT)
120 #define REMOTE_ADDR(n,a) (NASID_SPACE(n) | (a))
121 #define NODE_OFFSET(x) ((x) & (NODE_ADDRSPACE_SIZE - 1))
122 #define NODE_ADDRSPACE_SIZE (1UL << AS_SHIFT)
123 #define NASID_GET(x) (int) (((u64) (x) >> NASID_SHIFT) & NASID_BITMASK)
124 #define LOCAL_MMR_ADDR(a) (LOCAL_MMR_SPACE | (a))
125 #define GLOBAL_MMR_ADDR(n,a) (GLOBAL_MMR_SPACE | REMOTE_ADDR(n,a))
126 #define GLOBAL_MMR_PHYS_ADDR(n,a) (GLOBAL_PHYS_MMR_SPACE | REMOTE_ADDR(n,a))
127 #define GLOBAL_CAC_ADDR(n,a) (CAC_BASE | REMOTE_ADDR(n,a))
128 #define CHANGE_NASID(n,x) ((void *)(((u64)(x) & ~NASID_MASK) | NASID_SPACE(n)))
129 #define IS_TIO_NASID(n) ((n) & 1)
132 /* non-II mmr's start at top of big window space (4G) */
133 #define BWIN_TOP 0x0000000100000000UL
136 * general address defines
138 #define CAC_BASE (CACHED | AS_CAC_SPACE)
139 #define AMO_BASE (UNCACHED | AS_AMO_SPACE)
140 #define AMO_PHYS_BASE (UNCACHED_PHYS | AS_AMO_SPACE)
141 #define GET_BASE (CACHED | AS_GET_SPACE)
144 * Convert Memory addresses between various addressing modes.
146 #define TO_PHYS(x) (TO_PHYS_MASK & (x))
147 #define TO_CAC(x) (CAC_BASE | TO_PHYS(x))
148 #define TO_AMO(x) (AMO_BASE | TO_PHYS(x))
149 #define TO_GET(x) (GET_BASE | TO_PHYS(x))
153 * Covert from processor physical address to II/TIO physical address:
154 * II - squeeze out the AS bits
155 * TIO- requires a chiplet id in bits 38-39. For DMA to memory,
156 * the chiplet id is zero. If we implement TIO-TIO dma, we might need
157 * to insert a chiplet id into this macro. However, it is our belief
158 * right now that this chiplet id will be ICE, which is also zero.
160 #define SH1_TIO_PHYS_TO_DMA(x) \
161 ((((u64)(NASID_GET(x))) << 40) | NODE_OFFSET(x))
163 #define SH2_NETWORK_BANK_OFFSET(x) \
164 ((u64)(x) & ((1UL << (sn_hub_info->nasid_shift - 4)) -1))
166 #define SH2_NETWORK_BANK_SELECT(x) \
167 ((((u64)(x) & (0x3UL << (sn_hub_info->nasid_shift - 4))) \
168 >> (sn_hub_info->nasid_shift - 4)) << 36)
170 #define SH2_NETWORK_ADDRESS(x) \
171 (SH2_NETWORK_BANK_OFFSET(x) | SH2_NETWORK_BANK_SELECT(x))
173 #define SH2_TIO_PHYS_TO_DMA(x) \
174 (((u64)(NASID_GET(x)) << 40) | SH2_NETWORK_ADDRESS(x))
176 #define PHYS_TO_TIODMA(x) \
177 (is_shub1() ? SH1_TIO_PHYS_TO_DMA(x) : SH2_TIO_PHYS_TO_DMA(x))
179 #define PHYS_TO_DMA(x) \
180 ((((u64)(x) & NASID_MASK) >> 2) | NODE_OFFSET(x))
184 * Macros to test for address type.
186 #define IS_AMO_ADDRESS(x) (((u64)(x) & (REGION_BITS | AS_MASK)) == AMO_BASE)
187 #define IS_AMO_PHYS_ADDRESS(x) (((u64)(x) & (REGION_BITS | AS_MASK)) == AMO_PHYS_BASE)
191 * The following definitions pertain to the IO special address
192 * space. They define the location of the big and little windows
195 #define BWIN_SIZE_BITS 29 /* big window size: 512M */
196 #define TIO_BWIN_SIZE_BITS 30 /* big window size: 1G */
197 #define NODE_SWIN_BASE(n, w) ((w == 0) ? NODE_BWIN_BASE((n), SWIN0_BIGWIN) \
198 : RAW_NODE_SWIN_BASE(n, w))
199 #define TIO_SWIN_BASE(n, w) (TIO_IO_BASE(n) + \
200 ((u64) (w) << TIO_SWIN_SIZE_BITS))
201 #define NODE_IO_BASE(n) (GLOBAL_MMR_SPACE | NASID_SPACE(n))
202 #define TIO_IO_BASE(n) (UNCACHED | NASID_SPACE(n))
203 #define BWIN_SIZE (1UL << BWIN_SIZE_BITS)
204 #define NODE_BWIN_BASE0(n) (NODE_IO_BASE(n) + BWIN_SIZE)
205 #define NODE_BWIN_BASE(n, w) (NODE_BWIN_BASE0(n) + ((u64) (w) << BWIN_SIZE_BITS))
206 #define RAW_NODE_SWIN_BASE(n, w) (NODE_IO_BASE(n) + ((u64) (w) << SWIN_SIZE_BITS))
207 #define BWIN_WIDGET_MASK 0x7
208 #define BWIN_WINDOWNUM(x) (((x) >> BWIN_SIZE_BITS) & BWIN_WIDGET_MASK)
209 #define SH1_IS_BIG_WINDOW_ADDR(x) ((x) & BWIN_TOP)
211 #define TIO_BWIN_WINDOW_SELECT_MASK 0x7
212 #define TIO_BWIN_WINDOWNUM(x) (((x) >> TIO_BWIN_SIZE_BITS) & TIO_BWIN_WINDOW_SELECT_MASK)
214 #define TIO_HWIN_SHIFT_BITS 33
215 #define TIO_HWIN(x) (NODE_OFFSET(x) >> TIO_HWIN_SHIFT_BITS)
218 * The following definitions pertain to the IO special address
219 * space. They define the location of the big and little windows
223 #define SWIN_SIZE_BITS 24
224 #define SWIN_WIDGET_MASK 0xF
226 #define TIO_SWIN_SIZE_BITS 28
227 #define TIO_SWIN_SIZE (1UL << TIO_SWIN_SIZE_BITS)
228 #define TIO_SWIN_WIDGET_MASK 0x3
231 * Convert smallwindow address to xtalk address.
233 * 'addr' can be physical or virtual address, but will be converted
234 * to Xtalk address in the range 0 -> SWINZ_SIZEMASK
236 #define SWIN_WIDGETNUM(x) (((x) >> SWIN_SIZE_BITS) & SWIN_WIDGET_MASK)
237 #define TIO_SWIN_WIDGETNUM(x) (((x) >> TIO_SWIN_SIZE_BITS) & TIO_SWIN_WIDGET_MASK)
241 * The following macros produce the correct base virtual address for
242 * the hub registers. The REMOTE_HUB_* macro produce
243 * the address for the specified hub's registers. The intent is
244 * that the appropriate PI, MD, NI, or II register would be substituted
248 * When certain Hub chip workaround are defined, it's not sufficient
249 * to dereference the *_HUB_ADDR() macros. You should instead use
250 * HUB_L() and HUB_S() if you must deal with pointers to hub registers.
251 * Otherwise, the recommended approach is to use *_HUB_L() and *_HUB_S().
252 * They're always safe.
254 /* Shub1 TIO & MMR addressing macros */
255 #define SH1_TIO_IOSPACE_ADDR(n,x) \
258 #define SH1_REMOTE_BWIN_MMR(n,x) \
261 #define SH1_REMOTE_SWIN_MMR(n,x) \
262 (NODE_SWIN_BASE(n,1) + 0x800000UL + (x))
264 #define SH1_REMOTE_MMR(n,x) \
265 (SH1_IS_BIG_WINDOW_ADDR(x) ? SH1_REMOTE_BWIN_MMR(n,x) : \
266 SH1_REMOTE_SWIN_MMR(n,x))
268 /* Shub1 TIO & MMR addressing macros */
269 #define SH2_TIO_IOSPACE_ADDR(n,x) \
270 ((UNCACHED | REMOTE_ADDR(n,x) | 1UL << (NASID_SHIFT - 2)))
272 #define SH2_REMOTE_MMR(n,x) \
276 /* TIO & MMR addressing macros that work on both shub1 & shub2 */
277 #define TIO_IOSPACE_ADDR(n,x) \
278 ((u64 *)(is_shub1() ? SH1_TIO_IOSPACE_ADDR(n,x) : \
279 SH2_TIO_IOSPACE_ADDR(n,x)))
281 #define SH_REMOTE_MMR(n,x) \
282 (is_shub1() ? SH1_REMOTE_MMR(n,x) : SH2_REMOTE_MMR(n,x))
284 #define REMOTE_HUB_ADDR(n,x) \
285 (IS_TIO_NASID(n) ? ((volatile u64*)TIO_IOSPACE_ADDR(n,x)) : \
286 ((volatile u64*)SH_REMOTE_MMR(n,x)))
289 #define HUB_L(x) (*((volatile typeof(*x) *)x))
290 #define HUB_S(x,d) (*((volatile typeof(*x) *)x) = (d))
292 #define REMOTE_HUB_L(n, a) HUB_L(REMOTE_HUB_ADDR((n), (a)))
293 #define REMOTE_HUB_S(n, a, d) HUB_S(REMOTE_HUB_ADDR((n), (a)), (d))
296 #endif /* _ASM_IA64_SN_ADDRS_H */