2 * Definitions for the SGI MACE (Multimedia, Audio and Communications Engine)
4 * This file is subject to the terms and conditions of the GNU General Public
5 * License. See the file "COPYING" in the main directory of this archive
8 * Copyright (C) 2000 Harald Koerfgen
9 * Copyright (C) 2004 Ladislav Michl
12 #ifndef __ASM_MACE_H__
13 #define __ASM_MACE_H__
18 #define MACE_BASE 0x1f000000 /* physical */
21 #define BIT(x) (1UL << (x))
27 volatile unsigned int error_addr;
28 volatile unsigned int error;
29 #define MACEPCI_ERROR_MASTER_ABORT BIT(31)
30 #define MACEPCI_ERROR_TARGET_ABORT BIT(30)
31 #define MACEPCI_ERROR_DATA_PARITY_ERR BIT(29)
32 #define MACEPCI_ERROR_RETRY_ERR BIT(28)
33 #define MACEPCI_ERROR_ILLEGAL_CMD BIT(27)
34 #define MACEPCI_ERROR_SYSTEM_ERR BIT(26)
35 #define MACEPCI_ERROR_INTERRUPT_TEST BIT(25)
36 #define MACEPCI_ERROR_PARITY_ERR BIT(24)
37 #define MACEPCI_ERROR_OVERRUN BIT(23)
38 #define MACEPCI_ERROR_RSVD BIT(22)
39 #define MACEPCI_ERROR_MEMORY_ADDR BIT(21)
40 #define MACEPCI_ERROR_CONFIG_ADDR BIT(20)
41 #define MACEPCI_ERROR_MASTER_ABORT_ADDR_VALID BIT(19)
42 #define MACEPCI_ERROR_TARGET_ABORT_ADDR_VALID BIT(18)
43 #define MACEPCI_ERROR_DATA_PARITY_ADDR_VALID BIT(17)
44 #define MACEPCI_ERROR_RETRY_ADDR_VALID BIT(16)
45 #define MACEPCI_ERROR_SIG_TABORT BIT(4)
46 #define MACEPCI_ERROR_DEVSEL_MASK 0xc0
47 #define MACEPCI_ERROR_DEVSEL_FAST 0
48 #define MACEPCI_ERROR_DEVSEL_MED 0x40
49 #define MACEPCI_ERROR_DEVSEL_SLOW 0x80
50 #define MACEPCI_ERROR_FBB BIT(1)
51 #define MACEPCI_ERROR_66MHZ BIT(0)
52 volatile unsigned int control;
53 #define MACEPCI_CONTROL_INT(x) BIT(x)
54 #define MACEPCI_CONTROL_INT_MASK 0xff
55 #define MACEPCI_CONTROL_SERR_ENA BIT(8)
56 #define MACEPCI_CONTROL_ARB_N6 BIT(9)
57 #define MACEPCI_CONTROL_PARITY_ERR BIT(10)
58 #define MACEPCI_CONTROL_MRMRA_ENA BIT(11)
59 #define MACEPCI_CONTROL_ARB_N3 BIT(12)
60 #define MACEPCI_CONTROL_ARB_N4 BIT(13)
61 #define MACEPCI_CONTROL_ARB_N5 BIT(14)
62 #define MACEPCI_CONTROL_PARK_LIU BIT(15)
63 #define MACEPCI_CONTROL_INV_INT(x) BIT(16+x)
64 #define MACEPCI_CONTROL_INV_INT_MASK 0x00ff0000
65 #define MACEPCI_CONTROL_OVERRUN_INT BIT(24)
66 #define MACEPCI_CONTROL_PARITY_INT BIT(25)
67 #define MACEPCI_CONTROL_SERR_INT BIT(26)
68 #define MACEPCI_CONTROL_IT_INT BIT(27)
69 #define MACEPCI_CONTROL_RE_INT BIT(28)
70 #define MACEPCI_CONTROL_DPED_INT BIT(29)
71 #define MACEPCI_CONTROL_TAR_INT BIT(30)
72 #define MACEPCI_CONTROL_MAR_INT BIT(31)
73 volatile unsigned int rev;
74 unsigned int _pad[0xcf8/4 - 4];
75 volatile unsigned int config_addr;
77 volatile unsigned char b[4];
78 volatile unsigned short w[2];
79 volatile unsigned int l;
82 #define MACEPCI_LOW_MEMORY 0x1a000000
83 #define MACEPCI_LOW_IO 0x18000000
84 #define MACEPCI_SWAPPED_VIEW 0
85 #define MACEPCI_NATIVE_VIEW 0x40000000
86 #define MACEPCI_IO 0x80000000
87 #define MACEPCI_HI_MEMORY 0x280000000
88 #define MACEPCI_HI_IO 0x100000000
94 unsigned long xxx; /* later... */
100 struct mace_ethernet {
101 volatile unsigned long mac_ctrl;
102 volatile unsigned long int_stat;
103 volatile unsigned long dma_ctrl;
104 volatile unsigned long timer;
105 volatile unsigned long tx_int_al;
106 volatile unsigned long rx_int_al;
107 volatile unsigned long tx_info;
108 volatile unsigned long tx_info_al;
109 volatile unsigned long rx_buff;
110 volatile unsigned long rx_buff_al1;
111 volatile unsigned long rx_buff_al2;
112 volatile unsigned long diag;
113 volatile unsigned long phy_data;
114 volatile unsigned long phy_regs;
115 volatile unsigned long phy_trans_go;
116 volatile unsigned long backoff_seed;
117 /*===================================*/
118 volatile unsigned long imq_reserved[4];
119 volatile unsigned long mac_addr;
120 volatile unsigned long mac_addr2;
121 volatile unsigned long mcast_filter;
122 volatile unsigned long tx_ring_base;
123 /* Following are read-only registers for debugging */
124 volatile unsigned long tx_pkt1_hdr;
125 volatile unsigned long tx_pkt1_ptr[3];
126 volatile unsigned long tx_pkt2_hdr;
127 volatile unsigned long tx_pkt2_ptr[3];
128 /*===================================*/
129 volatile unsigned long rx_fifo;
136 /* Audio registers */
138 volatile unsigned long control;
139 volatile unsigned long codec_control; /* codec status control */
140 volatile unsigned long codec_mask; /* codec status input mask */
141 volatile unsigned long codec_read; /* codec status read data */
143 volatile unsigned long control; /* channel control */
144 volatile unsigned long read_ptr; /* channel read pointer */
145 volatile unsigned long write_ptr; /* channel write pointer */
146 volatile unsigned long depth; /* channel depth */
151 /* register definitions for parallel port DMA */
152 struct mace_parport {
153 /* 0 - do nothing, 1 - pulse terminal count to the device after buffer is drained */
154 #define MACEPAR_CONTEXT_LASTFLAG BIT(63)
155 /* Should not cross 4K page boundary */
156 #define MACEPAR_CONTEXT_DATALEN_MASK 0xfff00000000
157 /* Can be arbitrarily aligned on any byte boundary on output, 64 byte aligned on input */
158 #define MACEPAR_CONTEXT_BASEADDR_MASK 0xffffffff
159 volatile u64 context_a;
160 volatile u64 context_b;
161 #define MACEPAR_CTLSTAT_DIRECTION BIT(0) /* 0 - mem->device, 1 - device->mem */
162 #define MACEPAR_CTLSTAT_ENABLE BIT(1) /* 0 - channel frozen, 1 - channel enabled */
163 #define MACEPAR_CTLSTAT_RESET BIT(2) /* 0 - channel active, 1 - complete channel reset */
164 #define MACEPAR_CTLSTAT_CTXB_VALID BIT(3)
165 #define MACEPAR_CTLSTAT_CTXA_VALID BIT(4)
166 volatile u64 cntlstat; /* Control/Status register */
167 #define MACEPAR_DIAG_CTXINUSE BIT(1)
168 #define MACEPAR_DIAG_DMACTIVE BIT(2) /* 1 - Dma engine is enabled and processing something */
169 #define MACEPAR_DIAG_CTRMASK 0x3ffc /* Counter of bytes left */
170 volatile u64 diagnostic; /* RO: diagnostic register */
173 /* ISA Control and DMA registers */
174 struct mace_isactrl {
175 volatile unsigned long ringbase;
176 #define MACEISA_RINGBUFFERS_SIZE (8 * 4096)
178 volatile unsigned long misc;
179 #define MACEISA_FLASH_WE BIT(0) /* 1=> Enable FLASH writes */
180 #define MACEISA_PWD_CLEAR BIT(1) /* 1=> PWD CLEAR jumper detected */
181 #define MACEISA_NIC_DEASSERT BIT(2)
182 #define MACEISA_NIC_DATA BIT(3)
183 #define MACEISA_LED_RED BIT(4) /* 0=> Illuminate red LED */
184 #define MACEISA_LED_GREEN BIT(5) /* 0=> Illuminate green LED */
185 #define MACEISA_DP_RAM_ENABLE BIT(6)
187 volatile unsigned long istat;
188 volatile unsigned long imask;
189 #define MACEISA_AUDIO_SW_INT BIT(0)
190 #define MACEISA_AUDIO_SC_INT BIT(1)
191 #define MACEISA_AUDIO1_DMAT_INT BIT(2)
192 #define MACEISA_AUDIO1_OF_INT BIT(3)
193 #define MACEISA_AUDIO2_DMAT_INT BIT(4)
194 #define MACEISA_AUDIO2_MERR_INT BIT(5)
195 #define MACEISA_AUDIO3_DMAT_INT BIT(6)
196 #define MACEISA_AUDIO3_MERR_INT BIT(7)
197 #define MACEISA_RTC_INT BIT(8)
198 #define MACEISA_KEYB_INT BIT(9)
199 #define MACEISA_KEYB_POLL_INT BIT(10)
200 #define MACEISA_MOUSE_INT BIT(11)
201 #define MACEISA_MOUSE_POLL_INT BIT(12)
202 #define MACEISA_TIMER0_INT BIT(13)
203 #define MACEISA_TIMER1_INT BIT(14)
204 #define MACEISA_TIMER2_INT BIT(15)
205 #define MACEISA_PARALLEL_INT BIT(16)
206 #define MACEISA_PAR_CTXA_INT BIT(17)
207 #define MACEISA_PAR_CTXB_INT BIT(18)
208 #define MACEISA_PAR_MERR_INT BIT(19)
209 #define MACEISA_SERIAL1_INT BIT(20)
210 #define MACEISA_SERIAL1_TDMAT_INT BIT(21)
211 #define MACEISA_SERIAL1_TDMAPR_INT BIT(22)
212 #define MACEISA_SERIAL1_TDMAME_INT BIT(23)
213 #define MACEISA_SERIAL1_RDMAT_INT BIT(24)
214 #define MACEISA_SERIAL1_RDMAOR_INT BIT(25)
215 #define MACEISA_SERIAL2_INT BIT(26)
216 #define MACEISA_SERIAL2_TDMAT_INT BIT(27)
217 #define MACEISA_SERIAL2_TDMAPR_INT BIT(28)
218 #define MACEISA_SERIAL2_TDMAME_INT BIT(29)
219 #define MACEISA_SERIAL2_RDMAT_INT BIT(30)
220 #define MACEISA_SERIAL2_RDMAOR_INT BIT(31)
222 volatile unsigned long _pad[0x2000/8 - 4];
224 volatile unsigned long dp_ram[0x400];
225 struct mace_parport parport;
228 /* Keyboard & Mouse registers
229 * -> drivers/input/serio/maceps2.c */
230 struct mace_ps2port {
231 volatile unsigned long tx;
232 volatile unsigned long rx;
233 volatile unsigned long control;
234 volatile unsigned long status;
238 struct mace_ps2port keyb;
239 struct mace_ps2port mouse;
243 * -> drivers/i2c/algos/i2c-algo-sgi.c */
245 volatile unsigned long config;
246 #define MACEI2C_RESET BIT(0)
247 #define MACEI2C_FAST BIT(1)
248 #define MACEI2C_DATA_OVERRIDE BIT(2)
249 #define MACEI2C_CLOCK_OVERRIDE BIT(3)
250 #define MACEI2C_DATA_STATUS BIT(4)
251 #define MACEI2C_CLOCK_STATUS BIT(5)
252 volatile unsigned long control;
253 volatile unsigned long data;
256 /* Timer registers */
258 volatile unsigned long ust_msc;
260 volatile unsigned int ust;
261 volatile unsigned int msc;
266 volatile unsigned long ust;
267 #define MACE_UST_PERIOD_NS 960
269 volatile unsigned long compare1;
270 volatile unsigned long compare2;
271 volatile unsigned long compare3;
274 timer_reg audio_out1;
275 timer_reg audio_out2;
282 struct mace_audio audio;
283 char _pad0[0x10000 - sizeof(struct mace_audio)];
285 struct mace_isactrl ctrl;
286 char _pad1[0x10000 - sizeof(struct mace_isactrl)];
289 char _pad2[0x10000 - sizeof(struct mace_ps2)];
292 char _pad3[0x10000 - sizeof(struct mace_i2c)];
294 struct mace_timers timers;
295 char _pad4[0x10000 - sizeof(struct mace_timers)];
304 struct mace_parallel {
307 struct mace_ecp1284 { /* later... */
312 volatile unsigned long xxx; /* later... */
316 struct mace_parallel parallel;
317 char _pad1[0x8000 - sizeof(struct mace_parallel)];
319 struct mace_ecp1284 ecp1284;
320 char _pad2[0x8000 - sizeof(struct mace_ecp1284)];
322 struct mace_serial serial1;
323 char _pad3[0x8000 - sizeof(struct mace_serial)];
325 struct mace_serial serial2;
326 char _pad4[0x8000 - sizeof(struct mace_serial)];
328 volatile unsigned char rtc[0x10000];
332 char _reserved[0x80000];
335 char _pad0[0x80000 - sizeof(struct mace_pci)];
337 struct mace_video video_in1;
338 char _pad1[0x80000 - sizeof(struct mace_video)];
340 struct mace_video video_in2;
341 char _pad2[0x80000 - sizeof(struct mace_video)];
343 struct mace_video video_out;
344 char _pad3[0x80000 - sizeof(struct mace_video)];
346 struct mace_ethernet eth;
347 char _pad4[0x80000 - sizeof(struct mace_ethernet)];
349 struct mace_perif perif;
350 char _pad5[0x80000 - sizeof(struct mace_perif)];
353 char _pad6[0x80000 - sizeof(struct mace_isa)];
356 extern struct sgi_mace *mace;
358 #endif /* __ASM_MACE_H__ */