include/asm-mips/mipsregs.h

   1 /*
   2  * This file is subject to the terms and conditions of the GNU General Public
   3  * License.  See the file "COPYING" in the main directory of this archive
   4  * for more details.
   5  *
   6  * Copyright (C) 1994, 1995, 1996, 1997, 2000, 2001 by Ralf Baechle
   7  * Copyright (C) 2000 Silicon Graphics, Inc.
   8  * Modified for further R[236]000 support by Paul M. Antoine, 1996.
   9  * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
  10  * Copyright (C) 2000 MIPS Technologies, Inc.  All rights reserved.
  11  * Copyright (C) 2003, 2004  Maciej W. Rozycki
  12  */
  13 #ifndef _ASM_MIPSREGS_H
  14 #define _ASM_MIPSREGS_H
  15
  16 #include <linux/config.h>
  17 #include <linux/linkage.h>
  18 #include <asm/hazards.h>
  19
  20 /*
  21  * The following macros are especially useful for __asm__
  22  * inline assembler.
  23  */
  24 #ifndef __STR
  25 #define __STR(x) #x
  26 #endif
  27 #ifndef STR
  28 #define STR(x) __STR(x)
  29 #endif
  30
  31 /*
  32  *  Configure language
  33  */
  34 #ifdef __ASSEMBLY__
  35 #define _ULCAST_
  36 #else
  37 #define _ULCAST_ (unsigned long)
  38 #endif
  39
  40 #include <asm/mipsmtregs.h>
  41
  42 /*
  43  * Coprocessor 0 register names
  44  */
  45 #define CP0_INDEX $0
  46 #define CP0_RANDOM $1
  47 #define CP0_ENTRYLO0 $2
  48 #define CP0_ENTRYLO1 $3
  49 #define CP0_CONF $3
  50 #define CP0_CONTEXT $4
  51 #define CP0_PAGEMASK $5
  52 #define CP0_WIRED $6
  53 #define CP0_INFO $7
  54 #define CP0_BADVADDR $8
  55 #define CP0_COUNT $9
  56 #define CP0_ENTRYHI $10
  57 #define CP0_COMPARE $11
  58 #define CP0_STATUS $12
  59 #define CP0_CAUSE $13
  60 #define CP0_EPC $14
  61 #define CP0_PRID $15
  62 #define CP0_CONFIG $16
  63 #define CP0_LLADDR $17
  64 #define CP0_WATCHLO $18
  65 #define CP0_WATCHHI $19
  66 #define CP0_XCONTEXT $20
  67 #define CP0_FRAMEMASK $21
  68 #define CP0_DIAGNOSTIC $22
  69 #define CP0_DEBUG $23
  70 #define CP0_DEPC $24
  71 #define CP0_PERFORMANCE $25
  72 #define CP0_ECC $26
  73 #define CP0_CACHEERR $27
  74 #define CP0_TAGLO $28
  75 #define CP0_TAGHI $29
  76 #define CP0_ERROREPC $30
  77 #define CP0_DESAVE $31
  78
  79 /*
  80  * R4640/R4650 cp0 register names.  These registers are listed
  81  * here only for completeness; without MMU these CPUs are not useable
  82  * by Linux.  A future ELKS port might take make Linux run on them
  83  * though ...
  84  */
  85 #define CP0_IBASE $0
  86 #define CP0_IBOUND $1
  87 #define CP0_DBASE $2
  88 #define CP0_DBOUND $3
  89 #define CP0_CALG $17
  90 #define CP0_IWATCH $18
  91 #define CP0_DWATCH $19
  92
  93 /*
  94  * Coprocessor 0 Set 1 register names
  95  */
  96 #define CP0_S1_DERRADDR0  $26
  97 #define CP0_S1_DERRADDR1  $27
  98 #define CP0_S1_INTCONTROL $20
  99
 100 /*
 101  * Coprocessor 0 Set 2 register names
 102  */
 103 #define CP0_S2_SRSCTL     $12   /* MIPSR2 */
 104
 105 /*
 106  * Coprocessor 0 Set 3 register names
 107  */
 108 #define CP0_S3_SRSMAP     $12   /* MIPSR2 */
 109
 110 /*
 111  *  TX39 Series
 112  */
 113 #define CP0_TX39_CACHE  $7
 114
 115 /*
 116  * Coprocessor 1 (FPU) register names
 117  */
 118 #define CP1_REVISION   $0
 119 #define CP1_STATUS     $31
 120
 121 /*
 122  * FPU Status Register Values
 123  */
 124 /*
 125  * Status Register Values
 126  */
 127
 128 #define FPU_CSR_FLUSH   0x01000000      /* flush denormalised results to 0 */
 129 #define FPU_CSR_COND    0x00800000      /* $fcc0 */
 130 #define FPU_CSR_COND0   0x00800000      /* $fcc0 */
 131 #define FPU_CSR_COND1   0x02000000      /* $fcc1 */
 132 #define FPU_CSR_COND2   0x04000000      /* $fcc2 */
 133 #define FPU_CSR_COND3   0x08000000      /* $fcc3 */
 134 #define FPU_CSR_COND4   0x10000000      /* $fcc4 */
 135 #define FPU_CSR_COND5   0x20000000      /* $fcc5 */
 136 #define FPU_CSR_COND6   0x40000000      /* $fcc6 */
 137 #define FPU_CSR_COND7   0x80000000      /* $fcc7 */
 138
 139 /*
 140  * X the exception cause indicator
 141  * E the exception enable
 142  * S the sticky/flag bit
 143 */
 144 #define FPU_CSR_ALL_X   0x0003f000
 145 #define FPU_CSR_UNI_X   0x00020000
 146 #define FPU_CSR_INV_X   0x00010000
 147 #define FPU_CSR_DIV_X   0x00008000
 148 #define FPU_CSR_OVF_X   0x00004000
 149 #define FPU_CSR_UDF_X   0x00002000
 150 #define FPU_CSR_INE_X   0x00001000
 151
 152 #define FPU_CSR_ALL_E   0x00000f80
 153 #define FPU_CSR_INV_E   0x00000800
 154 #define FPU_CSR_DIV_E   0x00000400
 155 #define FPU_CSR_OVF_E   0x00000200
 156 #define FPU_CSR_UDF_E   0x00000100
 157 #define FPU_CSR_INE_E   0x00000080
 158
 159 #define FPU_CSR_ALL_S   0x0000007c
 160 #define FPU_CSR_INV_S   0x00000040
 161 #define FPU_CSR_DIV_S   0x00000020
 162 #define FPU_CSR_OVF_S   0x00000010
 163 #define FPU_CSR_UDF_S   0x00000008
 164 #define FPU_CSR_INE_S   0x00000004
 165
 166 /* rounding mode */
 167 #define FPU_CSR_RN      0x0     /* nearest */
 168 #define FPU_CSR_RZ      0x1     /* towards zero */
 169 #define FPU_CSR_RU      0x2     /* towards +Infinity */
 170 #define FPU_CSR_RD      0x3     /* towards -Infinity */
 171
 172
 173 /*
 174  * Values for PageMask register
 175  */
 176 #ifdef CONFIG_CPU_VR41XX
 177
 178 /* Why doesn't stupidity hurt ... */
 179
 180 #define PM_1K           0x00000000
 181 #define PM_4K           0x00001800
 182 #define PM_16K          0x00007800
 183 #define PM_64K          0x0001f800
 184 #define PM_256K         0x0007f800
 185
 186 #else
 187
 188 #define PM_4K           0x00000000
 189 #define PM_16K          0x00006000
 190 #define PM_64K          0x0001e000
 191 #define PM_256K         0x0007e000
 192 #define PM_1M           0x001fe000
 193 #define PM_4M           0x007fe000
 194 #define PM_16M          0x01ffe000
 195 #define PM_64M          0x07ffe000
 196 #define PM_256M         0x1fffe000
 197
 198 #endif
 199
 200 /*
 201  * Default page size for a given kernel configuration
 202  */
 203 #ifdef CONFIG_PAGE_SIZE_4KB
 204 #define PM_DEFAULT_MASK PM_4K
 205 #elif defined(CONFIG_PAGE_SIZE_16KB)
 206 #define PM_DEFAULT_MASK PM_16K
 207 #elif defined(CONFIG_PAGE_SIZE_64KB)
 208 #define PM_DEFAULT_MASK PM_64K
 209 #else
 210 #error Bad page size configuration!
 211 #endif
 212
 213
 214 /*
 215  * Values used for computation of new tlb entries
 216  */
 217 #define PL_4K           12
 218 #define PL_16K          14
 219 #define PL_64K          16
 220 #define PL_256K         18
 221 #define PL_1M           20
 222 #define PL_4M           22
 223 #define PL_16M          24
 224 #define PL_64M          26
 225 #define PL_256M         28
 226
 227 /*
 228  * R4x00 interrupt enable / cause bits
 229  */
 230 #define IE_SW0          (_ULCAST_(1) <<  8)
 231 #define IE_SW1          (_ULCAST_(1) <<  9)
 232 #define IE_IRQ0         (_ULCAST_(1) << 10)
 233 #define IE_IRQ1         (_ULCAST_(1) << 11)
 234 #define IE_IRQ2         (_ULCAST_(1) << 12)
 235 #define IE_IRQ3         (_ULCAST_(1) << 13)
 236 #define IE_IRQ4         (_ULCAST_(1) << 14)
 237 #define IE_IRQ5         (_ULCAST_(1) << 15)
 238
 239 /*
 240  * R4x00 interrupt cause bits
 241  */
 242 #define C_SW0           (_ULCAST_(1) <<  8)
 243 #define C_SW1           (_ULCAST_(1) <<  9)
 244 #define C_IRQ0          (_ULCAST_(1) << 10)
 245 #define C_IRQ1          (_ULCAST_(1) << 11)
 246 #define C_IRQ2          (_ULCAST_(1) << 12)
 247 #define C_IRQ3          (_ULCAST_(1) << 13)
 248 #define C_IRQ4          (_ULCAST_(1) << 14)
 249 #define C_IRQ5          (_ULCAST_(1) << 15)
 250
 251 /*
 252  * Bitfields in the R4xx0 cp0 status register
 253  */
 254 #define ST0_IE                  0x00000001
 255 #define ST0_EXL                 0x00000002
 256 #define ST0_ERL                 0x00000004
 257 #define ST0_KSU                 0x00000018
 258 #  define KSU_USER              0x00000010
 259 #  define KSU_SUPERVISOR        0x00000008
 260 #  define KSU_KERNEL            0x00000000
 261 #define ST0_UX                  0x00000020
 262 #define ST0_SX                  0x00000040
 263 #define ST0_KX                  0x00000080
 264 #define ST0_DE                  0x00010000
 265 #define ST0_CE                  0x00020000
 266
 267 /*
 268  * Setting c0_status.co enables Hit_Writeback and Hit_Writeback_Invalidate
 269  * cacheops in userspace.  This bit exists only on RM7000 and RM9000
 270  * processors.
 271  */
 272 #define ST0_CO                  0x08000000
 273
 274 /*
 275  * Bitfields in the R[23]000 cp0 status register.
 276  */
 277 #define ST0_IEC                 0x00000001
 278 #define ST0_KUC                 0x00000002
 279 #define ST0_IEP                 0x00000004
 280 #define ST0_KUP                 0x00000008
 281 #define ST0_IEO                 0x00000010
 282 #define ST0_KUO                 0x00000020
 283 /* bits 6 & 7 are reserved on R[23]000 */
 284 #define ST0_ISC                 0x00010000
 285 #define ST0_SWC                 0x00020000
 286 #define ST0_CM                  0x00080000
 287
 288 /*
 289  * Bits specific to the R4640/R4650
 290  */
 291 #define ST0_UM                  (_ULCAST_(1) <<  4)
 292 #define ST0_IL                  (_ULCAST_(1) << 23)
 293 #define ST0_DL                  (_ULCAST_(1) << 24)
 294
 295 /*
 296  * Enable the MIPS DSP ASE
 297  */
 298 #define ST0_MX                  0x01000000
 299
 300 /*
 301  * Bitfields in the TX39 family CP0 Configuration Register 3
 302  */
 303 #define TX39_CONF_ICS_SHIFT     19
 304 #define TX39_CONF_ICS_MASK      0x00380000
 305 #define TX39_CONF_ICS_1KB       0x00000000
 306 #define TX39_CONF_ICS_2KB       0x00080000
 307 #define TX39_CONF_ICS_4KB       0x00100000
 308 #define TX39_CONF_ICS_8KB       0x00180000
 309 #define TX39_CONF_ICS_16KB      0x00200000
 310
 311 #define TX39_CONF_DCS_SHIFT     16
 312 #define TX39_CONF_DCS_MASK      0x00070000
 313 #define TX39_CONF_DCS_1KB       0x00000000
 314 #define TX39_CONF_DCS_2KB       0x00010000
 315 #define TX39_CONF_DCS_4KB       0x00020000
 316 #define TX39_CONF_DCS_8KB       0x00030000
 317 #define TX39_CONF_DCS_16KB      0x00040000
 318
 319 #define TX39_CONF_CWFON         0x00004000
 320 #define TX39_CONF_WBON          0x00002000
 321 #define TX39_CONF_RF_SHIFT      10
 322 #define TX39_CONF_RF_MASK       0x00000c00
 323 #define TX39_CONF_DOZE          0x00000200
 324 #define TX39_CONF_HALT          0x00000100
 325 #define TX39_CONF_LOCK          0x00000080
 326 #define TX39_CONF_ICE           0x00000020
 327 #define TX39_CONF_DCE           0x00000010
 328 #define TX39_CONF_IRSIZE_SHIFT  2
 329 #define TX39_CONF_IRSIZE_MASK   0x0000000c
 330 #define TX39_CONF_DRSIZE_SHIFT  0
 331 #define TX39_CONF_DRSIZE_MASK   0x00000003
 332
 333 /*
 334  * Status register bits available in all MIPS CPUs.
 335  */
 336 #define ST0_IM                  0x0000ff00
 337 #define  STATUSB_IP0            8
 338 #define  STATUSF_IP0            (_ULCAST_(1) <<  8)
 339 #define  STATUSB_IP1            9
 340 #define  STATUSF_IP1            (_ULCAST_(1) <<  9)
 341 #define  STATUSB_IP2            10
 342 #define  STATUSF_IP2            (_ULCAST_(1) << 10)
 343 #define  STATUSB_IP3            11
 344 #define  STATUSF_IP3            (_ULCAST_(1) << 11)
 345 #define  STATUSB_IP4            12
 346 #define  STATUSF_IP4            (_ULCAST_(1) << 12)
 347 #define  STATUSB_IP5            13
 348 #define  STATUSF_IP5            (_ULCAST_(1) << 13)
 349 #define  STATUSB_IP6            14
 350 #define  STATUSF_IP6            (_ULCAST_(1) << 14)
 351 #define  STATUSB_IP7            15
 352 #define  STATUSF_IP7            (_ULCAST_(1) << 15)
 353 #define  STATUSB_IP8            0
 354 #define  STATUSF_IP8            (_ULCAST_(1) <<  0)
 355 #define  STATUSB_IP9            1
 356 #define  STATUSF_IP9            (_ULCAST_(1) <<  1)
 357 #define  STATUSB_IP10           2
 358 #define  STATUSF_IP10           (_ULCAST_(1) <<  2)
 359 #define  STATUSB_IP11           3
 360 #define  STATUSF_IP11           (_ULCAST_(1) <<  3)
 361 #define  STATUSB_IP12           4
 362 #define  STATUSF_IP12           (_ULCAST_(1) <<  4)
 363 #define  STATUSB_IP13           5
 364 #define  STATUSF_IP13           (_ULCAST_(1) <<  5)
 365 #define  STATUSB_IP14           6
 366 #define  STATUSF_IP14           (_ULCAST_(1) <<  6)
 367 #define  STATUSB_IP15           7
 368 #define  STATUSF_IP15           (_ULCAST_(1) <<  7)
 369 #define ST0_CH                  0x00040000
 370 #define ST0_SR                  0x00100000
 371 #define ST0_TS                  0x00200000
 372 #define ST0_BEV                 0x00400000
 373 #define ST0_RE                  0x02000000
 374 #define ST0_FR                  0x04000000
 375 #define ST0_CU                  0xf0000000
 376 #define ST0_CU0                 0x10000000
 377 #define ST0_CU1                 0x20000000
 378 #define ST0_CU2                 0x40000000
 379 #define ST0_CU3                 0x80000000
 380 #define ST0_XX                  0x80000000      /* MIPS IV naming */
 381
 382 /*
 383  * Bitfields and bit numbers in the coprocessor 0 cause register.
 384  *
 385  * Refer to your MIPS R4xx0 manual, chapter 5 for explanation.
 386  */
 387 #define  CAUSEB_EXCCODE         2
 388 #define  CAUSEF_EXCCODE         (_ULCAST_(31)  <<  2)
 389 #define  CAUSEB_IP              8
 390 #define  CAUSEF_IP              (_ULCAST_(255) <<  8)
 391 #define  CAUSEB_IP0             8
 392 #define  CAUSEF_IP0             (_ULCAST_(1)   <<  8)
 393 #define  CAUSEB_IP1             9
 394 #define  CAUSEF_IP1             (_ULCAST_(1)   <<  9)
 395 #define  CAUSEB_IP2             10
 396 #define  CAUSEF_IP2             (_ULCAST_(1)   << 10)
 397 #define  CAUSEB_IP3             11
 398 #define  CAUSEF_IP3             (_ULCAST_(1)   << 11)
 399 #define  CAUSEB_IP4             12
 400 #define  CAUSEF_IP4             (_ULCAST_(1)   << 12)
 401 #define  CAUSEB_IP5             13
 402 #define  CAUSEF_IP5             (_ULCAST_(1)   << 13)
 403 #define  CAUSEB_IP6             14
 404 #define  CAUSEF_IP6             (_ULCAST_(1)   << 14)
 405 #define  CAUSEB_IP7             15
 406 #define  CAUSEF_IP7             (_ULCAST_(1)   << 15)
 407 #define  CAUSEB_IV              23
 408 #define  CAUSEF_IV              (_ULCAST_(1)   << 23)
 409 #define  CAUSEB_CE              28
 410 #define  CAUSEF_CE              (_ULCAST_(3)   << 28)
 411 #define  CAUSEB_BD              31
 412 #define  CAUSEF_BD              (_ULCAST_(1)   << 31)
 413
 414 /*
 415  * Bits in the coprocessor 0 config register.
 416  */
 417 /* Generic bits.  */
 418 #define CONF_CM_CACHABLE_NO_WA          0
 419 #define CONF_CM_CACHABLE_WA             1
 420 #define CONF_CM_UNCACHED                2
 421 #define CONF_CM_CACHABLE_NONCOHERENT    3
 422 #define CONF_CM_CACHABLE_CE             4
 423 #define CONF_CM_CACHABLE_COW            5
 424 #define CONF_CM_CACHABLE_CUW            6
 425 #define CONF_CM_CACHABLE_ACCELERATED    7
 426 #define CONF_CM_CMASK                   7
 427 #define CONF_BE                 (_ULCAST_(1) << 15)
 428
 429 /* Bits common to various processors.  */
 430 #define CONF_CU                 (_ULCAST_(1) <<  3)
 431 #define CONF_DB                 (_ULCAST_(1) <<  4)
 432 #define CONF_IB                 (_ULCAST_(1) <<  5)
 433 #define CONF_DC                 (_ULCAST_(7) <<  6)
 434 #define CONF_IC                 (_ULCAST_(7) <<  9)
 435 #define CONF_EB                 (_ULCAST_(1) << 13)
 436 #define CONF_EM                 (_ULCAST_(1) << 14)
 437 #define CONF_SM                 (_ULCAST_(1) << 16)
 438 #define CONF_SC                 (_ULCAST_(1) << 17)
 439 #define CONF_EW                 (_ULCAST_(3) << 18)
 440 #define CONF_EP                 (_ULCAST_(15)<< 24)
 441 #define CONF_EC                 (_ULCAST_(7) << 28)
 442 #define CONF_CM                 (_ULCAST_(1) << 31)
 443
 444 /* Bits specific to the R4xx0.  */
 445 #define R4K_CONF_SW             (_ULCAST_(1) << 20)
 446 #define R4K_CONF_SS             (_ULCAST_(1) << 21)
 447 #define R4K_CONF_SB             (_ULCAST_(3) << 22)
 448
 449 /* Bits specific to the R5000.  */
 450 #define R5K_CONF_SE             (_ULCAST_(1) << 12)
 451 #define R5K_CONF_SS             (_ULCAST_(3) << 20)
 452
 453 /* Bits specific to the RM7000.  */
 454 #define RM7K_CONF_SE            (_ULCAST_(1) <<  3)
 455 #define RM7K_CONF_TE            (_ULCAST_(1) << 12)
 456 #define RM7K_CONF_CLK           (_ULCAST_(1) << 16)
 457 #define RM7K_CONF_TC            (_ULCAST_(1) << 17)
 458 #define RM7K_CONF_SI            (_ULCAST_(3) << 20)
 459 #define RM7K_CONF_SC            (_ULCAST_(1) << 31)
 460
 461 /* Bits specific to the R10000.  */
 462 #define R10K_CONF_DN            (_ULCAST_(3) <<  3)
 463 #define R10K_CONF_CT            (_ULCAST_(1) <<  5)
 464 #define R10K_CONF_PE            (_ULCAST_(1) <<  6)
 465 #define R10K_CONF_PM            (_ULCAST_(3) <<  7)
 466 #define R10K_CONF_EC            (_ULCAST_(15)<<  9)
 467 #define R10K_CONF_SB            (_ULCAST_(1) << 13)
 468 #define R10K_CONF_SK            (_ULCAST_(1) << 14)
 469 #define R10K_CONF_SS            (_ULCAST_(7) << 16)
 470 #define R10K_CONF_SC            (_ULCAST_(7) << 19)
 471 #define R10K_CONF_DC            (_ULCAST_(7) << 26)
 472 #define R10K_CONF_IC            (_ULCAST_(7) << 29)
 473
 474 /* Bits specific to the VR41xx.  */
 475 #define VR41_CONF_CS            (_ULCAST_(1) << 12)
 476 #define VR41_CONF_M16           (_ULCAST_(1) << 20)
 477 #define VR41_CONF_AD            (_ULCAST_(1) << 23)
 478
 479 /* Bits specific to the R30xx.  */
 480 #define R30XX_CONF_FDM          (_ULCAST_(1) << 19)
 481 #define R30XX_CONF_REV          (_ULCAST_(1) << 22)
 482 #define R30XX_CONF_AC           (_ULCAST_(1) << 23)
 483 #define R30XX_CONF_RF           (_ULCAST_(1) << 24)
 484 #define R30XX_CONF_HALT         (_ULCAST_(1) << 25)
 485 #define R30XX_CONF_FPINT        (_ULCAST_(7) << 26)
 486 #define R30XX_CONF_DBR          (_ULCAST_(1) << 29)
 487 #define R30XX_CONF_SB           (_ULCAST_(1) << 30)
 488 #define R30XX_CONF_LOCK         (_ULCAST_(1) << 31)
 489
 490 /* Bits specific to the TX49.  */
 491 #define TX49_CONF_DC            (_ULCAST_(1) << 16)
 492 #define TX49_CONF_IC            (_ULCAST_(1) << 17)  /* conflict with CONF_SC */
 493 #define TX49_CONF_HALT          (_ULCAST_(1) << 18)
 494 #define TX49_CONF_CWFON         (_ULCAST_(1) << 27)
 495
 496 /* Bits specific to the MIPS32/64 PRA.  */
 497 #define MIPS_CONF_MT            (_ULCAST_(7) <<  7)
 498 #define MIPS_CONF_AR            (_ULCAST_(7) << 10)
 499 #define MIPS_CONF_AT            (_ULCAST_(3) << 13)
 500 #define MIPS_CONF_M             (_ULCAST_(1) << 31)
 501
 502 /*
 503  * Bits in the MIPS32/64 PRA coprocessor 0 config registers 1 and above.
 504  */
 505 #define MIPS_CONF1_FP           (_ULCAST_(1) <<  0)
 506 #define MIPS_CONF1_EP           (_ULCAST_(1) <<  1)
 507 #define MIPS_CONF1_CA           (_ULCAST_(1) <<  2)
 508 #define MIPS_CONF1_WR           (_ULCAST_(1) <<  3)
 509 #define MIPS_CONF1_PC           (_ULCAST_(1) <<  4)
 510 #define MIPS_CONF1_MD           (_ULCAST_(1) <<  5)
 511 #define MIPS_CONF1_C2           (_ULCAST_(1) <<  6)
 512 #define MIPS_CONF1_DA           (_ULCAST_(7) <<  7)
 513 #define MIPS_CONF1_DL           (_ULCAST_(7) << 10)
 514 #define MIPS_CONF1_DS           (_ULCAST_(7) << 13)
 515 #define MIPS_CONF1_IA           (_ULCAST_(7) << 16)
 516 #define MIPS_CONF1_IL           (_ULCAST_(7) << 19)
 517 #define MIPS_CONF1_IS           (_ULCAST_(7) << 22)
 518 #define MIPS_CONF1_TLBS         (_ULCAST_(63)<< 25)
 519
 520 #define MIPS_CONF2_SA           (_ULCAST_(15)<<  0)
 521 #define MIPS_CONF2_SL           (_ULCAST_(15)<<  4)
 522 #define MIPS_CONF2_SS           (_ULCAST_(15)<<  8)
 523 #define MIPS_CONF2_SU           (_ULCAST_(15)<< 12)
 524 #define MIPS_CONF2_TA           (_ULCAST_(15)<< 16)
 525 #define MIPS_CONF2_TL           (_ULCAST_(15)<< 20)
 526 #define MIPS_CONF2_TS           (_ULCAST_(15)<< 24)
 527 #define MIPS_CONF2_TU           (_ULCAST_(7) << 28)
 528
 529 #define MIPS_CONF3_TL           (_ULCAST_(1) <<  0)
 530 #define MIPS_CONF3_SM           (_ULCAST_(1) <<  1)
 531 #define MIPS_CONF3_SP           (_ULCAST_(1) <<  4)
 532 #define MIPS_CONF3_VINT         (_ULCAST_(1) <<  5)
 533 #define MIPS_CONF3_VEIC         (_ULCAST_(1) <<  6)
 534 #define MIPS_CONF3_LPA          (_ULCAST_(1) <<  7)
 535 #define MIPS_CONF3_DSP          (_ULCAST_(1) << 10)
 536
 537 /*
 538  * Bits in the MIPS32/64 coprocessor 1 (FPU) revision register.
 539  */
 540 #define MIPS_FPIR_S             (_ULCAST_(1) << 16)
 541 #define MIPS_FPIR_D             (_ULCAST_(1) << 17)
 542 #define MIPS_FPIR_PS            (_ULCAST_(1) << 18)
 543 #define MIPS_FPIR_3D            (_ULCAST_(1) << 19)
 544 #define MIPS_FPIR_W             (_ULCAST_(1) << 20)
 545 #define MIPS_FPIR_L             (_ULCAST_(1) << 21)
 546 #define MIPS_FPIR_F64           (_ULCAST_(1) << 22)
 547
 548 /*
 549  * R10000 performance counter definitions.
 550  *
 551  * FIXME: The R10000 performance counter opens a nice way to implement CPU
 552  *        time accounting with a precission of one cycle.  I don't have
 553  *        R10000 silicon but just a manual, so ...
 554  */
 555
 556 /*
 557  * Events counted by counter #0
 558  */
 559 #define CE0_CYCLES                      0
 560 #define CE0_INSN_ISSUED                 1
 561 #define CE0_LPSC_ISSUED                 2
 562 #define CE0_S_ISSUED                    3
 563 #define CE0_SC_ISSUED                   4
 564 #define CE0_SC_FAILED                   5
 565 #define CE0_BRANCH_DECODED              6
 566 #define CE0_QW_WB_SECONDARY             7
 567 #define CE0_CORRECTED_ECC_ERRORS        8
 568 #define CE0_ICACHE_MISSES               9
 569 #define CE0_SCACHE_I_MISSES             10
 570 #define CE0_SCACHE_I_WAY_MISSPREDICTED  11
 571 #define CE0_EXT_INTERVENTIONS_REQ       12
 572 #define CE0_EXT_INVALIDATE_REQ          13
 573 #define CE0_VIRTUAL_COHERENCY_COND      14
 574 #define CE0_INSN_GRADUATED              15
 575
 576 /*
 577  * Events counted by counter #1
 578  */
 579 #define CE1_CYCLES                      0
 580 #define CE1_INSN_GRADUATED              1
 581 #define CE1_LPSC_GRADUATED              2
 582 #define CE1_S_GRADUATED                 3
 583 #define CE1_SC_GRADUATED                4
 584 #define CE1_FP_INSN_GRADUATED           5
 585 #define CE1_QW_WB_PRIMARY               6
 586 #define CE1_TLB_REFILL                  7
 587 #define CE1_BRANCH_MISSPREDICTED        8
 588 #define CE1_DCACHE_MISS                 9
 589 #define CE1_SCACHE_D_MISSES             10
 590 #define CE1_SCACHE_D_WAY_MISSPREDICTED  11
 591 #define CE1_EXT_INTERVENTION_HITS       12
 592 #define CE1_EXT_INVALIDATE_REQ          13
 593 #define CE1_SP_HINT_TO_CEXCL_SC_BLOCKS  14
 594 #define CE1_SP_HINT_TO_SHARED_SC_BLOCKS 15
 595
 596 /*
 597  * These flags define in which privilege mode the counters count events
 598  */
 599 #define CEB_USER        8       /* Count events in user mode, EXL = ERL = 0 */
 600 #define CEB_SUPERVISOR  4       /* Count events in supvervisor mode EXL = ERL = 0 */
 601 #define CEB_KERNEL      2       /* Count events in kernel mode EXL = ERL = 0 */
 602 #define CEB_EXL         1       /* Count events with EXL = 1, ERL = 0 */
 603
 604 #ifndef __ASSEMBLY__
 605
 606 /*
 607  * Functions to access the R10000 performance counters.  These are basically
 608  * mfc0 and mtc0 instructions from and to coprocessor register with a 5-bit
 609  * performance counter number encoded into bits 1 ... 5 of the instruction.
 610  * Only performance counters 0 to 1 actually exist, so for a non-R10000 aware
 611  * disassembler these will look like an access to sel 0 or 1.
 612  */
 613 #define read_r10k_perf_cntr(counter)                            \
 614 ({                                                              \
 615         unsigned int __res;                                     \
 616         __asm__ __volatile__(                                   \
 617         "mfpc\t%0, %1"                                          \
 618         : "=r" (__res)                                          \
 619         : "i" (counter));                                       \
 620                                                                 \
 621         __res;                                                  \
 622 })
 623
 624 #define write_r10k_perf_cntr(counter,val)                       \
 625 do {                                                            \
 626         __asm__ __volatile__(                                   \
 627         "mtpc\t%0, %1"                                          \
 628         :                                                       \
 629         : "r" (val), "i" (counter));                            \
 630 } while (0)
 631
 632 #define read_r10k_perf_event(counter)                           \
 633 ({                                                              \
 634         unsigned int __res;                                     \
 635         __asm__ __volatile__(                                   \
 636         "mfps\t%0, %1"                                          \
 637         : "=r" (__res)                                          \
 638         : "i" (counter));                                       \
 639                                                                 \
 640         __res;                                                  \
 641 })
 642
 643 #define write_r10k_perf_cntl(counter,val)                       \
 644 do {                                                            \
 645         __asm__ __volatile__(                                   \
 646         "mtps\t%0, %1"                                          \
 647         :                                                       \
 648         : "r" (val), "i" (counter));                            \
 649 } while (0)
 650
 651
 652 /*
 653  * Macros to access the system control coprocessor
 654  */
 655
 656 #define __read_32bit_c0_register(source, sel)                           \
 657 ({ int __res;                                                           \
 658         if (sel == 0)                                                   \
 659                 __asm__ __volatile__(                                   \
 660                         "mfc0\t%0, " #source "\n\t"                     \
 661                         : "=r" (__res));                                \
 662         else                                                            \
 663                 __asm__ __volatile__(                                   \
 664                         ".set\tmips32\n\t"                              \
 665                         "mfc0\t%0, " #source ", " #sel "\n\t"           \
 666                         ".set\tmips0\n\t"                               \
 667                         : "=r" (__res));                                \
 668         __res;                                                          \
 669 })
 670
 671 #define __read_64bit_c0_register(source, sel)                           \
 672 ({ unsigned long long __res;                                            \
 673         if (sizeof(unsigned long) == 4)                                 \
 674                 __res = __read_64bit_c0_split(source, sel);             \
 675         else if (sel == 0)                                              \
 676                 __asm__ __volatile__(                                   \
 677                         ".set\tmips3\n\t"                               \
 678                         "dmfc0\t%0, " #source "\n\t"                    \
 679                         ".set\tmips0"                                   \
 680                         : "=r" (__res));                                \
 681         else                                                            \
 682                 __asm__ __volatile__(                                   \
 683                         ".set\tmips64\n\t"                              \
 684                         "dmfc0\t%0, " #source ", " #sel "\n\t"          \
 685                         ".set\tmips0"                                   \
 686                         : "=r" (__res));                                \
 687         __res;                                                          \
 688 })
 689
 690 #define __write_32bit_c0_register(register, sel, value)                 \
 691 do {                                                                    \
 692         if (sel == 0)                                                   \
 693                 __asm__ __volatile__(                                   \
 694                         "mtc0\t%z0, " #register "\n\t"                  \
 695                         : : "Jr" ((unsigned int)value));                \
 696         else                                                            \
 697                 __asm__ __volatile__(                                   \
 698                         ".set\tmips32\n\t"                              \
 699                         "mtc0\t%z0, " #register ", " #sel "\n\t"        \
 700                         ".set\tmips0"                                   \
 701                         : : "Jr" ((unsigned int)value));                \
 702 } while (0)
 703
 704 #define __write_64bit_c0_register(register, sel, value)                 \
 705 do {                                                                    \
 706         if (sizeof(unsigned long) == 4)                                 \
 707                 __write_64bit_c0_split(register, sel, value);           \
 708         else if (sel == 0)                                              \
 709                 __asm__ __volatile__(                                   \
 710                         ".set\tmips3\n\t"                               \
 711                         "dmtc0\t%z0, " #register "\n\t"                 \
 712                         ".set\tmips0"                                   \
 713                         : : "Jr" (value));                              \
 714         else                                                            \
 715                 __asm__ __volatile__(                                   \
 716                         ".set\tmips64\n\t"                              \
 717                         "dmtc0\t%z0, " #register ", " #sel "\n\t"       \
 718                         ".set\tmips0"                                   \
 719                         : : "Jr" (value));                              \
 720 } while (0)
 721
 722 #define __read_ulong_c0_register(reg, sel)                              \
 723         ((sizeof(unsigned long) == 4) ?                                 \
 724         (unsigned long) __read_32bit_c0_register(reg, sel) :            \
 725         (unsigned long) __read_64bit_c0_register(reg, sel))
 726
 727 #define __write_ulong_c0_register(reg, sel, val)                        \
 728 do {                                                                    \
 729         if (sizeof(unsigned long) == 4)                                 \
 730                 __write_32bit_c0_register(reg, sel, val);               \
 731         else                                                            \
 732                 __write_64bit_c0_register(reg, sel, val);               \
 733 } while (0)
 734
 735 /*
 736  * On RM7000/RM9000 these are uses to access cop0 set 1 registers
 737  */
 738 #define __read_32bit_c0_ctrl_register(source)                           \
 739 ({ int __res;                                                           \
 740         __asm__ __volatile__(                                           \
 741                 "cfc0\t%0, " #source "\n\t"                             \
 742                 : "=r" (__res));                                        \
 743         __res;                                                          \
 744 })
 745
 746 #define __write_32bit_c0_ctrl_register(register, value)                 \
 747 do {                                                                    \
 748         __asm__ __volatile__(                                           \
 749                 "ctc0\t%z0, " #register "\n\t"                          \
 750                 : : "Jr" ((unsigned int)value));                        \
 751 } while (0)
 752
 753 /*
 754  * These versions are only needed for systems with more than 38 bits of
 755  * physical address space running the 32-bit kernel.  That's none atm :-)
 756  */
 757 #define __read_64bit_c0_split(source, sel)                              \
 758 ({                                                                      \
 759         unsigned long long val;                                         \
 760         unsigned long flags;                                            \
 761                                                                         \
 762         local_irq_save(flags);                                          \
 763         if (sel == 0)                                                   \
 764                 __asm__ __volatile__(                                   \
 765                         ".set\tmips64\n\t"                              \
 766                         "dmfc0\t%M0, " #source "\n\t"                   \
 767                         "dsll\t%L0, %M0, 32\n\t"                        \
 768                         "dsrl\t%M0, %M0, 32\n\t"                        \
 769                         "dsrl\t%L0, %L0, 32\n\t"                        \
 770                         ".set\tmips0"                                   \
 771                         : "=r" (val));                                  \
 772         else                                                            \
 773                 __asm__ __volatile__(                                   \
 774                         ".set\tmips64\n\t"                              \
 775                         "dmfc0\t%M0, " #source ", " #sel "\n\t"         \
 776                         "dsll\t%L0, %M0, 32\n\t"                        \
 777                         "dsrl\t%M0, %M0, 32\n\t"                        \
 778                         "dsrl\t%L0, %L0, 32\n\t"                        \
 779                         ".set\tmips0"                                   \
 780                         : "=r" (val));                                  \
 781         local_irq_restore(flags);                                       \
 782                                                                         \
 783         val;                                                            \
 784 })
 785
 786 #define __write_64bit_c0_split(source, sel, val)                        \
 787 do {                                                                    \
 788         unsigned long flags;                                            \
 789                                                                         \
 790         local_irq_save(flags);                                          \
 791         if (sel == 0)                                                   \
 792                 __asm__ __volatile__(                                   \
 793                         ".set\tmips64\n\t"                              \
 794                         "dsll\t%L0, %L0, 32\n\t"                        \
 795                         "dsrl\t%L0, %L0, 32\n\t"                        \
 796                         "dsll\t%M0, %M0, 32\n\t"                        \
 797                         "or\t%L0, %L0, %M0\n\t"                         \
 798                         "dmtc0\t%L0, " #source "\n\t"                   \
 799                         ".set\tmips0"                                   \
 800                         : : "r" (val));                                 \
 801         else                                                            \
 802                 __asm__ __volatile__(                                   \
 803                         ".set\tmips64\n\t"                              \
 804                         "dsll\t%L0, %L0, 32\n\t"                        \
 805                         "dsrl\t%L0, %L0, 32\n\t"                        \
 806                         "dsll\t%M0, %M0, 32\n\t"                        \
 807                         "or\t%L0, %L0, %M0\n\t"                         \
 808                         "dmtc0\t%L0, " #source ", " #sel "\n\t"         \
 809                         ".set\tmips0"                                   \
 810                         : : "r" (val));                                 \
 811         local_irq_restore(flags);                                       \
 812 } while (0)
 813
 814 #define read_c0_index()         __read_32bit_c0_register($0, 0)
 815 #define write_c0_index(val)     __write_32bit_c0_register($0, 0, val)
 816
 817 #define read_c0_entrylo0()      __read_ulong_c0_register($2, 0)
 818 #define write_c0_entrylo0(val)  __write_ulong_c0_register($2, 0, val)
 819
 820 #define read_c0_entrylo1()      __read_ulong_c0_register($3, 0)
 821 #define write_c0_entrylo1(val)  __write_ulong_c0_register($3, 0, val)
 822
 823 #define read_c0_conf()          __read_32bit_c0_register($3, 0)
 824 #define write_c0_conf(val)      __write_32bit_c0_register($3, 0, val)
 825
 826 #define read_c0_context()       __read_ulong_c0_register($4, 0)
 827 #define write_c0_context(val)   __write_ulong_c0_register($4, 0, val)
 828
 829 #define read_c0_pagemask()      __read_32bit_c0_register($5, 0)
 830 #define write_c0_pagemask(val)  __write_32bit_c0_register($5, 0, val)
 831
 832 #define read_c0_wired()         __read_32bit_c0_register($6, 0)
 833 #define write_c0_wired(val)     __write_32bit_c0_register($6, 0, val)
 834
 835 #define read_c0_info()          __read_32bit_c0_register($7, 0)
 836
 837 #define read_c0_cache()         __read_32bit_c0_register($7, 0) /* TX39xx */
 838 #define write_c0_cache(val)     __write_32bit_c0_register($7, 0, val)
 839
 840 #define read_c0_count()         __read_32bit_c0_register($9, 0)
 841 #define write_c0_count(val)     __write_32bit_c0_register($9, 0, val)
 842
 843 #define read_c0_entryhi()       __read_ulong_c0_register($10, 0)
 844 #define write_c0_entryhi(val)   __write_ulong_c0_register($10, 0, val)
 845
 846 #define read_c0_compare()       __read_32bit_c0_register($11, 0)
 847 #define write_c0_compare(val)   __write_32bit_c0_register($11, 0, val)
 848
 849 #define read_c0_status()        __read_32bit_c0_register($12, 0)
 850 #define write_c0_status(val)    __write_32bit_c0_register($12, 0, val)
 851
 852 #define read_c0_cause()         __read_32bit_c0_register($13, 0)
 853 #define write_c0_cause(val)     __write_32bit_c0_register($13, 0, val)
 854
 855 #define read_c0_epc()           __read_ulong_c0_register($14, 0)
 856 #define write_c0_epc(val)       __write_ulong_c0_register($14, 0, val)
 857
 858 #define read_c0_prid()          __read_32bit_c0_register($15, 0)
 859
 860 #define read_c0_config()        __read_32bit_c0_register($16, 0)
 861 #define read_c0_config1()       __read_32bit_c0_register($16, 1)
 862 #define read_c0_config2()       __read_32bit_c0_register($16, 2)
 863 #define read_c0_config3()       __read_32bit_c0_register($16, 3)
 864 #define read_c0_config4()       __read_32bit_c0_register($16, 4)
 865 #define read_c0_config5()       __read_32bit_c0_register($16, 5)
 866 #define read_c0_config6()       __read_32bit_c0_register($16, 6)
 867 #define read_c0_config7()       __read_32bit_c0_register($16, 7)
 868 #define write_c0_config(val)    __write_32bit_c0_register($16, 0, val)
 869 #define write_c0_config1(val)   __write_32bit_c0_register($16, 1, val)
 870 #define write_c0_config2(val)   __write_32bit_c0_register($16, 2, val)
 871 #define write_c0_config3(val)   __write_32bit_c0_register($16, 3, val)
 872 #define write_c0_config4(val)   __write_32bit_c0_register($16, 4, val)
 873 #define write_c0_config5(val)   __write_32bit_c0_register($16, 5, val)
 874 #define write_c0_config6(val)   __write_32bit_c0_register($16, 6, val)
 875 #define write_c0_config7(val)   __write_32bit_c0_register($16, 7, val)
 876
 877 /*
 878  * The WatchLo register.  There may be upto 8 of them.
 879  */
 880 #define read_c0_watchlo0()      __read_ulong_c0_register($18, 0)
 881 #define read_c0_watchlo1()      __read_ulong_c0_register($18, 1)
 882 #define read_c0_watchlo2()      __read_ulong_c0_register($18, 2)
 883 #define read_c0_watchlo3()      __read_ulong_c0_register($18, 3)
 884 #define read_c0_watchlo4()      __read_ulong_c0_register($18, 4)
 885 #define read_c0_watchlo5()      __read_ulong_c0_register($18, 5)
 886 #define read_c0_watchlo6()      __read_ulong_c0_register($18, 6)
 887 #define read_c0_watchlo7()      __read_ulong_c0_register($18, 7)
 888 #define write_c0_watchlo0(val)  __write_ulong_c0_register($18, 0, val)
 889 #define write_c0_watchlo1(val)  __write_ulong_c0_register($18, 1, val)
 890 #define write_c0_watchlo2(val)  __write_ulong_c0_register($18, 2, val)
 891 #define write_c0_watchlo3(val)  __write_ulong_c0_register($18, 3, val)
 892 #define write_c0_watchlo4(val)  __write_ulong_c0_register($18, 4, val)
 893 #define write_c0_watchlo5(val)  __write_ulong_c0_register($18, 5, val)
 894 #define write_c0_watchlo6(val)  __write_ulong_c0_register($18, 6, val)
 895 #define write_c0_watchlo7(val)  __write_ulong_c0_register($18, 7, val)
 896
 897 /*
 898  * The WatchHi register.  There may be upto 8 of them.
 899  */
 900 #define read_c0_watchhi0()      __read_32bit_c0_register($19, 0)
 901 #define read_c0_watchhi1()      __read_32bit_c0_register($19, 1)
 902 #define read_c0_watchhi2()      __read_32bit_c0_register($19, 2)
 903 #define read_c0_watchhi3()      __read_32bit_c0_register($19, 3)
 904 #define read_c0_watchhi4()      __read_32bit_c0_register($19, 4)
 905 #define read_c0_watchhi5()      __read_32bit_c0_register($19, 5)
 906 #define read_c0_watchhi6()      __read_32bit_c0_register($19, 6)
 907 #define read_c0_watchhi7()      __read_32bit_c0_register($19, 7)
 908
 909 #define write_c0_watchhi0(val)  __write_32bit_c0_register($19, 0, val)
 910 #define write_c0_watchhi1(val)  __write_32bit_c0_register($19, 1, val)
 911 #define write_c0_watchhi2(val)  __write_32bit_c0_register($19, 2, val)
 912 #define write_c0_watchhi3(val)  __write_32bit_c0_register($19, 3, val)
 913 #define write_c0_watchhi4(val)  __write_32bit_c0_register($19, 4, val)
 914 #define write_c0_watchhi5(val)  __write_32bit_c0_register($19, 5, val)
 915 #define write_c0_watchhi6(val)  __write_32bit_c0_register($19, 6, val)
 916 #define write_c0_watchhi7(val)  __write_32bit_c0_register($19, 7, val)
 917
 918 #define read_c0_xcontext()      __read_ulong_c0_register($20, 0)
 919 #define write_c0_xcontext(val)  __write_ulong_c0_register($20, 0, val)
 920
 921 #define read_c0_intcontrol()    __read_32bit_c0_ctrl_register($20)
 922 #define write_c0_intcontrol(val) __write_32bit_c0_ctrl_register($20, val)
 923
 924 #define read_c0_framemask()     __read_32bit_c0_register($21, 0)
 925 #define write_c0_framemask(val) __write_32bit_c0_register($21, 0, val)
 926
 927 /* RM9000 PerfControl performance counter control register */
 928 #define read_c0_perfcontrol()   __read_32bit_c0_register($22, 0)
 929 #define write_c0_perfcontrol(val) __write_32bit_c0_register($22, 0, val)
 930
 931 #define read_c0_diag()          __read_32bit_c0_register($22, 0)
 932 #define write_c0_diag(val)      __write_32bit_c0_register($22, 0, val)
 933
 934 #define read_c0_diag1()         __read_32bit_c0_register($22, 1)
 935 #define write_c0_diag1(val)     __write_32bit_c0_register($22, 1, val)
 936
 937 #define read_c0_diag2()         __read_32bit_c0_register($22, 2)
 938 #define write_c0_diag2(val)     __write_32bit_c0_register($22, 2, val)
 939
 940 #define read_c0_diag3()         __read_32bit_c0_register($22, 3)
 941 #define write_c0_diag3(val)     __write_32bit_c0_register($22, 3, val)
 942
 943 #define read_c0_diag4()         __read_32bit_c0_register($22, 4)
 944 #define write_c0_diag4(val)     __write_32bit_c0_register($22, 4, val)
 945
 946 #define read_c0_diag5()         __read_32bit_c0_register($22, 5)
 947 #define write_c0_diag5(val)     __write_32bit_c0_register($22, 5, val)
 948
 949 #define read_c0_debug()         __read_32bit_c0_register($23, 0)
 950 #define write_c0_debug(val)     __write_32bit_c0_register($23, 0, val)
 951
 952 #define read_c0_depc()          __read_ulong_c0_register($24, 0)
 953 #define write_c0_depc(val)      __write_ulong_c0_register($24, 0, val)
 954
 955 /*
 956  * MIPS32 / MIPS64 performance counters
 957  */
 958 #define read_c0_perfctrl0()     __read_32bit_c0_register($25, 0)
 959 #define write_c0_perfctrl0(val) __write_32bit_c0_register($25, 0, val)
 960 #define read_c0_perfcntr0()     __read_32bit_c0_register($25, 1)
 961 #define write_c0_perfcntr0(val) __write_32bit_c0_register($25, 1, val)
 962 #define read_c0_perfctrl1()     __read_32bit_c0_register($25, 2)
 963 #define write_c0_perfctrl1(val) __write_32bit_c0_register($25, 2, val)
 964 #define read_c0_perfcntr1()     __read_32bit_c0_register($25, 3)
 965 #define write_c0_perfcntr1(val) __write_32bit_c0_register($25, 3, val)
 966 #define read_c0_perfctrl2()     __read_32bit_c0_register($25, 4)
 967 #define write_c0_perfctrl2(val) __write_32bit_c0_register($25, 4, val)
 968 #define read_c0_perfcntr2()     __read_32bit_c0_register($25, 5)
 969 #define write_c0_perfcntr2(val) __write_32bit_c0_register($25, 5, val)
 970 #define read_c0_perfctrl3()     __read_32bit_c0_register($25, 6)
 971 #define write_c0_perfctrl3(val) __write_32bit_c0_register($25, 6, val)
 972 #define read_c0_perfcntr3()     __read_32bit_c0_register($25, 7)
 973 #define write_c0_perfcntr3(val) __write_32bit_c0_register($25, 7, val)
 974
 975 /* RM9000 PerfCount performance counter register */
 976 #define read_c0_perfcount()     __read_64bit_c0_register($25, 0)
 977 #define write_c0_perfcount(val) __write_64bit_c0_register($25, 0, val)
 978
 979 #define read_c0_ecc()           __read_32bit_c0_register($26, 0)
 980 #define write_c0_ecc(val)       __write_32bit_c0_register($26, 0, val)
 981
 982 #define read_c0_derraddr0()     __read_ulong_c0_register($26, 1)
 983 #define write_c0_derraddr0(val) __write_ulong_c0_register($26, 1, val)
 984
 985 #define read_c0_cacheerr()      __read_32bit_c0_register($27, 0)
 986
 987 #define read_c0_derraddr1()     __read_ulong_c0_register($27, 1)
 988 #define write_c0_derraddr1(val) __write_ulong_c0_register($27, 1, val)
 989
 990 #define read_c0_taglo()         __read_32bit_c0_register($28, 0)
 991 #define write_c0_taglo(val)     __write_32bit_c0_register($28, 0, val)
 992
 993 #define read_c0_taghi()         __read_32bit_c0_register($29, 0)
 994 #define write_c0_taghi(val)     __write_32bit_c0_register($29, 0, val)
 995
 996 #define read_c0_errorepc()      __read_ulong_c0_register($30, 0)
 997 #define write_c0_errorepc(val)  __write_ulong_c0_register($30, 0, val)
 998
 999 /* MIPSR2 */
1000 #define read_c0_hwrena()        __read_32bit_c0_register($7,0)
1001 #define write_c0_hwrena(val)    __write_32bit_c0_register($7, 0, val)
1002
1003 #define read_c0_intctl()        __read_32bit_c0_register($12, 1)
1004 #define write_c0_intctl(val)    __write_32bit_c0_register($12, 1, val)
1005
1006 #define read_c0_srsctl()        __read_32bit_c0_register($12, 2)
1007 #define write_c0_srsctl(val)    __write_32bit_c0_register($12, 2, val)
1008
1009 #define read_c0_srsmap()        __read_32bit_c0_register($12, 3)
1010 #define write_c0_srsmap(val)    __write_32bit_c0_register($12, 3, val)
1011
1012 #define read_c0_ebase()         __read_32bit_c0_register($15,1)
1013 #define write_c0_ebase(val)     __write_32bit_c0_register($15, 1, val)
1014
1015 /*
1016  * Macros to access the floating point coprocessor control registers
1017  */
1018 #define read_32bit_cp1_register(source)                         \
1019 ({ int __res;                                                   \
1020         __asm__ __volatile__(                                   \
1021         ".set\tpush\n\t"                                        \
1022         ".set\treorder\n\t"                                     \
1023         "cfc1\t%0,"STR(source)"\n\t"                            \
1024         ".set\tpop"                                             \
1025         : "=r" (__res));                                        \
1026         __res;})
1027
1028 #define rddsp(mask)                                                     \
1029 ({                                                                      \
1030         unsigned int __res;                                             \
1031                                                                         \
1032         __asm__ __volatile__(                                           \
1033         "       .set    push                            \n"             \
1034         "       .set    noat                            \n"             \
1035         "       # rddsp $1, %x1                         \n"             \
1036         "       .word   0x7c000cb8 | (%x1 << 16)        \n"             \
1037         "       move    %0, $1                          \n"             \
1038         "       .set    pop                             \n"             \
1039         : "=r" (__res)                                                  \
1040         : "i" (mask));                                                  \
1041         __res;                                                          \
1042 })
1043
1044 #define wrdsp(val, mask)                                                \
1045 do {                                                                    \
1046         __asm__ __volatile__(                                           \
1047         "       .set    push                                    \n"     \
1048         "       .set    noat                                    \n"     \
1049         "       move    $1, %0                                  \n"     \
1050         "       # wrdsp $1, %x1                                 \n"     \
1051         "       .word   0x7c2004f8 | (%x1 << 15)                \n"     \
1052         "       .set    pop                                     \n"     \
1053         :                                                               \
1054         : "r" (val), "i" (mask));                                       \
1055 } while (0)
1056
1057 #if 0   /* Need DSP ASE capable assembler ... */
1058 #define mflo0() ({ long mflo0; __asm__("mflo %0, $ac0" : "=r" (mflo0)); mflo0;})
1059 #define mflo1() ({ long mflo1; __asm__("mflo %0, $ac1" : "=r" (mflo1)); mflo1;})
1060 #define mflo2() ({ long mflo2; __asm__("mflo %0, $ac2" : "=r" (mflo2)); mflo2;})
1061 #define mflo3() ({ long mflo3; __asm__("mflo %0, $ac3" : "=r" (mflo3)); mflo3;})
1062
1063 #define mfhi0() ({ long mfhi0; __asm__("mfhi %0, $ac0" : "=r" (mfhi0)); mfhi0;})
1064 #define mfhi1() ({ long mfhi1; __asm__("mfhi %0, $ac1" : "=r" (mfhi1)); mfhi1;})
1065 #define mfhi2() ({ long mfhi2; __asm__("mfhi %0, $ac2" : "=r" (mfhi2)); mfhi2;})
1066 #define mfhi3() ({ long mfhi3; __asm__("mfhi %0, $ac3" : "=r" (mfhi3)); mfhi3;})
1067
1068 #define mtlo0(x) __asm__("mtlo %0, $ac0" ::"r" (x))
1069 #define mtlo1(x) __asm__("mtlo %0, $ac1" ::"r" (x))
1070 #define mtlo2(x) __asm__("mtlo %0, $ac2" ::"r" (x))
1071 #define mtlo3(x) __asm__("mtlo %0, $ac3" ::"r" (x))
1072
1073 #define mthi0(x) __asm__("mthi %0, $ac0" ::"r" (x))
1074 #define mthi1(x) __asm__("mthi %0, $ac1" ::"r" (x))
1075 #define mthi2(x) __asm__("mthi %0, $ac2" ::"r" (x))
1076 #define mthi3(x) __asm__("mthi %0, $ac3" ::"r" (x))
1077
1078 #else
1079
1080 #define mfhi0()                                                         \
1081 ({                                                                      \
1082         unsigned long __treg;                                           \
1083                                                                         \
1084         __asm__ __volatile__(                                           \
1085         "       .set    push                    \n"                     \
1086         "       .set    noat                    \n"                     \
1087         "       # mfhi  %0, $ac0                \n"                     \
1088         "       .word   0x00000810              \n"                     \
1089         "       move    %0, $1                  \n"                     \
1090         "       .set    pop                     \n"                     \
1091         : "=r" (__treg));                                               \
1092         __treg;                                                         \
1093 })
1094
1095 #define mfhi1()                                                         \
1096 ({                                                                      \
1097         unsigned long __treg;                                           \
1098                                                                         \
1099         __asm__ __volatile__(                                           \
1100         "       .set    push                    \n"                     \
1101         "       .set    noat                    \n"                     \
1102         "       # mfhi  %0, $ac1                \n"                     \
1103         "       .word   0x00200810              \n"                     \
1104         "       move    %0, $1                  \n"                     \
1105         "       .set    pop                     \n"                     \
1106         : "=r" (__treg));                                               \
1107         __treg;                                                         \
1108 })
1109
1110 #define mfhi2()                                                         \
1111 ({                                                                      \
1112         unsigned long __treg;                                           \
1113                                                                         \
1114         __asm__ __volatile__(                                           \
1115         "       .set    push                    \n"                     \
1116         "       .set    noat                    \n"                     \
1117         "       # mfhi  %0, $ac2                \n"                     \
1118         "       .word   0x00400810              \n"                     \
1119         "       move    %0, $1                  \n"                     \
1120         "       .set    pop                     \n"                     \
1121         : "=r" (__treg));                                               \
1122         __treg;                                                         \
1123 })
1124
1125 #define mfhi3()                                                         \
1126 ({                                                                      \
1127         unsigned long __treg;                                           \
1128                                                                         \
1129         __asm__ __volatile__(                                           \
1130         "       .set    push                    \n"                     \
1131         "       .set    noat                    \n"                     \
1132         "       # mfhi  %0, $ac3                \n"                     \
1133         "       .word   0x00600810              \n"                     \
1134         "       move    %0, $1                  \n"                     \
1135         "       .set    pop                     \n"                     \
1136         : "=r" (__treg));                                               \
1137         __treg;                                                         \
1138 })
1139
1140 #define mflo0()                                                         \
1141 ({                                                                      \
1142         unsigned long __treg;                                           \
1143                                                                         \
1144         __asm__ __volatile__(                                           \
1145         "       .set    push                    \n"                     \
1146         "       .set    noat                    \n"                     \
1147         "       # mflo  %0, $ac0                \n"                     \
1148         "       .word   0x00000812              \n"                     \
1149         "       move    %0, $1                  \n"                     \
1150         "       .set    pop                     \n"                     \
1151         : "=r" (__treg));                                               \
1152         __treg;                                                         \
1153 })
1154
1155 #define mflo1()                                                         \
1156 ({                                                                      \
1157         unsigned long __treg;                                           \
1158                                                                         \
1159         __asm__ __volatile__(                                           \
1160         "       .set    push                    \n"                     \
1161         "       .set    noat                    \n"                     \
1162         "       # mflo  %0, $ac1                \n"                     \
1163         "       .word   0x00200812              \n"                     \
1164         "       move    %0, $1                  \n"                     \
1165         "       .set    pop                     \n"                     \
1166         : "=r" (__treg));                                               \
1167         __treg;                                                         \
1168 })
1169
1170 #define mflo2()                                                         \
1171 ({                                                                      \
1172         unsigned long __treg;                                           \
1173                                                                         \
1174         __asm__ __volatile__(                                           \
1175         "       .set    push                    \n"                     \
1176         "       .set    noat                    \n"                     \
1177         "       # mflo  %0, $ac2                \n"                     \
1178         "       .word   0x00400812              \n"                     \
1179         "       move    %0, $1                  \n"                     \
1180         "       .set    pop                     \n"                     \
1181         : "=r" (__treg));                                               \
1182         __treg;                                                         \
1183 })
1184
1185 #define mflo3()                                                         \
1186 ({                                                                      \
1187         unsigned long __treg;                                           \
1188                                                                         \
1189         __asm__ __volatile__(                                           \
1190         "       .set    push                    \n"                     \
1191         "       .set    noat                    \n"                     \
1192         "       # mflo  %0, $ac3                \n"                     \
1193         "       .word   0x00600812              \n"                     \
1194         "       move    %0, $1                  \n"                     \
1195         "       .set    pop                     \n"                     \
1196         : "=r" (__treg));                                               \
1197         __treg;                                                         \
1198 })
1199
1200 #define mthi0(x)                                                        \
1201 do {                                                                    \
1202         __asm__ __volatile__(                                           \
1203         "       .set    push                                    \n"     \
1204         "       .set    noat                                    \n"     \
1205         "       move    $1, %0                                  \n"     \
1206         "       # mthi  $1, $ac0                                \n"     \
1207         "       .word   0x00200011                              \n"     \
1208         "       .set    pop                                     \n"     \
1209         :                                                               \
1210         : "r" (x));                                                     \
1211 } while (0)
1212
1213 #define mthi1(x)                                                        \
1214 do {                                                                    \
1215         __asm__ __volatile__(                                           \
1216         "       .set    push                                    \n"     \
1217         "       .set    noat                                    \n"     \
1218         "       move    $1, %0                                  \n"     \
1219         "       # mthi  $1, $ac1                                \n"     \
1220         "       .word   0x00200811                              \n"     \
1221         "       .set    pop                                     \n"     \
1222         :                                                               \
1223         : "r" (x));                                                     \
1224 } while (0)
1225
1226 #define mthi2(x)                                                        \
1227 do {                                                                    \
1228         __asm__ __volatile__(                                           \
1229         "       .set    push                                    \n"     \
1230         "       .set    noat                                    \n"     \
1231         "       move    $1, %0                                  \n"     \
1232         "       # mthi  $1, $ac2                                \n"     \
1233         "       .word   0x00201011                              \n"     \
1234         "       .set    pop                                     \n"     \
1235         :                                                               \
1236         : "r" (x));                                                     \
1237 } while (0)
1238
1239 #define mthi3(x)                                                        \
1240 do {                                                                    \
1241         __asm__ __volatile__(                                           \
1242         "       .set    push                                    \n"     \
1243         "       .set    noat                                    \n"     \
1244         "       move    $1, %0                                  \n"     \
1245         "       # mthi  $1, $ac3                                \n"     \
1246         "       .word   0x00201811                              \n"     \
1247         "       .set    pop                                     \n"     \
1248         :                                                               \
1249         : "r" (x));                                                     \
1250 } while (0)
1251
1252 #define mtlo0(x)                                                        \
1253 do {                                                                    \
1254         __asm__ __volatile__(                                           \
1255         "       .set    push                                    \n"     \
1256         "       .set    noat                                    \n"     \
1257         "       move    $1, %0                                  \n"     \
1258         "       # mtlo  $1, $ac0                                \n"     \
1259         "       .word   0x00200013                              \n"     \
1260         "       .set    pop                                     \n"     \
1261         :                                                               \
1262         : "r" (x));                                                     \
1263 } while (0)
1264
1265 #define mtlo1(x)                                                        \
1266 do {                                                                    \
1267         __asm__ __volatile__(                                           \
1268         "       .set    push                                    \n"     \
1269         "       .set    noat                                    \n"     \
1270         "       move    $1, %0                                  \n"     \
1271         "       # mtlo  $1, $ac1                                \n"     \
1272         "       .word   0x00200813                              \n"     \
1273         "       .set    pop                                     \n"     \
1274         :                                                               \
1275         : "r" (x));                                                     \
1276 } while (0)
1277
1278 #define mtlo2(x)                                                        \
1279 do {                                                                    \
1280         __asm__ __volatile__(                                           \
1281         "       .set    push                                    \n"     \
1282         "       .set    noat                                    \n"     \
1283         "       move    $1, %0                                  \n"     \
1284         "       # mtlo  $1, $ac2                                \n"     \
1285         "       .word   0x00201013                              \n"     \
1286         "       .set    pop                                     \n"     \
1287         :                                                               \
1288         : "r" (x));                                                     \
1289 } while (0)
1290
1291 #define mtlo3(x)                                                        \
1292 do {                                                                    \
1293         __asm__ __volatile__(                                           \
1294         "       .set    push                                    \n"     \
1295         "       .set    noat                                    \n"     \
1296         "       move    $1, %0                                  \n"     \
1297         "       # mtlo  $1, $ac3                                \n"     \
1298         "       .word   0x00201813                              \n"     \
1299         "       .set    pop                                     \n"     \
1300         :                                                               \
1301         : "r" (x));                                                     \
1302 } while (0)
1303
1304 #endif
1305
1306 /*
1307  * TLB operations.
1308  *
1309  * It is responsibility of the caller to take care of any TLB hazards.
1310  */
1311 static inline void tlb_probe(void)
1312 {
1313         __asm__ __volatile__(
1314                 ".set noreorder\n\t"
1315                 "tlbp\n\t"
1316                 ".set reorder");
1317 }
1318
1319 static inline void tlb_read(void)
1320 {
1321         __asm__ __volatile__(
1322                 ".set noreorder\n\t"
1323                 "tlbr\n\t"
1324                 ".set reorder");
1325 }
1326
1327 static inline void tlb_write_indexed(void)
1328 {
1329         __asm__ __volatile__(
1330                 ".set noreorder\n\t"
1331                 "tlbwi\n\t"
1332                 ".set reorder");
1333 }
1334
1335 static inline void tlb_write_random(void)
1336 {
1337         __asm__ __volatile__(
1338                 ".set noreorder\n\t"
1339                 "tlbwr\n\t"
1340                 ".set reorder");
1341 }
1342
1343 /*
1344  * Manipulate bits in a c0 register.
1345  */
1346 #define __BUILD_SET_C0(name)                                    \
1347 static inline unsigned int                                      \
1348 set_c0_##name(unsigned int set)                                 \
1349 {                                                               \
1350         unsigned int res;                                       \
1351                                                                 \
1352         res = read_c0_##name();                                 \
1353         res |= set;                                             \
1354         write_c0_##name(res);                                   \
1355                                                                 \
1356         return res;                                             \
1357 }                                                               \
1358                                                                 \
1359 static inline unsigned int                                      \
1360 clear_c0_##name(unsigned int clear)                             \
1361 {                                                               \
1362         unsigned int res;                                       \
1363                                                                 \
1364         res = read_c0_##name();                                 \
1365         res &= ~clear;                                          \
1366         write_c0_##name(res);                                   \
1367                                                                 \
1368         return res;                                             \
1369 }                                                               \
1370                                                                 \
1371 static inline unsigned int                                      \
1372 change_c0_##name(unsigned int change, unsigned int new)         \
1373 {                                                               \
1374         unsigned int res;                                       \
1375                                                                 \
1376         res = read_c0_##name();                                 \
1377         res &= ~change;                                         \
1378         res |= (new & change);                                  \
1379         write_c0_##name(res);                                   \
1380                                                                 \
1381         return res;                                             \
1382 }
1383
1384 __BUILD_SET_C0(status)
1385 __BUILD_SET_C0(cause)
1386 __BUILD_SET_C0(config)
1387 __BUILD_SET_C0(intcontrol)
1388 __BUILD_SET_C0(intctl)
1389 __BUILD_SET_C0(srsmap)
1390
1391 #endif /* !__ASSEMBLY__ */
1392
1393 #endif /* _ASM_MIPSREGS_H */