1 /* *********************************************************************
2 * SB1250 Board Support Package
4 * SCD Constants and Macros File: sb1250_scd.h
6 * This module contains constants and macros useful for
7 * manipulating the System Control and Debug module on the 1250.
9 * SB1250 specification level: User's manual 1/02/02
11 * Author: Mitch Lichtenberg
13 *********************************************************************
15 * Copyright 2000,2001,2002,2003
16 * Broadcom Corporation. All rights reserved.
18 * This program is free software; you can redistribute it and/or
19 * modify it under the terms of the GNU General Public License as
20 * published by the Free Software Foundation; either version 2 of
21 * the License, or (at your option) any later version.
23 * This program is distributed in the hope that it will be useful,
24 * but WITHOUT ANY WARRANTY; without even the implied warranty of
25 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
26 * GNU General Public License for more details.
28 * You should have received a copy of the GNU General Public License
29 * along with this program; if not, write to the Free Software
30 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
32 ********************************************************************* */
37 #include "sb1250_defs.h"
39 /* *********************************************************************
40 * System control/debug registers
41 ********************************************************************* */
44 * System Revision Register (Table 4-1)
47 #define M_SYS_RESERVED _SB_MAKEMASK(8,0)
49 #define S_SYS_REVISION _SB_MAKE64(8)
50 #define M_SYS_REVISION _SB_MAKEMASK(8,S_SYS_REVISION)
51 #define V_SYS_REVISION(x) _SB_MAKEVALUE(x,S_SYS_REVISION)
52 #define G_SYS_REVISION(x) _SB_GETVALUE(x,S_SYS_REVISION,M_SYS_REVISION)
54 #define K_SYS_REVISION_BCM1250_PASS1 0x01
56 #define K_SYS_REVISION_BCM1250_PASS2 0x03
57 #define K_SYS_REVISION_BCM1250_A1 0x03 /* Pass 2.0 WB */
58 #define K_SYS_REVISION_BCM1250_A2 0x04 /* Pass 2.0 FC */
59 #define K_SYS_REVISION_BCM1250_A3 0x05 /* Pass 2.1 FC */
60 #define K_SYS_REVISION_BCM1250_A4 0x06 /* Pass 2.1 WB */
61 #define K_SYS_REVISION_BCM1250_A6 0x07 /* OR 0x04 (A2) w/WID != 0 */
62 #define K_SYS_REVISION_BCM1250_A8 0x0b /* A8/A10 */
63 #define K_SYS_REVISION_BCM1250_A9 0x08
64 #define K_SYS_REVISION_BCM1250_A10 K_SYS_REVISION_BCM1250_A8
66 #define K_SYS_REVISION_BCM1250_PASS2_2 0x10
67 #define K_SYS_REVISION_BCM1250_B0 K_SYS_REVISION_BCM1250_B1
68 #define K_SYS_REVISION_BCM1250_B1 0x10
69 #define K_SYS_REVISION_BCM1250_B2 0x11
71 #define K_SYS_REVISION_BCM1250_C0 0x20
72 #define K_SYS_REVISION_BCM1250_C1 0x21
73 #define K_SYS_REVISION_BCM1250_C2 0x22
74 #define K_SYS_REVISION_BCM1250_C3 0x23
76 #if SIBYTE_HDR_FEATURE_CHIP(1250)
77 /* XXX: discourage people from using these constants. */
78 #define K_SYS_REVISION_PASS1 K_SYS_REVISION_BCM1250_PASS1
79 #define K_SYS_REVISION_PASS2 K_SYS_REVISION_BCM1250_PASS2
80 #define K_SYS_REVISION_PASS2_2 K_SYS_REVISION_BCM1250_PASS2_2
81 #define K_SYS_REVISION_PASS3 K_SYS_REVISION_BCM1250_PASS3
82 #define K_SYS_REVISION_BCM1250_PASS3 K_SYS_REVISION_BCM1250_C0
85 #define K_SYS_REVISION_BCM112x_A1 0x20
86 #define K_SYS_REVISION_BCM112x_A2 0x21
87 #define K_SYS_REVISION_BCM112x_A3 0x22
88 #define K_SYS_REVISION_BCM112x_A4 0x23
90 #define K_SYS_REVISION_BCM1480_S0 0x01
91 #define K_SYS_REVISION_BCM1480_A1 0x02
92 #define K_SYS_REVISION_BCM1480_A2 0x03
93 #define K_SYS_REVISION_BCM1480_A3 0x04
94 #define K_SYS_REVISION_BCM1480_B0 0x11
96 /*Cache size - 23:20 of revision register*/
97 #define S_SYS_L2C_SIZE _SB_MAKE64(20)
98 #define M_SYS_L2C_SIZE _SB_MAKEMASK(4,S_SYS_L2C_SIZE)
99 #define V_SYS_L2C_SIZE(x) _SB_MAKEVALUE(x,S_SYS_L2C_SIZE)
100 #define G_SYS_L2C_SIZE(x) _SB_GETVALUE(x,S_SYS_L2C_SIZE,M_SYS_L2C_SIZE)
102 #define K_SYS_L2C_SIZE_1MB 0
103 #define K_SYS_L2C_SIZE_512KB 5
104 #define K_SYS_L2C_SIZE_256KB 2
105 #define K_SYS_L2C_SIZE_128KB 1
107 #define K_SYS_L2C_SIZE_BCM1250 K_SYS_L2C_SIZE_512KB
108 #define K_SYS_L2C_SIZE_BCM1125 K_SYS_L2C_SIZE_256KB
109 #define K_SYS_L2C_SIZE_BCM1122 K_SYS_L2C_SIZE_128KB
112 /* Number of CPU cores, bits 27:24 of revision register*/
113 #define S_SYS_NUM_CPUS _SB_MAKE64(24)
114 #define M_SYS_NUM_CPUS _SB_MAKEMASK(4,S_SYS_NUM_CPUS)
115 #define V_SYS_NUM_CPUS(x) _SB_MAKEVALUE(x,S_SYS_NUM_CPUS)
116 #define G_SYS_NUM_CPUS(x) _SB_GETVALUE(x,S_SYS_NUM_CPUS,M_SYS_NUM_CPUS)
119 /* XXX: discourage people from using these constants. */
120 #define S_SYS_PART _SB_MAKE64(16)
121 #define M_SYS_PART _SB_MAKEMASK(16,S_SYS_PART)
122 #define V_SYS_PART(x) _SB_MAKEVALUE(x,S_SYS_PART)
123 #define G_SYS_PART(x) _SB_GETVALUE(x,S_SYS_PART,M_SYS_PART)
125 /* XXX: discourage people from using these constants. */
126 #define K_SYS_PART_SB1250 0x1250
127 #define K_SYS_PART_BCM1120 0x1121
128 #define K_SYS_PART_BCM1125 0x1123
129 #define K_SYS_PART_BCM1125H 0x1124
130 #define K_SYS_PART_BCM1122 0x1113
133 /* The "peripheral set" (SOC type) is the low 4 bits of the "part" field. */
134 #define S_SYS_SOC_TYPE _SB_MAKE64(16)
135 #define M_SYS_SOC_TYPE _SB_MAKEMASK(4,S_SYS_SOC_TYPE)
136 #define V_SYS_SOC_TYPE(x) _SB_MAKEVALUE(x,S_SYS_SOC_TYPE)
137 #define G_SYS_SOC_TYPE(x) _SB_GETVALUE(x,S_SYS_SOC_TYPE,M_SYS_SOC_TYPE)
139 #define K_SYS_SOC_TYPE_BCM1250 0x0
140 #define K_SYS_SOC_TYPE_BCM1120 0x1
141 #define K_SYS_SOC_TYPE_BCM1250_ALT 0x2 /* 1250pass2 w/ 1/4 L2. */
142 #define K_SYS_SOC_TYPE_BCM1125 0x3
143 #define K_SYS_SOC_TYPE_BCM1125H 0x4
144 #define K_SYS_SOC_TYPE_BCM1250_ALT2 0x5 /* 1250pass2 w/ 1/2 L2. */
145 #define K_SYS_SOC_TYPE_BCM1x80 0x6
146 #define K_SYS_SOC_TYPE_BCM1x55 0x7
149 * Calculate correct SOC type given a copy of system revision register.
151 * (For the assembler version, sysrev and dest may be the same register.
152 * Also, it clobbers AT.)
155 #define SYS_SOC_TYPE(dest, sysrev) \
158 dsrl dest, sysrev, S_SYS_SOC_TYPE ; \
159 andi dest, dest, (M_SYS_SOC_TYPE >> S_SYS_SOC_TYPE); \
160 beq dest, K_SYS_SOC_TYPE_BCM1250_ALT, 991f ; \
161 beq dest, K_SYS_SOC_TYPE_BCM1250_ALT2, 991f ; \
163 991: li dest, K_SYS_SOC_TYPE_BCM1250 ; \
167 #define SYS_SOC_TYPE(sysrev) \
168 ((G_SYS_SOC_TYPE(sysrev) == K_SYS_SOC_TYPE_BCM1250_ALT \
169 || G_SYS_SOC_TYPE(sysrev) == K_SYS_SOC_TYPE_BCM1250_ALT2) \
170 ? K_SYS_SOC_TYPE_BCM1250 : G_SYS_SOC_TYPE(sysrev))
173 #define S_SYS_WID _SB_MAKE64(32)
174 #define M_SYS_WID _SB_MAKEMASK(32,S_SYS_WID)
175 #define V_SYS_WID(x) _SB_MAKEVALUE(x,S_SYS_WID)
176 #define G_SYS_WID(x) _SB_GETVALUE(x,S_SYS_WID,M_SYS_WID)
179 * System Manufacturing Register
180 * Register: SCD_SYSTEM_MANUF
183 #if SIBYTE_HDR_FEATURE_1250_112x
184 /* Wafer ID: bits 31:0 */
185 #define S_SYS_WAFERID1_200 _SB_MAKE64(0)
186 #define M_SYS_WAFERID1_200 _SB_MAKEMASK(32,S_SYS_WAFERID1_200)
187 #define V_SYS_WAFERID1_200(x) _SB_MAKEVALUE(x,S_SYS_WAFERID1_200)
188 #define G_SYS_WAFERID1_200(x) _SB_GETVALUE(x,S_SYS_WAFERID1_200,M_SYS_WAFERID1_200)
190 #define S_SYS_BIN _SB_MAKE64(32)
191 #define M_SYS_BIN _SB_MAKEMASK(4,S_SYS_BIN)
192 #define V_SYS_BIN(x) _SB_MAKEVALUE(x,S_SYS_BIN)
193 #define G_SYS_BIN(x) _SB_GETVALUE(x,S_SYS_BIN,M_SYS_BIN)
195 /* Wafer ID: bits 39:36 */
196 #define S_SYS_WAFERID2_200 _SB_MAKE64(36)
197 #define M_SYS_WAFERID2_200 _SB_MAKEMASK(4,S_SYS_WAFERID2_200)
198 #define V_SYS_WAFERID2_200(x) _SB_MAKEVALUE(x,S_SYS_WAFERID2_200)
199 #define G_SYS_WAFERID2_200(x) _SB_GETVALUE(x,S_SYS_WAFERID2_200,M_SYS_WAFERID2_200)
201 /* Wafer ID: bits 39:0 */
202 #define S_SYS_WAFERID_300 _SB_MAKE64(0)
203 #define M_SYS_WAFERID_300 _SB_MAKEMASK(40,S_SYS_WAFERID_300)
204 #define V_SYS_WAFERID_300(x) _SB_MAKEVALUE(x,S_SYS_WAFERID_300)
205 #define G_SYS_WAFERID_300(x) _SB_GETVALUE(x,S_SYS_WAFERID_300,M_SYS_WAFERID_300)
207 #define S_SYS_XPOS _SB_MAKE64(40)
208 #define M_SYS_XPOS _SB_MAKEMASK(6,S_SYS_XPOS)
209 #define V_SYS_XPOS(x) _SB_MAKEVALUE(x,S_SYS_XPOS)
210 #define G_SYS_XPOS(x) _SB_GETVALUE(x,S_SYS_XPOS,M_SYS_XPOS)
212 #define S_SYS_YPOS _SB_MAKE64(46)
213 #define M_SYS_YPOS _SB_MAKEMASK(6,S_SYS_YPOS)
214 #define V_SYS_YPOS(x) _SB_MAKEVALUE(x,S_SYS_YPOS)
215 #define G_SYS_YPOS(x) _SB_GETVALUE(x,S_SYS_YPOS,M_SYS_YPOS)
219 * System Config Register (Table 4-2)
220 * Register: SCD_SYSTEM_CFG
223 #if SIBYTE_HDR_FEATURE_1250_112x
224 #define M_SYS_LDT_PLL_BYP _SB_MAKEMASK1(3)
225 #define M_SYS_PCI_SYNC_TEST_MODE _SB_MAKEMASK1(4)
226 #define M_SYS_IOB0_DIV _SB_MAKEMASK1(5)
227 #define M_SYS_IOB1_DIV _SB_MAKEMASK1(6)
229 #define S_SYS_PLL_DIV _SB_MAKE64(7)
230 #define M_SYS_PLL_DIV _SB_MAKEMASK(5,S_SYS_PLL_DIV)
231 #define V_SYS_PLL_DIV(x) _SB_MAKEVALUE(x,S_SYS_PLL_DIV)
232 #define G_SYS_PLL_DIV(x) _SB_GETVALUE(x,S_SYS_PLL_DIV,M_SYS_PLL_DIV)
234 #define M_SYS_SER0_ENABLE _SB_MAKEMASK1(12)
235 #define M_SYS_SER0_RSTB_EN _SB_MAKEMASK1(13)
236 #define M_SYS_SER1_ENABLE _SB_MAKEMASK1(14)
237 #define M_SYS_SER1_RSTB_EN _SB_MAKEMASK1(15)
238 #define M_SYS_PCMCIA_ENABLE _SB_MAKEMASK1(16)
240 #define S_SYS_BOOT_MODE _SB_MAKE64(17)
241 #define M_SYS_BOOT_MODE _SB_MAKEMASK(2,S_SYS_BOOT_MODE)
242 #define V_SYS_BOOT_MODE(x) _SB_MAKEVALUE(x,S_SYS_BOOT_MODE)
243 #define G_SYS_BOOT_MODE(x) _SB_GETVALUE(x,S_SYS_BOOT_MODE,M_SYS_BOOT_MODE)
244 #define K_SYS_BOOT_MODE_ROM32 0
245 #define K_SYS_BOOT_MODE_ROM8 1
246 #define K_SYS_BOOT_MODE_SMBUS_SMALL 2
247 #define K_SYS_BOOT_MODE_SMBUS_BIG 3
249 #define M_SYS_PCI_HOST _SB_MAKEMASK1(19)
250 #define M_SYS_PCI_ARBITER _SB_MAKEMASK1(20)
251 #define M_SYS_SOUTH_ON_LDT _SB_MAKEMASK1(21)
252 #define M_SYS_BIG_ENDIAN _SB_MAKEMASK1(22)
253 #define M_SYS_GENCLK_EN _SB_MAKEMASK1(23)
254 #define M_SYS_LDT_TEST_EN _SB_MAKEMASK1(24)
255 #define M_SYS_GEN_PARITY_EN _SB_MAKEMASK1(25)
257 #define S_SYS_CONFIG 26
258 #define M_SYS_CONFIG _SB_MAKEMASK(6,S_SYS_CONFIG)
259 #define V_SYS_CONFIG(x) _SB_MAKEVALUE(x,S_SYS_CONFIG)
260 #define G_SYS_CONFIG(x) _SB_GETVALUE(x,S_SYS_CONFIG,M_SYS_CONFIG)
262 /* The following bits are writeable by JTAG only. */
264 #define M_SYS_CLKSTOP _SB_MAKEMASK1(32)
265 #define M_SYS_CLKSTEP _SB_MAKEMASK1(33)
267 #define S_SYS_CLKCOUNT 34
268 #define M_SYS_CLKCOUNT _SB_MAKEMASK(8,S_SYS_CLKCOUNT)
269 #define V_SYS_CLKCOUNT(x) _SB_MAKEVALUE(x,S_SYS_CLKCOUNT)
270 #define G_SYS_CLKCOUNT(x) _SB_GETVALUE(x,S_SYS_CLKCOUNT,M_SYS_CLKCOUNT)
272 #define M_SYS_PLL_BYPASS _SB_MAKEMASK1(42)
274 #define S_SYS_PLL_IREF 43
275 #define M_SYS_PLL_IREF _SB_MAKEMASK(2,S_SYS_PLL_IREF)
277 #define S_SYS_PLL_VCO 45
278 #define M_SYS_PLL_VCO _SB_MAKEMASK(2,S_SYS_PLL_VCO)
280 #define S_SYS_PLL_VREG 47
281 #define M_SYS_PLL_VREG _SB_MAKEMASK(2,S_SYS_PLL_VREG)
283 #define M_SYS_MEM_RESET _SB_MAKEMASK1(49)
284 #define M_SYS_L2C_RESET _SB_MAKEMASK1(50)
285 #define M_SYS_IO_RESET_0 _SB_MAKEMASK1(51)
286 #define M_SYS_IO_RESET_1 _SB_MAKEMASK1(52)
287 #define M_SYS_SCD_RESET _SB_MAKEMASK1(53)
289 /* End of bits writable by JTAG only. */
291 #define M_SYS_CPU_RESET_0 _SB_MAKEMASK1(54)
292 #define M_SYS_CPU_RESET_1 _SB_MAKEMASK1(55)
294 #define M_SYS_UNICPU0 _SB_MAKEMASK1(56)
295 #define M_SYS_UNICPU1 _SB_MAKEMASK1(57)
297 #define M_SYS_SB_SOFTRES _SB_MAKEMASK1(58)
298 #define M_SYS_EXT_RESET _SB_MAKEMASK1(59)
299 #define M_SYS_SYSTEM_RESET _SB_MAKEMASK1(60)
301 #define M_SYS_MISR_MODE _SB_MAKEMASK1(61)
302 #define M_SYS_MISR_RESET _SB_MAKEMASK1(62)
304 #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1)
305 #define M_SYS_SW_FLAG _SB_MAKEMASK1(63)
306 #endif /* 1250 PASS2 || 112x PASS1 */
312 * Mailbox Registers (Table 4-3)
313 * Registers: SCD_MBOX_CPU_x
316 #define S_MBOX_INT_3 0
317 #define M_MBOX_INT_3 _SB_MAKEMASK(16,S_MBOX_INT_3)
318 #define S_MBOX_INT_2 16
319 #define M_MBOX_INT_2 _SB_MAKEMASK(16,S_MBOX_INT_2)
320 #define S_MBOX_INT_1 32
321 #define M_MBOX_INT_1 _SB_MAKEMASK(16,S_MBOX_INT_1)
322 #define S_MBOX_INT_0 48
323 #define M_MBOX_INT_0 _SB_MAKEMASK(16,S_MBOX_INT_0)
326 * Watchdog Registers (Table 4-8) (Table 4-9) (Table 4-10)
327 * Registers: SCD_WDOG_INIT_CNT_x
330 #define V_SCD_WDOG_FREQ 1000000
332 #define S_SCD_WDOG_INIT 0
333 #define M_SCD_WDOG_INIT _SB_MAKEMASK(23,S_SCD_WDOG_INIT)
335 #define S_SCD_WDOG_CNT 0
336 #define M_SCD_WDOG_CNT _SB_MAKEMASK(23,S_SCD_WDOG_CNT)
338 #define S_SCD_WDOG_ENABLE 0
339 #define M_SCD_WDOG_ENABLE _SB_MAKEMASK1(S_SCD_WDOG_ENABLE)
341 #define S_SCD_WDOG_RESET_TYPE 2
342 #define M_SCD_WDOG_RESET_TYPE _SB_MAKEMASK(3,S_SCD_WDOG_RESET_TYPE)
343 #define V_SCD_WDOG_RESET_TYPE(x) _SB_MAKEVALUE(x,S_SCD_WDOG_RESET_TYPE)
344 #define G_SCD_WDOG_RESET_TYPE(x) _SB_GETVALUE(x,S_SCD_WDOG_RESET_TYPE,M_SCD_WDOG_RESET_TYPE)
346 #define K_SCD_WDOG_RESET_FULL 0 /* actually, (x & 1) == 0 */
347 #define K_SCD_WDOG_RESET_SOFT 1
348 #define K_SCD_WDOG_RESET_CPU0 3
349 #define K_SCD_WDOG_RESET_CPU1 5
350 #define K_SCD_WDOG_RESET_BOTH_CPUS 7
352 /* This feature is present in 1250 C0 and later, but *not* in 112x A revs. */
353 #if SIBYTE_HDR_FEATURE(1250, PASS3)
354 #define S_SCD_WDOG_HAS_RESET 8
355 #define M_SCD_WDOG_HAS_RESET _SB_MAKEMASK1(S_SCD_WDOG_HAS_RESET)
360 * Timer Registers (Table 4-11) (Table 4-12) (Table 4-13)
363 #define V_SCD_TIMER_FREQ 1000000
365 #define S_SCD_TIMER_INIT 0
366 #define M_SCD_TIMER_INIT _SB_MAKEMASK(20,S_SCD_TIMER_INIT)
367 #define V_SCD_TIMER_INIT(x) _SB_MAKEVALUE(x,S_SCD_TIMER_INIT)
368 #define G_SCD_TIMER_INIT(x) _SB_GETVALUE(x,S_SCD_TIMER_INIT,M_SCD_TIMER_INIT)
370 #define S_SCD_TIMER_CNT 0
371 #define M_SCD_TIMER_CNT _SB_MAKEMASK(20,S_SCD_TIMER_CNT)
372 #define V_SCD_TIMER_CNT(x) _SB_MAKEVALUE(x,S_SCD_TIMER_CNT)
373 #define G_SCD_TIMER_CNT(x) _SB_GETVALUE(x,S_SCD_TIMER_CNT,M_SCD_TIMER_CNT)
375 #define M_SCD_TIMER_ENABLE _SB_MAKEMASK1(0)
376 #define M_SCD_TIMER_MODE _SB_MAKEMASK1(1)
377 #define M_SCD_TIMER_MODE_CONTINUOUS M_SCD_TIMER_MODE
380 * System Performance Counters
383 #if SIBYTE_HDR_FEATURE_1250_112x
384 #define S_SPC_CFG_SRC0 0
385 #define M_SPC_CFG_SRC0 _SB_MAKEMASK(8,S_SPC_CFG_SRC0)
386 #define V_SPC_CFG_SRC0(x) _SB_MAKEVALUE(x,S_SPC_CFG_SRC0)
387 #define G_SPC_CFG_SRC0(x) _SB_GETVALUE(x,S_SPC_CFG_SRC0,M_SPC_CFG_SRC0)
389 #define S_SPC_CFG_SRC1 8
390 #define M_SPC_CFG_SRC1 _SB_MAKEMASK(8,S_SPC_CFG_SRC1)
391 #define V_SPC_CFG_SRC1(x) _SB_MAKEVALUE(x,S_SPC_CFG_SRC1)
392 #define G_SPC_CFG_SRC1(x) _SB_GETVALUE(x,S_SPC_CFG_SRC1,M_SPC_CFG_SRC1)
394 #define S_SPC_CFG_SRC2 16
395 #define M_SPC_CFG_SRC2 _SB_MAKEMASK(8,S_SPC_CFG_SRC2)
396 #define V_SPC_CFG_SRC2(x) _SB_MAKEVALUE(x,S_SPC_CFG_SRC2)
397 #define G_SPC_CFG_SRC2(x) _SB_GETVALUE(x,S_SPC_CFG_SRC2,M_SPC_CFG_SRC2)
399 #define S_SPC_CFG_SRC3 24
400 #define M_SPC_CFG_SRC3 _SB_MAKEMASK(8,S_SPC_CFG_SRC3)
401 #define V_SPC_CFG_SRC3(x) _SB_MAKEVALUE(x,S_SPC_CFG_SRC3)
402 #define G_SPC_CFG_SRC3(x) _SB_GETVALUE(x,S_SPC_CFG_SRC3,M_SPC_CFG_SRC3)
404 #define M_SPC_CFG_CLEAR _SB_MAKEMASK1(32)
405 #define M_SPC_CFG_ENABLE _SB_MAKEMASK1(33)
413 #define S_SCD_BERR_TID 8
414 #define M_SCD_BERR_TID _SB_MAKEMASK(10,S_SCD_BERR_TID)
415 #define V_SCD_BERR_TID(x) _SB_MAKEVALUE(x,S_SCD_BERR_TID)
416 #define G_SCD_BERR_TID(x) _SB_GETVALUE(x,S_SCD_BERR_TID,M_SCD_BERR_TID)
418 #define S_SCD_BERR_RID 18
419 #define M_SCD_BERR_RID _SB_MAKEMASK(4,S_SCD_BERR_RID)
420 #define V_SCD_BERR_RID(x) _SB_MAKEVALUE(x,S_SCD_BERR_RID)
421 #define G_SCD_BERR_RID(x) _SB_GETVALUE(x,S_SCD_BERR_RID,M_SCD_BERR_RID)
423 #define S_SCD_BERR_DCODE 22
424 #define M_SCD_BERR_DCODE _SB_MAKEMASK(3,S_SCD_BERR_DCODE)
425 #define V_SCD_BERR_DCODE(x) _SB_MAKEVALUE(x,S_SCD_BERR_DCODE)
426 #define G_SCD_BERR_DCODE(x) _SB_GETVALUE(x,S_SCD_BERR_DCODE,M_SCD_BERR_DCODE)
428 #define M_SCD_BERR_MULTERRS _SB_MAKEMASK1(30)
431 #define S_SCD_L2ECC_CORR_D 0
432 #define M_SCD_L2ECC_CORR_D _SB_MAKEMASK(8,S_SCD_L2ECC_CORR_D)
433 #define V_SCD_L2ECC_CORR_D(x) _SB_MAKEVALUE(x,S_SCD_L2ECC_CORR_D)
434 #define G_SCD_L2ECC_CORR_D(x) _SB_GETVALUE(x,S_SCD_L2ECC_CORR_D,M_SCD_L2ECC_CORR_D)
436 #define S_SCD_L2ECC_BAD_D 8
437 #define M_SCD_L2ECC_BAD_D _SB_MAKEMASK(8,S_SCD_L2ECC_BAD_D)
438 #define V_SCD_L2ECC_BAD_D(x) _SB_MAKEVALUE(x,S_SCD_L2ECC_BAD_D)
439 #define G_SCD_L2ECC_BAD_D(x) _SB_GETVALUE(x,S_SCD_L2ECC_BAD_D,M_SCD_L2ECC_BAD_D)
441 #define S_SCD_L2ECC_CORR_T 16
442 #define M_SCD_L2ECC_CORR_T _SB_MAKEMASK(8,S_SCD_L2ECC_CORR_T)
443 #define V_SCD_L2ECC_CORR_T(x) _SB_MAKEVALUE(x,S_SCD_L2ECC_CORR_T)
444 #define G_SCD_L2ECC_CORR_T(x) _SB_GETVALUE(x,S_SCD_L2ECC_CORR_T,M_SCD_L2ECC_CORR_T)
446 #define S_SCD_L2ECC_BAD_T 24
447 #define M_SCD_L2ECC_BAD_T _SB_MAKEMASK(8,S_SCD_L2ECC_BAD_T)
448 #define V_SCD_L2ECC_BAD_T(x) _SB_MAKEVALUE(x,S_SCD_L2ECC_BAD_T)
449 #define G_SCD_L2ECC_BAD_T(x) _SB_GETVALUE(x,S_SCD_L2ECC_BAD_T,M_SCD_L2ECC_BAD_T)
451 #define S_SCD_MEM_ECC_CORR 0
452 #define M_SCD_MEM_ECC_CORR _SB_MAKEMASK(8,S_SCD_MEM_ECC_CORR)
453 #define V_SCD_MEM_ECC_CORR(x) _SB_MAKEVALUE(x,S_SCD_MEM_ECC_CORR)
454 #define G_SCD_MEM_ECC_CORR(x) _SB_GETVALUE(x,S_SCD_MEM_ECC_CORR,M_SCD_MEM_ECC_CORR)
456 #define S_SCD_MEM_ECC_BAD 8
457 #define M_SCD_MEM_ECC_BAD _SB_MAKEMASK(8,S_SCD_MEM_ECC_BAD)
458 #define V_SCD_MEM_ECC_BAD(x) _SB_MAKEVALUE(x,S_SCD_MEM_ECC_BAD)
459 #define G_SCD_MEM_ECC_BAD(x) _SB_GETVALUE(x,S_SCD_MEM_ECC_BAD,M_SCD_MEM_ECC_BAD)
461 #define S_SCD_MEM_BUSERR 16
462 #define M_SCD_MEM_BUSERR _SB_MAKEMASK(8,S_SCD_MEM_BUSERR)
463 #define V_SCD_MEM_BUSERR(x) _SB_MAKEVALUE(x,S_SCD_MEM_BUSERR)
464 #define G_SCD_MEM_BUSERR(x) _SB_GETVALUE(x,S_SCD_MEM_BUSERR,M_SCD_MEM_BUSERR)
468 * Address Trap Registers
471 #if SIBYTE_HDR_FEATURE_1250_112x
472 #define M_ATRAP_INDEX _SB_MAKEMASK(4,0)
473 #define M_ATRAP_ADDRESS _SB_MAKEMASK(40,0)
475 #define S_ATRAP_CFG_CNT 0
476 #define M_ATRAP_CFG_CNT _SB_MAKEMASK(3,S_ATRAP_CFG_CNT)
477 #define V_ATRAP_CFG_CNT(x) _SB_MAKEVALUE(x,S_ATRAP_CFG_CNT)
478 #define G_ATRAP_CFG_CNT(x) _SB_GETVALUE(x,S_ATRAP_CFG_CNT,M_ATRAP_CFG_CNT)
480 #define M_ATRAP_CFG_WRITE _SB_MAKEMASK1(3)
481 #define M_ATRAP_CFG_ALL _SB_MAKEMASK1(4)
482 #define M_ATRAP_CFG_INV _SB_MAKEMASK1(5)
483 #define M_ATRAP_CFG_USESRC _SB_MAKEMASK1(6)
484 #define M_ATRAP_CFG_SRCINV _SB_MAKEMASK1(7)
486 #define S_ATRAP_CFG_AGENTID 8
487 #define M_ATRAP_CFG_AGENTID _SB_MAKEMASK(4,S_ATRAP_CFG_AGENTID)
488 #define V_ATRAP_CFG_AGENTID(x) _SB_MAKEVALUE(x,S_ATRAP_CFG_AGENTID)
489 #define G_ATRAP_CFG_AGENTID(x) _SB_GETVALUE(x,S_ATRAP_CFG_AGENTID,M_ATRAP_CFG_AGENTID)
491 #define K_BUS_AGENT_CPU0 0
492 #define K_BUS_AGENT_CPU1 1
493 #define K_BUS_AGENT_IOB0 2
494 #define K_BUS_AGENT_IOB1 3
495 #define K_BUS_AGENT_SCD 4
496 #define K_BUS_AGENT_L2C 6
497 #define K_BUS_AGENT_MC 7
499 #define S_ATRAP_CFG_CATTR 12
500 #define M_ATRAP_CFG_CATTR _SB_MAKEMASK(3,S_ATRAP_CFG_CATTR)
501 #define V_ATRAP_CFG_CATTR(x) _SB_MAKEVALUE(x,S_ATRAP_CFG_CATTR)
502 #define G_ATRAP_CFG_CATTR(x) _SB_GETVALUE(x,S_ATRAP_CFG_CATTR,M_ATRAP_CFG_CATTR)
504 #define K_ATRAP_CFG_CATTR_IGNORE 0
505 #define K_ATRAP_CFG_CATTR_UNC 1
506 #define K_ATRAP_CFG_CATTR_CACHEABLE 2
507 #define K_ATRAP_CFG_CATTR_NONCOH 3
508 #define K_ATRAP_CFG_CATTR_COHERENT 4
509 #define K_ATRAP_CFG_CATTR_NOTUNC 5
510 #define K_ATRAP_CFG_CATTR_NOTNONCOH 6
511 #define K_ATRAP_CFG_CATTR_NOTCOHERENT 7
513 #endif /* 1250/112x */
516 * Trace Buffer Config register
519 #if SIBYTE_HDR_FEATURE_1250_112x
521 #define M_SCD_TRACE_CFG_RESET _SB_MAKEMASK1(0)
522 #define M_SCD_TRACE_CFG_START_READ _SB_MAKEMASK1(1)
523 #define M_SCD_TRACE_CFG_START _SB_MAKEMASK1(2)
524 #define M_SCD_TRACE_CFG_STOP _SB_MAKEMASK1(3)
525 #define M_SCD_TRACE_CFG_FREEZE _SB_MAKEMASK1(4)
526 #define M_SCD_TRACE_CFG_FREEZE_FULL _SB_MAKEMASK1(5)
527 #define M_SCD_TRACE_CFG_DEBUG_FULL _SB_MAKEMASK1(6)
528 #define M_SCD_TRACE_CFG_FULL _SB_MAKEMASK1(7)
529 #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1)
530 #define M_SCD_TRACE_CFG_FORCECNT _SB_MAKEMASK1(8)
531 #endif /* 1250 PASS2 || 112x PASS1 */
533 #define S_SCD_TRACE_CFG_CUR_ADDR 10
534 #define M_SCD_TRACE_CFG_CUR_ADDR _SB_MAKEMASK(8,S_SCD_TRACE_CFG_CUR_ADDR)
535 #define V_SCD_TRACE_CFG_CUR_ADDR(x) _SB_MAKEVALUE(x,S_SCD_TRACE_CFG_CUR_ADDR)
536 #define G_SCD_TRACE_CFG_CUR_ADDR(x) _SB_GETVALUE(x,S_SCD_TRACE_CFG_CUR_ADDR,M_SCD_TRACE_CFG_CUR_ADDR)
538 #endif /* 1250/112x */
541 * Trace Event registers
544 #define S_SCD_TREVT_ADDR_MATCH 0
545 #define M_SCD_TREVT_ADDR_MATCH _SB_MAKEMASK(4,S_SCD_TREVT_ADDR_MATCH)
546 #define V_SCD_TREVT_ADDR_MATCH(x) _SB_MAKEVALUE(x,S_SCD_TREVT_ADDR_MATCH)
547 #define G_SCD_TREVT_ADDR_MATCH(x) _SB_GETVALUE(x,S_SCD_TREVT_ADDR_MATCH,M_SCD_TREVT_ADDR_MATCH)
549 #define M_SCD_TREVT_REQID_MATCH _SB_MAKEMASK1(4)
550 #define M_SCD_TREVT_DATAID_MATCH _SB_MAKEMASK1(5)
551 #define M_SCD_TREVT_RESPID_MATCH _SB_MAKEMASK1(6)
552 #define M_SCD_TREVT_INTERRUPT _SB_MAKEMASK1(7)
553 #define M_SCD_TREVT_DEBUG_PIN _SB_MAKEMASK1(9)
554 #define M_SCD_TREVT_WRITE _SB_MAKEMASK1(10)
555 #define M_SCD_TREVT_READ _SB_MAKEMASK1(11)
557 #define S_SCD_TREVT_REQID 12
558 #define M_SCD_TREVT_REQID _SB_MAKEMASK(4,S_SCD_TREVT_REQID)
559 #define V_SCD_TREVT_REQID(x) _SB_MAKEVALUE(x,S_SCD_TREVT_REQID)
560 #define G_SCD_TREVT_REQID(x) _SB_GETVALUE(x,S_SCD_TREVT_REQID,M_SCD_TREVT_REQID)
562 #define S_SCD_TREVT_RESPID 16
563 #define M_SCD_TREVT_RESPID _SB_MAKEMASK(4,S_SCD_TREVT_RESPID)
564 #define V_SCD_TREVT_RESPID(x) _SB_MAKEVALUE(x,S_SCD_TREVT_RESPID)
565 #define G_SCD_TREVT_RESPID(x) _SB_GETVALUE(x,S_SCD_TREVT_RESPID,M_SCD_TREVT_RESPID)
567 #define S_SCD_TREVT_DATAID 20
568 #define M_SCD_TREVT_DATAID _SB_MAKEMASK(4,S_SCD_TREVT_DATAID)
569 #define V_SCD_TREVT_DATAID(x) _SB_MAKEVALUE(x,S_SCD_TREVT_DATAID)
570 #define G_SCD_TREVT_DATAID(x) _SB_GETVALUE(x,S_SCD_TREVT_DATAID,M_SCD_TREVT_DATID)
572 #define S_SCD_TREVT_COUNT 24
573 #define M_SCD_TREVT_COUNT _SB_MAKEMASK(8,S_SCD_TREVT_COUNT)
574 #define V_SCD_TREVT_COUNT(x) _SB_MAKEVALUE(x,S_SCD_TREVT_COUNT)
575 #define G_SCD_TREVT_COUNT(x) _SB_GETVALUE(x,S_SCD_TREVT_COUNT,M_SCD_TREVT_COUNT)
578 * Trace Sequence registers
581 #define S_SCD_TRSEQ_EVENT4 0
582 #define M_SCD_TRSEQ_EVENT4 _SB_MAKEMASK(4,S_SCD_TRSEQ_EVENT4)
583 #define V_SCD_TRSEQ_EVENT4(x) _SB_MAKEVALUE(x,S_SCD_TRSEQ_EVENT4)
584 #define G_SCD_TRSEQ_EVENT4(x) _SB_GETVALUE(x,S_SCD_TRSEQ_EVENT4,M_SCD_TRSEQ_EVENT4)
586 #define S_SCD_TRSEQ_EVENT3 4
587 #define M_SCD_TRSEQ_EVENT3 _SB_MAKEMASK(4,S_SCD_TRSEQ_EVENT3)
588 #define V_SCD_TRSEQ_EVENT3(x) _SB_MAKEVALUE(x,S_SCD_TRSEQ_EVENT3)
589 #define G_SCD_TRSEQ_EVENT3(x) _SB_GETVALUE(x,S_SCD_TRSEQ_EVENT3,M_SCD_TRSEQ_EVENT3)
591 #define S_SCD_TRSEQ_EVENT2 8
592 #define M_SCD_TRSEQ_EVENT2 _SB_MAKEMASK(4,S_SCD_TRSEQ_EVENT2)
593 #define V_SCD_TRSEQ_EVENT2(x) _SB_MAKEVALUE(x,S_SCD_TRSEQ_EVENT2)
594 #define G_SCD_TRSEQ_EVENT2(x) _SB_GETVALUE(x,S_SCD_TRSEQ_EVENT2,M_SCD_TRSEQ_EVENT2)
596 #define S_SCD_TRSEQ_EVENT1 12
597 #define M_SCD_TRSEQ_EVENT1 _SB_MAKEMASK(4,S_SCD_TRSEQ_EVENT1)
598 #define V_SCD_TRSEQ_EVENT1(x) _SB_MAKEVALUE(x,S_SCD_TRSEQ_EVENT1)
599 #define G_SCD_TRSEQ_EVENT1(x) _SB_GETVALUE(x,S_SCD_TRSEQ_EVENT1,M_SCD_TRSEQ_EVENT1)
601 #define K_SCD_TRSEQ_E0 0
602 #define K_SCD_TRSEQ_E1 1
603 #define K_SCD_TRSEQ_E2 2
604 #define K_SCD_TRSEQ_E3 3
605 #define K_SCD_TRSEQ_E0_E1 4
606 #define K_SCD_TRSEQ_E1_E2 5
607 #define K_SCD_TRSEQ_E2_E3 6
608 #define K_SCD_TRSEQ_E0_E1_E2 7
609 #define K_SCD_TRSEQ_E0_E1_E2_E3 8
610 #define K_SCD_TRSEQ_E0E1 9
611 #define K_SCD_TRSEQ_E0E1E2 10
612 #define K_SCD_TRSEQ_E0E1E2E3 11
613 #define K_SCD_TRSEQ_E0E1_E2 12
614 #define K_SCD_TRSEQ_E0E1_E2E3 13
615 #define K_SCD_TRSEQ_E0E1_E2_E3 14
616 #define K_SCD_TRSEQ_IGNORED 15
618 #define K_SCD_TRSEQ_TRIGGER_ALL (V_SCD_TRSEQ_EVENT1(K_SCD_TRSEQ_IGNORED) | \
619 V_SCD_TRSEQ_EVENT2(K_SCD_TRSEQ_IGNORED) | \
620 V_SCD_TRSEQ_EVENT3(K_SCD_TRSEQ_IGNORED) | \
621 V_SCD_TRSEQ_EVENT4(K_SCD_TRSEQ_IGNORED))
623 #define S_SCD_TRSEQ_FUNCTION 16
624 #define M_SCD_TRSEQ_FUNCTION _SB_MAKEMASK(4,S_SCD_TRSEQ_FUNCTION)
625 #define V_SCD_TRSEQ_FUNCTION(x) _SB_MAKEVALUE(x,S_SCD_TRSEQ_FUNCTION)
626 #define G_SCD_TRSEQ_FUNCTION(x) _SB_GETVALUE(x,S_SCD_TRSEQ_FUNCTION,M_SCD_TRSEQ_FUNCTION)
628 #define K_SCD_TRSEQ_FUNC_NOP 0
629 #define K_SCD_TRSEQ_FUNC_START 1
630 #define K_SCD_TRSEQ_FUNC_STOP 2
631 #define K_SCD_TRSEQ_FUNC_FREEZE 3
633 #define V_SCD_TRSEQ_FUNC_NOP V_SCD_TRSEQ_FUNCTION(K_SCD_TRSEQ_FUNC_NOP)
634 #define V_SCD_TRSEQ_FUNC_START V_SCD_TRSEQ_FUNCTION(K_SCD_TRSEQ_FUNC_START)
635 #define V_SCD_TRSEQ_FUNC_STOP V_SCD_TRSEQ_FUNCTION(K_SCD_TRSEQ_FUNC_STOP)
636 #define V_SCD_TRSEQ_FUNC_FREEZE V_SCD_TRSEQ_FUNCTION(K_SCD_TRSEQ_FUNC_FREEZE)
638 #define M_SCD_TRSEQ_ASAMPLE _SB_MAKEMASK1(18)
639 #define M_SCD_TRSEQ_DSAMPLE _SB_MAKEMASK1(19)
640 #define M_SCD_TRSEQ_DEBUGPIN _SB_MAKEMASK1(20)
641 #define M_SCD_TRSEQ_DEBUGCPU _SB_MAKEMASK1(21)
642 #define M_SCD_TRSEQ_CLEARUSE _SB_MAKEMASK1(22)
643 #define M_SCD_TRSEQ_ALLD_A _SB_MAKEMASK1(23)
644 #define M_SCD_TRSEQ_ALL_A _SB_MAKEMASK1(24)