2 * Copyright (C) 1995-1999 Gary Thomas, Paul Mackerras, Cort Dougan.
5 #ifndef _ASM_POWERPC_PPC_ASM_H
6 #define _ASM_POWERPC_PPC_ASM_H
11 * Macros for storing registers into and loading registers from
15 #define SAVE_GPR(n, base) std n,GPR0+8*(n)(base)
16 #define REST_GPR(n, base) ld n,GPR0+8*(n)(base)
17 #define SAVE_NVGPRS(base) SAVE_8GPRS(14, base); SAVE_10GPRS(22, base)
18 #define REST_NVGPRS(base) REST_8GPRS(14, base); REST_10GPRS(22, base)
20 #define SAVE_GPR(n, base) stw n,GPR0+4*(n)(base)
21 #define REST_GPR(n, base) lwz n,GPR0+4*(n)(base)
22 #define SAVE_NVGPRS(base) SAVE_GPR(13, base); SAVE_8GPRS(14, base); \
24 #define REST_NVGPRS(base) REST_GPR(13, base); REST_8GPRS(14, base); \
29 #define SAVE_2GPRS(n, base) SAVE_GPR(n, base); SAVE_GPR(n+1, base)
30 #define SAVE_4GPRS(n, base) SAVE_2GPRS(n, base); SAVE_2GPRS(n+2, base)
31 #define SAVE_8GPRS(n, base) SAVE_4GPRS(n, base); SAVE_4GPRS(n+4, base)
32 #define SAVE_10GPRS(n, base) SAVE_8GPRS(n, base); SAVE_2GPRS(n+8, base)
33 #define REST_2GPRS(n, base) REST_GPR(n, base); REST_GPR(n+1, base)
34 #define REST_4GPRS(n, base) REST_2GPRS(n, base); REST_2GPRS(n+2, base)
35 #define REST_8GPRS(n, base) REST_4GPRS(n, base); REST_4GPRS(n+4, base)
36 #define REST_10GPRS(n, base) REST_8GPRS(n, base); REST_2GPRS(n+8, base)
38 #define SAVE_FPR(n, base) stfd n,THREAD_FPR0+8*(n)(base)
39 #define SAVE_2FPRS(n, base) SAVE_FPR(n, base); SAVE_FPR(n+1, base)
40 #define SAVE_4FPRS(n, base) SAVE_2FPRS(n, base); SAVE_2FPRS(n+2, base)
41 #define SAVE_8FPRS(n, base) SAVE_4FPRS(n, base); SAVE_4FPRS(n+4, base)
42 #define SAVE_16FPRS(n, base) SAVE_8FPRS(n, base); SAVE_8FPRS(n+8, base)
43 #define SAVE_32FPRS(n, base) SAVE_16FPRS(n, base); SAVE_16FPRS(n+16, base)
44 #define REST_FPR(n, base) lfd n,THREAD_FPR0+8*(n)(base)
45 #define REST_2FPRS(n, base) REST_FPR(n, base); REST_FPR(n+1, base)
46 #define REST_4FPRS(n, base) REST_2FPRS(n, base); REST_2FPRS(n+2, base)
47 #define REST_8FPRS(n, base) REST_4FPRS(n, base); REST_4FPRS(n+4, base)
48 #define REST_16FPRS(n, base) REST_8FPRS(n, base); REST_8FPRS(n+8, base)
49 #define REST_32FPRS(n, base) REST_16FPRS(n, base); REST_16FPRS(n+16, base)
51 #define SAVE_VR(n,b,base) li b,THREAD_VR0+(16*(n)); stvx n,b,base
52 #define SAVE_2VRS(n,b,base) SAVE_VR(n,b,base); SAVE_VR(n+1,b,base)
53 #define SAVE_4VRS(n,b,base) SAVE_2VRS(n,b,base); SAVE_2VRS(n+2,b,base)
54 #define SAVE_8VRS(n,b,base) SAVE_4VRS(n,b,base); SAVE_4VRS(n+4,b,base)
55 #define SAVE_16VRS(n,b,base) SAVE_8VRS(n,b,base); SAVE_8VRS(n+8,b,base)
56 #define SAVE_32VRS(n,b,base) SAVE_16VRS(n,b,base); SAVE_16VRS(n+16,b,base)
57 #define REST_VR(n,b,base) li b,THREAD_VR0+(16*(n)); lvx n,b,base
58 #define REST_2VRS(n,b,base) REST_VR(n,b,base); REST_VR(n+1,b,base)
59 #define REST_4VRS(n,b,base) REST_2VRS(n,b,base); REST_2VRS(n+2,b,base)
60 #define REST_8VRS(n,b,base) REST_4VRS(n,b,base); REST_4VRS(n+4,b,base)
61 #define REST_16VRS(n,b,base) REST_8VRS(n,b,base); REST_8VRS(n+8,b,base)
62 #define REST_32VRS(n,b,base) REST_16VRS(n,b,base); REST_16VRS(n+16,b,base)
64 #define SAVE_EVR(n,s,base) evmergehi s,s,n; stw s,THREAD_EVR0+4*(n)(base)
65 #define SAVE_2EVRS(n,s,base) SAVE_EVR(n,s,base); SAVE_EVR(n+1,s,base)
66 #define SAVE_4EVRS(n,s,base) SAVE_2EVRS(n,s,base); SAVE_2EVRS(n+2,s,base)
67 #define SAVE_8EVRS(n,s,base) SAVE_4EVRS(n,s,base); SAVE_4EVRS(n+4,s,base)
68 #define SAVE_16EVRS(n,s,base) SAVE_8EVRS(n,s,base); SAVE_8EVRS(n+8,s,base)
69 #define SAVE_32EVRS(n,s,base) SAVE_16EVRS(n,s,base); SAVE_16EVRS(n+16,s,base)
70 #define REST_EVR(n,s,base) lwz s,THREAD_EVR0+4*(n)(base); evmergelo n,s,n
71 #define REST_2EVRS(n,s,base) REST_EVR(n,s,base); REST_EVR(n+1,s,base)
72 #define REST_4EVRS(n,s,base) REST_2EVRS(n,s,base); REST_2EVRS(n+2,s,base)
73 #define REST_8EVRS(n,s,base) REST_4EVRS(n,s,base); REST_4EVRS(n+4,s,base)
74 #define REST_16EVRS(n,s,base) REST_8EVRS(n,s,base); REST_8EVRS(n+8,s,base)
75 #define REST_32EVRS(n,s,base) REST_16EVRS(n,s,base); REST_16EVRS(n+16,s,base)
77 /* Macros to adjust thread priority for Iseries hardware multithreading */
78 #define HMT_LOW or 1,1,1
79 #define HMT_MEDIUM or 2,2,2
80 #define HMT_HIGH or 3,3,3
82 /* handle instructions that older assemblers may not know */
83 #define RFCI .long 0x4c000066 /* rfci instruction */
84 #define RFDI .long 0x4c00004e /* rfdi instruction */
85 #define RFMCI .long 0x4c00004c /* rfmci instruction */
88 * LOADADDR( rn, name )
89 * loads the address of 'name' into 'rn'
91 * LOADBASE( rn, name )
92 * loads the address (less the low 16 bits) of 'name' into 'rn'
93 * suitable for base+disp addressing
96 #define LOADADDR(rn,name) \
97 lis rn,name##@highest; \
98 ori rn,rn,name##@higher; \
100 oris rn,rn,name##@h; \
103 #define LOADBASE(rn,name) \
104 lis rn,name@highest; \
105 ori rn,rn,name@higher; \
106 rldicr rn,rn,32,31; \
110 #define SET_REG_TO_CONST(reg, value) \
111 lis reg,(((value)>>48)&0xFFFF); \
112 ori reg,reg,(((value)>>32)&0xFFFF); \
113 rldicr reg,reg,32,31; \
114 oris reg,reg,(((value)>>16)&0xFFFF); \
115 ori reg,reg,((value)&0xFFFF);
117 #define SET_REG_TO_LABEL(reg, label) \
118 lis reg,(label)@highest; \
119 ori reg,reg,(label)@higher; \
120 rldicr reg,reg,32,31; \
121 oris reg,reg,(label)@h; \
122 ori reg,reg,(label)@l;
125 /* various errata or part fixups */
126 #ifdef CONFIG_PPC601_SYNC_FIX
131 END_FTR_SECTION_IFSET(CPU_FTR_601)
135 END_FTR_SECTION_IFSET(CPU_FTR_601)
139 END_FTR_SECTION_IFSET(CPU_FTR_601)
149 #else /* CONFIG_SMP */
150 /* tlbsync is not implemented on 601 */
155 END_FTR_SECTION_IFCLR(CPU_FTR_601)
160 * This instruction is not implemented on the PPC 603 or 601; however, on
161 * the 403GCX and 405GP tlbia IS defined and tlbie is not.
162 * All of these instructions exist in the 8xx, they have magical powers,
163 * and they must be used.
166 #if !defined(CONFIG_4xx) && !defined(CONFIG_8xx)
170 lis r4,KERNELBASE@h; \
177 #ifdef CONFIG_IBM405_ERR77
178 #define PPC405_ERR77(ra,rb) dcbt ra, rb;
179 #define PPC405_ERR77_SYNC sync;
181 #define PPC405_ERR77(ra,rb)
182 #define PPC405_ERR77_SYNC
186 #ifdef CONFIG_IBM440EP_ERR42
187 #define PPC440EP_ERR42 isync
189 #define PPC440EP_ERR42
193 #if defined(CONFIG_BOOKE)
194 #define tophys(rd,rs) \
197 #define tovirt(rd,rs) \
200 #elif defined(CONFIG_PPC64)
201 /* PPPBBB - DRENG If KERNELBASE is always 0xC0...,
202 * Then we can easily do this with one asm insn. -Peter
204 #define tophys(rd,rs) \
205 lis rd,((KERNELBASE>>48)&0xFFFF); \
206 rldicr rd,rd,32,31; \
209 #define tovirt(rd,rs) \
210 lis rd,((KERNELBASE>>48)&0xFFFF); \
211 rldicr rd,rd,32,31; \
215 * On APUS (Amiga PowerPC cpu upgrade board), we don't know the
216 * physical base address of RAM at compile time.
218 #define tophys(rd,rs) \
219 0: addis rd,rs,-KERNELBASE@h; \
220 .section ".vtop_fixup","aw"; \
225 #define tovirt(rd,rs) \
226 0: addis rd,rs,KERNELBASE@h; \
227 .section ".ptov_fixup","aw"; \
234 * On 64-bit cpus, we use the rfid instruction instead of rfi, but
235 * we then have to make sure we preserve the top 32 bits except for
236 * the 64-bit mode bit, which we clear.
238 #if defined(CONFIG_PPC64BRIDGE)
239 #define FIX_SRR1(ra, rb) \
242 clrldi ra,ra,1; /* turn off 64-bit mode */ \
244 #define RFI .long 0x4c000024 /* rfid instruction */
245 #define MTMSRD(r) .long (0x7c000164 + ((r) << 21)) /* mtmsrd */
246 #define CLR_TOP32(r) rlwinm (r),(r),0,0,31 /* clear top 32 bits */
247 #elif defined(CONFIG_PPC64)
248 /* Insert the high 32 bits of the MSR into what will be the new
249 MSR (via SRR1 and rfid) This preserves the MSR.SF and MSR.ISF
252 #define FIX_SRR1(ra, rb) \
257 #define CLR_TOP32(r) rlwinm (r),(r),0,0,31 /* clear top 32 bits */
260 #define FIX_SRR1(ra, rb)
264 #define RFI rfi; b . /* Prevent prefetch past rfi */
266 #define MTMSRD(r) mtmsr r
270 /* The boring bits... */
272 /* Condition Register Bit Fields */
284 /* General Purpose Registers (GPRs) */
320 /* Floating Point Registers (FPRs) */
355 /* AltiVec Registers (VPRs) */
390 /* SPE Registers (EVPRs) */
425 /* some stab codes */
431 #define ASM_CONST(x) x
433 #define __ASM_CONST(x) x##UL
434 #define ASM_CONST(x) __ASM_CONST(x)
435 #endif /* __ASSEMBLY__ */
437 #endif /* _ASM_POWERPC_PPC_ASM_H */